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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.16 96.89 91.85 97.68 100.00 98.28 97.30 98.14


Total test records in report: 452
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T304 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.930490219 Jun 28 04:32:44 PM PDT 24 Jun 28 04:33:03 PM PDT 24 4476549901 ps
T305 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1389429844 Jun 28 04:33:18 PM PDT 24 Jun 28 04:48:59 PM PDT 24 364115792843 ps
T56 /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1707306379 Jun 28 04:32:57 PM PDT 24 Jun 28 05:00:52 PM PDT 24 40586803792 ps
T306 /workspace/coverage/default/30.rom_ctrl_stress_all.2111042734 Jun 28 04:33:02 PM PDT 24 Jun 28 04:33:17 PM PDT 24 209658804 ps
T307 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2033211905 Jun 28 04:33:09 PM PDT 24 Jun 28 04:33:46 PM PDT 24 4390718052 ps
T308 /workspace/coverage/default/42.rom_ctrl_smoke.913390198 Jun 28 04:33:26 PM PDT 24 Jun 28 04:34:25 PM PDT 24 11005227450 ps
T309 /workspace/coverage/default/10.rom_ctrl_smoke.1113267900 Jun 28 04:33:07 PM PDT 24 Jun 28 04:33:47 PM PDT 24 5377077323 ps
T310 /workspace/coverage/default/1.rom_ctrl_smoke.3136750784 Jun 28 04:32:42 PM PDT 24 Jun 28 04:33:09 PM PDT 24 1380243296 ps
T311 /workspace/coverage/default/15.rom_ctrl_smoke.4191225674 Jun 28 04:32:48 PM PDT 24 Jun 28 04:33:27 PM PDT 24 15214235530 ps
T312 /workspace/coverage/default/35.rom_ctrl_stress_all.2879243023 Jun 28 04:33:34 PM PDT 24 Jun 28 04:34:38 PM PDT 24 6430159004 ps
T313 /workspace/coverage/default/16.rom_ctrl_smoke.3340332774 Jun 28 04:32:52 PM PDT 24 Jun 28 04:33:44 PM PDT 24 19893221729 ps
T314 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3761171452 Jun 28 04:32:59 PM PDT 24 Jun 28 04:47:16 PM PDT 24 87844640856 ps
T315 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.391045852 Jun 28 04:33:23 PM PDT 24 Jun 28 04:33:46 PM PDT 24 5061269282 ps
T316 /workspace/coverage/default/47.rom_ctrl_alert_test.494340654 Jun 28 04:33:18 PM PDT 24 Jun 28 04:33:46 PM PDT 24 6478938322 ps
T317 /workspace/coverage/default/44.rom_ctrl_stress_all.71290659 Jun 28 04:33:14 PM PDT 24 Jun 28 04:33:31 PM PDT 24 420708772 ps
T318 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2017680604 Jun 28 04:33:10 PM PDT 24 Jun 28 04:33:27 PM PDT 24 3370539738 ps
T319 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.200690182 Jun 28 04:33:16 PM PDT 24 Jun 28 04:34:23 PM PDT 24 30879655751 ps
T320 /workspace/coverage/default/17.rom_ctrl_alert_test.1169849259 Jun 28 04:33:05 PM PDT 24 Jun 28 04:33:28 PM PDT 24 2054066682 ps
T321 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3036781292 Jun 28 04:32:55 PM PDT 24 Jun 28 04:48:42 PM PDT 24 402048530705 ps
T322 /workspace/coverage/default/31.rom_ctrl_stress_all.2231764011 Jun 28 04:33:03 PM PDT 24 Jun 28 04:33:57 PM PDT 24 892332552 ps
T323 /workspace/coverage/default/20.rom_ctrl_stress_all.2344585992 Jun 28 04:33:04 PM PDT 24 Jun 28 04:33:50 PM PDT 24 711622060 ps
T324 /workspace/coverage/default/9.rom_ctrl_smoke.2231415871 Jun 28 04:33:01 PM PDT 24 Jun 28 04:33:25 PM PDT 24 360831071 ps
T325 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2187034233 Jun 28 04:32:52 PM PDT 24 Jun 28 04:34:00 PM PDT 24 39358612593 ps
T326 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2329934220 Jun 28 04:33:15 PM PDT 24 Jun 28 04:37:36 PM PDT 24 55669748480 ps
T327 /workspace/coverage/default/24.rom_ctrl_alert_test.574773632 Jun 28 04:33:16 PM PDT 24 Jun 28 04:33:47 PM PDT 24 7059194711 ps
T328 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2289936760 Jun 28 04:33:11 PM PDT 24 Jun 28 04:33:32 PM PDT 24 688679476 ps
T329 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2065546989 Jun 28 04:32:45 PM PDT 24 Jun 28 04:33:05 PM PDT 24 5975968749 ps
T330 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.806514212 Jun 28 04:32:50 PM PDT 24 Jun 28 04:33:28 PM PDT 24 32797432406 ps
T331 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3177576854 Jun 28 04:32:35 PM PDT 24 Jun 28 04:35:37 PM PDT 24 34150682905 ps
T332 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2576024689 Jun 28 04:33:01 PM PDT 24 Jun 28 04:44:48 PM PDT 24 63666385670 ps
T333 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2805806426 Jun 28 04:33:05 PM PDT 24 Jun 28 04:33:42 PM PDT 24 15266081105 ps
T334 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3542406636 Jun 28 04:32:51 PM PDT 24 Jun 28 04:41:02 PM PDT 24 225811232321 ps
T335 /workspace/coverage/default/33.rom_ctrl_smoke.1800503559 Jun 28 04:33:09 PM PDT 24 Jun 28 04:34:23 PM PDT 24 7512804350 ps
T336 /workspace/coverage/default/3.rom_ctrl_stress_all.1170955378 Jun 28 04:32:32 PM PDT 24 Jun 28 04:34:52 PM PDT 24 97046554519 ps
T337 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2812048404 Jun 28 04:33:22 PM PDT 24 Jun 28 04:33:42 PM PDT 24 661706827 ps
T338 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.582265249 Jun 28 04:33:14 PM PDT 24 Jun 28 04:33:51 PM PDT 24 2770759759 ps
T339 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3321414727 Jun 28 04:32:59 PM PDT 24 Jun 28 04:34:05 PM PDT 24 8029957836 ps
T340 /workspace/coverage/default/23.rom_ctrl_stress_all.3099188334 Jun 28 04:32:50 PM PDT 24 Jun 28 04:33:16 PM PDT 24 1492658737 ps
T341 /workspace/coverage/default/7.rom_ctrl_stress_all.1159348179 Jun 28 04:32:39 PM PDT 24 Jun 28 04:34:27 PM PDT 24 51657989494 ps
T342 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3908095083 Jun 28 04:33:27 PM PDT 24 Jun 28 04:38:27 PM PDT 24 92695381226 ps
T343 /workspace/coverage/default/34.rom_ctrl_stress_all.1809501141 Jun 28 04:33:23 PM PDT 24 Jun 28 04:34:18 PM PDT 24 3487075449 ps
T344 /workspace/coverage/default/18.rom_ctrl_smoke.508688819 Jun 28 04:33:13 PM PDT 24 Jun 28 04:33:35 PM PDT 24 4292902340 ps
T345 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.248945947 Jun 28 04:32:47 PM PDT 24 Jun 28 04:33:08 PM PDT 24 674844797 ps
T346 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2545321376 Jun 28 04:32:43 PM PDT 24 Jun 28 04:39:35 PM PDT 24 36529389865 ps
T347 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2518595971 Jun 28 04:33:15 PM PDT 24 Jun 28 04:34:10 PM PDT 24 40690081169 ps
T348 /workspace/coverage/default/2.rom_ctrl_stress_all.3832842506 Jun 28 04:33:11 PM PDT 24 Jun 28 04:34:05 PM PDT 24 5725600093 ps
T349 /workspace/coverage/default/36.rom_ctrl_smoke.3492754205 Jun 28 04:33:17 PM PDT 24 Jun 28 04:33:49 PM PDT 24 6880859969 ps
T350 /workspace/coverage/default/40.rom_ctrl_stress_all.1465979717 Jun 28 04:33:16 PM PDT 24 Jun 28 04:35:38 PM PDT 24 31517491103 ps
T351 /workspace/coverage/default/22.rom_ctrl_stress_all.294282122 Jun 28 04:33:08 PM PDT 24 Jun 28 04:34:37 PM PDT 24 47909899525 ps
T352 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.975870582 Jun 28 04:33:14 PM PDT 24 Jun 28 04:33:41 PM PDT 24 6290761103 ps
T353 /workspace/coverage/default/43.rom_ctrl_stress_all.521588296 Jun 28 04:33:15 PM PDT 24 Jun 28 04:34:25 PM PDT 24 7029243740 ps
T354 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.833553472 Jun 28 04:33:08 PM PDT 24 Jun 28 04:37:24 PM PDT 24 11066045226 ps
T355 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2941354794 Jun 28 04:32:56 PM PDT 24 Jun 28 04:40:43 PM PDT 24 33552055987 ps
T356 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2941680216 Jun 28 04:33:06 PM PDT 24 Jun 28 04:33:31 PM PDT 24 1982320760 ps
T357 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3204701882 Jun 28 04:32:51 PM PDT 24 Jun 28 04:39:25 PM PDT 24 82330371524 ps
T358 /workspace/coverage/default/28.rom_ctrl_stress_all.336347324 Jun 28 04:33:06 PM PDT 24 Jun 28 04:33:43 PM PDT 24 726857634 ps
T359 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2334498147 Jun 28 04:32:55 PM PDT 24 Jun 28 04:33:27 PM PDT 24 4103875101 ps
T360 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3757869749 Jun 28 04:32:24 PM PDT 24 Jun 28 04:32:51 PM PDT 24 10867107960 ps
T64 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3377869110 Jun 28 04:32:27 PM PDT 24 Jun 28 04:33:00 PM PDT 24 3596902603 ps
T65 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.595013250 Jun 28 04:32:28 PM PDT 24 Jun 28 04:32:48 PM PDT 24 1889784787 ps
T66 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1699117508 Jun 28 04:32:35 PM PDT 24 Jun 28 04:35:11 PM PDT 24 17787233826 ps
T57 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.761930765 Jun 28 04:32:23 PM PDT 24 Jun 28 04:35:11 PM PDT 24 2919267185 ps
T98 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2197020115 Jun 28 04:32:20 PM PDT 24 Jun 28 04:33:23 PM PDT 24 4567990899 ps
T58 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4023911466 Jun 28 04:32:34 PM PDT 24 Jun 28 04:32:44 PM PDT 24 359144150 ps
T59 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3532560413 Jun 28 04:32:24 PM PDT 24 Jun 28 04:32:58 PM PDT 24 4169370701 ps
T70 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2683204970 Jun 28 04:32:34 PM PDT 24 Jun 28 04:33:14 PM PDT 24 689949558 ps
T361 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2622991544 Jun 28 04:32:33 PM PDT 24 Jun 28 04:32:57 PM PDT 24 1663634009 ps
T362 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1325356981 Jun 28 04:32:33 PM PDT 24 Jun 28 04:32:56 PM PDT 24 10969409756 ps
T103 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.44011730 Jun 28 04:32:34 PM PDT 24 Jun 28 04:32:55 PM PDT 24 7843758325 ps
T104 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3772050857 Jun 28 04:32:30 PM PDT 24 Jun 28 04:32:42 PM PDT 24 2044844010 ps
T105 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3994645500 Jun 28 04:32:09 PM PDT 24 Jun 28 04:33:42 PM PDT 24 35717335894 ps
T60 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.177226125 Jun 28 04:32:55 PM PDT 24 Jun 28 04:34:37 PM PDT 24 24431576148 ps
T71 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2686611364 Jun 28 04:32:39 PM PDT 24 Jun 28 04:33:13 PM PDT 24 4293237499 ps
T61 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2093248776 Jun 28 04:32:25 PM PDT 24 Jun 28 04:33:03 PM PDT 24 18354520474 ps
T106 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3735820877 Jun 28 04:32:32 PM PDT 24 Jun 28 04:32:56 PM PDT 24 42674513648 ps
T62 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2169532525 Jun 28 04:32:23 PM PDT 24 Jun 28 04:35:20 PM PDT 24 4136050478 ps
T69 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1361824468 Jun 28 04:32:24 PM PDT 24 Jun 28 04:32:33 PM PDT 24 201736437 ps
T363 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3175267861 Jun 28 04:32:27 PM PDT 24 Jun 28 04:32:53 PM PDT 24 4535421934 ps
T364 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.627210694 Jun 28 04:32:39 PM PDT 24 Jun 28 04:32:53 PM PDT 24 436687865 ps
T113 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1450783773 Jun 28 04:32:27 PM PDT 24 Jun 28 04:34:12 PM PDT 24 17343836668 ps
T365 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1711156143 Jun 28 04:32:30 PM PDT 24 Jun 28 04:33:03 PM PDT 24 4223043091 ps
T72 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2148570757 Jun 28 04:32:31 PM PDT 24 Jun 28 04:32:52 PM PDT 24 9262637229 ps
T366 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2602720724 Jun 28 04:32:26 PM PDT 24 Jun 28 04:32:35 PM PDT 24 373240091 ps
T109 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3524382744 Jun 28 04:32:32 PM PDT 24 Jun 28 04:34:07 PM PDT 24 8428044420 ps
T99 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2712981587 Jun 28 04:32:31 PM PDT 24 Jun 28 04:32:45 PM PDT 24 688601355 ps
T73 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2019292701 Jun 28 04:32:32 PM PDT 24 Jun 28 04:32:43 PM PDT 24 765324847 ps
T100 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.592198022 Jun 28 04:32:44 PM PDT 24 Jun 28 04:33:10 PM PDT 24 11220077644 ps
T74 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2922386030 Jun 28 04:32:26 PM PDT 24 Jun 28 04:32:41 PM PDT 24 986558104 ps
T367 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1240528232 Jun 28 04:32:36 PM PDT 24 Jun 28 04:35:25 PM PDT 24 75077074458 ps
T101 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1008136448 Jun 28 04:32:34 PM PDT 24 Jun 28 04:32:45 PM PDT 24 1373099521 ps
T368 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1012163685 Jun 28 04:32:49 PM PDT 24 Jun 28 04:33:02 PM PDT 24 593626610 ps
T369 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.519115670 Jun 28 04:32:24 PM PDT 24 Jun 28 04:32:33 PM PDT 24 719018323 ps
T118 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3078174015 Jun 28 04:32:35 PM PDT 24 Jun 28 04:35:14 PM PDT 24 1796668884 ps
T370 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4038888558 Jun 28 04:32:38 PM PDT 24 Jun 28 04:33:10 PM PDT 24 14059147245 ps
T371 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1254905427 Jun 28 04:32:48 PM PDT 24 Jun 28 04:33:22 PM PDT 24 12107498775 ps
T372 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2729528998 Jun 28 04:32:38 PM PDT 24 Jun 28 04:32:53 PM PDT 24 758884455 ps
T373 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3956074528 Jun 28 04:32:13 PM PDT 24 Jun 28 04:32:45 PM PDT 24 4275360572 ps
T102 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3193915975 Jun 28 04:32:33 PM PDT 24 Jun 28 04:32:56 PM PDT 24 2333119331 ps
T374 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1632960077 Jun 28 04:32:13 PM PDT 24 Jun 28 04:32:37 PM PDT 24 47536521438 ps
T75 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3239595392 Jun 28 04:32:32 PM PDT 24 Jun 28 04:34:26 PM PDT 24 19527902293 ps
T76 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.239345539 Jun 28 04:32:33 PM PDT 24 Jun 28 04:32:50 PM PDT 24 616649585 ps
T375 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1806362865 Jun 28 04:32:47 PM PDT 24 Jun 28 04:33:00 PM PDT 24 687689816 ps
T83 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2106061632 Jun 28 04:32:40 PM PDT 24 Jun 28 04:35:15 PM PDT 24 61307343744 ps
T376 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.731676411 Jun 28 04:32:08 PM PDT 24 Jun 28 04:32:17 PM PDT 24 676962767 ps
T84 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4052835167 Jun 28 04:32:23 PM PDT 24 Jun 28 04:32:35 PM PDT 24 670081998 ps
T377 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.674753300 Jun 28 04:32:44 PM PDT 24 Jun 28 04:32:56 PM PDT 24 815634145 ps
T378 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.4167270843 Jun 28 04:32:27 PM PDT 24 Jun 28 04:32:56 PM PDT 24 3315698544 ps
T85 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2884502072 Jun 28 04:32:28 PM PDT 24 Jun 28 04:32:58 PM PDT 24 15460507851 ps
T379 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.200854164 Jun 28 04:32:30 PM PDT 24 Jun 28 04:32:39 PM PDT 24 171169865 ps
T380 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2133758783 Jun 28 04:32:52 PM PDT 24 Jun 28 04:33:26 PM PDT 24 7832098480 ps
T381 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.662074359 Jun 28 04:32:30 PM PDT 24 Jun 28 04:32:50 PM PDT 24 6983538081 ps
T382 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.4236929652 Jun 28 04:32:35 PM PDT 24 Jun 28 04:32:53 PM PDT 24 5798507924 ps
T383 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.139522183 Jun 28 04:32:12 PM PDT 24 Jun 28 04:32:31 PM PDT 24 1791310584 ps
T86 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2647157647 Jun 28 04:32:26 PM PDT 24 Jun 28 04:32:57 PM PDT 24 3139795579 ps
T384 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1799605127 Jun 28 04:32:32 PM PDT 24 Jun 28 04:33:03 PM PDT 24 4171704272 ps
T87 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.878650070 Jun 28 04:32:41 PM PDT 24 Jun 28 04:34:38 PM PDT 24 13124001467 ps
T89 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2284483349 Jun 28 04:32:38 PM PDT 24 Jun 28 04:33:08 PM PDT 24 3830497511 ps
T116 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.281894587 Jun 28 04:32:42 PM PDT 24 Jun 28 04:34:05 PM PDT 24 907540176 ps
T385 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2217238398 Jun 28 04:32:16 PM PDT 24 Jun 28 04:32:39 PM PDT 24 2292963785 ps
T386 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1981573073 Jun 28 04:32:37 PM PDT 24 Jun 28 04:32:50 PM PDT 24 569596586 ps
T387 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.675956026 Jun 28 04:32:36 PM PDT 24 Jun 28 04:32:57 PM PDT 24 29803102902 ps
T388 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2722237315 Jun 28 04:32:28 PM PDT 24 Jun 28 04:33:57 PM PDT 24 8931956438 ps
T389 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2331287479 Jun 28 04:32:26 PM PDT 24 Jun 28 04:32:46 PM PDT 24 8224455493 ps
T390 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2688988792 Jun 28 04:32:21 PM PDT 24 Jun 28 04:32:50 PM PDT 24 18248147612 ps
T391 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2268180061 Jun 28 04:32:25 PM PDT 24 Jun 28 04:32:45 PM PDT 24 6879812437 ps
T97 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2460082686 Jun 28 04:32:24 PM PDT 24 Jun 28 04:32:59 PM PDT 24 3860114253 ps
T392 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.260731708 Jun 28 04:32:31 PM PDT 24 Jun 28 04:32:40 PM PDT 24 661461295 ps
T393 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2728821796 Jun 28 04:32:29 PM PDT 24 Jun 28 04:33:01 PM PDT 24 11591831384 ps
T112 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1399531006 Jun 28 04:32:21 PM PDT 24 Jun 28 04:35:10 PM PDT 24 10803366743 ps
T394 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1603247867 Jun 28 04:32:35 PM PDT 24 Jun 28 04:32:45 PM PDT 24 167446556 ps
T395 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1466749972 Jun 28 04:32:24 PM PDT 24 Jun 28 04:35:32 PM PDT 24 22366819255 ps
T95 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1507648345 Jun 28 04:32:33 PM PDT 24 Jun 28 04:34:47 PM PDT 24 22109459981 ps
T396 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4096075842 Jun 28 04:32:23 PM PDT 24 Jun 28 04:32:31 PM PDT 24 167413980 ps
T397 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3479477037 Jun 28 04:32:22 PM PDT 24 Jun 28 04:32:44 PM PDT 24 4804881541 ps
T398 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3578890652 Jun 28 04:32:27 PM PDT 24 Jun 28 04:32:59 PM PDT 24 6241559448 ps
T114 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4187788154 Jun 28 04:32:30 PM PDT 24 Jun 28 04:33:50 PM PDT 24 443485664 ps
T399 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1223579957 Jun 28 04:32:34 PM PDT 24 Jun 28 04:33:07 PM PDT 24 72656964171 ps
T400 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2597109497 Jun 28 04:32:31 PM PDT 24 Jun 28 04:32:59 PM PDT 24 11136567231 ps
T401 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3622497162 Jun 28 04:32:42 PM PDT 24 Jun 28 04:33:09 PM PDT 24 28816471203 ps
T402 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2185617951 Jun 28 04:32:22 PM PDT 24 Jun 28 04:32:53 PM PDT 24 8061107222 ps
T90 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3904045729 Jun 28 04:32:21 PM PDT 24 Jun 28 04:34:06 PM PDT 24 47898596839 ps
T110 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3699017032 Jun 28 04:32:38 PM PDT 24 Jun 28 04:34:07 PM PDT 24 1472182560 ps
T403 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1588045097 Jun 28 04:32:57 PM PDT 24 Jun 28 04:33:15 PM PDT 24 1685396543 ps
T404 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2624471050 Jun 28 04:32:31 PM PDT 24 Jun 28 04:32:40 PM PDT 24 869661284 ps
T405 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2528498569 Jun 28 04:32:29 PM PDT 24 Jun 28 04:32:44 PM PDT 24 905524575 ps
T406 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3366409529 Jun 28 04:32:49 PM PDT 24 Jun 28 04:34:05 PM PDT 24 5930681034 ps
T407 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1636405381 Jun 28 04:32:27 PM PDT 24 Jun 28 04:32:48 PM PDT 24 9221543894 ps
T408 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4070800579 Jun 28 04:32:34 PM PDT 24 Jun 28 04:32:46 PM PDT 24 908959488 ps
T91 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1421200468 Jun 28 04:32:36 PM PDT 24 Jun 28 04:34:03 PM PDT 24 7897543730 ps
T409 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.554366853 Jun 28 04:32:50 PM PDT 24 Jun 28 04:33:02 PM PDT 24 345834581 ps
T410 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.875021665 Jun 28 04:32:41 PM PDT 24 Jun 28 04:33:13 PM PDT 24 3079897583 ps
T411 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2747142827 Jun 28 04:32:26 PM PDT 24 Jun 28 04:32:36 PM PDT 24 190571518 ps
T111 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1297589972 Jun 28 04:32:36 PM PDT 24 Jun 28 04:33:59 PM PDT 24 299873761 ps
T96 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.182847076 Jun 28 04:32:36 PM PDT 24 Jun 28 04:32:59 PM PDT 24 9592507524 ps
T412 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1850369236 Jun 28 04:32:17 PM PDT 24 Jun 28 04:32:29 PM PDT 24 687854969 ps
T413 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.583444612 Jun 28 04:32:43 PM PDT 24 Jun 28 04:33:15 PM PDT 24 3829927460 ps
T414 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3544705661 Jun 28 04:32:31 PM PDT 24 Jun 28 04:33:01 PM PDT 24 14434872913 ps
T415 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1002596311 Jun 28 04:32:34 PM PDT 24 Jun 28 04:33:03 PM PDT 24 19629904496 ps
T416 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2535012493 Jun 28 04:32:32 PM PDT 24 Jun 28 04:32:57 PM PDT 24 2078597402 ps
T115 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1488783859 Jun 28 04:32:35 PM PDT 24 Jun 28 04:35:27 PM PDT 24 12011837673 ps
T92 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2055826199 Jun 28 04:32:29 PM PDT 24 Jun 28 04:34:42 PM PDT 24 120594208050 ps
T117 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1310940266 Jun 28 04:32:25 PM PDT 24 Jun 28 04:35:14 PM PDT 24 22108925406 ps
T417 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3218206061 Jun 28 04:32:46 PM PDT 24 Jun 28 04:33:10 PM PDT 24 2537375874 ps
T418 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.468902524 Jun 28 04:32:35 PM PDT 24 Jun 28 04:33:04 PM PDT 24 10631986467 ps
T419 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.569169163 Jun 28 04:32:32 PM PDT 24 Jun 28 04:32:45 PM PDT 24 1030781992 ps
T420 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.4123814079 Jun 28 04:32:34 PM PDT 24 Jun 28 04:34:00 PM PDT 24 1498923673 ps
T421 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4027278117 Jun 28 04:32:44 PM PDT 24 Jun 28 04:33:15 PM PDT 24 11924077060 ps
T422 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3449235512 Jun 28 04:32:31 PM PDT 24 Jun 28 04:35:19 PM PDT 24 17695913552 ps
T423 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1837453042 Jun 28 04:32:40 PM PDT 24 Jun 28 04:35:34 PM PDT 24 40950464330 ps
T424 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3339954283 Jun 28 04:32:30 PM PDT 24 Jun 28 04:32:47 PM PDT 24 1014573168 ps
T93 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1745383196 Jun 28 04:32:36 PM PDT 24 Jun 28 04:33:06 PM PDT 24 7542961187 ps
T425 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2683294225 Jun 28 04:32:34 PM PDT 24 Jun 28 04:33:02 PM PDT 24 13437756440 ps
T426 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2598066892 Jun 28 04:32:55 PM PDT 24 Jun 28 04:33:10 PM PDT 24 1069605946 ps
T94 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3854987867 Jun 28 04:32:31 PM PDT 24 Jun 28 04:35:41 PM PDT 24 90621104606 ps
T427 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3020177200 Jun 28 04:32:34 PM PDT 24 Jun 28 04:32:45 PM PDT 24 941969152 ps
T428 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1788979407 Jun 28 04:32:36 PM PDT 24 Jun 28 04:32:50 PM PDT 24 2304837027 ps
T429 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.727344040 Jun 28 04:32:28 PM PDT 24 Jun 28 04:34:03 PM PDT 24 7673156511 ps
T430 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.217957050 Jun 28 04:32:33 PM PDT 24 Jun 28 04:32:44 PM PDT 24 270484435 ps
T431 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.122903825 Jun 28 04:32:23 PM PDT 24 Jun 28 04:32:42 PM PDT 24 1960164566 ps
T432 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2372291643 Jun 28 04:32:32 PM PDT 24 Jun 28 04:33:04 PM PDT 24 8078017911 ps
T433 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2942768044 Jun 28 04:32:18 PM PDT 24 Jun 28 04:32:54 PM PDT 24 25886113255 ps
T434 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2356428340 Jun 28 04:32:09 PM PDT 24 Jun 28 04:32:33 PM PDT 24 9642744235 ps
T435 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1168817936 Jun 28 04:32:33 PM PDT 24 Jun 28 04:34:56 PM PDT 24 28749059908 ps
T436 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2783220175 Jun 28 04:32:32 PM PDT 24 Jun 28 04:32:42 PM PDT 24 260681808 ps
T437 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2386092216 Jun 28 04:32:38 PM PDT 24 Jun 28 04:32:48 PM PDT 24 347768839 ps
T438 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1608492214 Jun 28 04:32:33 PM PDT 24 Jun 28 04:32:48 PM PDT 24 358173831 ps
T439 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1705370999 Jun 28 04:32:34 PM PDT 24 Jun 28 04:32:44 PM PDT 24 174215916 ps
T440 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.591211151 Jun 28 04:32:31 PM PDT 24 Jun 28 04:33:00 PM PDT 24 21527059082 ps
T441 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4207362780 Jun 28 04:32:30 PM PDT 24 Jun 28 04:32:58 PM PDT 24 3544022083 ps
T442 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.557753117 Jun 28 04:32:34 PM PDT 24 Jun 28 04:33:57 PM PDT 24 4631288372 ps
T443 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1411682713 Jun 28 04:32:35 PM PDT 24 Jun 28 04:34:23 PM PDT 24 15974168381 ps
T444 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2261545185 Jun 28 04:32:21 PM PDT 24 Jun 28 04:32:45 PM PDT 24 4323760094 ps
T445 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1280487322 Jun 28 04:32:08 PM PDT 24 Jun 28 04:32:31 PM PDT 24 9157294162 ps
T88 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3235099342 Jun 28 04:32:34 PM PDT 24 Jun 28 04:32:53 PM PDT 24 5877956263 ps
T446 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2798332387 Jun 28 04:32:24 PM PDT 24 Jun 28 04:33:41 PM PDT 24 2607911907 ps
T119 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3429523104 Jun 28 04:32:36 PM PDT 24 Jun 28 04:34:11 PM PDT 24 2339332802 ps
T447 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3654481069 Jun 28 04:32:29 PM PDT 24 Jun 28 04:32:49 PM PDT 24 1933328249 ps
T448 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2483054082 Jun 28 04:32:38 PM PDT 24 Jun 28 04:33:10 PM PDT 24 3669435248 ps
T449 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1914553314 Jun 28 04:32:30 PM PDT 24 Jun 28 04:32:55 PM PDT 24 2710815933 ps
T450 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.654849105 Jun 28 04:32:35 PM PDT 24 Jun 28 04:33:07 PM PDT 24 11741706245 ps
T451 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2674486373 Jun 28 04:32:26 PM PDT 24 Jun 28 04:35:28 PM PDT 24 86086694549 ps
T452 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.63387857 Jun 28 04:32:25 PM PDT 24 Jun 28 04:33:54 PM PDT 24 1369972658 ps

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.2236428986
Short name T9
Test name
Test status
Simulation time 13227499691 ps
CPU time 3234.07 seconds
Started Jun 28 04:33:23 PM PDT 24
Finished Jun 28 05:27:18 PM PDT 24
Peak memory 229836 kb
Host smart-f58356a0-1787-4381-8a08-66541d8c78fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236428986 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.2236428986
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3264006092
Short name T17
Test name
Test status
Simulation time 253359211645 ps
CPU time 699.7 seconds
Started Jun 28 04:32:43 PM PDT 24
Finished Jun 28 04:44:24 PM PDT 24
Peak memory 233784 kb
Host smart-8672d9dd-eda1-442d-ba5a-bd626fef8929
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264006092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3264006092
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.2532229741
Short name T12
Test name
Test status
Simulation time 154809840085 ps
CPU time 3120.93 seconds
Started Jun 28 04:33:10 PM PDT 24
Finished Jun 28 05:25:14 PM PDT 24
Peak memory 251596 kb
Host smart-2523d286-6eb2-4bf0-8bb0-90e14fa4737b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532229741 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.2532229741
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.69753048
Short name T21
Test name
Test status
Simulation time 4486479461 ps
CPU time 249.03 seconds
Started Jun 28 04:32:52 PM PDT 24
Finished Jun 28 04:37:02 PM PDT 24
Peak memory 234936 kb
Host smart-2d1d40d2-2466-46c6-a72c-747bb33d98a9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69753048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.69753048
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1399531006
Short name T112
Test name
Test status
Simulation time 10803366743 ps
CPU time 168.56 seconds
Started Jun 28 04:32:21 PM PDT 24
Finished Jun 28 04:35:10 PM PDT 24
Peak memory 214260 kb
Host smart-89783ba8-b8a0-4bff-b30c-b5b39c33bc85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399531006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1399531006
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2731731014
Short name T6
Test name
Test status
Simulation time 4667213155 ps
CPU time 35.94 seconds
Started Jun 28 04:33:05 PM PDT 24
Finished Jun 28 04:33:44 PM PDT 24
Peak memory 215968 kb
Host smart-576e37b0-8b46-4dc6-acaf-995acc11f6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731731014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2731731014
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1699117508
Short name T66
Test name
Test status
Simulation time 17787233826 ps
CPU time 154.77 seconds
Started Jun 28 04:32:35 PM PDT 24
Finished Jun 28 04:35:11 PM PDT 24
Peak memory 215228 kb
Host smart-c4739f54-746e-4fb8-b2db-d8551b917380
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699117508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1699117508
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.890403498
Short name T42
Test name
Test status
Simulation time 18401198563 ps
CPU time 412.54 seconds
Started Jun 28 04:33:09 PM PDT 24
Finished Jun 28 04:40:05 PM PDT 24
Peak memory 240564 kb
Host smart-fc844d57-4813-4416-ba93-1a6868827ffc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890403498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.890403498
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1488783859
Short name T115
Test name
Test status
Simulation time 12011837673 ps
CPU time 170.47 seconds
Started Jun 28 04:32:35 PM PDT 24
Finished Jun 28 04:35:27 PM PDT 24
Peak memory 214164 kb
Host smart-bc1b083c-501b-48a7-a0f8-36b37355d790
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488783859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1488783859
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.612315507
Short name T31
Test name
Test status
Simulation time 10907464741 ps
CPU time 14.43 seconds
Started Jun 28 04:33:11 PM PDT 24
Finished Jun 28 04:33:28 PM PDT 24
Peak memory 217396 kb
Host smart-5924fbc3-1c83-4002-922e-e7c891ab0db9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612315507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.612315507
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3074058957
Short name T8
Test name
Test status
Simulation time 917831314 ps
CPU time 19.02 seconds
Started Jun 28 04:33:14 PM PDT 24
Finished Jun 28 04:33:34 PM PDT 24
Peak memory 219172 kb
Host smart-cdb22f83-2a49-47e5-8878-9cb4fb7fc079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074058957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3074058957
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3116164751
Short name T23
Test name
Test status
Simulation time 662305479 ps
CPU time 23.84 seconds
Started Jun 28 04:33:01 PM PDT 24
Finished Jun 28 04:33:27 PM PDT 24
Peak memory 218464 kb
Host smart-0bc24a54-c7b9-4dc7-8b3a-41e321b52511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116164751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3116164751
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1297589972
Short name T111
Test name
Test status
Simulation time 299873761 ps
CPU time 82.33 seconds
Started Jun 28 04:32:36 PM PDT 24
Finished Jun 28 04:33:59 PM PDT 24
Peak memory 213644 kb
Host smart-0fd3c6d7-efa2-479d-9ba5-aeeb55ce8312
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297589972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1297589972
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1641937051
Short name T22
Test name
Test status
Simulation time 3411847528 ps
CPU time 137.91 seconds
Started Jun 28 04:32:37 PM PDT 24
Finished Jun 28 04:34:56 PM PDT 24
Peak memory 238164 kb
Host smart-056bc6e7-8ae6-4932-9311-0ef443ce09f5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641937051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1641937051
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1168817936
Short name T435
Test name
Test status
Simulation time 28749059908 ps
CPU time 141.82 seconds
Started Jun 28 04:32:33 PM PDT 24
Finished Jun 28 04:34:56 PM PDT 24
Peak memory 214836 kb
Host smart-a33a5656-2b90-43d8-ad2c-ef7553cfda97
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168817936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1168817936
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3521309529
Short name T47
Test name
Test status
Simulation time 1642274290 ps
CPU time 20.01 seconds
Started Jun 28 04:33:10 PM PDT 24
Finished Jun 28 04:33:33 PM PDT 24
Peak memory 219188 kb
Host smart-5c6349a2-294e-40de-9447-dabbd9ad4514
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3521309529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3521309529
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2725784675
Short name T230
Test name
Test status
Simulation time 28843145174 ps
CPU time 67.36 seconds
Started Jun 28 04:32:44 PM PDT 24
Finished Jun 28 04:33:53 PM PDT 24
Peak memory 219212 kb
Host smart-886ff9ab-7df4-479b-8218-67136e01524c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725784675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2725784675
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1280487322
Short name T445
Test name
Test status
Simulation time 9157294162 ps
CPU time 22.2 seconds
Started Jun 28 04:32:08 PM PDT 24
Finished Jun 28 04:32:31 PM PDT 24
Peak memory 211764 kb
Host smart-90baa6eb-776e-43f8-bea9-cde643c33516
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280487322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1280487322
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1705370999
Short name T439
Test name
Test status
Simulation time 174215916 ps
CPU time 8.69 seconds
Started Jun 28 04:32:34 PM PDT 24
Finished Jun 28 04:32:44 PM PDT 24
Peak memory 210532 kb
Host smart-ecc6ef73-ae2d-4c54-8946-a45d3717be6f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705370999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1705370999
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2261545185
Short name T444
Test name
Test status
Simulation time 4323760094 ps
CPU time 24.23 seconds
Started Jun 28 04:32:21 PM PDT 24
Finished Jun 28 04:32:45 PM PDT 24
Peak memory 211804 kb
Host smart-edebeff6-69c5-458a-9308-2670bcbafc49
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261545185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2261545185
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2356428340
Short name T434
Test name
Test status
Simulation time 9642744235 ps
CPU time 23.33 seconds
Started Jun 28 04:32:09 PM PDT 24
Finished Jun 28 04:32:33 PM PDT 24
Peak memory 216264 kb
Host smart-7fecd4ff-7b8a-4ebb-aab9-d81188761b2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356428340 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2356428340
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.4167270843
Short name T378
Test name
Test status
Simulation time 3315698544 ps
CPU time 27.74 seconds
Started Jun 28 04:32:27 PM PDT 24
Finished Jun 28 04:32:56 PM PDT 24
Peak memory 211740 kb
Host smart-41513600-486f-4f30-b858-c19603493eb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167270843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.4167270843
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4096075842
Short name T396
Test name
Test status
Simulation time 167413980 ps
CPU time 8.08 seconds
Started Jun 28 04:32:23 PM PDT 24
Finished Jun 28 04:32:31 PM PDT 24
Peak memory 210448 kb
Host smart-31271572-4f95-415c-8393-16345ae78f56
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096075842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.4096075842
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.122903825
Short name T431
Test name
Test status
Simulation time 1960164566 ps
CPU time 19.43 seconds
Started Jun 28 04:32:23 PM PDT 24
Finished Jun 28 04:32:42 PM PDT 24
Peak memory 210436 kb
Host smart-2d9fa3de-560e-436a-9bd8-6f49610e4d59
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122903825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
122903825
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3994645500
Short name T105
Test name
Test status
Simulation time 35717335894 ps
CPU time 92.01 seconds
Started Jun 28 04:32:09 PM PDT 24
Finished Jun 28 04:33:42 PM PDT 24
Peak memory 214028 kb
Host smart-b34a33e8-3c67-4f11-9068-681a246c79b9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994645500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3994645500
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2688988792
Short name T390
Test name
Test status
Simulation time 18248147612 ps
CPU time 28.66 seconds
Started Jun 28 04:32:21 PM PDT 24
Finished Jun 28 04:32:50 PM PDT 24
Peak memory 212624 kb
Host smart-fddd245d-a97e-42d8-bd70-0de282ebbbad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688988792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2688988792
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2093248776
Short name T61
Test name
Test status
Simulation time 18354520474 ps
CPU time 37.7 seconds
Started Jun 28 04:32:25 PM PDT 24
Finished Jun 28 04:33:03 PM PDT 24
Peak memory 217672 kb
Host smart-84a7b631-86b5-4389-87d0-d1f321dae7db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093248776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2093248776
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.761930765
Short name T57
Test name
Test status
Simulation time 2919267185 ps
CPU time 167.6 seconds
Started Jun 28 04:32:23 PM PDT 24
Finished Jun 28 04:35:11 PM PDT 24
Peak memory 213832 kb
Host smart-9eca0697-1fb1-4e01-bf10-8e88973cca45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761930765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.761930765
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.182847076
Short name T96
Test name
Test status
Simulation time 9592507524 ps
CPU time 21.87 seconds
Started Jun 28 04:32:36 PM PDT 24
Finished Jun 28 04:32:59 PM PDT 24
Peak memory 211300 kb
Host smart-317a56cb-053f-4afe-be95-f4ea6eef6233
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182847076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.182847076
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.569169163
Short name T419
Test name
Test status
Simulation time 1030781992 ps
CPU time 12.11 seconds
Started Jun 28 04:32:32 PM PDT 24
Finished Jun 28 04:32:45 PM PDT 24
Peak memory 210588 kb
Host smart-667826ce-cf32-4753-9dd5-1d784ecda1d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569169163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.569169163
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3377869110
Short name T64
Test name
Test status
Simulation time 3596902603 ps
CPU time 32.67 seconds
Started Jun 28 04:32:27 PM PDT 24
Finished Jun 28 04:33:00 PM PDT 24
Peak memory 211644 kb
Host smart-6a9171e7-5ec0-401f-9380-78697932b8a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377869110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3377869110
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.731676411
Short name T376
Test name
Test status
Simulation time 676962767 ps
CPU time 8.48 seconds
Started Jun 28 04:32:08 PM PDT 24
Finished Jun 28 04:32:17 PM PDT 24
Peak memory 216352 kb
Host smart-e43284a6-7810-41c1-ad51-7d2543c0ba41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731676411 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.731676411
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2217238398
Short name T385
Test name
Test status
Simulation time 2292963785 ps
CPU time 22.99 seconds
Started Jun 28 04:32:16 PM PDT 24
Finished Jun 28 04:32:39 PM PDT 24
Peak memory 211544 kb
Host smart-e4e4cb57-d5f4-48ef-b148-d676e9adddee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217238398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2217238398
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3956074528
Short name T373
Test name
Test status
Simulation time 4275360572 ps
CPU time 31.64 seconds
Started Jun 28 04:32:13 PM PDT 24
Finished Jun 28 04:32:45 PM PDT 24
Peak memory 210520 kb
Host smart-d8731f7c-175f-4d84-af95-34c093ee544f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956074528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3956074528
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4207362780
Short name T441
Test name
Test status
Simulation time 3544022083 ps
CPU time 27.77 seconds
Started Jun 28 04:32:30 PM PDT 24
Finished Jun 28 04:32:58 PM PDT 24
Peak memory 210516 kb
Host smart-b8ab8231-fb3a-4128-a8ed-995ad9cdfec6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207362780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.4207362780
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2722237315
Short name T388
Test name
Test status
Simulation time 8931956438 ps
CPU time 87.77 seconds
Started Jun 28 04:32:28 PM PDT 24
Finished Jun 28 04:33:57 PM PDT 24
Peak memory 213956 kb
Host smart-f27e3ab7-3a3a-4d6c-8521-9badbaad1029
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722237315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2722237315
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1636405381
Short name T407
Test name
Test status
Simulation time 9221543894 ps
CPU time 20.43 seconds
Started Jun 28 04:32:27 PM PDT 24
Finished Jun 28 04:32:48 PM PDT 24
Peak memory 212496 kb
Host smart-7ce49866-428e-4c1e-8c07-9e00d2388cda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636405381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1636405381
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3339954283
Short name T424
Test name
Test status
Simulation time 1014573168 ps
CPU time 16.72 seconds
Started Jun 28 04:32:30 PM PDT 24
Finished Jun 28 04:32:47 PM PDT 24
Peak memory 217260 kb
Host smart-736994f6-f32d-432b-889c-b841d796020f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339954283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3339954283
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2386092216
Short name T437
Test name
Test status
Simulation time 347768839 ps
CPU time 8.5 seconds
Started Jun 28 04:32:38 PM PDT 24
Finished Jun 28 04:32:48 PM PDT 24
Peak memory 215148 kb
Host smart-68316afb-6a11-45c6-9ce1-b9ca42afc003
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386092216 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2386092216
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.662074359
Short name T381
Test name
Test status
Simulation time 6983538081 ps
CPU time 19.65 seconds
Started Jun 28 04:32:30 PM PDT 24
Finished Jun 28 04:32:50 PM PDT 24
Peak memory 211844 kb
Host smart-46e3ef9d-b7e9-4527-9465-a934083fb043
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662074359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.662074359
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2712981587
Short name T99
Test name
Test status
Simulation time 688601355 ps
CPU time 8.33 seconds
Started Jun 28 04:32:31 PM PDT 24
Finished Jun 28 04:32:45 PM PDT 24
Peak memory 211144 kb
Host smart-bad3a04c-6f5b-4c03-b867-ebdf4e4f870d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712981587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2712981587
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2597109497
Short name T400
Test name
Test status
Simulation time 11136567231 ps
CPU time 26.99 seconds
Started Jun 28 04:32:31 PM PDT 24
Finished Jun 28 04:32:59 PM PDT 24
Peak memory 218592 kb
Host smart-cf65169f-f2c0-4c35-99f4-4fb132e451a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597109497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2597109497
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3020177200
Short name T427
Test name
Test status
Simulation time 941969152 ps
CPU time 9.49 seconds
Started Jun 28 04:32:34 PM PDT 24
Finished Jun 28 04:32:45 PM PDT 24
Peak memory 217152 kb
Host smart-f9edf773-a7e4-4f97-8931-8f10c547438e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020177200 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3020177200
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2922386030
Short name T74
Test name
Test status
Simulation time 986558104 ps
CPU time 14.86 seconds
Started Jun 28 04:32:26 PM PDT 24
Finished Jun 28 04:32:41 PM PDT 24
Peak memory 211340 kb
Host smart-d87be7e6-0297-4dbe-a42c-4e7a87515704
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922386030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2922386030
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.592198022
Short name T100
Test name
Test status
Simulation time 11220077644 ps
CPU time 25.2 seconds
Started Jun 28 04:32:44 PM PDT 24
Finished Jun 28 04:33:10 PM PDT 24
Peak memory 212612 kb
Host smart-901a88e0-4671-45b7-9f42-94493353446a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592198022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.592198022
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3622497162
Short name T401
Test name
Test status
Simulation time 28816471203 ps
CPU time 26.55 seconds
Started Jun 28 04:32:42 PM PDT 24
Finished Jun 28 04:33:09 PM PDT 24
Peak memory 218576 kb
Host smart-192bc0ca-efe6-4cf5-b08c-5f00400fb8e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622497162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3622497162
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.557753117
Short name T442
Test name
Test status
Simulation time 4631288372 ps
CPU time 81.69 seconds
Started Jun 28 04:32:34 PM PDT 24
Finished Jun 28 04:33:57 PM PDT 24
Peak memory 214052 kb
Host smart-c4864345-c909-4f75-8e41-789cdb1047a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557753117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.557753117
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1361824468
Short name T69
Test name
Test status
Simulation time 201736437 ps
CPU time 8.8 seconds
Started Jun 28 04:32:24 PM PDT 24
Finished Jun 28 04:32:33 PM PDT 24
Peak memory 215916 kb
Host smart-549aaed3-9003-49bf-9f67-a7d544f2a789
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361824468 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1361824468
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1799605127
Short name T384
Test name
Test status
Simulation time 4171704272 ps
CPU time 30.54 seconds
Started Jun 28 04:32:32 PM PDT 24
Finished Jun 28 04:33:03 PM PDT 24
Peak memory 211768 kb
Host smart-b4728162-a56b-4c02-a076-b1a6a5da43f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799605127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1799605127
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1507648345
Short name T95
Test name
Test status
Simulation time 22109459981 ps
CPU time 133.56 seconds
Started Jun 28 04:32:33 PM PDT 24
Finished Jun 28 04:34:47 PM PDT 24
Peak memory 215396 kb
Host smart-67062251-dd84-4f0b-bbb8-307ad83576a5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507648345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1507648345
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2372291643
Short name T432
Test name
Test status
Simulation time 8078017911 ps
CPU time 30.72 seconds
Started Jun 28 04:32:32 PM PDT 24
Finished Jun 28 04:33:04 PM PDT 24
Peak memory 212504 kb
Host smart-155702df-e6fb-424b-b852-b7d7dc255081
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372291643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2372291643
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2535012493
Short name T416
Test name
Test status
Simulation time 2078597402 ps
CPU time 23.98 seconds
Started Jun 28 04:32:32 PM PDT 24
Finished Jun 28 04:32:57 PM PDT 24
Peak memory 218116 kb
Host smart-40348d1f-9cf8-4239-af57-d15c92f4a577
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535012493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2535012493
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3524382744
Short name T109
Test name
Test status
Simulation time 8428044420 ps
CPU time 93.86 seconds
Started Jun 28 04:32:32 PM PDT 24
Finished Jun 28 04:34:07 PM PDT 24
Peak memory 218788 kb
Host smart-d75b8412-a872-4940-b763-177237d80d32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524382744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3524382744
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.654849105
Short name T450
Test name
Test status
Simulation time 11741706245 ps
CPU time 31.19 seconds
Started Jun 28 04:32:35 PM PDT 24
Finished Jun 28 04:33:07 PM PDT 24
Peak memory 218208 kb
Host smart-1a8c1ae8-58b2-46e2-a3b4-c3c104061cef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654849105 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.654849105
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2622991544
Short name T361
Test name
Test status
Simulation time 1663634009 ps
CPU time 18.81 seconds
Started Jun 28 04:32:33 PM PDT 24
Finished Jun 28 04:32:57 PM PDT 24
Peak memory 211184 kb
Host smart-1b09fa60-f023-488f-a82f-d4540c1dfe36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622991544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2622991544
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2798332387
Short name T446
Test name
Test status
Simulation time 2607911907 ps
CPU time 76.28 seconds
Started Jun 28 04:32:24 PM PDT 24
Finished Jun 28 04:33:41 PM PDT 24
Peak memory 214748 kb
Host smart-61a5af9c-f44f-47ce-a6c6-2e32238066ce
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798332387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2798332387
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1223579957
Short name T399
Test name
Test status
Simulation time 72656964171 ps
CPU time 32.43 seconds
Started Jun 28 04:32:34 PM PDT 24
Finished Jun 28 04:33:07 PM PDT 24
Peak memory 212448 kb
Host smart-48929be6-63a6-4f6b-b0af-0e4570dd761f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223579957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1223579957
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.875021665
Short name T410
Test name
Test status
Simulation time 3079897583 ps
CPU time 31.39 seconds
Started Jun 28 04:32:41 PM PDT 24
Finished Jun 28 04:33:13 PM PDT 24
Peak memory 218884 kb
Host smart-3f7987db-e142-4380-b260-65f30bb7a211
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875021665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.875021665
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.177226125
Short name T60
Test name
Test status
Simulation time 24431576148 ps
CPU time 101.66 seconds
Started Jun 28 04:32:55 PM PDT 24
Finished Jun 28 04:34:37 PM PDT 24
Peak memory 213540 kb
Host smart-bcfb004f-d7f1-4c3a-850b-19dc1355f55f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177226125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.177226125
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3532560413
Short name T59
Test name
Test status
Simulation time 4169370701 ps
CPU time 32.83 seconds
Started Jun 28 04:32:24 PM PDT 24
Finished Jun 28 04:32:58 PM PDT 24
Peak memory 216848 kb
Host smart-499cffec-18f3-44d2-90b8-d19b12c7c42d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532560413 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3532560413
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3235099342
Short name T88
Test name
Test status
Simulation time 5877956263 ps
CPU time 17.67 seconds
Started Jun 28 04:32:34 PM PDT 24
Finished Jun 28 04:32:53 PM PDT 24
Peak memory 211996 kb
Host smart-4715ac4b-bf0e-4c61-a5df-0330e1c1b061
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235099342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3235099342
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1837453042
Short name T423
Test name
Test status
Simulation time 40950464330 ps
CPU time 172.69 seconds
Started Jun 28 04:32:40 PM PDT 24
Finished Jun 28 04:35:34 PM PDT 24
Peak memory 214960 kb
Host smart-56ed35c0-f370-48f6-9bca-5d055a953d58
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837453042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1837453042
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2331287479
Short name T389
Test name
Test status
Simulation time 8224455493 ps
CPU time 19.03 seconds
Started Jun 28 04:32:26 PM PDT 24
Finished Jun 28 04:32:46 PM PDT 24
Peak memory 212444 kb
Host smart-d5a6021e-670b-47b2-9b71-278fef1f4898
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331287479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2331287479
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3578890652
Short name T398
Test name
Test status
Simulation time 6241559448 ps
CPU time 31.7 seconds
Started Jun 28 04:32:27 PM PDT 24
Finished Jun 28 04:32:59 PM PDT 24
Peak memory 217432 kb
Host smart-95d4f60a-ff71-4a60-97cd-c26730fc14b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578890652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3578890652
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3429523104
Short name T119
Test name
Test status
Simulation time 2339332802 ps
CPU time 93.69 seconds
Started Jun 28 04:32:36 PM PDT 24
Finished Jun 28 04:34:11 PM PDT 24
Peak memory 213556 kb
Host smart-e89abe4d-b450-4c4d-8b27-ac19a46c2f17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429523104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3429523104
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3544705661
Short name T414
Test name
Test status
Simulation time 14434872913 ps
CPU time 29.21 seconds
Started Jun 28 04:32:31 PM PDT 24
Finished Jun 28 04:33:01 PM PDT 24
Peak memory 217212 kb
Host smart-a97882da-b559-4146-a968-38f21b7f4ac4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544705661 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3544705661
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2019292701
Short name T73
Test name
Test status
Simulation time 765324847 ps
CPU time 10.59 seconds
Started Jun 28 04:32:32 PM PDT 24
Finished Jun 28 04:32:43 PM PDT 24
Peak memory 210564 kb
Host smart-ef0f10ff-b7ac-441d-962a-8187ff256988
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019292701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2019292701
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1466749972
Short name T395
Test name
Test status
Simulation time 22366819255 ps
CPU time 186.76 seconds
Started Jun 28 04:32:24 PM PDT 24
Finished Jun 28 04:35:32 PM PDT 24
Peak memory 215088 kb
Host smart-f3ca4995-4248-47a0-87c2-43233ba1071b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466749972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1466749972
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2598066892
Short name T426
Test name
Test status
Simulation time 1069605946 ps
CPU time 14.89 seconds
Started Jun 28 04:32:55 PM PDT 24
Finished Jun 28 04:33:10 PM PDT 24
Peak memory 211240 kb
Host smart-d9862676-eec4-4edc-a8fc-82b043c427bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598066892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2598066892
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1806362865
Short name T375
Test name
Test status
Simulation time 687689816 ps
CPU time 12.07 seconds
Started Jun 28 04:32:47 PM PDT 24
Finished Jun 28 04:33:00 PM PDT 24
Peak memory 217156 kb
Host smart-089695d6-c5bb-4f57-9e99-b1ca6ce385a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806362865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1806362865
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1310940266
Short name T117
Test name
Test status
Simulation time 22108925406 ps
CPU time 168.42 seconds
Started Jun 28 04:32:25 PM PDT 24
Finished Jun 28 04:35:14 PM PDT 24
Peak memory 212780 kb
Host smart-f2302abb-9785-4378-b976-d8439ce7cbe5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310940266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1310940266
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2729528998
Short name T372
Test name
Test status
Simulation time 758884455 ps
CPU time 14.27 seconds
Started Jun 28 04:32:38 PM PDT 24
Finished Jun 28 04:32:53 PM PDT 24
Peak memory 216964 kb
Host smart-deee3ebe-874d-49f6-b3a0-8dca2918a02c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729528998 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2729528998
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1588045097
Short name T403
Test name
Test status
Simulation time 1685396543 ps
CPU time 16.12 seconds
Started Jun 28 04:32:57 PM PDT 24
Finished Jun 28 04:33:15 PM PDT 24
Peak memory 210388 kb
Host smart-a9132e1e-f215-47c7-8fc2-4fcb00edd4b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588045097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1588045097
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1240528232
Short name T367
Test name
Test status
Simulation time 75077074458 ps
CPU time 167.11 seconds
Started Jun 28 04:32:36 PM PDT 24
Finished Jun 28 04:35:25 PM PDT 24
Peak memory 214924 kb
Host smart-d474f2a3-dfed-4429-a136-88e280e21912
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240528232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1240528232
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3218206061
Short name T417
Test name
Test status
Simulation time 2537375874 ps
CPU time 23.93 seconds
Started Jun 28 04:32:46 PM PDT 24
Finished Jun 28 04:33:10 PM PDT 24
Peak memory 212392 kb
Host smart-6d0af98a-7c00-46d8-8de6-2630e6910451
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218206061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3218206061
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2133758783
Short name T380
Test name
Test status
Simulation time 7832098480 ps
CPU time 32.75 seconds
Started Jun 28 04:32:52 PM PDT 24
Finished Jun 28 04:33:26 PM PDT 24
Peak memory 218468 kb
Host smart-3a85aa8e-31c2-4ab2-ae9e-53adba7e037e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133758783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2133758783
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3078174015
Short name T118
Test name
Test status
Simulation time 1796668884 ps
CPU time 158.38 seconds
Started Jun 28 04:32:35 PM PDT 24
Finished Jun 28 04:35:14 PM PDT 24
Peak memory 213900 kb
Host smart-698f13bb-7c1a-4587-9288-abd33a4834fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078174015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3078174015
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4070800579
Short name T408
Test name
Test status
Simulation time 908959488 ps
CPU time 11.4 seconds
Started Jun 28 04:32:34 PM PDT 24
Finished Jun 28 04:32:46 PM PDT 24
Peak memory 213908 kb
Host smart-c5072341-a633-4330-ad29-b6bd22b72c6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070800579 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.4070800579
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2284483349
Short name T89
Test name
Test status
Simulation time 3830497511 ps
CPU time 29.12 seconds
Started Jun 28 04:32:38 PM PDT 24
Finished Jun 28 04:33:08 PM PDT 24
Peak memory 211664 kb
Host smart-e5445f0b-b978-4526-bbe1-78a063e3c0b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284483349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2284483349
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2106061632
Short name T83
Test name
Test status
Simulation time 61307343744 ps
CPU time 154.14 seconds
Started Jun 28 04:32:40 PM PDT 24
Finished Jun 28 04:35:15 PM PDT 24
Peak memory 214988 kb
Host smart-33868433-5372-417e-934a-7948a19a784e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106061632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2106061632
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2686611364
Short name T71
Test name
Test status
Simulation time 4293237499 ps
CPU time 32.9 seconds
Started Jun 28 04:32:39 PM PDT 24
Finished Jun 28 04:33:13 PM PDT 24
Peak memory 212276 kb
Host smart-791fa608-c18e-45bf-8386-fe1be143fc97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686611364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2686611364
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1254905427
Short name T371
Test name
Test status
Simulation time 12107498775 ps
CPU time 33.13 seconds
Started Jun 28 04:32:48 PM PDT 24
Finished Jun 28 04:33:22 PM PDT 24
Peak memory 217728 kb
Host smart-667e885d-d58f-42f6-9f09-adcd95758722
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254905427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1254905427
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1450783773
Short name T113
Test name
Test status
Simulation time 17343836668 ps
CPU time 103.96 seconds
Started Jun 28 04:32:27 PM PDT 24
Finished Jun 28 04:34:12 PM PDT 24
Peak memory 213524 kb
Host smart-146e3d12-47a2-4dc5-8cf9-e0b9a67a25f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450783773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1450783773
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.674753300
Short name T377
Test name
Test status
Simulation time 815634145 ps
CPU time 11.38 seconds
Started Jun 28 04:32:44 PM PDT 24
Finished Jun 28 04:32:56 PM PDT 24
Peak memory 214364 kb
Host smart-7c9da468-8fad-4adf-97dc-41f54053d7d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674753300 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.674753300
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1012163685
Short name T368
Test name
Test status
Simulation time 593626610 ps
CPU time 12.15 seconds
Started Jun 28 04:32:49 PM PDT 24
Finished Jun 28 04:33:02 PM PDT 24
Peak memory 210608 kb
Host smart-0a3ae9c0-5720-4634-9a7d-1d8831889acb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012163685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1012163685
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3366409529
Short name T406
Test name
Test status
Simulation time 5930681034 ps
CPU time 74.91 seconds
Started Jun 28 04:32:49 PM PDT 24
Finished Jun 28 04:34:05 PM PDT 24
Peak memory 214456 kb
Host smart-9ad37707-7c02-4edf-ac70-05572a9a1c71
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366409529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3366409529
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.260731708
Short name T392
Test name
Test status
Simulation time 661461295 ps
CPU time 8.15 seconds
Started Jun 28 04:32:31 PM PDT 24
Finished Jun 28 04:32:40 PM PDT 24
Peak memory 211116 kb
Host smart-a15f2a36-9c9a-4c40-aed2-76a18ae396e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260731708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.260731708
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1981573073
Short name T386
Test name
Test status
Simulation time 569596586 ps
CPU time 11.6 seconds
Started Jun 28 04:32:37 PM PDT 24
Finished Jun 28 04:32:50 PM PDT 24
Peak memory 216056 kb
Host smart-f8b6ce1a-8d67-4732-ac25-c3009764d359
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981573073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1981573073
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.4123814079
Short name T420
Test name
Test status
Simulation time 1498923673 ps
CPU time 85.1 seconds
Started Jun 28 04:32:34 PM PDT 24
Finished Jun 28 04:34:00 PM PDT 24
Peak memory 212472 kb
Host smart-15a91ed5-f1fe-412d-b806-bb697a497f39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123814079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.4123814079
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1711156143
Short name T365
Test name
Test status
Simulation time 4223043091 ps
CPU time 32.19 seconds
Started Jun 28 04:32:30 PM PDT 24
Finished Jun 28 04:33:03 PM PDT 24
Peak memory 214904 kb
Host smart-1f3a8a94-ea97-484a-97f9-e0f92b28a54a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711156143 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1711156143
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.583444612
Short name T413
Test name
Test status
Simulation time 3829927460 ps
CPU time 30.36 seconds
Started Jun 28 04:32:43 PM PDT 24
Finished Jun 28 04:33:15 PM PDT 24
Peak memory 211328 kb
Host smart-bed3f308-cbdf-40a2-bd2a-b88145562136
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583444612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.583444612
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1421200468
Short name T91
Test name
Test status
Simulation time 7897543730 ps
CPU time 83.98 seconds
Started Jun 28 04:32:36 PM PDT 24
Finished Jun 28 04:34:03 PM PDT 24
Peak memory 214056 kb
Host smart-19dabb0b-1156-4c2d-83ee-7443f93a23e3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421200468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1421200468
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1008136448
Short name T101
Test name
Test status
Simulation time 1373099521 ps
CPU time 10.8 seconds
Started Jun 28 04:32:34 PM PDT 24
Finished Jun 28 04:32:45 PM PDT 24
Peak memory 211444 kb
Host smart-98772150-7ab3-4561-bb39-119a1094ec46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008136448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1008136448
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.554366853
Short name T409
Test name
Test status
Simulation time 345834581 ps
CPU time 11.06 seconds
Started Jun 28 04:32:50 PM PDT 24
Finished Jun 28 04:33:02 PM PDT 24
Peak memory 217996 kb
Host smart-42073433-3db8-496b-9613-91c147c7d7b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554366853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.554366853
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3699017032
Short name T110
Test name
Test status
Simulation time 1472182560 ps
CPU time 87.48 seconds
Started Jun 28 04:32:38 PM PDT 24
Finished Jun 28 04:34:07 PM PDT 24
Peak memory 213596 kb
Host smart-e5db8622-07b1-4d81-a213-8047382e866e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699017032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3699017032
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2647157647
Short name T86
Test name
Test status
Simulation time 3139795579 ps
CPU time 25.44 seconds
Started Jun 28 04:32:26 PM PDT 24
Finished Jun 28 04:32:57 PM PDT 24
Peak memory 211388 kb
Host smart-e0b32f5a-8c0d-4b27-a16a-3681c15c2ab4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647157647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2647157647
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.519115670
Short name T369
Test name
Test status
Simulation time 719018323 ps
CPU time 8.91 seconds
Started Jun 28 04:32:24 PM PDT 24
Finished Jun 28 04:32:33 PM PDT 24
Peak memory 210768 kb
Host smart-b260ea51-7d3b-4d1a-9b0d-063c3581b600
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519115670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.519115670
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4052835167
Short name T84
Test name
Test status
Simulation time 670081998 ps
CPU time 11.65 seconds
Started Jun 28 04:32:23 PM PDT 24
Finished Jun 28 04:32:35 PM PDT 24
Peak memory 211780 kb
Host smart-2d9189c9-362d-4e66-89ed-bc643dbedabe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052835167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.4052835167
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2185617951
Short name T402
Test name
Test status
Simulation time 8061107222 ps
CPU time 31 seconds
Started Jun 28 04:32:22 PM PDT 24
Finished Jun 28 04:32:53 PM PDT 24
Peak memory 217824 kb
Host smart-0b1c0239-2eb2-4350-817d-8785ab41a70a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185617951 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2185617951
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2528498569
Short name T405
Test name
Test status
Simulation time 905524575 ps
CPU time 13.85 seconds
Started Jun 28 04:32:29 PM PDT 24
Finished Jun 28 04:32:44 PM PDT 24
Peak memory 210516 kb
Host smart-66a4811e-40cf-4477-98ba-a04ffc6c1e8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528498569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2528498569
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.591211151
Short name T440
Test name
Test status
Simulation time 21527059082 ps
CPU time 27.72 seconds
Started Jun 28 04:32:31 PM PDT 24
Finished Jun 28 04:33:00 PM PDT 24
Peak memory 210520 kb
Host smart-7dcf6bb5-bf29-4c48-8ba1-86462b60caee
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591211151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.591211151
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1632960077
Short name T374
Test name
Test status
Simulation time 47536521438 ps
CPU time 23.9 seconds
Started Jun 28 04:32:13 PM PDT 24
Finished Jun 28 04:32:37 PM PDT 24
Peak memory 211020 kb
Host smart-f53104e1-6d1d-435e-afb0-79c9557cec7a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632960077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1632960077
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2197020115
Short name T98
Test name
Test status
Simulation time 4567990899 ps
CPU time 62.4 seconds
Started Jun 28 04:32:20 PM PDT 24
Finished Jun 28 04:33:23 PM PDT 24
Peak memory 214024 kb
Host smart-b041542f-fd18-4f10-a29b-d1d466c20fb4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197020115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2197020115
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3479477037
Short name T397
Test name
Test status
Simulation time 4804881541 ps
CPU time 21.81 seconds
Started Jun 28 04:32:22 PM PDT 24
Finished Jun 28 04:32:44 PM PDT 24
Peak memory 212688 kb
Host smart-9cfbf330-8a99-4ab1-9c2e-609b38b1479e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479477037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3479477037
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2483054082
Short name T448
Test name
Test status
Simulation time 3669435248 ps
CPU time 30.68 seconds
Started Jun 28 04:32:38 PM PDT 24
Finished Jun 28 04:33:10 PM PDT 24
Peak memory 218132 kb
Host smart-724ac4ed-39cd-4c66-b272-c214357b6bc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483054082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2483054082
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2884502072
Short name T85
Test name
Test status
Simulation time 15460507851 ps
CPU time 29.71 seconds
Started Jun 28 04:32:28 PM PDT 24
Finished Jun 28 04:32:58 PM PDT 24
Peak memory 211740 kb
Host smart-12091ba4-7d7c-4f76-8411-76bb15dc7e56
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884502072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2884502072
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3735820877
Short name T106
Test name
Test status
Simulation time 42674513648 ps
CPU time 23.65 seconds
Started Jun 28 04:32:32 PM PDT 24
Finished Jun 28 04:32:56 PM PDT 24
Peak memory 210716 kb
Host smart-94013e63-3b6e-4fbc-a6be-fb4eee824249
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735820877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3735820877
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2942768044
Short name T433
Test name
Test status
Simulation time 25886113255 ps
CPU time 35.26 seconds
Started Jun 28 04:32:18 PM PDT 24
Finished Jun 28 04:32:54 PM PDT 24
Peak memory 212220 kb
Host smart-b973a7a5-912e-4f74-9d4a-102baa520610
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942768044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2942768044
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2747142827
Short name T411
Test name
Test status
Simulation time 190571518 ps
CPU time 9.21 seconds
Started Jun 28 04:32:26 PM PDT 24
Finished Jun 28 04:32:36 PM PDT 24
Peak memory 216548 kb
Host smart-9781bc5c-adca-4416-825a-5ea762dba60d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747142827 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2747142827
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2624471050
Short name T404
Test name
Test status
Simulation time 869661284 ps
CPU time 8.62 seconds
Started Jun 28 04:32:31 PM PDT 24
Finished Jun 28 04:32:40 PM PDT 24
Peak memory 210516 kb
Host smart-2281f9b0-7de1-44ee-b251-35adf81f27cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624471050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2624471050
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2783220175
Short name T436
Test name
Test status
Simulation time 260681808 ps
CPU time 9.89 seconds
Started Jun 28 04:32:32 PM PDT 24
Finished Jun 28 04:32:42 PM PDT 24
Peak memory 210220 kb
Host smart-6665bc21-82ef-4dbc-a455-200112844eca
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783220175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2783220175
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1325356981
Short name T362
Test name
Test status
Simulation time 10969409756 ps
CPU time 22.1 seconds
Started Jun 28 04:32:33 PM PDT 24
Finished Jun 28 04:32:56 PM PDT 24
Peak memory 210720 kb
Host smart-709845c3-56f3-4f69-8b93-304cfe51f357
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325356981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1325356981
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2055826199
Short name T92
Test name
Test status
Simulation time 120594208050 ps
CPU time 132.94 seconds
Started Jun 28 04:32:29 PM PDT 24
Finished Jun 28 04:34:42 PM PDT 24
Peak memory 215028 kb
Host smart-299c24f5-50ad-45ab-b657-59e458223978
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055826199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2055826199
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.139522183
Short name T383
Test name
Test status
Simulation time 1791310584 ps
CPU time 18.05 seconds
Started Jun 28 04:32:12 PM PDT 24
Finished Jun 28 04:32:31 PM PDT 24
Peak memory 211128 kb
Host smart-d8c5bdb0-3560-4b89-a124-6d31e80e9edc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139522183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.139522183
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3654481069
Short name T447
Test name
Test status
Simulation time 1933328249 ps
CPU time 19.42 seconds
Started Jun 28 04:32:29 PM PDT 24
Finished Jun 28 04:32:49 PM PDT 24
Peak memory 218404 kb
Host smart-36b14fcc-203a-404d-8914-384f1e9d3382
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654481069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3654481069
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4187788154
Short name T114
Test name
Test status
Simulation time 443485664 ps
CPU time 78.9 seconds
Started Jun 28 04:32:30 PM PDT 24
Finished Jun 28 04:33:50 PM PDT 24
Peak memory 213248 kb
Host smart-afc7e342-3d23-4329-bd10-075d65a9c859
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187788154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.4187788154
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2148570757
Short name T72
Test name
Test status
Simulation time 9262637229 ps
CPU time 20.1 seconds
Started Jun 28 04:32:31 PM PDT 24
Finished Jun 28 04:32:52 PM PDT 24
Peak memory 210588 kb
Host smart-051f290f-412b-46b1-88b7-70a8b39008e8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148570757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2148570757
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.44011730
Short name T103
Test name
Test status
Simulation time 7843758325 ps
CPU time 19.12 seconds
Started Jun 28 04:32:34 PM PDT 24
Finished Jun 28 04:32:55 PM PDT 24
Peak memory 211552 kb
Host smart-7808ed1a-84d1-4064-9ee0-fb4995c41b12
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44011730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_ba
sh.44011730
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2460082686
Short name T97
Test name
Test status
Simulation time 3860114253 ps
CPU time 33.6 seconds
Started Jun 28 04:32:24 PM PDT 24
Finished Jun 28 04:32:59 PM PDT 24
Peak memory 211940 kb
Host smart-c1df568d-20ec-4f25-b9d7-000c6122f1ce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460082686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2460082686
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.217957050
Short name T430
Test name
Test status
Simulation time 270484435 ps
CPU time 10.45 seconds
Started Jun 28 04:32:33 PM PDT 24
Finished Jun 28 04:32:44 PM PDT 24
Peak memory 216072 kb
Host smart-059dd6aa-e6a7-48eb-91f9-6f7d4c05e9f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217957050 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.217957050
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2683294225
Short name T425
Test name
Test status
Simulation time 13437756440 ps
CPU time 26.09 seconds
Started Jun 28 04:32:34 PM PDT 24
Finished Jun 28 04:33:02 PM PDT 24
Peak memory 212284 kb
Host smart-35d47c22-6dca-4d59-b650-adedfc0aaeec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683294225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2683294225
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1603247867
Short name T394
Test name
Test status
Simulation time 167446556 ps
CPU time 8.06 seconds
Started Jun 28 04:32:35 PM PDT 24
Finished Jun 28 04:32:45 PM PDT 24
Peak memory 210408 kb
Host smart-91bb82e6-621d-4443-80a4-fdd32315e072
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603247867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1603247867
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3757869749
Short name T360
Test name
Test status
Simulation time 10867107960 ps
CPU time 25.41 seconds
Started Jun 28 04:32:24 PM PDT 24
Finished Jun 28 04:32:51 PM PDT 24
Peak memory 210712 kb
Host smart-959be6dc-e9ff-4864-8781-e72cbcd4c731
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757869749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3757869749
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3904045729
Short name T90
Test name
Test status
Simulation time 47898596839 ps
CPU time 104.16 seconds
Started Jun 28 04:32:21 PM PDT 24
Finished Jun 28 04:34:06 PM PDT 24
Peak memory 214508 kb
Host smart-47bf04e9-7438-47ca-8512-a5df1a7f0f40
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904045729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3904045729
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1914553314
Short name T449
Test name
Test status
Simulation time 2710815933 ps
CPU time 24.97 seconds
Started Jun 28 04:32:30 PM PDT 24
Finished Jun 28 04:32:55 PM PDT 24
Peak memory 212384 kb
Host smart-2f2c5e5d-cc7c-411c-9065-3543ad3bd8b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914553314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1914553314
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1850369236
Short name T412
Test name
Test status
Simulation time 687854969 ps
CPU time 10.82 seconds
Started Jun 28 04:32:17 PM PDT 24
Finished Jun 28 04:32:29 PM PDT 24
Peak memory 217228 kb
Host smart-f8dfda6a-3d7b-4e2e-9072-e8a26ed973e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850369236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1850369236
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2169532525
Short name T62
Test name
Test status
Simulation time 4136050478 ps
CPU time 176.04 seconds
Started Jun 28 04:32:23 PM PDT 24
Finished Jun 28 04:35:20 PM PDT 24
Peak memory 213912 kb
Host smart-36dc5ac1-e398-4cf6-a1cd-d2bae1380816
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169532525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2169532525
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4038888558
Short name T370
Test name
Test status
Simulation time 14059147245 ps
CPU time 30.12 seconds
Started Jun 28 04:32:38 PM PDT 24
Finished Jun 28 04:33:10 PM PDT 24
Peak memory 218352 kb
Host smart-3070de82-309c-46b3-912b-cd90c5ff9761
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038888558 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.4038888558
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1788979407
Short name T428
Test name
Test status
Simulation time 2304837027 ps
CPU time 12.43 seconds
Started Jun 28 04:32:36 PM PDT 24
Finished Jun 28 04:32:50 PM PDT 24
Peak memory 210944 kb
Host smart-c813edc8-8919-4842-b3bd-fdd5722df6ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788979407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1788979407
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2683204970
Short name T70
Test name
Test status
Simulation time 689949558 ps
CPU time 38.41 seconds
Started Jun 28 04:32:34 PM PDT 24
Finished Jun 28 04:33:14 PM PDT 24
Peak memory 214128 kb
Host smart-192f2ae5-b220-46d5-9c3c-29a57bc418f9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683204970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2683204970
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.595013250
Short name T65
Test name
Test status
Simulation time 1889784787 ps
CPU time 19.62 seconds
Started Jun 28 04:32:28 PM PDT 24
Finished Jun 28 04:32:48 PM PDT 24
Peak memory 211428 kb
Host smart-34d78aab-14b2-47dd-8200-61cecce65b80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595013250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.595013250
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3175267861
Short name T363
Test name
Test status
Simulation time 4535421934 ps
CPU time 25.29 seconds
Started Jun 28 04:32:27 PM PDT 24
Finished Jun 28 04:32:53 PM PDT 24
Peak memory 217624 kb
Host smart-4ee5929b-4342-49fa-91a4-747eb6901de2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175267861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3175267861
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1411682713
Short name T443
Test name
Test status
Simulation time 15974168381 ps
CPU time 104.46 seconds
Started Jun 28 04:32:35 PM PDT 24
Finished Jun 28 04:34:23 PM PDT 24
Peak memory 213444 kb
Host smart-c5dd6e09-53ae-4db5-a0ee-b1301726ae34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411682713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1411682713
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2602720724
Short name T366
Test name
Test status
Simulation time 373240091 ps
CPU time 9.34 seconds
Started Jun 28 04:32:26 PM PDT 24
Finished Jun 28 04:32:35 PM PDT 24
Peak memory 217268 kb
Host smart-29829fbf-a8fe-4106-bc9f-e14c29f9d047
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602720724 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2602720724
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2268180061
Short name T391
Test name
Test status
Simulation time 6879812437 ps
CPU time 18.96 seconds
Started Jun 28 04:32:25 PM PDT 24
Finished Jun 28 04:32:45 PM PDT 24
Peak memory 212244 kb
Host smart-ec8f4351-b911-4b83-a9d5-43915827b93d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268180061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2268180061
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3239595392
Short name T75
Test name
Test status
Simulation time 19527902293 ps
CPU time 113.66 seconds
Started Jun 28 04:32:32 PM PDT 24
Finished Jun 28 04:34:26 PM PDT 24
Peak memory 215036 kb
Host smart-8114b769-5bcd-471b-bb9d-1d48a01fadbf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239595392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3239595392
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3193915975
Short name T102
Test name
Test status
Simulation time 2333119331 ps
CPU time 21.93 seconds
Started Jun 28 04:32:33 PM PDT 24
Finished Jun 28 04:32:56 PM PDT 24
Peak memory 212320 kb
Host smart-2ec70fba-caae-42a1-a7ed-9fe19b4032a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193915975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3193915975
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1608492214
Short name T438
Test name
Test status
Simulation time 358173831 ps
CPU time 13.66 seconds
Started Jun 28 04:32:33 PM PDT 24
Finished Jun 28 04:32:48 PM PDT 24
Peak memory 217484 kb
Host smart-3d7b8c49-12ca-47f7-a593-47a5f3c828e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608492214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1608492214
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.281894587
Short name T116
Test name
Test status
Simulation time 907540176 ps
CPU time 81.95 seconds
Started Jun 28 04:32:42 PM PDT 24
Finished Jun 28 04:34:05 PM PDT 24
Peak memory 213732 kb
Host smart-7390ae92-30cb-44db-9b7e-2177d4a00153
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281894587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.281894587
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4023911466
Short name T58
Test name
Test status
Simulation time 359144150 ps
CPU time 8.99 seconds
Started Jun 28 04:32:34 PM PDT 24
Finished Jun 28 04:32:44 PM PDT 24
Peak memory 216528 kb
Host smart-33db44e1-4f33-453e-9a55-d387643f6188
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023911466 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.4023911466
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1745383196
Short name T93
Test name
Test status
Simulation time 7542961187 ps
CPU time 29.29 seconds
Started Jun 28 04:32:36 PM PDT 24
Finished Jun 28 04:33:06 PM PDT 24
Peak memory 211960 kb
Host smart-1917956a-4ca7-43b3-956d-19c77a154df8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745383196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1745383196
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.878650070
Short name T87
Test name
Test status
Simulation time 13124001467 ps
CPU time 116.48 seconds
Started Jun 28 04:32:41 PM PDT 24
Finished Jun 28 04:34:38 PM PDT 24
Peak memory 213732 kb
Host smart-a4124d0b-35ac-46f3-946d-c2217ead058f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878650070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.878650070
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1002596311
Short name T415
Test name
Test status
Simulation time 19629904496 ps
CPU time 28.21 seconds
Started Jun 28 04:32:34 PM PDT 24
Finished Jun 28 04:33:03 PM PDT 24
Peak memory 212508 kb
Host smart-9650a956-4133-4062-b72d-a04bc70dd884
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002596311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1002596311
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.468902524
Short name T418
Test name
Test status
Simulation time 10631986467 ps
CPU time 27.08 seconds
Started Jun 28 04:32:35 PM PDT 24
Finished Jun 28 04:33:04 PM PDT 24
Peak memory 217216 kb
Host smart-3212ee2a-546c-4cca-808f-185612bcf23e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468902524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.468902524
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.727344040
Short name T429
Test name
Test status
Simulation time 7673156511 ps
CPU time 93.9 seconds
Started Jun 28 04:32:28 PM PDT 24
Finished Jun 28 04:34:03 PM PDT 24
Peak memory 213896 kb
Host smart-6fe5cdd8-5049-4b99-a5c4-0d48a7308526
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727344040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.727344040
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4027278117
Short name T421
Test name
Test status
Simulation time 11924077060 ps
CPU time 29.74 seconds
Started Jun 28 04:32:44 PM PDT 24
Finished Jun 28 04:33:15 PM PDT 24
Peak memory 216800 kb
Host smart-4b4fd394-bd7a-4c3b-a782-80bd0fe08234
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027278117 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.4027278117
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.200854164
Short name T379
Test name
Test status
Simulation time 171169865 ps
CPU time 8.34 seconds
Started Jun 28 04:32:30 PM PDT 24
Finished Jun 28 04:32:39 PM PDT 24
Peak memory 210656 kb
Host smart-51ec49f0-c42d-49b9-abcd-469df673fd28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200854164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.200854164
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3854987867
Short name T94
Test name
Test status
Simulation time 90621104606 ps
CPU time 188.17 seconds
Started Jun 28 04:32:31 PM PDT 24
Finished Jun 28 04:35:41 PM PDT 24
Peak memory 214748 kb
Host smart-a67ec37a-b482-4a86-ba35-dddccb3c6f60
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854987867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3854987867
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.4236929652
Short name T382
Test name
Test status
Simulation time 5798507924 ps
CPU time 16.92 seconds
Started Jun 28 04:32:35 PM PDT 24
Finished Jun 28 04:32:53 PM PDT 24
Peak memory 211552 kb
Host smart-0595689c-b042-4804-a4c5-d3602a031506
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236929652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.4236929652
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2728821796
Short name T393
Test name
Test status
Simulation time 11591831384 ps
CPU time 30.82 seconds
Started Jun 28 04:32:29 PM PDT 24
Finished Jun 28 04:33:01 PM PDT 24
Peak memory 218876 kb
Host smart-0a41d008-04eb-4317-82ac-082b9bd502af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728821796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2728821796
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.63387857
Short name T452
Test name
Test status
Simulation time 1369972658 ps
CPU time 87.95 seconds
Started Jun 28 04:32:25 PM PDT 24
Finished Jun 28 04:33:54 PM PDT 24
Peak memory 213620 kb
Host smart-ca7639e8-49ad-41d8-adf6-2f7e1c6d54c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63387857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_intg
_err.63387857
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.675956026
Short name T387
Test name
Test status
Simulation time 29803102902 ps
CPU time 19.09 seconds
Started Jun 28 04:32:36 PM PDT 24
Finished Jun 28 04:32:57 PM PDT 24
Peak memory 218216 kb
Host smart-ea72ee92-db33-4eb7-9884-f559979d5769
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675956026 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.675956026
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3772050857
Short name T104
Test name
Test status
Simulation time 2044844010 ps
CPU time 11.55 seconds
Started Jun 28 04:32:30 PM PDT 24
Finished Jun 28 04:32:42 PM PDT 24
Peak memory 210584 kb
Host smart-8cde7bf7-7f97-4d47-ac51-ab4d57c26742
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772050857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3772050857
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2674486373
Short name T451
Test name
Test status
Simulation time 86086694549 ps
CPU time 180.99 seconds
Started Jun 28 04:32:26 PM PDT 24
Finished Jun 28 04:35:28 PM PDT 24
Peak memory 214856 kb
Host smart-cf7be0b2-24d5-4724-829e-b18ae68401de
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674486373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2674486373
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.239345539
Short name T76
Test name
Test status
Simulation time 616649585 ps
CPU time 16.25 seconds
Started Jun 28 04:32:33 PM PDT 24
Finished Jun 28 04:32:50 PM PDT 24
Peak memory 212544 kb
Host smart-cc557df0-5211-4e33-992e-f5888d969018
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239345539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.239345539
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.627210694
Short name T364
Test name
Test status
Simulation time 436687865 ps
CPU time 13.19 seconds
Started Jun 28 04:32:39 PM PDT 24
Finished Jun 28 04:32:53 PM PDT 24
Peak memory 217320 kb
Host smart-7087d4e2-a8c0-42dc-8d9c-272fa4d53b58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627210694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.627210694
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3449235512
Short name T422
Test name
Test status
Simulation time 17695913552 ps
CPU time 167.06 seconds
Started Jun 28 04:32:31 PM PDT 24
Finished Jun 28 04:35:19 PM PDT 24
Peak memory 214124 kb
Host smart-a3ea1d5d-87a7-4e87-b15d-3c19b97ea18c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449235512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3449235512
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1243109921
Short name T283
Test name
Test status
Simulation time 7172103424 ps
CPU time 27.5 seconds
Started Jun 28 04:32:48 PM PDT 24
Finished Jun 28 04:33:17 PM PDT 24
Peak memory 217356 kb
Host smart-5cefdc23-6c64-4cf6-b0c8-af65a0c80cc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243109921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1243109921
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2545321376
Short name T346
Test name
Test status
Simulation time 36529389865 ps
CPU time 411.16 seconds
Started Jun 28 04:32:43 PM PDT 24
Finished Jun 28 04:39:35 PM PDT 24
Peak memory 233808 kb
Host smart-b84a0fec-c408-4557-b013-dbeaf09b8548
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545321376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2545321376
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3517962188
Short name T207
Test name
Test status
Simulation time 17178878649 ps
CPU time 43.21 seconds
Started Jun 28 04:32:37 PM PDT 24
Finished Jun 28 04:33:21 PM PDT 24
Peak memory 219240 kb
Host smart-dc765a2a-180a-4259-a24e-0c908d4ed3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517962188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3517962188
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3670769569
Short name T198
Test name
Test status
Simulation time 2597462870 ps
CPU time 24.46 seconds
Started Jun 28 04:32:38 PM PDT 24
Finished Jun 28 04:33:03 PM PDT 24
Peak memory 217604 kb
Host smart-fe3f88cc-834e-42ec-8cd4-ac71c9a2050c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3670769569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3670769569
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.4279496967
Short name T14
Test name
Test status
Simulation time 4454695721 ps
CPU time 43.99 seconds
Started Jun 28 04:32:57 PM PDT 24
Finished Jun 28 04:33:42 PM PDT 24
Peak memory 216604 kb
Host smart-d00b3ef2-3e80-40f3-8ddb-419e86d136bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279496967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.4279496967
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3079355212
Short name T291
Test name
Test status
Simulation time 14356553366 ps
CPU time 60.91 seconds
Started Jun 28 04:32:48 PM PDT 24
Finished Jun 28 04:33:50 PM PDT 24
Peak memory 216748 kb
Host smart-9dcc0a95-8b2f-4a18-be40-5e69f34d41ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079355212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3079355212
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.850973350
Short name T290
Test name
Test status
Simulation time 2350956936 ps
CPU time 8.32 seconds
Started Jun 28 04:32:47 PM PDT 24
Finished Jun 28 04:32:55 PM PDT 24
Peak memory 217080 kb
Host smart-3e9afd7a-5f39-4fbe-a4f6-01c41bf5ea9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850973350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.850973350
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2779873888
Short name T54
Test name
Test status
Simulation time 119523916283 ps
CPU time 260.9 seconds
Started Jun 28 04:32:49 PM PDT 24
Finished Jun 28 04:37:11 PM PDT 24
Peak memory 239556 kb
Host smart-852ce6d9-b1b3-4124-99bc-daaf73d18a0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779873888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2779873888
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3911617672
Short name T156
Test name
Test status
Simulation time 1502050997 ps
CPU time 19.14 seconds
Started Jun 28 04:32:37 PM PDT 24
Finished Jun 28 04:32:57 PM PDT 24
Peak memory 219060 kb
Host smart-9f6fb5e4-8eae-4cec-9940-1f0f5eb6ee6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911617672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3911617672
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1662397458
Short name T183
Test name
Test status
Simulation time 5861617945 ps
CPU time 28.81 seconds
Started Jun 28 04:32:51 PM PDT 24
Finished Jun 28 04:33:21 PM PDT 24
Peak memory 219248 kb
Host smart-c6ebe11a-dda1-4bd2-9e09-4c7a42de3cd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1662397458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1662397458
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3136750784
Short name T310
Test name
Test status
Simulation time 1380243296 ps
CPU time 26.5 seconds
Started Jun 28 04:32:42 PM PDT 24
Finished Jun 28 04:33:09 PM PDT 24
Peak memory 216484 kb
Host smart-4af63c6d-4d22-4791-a485-483bf090a1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136750784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3136750784
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.439305876
Short name T175
Test name
Test status
Simulation time 21465635025 ps
CPU time 62.67 seconds
Started Jun 28 04:32:36 PM PDT 24
Finished Jun 28 04:33:40 PM PDT 24
Peak memory 216584 kb
Host smart-b200761c-6d14-4737-9ef5-89c149c0180f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439305876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.439305876
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.41266846
Short name T26
Test name
Test status
Simulation time 7559215057 ps
CPU time 29.95 seconds
Started Jun 28 04:33:01 PM PDT 24
Finished Jun 28 04:33:35 PM PDT 24
Peak memory 217416 kb
Host smart-062ee946-8fe0-44d3-ae45-94b46e01930a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41266846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.41266846
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3761171452
Short name T314
Test name
Test status
Simulation time 87844640856 ps
CPU time 854.52 seconds
Started Jun 28 04:32:59 PM PDT 24
Finished Jun 28 04:47:16 PM PDT 24
Peak memory 236076 kb
Host smart-5dd2c51d-1ffb-43ed-81c2-41578adaa107
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761171452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3761171452
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3923672576
Short name T259
Test name
Test status
Simulation time 342855586 ps
CPU time 19.37 seconds
Started Jun 28 04:33:14 PM PDT 24
Finished Jun 28 04:33:35 PM PDT 24
Peak memory 219200 kb
Host smart-6669d3dd-ca97-41db-908f-f842ab9b5983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923672576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3923672576
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.680115717
Short name T236
Test name
Test status
Simulation time 44591329384 ps
CPU time 28.36 seconds
Started Jun 28 04:32:45 PM PDT 24
Finished Jun 28 04:33:14 PM PDT 24
Peak memory 219232 kb
Host smart-49003458-29fd-4ef2-99c2-5827ce40d85a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=680115717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.680115717
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1113267900
Short name T309
Test name
Test status
Simulation time 5377077323 ps
CPU time 36.31 seconds
Started Jun 28 04:33:07 PM PDT 24
Finished Jun 28 04:33:47 PM PDT 24
Peak memory 216336 kb
Host smart-229a286f-e47c-49f9-8dbb-85e5f7a43564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113267900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1113267900
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.4072456
Short name T82
Test name
Test status
Simulation time 5198393714 ps
CPU time 55.25 seconds
Started Jun 28 04:33:01 PM PDT 24
Finished Jun 28 04:34:00 PM PDT 24
Peak memory 219004 kb
Host smart-d7404d3d-aae5-4520-a713-258455c72633
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.rom_ctrl_stress_all.4072456
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1738177051
Short name T295
Test name
Test status
Simulation time 11883262473 ps
CPU time 27.68 seconds
Started Jun 28 04:32:43 PM PDT 24
Finished Jun 28 04:33:11 PM PDT 24
Peak memory 217352 kb
Host smart-164cf4cc-ce18-4db4-9a4d-25543284c396
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738177051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1738177051
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.56154265
Short name T201
Test name
Test status
Simulation time 21527415929 ps
CPU time 348.1 seconds
Started Jun 28 04:33:00 PM PDT 24
Finished Jun 28 04:38:50 PM PDT 24
Peak memory 235080 kb
Host smart-f5bceaf3-bb1a-4274-aa5e-6a9eeb3b69b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56154265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_co
rrupt_sig_fatal_chk.56154265
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3890259303
Short name T215
Test name
Test status
Simulation time 16305438116 ps
CPU time 45.44 seconds
Started Jun 28 04:32:56 PM PDT 24
Finished Jun 28 04:33:43 PM PDT 24
Peak memory 219336 kb
Host smart-94ddd467-f3fa-4056-8106-487cfae816e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890259303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3890259303
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1122026052
Short name T34
Test name
Test status
Simulation time 871551908 ps
CPU time 10.46 seconds
Started Jun 28 04:33:08 PM PDT 24
Finished Jun 28 04:33:22 PM PDT 24
Peak memory 219176 kb
Host smart-58f3bcb4-d7af-43c6-bf26-d46a07acd8a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1122026052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1122026052
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2193517335
Short name T229
Test name
Test status
Simulation time 30616317659 ps
CPU time 67.45 seconds
Started Jun 28 04:32:59 PM PDT 24
Finished Jun 28 04:34:08 PM PDT 24
Peak memory 215248 kb
Host smart-705f05a6-174a-4cf6-a777-89275c56539d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193517335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2193517335
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3669017447
Short name T265
Test name
Test status
Simulation time 2556150016 ps
CPU time 37.82 seconds
Started Jun 28 04:32:56 PM PDT 24
Finished Jun 28 04:33:36 PM PDT 24
Peak memory 219312 kb
Host smart-1b3bd51b-995a-40d4-a079-fdf8b9e23038
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669017447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3669017447
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3665588223
Short name T173
Test name
Test status
Simulation time 688398314 ps
CPU time 8.14 seconds
Started Jun 28 04:32:40 PM PDT 24
Finished Jun 28 04:32:49 PM PDT 24
Peak memory 216908 kb
Host smart-1744206c-97df-4a58-8347-f4616e5851b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665588223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3665588223
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.162925193
Short name T242
Test name
Test status
Simulation time 749091689944 ps
CPU time 693.69 seconds
Started Jun 28 04:33:11 PM PDT 24
Finished Jun 28 04:44:47 PM PDT 24
Peak memory 234408 kb
Host smart-c8f55a72-0f80-4ac2-a1d8-b8b4f796f066
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162925193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.162925193
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2334498147
Short name T359
Test name
Test status
Simulation time 4103875101 ps
CPU time 31.98 seconds
Started Jun 28 04:32:55 PM PDT 24
Finished Jun 28 04:33:27 PM PDT 24
Peak memory 211228 kb
Host smart-8b4f6c63-e016-4745-9532-f8292658991f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2334498147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2334498147
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3018478192
Short name T161
Test name
Test status
Simulation time 33520658662 ps
CPU time 64.71 seconds
Started Jun 28 04:32:46 PM PDT 24
Finished Jun 28 04:33:51 PM PDT 24
Peak memory 216444 kb
Host smart-6c276b07-441e-44fc-bb3c-d04b861cfc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018478192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3018478192
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2636805360
Short name T191
Test name
Test status
Simulation time 5691956308 ps
CPU time 16.09 seconds
Started Jun 28 04:32:45 PM PDT 24
Finished Jun 28 04:33:02 PM PDT 24
Peak memory 217408 kb
Host smart-b3f68f4e-2fbb-45a7-ad46-14a9766f8b94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636805360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2636805360
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3340421228
Short name T300
Test name
Test status
Simulation time 4633351991 ps
CPU time 167.62 seconds
Started Jun 28 04:32:50 PM PDT 24
Finished Jun 28 04:35:39 PM PDT 24
Peak memory 233808 kb
Host smart-3dbfca12-9dbd-4aa2-925f-92728e134d2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340421228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3340421228
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.248945947
Short name T345
Test name
Test status
Simulation time 674844797 ps
CPU time 19.3 seconds
Started Jun 28 04:32:47 PM PDT 24
Finished Jun 28 04:33:08 PM PDT 24
Peak memory 219176 kb
Host smart-ecc98dd7-cb25-4785-93ca-f4b6612f8bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248945947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.248945947
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.393031829
Short name T273
Test name
Test status
Simulation time 4970193686 ps
CPU time 23.23 seconds
Started Jun 28 04:32:55 PM PDT 24
Finished Jun 28 04:33:19 PM PDT 24
Peak memory 219232 kb
Host smart-34007735-d8ba-45d3-b8ba-741d4352c6d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=393031829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.393031829
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.544903373
Short name T223
Test name
Test status
Simulation time 19289444992 ps
CPU time 29.73 seconds
Started Jun 28 04:33:08 PM PDT 24
Finished Jun 28 04:33:41 PM PDT 24
Peak memory 216088 kb
Host smart-0fb295e2-03a9-4924-baa3-89f8577bbc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544903373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.544903373
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1951665172
Short name T213
Test name
Test status
Simulation time 566228653 ps
CPU time 33.5 seconds
Started Jun 28 04:33:00 PM PDT 24
Finished Jun 28 04:33:36 PM PDT 24
Peak memory 219264 kb
Host smart-a4db8be9-2bdf-424d-af5a-8f178896e5a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951665172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1951665172
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3471861135
Short name T177
Test name
Test status
Simulation time 3363246832 ps
CPU time 27.65 seconds
Started Jun 28 04:33:03 PM PDT 24
Finished Jun 28 04:33:34 PM PDT 24
Peak memory 217192 kb
Host smart-67c29a9b-a035-4530-9d9b-c21eb7524abd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471861135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3471861135
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1708750913
Short name T40
Test name
Test status
Simulation time 42361770643 ps
CPU time 432.17 seconds
Started Jun 28 04:33:05 PM PDT 24
Finished Jun 28 04:40:21 PM PDT 24
Peak memory 234136 kb
Host smart-9ac39c0d-2bee-4276-a17e-711856742da9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708750913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1708750913
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.806514212
Short name T330
Test name
Test status
Simulation time 32797432406 ps
CPU time 37.61 seconds
Started Jun 28 04:32:50 PM PDT 24
Finished Jun 28 04:33:28 PM PDT 24
Peak memory 219176 kb
Host smart-337ece08-4123-49f4-b1f0-4fc12fefd633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806514212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.806514212
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3818915493
Short name T248
Test name
Test status
Simulation time 178079489 ps
CPU time 11.01 seconds
Started Jun 28 04:32:52 PM PDT 24
Finished Jun 28 04:33:04 PM PDT 24
Peak memory 219188 kb
Host smart-47516ecd-a187-408b-8cb4-a8cc8677f203
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3818915493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3818915493
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1908739895
Short name T240
Test name
Test status
Simulation time 62521044766 ps
CPU time 68.17 seconds
Started Jun 28 04:33:13 PM PDT 24
Finished Jun 28 04:34:23 PM PDT 24
Peak memory 216320 kb
Host smart-12f96455-ebef-412d-b8d9-987365af363b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908739895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1908739895
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2668960339
Short name T169
Test name
Test status
Simulation time 21533520593 ps
CPU time 57.46 seconds
Started Jun 28 04:33:06 PM PDT 24
Finished Jun 28 04:34:06 PM PDT 24
Peak memory 217184 kb
Host smart-19b15ac6-622c-4930-aa2e-b51937d9bffe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668960339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2668960339
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3801906564
Short name T37
Test name
Test status
Simulation time 2754972341 ps
CPU time 24.5 seconds
Started Jun 28 04:32:48 PM PDT 24
Finished Jun 28 04:33:14 PM PDT 24
Peak memory 218136 kb
Host smart-05301f90-9a60-4b75-8333-1bfc6ea1b577
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801906564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3801906564
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1549128252
Short name T39
Test name
Test status
Simulation time 14053352193 ps
CPU time 337.71 seconds
Started Jun 28 04:33:10 PM PDT 24
Finished Jun 28 04:38:50 PM PDT 24
Peak memory 218532 kb
Host smart-9a5d1b33-eb45-4095-9e26-e69e4b8e7609
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549128252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1549128252
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2160064981
Short name T162
Test name
Test status
Simulation time 371705127 ps
CPU time 10.35 seconds
Started Jun 28 04:33:01 PM PDT 24
Finished Jun 28 04:33:14 PM PDT 24
Peak memory 219200 kb
Host smart-1bb5b0e6-2b3e-4b1f-90c4-e52b473e0166
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2160064981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2160064981
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.4191225674
Short name T311
Test name
Test status
Simulation time 15214235530 ps
CPU time 37.37 seconds
Started Jun 28 04:32:48 PM PDT 24
Finished Jun 28 04:33:27 PM PDT 24
Peak memory 216920 kb
Host smart-fac0cd4d-c608-4ade-b923-8e8dc57e94bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191225674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.4191225674
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.4023387577
Short name T1
Test name
Test status
Simulation time 599744042 ps
CPU time 24.74 seconds
Started Jun 28 04:32:50 PM PDT 24
Finished Jun 28 04:33:16 PM PDT 24
Peak memory 219056 kb
Host smart-2d864c0e-7e01-473b-8baa-d2f8f2c9e0a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023387577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.4023387577
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2063658317
Short name T254
Test name
Test status
Simulation time 599139009 ps
CPU time 12.67 seconds
Started Jun 28 04:33:07 PM PDT 24
Finished Jun 28 04:33:23 PM PDT 24
Peak memory 217124 kb
Host smart-c7bacbc7-d3af-4cae-96d5-9a78be3daf57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063658317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2063658317
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2223874240
Short name T222
Test name
Test status
Simulation time 21101689333 ps
CPU time 260.48 seconds
Started Jun 28 04:33:06 PM PDT 24
Finished Jun 28 04:37:30 PM PDT 24
Peak memory 233744 kb
Host smart-292d5bed-ec7c-4664-89aa-e9cf32514ca1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223874240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2223874240
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3009747763
Short name T188
Test name
Test status
Simulation time 4032300751 ps
CPU time 42.23 seconds
Started Jun 28 04:33:08 PM PDT 24
Finished Jun 28 04:33:53 PM PDT 24
Peak memory 219260 kb
Host smart-255e136a-43ec-4e92-a73e-b31f14804eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009747763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3009747763
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2065546989
Short name T329
Test name
Test status
Simulation time 5975968749 ps
CPU time 19.11 seconds
Started Jun 28 04:32:45 PM PDT 24
Finished Jun 28 04:33:05 PM PDT 24
Peak memory 219232 kb
Host smart-31313b4c-55a6-4e90-b030-81a086894b29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2065546989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2065546989
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3340332774
Short name T313
Test name
Test status
Simulation time 19893221729 ps
CPU time 51.44 seconds
Started Jun 28 04:32:52 PM PDT 24
Finished Jun 28 04:33:44 PM PDT 24
Peak memory 216536 kb
Host smart-f872f5d1-a097-486f-9f9f-d9e1b6539333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340332774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3340332774
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3306756436
Short name T172
Test name
Test status
Simulation time 31504375332 ps
CPU time 72.48 seconds
Started Jun 28 04:32:59 PM PDT 24
Finished Jun 28 04:34:12 PM PDT 24
Peak memory 217652 kb
Host smart-57ff4305-d4bf-43ec-add9-be86430fce61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306756436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3306756436
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1169849259
Short name T320
Test name
Test status
Simulation time 2054066682 ps
CPU time 20.14 seconds
Started Jun 28 04:33:05 PM PDT 24
Finished Jun 28 04:33:28 PM PDT 24
Peak memory 217032 kb
Host smart-6a1e63e0-79d0-4c1c-b317-741001925dac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169849259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1169849259
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3714382290
Short name T121
Test name
Test status
Simulation time 33628564912 ps
CPU time 283.68 seconds
Started Jun 28 04:33:06 PM PDT 24
Finished Jun 28 04:37:53 PM PDT 24
Peak memory 219408 kb
Host smart-2f4f6c82-307a-4e20-86f6-8812ed430c6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714382290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3714382290
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1419668835
Short name T267
Test name
Test status
Simulation time 20529278881 ps
CPU time 35.93 seconds
Started Jun 28 04:32:48 PM PDT 24
Finished Jun 28 04:33:25 PM PDT 24
Peak memory 219224 kb
Host smart-d1ef2a1a-2bdd-412b-86d5-a5a52fc02ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419668835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1419668835
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.930490219
Short name T304
Test name
Test status
Simulation time 4476549901 ps
CPU time 17.55 seconds
Started Jun 28 04:32:44 PM PDT 24
Finished Jun 28 04:33:03 PM PDT 24
Peak memory 219228 kb
Host smart-1d459f58-f76d-4a90-a3a9-3c10a6e08845
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=930490219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.930490219
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2325010607
Short name T221
Test name
Test status
Simulation time 27661328576 ps
CPU time 59.81 seconds
Started Jun 28 04:33:00 PM PDT 24
Finished Jun 28 04:34:02 PM PDT 24
Peak memory 215936 kb
Host smart-b2ed4f54-732b-40d8-8bfd-93359351cab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325010607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2325010607
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3936643963
Short name T202
Test name
Test status
Simulation time 1242375698 ps
CPU time 20.59 seconds
Started Jun 28 04:33:08 PM PDT 24
Finished Jun 28 04:33:32 PM PDT 24
Peak memory 214664 kb
Host smart-c3f55212-9755-4cb0-b115-2113c5449808
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936643963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3936643963
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.609937152
Short name T233
Test name
Test status
Simulation time 1030559423 ps
CPU time 8.14 seconds
Started Jun 28 04:33:05 PM PDT 24
Finished Jun 28 04:33:16 PM PDT 24
Peak memory 217064 kb
Host smart-d0e6bf26-19c8-4eb8-b03c-83b5f44f8216
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609937152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.609937152
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.191277537
Short name T140
Test name
Test status
Simulation time 175822090455 ps
CPU time 180.89 seconds
Started Jun 28 04:32:57 PM PDT 24
Finished Jun 28 04:35:59 PM PDT 24
Peak memory 228736 kb
Host smart-382dc739-f2de-4a98-a966-d14378adf860
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191277537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.191277537
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2756393830
Short name T298
Test name
Test status
Simulation time 32157508413 ps
CPU time 69.91 seconds
Started Jun 28 04:33:04 PM PDT 24
Finished Jun 28 04:34:17 PM PDT 24
Peak memory 219256 kb
Host smart-1d0dcab2-cef0-4dc2-85e5-f7867cf81ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756393830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2756393830
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2708830900
Short name T107
Test name
Test status
Simulation time 7921469921 ps
CPU time 22.74 seconds
Started Jun 28 04:32:58 PM PDT 24
Finished Jun 28 04:33:21 PM PDT 24
Peak memory 211888 kb
Host smart-c7a6d298-7226-440c-952f-0241bc0dfd2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2708830900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2708830900
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.508688819
Short name T344
Test name
Test status
Simulation time 4292902340 ps
CPU time 20.15 seconds
Started Jun 28 04:33:13 PM PDT 24
Finished Jun 28 04:33:35 PM PDT 24
Peak memory 215960 kb
Host smart-c4b5dc9e-f092-4e90-b40c-8c5ef2f45e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508688819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.508688819
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3660852789
Short name T151
Test name
Test status
Simulation time 28808897116 ps
CPU time 79.42 seconds
Started Jun 28 04:33:00 PM PDT 24
Finished Jun 28 04:34:22 PM PDT 24
Peak memory 216940 kb
Host smart-27e88e05-f62b-4c60-ab5b-660b333d48af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660852789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3660852789
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3848852880
Short name T303
Test name
Test status
Simulation time 3433140063 ps
CPU time 27.88 seconds
Started Jun 28 04:33:07 PM PDT 24
Finished Jun 28 04:33:38 PM PDT 24
Peak memory 217176 kb
Host smart-c45f2eaf-9b35-46dc-b832-802b80ee0aa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848852880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3848852880
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2941354794
Short name T355
Test name
Test status
Simulation time 33552055987 ps
CPU time 466.17 seconds
Started Jun 28 04:32:56 PM PDT 24
Finished Jun 28 04:40:43 PM PDT 24
Peak memory 235520 kb
Host smart-887216d1-d170-4105-a57a-05ed2152acb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941354794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2941354794
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2936197284
Short name T249
Test name
Test status
Simulation time 5420344070 ps
CPU time 48.74 seconds
Started Jun 28 04:33:05 PM PDT 24
Finished Jun 28 04:33:57 PM PDT 24
Peak memory 219260 kb
Host smart-0b08720e-a573-4597-9d94-9f3360940119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936197284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2936197284
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1199615363
Short name T158
Test name
Test status
Simulation time 2766998084 ps
CPU time 15.2 seconds
Started Jun 28 04:32:52 PM PDT 24
Finished Jun 28 04:33:09 PM PDT 24
Peak memory 211744 kb
Host smart-b76649d8-2e3b-4512-9c1d-71f8ae9519af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1199615363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1199615363
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1704461387
Short name T195
Test name
Test status
Simulation time 5535669136 ps
CPU time 61.97 seconds
Started Jun 28 04:32:58 PM PDT 24
Finished Jun 28 04:34:01 PM PDT 24
Peak memory 216024 kb
Host smart-f708b8d9-b287-4bd5-89b0-301af471e5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704461387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1704461387
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3935226585
Short name T244
Test name
Test status
Simulation time 39984133202 ps
CPU time 40.59 seconds
Started Jun 28 04:33:05 PM PDT 24
Finished Jun 28 04:33:49 PM PDT 24
Peak memory 217800 kb
Host smart-0bbdc9a2-cef7-412b-9a17-f54f8d6bc92b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935226585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3935226585
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.549098601
Short name T166
Test name
Test status
Simulation time 3256951175 ps
CPU time 26.3 seconds
Started Jun 28 04:33:00 PM PDT 24
Finished Jun 28 04:33:30 PM PDT 24
Peak memory 217176 kb
Host smart-4d07a1ae-d971-4ea1-b95b-a12e290cee61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549098601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.549098601
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3177576854
Short name T331
Test name
Test status
Simulation time 34150682905 ps
CPU time 178.03 seconds
Started Jun 28 04:32:35 PM PDT 24
Finished Jun 28 04:35:37 PM PDT 24
Peak memory 239900 kb
Host smart-9ba6f909-fdb2-413e-9bf3-6d2fcb9c2637
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177576854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3177576854
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3758743233
Short name T289
Test name
Test status
Simulation time 4305124719 ps
CPU time 45.04 seconds
Started Jun 28 04:33:08 PM PDT 24
Finished Jun 28 04:33:56 PM PDT 24
Peak memory 219260 kb
Host smart-8997ec2d-6ada-4762-8ca7-1336e42e82b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758743233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3758743233
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.105871366
Short name T125
Test name
Test status
Simulation time 1397852878 ps
CPU time 14.95 seconds
Started Jun 28 04:32:38 PM PDT 24
Finished Jun 28 04:32:54 PM PDT 24
Peak memory 218920 kb
Host smart-90af5eb6-2403-4253-804a-0da71d14dfb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=105871366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.105871366
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1501607558
Short name T29
Test name
Test status
Simulation time 11468709996 ps
CPU time 130.75 seconds
Started Jun 28 04:32:37 PM PDT 24
Finished Jun 28 04:34:50 PM PDT 24
Peak memory 237508 kb
Host smart-0eddecca-b4a6-45f4-b526-f6c354fedcc8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501607558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1501607558
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2281412718
Short name T189
Test name
Test status
Simulation time 1728370690 ps
CPU time 33.17 seconds
Started Jun 28 04:32:59 PM PDT 24
Finished Jun 28 04:33:33 PM PDT 24
Peak memory 216168 kb
Host smart-191f91b2-76ff-4885-a022-21e581506ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281412718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2281412718
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3832842506
Short name T348
Test name
Test status
Simulation time 5725600093 ps
CPU time 51.67 seconds
Started Jun 28 04:33:11 PM PDT 24
Finished Jun 28 04:34:05 PM PDT 24
Peak memory 216924 kb
Host smart-645d470c-270d-4643-87ff-84ce5f346d31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832842506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3832842506
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3641669996
Short name T190
Test name
Test status
Simulation time 10393136053 ps
CPU time 22.24 seconds
Started Jun 28 04:33:08 PM PDT 24
Finished Jun 28 04:33:33 PM PDT 24
Peak memory 217472 kb
Host smart-4e926c75-f754-41f9-95b8-380f6997d57a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641669996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3641669996
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3204701882
Short name T357
Test name
Test status
Simulation time 82330371524 ps
CPU time 392.02 seconds
Started Jun 28 04:32:51 PM PDT 24
Finished Jun 28 04:39:25 PM PDT 24
Peak memory 237132 kb
Host smart-d026e3ad-13d0-4f24-99f1-2f7f1336bf92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204701882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3204701882
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2582304211
Short name T180
Test name
Test status
Simulation time 1570586372 ps
CPU time 18.76 seconds
Started Jun 28 04:33:18 PM PDT 24
Finished Jun 28 04:33:39 PM PDT 24
Peak memory 219168 kb
Host smart-439897d5-2e54-4022-ad97-b063620efc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582304211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2582304211
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2004816291
Short name T208
Test name
Test status
Simulation time 13833017280 ps
CPU time 29.53 seconds
Started Jun 28 04:33:02 PM PDT 24
Finished Jun 28 04:33:35 PM PDT 24
Peak memory 218992 kb
Host smart-ad681fb9-f6f1-452c-9cc9-899fe5acfa15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2004816291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2004816291
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2344585992
Short name T323
Test name
Test status
Simulation time 711622060 ps
CPU time 42.71 seconds
Started Jun 28 04:33:04 PM PDT 24
Finished Jun 28 04:33:50 PM PDT 24
Peak memory 219296 kb
Host smart-29dd998f-6d6f-41ee-abce-3dd3c6382953
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344585992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2344585992
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1254351465
Short name T302
Test name
Test status
Simulation time 1794694043 ps
CPU time 18.81 seconds
Started Jun 28 04:32:51 PM PDT 24
Finished Jun 28 04:33:11 PM PDT 24
Peak memory 216792 kb
Host smart-be330c20-523c-47b8-bb7a-d472c93adf7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254351465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1254351465
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3589388688
Short name T261
Test name
Test status
Simulation time 136773743784 ps
CPU time 719.12 seconds
Started Jun 28 04:33:06 PM PDT 24
Finished Jun 28 04:45:09 PM PDT 24
Peak memory 234004 kb
Host smart-fd1c8cc4-4b12-4b09-8332-84a131e71696
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589388688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3589388688
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.349601068
Short name T263
Test name
Test status
Simulation time 2997878683 ps
CPU time 19.42 seconds
Started Jun 28 04:33:07 PM PDT 24
Finished Jun 28 04:33:30 PM PDT 24
Peak memory 219280 kb
Host smart-2853c8df-57b8-45ca-8882-d7275905cf68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349601068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.349601068
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2783657086
Short name T149
Test name
Test status
Simulation time 3336611542 ps
CPU time 27.48 seconds
Started Jun 28 04:33:11 PM PDT 24
Finished Jun 28 04:33:41 PM PDT 24
Peak memory 219000 kb
Host smart-9ab77604-f8cd-40f3-8fbf-ce735900b962
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2783657086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2783657086
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2833478161
Short name T148
Test name
Test status
Simulation time 10012138227 ps
CPU time 33.95 seconds
Started Jun 28 04:33:04 PM PDT 24
Finished Jun 28 04:33:41 PM PDT 24
Peak memory 216060 kb
Host smart-bd5edc13-83a1-4b9e-b49d-d9cbedb00581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833478161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2833478161
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.673982049
Short name T129
Test name
Test status
Simulation time 12217841107 ps
CPU time 91.97 seconds
Started Jun 28 04:32:59 PM PDT 24
Finished Jun 28 04:34:33 PM PDT 24
Peak memory 220008 kb
Host smart-d87e4e20-6a2a-4235-94a4-e2c8606a1b67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673982049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.673982049
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.1957828839
Short name T55
Test name
Test status
Simulation time 16098932032 ps
CPU time 484.52 seconds
Started Jun 28 04:33:02 PM PDT 24
Finished Jun 28 04:41:11 PM PDT 24
Peak memory 228884 kb
Host smart-5e594b87-714f-4902-9dae-ba159ee58be8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957828839 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.1957828839
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1000138332
Short name T257
Test name
Test status
Simulation time 3423982085 ps
CPU time 28.14 seconds
Started Jun 28 04:32:58 PM PDT 24
Finished Jun 28 04:33:28 PM PDT 24
Peak memory 213204 kb
Host smart-a74d3ae3-d369-4be4-8e75-7b1f5444621f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000138332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1000138332
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2855036616
Short name T45
Test name
Test status
Simulation time 101862975097 ps
CPU time 945.68 seconds
Started Jun 28 04:33:09 PM PDT 24
Finished Jun 28 04:48:57 PM PDT 24
Peak memory 237876 kb
Host smart-5b10eef1-eef9-42d0-89e5-3fab862b227c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855036616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2855036616
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2601922442
Short name T36
Test name
Test status
Simulation time 28857621376 ps
CPU time 60.98 seconds
Started Jun 28 04:33:13 PM PDT 24
Finished Jun 28 04:34:16 PM PDT 24
Peak memory 219232 kb
Host smart-66c49dec-7d66-43f0-ba0a-2522c9370a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601922442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2601922442
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2017680604
Short name T318
Test name
Test status
Simulation time 3370539738 ps
CPU time 14.81 seconds
Started Jun 28 04:33:10 PM PDT 24
Finished Jun 28 04:33:27 PM PDT 24
Peak memory 219232 kb
Host smart-3c799dbc-f185-40cd-b860-6da6d2498cdd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2017680604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2017680604
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.756212621
Short name T79
Test name
Test status
Simulation time 1339963078 ps
CPU time 29.73 seconds
Started Jun 28 04:32:38 PM PDT 24
Finished Jun 28 04:33:09 PM PDT 24
Peak memory 215568 kb
Host smart-233dbead-c13a-497c-b370-388eb2536b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756212621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.756212621
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.294282122
Short name T351
Test name
Test status
Simulation time 47909899525 ps
CPU time 85.31 seconds
Started Jun 28 04:33:08 PM PDT 24
Finished Jun 28 04:34:37 PM PDT 24
Peak memory 219244 kb
Host smart-8ccc087d-fea0-4e28-bf87-ec5db9830769
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294282122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.294282122
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.4054968744
Short name T262
Test name
Test status
Simulation time 48119163303 ps
CPU time 456.07 seconds
Started Jun 28 04:32:39 PM PDT 24
Finished Jun 28 04:40:16 PM PDT 24
Peak memory 242008 kb
Host smart-3a193959-dbe4-4329-8ca0-e43636b12e94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054968744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.4054968744
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3781396826
Short name T271
Test name
Test status
Simulation time 1375083958 ps
CPU time 19.29 seconds
Started Jun 28 04:33:10 PM PDT 24
Finished Jun 28 04:33:32 PM PDT 24
Peak memory 219276 kb
Host smart-319795a2-c8dc-4090-9888-1ba4f6d4d28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781396826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3781396826
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3590686155
Short name T256
Test name
Test status
Simulation time 8205483433 ps
CPU time 22.37 seconds
Started Jun 28 04:32:57 PM PDT 24
Finished Jun 28 04:33:21 PM PDT 24
Peak memory 217872 kb
Host smart-fba5237f-680e-4c4b-9ba2-df6cdf93cae7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3590686155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3590686155
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2868412141
Short name T155
Test name
Test status
Simulation time 27489805297 ps
CPU time 58.96 seconds
Started Jun 28 04:33:03 PM PDT 24
Finished Jun 28 04:34:06 PM PDT 24
Peak memory 216648 kb
Host smart-79fb9dde-52a9-4fb4-92ad-807565567229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868412141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2868412141
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3099188334
Short name T340
Test name
Test status
Simulation time 1492658737 ps
CPU time 25.61 seconds
Started Jun 28 04:32:50 PM PDT 24
Finished Jun 28 04:33:16 PM PDT 24
Peak memory 219204 kb
Host smart-1a73e9c7-eba7-46bb-a516-31ea6f8249e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099188334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3099188334
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.318236290
Short name T13
Test name
Test status
Simulation time 36576277419 ps
CPU time 1354.06 seconds
Started Jun 28 04:32:51 PM PDT 24
Finished Jun 28 04:55:26 PM PDT 24
Peak memory 235712 kb
Host smart-81334cfd-22d4-4294-bbf3-2cc286fc09d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318236290 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.318236290
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.574773632
Short name T327
Test name
Test status
Simulation time 7059194711 ps
CPU time 28.75 seconds
Started Jun 28 04:33:16 PM PDT 24
Finished Jun 28 04:33:47 PM PDT 24
Peak memory 213204 kb
Host smart-fc8000f5-d175-4ac3-8b3e-190637e5bc49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574773632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.574773632
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3428150785
Short name T19
Test name
Test status
Simulation time 172869143105 ps
CPU time 467.43 seconds
Started Jun 28 04:33:07 PM PDT 24
Finished Jun 28 04:40:57 PM PDT 24
Peak memory 234312 kb
Host smart-f518c082-b69d-40f2-9330-13126f90e0f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428150785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3428150785
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2351598138
Short name T276
Test name
Test status
Simulation time 15129699201 ps
CPU time 43.83 seconds
Started Jun 28 04:33:06 PM PDT 24
Finished Jun 28 04:33:53 PM PDT 24
Peak memory 219200 kb
Host smart-6833f184-0167-426a-b1c2-e45304a410e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351598138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2351598138
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1961126030
Short name T135
Test name
Test status
Simulation time 26705538980 ps
CPU time 24.64 seconds
Started Jun 28 04:33:00 PM PDT 24
Finished Jun 28 04:33:26 PM PDT 24
Peak memory 219248 kb
Host smart-39e93ecb-7c44-45af-a10f-2dcc4fb544e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1961126030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1961126030
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1555024747
Short name T237
Test name
Test status
Simulation time 27615930235 ps
CPU time 53.66 seconds
Started Jun 28 04:33:06 PM PDT 24
Finished Jun 28 04:34:03 PM PDT 24
Peak memory 217208 kb
Host smart-dfa95771-28f0-44d8-bafb-2e9e5ac7949a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555024747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1555024747
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3170281763
Short name T228
Test name
Test status
Simulation time 32924159826 ps
CPU time 107.33 seconds
Started Jun 28 04:33:10 PM PDT 24
Finished Jun 28 04:35:00 PM PDT 24
Peak memory 221136 kb
Host smart-f9c828df-5f33-4191-8878-f54f742c0f5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170281763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3170281763
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.4284567049
Short name T187
Test name
Test status
Simulation time 2062207532 ps
CPU time 12.39 seconds
Started Jun 28 04:33:03 PM PDT 24
Finished Jun 28 04:33:19 PM PDT 24
Peak memory 217172 kb
Host smart-f19a7b1e-6ddf-4e40-9bd8-def5654e6a2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284567049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.4284567049
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3542406636
Short name T334
Test name
Test status
Simulation time 225811232321 ps
CPU time 490.38 seconds
Started Jun 28 04:32:51 PM PDT 24
Finished Jun 28 04:41:02 PM PDT 24
Peak memory 228312 kb
Host smart-5c766f0f-4a17-44cf-8823-bf9dc8c4d422
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542406636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3542406636
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3656720449
Short name T134
Test name
Test status
Simulation time 661905674 ps
CPU time 19.55 seconds
Started Jun 28 04:33:10 PM PDT 24
Finished Jun 28 04:33:32 PM PDT 24
Peak memory 219196 kb
Host smart-639710c7-8fdb-4800-b379-a1efea7e57a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656720449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3656720449
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2747841174
Short name T30
Test name
Test status
Simulation time 16740155314 ps
CPU time 33.32 seconds
Started Jun 28 04:33:09 PM PDT 24
Finished Jun 28 04:33:46 PM PDT 24
Peak memory 212120 kb
Host smart-4f0ca7ef-f547-4c3e-8ae0-6395a1cb4282
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2747841174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2747841174
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1906798203
Short name T194
Test name
Test status
Simulation time 29402443069 ps
CPU time 66.03 seconds
Started Jun 28 04:33:09 PM PDT 24
Finished Jun 28 04:34:18 PM PDT 24
Peak memory 216168 kb
Host smart-51f5d959-da2f-4023-a98f-d515789b18de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906798203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1906798203
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2599280423
Short name T258
Test name
Test status
Simulation time 207372250 ps
CPU time 21.49 seconds
Started Jun 28 04:33:05 PM PDT 24
Finished Jun 28 04:33:30 PM PDT 24
Peak memory 219160 kb
Host smart-67baf9b8-8785-4353-906a-e3e7c469c43b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599280423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2599280423
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2841224284
Short name T67
Test name
Test status
Simulation time 6354757591 ps
CPU time 26.28 seconds
Started Jun 28 04:33:01 PM PDT 24
Finished Jun 28 04:33:30 PM PDT 24
Peak memory 217464 kb
Host smart-5ca02630-1354-4d12-aefc-d275146398d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841224284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2841224284
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.588534054
Short name T225
Test name
Test status
Simulation time 87449380522 ps
CPU time 435.61 seconds
Started Jun 28 04:33:07 PM PDT 24
Finished Jun 28 04:40:25 PM PDT 24
Peak memory 237624 kb
Host smart-66d3fd96-14ad-4b3b-9c4a-b9f6553841fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588534054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.588534054
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3321414727
Short name T339
Test name
Test status
Simulation time 8029957836 ps
CPU time 64.7 seconds
Started Jun 28 04:32:59 PM PDT 24
Finished Jun 28 04:34:05 PM PDT 24
Peak memory 219080 kb
Host smart-a33aef4f-d578-435e-af43-fb90d8910f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321414727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3321414727
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2995370944
Short name T206
Test name
Test status
Simulation time 16088187180 ps
CPU time 32.48 seconds
Started Jun 28 04:33:12 PM PDT 24
Finished Jun 28 04:33:47 PM PDT 24
Peak memory 219244 kb
Host smart-95a99ede-772e-4f5f-976b-8a28da78a2a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2995370944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2995370944
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.542940844
Short name T239
Test name
Test status
Simulation time 5943619877 ps
CPU time 30.28 seconds
Started Jun 28 04:33:08 PM PDT 24
Finished Jun 28 04:33:42 PM PDT 24
Peak memory 217044 kb
Host smart-fcb96e1e-672e-447b-b0fd-e6df707e7548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542940844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.542940844
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2153246831
Short name T288
Test name
Test status
Simulation time 1983012676 ps
CPU time 28.17 seconds
Started Jun 28 04:32:51 PM PDT 24
Finished Jun 28 04:33:20 PM PDT 24
Peak memory 219048 kb
Host smart-0bc32dbd-826b-46d0-99c6-81f4554505d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153246831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2153246831
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3883625100
Short name T32
Test name
Test status
Simulation time 10580779598 ps
CPU time 25.62 seconds
Started Jun 28 04:32:56 PM PDT 24
Finished Jun 28 04:33:23 PM PDT 24
Peak memory 217464 kb
Host smart-8e1579f1-86af-4955-8e55-bef85cb0994d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883625100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3883625100
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2576024689
Short name T332
Test name
Test status
Simulation time 63666385670 ps
CPU time 702.94 seconds
Started Jun 28 04:33:01 PM PDT 24
Finished Jun 28 04:44:48 PM PDT 24
Peak memory 236192 kb
Host smart-dd908891-d1ba-41a3-9aec-21c337269e73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576024689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2576024689
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2454223102
Short name T50
Test name
Test status
Simulation time 342840286 ps
CPU time 19.43 seconds
Started Jun 28 04:33:02 PM PDT 24
Finished Jun 28 04:33:25 PM PDT 24
Peak memory 219196 kb
Host smart-5e0f720e-6260-4e0c-ab9b-c713ad93dc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454223102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2454223102
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2805806426
Short name T333
Test name
Test status
Simulation time 15266081105 ps
CPU time 32.99 seconds
Started Jun 28 04:33:05 PM PDT 24
Finished Jun 28 04:33:42 PM PDT 24
Peak memory 219592 kb
Host smart-5a07c381-2391-4a17-b342-ce134e5255d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2805806426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2805806426
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2971503273
Short name T284
Test name
Test status
Simulation time 25295977284 ps
CPU time 55.94 seconds
Started Jun 28 04:33:01 PM PDT 24
Finished Jun 28 04:33:59 PM PDT 24
Peak memory 217308 kb
Host smart-0d36a270-8016-4f34-926b-25a6f462128f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971503273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2971503273
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3967966911
Short name T220
Test name
Test status
Simulation time 2924555172 ps
CPU time 44.18 seconds
Started Jun 28 04:33:04 PM PDT 24
Finished Jun 28 04:33:51 PM PDT 24
Peak memory 220004 kb
Host smart-229270f2-7a77-4557-b247-17084289f2d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967966911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3967966911
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.4087621698
Short name T192
Test name
Test status
Simulation time 169062731 ps
CPU time 8.04 seconds
Started Jun 28 04:33:02 PM PDT 24
Finished Jun 28 04:33:13 PM PDT 24
Peak memory 217016 kb
Host smart-b93c6bbf-f70f-4056-a4b7-9fde86bb7b0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087621698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.4087621698
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.4024163405
Short name T214
Test name
Test status
Simulation time 53828477066 ps
CPU time 423.26 seconds
Started Jun 28 04:33:11 PM PDT 24
Finished Jun 28 04:40:17 PM PDT 24
Peak memory 238696 kb
Host smart-332e68b6-29b7-4879-871e-91d73907c278
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024163405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.4024163405
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2258654392
Short name T185
Test name
Test status
Simulation time 23235903048 ps
CPU time 52.89 seconds
Started Jun 28 04:32:58 PM PDT 24
Finished Jun 28 04:33:52 PM PDT 24
Peak memory 219300 kb
Host smart-9365f7b6-fd7b-4f69-8870-27ef3832e5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258654392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2258654392
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2941680216
Short name T356
Test name
Test status
Simulation time 1982320760 ps
CPU time 21.64 seconds
Started Jun 28 04:33:06 PM PDT 24
Finished Jun 28 04:33:31 PM PDT 24
Peak memory 219184 kb
Host smart-d09bfbae-648b-4a4b-970d-4ad05faed420
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2941680216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2941680216
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.336347324
Short name T358
Test name
Test status
Simulation time 726857634 ps
CPU time 33.54 seconds
Started Jun 28 04:33:06 PM PDT 24
Finished Jun 28 04:33:43 PM PDT 24
Peak memory 219536 kb
Host smart-bb45fcd8-f3cd-4f2a-8c82-785fd266d898
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336347324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.rom_ctrl_stress_all.336347324
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1707306379
Short name T56
Test name
Test status
Simulation time 40586803792 ps
CPU time 1673.38 seconds
Started Jun 28 04:32:57 PM PDT 24
Finished Jun 28 05:00:52 PM PDT 24
Peak memory 235712 kb
Host smart-129abe14-2444-4bab-a806-bcab38651d20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707306379 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.1707306379
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.4284993153
Short name T24
Test name
Test status
Simulation time 63787416805 ps
CPU time 28.32 seconds
Started Jun 28 04:33:15 PM PDT 24
Finished Jun 28 04:33:46 PM PDT 24
Peak memory 213192 kb
Host smart-31d3540b-e747-4607-929d-d05f1bad02a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284993153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.4284993153
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.4293725623
Short name T186
Test name
Test status
Simulation time 22968828112 ps
CPU time 304.13 seconds
Started Jun 28 04:33:07 PM PDT 24
Finished Jun 28 04:38:14 PM PDT 24
Peak memory 224432 kb
Host smart-bc6b6ba2-2776-46ce-969e-086e6075be01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293725623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.4293725623
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.738322914
Short name T163
Test name
Test status
Simulation time 6074348665 ps
CPU time 55.73 seconds
Started Jun 28 04:32:58 PM PDT 24
Finished Jun 28 04:33:55 PM PDT 24
Peak memory 219452 kb
Host smart-6b6a4a59-3cac-4def-aabc-c86d17d1d0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738322914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.738322914
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.394917489
Short name T138
Test name
Test status
Simulation time 8529369344 ps
CPU time 33.4 seconds
Started Jun 28 04:33:17 PM PDT 24
Finished Jun 28 04:33:52 PM PDT 24
Peak memory 211896 kb
Host smart-d235233b-b569-45be-9ae0-1dec00a86a75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=394917489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.394917489
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3007254206
Short name T127
Test name
Test status
Simulation time 1897642207 ps
CPU time 32.18 seconds
Started Jun 28 04:33:07 PM PDT 24
Finished Jun 28 04:33:42 PM PDT 24
Peak memory 215676 kb
Host smart-15273116-43cf-451c-b2d0-800b12232933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007254206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3007254206
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1283781421
Short name T126
Test name
Test status
Simulation time 11005812245 ps
CPU time 52.38 seconds
Started Jun 28 04:32:59 PM PDT 24
Finished Jun 28 04:33:53 PM PDT 24
Peak memory 217460 kb
Host smart-90d43961-dd52-43a1-a270-d780d77d4364
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283781421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1283781421
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2596104960
Short name T159
Test name
Test status
Simulation time 7506369935 ps
CPU time 23.61 seconds
Started Jun 28 04:32:56 PM PDT 24
Finished Jun 28 04:33:20 PM PDT 24
Peak memory 217344 kb
Host smart-357cf6e8-b423-4a77-ba53-4e3a6247049e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596104960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2596104960
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.4182134334
Short name T219
Test name
Test status
Simulation time 38808094945 ps
CPU time 432.15 seconds
Started Jun 28 04:32:40 PM PDT 24
Finished Jun 28 04:39:53 PM PDT 24
Peak memory 234280 kb
Host smart-d4cb0721-a1cd-4d62-b7a0-c4ff286fc220
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182134334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.4182134334
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2187034233
Short name T325
Test name
Test status
Simulation time 39358612593 ps
CPU time 66.72 seconds
Started Jun 28 04:32:52 PM PDT 24
Finished Jun 28 04:34:00 PM PDT 24
Peak memory 219104 kb
Host smart-0786edd4-4618-4715-b1cb-11ce7feca88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187034233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2187034233
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3914810342
Short name T241
Test name
Test status
Simulation time 19319211491 ps
CPU time 26.46 seconds
Started Jun 28 04:32:47 PM PDT 24
Finished Jun 28 04:33:15 PM PDT 24
Peak memory 212160 kb
Host smart-f8f6bc92-4342-4624-ba4f-5dc1c9f4fdbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3914810342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3914810342
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.418625352
Short name T20
Test name
Test status
Simulation time 3317221406 ps
CPU time 240.12 seconds
Started Jun 28 04:32:36 PM PDT 24
Finished Jun 28 04:36:38 PM PDT 24
Peak memory 234740 kb
Host smart-512a2c3d-cf0f-4e2a-b52d-0a79166e9975
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418625352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.418625352
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1382342127
Short name T123
Test name
Test status
Simulation time 7699572624 ps
CPU time 63.34 seconds
Started Jun 28 04:32:42 PM PDT 24
Finished Jun 28 04:33:46 PM PDT 24
Peak memory 216176 kb
Host smart-628f881c-d2f0-4ff7-a610-47d39ca9ed56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382342127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1382342127
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1170955378
Short name T336
Test name
Test status
Simulation time 97046554519 ps
CPU time 138.66 seconds
Started Jun 28 04:32:32 PM PDT 24
Finished Jun 28 04:34:52 PM PDT 24
Peak memory 220980 kb
Host smart-f8224562-286a-40d3-87c3-9dc45ad0abf2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170955378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1170955378
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1717012197
Short name T280
Test name
Test status
Simulation time 9936404724 ps
CPU time 32.85 seconds
Started Jun 28 04:33:01 PM PDT 24
Finished Jun 28 04:33:36 PM PDT 24
Peak memory 217360 kb
Host smart-c2395970-08e1-4bec-ba05-b939d17d86a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717012197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1717012197
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3601469556
Short name T154
Test name
Test status
Simulation time 285009729735 ps
CPU time 724.03 seconds
Started Jun 28 04:32:58 PM PDT 24
Finished Jun 28 04:45:03 PM PDT 24
Peak memory 217808 kb
Host smart-4867631b-3f13-4815-8750-72bb9ef8012e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601469556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3601469556
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3216029506
Short name T143
Test name
Test status
Simulation time 2525919640 ps
CPU time 27.79 seconds
Started Jun 28 04:33:02 PM PDT 24
Finished Jun 28 04:33:33 PM PDT 24
Peak memory 219256 kb
Host smart-9a5042fc-782f-47ac-8900-6199a39b38b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216029506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3216029506
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2401943067
Short name T5
Test name
Test status
Simulation time 718717303 ps
CPU time 10.78 seconds
Started Jun 28 04:33:06 PM PDT 24
Finished Jun 28 04:33:20 PM PDT 24
Peak memory 219188 kb
Host smart-3ef395ca-186d-4b9e-a055-990cf5adac06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2401943067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2401943067
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.4162301835
Short name T170
Test name
Test status
Simulation time 1430373399 ps
CPU time 20.5 seconds
Started Jun 28 04:32:58 PM PDT 24
Finished Jun 28 04:33:20 PM PDT 24
Peak memory 215812 kb
Host smart-4fe856ce-9089-433c-a7d2-872d1451598f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162301835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.4162301835
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2111042734
Short name T306
Test name
Test status
Simulation time 209658804 ps
CPU time 11.23 seconds
Started Jun 28 04:33:02 PM PDT 24
Finished Jun 28 04:33:17 PM PDT 24
Peak memory 214660 kb
Host smart-6410ae74-262c-40f9-9775-41b0ecc2a332
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111042734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2111042734
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.17835788
Short name T48
Test name
Test status
Simulation time 170915967 ps
CPU time 8.45 seconds
Started Jun 28 04:33:14 PM PDT 24
Finished Jun 28 04:33:25 PM PDT 24
Peak memory 217064 kb
Host smart-b6584ce0-ee78-4c93-9382-da7b3673e2fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17835788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.17835788
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3945645028
Short name T278
Test name
Test status
Simulation time 34987753358 ps
CPU time 294.08 seconds
Started Jun 28 04:33:13 PM PDT 24
Finished Jun 28 04:38:09 PM PDT 24
Peak memory 225028 kb
Host smart-4b94168c-2774-41af-9be1-3a2720ca85fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945645028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3945645028
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.492063636
Short name T196
Test name
Test status
Simulation time 1500292034 ps
CPU time 18.53 seconds
Started Jun 28 04:33:16 PM PDT 24
Finished Jun 28 04:33:37 PM PDT 24
Peak memory 219200 kb
Host smart-26d75ccf-39cd-4849-b03d-14d96ce9ba82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492063636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.492063636
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.4017254739
Short name T260
Test name
Test status
Simulation time 3259629418 ps
CPU time 28.58 seconds
Started Jun 28 04:33:01 PM PDT 24
Finished Jun 28 04:33:33 PM PDT 24
Peak memory 219248 kb
Host smart-3f135813-1ad7-4b56-b183-ef739fc36a03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4017254739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.4017254739
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.603904448
Short name T81
Test name
Test status
Simulation time 6535555293 ps
CPU time 63.3 seconds
Started Jun 28 04:33:12 PM PDT 24
Finished Jun 28 04:34:17 PM PDT 24
Peak memory 217056 kb
Host smart-4ebe8486-7307-4dfd-827f-510a1c73c60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603904448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.603904448
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2231764011
Short name T322
Test name
Test status
Simulation time 892332552 ps
CPU time 50.31 seconds
Started Jun 28 04:33:03 PM PDT 24
Finished Jun 28 04:33:57 PM PDT 24
Peak memory 219352 kb
Host smart-183683c6-c66a-4ddb-9505-7bdf993787cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231764011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2231764011
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2868111257
Short name T153
Test name
Test status
Simulation time 17074653570 ps
CPU time 22.31 seconds
Started Jun 28 04:33:20 PM PDT 24
Finished Jun 28 04:33:44 PM PDT 24
Peak memory 217468 kb
Host smart-7398ce11-9c8e-4cc8-9466-410b2b2eded4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868111257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2868111257
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3036781292
Short name T321
Test name
Test status
Simulation time 402048530705 ps
CPU time 946.49 seconds
Started Jun 28 04:32:55 PM PDT 24
Finished Jun 28 04:48:42 PM PDT 24
Peak memory 234400 kb
Host smart-26f3c553-b4c9-4a49-bce4-b3ef45f03448
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036781292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3036781292
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.370939474
Short name T147
Test name
Test status
Simulation time 3332773242 ps
CPU time 39.16 seconds
Started Jun 28 04:33:04 PM PDT 24
Finished Jun 28 04:33:46 PM PDT 24
Peak memory 219240 kb
Host smart-b68136cc-f01f-403a-a565-434527b6df12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370939474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.370939474
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3576128797
Short name T122
Test name
Test status
Simulation time 7147677021 ps
CPU time 30.22 seconds
Started Jun 28 04:33:07 PM PDT 24
Finished Jun 28 04:33:40 PM PDT 24
Peak memory 219344 kb
Host smart-514649f1-48c4-4ca2-9636-8ef1c574319a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3576128797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3576128797
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3083310216
Short name T63
Test name
Test status
Simulation time 8291964249 ps
CPU time 68.35 seconds
Started Jun 28 04:33:13 PM PDT 24
Finished Jun 28 04:34:23 PM PDT 24
Peak memory 216912 kb
Host smart-fc2bd93d-d25c-466e-be6b-68ea0f825e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083310216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3083310216
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1736681456
Short name T52
Test name
Test status
Simulation time 28577160312 ps
CPU time 67.99 seconds
Started Jun 28 04:33:17 PM PDT 24
Finished Jun 28 04:34:27 PM PDT 24
Peak memory 216132 kb
Host smart-a1038776-8fce-43ee-892e-3587f2cb1da0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736681456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1736681456
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1129184626
Short name T292
Test name
Test status
Simulation time 425932114 ps
CPU time 11.46 seconds
Started Jun 28 04:33:01 PM PDT 24
Finished Jun 28 04:33:16 PM PDT 24
Peak memory 216956 kb
Host smart-70ff48ba-5259-473b-af1f-d8f22a3e6f69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129184626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1129184626
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.524613393
Short name T296
Test name
Test status
Simulation time 45635259966 ps
CPU time 332.9 seconds
Started Jun 28 04:33:17 PM PDT 24
Finished Jun 28 04:38:52 PM PDT 24
Peak memory 227552 kb
Host smart-bef5347f-a70a-4051-a7fe-c27ad9bdbecd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524613393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.524613393
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1324316692
Short name T145
Test name
Test status
Simulation time 19644714614 ps
CPU time 46.93 seconds
Started Jun 28 04:33:10 PM PDT 24
Finished Jun 28 04:33:59 PM PDT 24
Peak memory 219148 kb
Host smart-6e861a22-d13d-49b2-ae8f-01bc635c5ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324316692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1324316692
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.4140360624
Short name T224
Test name
Test status
Simulation time 186901808 ps
CPU time 10.67 seconds
Started Jun 28 04:33:03 PM PDT 24
Finished Jun 28 04:33:17 PM PDT 24
Peak memory 219224 kb
Host smart-1dbcfac5-1f45-4bbe-9749-7f0ab2428e8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4140360624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.4140360624
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1800503559
Short name T335
Test name
Test status
Simulation time 7512804350 ps
CPU time 71.47 seconds
Started Jun 28 04:33:09 PM PDT 24
Finished Jun 28 04:34:23 PM PDT 24
Peak memory 216804 kb
Host smart-1b172258-2d5f-4f0c-a8d9-3c069ff099d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800503559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1800503559
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1983972549
Short name T130
Test name
Test status
Simulation time 11352556716 ps
CPU time 51.07 seconds
Started Jun 28 04:33:09 PM PDT 24
Finished Jun 28 04:34:03 PM PDT 24
Peak memory 219240 kb
Host smart-02728e53-f503-431f-b9ba-2e0f24b90bf3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983972549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1983972549
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.718212619
Short name T270
Test name
Test status
Simulation time 2398944108 ps
CPU time 21.7 seconds
Started Jun 28 04:33:14 PM PDT 24
Finished Jun 28 04:33:37 PM PDT 24
Peak memory 217188 kb
Host smart-ef890dce-057e-4381-a981-0efbc75d0e15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718212619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.718212619
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1389429844
Short name T305
Test name
Test status
Simulation time 364115792843 ps
CPU time 939.37 seconds
Started Jun 28 04:33:18 PM PDT 24
Finished Jun 28 04:48:59 PM PDT 24
Peak memory 216916 kb
Host smart-1543ced1-ee6b-40d3-986c-2581bceb6b34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389429844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1389429844
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3982777281
Short name T199
Test name
Test status
Simulation time 9475207649 ps
CPU time 35.9 seconds
Started Jun 28 04:33:11 PM PDT 24
Finished Jun 28 04:33:49 PM PDT 24
Peak memory 219148 kb
Host smart-7ee3a81d-973b-4dcf-aaab-989780b59504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982777281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3982777281
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2844238960
Short name T128
Test name
Test status
Simulation time 1737405821 ps
CPU time 20.46 seconds
Started Jun 28 04:33:16 PM PDT 24
Finished Jun 28 04:33:38 PM PDT 24
Peak memory 219180 kb
Host smart-c3e97edf-8724-452c-970e-8cf6fbcd9821
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2844238960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2844238960
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1801994636
Short name T157
Test name
Test status
Simulation time 1266224481 ps
CPU time 19.55 seconds
Started Jun 28 04:33:09 PM PDT 24
Finished Jun 28 04:33:32 PM PDT 24
Peak memory 215888 kb
Host smart-0b248763-e0bb-46a7-bc0b-1ccee7ae8f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801994636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1801994636
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1809501141
Short name T343
Test name
Test status
Simulation time 3487075449 ps
CPU time 54.22 seconds
Started Jun 28 04:33:23 PM PDT 24
Finished Jun 28 04:34:18 PM PDT 24
Peak memory 219264 kb
Host smart-2c6e9e0f-83ce-4559-8f77-85a346141be2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809501141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1809501141
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3665751322
Short name T193
Test name
Test status
Simulation time 3927309618 ps
CPU time 19.21 seconds
Started Jun 28 04:33:22 PM PDT 24
Finished Jun 28 04:33:42 PM PDT 24
Peak memory 213188 kb
Host smart-db296e5b-ee7c-4220-9161-e199182603f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665751322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3665751322
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2709139352
Short name T43
Test name
Test status
Simulation time 224322307542 ps
CPU time 732.2 seconds
Started Jun 28 04:33:16 PM PDT 24
Finished Jun 28 04:45:31 PM PDT 24
Peak memory 239704 kb
Host smart-68a892c2-760b-4b4a-8467-0d21254d6579
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709139352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2709139352
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.803650147
Short name T168
Test name
Test status
Simulation time 3279489253 ps
CPU time 38.77 seconds
Started Jun 28 04:33:06 PM PDT 24
Finished Jun 28 04:33:47 PM PDT 24
Peak memory 219260 kb
Host smart-43753987-9774-4f6e-83ac-68fd4928ad17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803650147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.803650147
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.391045852
Short name T315
Test name
Test status
Simulation time 5061269282 ps
CPU time 21.54 seconds
Started Jun 28 04:33:23 PM PDT 24
Finished Jun 28 04:33:46 PM PDT 24
Peak memory 219236 kb
Host smart-a192b7f4-559d-43eb-9c86-97218f017de9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=391045852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.391045852
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1052528726
Short name T10
Test name
Test status
Simulation time 1216899151 ps
CPU time 28.48 seconds
Started Jun 28 04:33:26 PM PDT 24
Finished Jun 28 04:33:56 PM PDT 24
Peak memory 216712 kb
Host smart-ea64f9d0-f944-48e4-b390-c983d5cc402a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052528726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1052528726
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2879243023
Short name T312
Test name
Test status
Simulation time 6430159004 ps
CPU time 64.01 seconds
Started Jun 28 04:33:34 PM PDT 24
Finished Jun 28 04:34:38 PM PDT 24
Peak memory 217320 kb
Host smart-54d33c37-50ac-401b-b2c9-faef1267e84e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879243023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2879243023
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1068662516
Short name T268
Test name
Test status
Simulation time 14779271979 ps
CPU time 29.65 seconds
Started Jun 28 04:33:19 PM PDT 24
Finished Jun 28 04:33:50 PM PDT 24
Peak memory 217356 kb
Host smart-19b412a5-722d-4eb0-9259-cb88f83e664c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068662516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1068662516
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.777699368
Short name T252
Test name
Test status
Simulation time 11161888989 ps
CPU time 184.14 seconds
Started Jun 28 04:33:13 PM PDT 24
Finished Jun 28 04:36:19 PM PDT 24
Peak memory 218772 kb
Host smart-d1fc2fc8-880a-45e8-9dc9-19659721323c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777699368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.777699368
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1606827427
Short name T287
Test name
Test status
Simulation time 20687067776 ps
CPU time 49.22 seconds
Started Jun 28 04:33:15 PM PDT 24
Finished Jun 28 04:34:06 PM PDT 24
Peak memory 219316 kb
Host smart-3a546f41-1279-42e1-96ba-0b868097418f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606827427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1606827427
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.975870582
Short name T352
Test name
Test status
Simulation time 6290761103 ps
CPU time 24.48 seconds
Started Jun 28 04:33:14 PM PDT 24
Finished Jun 28 04:33:41 PM PDT 24
Peak memory 219232 kb
Host smart-4d3b07b6-3d45-4d8c-a8b1-f66816f56311
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=975870582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.975870582
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3492754205
Short name T349
Test name
Test status
Simulation time 6880859969 ps
CPU time 30.43 seconds
Started Jun 28 04:33:17 PM PDT 24
Finished Jun 28 04:33:49 PM PDT 24
Peak memory 216616 kb
Host smart-b7ce9e66-7367-4b66-a001-dce5d0fe9a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492754205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3492754205
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2212035500
Short name T131
Test name
Test status
Simulation time 98624506530 ps
CPU time 133.22 seconds
Started Jun 28 04:33:11 PM PDT 24
Finished Jun 28 04:35:26 PM PDT 24
Peak memory 220404 kb
Host smart-17a766da-200b-4d66-a32d-3b46271dca47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212035500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2212035500
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1184974020
Short name T251
Test name
Test status
Simulation time 2660353987 ps
CPU time 16.87 seconds
Started Jun 28 04:33:25 PM PDT 24
Finished Jun 28 04:33:43 PM PDT 24
Peak memory 217188 kb
Host smart-3018c9ec-1ecc-4a98-9bba-a7887c2dee09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184974020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1184974020
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.762380565
Short name T44
Test name
Test status
Simulation time 60288724427 ps
CPU time 755.53 seconds
Started Jun 28 04:33:09 PM PDT 24
Finished Jun 28 04:45:48 PM PDT 24
Peak memory 237644 kb
Host smart-542fafa2-21ff-439c-8dbf-b679dab6b88b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762380565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.762380565
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2289936760
Short name T328
Test name
Test status
Simulation time 688679476 ps
CPU time 19.16 seconds
Started Jun 28 04:33:11 PM PDT 24
Finished Jun 28 04:33:32 PM PDT 24
Peak memory 219276 kb
Host smart-3b3b0a9a-6a07-420e-ab51-ff18a4c661b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289936760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2289936760
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1532973765
Short name T142
Test name
Test status
Simulation time 722989470 ps
CPU time 9.94 seconds
Started Jun 28 04:33:08 PM PDT 24
Finished Jun 28 04:33:22 PM PDT 24
Peak memory 219200 kb
Host smart-403bbd05-184d-44d1-85ad-be3d43b9d9da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1532973765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1532973765
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.622080673
Short name T108
Test name
Test status
Simulation time 15646141723 ps
CPU time 64.35 seconds
Started Jun 28 04:33:14 PM PDT 24
Finished Jun 28 04:34:21 PM PDT 24
Peak memory 217048 kb
Host smart-e1b1f883-5f99-4680-8bac-aa40c84ff63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622080673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.622080673
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2824651258
Short name T4
Test name
Test status
Simulation time 6692481360 ps
CPU time 79.55 seconds
Started Jun 28 04:33:13 PM PDT 24
Finished Jun 28 04:34:34 PM PDT 24
Peak memory 219808 kb
Host smart-40eee12f-d653-4bcc-865e-d6845531ca02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824651258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2824651258
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.64636543
Short name T2
Test name
Test status
Simulation time 22903076950 ps
CPU time 28.27 seconds
Started Jun 28 04:33:02 PM PDT 24
Finished Jun 28 04:33:34 PM PDT 24
Peak memory 217084 kb
Host smart-3df91b01-8dcd-4983-8668-34f844193140
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64636543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.64636543
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3016528202
Short name T27
Test name
Test status
Simulation time 34722648867 ps
CPU time 67.26 seconds
Started Jun 28 04:33:15 PM PDT 24
Finished Jun 28 04:34:25 PM PDT 24
Peak memory 218520 kb
Host smart-69fbd2a5-60eb-4b16-9f8f-9912b8c8fc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016528202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3016528202
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.1486253606
Short name T286
Test name
Test status
Simulation time 1976290517 ps
CPU time 32.54 seconds
Started Jun 28 04:33:07 PM PDT 24
Finished Jun 28 04:33:43 PM PDT 24
Peak memory 217908 kb
Host smart-46af63cc-1498-4c14-8127-7147fcaee243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486253606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1486253606
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1815773320
Short name T234
Test name
Test status
Simulation time 6029659746 ps
CPU time 73.12 seconds
Started Jun 28 04:33:14 PM PDT 24
Finished Jun 28 04:34:29 PM PDT 24
Peak memory 219940 kb
Host smart-d9f2f581-7b96-4747-bf8d-cf7cc0f73cb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815773320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1815773320
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.444693523
Short name T272
Test name
Test status
Simulation time 6152733136 ps
CPU time 16.92 seconds
Started Jun 28 04:33:15 PM PDT 24
Finished Jun 28 04:33:34 PM PDT 24
Peak memory 216972 kb
Host smart-7a187f79-e4ee-44fc-9a75-1f3b739d142d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444693523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.444693523
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3185838537
Short name T120
Test name
Test status
Simulation time 12361173101 ps
CPU time 260.58 seconds
Started Jun 28 04:33:12 PM PDT 24
Finished Jun 28 04:37:35 PM PDT 24
Peak memory 236344 kb
Host smart-f6a2cc9c-e256-43ab-905c-6da2cbb75780
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185838537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3185838537
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.582265249
Short name T338
Test name
Test status
Simulation time 2770759759 ps
CPU time 34.64 seconds
Started Jun 28 04:33:14 PM PDT 24
Finished Jun 28 04:33:51 PM PDT 24
Peak memory 218580 kb
Host smart-9c2439d0-15aa-4c14-828f-593f3760f309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582265249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.582265249
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2033211905
Short name T307
Test name
Test status
Simulation time 4390718052 ps
CPU time 34.07 seconds
Started Jun 28 04:33:09 PM PDT 24
Finished Jun 28 04:33:46 PM PDT 24
Peak memory 217604 kb
Host smart-8abb24dc-bf1a-4646-98c9-35e3fc24567f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2033211905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2033211905
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.459419637
Short name T165
Test name
Test status
Simulation time 7188716487 ps
CPU time 58.2 seconds
Started Jun 28 04:33:03 PM PDT 24
Finished Jun 28 04:34:04 PM PDT 24
Peak memory 216736 kb
Host smart-3b2d32a2-c0f2-4df9-8d17-0b8c3be7a48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459419637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.459419637
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3964570358
Short name T301
Test name
Test status
Simulation time 1493258017 ps
CPU time 23.99 seconds
Started Jun 28 04:33:10 PM PDT 24
Finished Jun 28 04:33:37 PM PDT 24
Peak memory 217344 kb
Host smart-5355d0a8-3512-42f8-b99b-07cb6400700b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964570358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3964570358
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1367331092
Short name T218
Test name
Test status
Simulation time 174297188 ps
CPU time 8.04 seconds
Started Jun 28 04:32:59 PM PDT 24
Finished Jun 28 04:33:08 PM PDT 24
Peak memory 217076 kb
Host smart-4146da0d-6eb9-4ccc-ad42-c9b7f6466650
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367331092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1367331092
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.639519253
Short name T235
Test name
Test status
Simulation time 517552280142 ps
CPU time 867.6 seconds
Started Jun 28 04:32:37 PM PDT 24
Finished Jun 28 04:47:06 PM PDT 24
Peak memory 236016 kb
Host smart-a1d1fec3-397d-4eb7-ba15-130fdb08df19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639519253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.639519253
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3509609834
Short name T217
Test name
Test status
Simulation time 1832703105 ps
CPU time 19.63 seconds
Started Jun 28 04:33:06 PM PDT 24
Finished Jun 28 04:33:29 PM PDT 24
Peak memory 219200 kb
Host smart-b3a3b6c3-da9d-4c9e-95ff-274b9c21c8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509609834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3509609834
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.929958833
Short name T133
Test name
Test status
Simulation time 14728255547 ps
CPU time 35.31 seconds
Started Jun 28 04:32:56 PM PDT 24
Finished Jun 28 04:33:33 PM PDT 24
Peak memory 211920 kb
Host smart-5f6ceae3-7cc0-4b65-800f-e0bc5725e552
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=929958833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.929958833
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1158267056
Short name T28
Test name
Test status
Simulation time 2907216583 ps
CPU time 235.65 seconds
Started Jun 28 04:32:39 PM PDT 24
Finished Jun 28 04:36:36 PM PDT 24
Peak memory 234700 kb
Host smart-fd59310a-c2d0-4964-879b-5be81803ea58
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158267056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1158267056
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2013529045
Short name T282
Test name
Test status
Simulation time 2029624696 ps
CPU time 20.01 seconds
Started Jun 28 04:32:43 PM PDT 24
Finished Jun 28 04:33:04 PM PDT 24
Peak memory 216784 kb
Host smart-7109d99d-746b-4240-84db-9805d56082fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013529045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2013529045
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.48932639
Short name T266
Test name
Test status
Simulation time 13464448984 ps
CPU time 67.73 seconds
Started Jun 28 04:32:41 PM PDT 24
Finished Jun 28 04:33:49 PM PDT 24
Peak memory 218548 kb
Host smart-ceec77b8-c267-4e65-9ccc-dcd39f63dc80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48932639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.rom_ctrl_stress_all.48932639
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.919835605
Short name T203
Test name
Test status
Simulation time 172445514 ps
CPU time 8 seconds
Started Jun 28 04:33:18 PM PDT 24
Finished Jun 28 04:33:27 PM PDT 24
Peak memory 216920 kb
Host smart-1f56f890-8d46-48e9-9553-bc3830fcaa1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919835605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.919835605
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.706759606
Short name T18
Test name
Test status
Simulation time 10996278835 ps
CPU time 185.84 seconds
Started Jun 28 04:33:19 PM PDT 24
Finished Jun 28 04:36:27 PM PDT 24
Peak memory 225300 kb
Host smart-dda7eb92-4715-47dd-9bb1-17080cd9b078
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706759606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.706759606
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.4068653102
Short name T297
Test name
Test status
Simulation time 2925641483 ps
CPU time 37.7 seconds
Started Jun 28 04:33:18 PM PDT 24
Finished Jun 28 04:33:57 PM PDT 24
Peak memory 219256 kb
Host smart-c06afd10-6685-47a5-9911-8f73cbddac43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068653102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.4068653102
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.990023253
Short name T212
Test name
Test status
Simulation time 1688914980 ps
CPU time 21.32 seconds
Started Jun 28 04:33:26 PM PDT 24
Finished Jun 28 04:33:49 PM PDT 24
Peak memory 211188 kb
Host smart-f711bace-5ff4-4a76-9f9e-5ff5970ac72a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=990023253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.990023253
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.688674598
Short name T281
Test name
Test status
Simulation time 30887111943 ps
CPU time 69.33 seconds
Started Jun 28 04:33:14 PM PDT 24
Finished Jun 28 04:34:25 PM PDT 24
Peak memory 216752 kb
Host smart-5a1ec1b0-80bb-493d-97af-c95fe12094b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688674598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.688674598
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1465979717
Short name T350
Test name
Test status
Simulation time 31517491103 ps
CPU time 139.97 seconds
Started Jun 28 04:33:16 PM PDT 24
Finished Jun 28 04:35:38 PM PDT 24
Peak memory 219936 kb
Host smart-b7d5fd07-461e-4e19-87e0-d0ffb6249f89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465979717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1465979717
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1402183253
Short name T250
Test name
Test status
Simulation time 3133662614 ps
CPU time 24.92 seconds
Started Jun 28 04:33:27 PM PDT 24
Finished Jun 28 04:33:53 PM PDT 24
Peak memory 217064 kb
Host smart-e7bbe8dc-420b-47e2-b377-bed4b9523533
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402183253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1402183253
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3648879684
Short name T146
Test name
Test status
Simulation time 17859969295 ps
CPU time 213.99 seconds
Started Jun 28 04:33:22 PM PDT 24
Finished Jun 28 04:36:57 PM PDT 24
Peak memory 237000 kb
Host smart-73c3ff88-a1c5-476f-bbfc-c329d8e9e4df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648879684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3648879684
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2518595971
Short name T347
Test name
Test status
Simulation time 40690081169 ps
CPU time 53.19 seconds
Started Jun 28 04:33:15 PM PDT 24
Finished Jun 28 04:34:10 PM PDT 24
Peak memory 219336 kb
Host smart-74dafd2f-9ab5-4574-8e9d-e890e206554f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518595971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2518595971
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3024269998
Short name T49
Test name
Test status
Simulation time 17784816102 ps
CPU time 32.79 seconds
Started Jun 28 04:33:21 PM PDT 24
Finished Jun 28 04:33:55 PM PDT 24
Peak memory 219312 kb
Host smart-a511cf92-99ac-4737-be7c-f7a671407efc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3024269998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3024269998
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.4131339597
Short name T35
Test name
Test status
Simulation time 28002199512 ps
CPU time 56.9 seconds
Started Jun 28 04:33:13 PM PDT 24
Finished Jun 28 04:34:12 PM PDT 24
Peak memory 217048 kb
Host smart-eafbdab6-8fe4-4e61-a927-cc0ec97efcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131339597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.4131339597
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3757072878
Short name T174
Test name
Test status
Simulation time 929721841 ps
CPU time 44.47 seconds
Started Jun 28 04:33:14 PM PDT 24
Finished Jun 28 04:34:00 PM PDT 24
Peak memory 220048 kb
Host smart-ade2752e-aa39-4024-8cbf-24687f24d9ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757072878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3757072878
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.4199188501
Short name T25
Test name
Test status
Simulation time 7418163195 ps
CPU time 14.26 seconds
Started Jun 28 04:33:18 PM PDT 24
Finished Jun 28 04:33:34 PM PDT 24
Peak memory 217372 kb
Host smart-0ebd1a00-2ca0-455f-ba7e-52a24dc8a614
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199188501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.4199188501
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2316210048
Short name T160
Test name
Test status
Simulation time 241372708201 ps
CPU time 579.06 seconds
Started Jun 28 04:33:27 PM PDT 24
Finished Jun 28 04:43:08 PM PDT 24
Peak memory 246684 kb
Host smart-f57d01a1-f9b1-4c9f-a443-9588c2aa65a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316210048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2316210048
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.200690182
Short name T319
Test name
Test status
Simulation time 30879655751 ps
CPU time 65.39 seconds
Started Jun 28 04:33:16 PM PDT 24
Finished Jun 28 04:34:23 PM PDT 24
Peak memory 219136 kb
Host smart-c82361e7-466d-47fd-a8bf-966cbfbd436b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200690182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.200690182
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3779746124
Short name T179
Test name
Test status
Simulation time 7589125658 ps
CPU time 31.78 seconds
Started Jun 28 04:33:19 PM PDT 24
Finished Jun 28 04:33:53 PM PDT 24
Peak memory 219536 kb
Host smart-dfc1e23a-0dc8-4951-9280-5e3da1914f2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3779746124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3779746124
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.913390198
Short name T308
Test name
Test status
Simulation time 11005227450 ps
CPU time 57.43 seconds
Started Jun 28 04:33:26 PM PDT 24
Finished Jun 28 04:34:25 PM PDT 24
Peak memory 217040 kb
Host smart-c139b37b-612f-4890-b32d-790afde26c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913390198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.913390198
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3524132226
Short name T33
Test name
Test status
Simulation time 15191897077 ps
CPU time 66.96 seconds
Started Jun 28 04:33:25 PM PDT 24
Finished Jun 28 04:34:33 PM PDT 24
Peak memory 217280 kb
Host smart-c8c513c7-b94c-453a-9c35-599b5e7d17e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524132226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3524132226
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.393290164
Short name T279
Test name
Test status
Simulation time 689148184 ps
CPU time 8.27 seconds
Started Jun 28 04:33:19 PM PDT 24
Finished Jun 28 04:33:29 PM PDT 24
Peak memory 213144 kb
Host smart-0c692e18-0131-480a-92d1-5187933d116a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393290164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.393290164
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1539580339
Short name T243
Test name
Test status
Simulation time 2749427546 ps
CPU time 24.39 seconds
Started Jun 28 04:33:18 PM PDT 24
Finished Jun 28 04:33:44 PM PDT 24
Peak memory 215536 kb
Host smart-31584709-a445-4890-b806-11ae9a6b6c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539580339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1539580339
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.828958796
Short name T255
Test name
Test status
Simulation time 9431657268 ps
CPU time 20.74 seconds
Started Jun 28 04:33:27 PM PDT 24
Finished Jun 28 04:33:49 PM PDT 24
Peak memory 212012 kb
Host smart-b5dc2c29-6dee-4710-9a51-82bb582b9c63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=828958796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.828958796
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3561441621
Short name T182
Test name
Test status
Simulation time 34304068044 ps
CPU time 68.05 seconds
Started Jun 28 04:33:26 PM PDT 24
Finished Jun 28 04:34:35 PM PDT 24
Peak memory 216568 kb
Host smart-aa2b700d-c9ec-4622-ab81-4011d0672e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561441621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3561441621
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.521588296
Short name T353
Test name
Test status
Simulation time 7029243740 ps
CPU time 67.59 seconds
Started Jun 28 04:33:15 PM PDT 24
Finished Jun 28 04:34:25 PM PDT 24
Peak memory 219268 kb
Host smart-1eb5de52-d58c-4f4f-8a0c-7df9228c584d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521588296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.521588296
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1467964955
Short name T7
Test name
Test status
Simulation time 28954480171 ps
CPU time 25.76 seconds
Started Jun 28 04:33:20 PM PDT 24
Finished Jun 28 04:33:48 PM PDT 24
Peak memory 217224 kb
Host smart-f3995c8b-8460-4f1e-8a5a-e3258a6a11c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467964955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1467964955
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2434561639
Short name T152
Test name
Test status
Simulation time 42175110592 ps
CPU time 429.4 seconds
Started Jun 28 04:33:27 PM PDT 24
Finished Jun 28 04:40:38 PM PDT 24
Peak memory 224860 kb
Host smart-7e719811-8f4b-4275-ba0c-4d13dc82a55f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434561639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2434561639
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2186337899
Short name T139
Test name
Test status
Simulation time 8305347706 ps
CPU time 64.14 seconds
Started Jun 28 04:33:19 PM PDT 24
Finished Jun 28 04:34:25 PM PDT 24
Peak memory 219244 kb
Host smart-93f2f09d-4e4a-4d9c-876a-765a44e19f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186337899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2186337899
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.864332655
Short name T144
Test name
Test status
Simulation time 352796116 ps
CPU time 10.3 seconds
Started Jun 28 04:33:29 PM PDT 24
Finished Jun 28 04:33:40 PM PDT 24
Peak memory 219172 kb
Host smart-710f4109-683f-4259-b1c5-99370d22e21b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=864332655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.864332655
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3472163964
Short name T78
Test name
Test status
Simulation time 12707777601 ps
CPU time 71.1 seconds
Started Jun 28 04:33:15 PM PDT 24
Finished Jun 28 04:34:28 PM PDT 24
Peak memory 215832 kb
Host smart-1212ce83-8a6e-4ea9-9637-043c63dffd63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472163964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3472163964
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.71290659
Short name T317
Test name
Test status
Simulation time 420708772 ps
CPU time 14.69 seconds
Started Jun 28 04:33:14 PM PDT 24
Finished Jun 28 04:33:31 PM PDT 24
Peak memory 219192 kb
Host smart-97b86cb2-72d9-489e-9ebb-15a7016f3fb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71290659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 44.rom_ctrl_stress_all.71290659
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3402161807
Short name T226
Test name
Test status
Simulation time 7385130909 ps
CPU time 29.79 seconds
Started Jun 28 04:33:24 PM PDT 24
Finished Jun 28 04:33:54 PM PDT 24
Peak memory 217432 kb
Host smart-bb34ece7-d626-4fa1-8a57-c69815de221f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402161807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3402161807
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2433074860
Short name T38
Test name
Test status
Simulation time 95977769111 ps
CPU time 407.19 seconds
Started Jun 28 04:33:16 PM PDT 24
Finished Jun 28 04:40:05 PM PDT 24
Peak memory 239668 kb
Host smart-ac2ae32c-4990-4a19-b303-91fc4c783d47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433074860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2433074860
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1651492827
Short name T51
Test name
Test status
Simulation time 5470277289 ps
CPU time 36.54 seconds
Started Jun 28 04:33:17 PM PDT 24
Finished Jun 28 04:33:56 PM PDT 24
Peak memory 219244 kb
Host smart-ea45fca4-5af6-459f-a4a2-9f73c45d347d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651492827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1651492827
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2145594800
Short name T200
Test name
Test status
Simulation time 581301225 ps
CPU time 10.14 seconds
Started Jun 28 04:33:19 PM PDT 24
Finished Jun 28 04:33:31 PM PDT 24
Peak memory 219188 kb
Host smart-6a7212b5-21f3-48a3-9c27-e4f2057909de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2145594800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2145594800
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2445045473
Short name T293
Test name
Test status
Simulation time 5587682180 ps
CPU time 25.38 seconds
Started Jun 28 04:33:26 PM PDT 24
Finished Jun 28 04:33:52 PM PDT 24
Peak memory 216704 kb
Host smart-97b13397-8811-4762-84e9-9466c74eabc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445045473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2445045473
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.442002251
Short name T15
Test name
Test status
Simulation time 43730307528 ps
CPU time 168.32 seconds
Started Jun 28 04:33:23 PM PDT 24
Finished Jun 28 04:36:12 PM PDT 24
Peak memory 220732 kb
Host smart-1a76bf27-28a9-41da-8d8a-dbed25c098bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442002251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.442002251
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3943849971
Short name T277
Test name
Test status
Simulation time 8233690702 ps
CPU time 33.52 seconds
Started Jun 28 04:33:21 PM PDT 24
Finished Jun 28 04:33:56 PM PDT 24
Peak memory 217472 kb
Host smart-6211ce5c-3e56-4955-b39f-05db8ce0b76e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943849971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3943849971
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2502919891
Short name T294
Test name
Test status
Simulation time 4556920347 ps
CPU time 173.22 seconds
Started Jun 28 04:33:24 PM PDT 24
Finished Jun 28 04:36:18 PM PDT 24
Peak memory 228944 kb
Host smart-d236c563-158f-4083-bd89-e37983e5e0ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502919891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2502919891
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2412528104
Short name T227
Test name
Test status
Simulation time 1374955565 ps
CPU time 18.92 seconds
Started Jun 28 04:33:18 PM PDT 24
Finished Jun 28 04:33:38 PM PDT 24
Peak memory 219196 kb
Host smart-611ebcb3-0792-4f3e-945e-575655e9e434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412528104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2412528104
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.591009046
Short name T264
Test name
Test status
Simulation time 177862964 ps
CPU time 10.32 seconds
Started Jun 28 04:33:28 PM PDT 24
Finished Jun 28 04:33:39 PM PDT 24
Peak memory 219188 kb
Host smart-61240f53-11ab-4e73-bb7a-044587527b5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=591009046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.591009046
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3613524351
Short name T77
Test name
Test status
Simulation time 4681353164 ps
CPU time 43.73 seconds
Started Jun 28 04:33:31 PM PDT 24
Finished Jun 28 04:34:15 PM PDT 24
Peak memory 215948 kb
Host smart-47773cff-4539-4700-940a-942ccab8141d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613524351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3613524351
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.309427065
Short name T253
Test name
Test status
Simulation time 6041469456 ps
CPU time 51.71 seconds
Started Jun 28 04:33:39 PM PDT 24
Finished Jun 28 04:34:32 PM PDT 24
Peak memory 217416 kb
Host smart-5ea7b13e-3af4-4a11-ac6e-56429acf3fb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309427065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.309427065
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.494340654
Short name T316
Test name
Test status
Simulation time 6478938322 ps
CPU time 25.92 seconds
Started Jun 28 04:33:18 PM PDT 24
Finished Jun 28 04:33:46 PM PDT 24
Peak memory 217360 kb
Host smart-af805401-a308-4346-9d6c-b504b9f9a84a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494340654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.494340654
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2329934220
Short name T326
Test name
Test status
Simulation time 55669748480 ps
CPU time 258.64 seconds
Started Jun 28 04:33:15 PM PDT 24
Finished Jun 28 04:37:36 PM PDT 24
Peak memory 240032 kb
Host smart-2236b7f6-21c0-4746-b6d2-10f93cb2c612
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329934220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2329934220
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2812048404
Short name T337
Test name
Test status
Simulation time 661706827 ps
CPU time 19.12 seconds
Started Jun 28 04:33:22 PM PDT 24
Finished Jun 28 04:33:42 PM PDT 24
Peak memory 219172 kb
Host smart-a14fac43-9bfa-4a01-a242-3c63111ca161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812048404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2812048404
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1432699078
Short name T285
Test name
Test status
Simulation time 3572397937 ps
CPU time 29.71 seconds
Started Jun 28 04:33:18 PM PDT 24
Finished Jun 28 04:33:49 PM PDT 24
Peak memory 217612 kb
Host smart-d606c05e-26a3-4ade-99ee-2f4e8bb14526
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1432699078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1432699078
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3562874662
Short name T184
Test name
Test status
Simulation time 5698209981 ps
CPU time 38.31 seconds
Started Jun 28 04:33:28 PM PDT 24
Finished Jun 28 04:34:07 PM PDT 24
Peak memory 216064 kb
Host smart-67a6fcf4-b31f-477c-8ffa-b9d62f536713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562874662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3562874662
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2008483667
Short name T16
Test name
Test status
Simulation time 482371153 ps
CPU time 15.43 seconds
Started Jun 28 04:33:16 PM PDT 24
Finished Jun 28 04:33:34 PM PDT 24
Peak memory 219180 kb
Host smart-024bd858-3d8b-4e82-a4ee-7cd07f58393e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008483667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2008483667
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3794707633
Short name T216
Test name
Test status
Simulation time 4099328091 ps
CPU time 32.07 seconds
Started Jun 28 04:33:24 PM PDT 24
Finished Jun 28 04:33:57 PM PDT 24
Peak memory 216756 kb
Host smart-25705f14-3ee5-4ff3-b080-f97a04c7f60f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794707633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3794707633
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3470943789
Short name T41
Test name
Test status
Simulation time 197097532670 ps
CPU time 1015.81 seconds
Started Jun 28 04:33:17 PM PDT 24
Finished Jun 28 04:50:14 PM PDT 24
Peak memory 225472 kb
Host smart-838b88fb-0519-47d1-8155-7dd8d58b159d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470943789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3470943789
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1832472933
Short name T53
Test name
Test status
Simulation time 33522940222 ps
CPU time 68.18 seconds
Started Jun 28 04:33:28 PM PDT 24
Finished Jun 28 04:34:37 PM PDT 24
Peak memory 219268 kb
Host smart-d65a6b9f-c33b-4fa0-816a-b54fc0b7588b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832472933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1832472933
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.4083899635
Short name T211
Test name
Test status
Simulation time 13420098136 ps
CPU time 30.09 seconds
Started Jun 28 04:33:28 PM PDT 24
Finished Jun 28 04:33:59 PM PDT 24
Peak memory 217624 kb
Host smart-0febe278-b6cf-4650-a01d-0e67316ba2f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4083899635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.4083899635
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1164294454
Short name T171
Test name
Test status
Simulation time 223904117 ps
CPU time 11.22 seconds
Started Jun 28 04:33:26 PM PDT 24
Finished Jun 28 04:33:37 PM PDT 24
Peak memory 214624 kb
Host smart-94e59ae0-3bd4-48bc-83a2-5d1b56299402
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164294454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1164294454
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2658995899
Short name T232
Test name
Test status
Simulation time 1177436155 ps
CPU time 12.67 seconds
Started Jun 28 04:33:33 PM PDT 24
Finished Jun 28 04:33:46 PM PDT 24
Peak memory 216956 kb
Host smart-0e50908d-d48c-4e58-97ed-f707c0df32db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658995899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2658995899
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3908095083
Short name T342
Test name
Test status
Simulation time 92695381226 ps
CPU time 298.88 seconds
Started Jun 28 04:33:27 PM PDT 24
Finished Jun 28 04:38:27 PM PDT 24
Peak memory 236704 kb
Host smart-27d82458-4026-4020-9ebf-eca894d6b579
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908095083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3908095083
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2620424628
Short name T137
Test name
Test status
Simulation time 2135056387 ps
CPU time 32.92 seconds
Started Jun 28 04:33:21 PM PDT 24
Finished Jun 28 04:33:55 PM PDT 24
Peak memory 219276 kb
Host smart-f748c452-0cf0-4622-9fbd-c5fc08a4b1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620424628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2620424628
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2466977405
Short name T11
Test name
Test status
Simulation time 1547072957 ps
CPU time 19.55 seconds
Started Jun 28 04:33:18 PM PDT 24
Finished Jun 28 04:33:39 PM PDT 24
Peak memory 217556 kb
Host smart-b9d06a8c-20c2-482e-a839-ad80b966fcc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2466977405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2466977405
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3170947874
Short name T205
Test name
Test status
Simulation time 2811654354 ps
CPU time 47.54 seconds
Started Jun 28 04:33:27 PM PDT 24
Finished Jun 28 04:34:16 PM PDT 24
Peak memory 217956 kb
Host smart-9e564b5e-c3c5-4db4-8020-83429154ab34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170947874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3170947874
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2753859092
Short name T3
Test name
Test status
Simulation time 1570470301 ps
CPU time 40.61 seconds
Started Jun 28 04:33:27 PM PDT 24
Finished Jun 28 04:34:09 PM PDT 24
Peak memory 219220 kb
Host smart-bd38f3cb-437d-421b-a3d4-7ceeb4347d7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753859092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2753859092
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3978826660
Short name T245
Test name
Test status
Simulation time 3551405444 ps
CPU time 25.76 seconds
Started Jun 28 04:32:43 PM PDT 24
Finished Jun 28 04:33:15 PM PDT 24
Peak memory 216052 kb
Host smart-a3af3c03-a4f3-4ac7-bb04-d7d1845f1fac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978826660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3978826660
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.75243813
Short name T164
Test name
Test status
Simulation time 192255097947 ps
CPU time 238.17 seconds
Started Jun 28 04:32:46 PM PDT 24
Finished Jun 28 04:36:45 PM PDT 24
Peak memory 216720 kb
Host smart-8104b456-eff2-443d-8da5-0de9517b9ffa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75243813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_cor
rupt_sig_fatal_chk.75243813
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.459595396
Short name T231
Test name
Test status
Simulation time 1500347182 ps
CPU time 19.08 seconds
Started Jun 28 04:33:15 PM PDT 24
Finished Jun 28 04:33:36 PM PDT 24
Peak memory 219196 kb
Host smart-447e74a9-b678-4e39-a463-98fab515a759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459595396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.459595396
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.786222826
Short name T150
Test name
Test status
Simulation time 16162694933 ps
CPU time 32.54 seconds
Started Jun 28 04:32:37 PM PDT 24
Finished Jun 28 04:33:10 PM PDT 24
Peak memory 211472 kb
Host smart-f770be89-da25-47f2-9eb3-7111b79bd0be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=786222826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.786222826
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3454286169
Short name T167
Test name
Test status
Simulation time 731211532 ps
CPU time 19.36 seconds
Started Jun 28 04:32:52 PM PDT 24
Finished Jun 28 04:33:13 PM PDT 24
Peak memory 216036 kb
Host smart-b3917b76-c6cd-46b9-8377-59c208ebc352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454286169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3454286169
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.128892813
Short name T204
Test name
Test status
Simulation time 58524340155 ps
CPU time 97.49 seconds
Started Jun 28 04:32:40 PM PDT 24
Finished Jun 28 04:34:19 PM PDT 24
Peak memory 219252 kb
Host smart-18806159-5277-45af-883a-86ecbd41aab3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128892813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.128892813
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.4035371129
Short name T299
Test name
Test status
Simulation time 2857414133 ps
CPU time 25.3 seconds
Started Jun 28 04:32:55 PM PDT 24
Finished Jun 28 04:33:21 PM PDT 24
Peak memory 217176 kb
Host smart-99c53a41-553b-406d-bb2b-b9e5916f77ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035371129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.4035371129
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2800591422
Short name T274
Test name
Test status
Simulation time 64157770726 ps
CPU time 707.4 seconds
Started Jun 28 04:33:02 PM PDT 24
Finished Jun 28 04:44:53 PM PDT 24
Peak memory 238548 kb
Host smart-b80a2d4d-15e5-4f50-9e4f-994d26efe951
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800591422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2800591422
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2986461404
Short name T141
Test name
Test status
Simulation time 342851482 ps
CPU time 19.53 seconds
Started Jun 28 04:32:46 PM PDT 24
Finished Jun 28 04:33:06 PM PDT 24
Peak memory 218920 kb
Host smart-beeaa7ed-97a8-4a09-9d16-7a66e6c19a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986461404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2986461404
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3684807974
Short name T246
Test name
Test status
Simulation time 722954217 ps
CPU time 10.32 seconds
Started Jun 28 04:32:42 PM PDT 24
Finished Jun 28 04:32:53 PM PDT 24
Peak memory 219200 kb
Host smart-ca745d4f-7503-4050-87c3-bae86a09fd3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3684807974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3684807974
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1464001716
Short name T80
Test name
Test status
Simulation time 28779364775 ps
CPU time 75.38 seconds
Started Jun 28 04:32:44 PM PDT 24
Finished Jun 28 04:34:00 PM PDT 24
Peak memory 216564 kb
Host smart-198b4f74-3787-471b-be1a-552c40cddcf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464001716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1464001716
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.647431506
Short name T124
Test name
Test status
Simulation time 4484193649 ps
CPU time 49 seconds
Started Jun 28 04:32:32 PM PDT 24
Finished Jun 28 04:33:22 PM PDT 24
Peak memory 219244 kb
Host smart-563b8dbf-bc66-4f05-89eb-a743584ed705
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647431506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.647431506
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.993001382
Short name T68
Test name
Test status
Simulation time 1689851258 ps
CPU time 19.29 seconds
Started Jun 28 04:32:53 PM PDT 24
Finished Jun 28 04:33:13 PM PDT 24
Peak memory 216880 kb
Host smart-9465676d-e6f9-4e32-b44f-790b6a3aee6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993001382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.993001382
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.915040241
Short name T247
Test name
Test status
Simulation time 31880394163 ps
CPU time 241.98 seconds
Started Jun 28 04:32:49 PM PDT 24
Finished Jun 28 04:36:52 PM PDT 24
Peak memory 233616 kb
Host smart-f9ec3de7-d7aa-406c-b961-8091e48fafcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915040241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.915040241
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2589423247
Short name T269
Test name
Test status
Simulation time 13019755844 ps
CPU time 39.91 seconds
Started Jun 28 04:32:38 PM PDT 24
Finished Jun 28 04:33:19 PM PDT 24
Peak memory 219240 kb
Host smart-d5f13e47-ed97-486b-82e1-14861250ce59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589423247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2589423247
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3341277743
Short name T209
Test name
Test status
Simulation time 17234690530 ps
CPU time 22.27 seconds
Started Jun 28 04:33:05 PM PDT 24
Finished Jun 28 04:33:31 PM PDT 24
Peak memory 217564 kb
Host smart-48c9ff04-8f88-411e-9441-e4e9bc139fb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3341277743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3341277743
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3084907074
Short name T178
Test name
Test status
Simulation time 3413842815 ps
CPU time 43.39 seconds
Started Jun 28 04:32:58 PM PDT 24
Finished Jun 28 04:33:42 PM PDT 24
Peak memory 216376 kb
Host smart-f3e1eb68-0d97-4bef-a898-772e91bfb479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084907074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3084907074
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1159348179
Short name T341
Test name
Test status
Simulation time 51657989494 ps
CPU time 106.56 seconds
Started Jun 28 04:32:39 PM PDT 24
Finished Jun 28 04:34:27 PM PDT 24
Peak memory 217796 kb
Host smart-bfc32337-9af8-415d-921e-7ce2e8590ede
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159348179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1159348179
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1426270483
Short name T275
Test name
Test status
Simulation time 1088261545 ps
CPU time 15.88 seconds
Started Jun 28 04:33:07 PM PDT 24
Finished Jun 28 04:33:26 PM PDT 24
Peak memory 217020 kb
Host smart-8928a1ad-40c7-4a1f-ab03-66a600e304a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426270483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1426270483
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1553152991
Short name T176
Test name
Test status
Simulation time 7197776246 ps
CPU time 42.19 seconds
Started Jun 28 04:32:39 PM PDT 24
Finished Jun 28 04:33:23 PM PDT 24
Peak memory 219476 kb
Host smart-47f3b786-2347-4f22-99b3-6943477c641a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553152991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1553152991
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1743542792
Short name T46
Test name
Test status
Simulation time 1522235348 ps
CPU time 19.64 seconds
Started Jun 28 04:32:43 PM PDT 24
Finished Jun 28 04:33:04 PM PDT 24
Peak memory 211180 kb
Host smart-ce15e32a-1ab0-438b-b40c-3ee21f74a41b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1743542792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1743542792
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1647145656
Short name T136
Test name
Test status
Simulation time 4814636302 ps
CPU time 51.28 seconds
Started Jun 28 04:33:05 PM PDT 24
Finished Jun 28 04:33:59 PM PDT 24
Peak memory 216140 kb
Host smart-863d1081-7d89-467d-ad1e-17dcd0e67bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647145656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1647145656
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1479256365
Short name T132
Test name
Test status
Simulation time 10676107484 ps
CPU time 26.04 seconds
Started Jun 28 04:32:44 PM PDT 24
Finished Jun 28 04:33:11 PM PDT 24
Peak memory 214488 kb
Host smart-7b71ef98-0e54-41ec-bd0b-94055bd69ef2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479256365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1479256365
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2664014761
Short name T197
Test name
Test status
Simulation time 2053107891 ps
CPU time 11.95 seconds
Started Jun 28 04:32:36 PM PDT 24
Finished Jun 28 04:32:49 PM PDT 24
Peak memory 216988 kb
Host smart-ccaf6758-781c-48dc-83a2-5b2ed6566971
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664014761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2664014761
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.833553472
Short name T354
Test name
Test status
Simulation time 11066045226 ps
CPU time 251.87 seconds
Started Jun 28 04:33:08 PM PDT 24
Finished Jun 28 04:37:24 PM PDT 24
Peak memory 237996 kb
Host smart-322e086f-a840-4e1f-bd61-3fdebe97a44b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833553472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.833553472
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2678646125
Short name T238
Test name
Test status
Simulation time 34798347920 ps
CPU time 67.15 seconds
Started Jun 28 04:32:41 PM PDT 24
Finished Jun 28 04:33:54 PM PDT 24
Peak memory 219064 kb
Host smart-1048d449-4584-4bfb-ad9f-47ef2125d0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678646125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2678646125
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2475235521
Short name T210
Test name
Test status
Simulation time 4776995523 ps
CPU time 24.46 seconds
Started Jun 28 04:33:04 PM PDT 24
Finished Jun 28 04:33:32 PM PDT 24
Peak memory 219196 kb
Host smart-9d59301f-2224-42a5-ab64-6e3d5fa4a8f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2475235521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2475235521
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2231415871
Short name T324
Test name
Test status
Simulation time 360831071 ps
CPU time 20.73 seconds
Started Jun 28 04:33:01 PM PDT 24
Finished Jun 28 04:33:25 PM PDT 24
Peak memory 216476 kb
Host smart-10e8c8fc-2137-411f-9181-a4acc5bca388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231415871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2231415871
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2339793372
Short name T181
Test name
Test status
Simulation time 98691355166 ps
CPU time 194.56 seconds
Started Jun 28 04:32:50 PM PDT 24
Finished Jun 28 04:36:06 PM PDT 24
Peak memory 220004 kb
Host smart-1e34dbd1-8379-4913-895b-21b76f4fc9b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339793372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2339793372
Directory /workspace/9.rom_ctrl_stress_all/latest
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