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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.21 96.89 91.99 97.68 100.00 98.28 97.30 98.37


Total test records in report: 459
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T302 /workspace/coverage/default/31.rom_ctrl_smoke.2071016238 Jun 29 04:34:44 PM PDT 24 Jun 29 04:35:17 PM PDT 24 7273449675 ps
T303 /workspace/coverage/default/27.rom_ctrl_alert_test.2347569657 Jun 29 04:34:44 PM PDT 24 Jun 29 04:34:59 PM PDT 24 3895867604 ps
T304 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.4041800252 Jun 29 04:34:33 PM PDT 24 Jun 29 04:34:57 PM PDT 24 4744423124 ps
T305 /workspace/coverage/default/25.rom_ctrl_stress_all.1445019765 Jun 29 04:34:35 PM PDT 24 Jun 29 04:37:51 PM PDT 24 22780910552 ps
T306 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1147987470 Jun 29 04:34:27 PM PDT 24 Jun 29 04:34:38 PM PDT 24 185733135 ps
T307 /workspace/coverage/default/7.rom_ctrl_stress_all.1815019051 Jun 29 04:34:15 PM PDT 24 Jun 29 04:36:37 PM PDT 24 131386926848 ps
T308 /workspace/coverage/default/44.rom_ctrl_stress_all.166287149 Jun 29 04:35:01 PM PDT 24 Jun 29 04:36:54 PM PDT 24 8558234776 ps
T309 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2968329049 Jun 29 04:34:26 PM PDT 24 Jun 29 04:35:12 PM PDT 24 16997804566 ps
T310 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.919376909 Jun 29 04:34:55 PM PDT 24 Jun 29 04:35:06 PM PDT 24 185732678 ps
T311 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3855889760 Jun 29 04:34:35 PM PDT 24 Jun 29 04:35:07 PM PDT 24 3831270929 ps
T312 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1884659261 Jun 29 04:34:42 PM PDT 24 Jun 29 04:35:43 PM PDT 24 6719222514 ps
T313 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3736776610 Jun 29 04:34:40 PM PDT 24 Jun 29 04:35:46 PM PDT 24 10431336106 ps
T314 /workspace/coverage/default/28.rom_ctrl_smoke.1269374076 Jun 29 04:34:44 PM PDT 24 Jun 29 04:35:06 PM PDT 24 1383147296 ps
T315 /workspace/coverage/default/22.rom_ctrl_stress_all.962382092 Jun 29 04:35:23 PM PDT 24 Jun 29 04:36:24 PM PDT 24 23845370912 ps
T316 /workspace/coverage/default/41.rom_ctrl_smoke.1928473326 Jun 29 04:35:02 PM PDT 24 Jun 29 04:35:22 PM PDT 24 1692404879 ps
T317 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2574624934 Jun 29 04:34:33 PM PDT 24 Jun 29 04:43:44 PM PDT 24 116024668850 ps
T318 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1981447648 Jun 29 04:35:03 PM PDT 24 Jun 29 04:43:38 PM PDT 24 47899715861 ps
T319 /workspace/coverage/default/32.rom_ctrl_stress_all.4165214513 Jun 29 04:34:46 PM PDT 24 Jun 29 04:35:38 PM PDT 24 3430933010 ps
T320 /workspace/coverage/default/49.rom_ctrl_alert_test.2808863641 Jun 29 04:35:10 PM PDT 24 Jun 29 04:35:32 PM PDT 24 4240336185 ps
T321 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2840887842 Jun 29 04:34:27 PM PDT 24 Jun 29 04:38:39 PM PDT 24 4064062773 ps
T322 /workspace/coverage/default/20.rom_ctrl_smoke.1192813876 Jun 29 04:34:34 PM PDT 24 Jun 29 04:35:18 PM PDT 24 16419518398 ps
T323 /workspace/coverage/default/41.rom_ctrl_alert_test.2626479648 Jun 29 04:35:02 PM PDT 24 Jun 29 04:35:25 PM PDT 24 7158374686 ps
T324 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.4244247921 Jun 29 04:34:44 PM PDT 24 Jun 29 04:35:19 PM PDT 24 4048765568 ps
T325 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1404833350 Jun 29 04:35:09 PM PDT 24 Jun 29 04:38:05 PM PDT 24 4476723625 ps
T326 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1713146880 Jun 29 04:34:51 PM PDT 24 Jun 29 04:37:34 PM PDT 24 17926256181 ps
T327 /workspace/coverage/default/47.rom_ctrl_stress_all.3869548307 Jun 29 04:35:03 PM PDT 24 Jun 29 04:35:19 PM PDT 24 203225358 ps
T328 /workspace/coverage/default/29.rom_ctrl_stress_all.1525105074 Jun 29 04:34:44 PM PDT 24 Jun 29 04:35:36 PM PDT 24 3997365236 ps
T29 /workspace/coverage/default/3.rom_ctrl_sec_cm.1257526108 Jun 29 04:34:03 PM PDT 24 Jun 29 04:37:56 PM PDT 24 2717741480 ps
T329 /workspace/coverage/default/32.rom_ctrl_smoke.676562153 Jun 29 04:34:50 PM PDT 24 Jun 29 04:35:12 PM PDT 24 431872051 ps
T330 /workspace/coverage/default/6.rom_ctrl_alert_test.3405589858 Jun 29 04:34:09 PM PDT 24 Jun 29 04:34:34 PM PDT 24 2933711558 ps
T331 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1755359311 Jun 29 04:34:38 PM PDT 24 Jun 29 04:42:30 PM PDT 24 178449213748 ps
T332 /workspace/coverage/default/29.rom_ctrl_alert_test.809297357 Jun 29 04:34:43 PM PDT 24 Jun 29 04:35:17 PM PDT 24 4419667314 ps
T333 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2297812109 Jun 29 04:34:03 PM PDT 24 Jun 29 04:42:29 PM PDT 24 226454837661 ps
T334 /workspace/coverage/default/2.rom_ctrl_smoke.237354731 Jun 29 04:34:00 PM PDT 24 Jun 29 04:34:57 PM PDT 24 6523013582 ps
T335 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1029693148 Jun 29 04:34:52 PM PDT 24 Jun 29 04:40:32 PM PDT 24 109748222526 ps
T48 /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.889311042 Jun 29 04:34:27 PM PDT 24 Jun 29 07:04:08 PM PDT 24 44863840852 ps
T336 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.776121745 Jun 29 04:34:37 PM PDT 24 Jun 29 04:34:49 PM PDT 24 177779508 ps
T337 /workspace/coverage/default/43.rom_ctrl_alert_test.3431775121 Jun 29 04:35:02 PM PDT 24 Jun 29 04:35:34 PM PDT 24 26347177374 ps
T338 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.393866911 Jun 29 04:34:35 PM PDT 24 Jun 29 04:35:34 PM PDT 24 6963860252 ps
T339 /workspace/coverage/default/18.rom_ctrl_smoke.3330189621 Jun 29 04:34:31 PM PDT 24 Jun 29 04:35:38 PM PDT 24 5305653285 ps
T340 /workspace/coverage/default/38.rom_ctrl_smoke.2678276740 Jun 29 04:34:53 PM PDT 24 Jun 29 04:35:49 PM PDT 24 5313169914 ps
T341 /workspace/coverage/default/7.rom_ctrl_alert_test.2517516895 Jun 29 04:34:15 PM PDT 24 Jun 29 04:34:43 PM PDT 24 17758922568 ps
T342 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1330572771 Jun 29 04:35:04 PM PDT 24 Jun 29 04:35:38 PM PDT 24 2235955054 ps
T343 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3731413142 Jun 29 04:34:47 PM PDT 24 Jun 29 04:35:02 PM PDT 24 603850523 ps
T344 /workspace/coverage/default/14.rom_ctrl_smoke.3428708371 Jun 29 04:34:26 PM PDT 24 Jun 29 04:35:40 PM PDT 24 42460490793 ps
T345 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2984317661 Jun 29 04:34:08 PM PDT 24 Jun 29 04:48:19 PM PDT 24 171221170747 ps
T346 /workspace/coverage/default/48.rom_ctrl_alert_test.43138817 Jun 29 04:35:11 PM PDT 24 Jun 29 04:35:29 PM PDT 24 5826431099 ps
T347 /workspace/coverage/default/3.rom_ctrl_smoke.1744212120 Jun 29 04:34:00 PM PDT 24 Jun 29 04:35:06 PM PDT 24 7179595563 ps
T348 /workspace/coverage/default/21.rom_ctrl_stress_all.2616884968 Jun 29 04:34:37 PM PDT 24 Jun 29 04:35:01 PM PDT 24 560991480 ps
T349 /workspace/coverage/default/10.rom_ctrl_stress_all.1717809708 Jun 29 04:34:14 PM PDT 24 Jun 29 04:37:42 PM PDT 24 100202881471 ps
T350 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.329878048 Jun 29 04:34:26 PM PDT 24 Jun 29 04:35:21 PM PDT 24 21099604633 ps
T351 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.69402266 Jun 29 04:35:00 PM PDT 24 Jun 29 04:35:30 PM PDT 24 3443776131 ps
T352 /workspace/coverage/default/39.rom_ctrl_smoke.3280675741 Jun 29 04:34:52 PM PDT 24 Jun 29 04:35:45 PM PDT 24 7382255198 ps
T353 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2009651004 Jun 29 04:34:34 PM PDT 24 Jun 29 04:34:44 PM PDT 24 176896186 ps
T354 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3759124724 Jun 29 04:34:40 PM PDT 24 Jun 29 04:34:51 PM PDT 24 2155643341 ps
T355 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2564362000 Jun 29 04:34:48 PM PDT 24 Jun 29 04:35:19 PM PDT 24 1650898033 ps
T356 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1493724795 Jun 29 04:35:13 PM PDT 24 Jun 29 04:36:01 PM PDT 24 5039334738 ps
T357 /workspace/coverage/default/30.rom_ctrl_smoke.1446958630 Jun 29 04:34:44 PM PDT 24 Jun 29 04:35:05 PM PDT 24 348341961 ps
T358 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2859334071 Jun 29 04:34:46 PM PDT 24 Jun 29 04:35:35 PM PDT 24 44574404754 ps
T359 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3996864985 Jun 29 04:35:02 PM PDT 24 Jun 29 04:35:38 PM PDT 24 4348858817 ps
T360 /workspace/coverage/default/15.rom_ctrl_smoke.1961597823 Jun 29 04:34:28 PM PDT 24 Jun 29 04:34:49 PM PDT 24 367151781 ps
T361 /workspace/coverage/default/37.rom_ctrl_alert_test.2270612734 Jun 29 04:34:49 PM PDT 24 Jun 29 04:35:19 PM PDT 24 13975068198 ps
T362 /workspace/coverage/default/20.rom_ctrl_stress_all.1310754190 Jun 29 04:34:39 PM PDT 24 Jun 29 04:35:52 PM PDT 24 14584718729 ps
T49 /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1139021417 Jun 29 04:34:51 PM PDT 24 Jun 29 04:49:37 PM PDT 24 22447206692 ps
T61 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.4269530990 Jun 29 05:23:03 PM PDT 24 Jun 29 05:23:37 PM PDT 24 19451398116 ps
T363 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1438565654 Jun 29 05:23:01 PM PDT 24 Jun 29 05:23:24 PM PDT 24 1723764057 ps
T62 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1092409067 Jun 29 05:23:00 PM PDT 24 Jun 29 05:23:33 PM PDT 24 8032572531 ps
T63 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3585432087 Jun 29 05:22:58 PM PDT 24 Jun 29 05:23:28 PM PDT 24 11958337836 ps
T58 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1129206494 Jun 29 05:23:04 PM PDT 24 Jun 29 05:25:40 PM PDT 24 359242301 ps
T100 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3848974454 Jun 29 05:22:59 PM PDT 24 Jun 29 05:23:30 PM PDT 24 7537411163 ps
T102 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4158246578 Jun 29 05:23:10 PM PDT 24 Jun 29 05:23:19 PM PDT 24 2351156519 ps
T364 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4057812390 Jun 29 05:22:53 PM PDT 24 Jun 29 05:23:13 PM PDT 24 13027804034 ps
T365 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.384030966 Jun 29 05:22:49 PM PDT 24 Jun 29 05:23:15 PM PDT 24 10270972256 ps
T69 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1292700083 Jun 29 05:23:10 PM PDT 24 Jun 29 05:23:19 PM PDT 24 688067876 ps
T59 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1094796425 Jun 29 05:22:49 PM PDT 24 Jun 29 05:25:41 PM PDT 24 2776569822 ps
T366 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1036066106 Jun 29 05:22:48 PM PDT 24 Jun 29 05:23:14 PM PDT 24 10289699910 ps
T367 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.794103299 Jun 29 05:23:10 PM PDT 24 Jun 29 05:23:21 PM PDT 24 360883536 ps
T70 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3901838389 Jun 29 05:23:02 PM PDT 24 Jun 29 05:24:33 PM PDT 24 9586546291 ps
T71 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3598341794 Jun 29 05:23:15 PM PDT 24 Jun 29 05:26:03 PM PDT 24 177397251830 ps
T368 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3488051169 Jun 29 05:23:01 PM PDT 24 Jun 29 05:23:29 PM PDT 24 2728147634 ps
T103 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2858688551 Jun 29 05:23:01 PM PDT 24 Jun 29 05:23:27 PM PDT 24 2795285894 ps
T369 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.983409253 Jun 29 05:22:48 PM PDT 24 Jun 29 05:23:15 PM PDT 24 3715859142 ps
T60 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.88937016 Jun 29 05:23:11 PM PDT 24 Jun 29 05:26:00 PM PDT 24 4132850133 ps
T370 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.329205517 Jun 29 05:22:57 PM PDT 24 Jun 29 05:23:10 PM PDT 24 167591300 ps
T371 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1812842889 Jun 29 05:23:00 PM PDT 24 Jun 29 05:23:36 PM PDT 24 15732099214 ps
T372 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2439165208 Jun 29 05:22:54 PM PDT 24 Jun 29 05:23:08 PM PDT 24 167563548 ps
T101 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1468838932 Jun 29 05:22:53 PM PDT 24 Jun 29 05:23:24 PM PDT 24 3994516972 ps
T373 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3862597481 Jun 29 05:23:01 PM PDT 24 Jun 29 05:23:29 PM PDT 24 12061033162 ps
T72 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3013416261 Jun 29 05:22:53 PM PDT 24 Jun 29 05:23:25 PM PDT 24 31325852837 ps
T374 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3300772263 Jun 29 05:23:09 PM PDT 24 Jun 29 05:23:39 PM PDT 24 3478594893 ps
T375 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3662593082 Jun 29 05:23:14 PM PDT 24 Jun 29 05:23:37 PM PDT 24 2216418994 ps
T73 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.499973273 Jun 29 05:22:47 PM PDT 24 Jun 29 05:24:11 PM PDT 24 17892936102 ps
T376 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.762810983 Jun 29 05:22:58 PM PDT 24 Jun 29 05:23:35 PM PDT 24 14468699744 ps
T115 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3213722579 Jun 29 05:23:16 PM PDT 24 Jun 29 05:26:18 PM PDT 24 4415934145 ps
T74 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3323451399 Jun 29 05:22:57 PM PDT 24 Jun 29 05:23:05 PM PDT 24 3291418889 ps
T75 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1486288645 Jun 29 05:23:11 PM PDT 24 Jun 29 05:23:37 PM PDT 24 5756216138 ps
T106 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1303332908 Jun 29 05:23:09 PM PDT 24 Jun 29 05:24:56 PM PDT 24 5839587717 ps
T377 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1077305897 Jun 29 05:23:09 PM PDT 24 Jun 29 05:23:22 PM PDT 24 635994146 ps
T111 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.674987168 Jun 29 05:23:01 PM PDT 24 Jun 29 05:24:40 PM PDT 24 12043416314 ps
T378 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3859125096 Jun 29 05:22:50 PM PDT 24 Jun 29 05:23:22 PM PDT 24 7502894791 ps
T379 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.4006825168 Jun 29 05:22:49 PM PDT 24 Jun 29 05:23:17 PM PDT 24 11844823598 ps
T76 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3278665211 Jun 29 05:22:54 PM PDT 24 Jun 29 05:23:08 PM PDT 24 1915774270 ps
T380 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3544265710 Jun 29 05:22:49 PM PDT 24 Jun 29 05:23:22 PM PDT 24 13282349470 ps
T381 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1574372392 Jun 29 05:22:59 PM PDT 24 Jun 29 05:23:26 PM PDT 24 3172438537 ps
T382 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3616578072 Jun 29 05:22:59 PM PDT 24 Jun 29 05:23:27 PM PDT 24 3101301116 ps
T83 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3502190794 Jun 29 05:23:16 PM PDT 24 Jun 29 05:25:52 PM PDT 24 73939425363 ps
T107 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4035088501 Jun 29 05:22:54 PM PDT 24 Jun 29 05:25:36 PM PDT 24 747931330 ps
T383 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3533989516 Jun 29 05:22:48 PM PDT 24 Jun 29 05:23:21 PM PDT 24 3869309577 ps
T384 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4026968704 Jun 29 05:22:59 PM PDT 24 Jun 29 05:23:34 PM PDT 24 16003984229 ps
T385 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.744485126 Jun 29 05:23:00 PM PDT 24 Jun 29 05:24:46 PM PDT 24 4309443675 ps
T386 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1412432129 Jun 29 05:22:57 PM PDT 24 Jun 29 05:23:32 PM PDT 24 4106345584 ps
T387 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2576318703 Jun 29 05:23:03 PM PDT 24 Jun 29 05:23:42 PM PDT 24 4331875654 ps
T388 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2964181951 Jun 29 05:23:01 PM PDT 24 Jun 29 05:23:24 PM PDT 24 8860455044 ps
T84 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3224301947 Jun 29 05:23:00 PM PDT 24 Jun 29 05:23:39 PM PDT 24 695130300 ps
T389 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2170016765 Jun 29 05:22:53 PM PDT 24 Jun 29 05:23:20 PM PDT 24 2902807512 ps
T390 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.4178601694 Jun 29 05:23:04 PM PDT 24 Jun 29 05:25:40 PM PDT 24 67682660150 ps
T391 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2632876948 Jun 29 05:22:59 PM PDT 24 Jun 29 05:23:30 PM PDT 24 3613264928 ps
T392 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4270828206 Jun 29 05:22:57 PM PDT 24 Jun 29 05:23:18 PM PDT 24 3448089210 ps
T85 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2819989344 Jun 29 05:23:11 PM PDT 24 Jun 29 05:24:39 PM PDT 24 9102868966 ps
T393 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4270400304 Jun 29 05:23:15 PM PDT 24 Jun 29 05:23:28 PM PDT 24 1373558421 ps
T394 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3673334845 Jun 29 05:23:16 PM PDT 24 Jun 29 05:23:39 PM PDT 24 2391319049 ps
T395 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2451650040 Jun 29 05:23:16 PM PDT 24 Jun 29 05:23:51 PM PDT 24 13178590941 ps
T396 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2238339177 Jun 29 05:22:59 PM PDT 24 Jun 29 05:23:24 PM PDT 24 2341248479 ps
T397 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.730866495 Jun 29 05:22:57 PM PDT 24 Jun 29 05:23:17 PM PDT 24 7869360272 ps
T398 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.522258057 Jun 29 05:22:55 PM PDT 24 Jun 29 05:23:31 PM PDT 24 4328889501 ps
T399 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2158252330 Jun 29 05:22:59 PM PDT 24 Jun 29 05:23:13 PM PDT 24 180654717 ps
T112 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.4238740198 Jun 29 05:22:49 PM PDT 24 Jun 29 05:25:28 PM PDT 24 410254735 ps
T400 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1957425405 Jun 29 05:23:10 PM PDT 24 Jun 29 05:23:34 PM PDT 24 4082602702 ps
T86 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3501156484 Jun 29 05:22:53 PM PDT 24 Jun 29 05:23:19 PM PDT 24 14649350709 ps
T109 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2389268212 Jun 29 05:23:03 PM PDT 24 Jun 29 05:25:43 PM PDT 24 3258051998 ps
T401 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2091636555 Jun 29 05:23:00 PM PDT 24 Jun 29 05:23:16 PM PDT 24 10237606130 ps
T402 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.56420440 Jun 29 05:23:02 PM PDT 24 Jun 29 05:23:37 PM PDT 24 3790885988 ps
T403 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1632156008 Jun 29 05:23:00 PM PDT 24 Jun 29 05:23:23 PM PDT 24 3419548272 ps
T404 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.250127015 Jun 29 05:23:01 PM PDT 24 Jun 29 05:26:03 PM PDT 24 25508831244 ps
T405 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1461366393 Jun 29 05:23:09 PM PDT 24 Jun 29 05:25:23 PM PDT 24 25652144674 ps
T406 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1465635303 Jun 29 05:23:00 PM PDT 24 Jun 29 05:23:30 PM PDT 24 3645306155 ps
T407 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1713753202 Jun 29 05:23:14 PM PDT 24 Jun 29 05:23:39 PM PDT 24 10841544733 ps
T118 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2287436107 Jun 29 05:22:50 PM PDT 24 Jun 29 05:25:46 PM PDT 24 3109386353 ps
T408 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.43634002 Jun 29 05:22:58 PM PDT 24 Jun 29 05:23:30 PM PDT 24 3320142661 ps
T87 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3535643787 Jun 29 05:23:08 PM PDT 24 Jun 29 05:23:17 PM PDT 24 339298769 ps
T409 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3231426390 Jun 29 05:23:07 PM PDT 24 Jun 29 05:24:47 PM PDT 24 13333980864 ps
T410 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1913912481 Jun 29 05:22:51 PM PDT 24 Jun 29 05:23:05 PM PDT 24 1031644187 ps
T411 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1153613566 Jun 29 05:23:03 PM PDT 24 Jun 29 05:23:37 PM PDT 24 13373041026 ps
T113 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.100535571 Jun 29 05:22:53 PM PDT 24 Jun 29 05:25:32 PM PDT 24 1626530915 ps
T412 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3763259255 Jun 29 05:23:07 PM PDT 24 Jun 29 05:23:25 PM PDT 24 1494140326 ps
T413 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.92898961 Jun 29 05:22:58 PM PDT 24 Jun 29 05:23:12 PM PDT 24 174661320 ps
T414 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3437944397 Jun 29 05:23:08 PM PDT 24 Jun 29 05:26:33 PM PDT 24 111977713491 ps
T116 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2350371781 Jun 29 05:23:06 PM PDT 24 Jun 29 05:25:57 PM PDT 24 14313194362 ps
T415 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1559846394 Jun 29 05:22:50 PM PDT 24 Jun 29 05:23:08 PM PDT 24 4243578181 ps
T416 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3639104977 Jun 29 05:23:03 PM PDT 24 Jun 29 05:23:12 PM PDT 24 661331290 ps
T417 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.547875182 Jun 29 05:22:58 PM PDT 24 Jun 29 05:23:11 PM PDT 24 2292883464 ps
T418 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2690047323 Jun 29 05:23:02 PM PDT 24 Jun 29 05:23:25 PM PDT 24 10572928264 ps
T419 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2361388698 Jun 29 05:23:01 PM PDT 24 Jun 29 05:23:10 PM PDT 24 1832435012 ps
T420 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3105843577 Jun 29 05:23:11 PM PDT 24 Jun 29 05:23:24 PM PDT 24 170916726 ps
T421 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.579289758 Jun 29 05:23:15 PM PDT 24 Jun 29 05:23:29 PM PDT 24 2747335807 ps
T422 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.863616332 Jun 29 05:23:01 PM PDT 24 Jun 29 05:23:26 PM PDT 24 10473484719 ps
T423 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3734809301 Jun 29 05:23:00 PM PDT 24 Jun 29 05:23:25 PM PDT 24 3549501265 ps
T424 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1530102556 Jun 29 05:22:58 PM PDT 24 Jun 29 05:23:07 PM PDT 24 345286204 ps
T425 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.959628965 Jun 29 05:22:57 PM PDT 24 Jun 29 05:23:29 PM PDT 24 4226729878 ps
T88 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1860885001 Jun 29 05:22:58 PM PDT 24 Jun 29 05:23:55 PM PDT 24 1073351595 ps
T426 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3716508627 Jun 29 05:22:50 PM PDT 24 Jun 29 05:23:25 PM PDT 24 4294934141 ps
T427 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3828071501 Jun 29 05:23:10 PM PDT 24 Jun 29 05:23:20 PM PDT 24 359239416 ps
T428 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3484186982 Jun 29 05:23:11 PM PDT 24 Jun 29 05:23:36 PM PDT 24 10317087111 ps
T429 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1470819914 Jun 29 05:23:17 PM PDT 24 Jun 29 05:23:27 PM PDT 24 181521229 ps
T95 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.4094742656 Jun 29 05:23:06 PM PDT 24 Jun 29 05:24:55 PM PDT 24 34363796540 ps
T430 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2771025590 Jun 29 05:23:16 PM PDT 24 Jun 29 05:23:49 PM PDT 24 21116184944 ps
T96 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2143692511 Jun 29 05:22:50 PM PDT 24 Jun 29 05:23:17 PM PDT 24 3237775143 ps
T110 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4066793151 Jun 29 05:23:01 PM PDT 24 Jun 29 05:24:44 PM PDT 24 3647211166 ps
T431 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.102150476 Jun 29 05:22:59 PM PDT 24 Jun 29 05:24:40 PM PDT 24 3054854661 ps
T432 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1060201968 Jun 29 05:23:01 PM PDT 24 Jun 29 05:23:37 PM PDT 24 5044707370 ps
T433 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1273613807 Jun 29 05:22:53 PM PDT 24 Jun 29 05:23:10 PM PDT 24 179806827 ps
T434 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2645128212 Jun 29 05:22:59 PM PDT 24 Jun 29 05:23:12 PM PDT 24 412137773 ps
T89 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.312600919 Jun 29 05:23:04 PM PDT 24 Jun 29 05:23:16 PM PDT 24 1649924058 ps
T435 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1258359652 Jun 29 05:23:12 PM PDT 24 Jun 29 05:23:33 PM PDT 24 9447860264 ps
T117 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3674655270 Jun 29 05:22:57 PM PDT 24 Jun 29 05:25:35 PM PDT 24 5736643116 ps
T436 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2816877672 Jun 29 05:22:53 PM PDT 24 Jun 29 05:23:03 PM PDT 24 1829989059 ps
T90 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.677175299 Jun 29 05:23:02 PM PDT 24 Jun 29 05:23:11 PM PDT 24 1498073972 ps
T437 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1948149475 Jun 29 05:22:59 PM PDT 24 Jun 29 05:23:52 PM PDT 24 13323893531 ps
T438 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1228808859 Jun 29 05:22:53 PM PDT 24 Jun 29 05:23:24 PM PDT 24 59904870992 ps
T439 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2344602460 Jun 29 05:22:57 PM PDT 24 Jun 29 05:24:58 PM PDT 24 32078552390 ps
T108 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.915768398 Jun 29 05:23:08 PM PDT 24 Jun 29 05:25:50 PM PDT 24 11604920953 ps
T440 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3326307562 Jun 29 05:23:02 PM PDT 24 Jun 29 05:23:36 PM PDT 24 33560677722 ps
T441 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1756096671 Jun 29 05:22:53 PM PDT 24 Jun 29 05:25:35 PM PDT 24 1789704794 ps
T442 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3003065840 Jun 29 05:23:07 PM PDT 24 Jun 29 05:23:16 PM PDT 24 660479929 ps
T443 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1426436915 Jun 29 05:22:47 PM PDT 24 Jun 29 05:22:57 PM PDT 24 353388360 ps
T444 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1117781641 Jun 29 05:23:18 PM PDT 24 Jun 29 05:23:35 PM PDT 24 1243185230 ps
T91 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3449487238 Jun 29 05:22:51 PM PDT 24 Jun 29 05:23:00 PM PDT 24 345649471 ps
T445 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1335585289 Jun 29 05:23:01 PM PDT 24 Jun 29 05:23:18 PM PDT 24 4321520258 ps
T446 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3387107082 Jun 29 05:23:08 PM PDT 24 Jun 29 05:23:20 PM PDT 24 822524828 ps
T447 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3636814938 Jun 29 05:22:54 PM PDT 24 Jun 29 05:23:13 PM PDT 24 1852530433 ps
T448 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.139985184 Jun 29 05:22:48 PM PDT 24 Jun 29 05:23:06 PM PDT 24 1517092446 ps
T97 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3964234334 Jun 29 05:23:04 PM PDT 24 Jun 29 05:23:34 PM PDT 24 7679084834 ps
T98 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.4145049132 Jun 29 05:23:10 PM PDT 24 Jun 29 05:25:27 PM PDT 24 96523157846 ps
T449 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2337026567 Jun 29 05:22:55 PM PDT 24 Jun 29 05:24:20 PM PDT 24 4065088550 ps
T450 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3245285670 Jun 29 05:22:58 PM PDT 24 Jun 29 05:23:26 PM PDT 24 12661966712 ps
T92 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3508491496 Jun 29 05:22:56 PM PDT 24 Jun 29 05:25:29 PM PDT 24 15440188699 ps
T451 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1980148697 Jun 29 05:22:59 PM PDT 24 Jun 29 05:23:33 PM PDT 24 7346265654 ps
T93 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1401617063 Jun 29 05:22:55 PM PDT 24 Jun 29 05:23:22 PM PDT 24 2298531922 ps
T452 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.883204837 Jun 29 05:23:09 PM PDT 24 Jun 29 05:23:23 PM PDT 24 346600346 ps
T453 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1415428231 Jun 29 05:23:01 PM PDT 24 Jun 29 05:23:10 PM PDT 24 2061858986 ps
T454 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.718285606 Jun 29 05:22:56 PM PDT 24 Jun 29 05:23:29 PM PDT 24 24052865461 ps
T94 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3301261756 Jun 29 05:22:58 PM PDT 24 Jun 29 05:25:34 PM PDT 24 34731134080 ps
T455 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.507425534 Jun 29 05:23:09 PM PDT 24 Jun 29 05:23:24 PM PDT 24 1120891154 ps
T114 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3020150051 Jun 29 05:23:06 PM PDT 24 Jun 29 05:25:52 PM PDT 24 1925508333 ps
T456 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3037305449 Jun 29 05:22:54 PM PDT 24 Jun 29 05:23:05 PM PDT 24 633725842 ps
T457 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4285992740 Jun 29 05:23:05 PM PDT 24 Jun 29 05:23:17 PM PDT 24 601462991 ps
T458 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2116687339 Jun 29 05:22:54 PM PDT 24 Jun 29 05:25:48 PM PDT 24 21881246921 ps
T459 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.218230560 Jun 29 05:22:54 PM PDT 24 Jun 29 05:23:19 PM PDT 24 11254939574 ps
T99 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.40636905 Jun 29 05:23:01 PM PDT 24 Jun 29 05:24:20 PM PDT 24 23209772680 ps

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1710989012
Short name T8
Test name
Test status
Simulation time 164225636820 ps
CPU time 173.39 seconds
Started Jun 29 04:34:25 PM PDT 24
Finished Jun 29 04:37:19 PM PDT 24
Peak memory 220800 kb
Host smart-a7a9972a-7219-4fc7-af86-aff52d584e0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710989012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1710989012
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.769793742
Short name T23
Test name
Test status
Simulation time 54404295839 ps
CPU time 542.56 seconds
Started Jun 29 04:34:12 PM PDT 24
Finished Jun 29 04:43:15 PM PDT 24
Peak memory 238836 kb
Host smart-b107e328-0ea1-4689-a9b3-d30571e02b8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769793742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.769793742
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3078431307
Short name T17
Test name
Test status
Simulation time 157907538977 ps
CPU time 3074.8 seconds
Started Jun 29 04:34:30 PM PDT 24
Finished Jun 29 05:25:46 PM PDT 24
Peak memory 252092 kb
Host smart-44d93ceb-6988-4e72-9f91-cf7853da4da1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078431307 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.3078431307
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2810086906
Short name T12
Test name
Test status
Simulation time 309926383 ps
CPU time 227.22 seconds
Started Jun 29 04:34:00 PM PDT 24
Finished Jun 29 04:37:47 PM PDT 24
Peak memory 238036 kb
Host smart-c483b3ec-8f59-40d0-98c7-049d1b83642e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810086906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2810086906
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3153712281
Short name T41
Test name
Test status
Simulation time 1201419604 ps
CPU time 15.6 seconds
Started Jun 29 04:34:00 PM PDT 24
Finished Jun 29 04:34:16 PM PDT 24
Peak memory 213124 kb
Host smart-b2b1747d-6757-456e-bc8c-83b83eb76681
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153712281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3153712281
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1094796425
Short name T59
Test name
Test status
Simulation time 2776569822 ps
CPU time 170.01 seconds
Started Jun 29 05:22:49 PM PDT 24
Finished Jun 29 05:25:41 PM PDT 24
Peak memory 213960 kb
Host smart-f5062235-27b6-4f51-91b1-b7169d60cbd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094796425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1094796425
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.514908390
Short name T21
Test name
Test status
Simulation time 36108999698 ps
CPU time 123.46 seconds
Started Jun 29 04:34:54 PM PDT 24
Finished Jun 29 04:36:58 PM PDT 24
Peak memory 220264 kb
Host smart-ce750cd7-756d-4ae2-80e3-8dd6b9f37b1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514908390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.514908390
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.4073453752
Short name T11
Test name
Test status
Simulation time 2300389772 ps
CPU time 20.28 seconds
Started Jun 29 04:34:24 PM PDT 24
Finished Jun 29 04:34:45 PM PDT 24
Peak memory 216936 kb
Host smart-d8c8c29e-774f-4282-b416-eda476c0a02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073453752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.4073453752
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.499973273
Short name T73
Test name
Test status
Simulation time 17892936102 ps
CPU time 82.16 seconds
Started Jun 29 05:22:47 PM PDT 24
Finished Jun 29 05:24:11 PM PDT 24
Peak memory 215468 kb
Host smart-7dab681c-136a-4a33-9f10-6dc624f049f6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499973273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.499973273
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3259249639
Short name T43
Test name
Test status
Simulation time 66331990266 ps
CPU time 561.16 seconds
Started Jun 29 04:35:03 PM PDT 24
Finished Jun 29 04:44:25 PM PDT 24
Peak memory 238792 kb
Host smart-a511f078-9981-45d1-90c7-e72523426f34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259249639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3259249639
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.4268431065
Short name T119
Test name
Test status
Simulation time 19368297968 ps
CPU time 35.14 seconds
Started Jun 29 04:34:13 PM PDT 24
Finished Jun 29 04:34:49 PM PDT 24
Peak memory 219616 kb
Host smart-e0db53a5-d136-433d-8eeb-941df0345686
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4268431065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.4268431065
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.214714655
Short name T30
Test name
Test status
Simulation time 36744253497 ps
CPU time 59.13 seconds
Started Jun 29 04:34:28 PM PDT 24
Finished Jun 29 04:35:28 PM PDT 24
Peak memory 219260 kb
Host smart-619b0595-babe-4b0a-a680-b8069666aef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214714655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.214714655
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3163026946
Short name T39
Test name
Test status
Simulation time 2995905670 ps
CPU time 19.05 seconds
Started Jun 29 04:34:14 PM PDT 24
Finished Jun 29 04:34:34 PM PDT 24
Peak memory 219236 kb
Host smart-d66170c3-2f47-4de6-8338-633d4afd6b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163026946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3163026946
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2350371781
Short name T116
Test name
Test status
Simulation time 14313194362 ps
CPU time 170.7 seconds
Started Jun 29 05:23:06 PM PDT 24
Finished Jun 29 05:25:57 PM PDT 24
Peak memory 214288 kb
Host smart-c01c63ed-7091-40af-9b17-35d123f56b89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350371781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2350371781
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.88937016
Short name T60
Test name
Test status
Simulation time 4132850133 ps
CPU time 167.88 seconds
Started Jun 29 05:23:11 PM PDT 24
Finished Jun 29 05:26:00 PM PDT 24
Peak memory 214100 kb
Host smart-ebf226cd-eab9-4cee-8e22-2e21fd2c8f58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88937016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_int
g_err.88937016
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.674987168
Short name T111
Test name
Test status
Simulation time 12043416314 ps
CPU time 98.76 seconds
Started Jun 29 05:23:01 PM PDT 24
Finished Jun 29 05:24:40 PM PDT 24
Peak memory 213608 kb
Host smart-98cf2c49-ec1e-4ea4-b305-a31f9218592b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674987168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.674987168
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1129206494
Short name T58
Test name
Test status
Simulation time 359242301 ps
CPU time 155.98 seconds
Started Jun 29 05:23:04 PM PDT 24
Finished Jun 29 05:25:40 PM PDT 24
Peak memory 214200 kb
Host smart-747a0976-a666-49ac-9822-c0b4827ad11e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129206494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1129206494
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.915768398
Short name T108
Test name
Test status
Simulation time 11604920953 ps
CPU time 161.88 seconds
Started Jun 29 05:23:08 PM PDT 24
Finished Jun 29 05:25:50 PM PDT 24
Peak memory 214248 kb
Host smart-0ce12bf5-3ce8-443a-a43b-86a2a737bf81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915768398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.915768398
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.4294221661
Short name T148
Test name
Test status
Simulation time 1434637590 ps
CPU time 17.11 seconds
Started Jun 29 04:34:15 PM PDT 24
Finished Jun 29 04:34:33 PM PDT 24
Peak memory 217008 kb
Host smart-eb8af269-be32-4c3c-8094-597df1f01672
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294221661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.4294221661
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.677175299
Short name T90
Test name
Test status
Simulation time 1498073972 ps
CPU time 8.34 seconds
Started Jun 29 05:23:02 PM PDT 24
Finished Jun 29 05:23:11 PM PDT 24
Peak memory 210760 kb
Host smart-de76156e-9d23-46ea-acbf-33de9a8e2807
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677175299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.677175299
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2858688551
Short name T103
Test name
Test status
Simulation time 2795285894 ps
CPU time 24.69 seconds
Started Jun 29 05:23:01 PM PDT 24
Finished Jun 29 05:23:27 PM PDT 24
Peak memory 211964 kb
Host smart-fa9b5514-1b60-418d-9f5d-cc794b41d54d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858688551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2858688551
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3428152563
Short name T19
Test name
Test status
Simulation time 159136047702 ps
CPU time 3243.76 seconds
Started Jun 29 04:35:01 PM PDT 24
Finished Jun 29 05:29:05 PM PDT 24
Peak memory 245688 kb
Host smart-effd84a2-a396-48e4-b0a8-c0d8a2bc1e24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428152563 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.3428152563
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1036066106
Short name T366
Test name
Test status
Simulation time 10289699910 ps
CPU time 24.41 seconds
Started Jun 29 05:22:48 PM PDT 24
Finished Jun 29 05:23:14 PM PDT 24
Peak memory 212308 kb
Host smart-b1e5d809-4e33-43c2-a92b-483220cb2994
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036066106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1036066106
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3544265710
Short name T380
Test name
Test status
Simulation time 13282349470 ps
CPU time 31.99 seconds
Started Jun 29 05:22:49 PM PDT 24
Finished Jun 29 05:23:22 PM PDT 24
Peak memory 212028 kb
Host smart-62f9cac3-6969-42b7-aaf2-ee7f5e21181b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544265710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3544265710
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1426436915
Short name T443
Test name
Test status
Simulation time 353388360 ps
CPU time 8.46 seconds
Started Jun 29 05:22:47 PM PDT 24
Finished Jun 29 05:22:57 PM PDT 24
Peak memory 213756 kb
Host smart-31646aa4-f84d-4a19-9e1e-6500de464d3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426436915 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1426436915
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3013416261
Short name T72
Test name
Test status
Simulation time 31325852837 ps
CPU time 31.11 seconds
Started Jun 29 05:22:53 PM PDT 24
Finished Jun 29 05:23:25 PM PDT 24
Peak memory 212496 kb
Host smart-8c0e6e88-51ce-44ba-a2eb-98fc297b752e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013416261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3013416261
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2964181951
Short name T388
Test name
Test status
Simulation time 8860455044 ps
CPU time 22.28 seconds
Started Jun 29 05:23:01 PM PDT 24
Finished Jun 29 05:23:24 PM PDT 24
Peak memory 210644 kb
Host smart-041e10b8-d99e-4f68-9af4-704f6c376b00
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964181951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2964181951
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.4006825168
Short name T379
Test name
Test status
Simulation time 11844823598 ps
CPU time 26.32 seconds
Started Jun 29 05:22:49 PM PDT 24
Finished Jun 29 05:23:17 PM PDT 24
Peak memory 210892 kb
Host smart-556bcacf-a0b8-4517-a4a8-ab7b58f25c72
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006825168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.4006825168
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3301261756
Short name T94
Test name
Test status
Simulation time 34731134080 ps
CPU time 155.81 seconds
Started Jun 29 05:22:58 PM PDT 24
Finished Jun 29 05:25:34 PM PDT 24
Peak memory 215100 kb
Host smart-a8552dd2-7301-4749-a0e8-83bae7344eed
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301261756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3301261756
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3323451399
Short name T74
Test name
Test status
Simulation time 3291418889 ps
CPU time 8.31 seconds
Started Jun 29 05:22:57 PM PDT 24
Finished Jun 29 05:23:05 PM PDT 24
Peak memory 211148 kb
Host smart-6ca95c33-1210-42fa-adab-4d04e995c09f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323451399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3323451399
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.139985184
Short name T448
Test name
Test status
Simulation time 1517092446 ps
CPU time 16.31 seconds
Started Jun 29 05:22:48 PM PDT 24
Finished Jun 29 05:23:06 PM PDT 24
Peak memory 217424 kb
Host smart-f0a1950d-2598-41fe-8eb9-7473e072830c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139985184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.139985184
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3449487238
Short name T91
Test name
Test status
Simulation time 345649471 ps
CPU time 8.31 seconds
Started Jun 29 05:22:51 PM PDT 24
Finished Jun 29 05:23:00 PM PDT 24
Peak memory 210996 kb
Host smart-7fd2f73a-4177-4808-83b1-c6e19619c674
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449487238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3449487238
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1559846394
Short name T415
Test name
Test status
Simulation time 4243578181 ps
CPU time 15.68 seconds
Started Jun 29 05:22:50 PM PDT 24
Finished Jun 29 05:23:08 PM PDT 24
Peak memory 210832 kb
Host smart-01851b0a-4f83-4bfc-9259-bc58084037ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559846394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1559846394
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1273613807
Short name T433
Test name
Test status
Simulation time 179806827 ps
CPU time 15.77 seconds
Started Jun 29 05:22:53 PM PDT 24
Finished Jun 29 05:23:10 PM PDT 24
Peak memory 211772 kb
Host smart-788e110e-ffd0-4e7c-b1fe-53c9558a5fa1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273613807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1273613807
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3716508627
Short name T426
Test name
Test status
Simulation time 4294934141 ps
CPU time 33.44 seconds
Started Jun 29 05:22:50 PM PDT 24
Finished Jun 29 05:23:25 PM PDT 24
Peak memory 219020 kb
Host smart-63559ecb-70e4-4803-b732-06c10b3fa0f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716508627 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3716508627
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3859125096
Short name T378
Test name
Test status
Simulation time 7502894791 ps
CPU time 29.72 seconds
Started Jun 29 05:22:50 PM PDT 24
Finished Jun 29 05:23:22 PM PDT 24
Peak memory 210960 kb
Host smart-4e370018-dc1c-48e2-be1f-73b3a095c296
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859125096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3859125096
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.384030966
Short name T365
Test name
Test status
Simulation time 10270972256 ps
CPU time 24.07 seconds
Started Jun 29 05:22:49 PM PDT 24
Finished Jun 29 05:23:15 PM PDT 24
Peak memory 210596 kb
Host smart-ec0a7d35-4d6c-45ba-8514-c6deb325ac70
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384030966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
384030966
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3848974454
Short name T100
Test name
Test status
Simulation time 7537411163 ps
CPU time 30.37 seconds
Started Jun 29 05:22:59 PM PDT 24
Finished Jun 29 05:23:30 PM PDT 24
Peak memory 212828 kb
Host smart-3b48f7e8-7bd9-489d-ab62-9f50de598221
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848974454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3848974454
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1913912481
Short name T410
Test name
Test status
Simulation time 1031644187 ps
CPU time 13.4 seconds
Started Jun 29 05:22:51 PM PDT 24
Finished Jun 29 05:23:05 PM PDT 24
Peak memory 217440 kb
Host smart-63d97956-7177-4dcf-bcc1-8abf1ca09881
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913912481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1913912481
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.4238740198
Short name T112
Test name
Test status
Simulation time 410254735 ps
CPU time 157.03 seconds
Started Jun 29 05:22:49 PM PDT 24
Finished Jun 29 05:25:28 PM PDT 24
Peak memory 214112 kb
Host smart-ac710059-16a5-4c55-a41a-1f684f66c075
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238740198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.4238740198
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3488051169
Short name T368
Test name
Test status
Simulation time 2728147634 ps
CPU time 26.69 seconds
Started Jun 29 05:23:01 PM PDT 24
Finished Jun 29 05:23:29 PM PDT 24
Peak memory 218216 kb
Host smart-a8a9888e-35ce-4eb9-bacb-0e5d475e7ebd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488051169 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3488051169
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.312600919
Short name T89
Test name
Test status
Simulation time 1649924058 ps
CPU time 12 seconds
Started Jun 29 05:23:04 PM PDT 24
Finished Jun 29 05:23:16 PM PDT 24
Peak memory 210604 kb
Host smart-e03c06c2-1f18-40f0-8a26-fede0f705e07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312600919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.312600919
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.4178601694
Short name T390
Test name
Test status
Simulation time 67682660150 ps
CPU time 155.42 seconds
Started Jun 29 05:23:04 PM PDT 24
Finished Jun 29 05:25:40 PM PDT 24
Peak memory 215140 kb
Host smart-77f034f2-8ecc-4cb1-b8f3-d271f31c09da
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178601694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.4178601694
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.56420440
Short name T402
Test name
Test status
Simulation time 3790885988 ps
CPU time 34.24 seconds
Started Jun 29 05:23:02 PM PDT 24
Finished Jun 29 05:23:37 PM PDT 24
Peak memory 212388 kb
Host smart-64a7d497-fbb2-4e95-ae33-10c63027fe1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56420440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ct
rl_same_csr_outstanding.56420440
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1153613566
Short name T411
Test name
Test status
Simulation time 13373041026 ps
CPU time 33.14 seconds
Started Jun 29 05:23:03 PM PDT 24
Finished Jun 29 05:23:37 PM PDT 24
Peak memory 218920 kb
Host smart-d179bec4-ce33-498f-a175-697bf91fb5d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153613566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1153613566
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2690047323
Short name T418
Test name
Test status
Simulation time 10572928264 ps
CPU time 22.07 seconds
Started Jun 29 05:23:02 PM PDT 24
Finished Jun 29 05:23:25 PM PDT 24
Peak memory 219020 kb
Host smart-2b404fe0-aa7e-48f9-8e8a-b0f8e1306342
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690047323 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2690047323
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1092409067
Short name T62
Test name
Test status
Simulation time 8032572531 ps
CPU time 31.55 seconds
Started Jun 29 05:23:00 PM PDT 24
Finished Jun 29 05:23:33 PM PDT 24
Peak memory 212488 kb
Host smart-94081986-a746-4d85-bb54-e75996a23aa7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092409067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1092409067
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3901838389
Short name T70
Test name
Test status
Simulation time 9586546291 ps
CPU time 90.24 seconds
Started Jun 29 05:23:02 PM PDT 24
Finished Jun 29 05:24:33 PM PDT 24
Peak memory 214908 kb
Host smart-315ef9bb-d6df-4cf8-a243-9a85d6359eaa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901838389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3901838389
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3639104977
Short name T416
Test name
Test status
Simulation time 661331290 ps
CPU time 8.63 seconds
Started Jun 29 05:23:03 PM PDT 24
Finished Jun 29 05:23:12 PM PDT 24
Peak memory 211160 kb
Host smart-435da2a9-137b-4fea-bf3b-105ff9036d21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639104977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3639104977
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3105843577
Short name T420
Test name
Test status
Simulation time 170916726 ps
CPU time 12.27 seconds
Started Jun 29 05:23:11 PM PDT 24
Finished Jun 29 05:23:24 PM PDT 24
Peak memory 216432 kb
Host smart-4b92bafa-dc8b-4b94-b23d-8c521da302d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105843577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3105843577
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3862597481
Short name T373
Test name
Test status
Simulation time 12061033162 ps
CPU time 26.13 seconds
Started Jun 29 05:23:01 PM PDT 24
Finished Jun 29 05:23:29 PM PDT 24
Peak memory 216036 kb
Host smart-a589f733-6370-4525-9645-df15268765b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862597481 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3862597481
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3964234334
Short name T97
Test name
Test status
Simulation time 7679084834 ps
CPU time 29.71 seconds
Started Jun 29 05:23:04 PM PDT 24
Finished Jun 29 05:23:34 PM PDT 24
Peak memory 212096 kb
Host smart-6a664d40-7a20-459e-9f79-7c853dd9563b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964234334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3964234334
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.40636905
Short name T99
Test name
Test status
Simulation time 23209772680 ps
CPU time 77.93 seconds
Started Jun 29 05:23:01 PM PDT 24
Finished Jun 29 05:24:20 PM PDT 24
Peak memory 213820 kb
Host smart-cfa9c4c6-df12-46b1-9e68-27f7248b1ff1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40636905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pas
sthru_mem_tl_intg_err.40636905
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.4269530990
Short name T61
Test name
Test status
Simulation time 19451398116 ps
CPU time 33.6 seconds
Started Jun 29 05:23:03 PM PDT 24
Finished Jun 29 05:23:37 PM PDT 24
Peak memory 212608 kb
Host smart-c8970f9d-7472-420e-8d4b-119e5887e11f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269530990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.4269530990
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1812842889
Short name T371
Test name
Test status
Simulation time 15732099214 ps
CPU time 34.81 seconds
Started Jun 29 05:23:00 PM PDT 24
Finished Jun 29 05:23:36 PM PDT 24
Peak memory 218796 kb
Host smart-6afb751b-71a8-422c-a4ab-5049adcb00be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812842889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1812842889
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3300772263
Short name T374
Test name
Test status
Simulation time 3478594893 ps
CPU time 29.27 seconds
Started Jun 29 05:23:09 PM PDT 24
Finished Jun 29 05:23:39 PM PDT 24
Peak memory 214744 kb
Host smart-3a4d3001-6fb4-4214-8512-ce4d04d6f7bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300772263 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3300772263
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4285992740
Short name T457
Test name
Test status
Simulation time 601462991 ps
CPU time 12.39 seconds
Started Jun 29 05:23:05 PM PDT 24
Finished Jun 29 05:23:17 PM PDT 24
Peak memory 210796 kb
Host smart-5ac524ea-7830-4ad7-b83b-20dd3f121386
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285992740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.4285992740
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.4094742656
Short name T95
Test name
Test status
Simulation time 34363796540 ps
CPU time 109.18 seconds
Started Jun 29 05:23:06 PM PDT 24
Finished Jun 29 05:24:55 PM PDT 24
Peak memory 215212 kb
Host smart-d24e76c6-6a01-4902-ae7d-99adc14a8ab3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094742656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.4094742656
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3326307562
Short name T440
Test name
Test status
Simulation time 33560677722 ps
CPU time 33.28 seconds
Started Jun 29 05:23:02 PM PDT 24
Finished Jun 29 05:23:36 PM PDT 24
Peak memory 212880 kb
Host smart-7994ead7-8724-452f-9583-b07a2b9289cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326307562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3326307562
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1438565654
Short name T363
Test name
Test status
Simulation time 1723764057 ps
CPU time 21.19 seconds
Started Jun 29 05:23:01 PM PDT 24
Finished Jun 29 05:23:24 PM PDT 24
Peak memory 218264 kb
Host smart-fcf7dabe-1adc-4825-b256-fca8126714cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438565654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1438565654
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2389268212
Short name T109
Test name
Test status
Simulation time 3258051998 ps
CPU time 159.73 seconds
Started Jun 29 05:23:03 PM PDT 24
Finished Jun 29 05:25:43 PM PDT 24
Peak memory 213852 kb
Host smart-6108df4d-91b4-49ac-be54-2f7f07875fca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389268212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2389268212
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3484186982
Short name T428
Test name
Test status
Simulation time 10317087111 ps
CPU time 24.26 seconds
Started Jun 29 05:23:11 PM PDT 24
Finished Jun 29 05:23:36 PM PDT 24
Peak memory 218220 kb
Host smart-630bb166-b021-4212-84a9-70eb33bbaffa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484186982 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3484186982
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3535643787
Short name T87
Test name
Test status
Simulation time 339298769 ps
CPU time 8.43 seconds
Started Jun 29 05:23:08 PM PDT 24
Finished Jun 29 05:23:17 PM PDT 24
Peak memory 210708 kb
Host smart-b069f867-18af-4bec-ab22-4a7574a5738e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535643787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3535643787
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3598341794
Short name T71
Test name
Test status
Simulation time 177397251830 ps
CPU time 166.55 seconds
Started Jun 29 05:23:15 PM PDT 24
Finished Jun 29 05:26:03 PM PDT 24
Peak memory 215000 kb
Host smart-e0b29ba7-790d-40d5-8ce0-cfa065577191
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598341794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3598341794
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3387107082
Short name T446
Test name
Test status
Simulation time 822524828 ps
CPU time 11.35 seconds
Started Jun 29 05:23:08 PM PDT 24
Finished Jun 29 05:23:20 PM PDT 24
Peak memory 211248 kb
Host smart-b328b3ce-f2eb-4ce1-a093-39d0296325ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387107082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3387107082
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.883204837
Short name T452
Test name
Test status
Simulation time 346600346 ps
CPU time 14.06 seconds
Started Jun 29 05:23:09 PM PDT 24
Finished Jun 29 05:23:23 PM PDT 24
Peak memory 215972 kb
Host smart-07bf91b6-a5c9-4f39-95cd-58ea8a667a3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883204837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.883204837
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.794103299
Short name T367
Test name
Test status
Simulation time 360883536 ps
CPU time 9.92 seconds
Started Jun 29 05:23:10 PM PDT 24
Finished Jun 29 05:23:21 PM PDT 24
Peak memory 217616 kb
Host smart-d991dd87-5252-45c7-9b1a-7bcdefd106ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794103299 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.794103299
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.507425534
Short name T455
Test name
Test status
Simulation time 1120891154 ps
CPU time 14.56 seconds
Started Jun 29 05:23:09 PM PDT 24
Finished Jun 29 05:23:24 PM PDT 24
Peak memory 210736 kb
Host smart-63a326f5-bee3-4988-91cc-4b9ad0033c38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507425534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.507425534
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3437944397
Short name T414
Test name
Test status
Simulation time 111977713491 ps
CPU time 203.72 seconds
Started Jun 29 05:23:08 PM PDT 24
Finished Jun 29 05:26:33 PM PDT 24
Peak memory 216236 kb
Host smart-2996aa80-0fb3-498b-9b8c-4edd9dcea556
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437944397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3437944397
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3673334845
Short name T394
Test name
Test status
Simulation time 2391319049 ps
CPU time 22.15 seconds
Started Jun 29 05:23:16 PM PDT 24
Finished Jun 29 05:23:39 PM PDT 24
Peak memory 212484 kb
Host smart-23d048d2-196e-42c8-b228-601211d13681
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673334845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3673334845
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1957425405
Short name T400
Test name
Test status
Simulation time 4082602702 ps
CPU time 23.57 seconds
Started Jun 29 05:23:10 PM PDT 24
Finished Jun 29 05:23:34 PM PDT 24
Peak memory 217460 kb
Host smart-13519c6a-ce9e-4857-bd46-efa5908edd22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957425405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1957425405
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3020150051
Short name T114
Test name
Test status
Simulation time 1925508333 ps
CPU time 165.24 seconds
Started Jun 29 05:23:06 PM PDT 24
Finished Jun 29 05:25:52 PM PDT 24
Peak memory 213856 kb
Host smart-f173b72d-f30e-4ee7-9ef2-48c4b502403a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020150051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3020150051
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3828071501
Short name T427
Test name
Test status
Simulation time 359239416 ps
CPU time 8.92 seconds
Started Jun 29 05:23:10 PM PDT 24
Finished Jun 29 05:23:20 PM PDT 24
Peak memory 216732 kb
Host smart-2c11db62-8a2f-402a-a981-538a06df1c1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828071501 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3828071501
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4158246578
Short name T102
Test name
Test status
Simulation time 2351156519 ps
CPU time 8.34 seconds
Started Jun 29 05:23:10 PM PDT 24
Finished Jun 29 05:23:19 PM PDT 24
Peak memory 210876 kb
Host smart-ec262ef0-0700-4e8b-9b17-c04b3e9c9fbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158246578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.4158246578
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.4145049132
Short name T98
Test name
Test status
Simulation time 96523157846 ps
CPU time 136.15 seconds
Started Jun 29 05:23:10 PM PDT 24
Finished Jun 29 05:25:27 PM PDT 24
Peak memory 213844 kb
Host smart-e6939227-bff8-401a-b298-83bff4bbfa04
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145049132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.4145049132
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3003065840
Short name T442
Test name
Test status
Simulation time 660479929 ps
CPU time 8.2 seconds
Started Jun 29 05:23:07 PM PDT 24
Finished Jun 29 05:23:16 PM PDT 24
Peak memory 211192 kb
Host smart-d5fc9462-c2d2-4a3e-8dcc-9fe9f92dedaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003065840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3003065840
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1077305897
Short name T377
Test name
Test status
Simulation time 635994146 ps
CPU time 11.59 seconds
Started Jun 29 05:23:09 PM PDT 24
Finished Jun 29 05:23:22 PM PDT 24
Peak memory 217244 kb
Host smart-004b4d4d-8bae-483f-bf19-a01b085e2042
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077305897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1077305897
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1303332908
Short name T106
Test name
Test status
Simulation time 5839587717 ps
CPU time 107.24 seconds
Started Jun 29 05:23:09 PM PDT 24
Finished Jun 29 05:24:56 PM PDT 24
Peak memory 214112 kb
Host smart-946b43cd-23eb-46d3-9109-58134b8511c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303332908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1303332908
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1258359652
Short name T435
Test name
Test status
Simulation time 9447860264 ps
CPU time 20.32 seconds
Started Jun 29 05:23:12 PM PDT 24
Finished Jun 29 05:23:33 PM PDT 24
Peak memory 217948 kb
Host smart-20c92a3d-f2b2-4a5a-ad73-20010303bfae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258359652 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1258359652
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.579289758
Short name T421
Test name
Test status
Simulation time 2747335807 ps
CPU time 12.77 seconds
Started Jun 29 05:23:15 PM PDT 24
Finished Jun 29 05:23:29 PM PDT 24
Peak memory 210872 kb
Host smart-a6fa6ada-956e-41a8-bb91-157fcd24942b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579289758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.579289758
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2819989344
Short name T85
Test name
Test status
Simulation time 9102868966 ps
CPU time 86.95 seconds
Started Jun 29 05:23:11 PM PDT 24
Finished Jun 29 05:24:39 PM PDT 24
Peak memory 215580 kb
Host smart-6c18b695-3fad-469d-99b6-d90cf86e4c73
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819989344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2819989344
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1486288645
Short name T75
Test name
Test status
Simulation time 5756216138 ps
CPU time 25.1 seconds
Started Jun 29 05:23:11 PM PDT 24
Finished Jun 29 05:23:37 PM PDT 24
Peak memory 212784 kb
Host smart-41f84067-e3b0-4392-879a-c76de5300832
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486288645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1486288645
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2771025590
Short name T430
Test name
Test status
Simulation time 21116184944 ps
CPU time 32 seconds
Started Jun 29 05:23:16 PM PDT 24
Finished Jun 29 05:23:49 PM PDT 24
Peak memory 217664 kb
Host smart-37ff7151-19cd-46ff-bf44-022affc62237
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771025590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2771025590
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3231426390
Short name T409
Test name
Test status
Simulation time 13333980864 ps
CPU time 100.02 seconds
Started Jun 29 05:23:07 PM PDT 24
Finished Jun 29 05:24:47 PM PDT 24
Peak memory 213936 kb
Host smart-b202cbeb-a21a-41e1-8748-096c162fdc4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231426390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3231426390
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1117781641
Short name T444
Test name
Test status
Simulation time 1243185230 ps
CPU time 16.28 seconds
Started Jun 29 05:23:18 PM PDT 24
Finished Jun 29 05:23:35 PM PDT 24
Peak memory 213900 kb
Host smart-ba157e02-9445-4c21-a84d-9a4d3464b61d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117781641 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1117781641
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1292700083
Short name T69
Test name
Test status
Simulation time 688067876 ps
CPU time 8.54 seconds
Started Jun 29 05:23:10 PM PDT 24
Finished Jun 29 05:23:19 PM PDT 24
Peak memory 211048 kb
Host smart-ac67539f-abfd-40ab-a1a3-25aad92dc66c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292700083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1292700083
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1461366393
Short name T405
Test name
Test status
Simulation time 25652144674 ps
CPU time 132.89 seconds
Started Jun 29 05:23:09 PM PDT 24
Finished Jun 29 05:25:23 PM PDT 24
Peak memory 214932 kb
Host smart-04eb3688-ab3f-4ca6-adbb-d1192b23f115
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461366393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1461366393
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3763259255
Short name T412
Test name
Test status
Simulation time 1494140326 ps
CPU time 17.79 seconds
Started Jun 29 05:23:07 PM PDT 24
Finished Jun 29 05:23:25 PM PDT 24
Peak memory 212400 kb
Host smart-f9297b8a-4c3f-42c7-bec1-b3623707e583
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763259255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3763259255
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4270400304
Short name T393
Test name
Test status
Simulation time 1373558421 ps
CPU time 11.67 seconds
Started Jun 29 05:23:15 PM PDT 24
Finished Jun 29 05:23:28 PM PDT 24
Peak memory 217468 kb
Host smart-f6b7eccd-86bc-40ce-8494-7e44e07492cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270400304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.4270400304
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1470819914
Short name T429
Test name
Test status
Simulation time 181521229 ps
CPU time 9.01 seconds
Started Jun 29 05:23:17 PM PDT 24
Finished Jun 29 05:23:27 PM PDT 24
Peak memory 218876 kb
Host smart-a4ee9d64-a5cf-468c-ab0a-0997be55a05d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470819914 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1470819914
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3662593082
Short name T375
Test name
Test status
Simulation time 2216418994 ps
CPU time 22.5 seconds
Started Jun 29 05:23:14 PM PDT 24
Finished Jun 29 05:23:37 PM PDT 24
Peak memory 211588 kb
Host smart-14b86717-c63a-4d1b-9834-2df77ac9da1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662593082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3662593082
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3502190794
Short name T83
Test name
Test status
Simulation time 73939425363 ps
CPU time 155.51 seconds
Started Jun 29 05:23:16 PM PDT 24
Finished Jun 29 05:25:52 PM PDT 24
Peak memory 214864 kb
Host smart-05ff258b-97a6-424c-989f-1a06357e8733
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502190794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3502190794
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1713753202
Short name T407
Test name
Test status
Simulation time 10841544733 ps
CPU time 24.48 seconds
Started Jun 29 05:23:14 PM PDT 24
Finished Jun 29 05:23:39 PM PDT 24
Peak memory 212656 kb
Host smart-11897197-4cbb-44de-b342-45e733fe897b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713753202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1713753202
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2451650040
Short name T395
Test name
Test status
Simulation time 13178590941 ps
CPU time 34.72 seconds
Started Jun 29 05:23:16 PM PDT 24
Finished Jun 29 05:23:51 PM PDT 24
Peak memory 218792 kb
Host smart-31d22664-0856-48e5-a361-5ec4b53b717f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451650040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2451650040
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3213722579
Short name T115
Test name
Test status
Simulation time 4415934145 ps
CPU time 181.5 seconds
Started Jun 29 05:23:16 PM PDT 24
Finished Jun 29 05:26:18 PM PDT 24
Peak memory 214296 kb
Host smart-3019d800-ad41-417d-b3a1-cf32fb0f000d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213722579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3213722579
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3501156484
Short name T86
Test name
Test status
Simulation time 14649350709 ps
CPU time 24.75 seconds
Started Jun 29 05:22:53 PM PDT 24
Finished Jun 29 05:23:19 PM PDT 24
Peak memory 211984 kb
Host smart-00443974-8331-4837-b4a7-039810f169b9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501156484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3501156484
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.959628965
Short name T425
Test name
Test status
Simulation time 4226729878 ps
CPU time 31.63 seconds
Started Jun 29 05:22:57 PM PDT 24
Finished Jun 29 05:23:29 PM PDT 24
Peak memory 211880 kb
Host smart-5ac76560-a9e2-4c24-95e5-c226154a925e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959628965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.959628965
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2143692511
Short name T96
Test name
Test status
Simulation time 3237775143 ps
CPU time 25.15 seconds
Started Jun 29 05:22:50 PM PDT 24
Finished Jun 29 05:23:17 PM PDT 24
Peak memory 211660 kb
Host smart-0a678b1d-3b8f-49b3-910a-042f779fadba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143692511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2143692511
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2632876948
Short name T391
Test name
Test status
Simulation time 3613264928 ps
CPU time 29.78 seconds
Started Jun 29 05:22:59 PM PDT 24
Finished Jun 29 05:23:30 PM PDT 24
Peak memory 215192 kb
Host smart-2d412bf9-0255-4930-8653-90dae7fd1248
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632876948 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2632876948
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1530102556
Short name T424
Test name
Test status
Simulation time 345286204 ps
CPU time 8.51 seconds
Started Jun 29 05:22:58 PM PDT 24
Finished Jun 29 05:23:07 PM PDT 24
Peak memory 210712 kb
Host smart-07d9b499-54a3-439f-a619-f89015230ed3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530102556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1530102556
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2361388698
Short name T419
Test name
Test status
Simulation time 1832435012 ps
CPU time 8.48 seconds
Started Jun 29 05:23:01 PM PDT 24
Finished Jun 29 05:23:10 PM PDT 24
Peak memory 210608 kb
Host smart-21093165-a1af-46ac-8bde-d35b925b74eb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361388698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2361388698
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3533989516
Short name T383
Test name
Test status
Simulation time 3869309577 ps
CPU time 31.31 seconds
Started Jun 29 05:22:48 PM PDT 24
Finished Jun 29 05:23:21 PM PDT 24
Peak memory 210684 kb
Host smart-500942e0-62a0-4dad-bdc2-41d97cfc8452
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533989516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3533989516
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3224301947
Short name T84
Test name
Test status
Simulation time 695130300 ps
CPU time 38.28 seconds
Started Jun 29 05:23:00 PM PDT 24
Finished Jun 29 05:23:39 PM PDT 24
Peak memory 213804 kb
Host smart-f0e3773b-1b83-4680-95ff-e6e28a4428c5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224301947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3224301947
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3734809301
Short name T423
Test name
Test status
Simulation time 3549501265 ps
CPU time 24.16 seconds
Started Jun 29 05:23:00 PM PDT 24
Finished Jun 29 05:23:25 PM PDT 24
Peak memory 212672 kb
Host smart-622084a3-40df-43e4-a775-87d7a9991986
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734809301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3734809301
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.983409253
Short name T369
Test name
Test status
Simulation time 3715859142 ps
CPU time 24.76 seconds
Started Jun 29 05:22:48 PM PDT 24
Finished Jun 29 05:23:15 PM PDT 24
Peak memory 218652 kb
Host smart-bf061a2d-2c99-46ed-ba09-4346e92995e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983409253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.983409253
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2287436107
Short name T118
Test name
Test status
Simulation time 3109386353 ps
CPU time 174.04 seconds
Started Jun 29 05:22:50 PM PDT 24
Finished Jun 29 05:25:46 PM PDT 24
Peak memory 215188 kb
Host smart-7fd6bf78-d4e6-4b76-8645-ed369d9c19be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287436107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2287436107
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3245285670
Short name T450
Test name
Test status
Simulation time 12661966712 ps
CPU time 27.21 seconds
Started Jun 29 05:22:58 PM PDT 24
Finished Jun 29 05:23:26 PM PDT 24
Peak memory 211684 kb
Host smart-8df1ea64-2e4f-4880-b66f-aa288799798c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245285670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3245285670
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2170016765
Short name T389
Test name
Test status
Simulation time 2902807512 ps
CPU time 26.38 seconds
Started Jun 29 05:22:53 PM PDT 24
Finished Jun 29 05:23:20 PM PDT 24
Peak memory 210860 kb
Host smart-dca8d40e-7702-4833-b69e-3ece730ee410
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170016765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2170016765
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.762810983
Short name T376
Test name
Test status
Simulation time 14468699744 ps
CPU time 36 seconds
Started Jun 29 05:22:58 PM PDT 24
Finished Jun 29 05:23:35 PM PDT 24
Peak memory 212340 kb
Host smart-b3f7582c-db55-407f-a451-3967c8c42721
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762810983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.762810983
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1228808859
Short name T438
Test name
Test status
Simulation time 59904870992 ps
CPU time 29.36 seconds
Started Jun 29 05:22:53 PM PDT 24
Finished Jun 29 05:23:24 PM PDT 24
Peak memory 215436 kb
Host smart-896cb2a4-e5ee-4ca4-8752-ad19f1a9c643
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228808859 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1228808859
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4270828206
Short name T392
Test name
Test status
Simulation time 3448089210 ps
CPU time 20.11 seconds
Started Jun 29 05:22:57 PM PDT 24
Finished Jun 29 05:23:18 PM PDT 24
Peak memory 212128 kb
Host smart-cfecb009-80b0-4218-8284-460ffbba69bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270828206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.4270828206
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1415428231
Short name T453
Test name
Test status
Simulation time 2061858986 ps
CPU time 8.37 seconds
Started Jun 29 05:23:01 PM PDT 24
Finished Jun 29 05:23:10 PM PDT 24
Peak memory 210644 kb
Host smart-473ed7e1-9951-4083-99b1-089b85a05df4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415428231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1415428231
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2238339177
Short name T396
Test name
Test status
Simulation time 2341248479 ps
CPU time 23.34 seconds
Started Jun 29 05:22:59 PM PDT 24
Finished Jun 29 05:23:24 PM PDT 24
Peak memory 210680 kb
Host smart-56c081de-df46-4cb1-a988-7fa42dc192bb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238339177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2238339177
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1860885001
Short name T88
Test name
Test status
Simulation time 1073351595 ps
CPU time 56.58 seconds
Started Jun 29 05:22:58 PM PDT 24
Finished Jun 29 05:23:55 PM PDT 24
Peak memory 214992 kb
Host smart-4e3534ac-6a70-4da2-9d45-c75311d702a3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860885001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1860885001
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1412432129
Short name T386
Test name
Test status
Simulation time 4106345584 ps
CPU time 34.85 seconds
Started Jun 29 05:22:57 PM PDT 24
Finished Jun 29 05:23:32 PM PDT 24
Peak memory 212308 kb
Host smart-1b93328f-72d1-4a8a-80e6-7c360705c9fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412432129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1412432129
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.43634002
Short name T408
Test name
Test status
Simulation time 3320142661 ps
CPU time 31.31 seconds
Started Jun 29 05:22:58 PM PDT 24
Finished Jun 29 05:23:30 PM PDT 24
Peak memory 217736 kb
Host smart-e88391b3-caae-4826-ab8b-542194126bc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43634002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.43634002
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1756096671
Short name T441
Test name
Test status
Simulation time 1789704794 ps
CPU time 160.82 seconds
Started Jun 29 05:22:53 PM PDT 24
Finished Jun 29 05:25:35 PM PDT 24
Peak memory 214040 kb
Host smart-07ed6e71-e8fa-488c-b4af-1dc4dd64686a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756096671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1756096671
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.730866495
Short name T397
Test name
Test status
Simulation time 7869360272 ps
CPU time 20.09 seconds
Started Jun 29 05:22:57 PM PDT 24
Finished Jun 29 05:23:17 PM PDT 24
Peak memory 210664 kb
Host smart-2e25c7fc-f04b-4c80-be77-10f7982eff29
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730866495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.730866495
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.863616332
Short name T422
Test name
Test status
Simulation time 10473484719 ps
CPU time 24.48 seconds
Started Jun 29 05:23:01 PM PDT 24
Finished Jun 29 05:23:26 PM PDT 24
Peak memory 212160 kb
Host smart-334b2827-6140-4417-b381-321b2953d9ff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863616332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.863616332
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1401617063
Short name T93
Test name
Test status
Simulation time 2298531922 ps
CPU time 26.08 seconds
Started Jun 29 05:22:55 PM PDT 24
Finished Jun 29 05:23:22 PM PDT 24
Peak memory 211492 kb
Host smart-f1e0917e-9b86-44fd-9e56-4725a4546d2c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401617063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1401617063
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.218230560
Short name T459
Test name
Test status
Simulation time 11254939574 ps
CPU time 24.34 seconds
Started Jun 29 05:22:54 PM PDT 24
Finished Jun 29 05:23:19 PM PDT 24
Peak memory 215904 kb
Host smart-60b0474f-9965-4fbb-9fa5-fd1bec423166
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218230560 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.218230560
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1574372392
Short name T381
Test name
Test status
Simulation time 3172438537 ps
CPU time 25.54 seconds
Started Jun 29 05:22:59 PM PDT 24
Finished Jun 29 05:23:26 PM PDT 24
Peak memory 211788 kb
Host smart-8f5af266-bcc2-4c9d-afd3-84ac59aa6b3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574372392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1574372392
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1060201968
Short name T432
Test name
Test status
Simulation time 5044707370 ps
CPU time 34.25 seconds
Started Jun 29 05:23:01 PM PDT 24
Finished Jun 29 05:23:37 PM PDT 24
Peak memory 210712 kb
Host smart-a127c6e0-e8e8-4677-9b64-bab082008f90
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060201968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1060201968
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.547875182
Short name T417
Test name
Test status
Simulation time 2292883464 ps
CPU time 12.43 seconds
Started Jun 29 05:22:58 PM PDT 24
Finished Jun 29 05:23:11 PM PDT 24
Peak memory 210696 kb
Host smart-86aa3267-18a1-4698-b92f-2388d077ad2c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547875182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
547875182
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1948149475
Short name T437
Test name
Test status
Simulation time 13323893531 ps
CPU time 52.66 seconds
Started Jun 29 05:22:59 PM PDT 24
Finished Jun 29 05:23:52 PM PDT 24
Peak memory 214240 kb
Host smart-54ed2823-b32d-4c7f-96a5-ada82425c134
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948149475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1948149475
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2158252330
Short name T399
Test name
Test status
Simulation time 180654717 ps
CPU time 12.6 seconds
Started Jun 29 05:22:59 PM PDT 24
Finished Jun 29 05:23:13 PM PDT 24
Peak memory 212420 kb
Host smart-41fae540-f5a3-4b49-aaca-5eb06249f5fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158252330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2158252330
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.522258057
Short name T398
Test name
Test status
Simulation time 4328889501 ps
CPU time 35.08 seconds
Started Jun 29 05:22:55 PM PDT 24
Finished Jun 29 05:23:31 PM PDT 24
Peak memory 218492 kb
Host smart-e021c9ca-5b76-48b6-a331-2b0f1ca253fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522258057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.522258057
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4035088501
Short name T107
Test name
Test status
Simulation time 747931330 ps
CPU time 160.79 seconds
Started Jun 29 05:22:54 PM PDT 24
Finished Jun 29 05:25:36 PM PDT 24
Peak memory 214184 kb
Host smart-e66d030d-92e9-4003-9a5c-ee5c9d3721d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035088501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.4035088501
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4026968704
Short name T384
Test name
Test status
Simulation time 16003984229 ps
CPU time 33.07 seconds
Started Jun 29 05:22:59 PM PDT 24
Finished Jun 29 05:23:34 PM PDT 24
Peak memory 218236 kb
Host smart-90cf2b24-17e5-4ba2-a421-0fde5e644eb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026968704 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.4026968704
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3616578072
Short name T382
Test name
Test status
Simulation time 3101301116 ps
CPU time 26.11 seconds
Started Jun 29 05:22:59 PM PDT 24
Finished Jun 29 05:23:27 PM PDT 24
Peak memory 211020 kb
Host smart-07f16089-b9d2-48dc-8a0b-e9c2c75a6a94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616578072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3616578072
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2337026567
Short name T449
Test name
Test status
Simulation time 4065088550 ps
CPU time 84.4 seconds
Started Jun 29 05:22:55 PM PDT 24
Finished Jun 29 05:24:20 PM PDT 24
Peak memory 215288 kb
Host smart-2e536ec5-10e1-4eb3-aa0f-b9d70b7632bf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337026567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2337026567
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3278665211
Short name T76
Test name
Test status
Simulation time 1915774270 ps
CPU time 12.13 seconds
Started Jun 29 05:22:54 PM PDT 24
Finished Jun 29 05:23:08 PM PDT 24
Peak memory 212568 kb
Host smart-9350644d-08b2-4aa8-8dd3-305a0571c422
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278665211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3278665211
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2576318703
Short name T387
Test name
Test status
Simulation time 4331875654 ps
CPU time 38.5 seconds
Started Jun 29 05:23:03 PM PDT 24
Finished Jun 29 05:23:42 PM PDT 24
Peak memory 217884 kb
Host smart-85f763a7-d099-4558-ac35-971cf04ed83b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576318703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2576318703
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.744485126
Short name T385
Test name
Test status
Simulation time 4309443675 ps
CPU time 104.8 seconds
Started Jun 29 05:23:00 PM PDT 24
Finished Jun 29 05:24:46 PM PDT 24
Peak memory 213988 kb
Host smart-96008d17-7d95-4be9-8d87-7408cac452ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744485126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.744485126
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.718285606
Short name T454
Test name
Test status
Simulation time 24052865461 ps
CPU time 31.72 seconds
Started Jun 29 05:22:56 PM PDT 24
Finished Jun 29 05:23:29 PM PDT 24
Peak memory 215156 kb
Host smart-3094f1e0-a1b2-44c6-9bf2-2f908e11010a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718285606 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.718285606
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2645128212
Short name T434
Test name
Test status
Simulation time 412137773 ps
CPU time 11.35 seconds
Started Jun 29 05:22:59 PM PDT 24
Finished Jun 29 05:23:12 PM PDT 24
Peak memory 210776 kb
Host smart-b6f5c72c-f3ee-4377-8f82-9b2aa2e81c04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645128212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2645128212
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.250127015
Short name T404
Test name
Test status
Simulation time 25508831244 ps
CPU time 180.59 seconds
Started Jun 29 05:23:01 PM PDT 24
Finished Jun 29 05:26:03 PM PDT 24
Peak memory 215064 kb
Host smart-c67eba2a-b24d-4e03-b9da-9a8499dfa644
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250127015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.250127015
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1468838932
Short name T101
Test name
Test status
Simulation time 3994516972 ps
CPU time 30.34 seconds
Started Jun 29 05:22:53 PM PDT 24
Finished Jun 29 05:23:24 PM PDT 24
Peak memory 212148 kb
Host smart-42392a79-99ae-4f15-9ca1-0918b58abbde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468838932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1468838932
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1980148697
Short name T451
Test name
Test status
Simulation time 7346265654 ps
CPU time 33.44 seconds
Started Jun 29 05:22:59 PM PDT 24
Finished Jun 29 05:23:33 PM PDT 24
Peak memory 219072 kb
Host smart-d59219bc-8839-4be5-92e6-a2b8d3e104ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980148697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1980148697
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.102150476
Short name T431
Test name
Test status
Simulation time 3054854661 ps
CPU time 100.64 seconds
Started Jun 29 05:22:59 PM PDT 24
Finished Jun 29 05:24:40 PM PDT 24
Peak memory 213848 kb
Host smart-eb648d13-0b37-464c-8c77-04d1d737abe5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102150476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.102150476
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2091636555
Short name T401
Test name
Test status
Simulation time 10237606130 ps
CPU time 15.29 seconds
Started Jun 29 05:23:00 PM PDT 24
Finished Jun 29 05:23:16 PM PDT 24
Peak memory 216652 kb
Host smart-28905bfb-b9c6-4783-a7ef-a2dc1e2cb0d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091636555 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2091636555
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3636814938
Short name T447
Test name
Test status
Simulation time 1852530433 ps
CPU time 18.6 seconds
Started Jun 29 05:22:54 PM PDT 24
Finished Jun 29 05:23:13 PM PDT 24
Peak memory 211492 kb
Host smart-b865f620-9e01-497f-a451-d6877d8d0ed9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636814938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3636814938
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3508491496
Short name T92
Test name
Test status
Simulation time 15440188699 ps
CPU time 153.32 seconds
Started Jun 29 05:22:56 PM PDT 24
Finished Jun 29 05:25:29 PM PDT 24
Peak memory 214104 kb
Host smart-b6e29591-426a-4765-a702-e641026c9668
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508491496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3508491496
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1465635303
Short name T406
Test name
Test status
Simulation time 3645306155 ps
CPU time 29.01 seconds
Started Jun 29 05:23:00 PM PDT 24
Finished Jun 29 05:23:30 PM PDT 24
Peak memory 211680 kb
Host smart-8e999bc3-482f-4481-80d3-aeef296fa1f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465635303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1465635303
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2439165208
Short name T372
Test name
Test status
Simulation time 167563548 ps
CPU time 12.99 seconds
Started Jun 29 05:22:54 PM PDT 24
Finished Jun 29 05:23:08 PM PDT 24
Peak memory 219012 kb
Host smart-7a3250b0-7544-462d-8bd6-6c900de28a85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439165208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2439165208
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3674655270
Short name T117
Test name
Test status
Simulation time 5736643116 ps
CPU time 157.26 seconds
Started Jun 29 05:22:57 PM PDT 24
Finished Jun 29 05:25:35 PM PDT 24
Peak memory 214352 kb
Host smart-b8b096db-372e-465c-be88-a5a3085aeed9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674655270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3674655270
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4057812390
Short name T364
Test name
Test status
Simulation time 13027804034 ps
CPU time 18.99 seconds
Started Jun 29 05:22:53 PM PDT 24
Finished Jun 29 05:23:13 PM PDT 24
Peak memory 216884 kb
Host smart-6bc0c4cb-ab77-48fa-a370-f2a62cb28fb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057812390 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.4057812390
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3037305449
Short name T456
Test name
Test status
Simulation time 633725842 ps
CPU time 10.47 seconds
Started Jun 29 05:22:54 PM PDT 24
Finished Jun 29 05:23:05 PM PDT 24
Peak memory 210672 kb
Host smart-41633aee-d370-4ade-985c-e9a991b910b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037305449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3037305449
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2344602460
Short name T439
Test name
Test status
Simulation time 32078552390 ps
CPU time 119.74 seconds
Started Jun 29 05:22:57 PM PDT 24
Finished Jun 29 05:24:58 PM PDT 24
Peak memory 213940 kb
Host smart-bde4c443-5a1c-415b-afa0-4f966357b1f9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344602460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2344602460
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2816877672
Short name T436
Test name
Test status
Simulation time 1829989059 ps
CPU time 8.54 seconds
Started Jun 29 05:22:53 PM PDT 24
Finished Jun 29 05:23:03 PM PDT 24
Peak memory 211396 kb
Host smart-a85da17c-53a6-4dab-b4d3-53f0f6a9d1aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816877672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2816877672
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.92898961
Short name T413
Test name
Test status
Simulation time 174661320 ps
CPU time 12.88 seconds
Started Jun 29 05:22:58 PM PDT 24
Finished Jun 29 05:23:12 PM PDT 24
Peak memory 217200 kb
Host smart-d2d7a0fe-9652-4ba6-babc-b8a237192c59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92898961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.92898961
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4066793151
Short name T110
Test name
Test status
Simulation time 3647211166 ps
CPU time 102.34 seconds
Started Jun 29 05:23:01 PM PDT 24
Finished Jun 29 05:24:44 PM PDT 24
Peak memory 219068 kb
Host smart-5d3c1ee2-d904-4bf3-8e8b-80c474dd1fc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066793151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.4066793151
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1335585289
Short name T445
Test name
Test status
Simulation time 4321520258 ps
CPU time 15.91 seconds
Started Jun 29 05:23:01 PM PDT 24
Finished Jun 29 05:23:18 PM PDT 24
Peak memory 217076 kb
Host smart-a985f085-df85-4cb0-94de-2541d614bf03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335585289 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1335585289
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1632156008
Short name T403
Test name
Test status
Simulation time 3419548272 ps
CPU time 21.52 seconds
Started Jun 29 05:23:00 PM PDT 24
Finished Jun 29 05:23:23 PM PDT 24
Peak memory 211928 kb
Host smart-2e29a348-68c1-4883-a621-73bc6bd8d340
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632156008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1632156008
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2116687339
Short name T458
Test name
Test status
Simulation time 21881246921 ps
CPU time 173.05 seconds
Started Jun 29 05:22:54 PM PDT 24
Finished Jun 29 05:25:48 PM PDT 24
Peak memory 215364 kb
Host smart-611787ee-d84c-4ba5-bbbb-cee383253018
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116687339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2116687339
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3585432087
Short name T63
Test name
Test status
Simulation time 11958337836 ps
CPU time 29.95 seconds
Started Jun 29 05:22:58 PM PDT 24
Finished Jun 29 05:23:28 PM PDT 24
Peak memory 212732 kb
Host smart-94e4a13e-1e29-4078-bb39-3935d9701e45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585432087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3585432087
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.329205517
Short name T370
Test name
Test status
Simulation time 167591300 ps
CPU time 12.98 seconds
Started Jun 29 05:22:57 PM PDT 24
Finished Jun 29 05:23:10 PM PDT 24
Peak memory 217364 kb
Host smart-329f6365-7721-41d0-91aa-cfb9f5595c0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329205517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.329205517
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.100535571
Short name T113
Test name
Test status
Simulation time 1626530915 ps
CPU time 157.64 seconds
Started Jun 29 05:22:53 PM PDT 24
Finished Jun 29 05:25:32 PM PDT 24
Peak memory 213924 kb
Host smart-d9ec473a-f13c-4866-af66-0b83e22cf27b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100535571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.100535571
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.42207671
Short name T151
Test name
Test status
Simulation time 20502842122 ps
CPU time 31.05 seconds
Started Jun 29 04:34:00 PM PDT 24
Finished Jun 29 04:34:32 PM PDT 24
Peak memory 217476 kb
Host smart-175d20b0-f966-4fbc-ba47-a04a9cf567fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42207671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.42207671
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.614783016
Short name T159
Test name
Test status
Simulation time 291082608756 ps
CPU time 715.06 seconds
Started Jun 29 04:34:06 PM PDT 24
Finished Jun 29 04:46:01 PM PDT 24
Peak memory 235444 kb
Host smart-5a99dba4-0faa-4196-8ef3-5e166fa01b10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614783016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.614783016
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.396822605
Short name T143
Test name
Test status
Simulation time 15806018069 ps
CPU time 44.05 seconds
Started Jun 29 04:34:01 PM PDT 24
Finished Jun 29 04:34:45 PM PDT 24
Peak memory 219204 kb
Host smart-63c94de5-d50a-4496-93f9-50d43f5c9c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396822605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.396822605
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.751641356
Short name T6
Test name
Test status
Simulation time 28633177326 ps
CPU time 25.13 seconds
Started Jun 29 04:34:00 PM PDT 24
Finished Jun 29 04:34:26 PM PDT 24
Peak memory 219236 kb
Host smart-995da2bf-2aa5-4a4d-aff4-86b91e3ebe1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=751641356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.751641356
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.4059951167
Short name T28
Test name
Test status
Simulation time 1216959180 ps
CPU time 114.31 seconds
Started Jun 29 04:34:01 PM PDT 24
Finished Jun 29 04:35:55 PM PDT 24
Peak memory 236060 kb
Host smart-0e2028f9-af25-474b-bf69-d49e6b72dde6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059951167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.4059951167
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.535083287
Short name T154
Test name
Test status
Simulation time 1484546472 ps
CPU time 30.05 seconds
Started Jun 29 04:33:57 PM PDT 24
Finished Jun 29 04:34:27 PM PDT 24
Peak memory 216200 kb
Host smart-3b300fd2-0ab7-456f-85c1-935787707e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535083287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.535083287
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3753198539
Short name T250
Test name
Test status
Simulation time 33408790886 ps
CPU time 94.75 seconds
Started Jun 29 04:33:55 PM PDT 24
Finished Jun 29 04:35:30 PM PDT 24
Peak memory 219248 kb
Host smart-ef476083-fcd2-4ed9-8b9f-64151ea67067
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753198539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3753198539
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.778839364
Short name T279
Test name
Test status
Simulation time 10258875850 ps
CPU time 34.46 seconds
Started Jun 29 04:34:09 PM PDT 24
Finished Jun 29 04:34:44 PM PDT 24
Peak memory 217336 kb
Host smart-e8cc6ae9-eee6-4b52-8497-8ac3f6275351
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778839364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.778839364
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2297812109
Short name T333
Test name
Test status
Simulation time 226454837661 ps
CPU time 505.79 seconds
Started Jun 29 04:34:03 PM PDT 24
Finished Jun 29 04:42:29 PM PDT 24
Peak memory 216768 kb
Host smart-d7c8e417-a8cc-42f8-841c-78a7c452973a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297812109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2297812109
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.4181912521
Short name T195
Test name
Test status
Simulation time 30145829907 ps
CPU time 65.98 seconds
Started Jun 29 04:34:06 PM PDT 24
Finished Jun 29 04:35:12 PM PDT 24
Peak memory 219252 kb
Host smart-bc74fe7a-7aa2-44a4-9d90-6665afcea936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181912521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.4181912521
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3205082338
Short name T120
Test name
Test status
Simulation time 186457887 ps
CPU time 11.31 seconds
Started Jun 29 04:33:59 PM PDT 24
Finished Jun 29 04:34:10 PM PDT 24
Peak memory 219204 kb
Host smart-c421d800-f109-48ba-bf90-af0b4cb57146
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3205082338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3205082338
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3260391893
Short name T24
Test name
Test status
Simulation time 12266517918 ps
CPU time 243.6 seconds
Started Jun 29 04:34:01 PM PDT 24
Finished Jun 29 04:38:05 PM PDT 24
Peak memory 238304 kb
Host smart-ad1f3fae-785f-4847-94cc-cbd29ddaee30
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260391893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3260391893
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2621193101
Short name T186
Test name
Test status
Simulation time 28312060927 ps
CPU time 52.72 seconds
Started Jun 29 04:33:57 PM PDT 24
Finished Jun 29 04:34:50 PM PDT 24
Peak memory 216984 kb
Host smart-64776db4-7bb0-4c62-a81c-c4d604169c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621193101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2621193101
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1011065555
Short name T142
Test name
Test status
Simulation time 746101103 ps
CPU time 13.95 seconds
Started Jun 29 04:34:08 PM PDT 24
Finished Jun 29 04:34:22 PM PDT 24
Peak memory 218500 kb
Host smart-59f74a07-6b15-456f-97d0-73415a429919
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011065555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1011065555
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3065177061
Short name T35
Test name
Test status
Simulation time 184109245838 ps
CPU time 864.7 seconds
Started Jun 29 04:34:24 PM PDT 24
Finished Jun 29 04:48:49 PM PDT 24
Peak memory 233880 kb
Host smart-8f4de4f1-8450-440f-9299-632b090605c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065177061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3065177061
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.324976994
Short name T170
Test name
Test status
Simulation time 4277281015 ps
CPU time 49.6 seconds
Started Jun 29 04:34:16 PM PDT 24
Finished Jun 29 04:35:06 PM PDT 24
Peak memory 216304 kb
Host smart-f899e474-442a-4254-93f3-d9ad61f60204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324976994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.324976994
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1717809708
Short name T349
Test name
Test status
Simulation time 100202881471 ps
CPU time 208.16 seconds
Started Jun 29 04:34:14 PM PDT 24
Finished Jun 29 04:37:42 PM PDT 24
Peak memory 220364 kb
Host smart-e1744c91-e81f-4e52-9eda-d2f8fd64cc7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717809708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1717809708
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3283377951
Short name T300
Test name
Test status
Simulation time 15745484504 ps
CPU time 28.96 seconds
Started Jun 29 04:34:24 PM PDT 24
Finished Jun 29 04:34:53 PM PDT 24
Peak memory 213192 kb
Host smart-2ece8a07-1c54-41e3-98a1-fd71bd71aab5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283377951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3283377951
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2746168939
Short name T237
Test name
Test status
Simulation time 140107447811 ps
CPU time 457.02 seconds
Started Jun 29 04:34:23 PM PDT 24
Finished Jun 29 04:42:01 PM PDT 24
Peak memory 235176 kb
Host smart-ac422a15-b51b-480b-bbc3-0d4b96e236a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746168939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2746168939
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1090374274
Short name T187
Test name
Test status
Simulation time 6419329883 ps
CPU time 37.73 seconds
Started Jun 29 04:34:21 PM PDT 24
Finished Jun 29 04:34:59 PM PDT 24
Peak memory 219264 kb
Host smart-a7425efc-13fc-4558-a658-a20f0cf0c776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090374274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1090374274
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.79736473
Short name T280
Test name
Test status
Simulation time 10736446415 ps
CPU time 23.72 seconds
Started Jun 29 04:34:25 PM PDT 24
Finished Jun 29 04:34:49 PM PDT 24
Peak memory 219232 kb
Host smart-41b5254f-188a-424c-8fc2-19e68218cdcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=79736473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.79736473
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.1238094325
Short name T211
Test name
Test status
Simulation time 1296699583 ps
CPU time 20.19 seconds
Started Jun 29 04:35:00 PM PDT 24
Finished Jun 29 04:35:20 PM PDT 24
Peak memory 216080 kb
Host smart-6d4c792e-4275-449e-bae8-0820d13b544d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238094325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1238094325
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1116623258
Short name T192
Test name
Test status
Simulation time 8162666692 ps
CPU time 79.28 seconds
Started Jun 29 04:34:25 PM PDT 24
Finished Jun 29 04:35:44 PM PDT 24
Peak memory 221464 kb
Host smart-09c81dea-ae53-4bfb-8e89-18722098f427
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116623258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1116623258
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3962408452
Short name T185
Test name
Test status
Simulation time 13492347184 ps
CPU time 29.32 seconds
Started Jun 29 04:34:28 PM PDT 24
Finished Jun 29 04:34:58 PM PDT 24
Peak memory 217348 kb
Host smart-072ad1eb-2ff7-464e-8969-1dc70216306f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962408452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3962408452
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2985500936
Short name T236
Test name
Test status
Simulation time 260048354648 ps
CPU time 474.46 seconds
Started Jun 29 04:34:23 PM PDT 24
Finished Jun 29 04:42:18 PM PDT 24
Peak memory 233556 kb
Host smart-01fd7aa5-a873-4a3c-91b3-c5168d0d2f04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985500936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2985500936
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3229770254
Short name T253
Test name
Test status
Simulation time 3760021243 ps
CPU time 43.52 seconds
Started Jun 29 04:34:18 PM PDT 24
Finished Jun 29 04:35:01 PM PDT 24
Peak memory 219236 kb
Host smart-484796cc-ce5e-4daf-87d6-0f0bcd22d4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229770254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3229770254
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1147987470
Short name T306
Test name
Test status
Simulation time 185733135 ps
CPU time 10.44 seconds
Started Jun 29 04:34:27 PM PDT 24
Finished Jun 29 04:34:38 PM PDT 24
Peak memory 219180 kb
Host smart-4f63113f-db39-4bc3-8b51-e6cab446f1c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1147987470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1147987470
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3595806370
Short name T55
Test name
Test status
Simulation time 2294353591 ps
CPU time 20.47 seconds
Started Jun 29 04:34:27 PM PDT 24
Finished Jun 29 04:34:48 PM PDT 24
Peak memory 215396 kb
Host smart-16bd0a1c-d66f-4eb9-a5ab-50c1236992bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595806370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3595806370
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.510289288
Short name T162
Test name
Test status
Simulation time 65783971246 ps
CPU time 94.95 seconds
Started Jun 29 04:34:30 PM PDT 24
Finished Jun 29 04:36:05 PM PDT 24
Peak memory 219284 kb
Host smart-43dc3ca8-f51d-427f-8a4a-5eeb7937bb56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510289288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.510289288
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.889311042
Short name T48
Test name
Test status
Simulation time 44863840852 ps
CPU time 8978.92 seconds
Started Jun 29 04:34:27 PM PDT 24
Finished Jun 29 07:04:08 PM PDT 24
Peak memory 230972 kb
Host smart-2e658bba-cc57-4710-8811-f6ada1531375
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889311042 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.889311042
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3850921903
Short name T31
Test name
Test status
Simulation time 3049852941 ps
CPU time 13.58 seconds
Started Jun 29 04:34:28 PM PDT 24
Finished Jun 29 04:34:42 PM PDT 24
Peak memory 217072 kb
Host smart-7f9ae930-3ce0-483c-b272-d11a2b5e399a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850921903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3850921903
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3737623500
Short name T292
Test name
Test status
Simulation time 5088883469 ps
CPU time 130.78 seconds
Started Jun 29 04:34:29 PM PDT 24
Finished Jun 29 04:36:40 PM PDT 24
Peak memory 233636 kb
Host smart-fdfa77d1-b166-4d09-88eb-5bdd201c8ca4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737623500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3737623500
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2968329049
Short name T309
Test name
Test status
Simulation time 16997804566 ps
CPU time 44.83 seconds
Started Jun 29 04:34:26 PM PDT 24
Finished Jun 29 04:35:12 PM PDT 24
Peak memory 219264 kb
Host smart-be6be0bd-c927-485f-8e0a-19acf80ee6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968329049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2968329049
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2569170491
Short name T204
Test name
Test status
Simulation time 643549647 ps
CPU time 14.51 seconds
Started Jun 29 04:34:31 PM PDT 24
Finished Jun 29 04:34:46 PM PDT 24
Peak memory 219180 kb
Host smart-fda69b0f-eaf3-4bd5-98c2-5d961dbeed92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2569170491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2569170491
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1598594128
Short name T283
Test name
Test status
Simulation time 64006486616 ps
CPU time 63.62 seconds
Started Jun 29 04:34:34 PM PDT 24
Finished Jun 29 04:35:38 PM PDT 24
Peak memory 215460 kb
Host smart-f0c2c02f-81ce-4ecb-b1bf-cc300ce317ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598594128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1598594128
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3397843590
Short name T189
Test name
Test status
Simulation time 4882162808 ps
CPU time 16.41 seconds
Started Jun 29 04:34:26 PM PDT 24
Finished Jun 29 04:34:43 PM PDT 24
Peak memory 217596 kb
Host smart-e384ea9e-9cef-4d5e-ac80-0925c67e9f1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397843590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3397843590
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1327474447
Short name T166
Test name
Test status
Simulation time 32679612803 ps
CPU time 488.72 seconds
Started Jun 29 04:34:27 PM PDT 24
Finished Jun 29 04:42:36 PM PDT 24
Peak memory 239036 kb
Host smart-b388726a-4fe5-4812-958e-be61e574bf3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327474447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1327474447
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1149446797
Short name T269
Test name
Test status
Simulation time 2510766192 ps
CPU time 24.77 seconds
Started Jun 29 04:34:31 PM PDT 24
Finished Jun 29 04:34:56 PM PDT 24
Peak memory 219268 kb
Host smart-55215a18-01d4-45e0-802c-776fa3bdf770
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1149446797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1149446797
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3428708371
Short name T344
Test name
Test status
Simulation time 42460490793 ps
CPU time 73.22 seconds
Started Jun 29 04:34:26 PM PDT 24
Finished Jun 29 04:35:40 PM PDT 24
Peak memory 217376 kb
Host smart-0e074ada-9232-42bf-9d8b-14c9ca38a0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428708371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3428708371
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3642408882
Short name T232
Test name
Test status
Simulation time 3910550589 ps
CPU time 59.17 seconds
Started Jun 29 04:34:27 PM PDT 24
Finished Jun 29 04:35:27 PM PDT 24
Peak memory 219236 kb
Host smart-f8305abd-b2c4-4085-afe5-80d67434db44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642408882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3642408882
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.900385046
Short name T193
Test name
Test status
Simulation time 61187089479 ps
CPU time 32.4 seconds
Started Jun 29 04:34:27 PM PDT 24
Finished Jun 29 04:35:00 PM PDT 24
Peak memory 217460 kb
Host smart-35d36901-7396-4542-a8f6-02453f5ecb9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900385046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.900385046
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1757490025
Short name T137
Test name
Test status
Simulation time 5471098442 ps
CPU time 36.78 seconds
Started Jun 29 04:34:29 PM PDT 24
Finished Jun 29 04:35:06 PM PDT 24
Peak memory 219264 kb
Host smart-5cf11a49-08bf-447c-9d6a-f2a7a62ff92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757490025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1757490025
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.149818930
Short name T260
Test name
Test status
Simulation time 440221288 ps
CPU time 13.61 seconds
Started Jun 29 04:34:29 PM PDT 24
Finished Jun 29 04:34:43 PM PDT 24
Peak memory 218480 kb
Host smart-9b57a517-f9f9-4345-9bd6-aa4aa971f6fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=149818930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.149818930
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1961597823
Short name T360
Test name
Test status
Simulation time 367151781 ps
CPU time 20.64 seconds
Started Jun 29 04:34:28 PM PDT 24
Finished Jun 29 04:34:49 PM PDT 24
Peak memory 216216 kb
Host smart-6926b0de-6a4f-4c99-8fdb-ff64bd445b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961597823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1961597823
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2990571737
Short name T284
Test name
Test status
Simulation time 8495223000 ps
CPU time 79.94 seconds
Started Jun 29 04:34:28 PM PDT 24
Finished Jun 29 04:35:48 PM PDT 24
Peak memory 219332 kb
Host smart-9d9b8044-5e60-4d65-aa69-bce0f7557633
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990571737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2990571737
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1420182261
Short name T244
Test name
Test status
Simulation time 26291635123 ps
CPU time 31.06 seconds
Started Jun 29 04:34:32 PM PDT 24
Finished Jun 29 04:35:03 PM PDT 24
Peak memory 217348 kb
Host smart-3d353213-61df-425c-ad0f-725bcde0b8dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420182261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1420182261
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2840887842
Short name T321
Test name
Test status
Simulation time 4064062773 ps
CPU time 251.59 seconds
Started Jun 29 04:34:27 PM PDT 24
Finished Jun 29 04:38:39 PM PDT 24
Peak memory 237320 kb
Host smart-69972bd1-06d4-4375-a64e-1107209ba5dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840887842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2840887842
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3677216539
Short name T139
Test name
Test status
Simulation time 7068687430 ps
CPU time 43.02 seconds
Started Jun 29 04:34:30 PM PDT 24
Finished Jun 29 04:35:14 PM PDT 24
Peak memory 219256 kb
Host smart-fec04997-b682-48ae-8d27-fb6f4e453881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677216539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3677216539
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2009651004
Short name T353
Test name
Test status
Simulation time 176896186 ps
CPU time 10.17 seconds
Started Jun 29 04:34:34 PM PDT 24
Finished Jun 29 04:34:44 PM PDT 24
Peak memory 219120 kb
Host smart-c4a7d736-32d8-47bf-bc07-5fada67b7504
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2009651004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2009651004
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.4045974576
Short name T13
Test name
Test status
Simulation time 14764030467 ps
CPU time 63.82 seconds
Started Jun 29 04:34:29 PM PDT 24
Finished Jun 29 04:35:33 PM PDT 24
Peak memory 217020 kb
Host smart-6a8b23e0-e96f-4f91-ad33-1f6b52671051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045974576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.4045974576
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2205467527
Short name T141
Test name
Test status
Simulation time 3638298813 ps
CPU time 45.41 seconds
Started Jun 29 04:34:30 PM PDT 24
Finished Jun 29 04:35:16 PM PDT 24
Peak memory 219112 kb
Host smart-9bb53461-6abe-4b71-9070-285e844e46a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205467527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2205467527
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3362708090
Short name T65
Test name
Test status
Simulation time 10380232711 ps
CPU time 24.95 seconds
Started Jun 29 04:34:29 PM PDT 24
Finished Jun 29 04:34:54 PM PDT 24
Peak memory 217460 kb
Host smart-477ff55d-87ec-477f-b7fb-72127057f0c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362708090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3362708090
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.48530447
Short name T34
Test name
Test status
Simulation time 7350333446 ps
CPU time 248.59 seconds
Started Jun 29 04:34:35 PM PDT 24
Finished Jun 29 04:38:44 PM PDT 24
Peak memory 237096 kb
Host smart-44f36ed7-c0f7-4d1a-aafa-cc5e96030b82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48530447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_co
rrupt_sig_fatal_chk.48530447
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.329878048
Short name T350
Test name
Test status
Simulation time 21099604633 ps
CPU time 54.53 seconds
Started Jun 29 04:34:26 PM PDT 24
Finished Jun 29 04:35:21 PM PDT 24
Peak memory 218848 kb
Host smart-0cbe8e47-754e-4507-913b-206b09e6cf96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329878048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.329878048
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1570331082
Short name T196
Test name
Test status
Simulation time 681818381 ps
CPU time 10.63 seconds
Started Jun 29 04:34:32 PM PDT 24
Finished Jun 29 04:34:43 PM PDT 24
Peak memory 219180 kb
Host smart-e8631ea6-e5bd-433e-9368-18dc8da04359
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1570331082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1570331082
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.624241396
Short name T293
Test name
Test status
Simulation time 4347637073 ps
CPU time 45.32 seconds
Started Jun 29 04:34:26 PM PDT 24
Finished Jun 29 04:35:11 PM PDT 24
Peak memory 216160 kb
Host smart-60627b58-0860-4608-b332-bc37b89cda3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624241396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.624241396
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.677397771
Short name T212
Test name
Test status
Simulation time 7334429594 ps
CPU time 66.54 seconds
Started Jun 29 04:34:29 PM PDT 24
Finished Jun 29 04:35:36 PM PDT 24
Peak memory 218292 kb
Host smart-486cb973-5378-4208-a2b8-ed4a5ba94122
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677397771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.677397771
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3682540075
Short name T56
Test name
Test status
Simulation time 5247987609 ps
CPU time 16.35 seconds
Started Jun 29 04:34:30 PM PDT 24
Finished Jun 29 04:34:47 PM PDT 24
Peak memory 217308 kb
Host smart-a201713e-b62c-423d-89e7-e899654d9d32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682540075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3682540075
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2446745838
Short name T216
Test name
Test status
Simulation time 26738113989 ps
CPU time 404.84 seconds
Started Jun 29 04:34:35 PM PDT 24
Finished Jun 29 04:41:20 PM PDT 24
Peak memory 239848 kb
Host smart-13fdebe6-4427-4be6-a0ac-289969ba3413
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446745838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2446745838
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1735433723
Short name T155
Test name
Test status
Simulation time 5283661708 ps
CPU time 40.31 seconds
Started Jun 29 04:34:29 PM PDT 24
Finished Jun 29 04:35:10 PM PDT 24
Peak memory 219152 kb
Host smart-371b955c-f481-4cc3-a3df-a265b8f8a44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735433723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1735433723
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3855889760
Short name T311
Test name
Test status
Simulation time 3831270929 ps
CPU time 31.41 seconds
Started Jun 29 04:34:35 PM PDT 24
Finished Jun 29 04:35:07 PM PDT 24
Peak memory 211260 kb
Host smart-a58af609-ae03-4e3b-969e-2d5c586bbe9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3855889760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3855889760
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.3330189621
Short name T339
Test name
Test status
Simulation time 5305653285 ps
CPU time 66.5 seconds
Started Jun 29 04:34:31 PM PDT 24
Finished Jun 29 04:35:38 PM PDT 24
Peak memory 217368 kb
Host smart-c24cfe54-8c25-455b-ada1-f65f34d74610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330189621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.3330189621
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.88084762
Short name T287
Test name
Test status
Simulation time 23305985014 ps
CPU time 125.73 seconds
Started Jun 29 04:34:30 PM PDT 24
Finished Jun 29 04:36:36 PM PDT 24
Peak memory 227464 kb
Host smart-0c6d669d-493d-47a0-931b-2d18199d9735
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88084762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 18.rom_ctrl_stress_all.88084762
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1460397696
Short name T235
Test name
Test status
Simulation time 4371773292 ps
CPU time 32.24 seconds
Started Jun 29 04:34:33 PM PDT 24
Finished Jun 29 04:35:06 PM PDT 24
Peak memory 217336 kb
Host smart-16712d34-9721-4265-857c-c25f6fd59e84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460397696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1460397696
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.377554481
Short name T33
Test name
Test status
Simulation time 85502350465 ps
CPU time 497.24 seconds
Started Jun 29 04:34:35 PM PDT 24
Finished Jun 29 04:42:52 PM PDT 24
Peak memory 239372 kb
Host smart-f3745ec8-4875-4823-8c0d-e91432c383b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377554481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.377554481
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3504959594
Short name T173
Test name
Test status
Simulation time 8684479819 ps
CPU time 43.29 seconds
Started Jun 29 04:34:37 PM PDT 24
Finished Jun 29 04:35:20 PM PDT 24
Peak memory 219260 kb
Host smart-a162d385-7967-443f-9cdf-5515fd6e0935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504959594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3504959594
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3759124724
Short name T354
Test name
Test status
Simulation time 2155643341 ps
CPU time 10.44 seconds
Started Jun 29 04:34:40 PM PDT 24
Finished Jun 29 04:34:51 PM PDT 24
Peak memory 219240 kb
Host smart-26a84c50-5150-4337-b033-a69aca574720
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3759124724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3759124724
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.4151111711
Short name T209
Test name
Test status
Simulation time 3896410041 ps
CPU time 52.2 seconds
Started Jun 29 04:34:25 PM PDT 24
Finished Jun 29 04:35:17 PM PDT 24
Peak memory 227500 kb
Host smart-f77e758b-30ef-4071-a38d-c7985f6d54ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151111711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.4151111711
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.2002683552
Short name T47
Test name
Test status
Simulation time 211086059790 ps
CPU time 2010.2 seconds
Started Jun 29 04:34:40 PM PDT 24
Finished Jun 29 05:08:11 PM PDT 24
Peak memory 244936 kb
Host smart-6595e5cc-b829-439f-a046-0bc4b6735d95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002683552 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.2002683552
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3608881632
Short name T257
Test name
Test status
Simulation time 2413670854 ps
CPU time 15.74 seconds
Started Jun 29 04:34:08 PM PDT 24
Finished Jun 29 04:34:24 PM PDT 24
Peak memory 217140 kb
Host smart-9a4e07a5-00f1-45b6-84df-9ea91416d06e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608881632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3608881632
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3661128219
Short name T290
Test name
Test status
Simulation time 87134706621 ps
CPU time 395.54 seconds
Started Jun 29 04:33:56 PM PDT 24
Finished Jun 29 04:40:32 PM PDT 24
Peak memory 234720 kb
Host smart-6ee17068-bbf5-4173-8bdd-df031457fcbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661128219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3661128219
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2216203123
Short name T227
Test name
Test status
Simulation time 688592065 ps
CPU time 18.82 seconds
Started Jun 29 04:34:00 PM PDT 24
Finished Jun 29 04:34:19 PM PDT 24
Peak memory 219168 kb
Host smart-3a170583-081c-4b86-9602-939bf6ccc2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216203123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2216203123
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.4263171722
Short name T122
Test name
Test status
Simulation time 784641989 ps
CPU time 15.4 seconds
Started Jun 29 04:33:54 PM PDT 24
Finished Jun 29 04:34:10 PM PDT 24
Peak memory 219184 kb
Host smart-7f1eca81-2a40-444f-99bd-12f87e2492d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4263171722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.4263171722
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2389316293
Short name T25
Test name
Test status
Simulation time 5850421825 ps
CPU time 235.83 seconds
Started Jun 29 04:33:56 PM PDT 24
Finished Jun 29 04:37:52 PM PDT 24
Peak memory 235268 kb
Host smart-68fb10c3-5a93-4293-8288-553e9c130f55
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389316293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2389316293
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.237354731
Short name T334
Test name
Test status
Simulation time 6523013582 ps
CPU time 56.8 seconds
Started Jun 29 04:34:00 PM PDT 24
Finished Jun 29 04:34:57 PM PDT 24
Peak memory 218128 kb
Host smart-a9c36274-0ba7-46da-86a6-b7e3e3e5027b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237354731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.237354731
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1422548525
Short name T261
Test name
Test status
Simulation time 24116305684 ps
CPU time 35.31 seconds
Started Jun 29 04:34:00 PM PDT 24
Finished Jun 29 04:34:36 PM PDT 24
Peak memory 214660 kb
Host smart-5ec1ae0d-1bc3-484a-b609-8a6c6b2bb85e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422548525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1422548525
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1484393845
Short name T177
Test name
Test status
Simulation time 1969736412 ps
CPU time 19.66 seconds
Started Jun 29 04:34:34 PM PDT 24
Finished Jun 29 04:34:54 PM PDT 24
Peak memory 216476 kb
Host smart-c215eb94-0ac6-440c-8f9d-64716fa9efcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484393845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1484393845
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.808951865
Short name T285
Test name
Test status
Simulation time 89846977411 ps
CPU time 226.47 seconds
Started Jun 29 04:34:38 PM PDT 24
Finished Jun 29 04:38:25 PM PDT 24
Peak memory 236988 kb
Host smart-a8d17813-0a48-456c-87cd-39c231bb1e58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808951865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.808951865
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3935749238
Short name T221
Test name
Test status
Simulation time 7011337416 ps
CPU time 55.8 seconds
Started Jun 29 04:34:37 PM PDT 24
Finished Jun 29 04:35:33 PM PDT 24
Peak memory 219236 kb
Host smart-bac52339-4aa8-4828-a7c3-87744873b570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935749238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3935749238
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.4041800252
Short name T304
Test name
Test status
Simulation time 4744423124 ps
CPU time 24.09 seconds
Started Jun 29 04:34:33 PM PDT 24
Finished Jun 29 04:34:57 PM PDT 24
Peak memory 219240 kb
Host smart-de1d054d-d009-4e52-9ec0-de17c4704eac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4041800252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.4041800252
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.1192813876
Short name T322
Test name
Test status
Simulation time 16419518398 ps
CPU time 44.31 seconds
Started Jun 29 04:34:34 PM PDT 24
Finished Jun 29 04:35:18 PM PDT 24
Peak memory 215852 kb
Host smart-ce376b99-ec83-48af-8124-4deb42dbe5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192813876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.1192813876
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.1310754190
Short name T362
Test name
Test status
Simulation time 14584718729 ps
CPU time 73.48 seconds
Started Jun 29 04:34:39 PM PDT 24
Finished Jun 29 04:35:52 PM PDT 24
Peak memory 217164 kb
Host smart-2d8c153b-6c7c-45a4-8e65-160212395da5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310754190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.1310754190
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.4294293506
Short name T52
Test name
Test status
Simulation time 3762082678 ps
CPU time 20.17 seconds
Started Jun 29 04:34:38 PM PDT 24
Finished Jun 29 04:34:59 PM PDT 24
Peak memory 215860 kb
Host smart-79c251bf-1a83-4a99-b0b0-4ff68b4eaf4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294293506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.4294293506
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1755359311
Short name T331
Test name
Test status
Simulation time 178449213748 ps
CPU time 471.25 seconds
Started Jun 29 04:34:38 PM PDT 24
Finished Jun 29 04:42:30 PM PDT 24
Peak memory 225396 kb
Host smart-bd04017a-7ff4-4e92-a2bb-77ea3caa2c1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755359311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1755359311
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.769794652
Short name T27
Test name
Test status
Simulation time 12958136572 ps
CPU time 50.34 seconds
Started Jun 29 04:34:39 PM PDT 24
Finished Jun 29 04:35:30 PM PDT 24
Peak memory 219252 kb
Host smart-0902d9d0-034d-47f0-a018-51fdd113c0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769794652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.769794652
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1713325039
Short name T214
Test name
Test status
Simulation time 1053430232 ps
CPU time 17.05 seconds
Started Jun 29 04:34:36 PM PDT 24
Finished Jun 29 04:34:53 PM PDT 24
Peak memory 211584 kb
Host smart-813297b5-5a2c-4d0e-af7b-bce51d582afe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1713325039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1713325039
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3052599372
Short name T224
Test name
Test status
Simulation time 4441635521 ps
CPU time 52.19 seconds
Started Jun 29 04:34:35 PM PDT 24
Finished Jun 29 04:35:27 PM PDT 24
Peak memory 216568 kb
Host smart-13695a07-7fbe-4bbe-a136-5a914faffc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052599372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3052599372
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2616884968
Short name T348
Test name
Test status
Simulation time 560991480 ps
CPU time 23.6 seconds
Started Jun 29 04:34:37 PM PDT 24
Finished Jun 29 04:35:01 PM PDT 24
Peak memory 217900 kb
Host smart-cb6ab7f0-eb8e-4590-a66d-ac90c9ffd155
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616884968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2616884968
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2567235662
Short name T207
Test name
Test status
Simulation time 5801915760 ps
CPU time 17.33 seconds
Started Jun 29 04:34:32 PM PDT 24
Finished Jun 29 04:34:50 PM PDT 24
Peak memory 216740 kb
Host smart-d8dde197-21bb-4977-b29f-446608d09510
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567235662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2567235662
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2422068055
Short name T176
Test name
Test status
Simulation time 156869373133 ps
CPU time 488.49 seconds
Started Jun 29 04:34:40 PM PDT 24
Finished Jun 29 04:42:49 PM PDT 24
Peak memory 234924 kb
Host smart-3031bc5f-9ec1-44bf-9eff-728e063b1006
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422068055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2422068055
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3736776610
Short name T313
Test name
Test status
Simulation time 10431336106 ps
CPU time 65.16 seconds
Started Jun 29 04:34:40 PM PDT 24
Finished Jun 29 04:35:46 PM PDT 24
Peak memory 218984 kb
Host smart-8545e58c-4660-4067-b7f4-79a231e3356b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736776610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3736776610
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1139597488
Short name T131
Test name
Test status
Simulation time 1676918348 ps
CPU time 15.09 seconds
Started Jun 29 04:34:38 PM PDT 24
Finished Jun 29 04:34:53 PM PDT 24
Peak memory 218616 kb
Host smart-81505a5f-267a-44b2-883b-d462261a6058
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1139597488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1139597488
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.501564905
Short name T128
Test name
Test status
Simulation time 7211419335 ps
CPU time 57.62 seconds
Started Jun 29 04:34:38 PM PDT 24
Finished Jun 29 04:35:36 PM PDT 24
Peak memory 216936 kb
Host smart-ea792994-8424-4405-803b-4b2434e0bc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501564905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.501564905
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.962382092
Short name T315
Test name
Test status
Simulation time 23845370912 ps
CPU time 60.66 seconds
Started Jun 29 04:35:23 PM PDT 24
Finished Jun 29 04:36:24 PM PDT 24
Peak memory 217528 kb
Host smart-e16a39af-5248-4ff7-8ec8-9e50c0203b55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962382092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.962382092
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.356396511
Short name T200
Test name
Test status
Simulation time 1907886153 ps
CPU time 14.71 seconds
Started Jun 29 04:34:37 PM PDT 24
Finished Jun 29 04:34:53 PM PDT 24
Peak memory 217156 kb
Host smart-ee63ef7c-df85-4676-9d65-e7617d90b394
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356396511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.356396511
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.514973266
Short name T54
Test name
Test status
Simulation time 25064910957 ps
CPU time 333.05 seconds
Started Jun 29 04:34:43 PM PDT 24
Finished Jun 29 04:40:17 PM PDT 24
Peak memory 239668 kb
Host smart-63b1cdc2-b1f7-4c9c-b683-409e9e53b3d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514973266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.514973266
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.4230647000
Short name T205
Test name
Test status
Simulation time 1320247988 ps
CPU time 19.31 seconds
Started Jun 29 04:34:38 PM PDT 24
Finished Jun 29 04:34:58 PM PDT 24
Peak memory 219176 kb
Host smart-0e01713e-5d33-460b-b316-e410253f3e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230647000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.4230647000
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.410731910
Short name T167
Test name
Test status
Simulation time 5021203905 ps
CPU time 31.01 seconds
Started Jun 29 04:34:36 PM PDT 24
Finished Jun 29 04:35:08 PM PDT 24
Peak memory 219244 kb
Host smart-8810b32b-c190-4ff6-89fb-e2bc30c75aa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=410731910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.410731910
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2701397194
Short name T288
Test name
Test status
Simulation time 25575879321 ps
CPU time 57.31 seconds
Started Jun 29 04:34:37 PM PDT 24
Finished Jun 29 04:35:35 PM PDT 24
Peak memory 216856 kb
Host smart-3431c9b6-30d5-4e4d-b6a1-7c69c4a7150c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701397194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2701397194
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1517534379
Short name T239
Test name
Test status
Simulation time 6895235175 ps
CPU time 36.51 seconds
Started Jun 29 04:34:42 PM PDT 24
Finished Jun 29 04:35:19 PM PDT 24
Peak memory 218520 kb
Host smart-f9279511-228e-4e77-9748-48b23a6803e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517534379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1517534379
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2933571758
Short name T245
Test name
Test status
Simulation time 170960550 ps
CPU time 8.4 seconds
Started Jun 29 04:34:36 PM PDT 24
Finished Jun 29 04:34:45 PM PDT 24
Peak memory 213084 kb
Host smart-9c8a667a-19f1-4cfa-8db6-c6de34a8ff92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933571758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2933571758
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.445575881
Short name T36
Test name
Test status
Simulation time 3796165300 ps
CPU time 249.99 seconds
Started Jun 29 04:34:41 PM PDT 24
Finished Jun 29 04:38:52 PM PDT 24
Peak memory 219388 kb
Host smart-053e2f8e-ed17-46c9-b041-9e828db304d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445575881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.445575881
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.393866911
Short name T338
Test name
Test status
Simulation time 6963860252 ps
CPU time 58.29 seconds
Started Jun 29 04:34:35 PM PDT 24
Finished Jun 29 04:35:34 PM PDT 24
Peak memory 219068 kb
Host smart-1113d1e8-8a2f-48a5-ae2f-7b9dc07758ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393866911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.393866911
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3630458602
Short name T125
Test name
Test status
Simulation time 18905324866 ps
CPU time 19.42 seconds
Started Jun 29 04:34:36 PM PDT 24
Finished Jun 29 04:34:56 PM PDT 24
Peak memory 217616 kb
Host smart-13447e42-1e1f-4a44-9bba-4c23a64324c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3630458602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3630458602
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3171679595
Short name T1
Test name
Test status
Simulation time 364203828 ps
CPU time 20.3 seconds
Started Jun 29 04:34:39 PM PDT 24
Finished Jun 29 04:35:00 PM PDT 24
Peak memory 215568 kb
Host smart-471ddb37-fb9f-4cb6-a09c-aec809c7f7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171679595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3171679595
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2698418838
Short name T273
Test name
Test status
Simulation time 22716225816 ps
CPU time 249.23 seconds
Started Jun 29 04:34:37 PM PDT 24
Finished Jun 29 04:38:47 PM PDT 24
Peak memory 230632 kb
Host smart-cc0fab20-cffe-47bc-823e-a30e71296a9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698418838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2698418838
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1296810289
Short name T153
Test name
Test status
Simulation time 174504945 ps
CPU time 8.62 seconds
Started Jun 29 04:34:41 PM PDT 24
Finished Jun 29 04:34:50 PM PDT 24
Peak memory 217136 kb
Host smart-265d0400-1812-4789-94f0-ee307ae3d19f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296810289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1296810289
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2574624934
Short name T317
Test name
Test status
Simulation time 116024668850 ps
CPU time 550.52 seconds
Started Jun 29 04:34:33 PM PDT 24
Finished Jun 29 04:43:44 PM PDT 24
Peak memory 237408 kb
Host smart-6b7b2c85-86c6-4e7e-a4ce-6417d0c24da2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574624934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2574624934
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1137770447
Short name T3
Test name
Test status
Simulation time 16749041650 ps
CPU time 64.54 seconds
Started Jun 29 04:34:46 PM PDT 24
Finished Jun 29 04:35:51 PM PDT 24
Peak memory 219260 kb
Host smart-729991a3-7f12-45d6-8039-bf34ceeafb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137770447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1137770447
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.776121745
Short name T336
Test name
Test status
Simulation time 177779508 ps
CPU time 10.71 seconds
Started Jun 29 04:34:37 PM PDT 24
Finished Jun 29 04:34:49 PM PDT 24
Peak memory 219204 kb
Host smart-6fe68830-1c58-4edb-8534-44044af1f736
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=776121745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.776121745
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2131027606
Short name T174
Test name
Test status
Simulation time 351992973 ps
CPU time 20.53 seconds
Started Jun 29 04:34:37 PM PDT 24
Finished Jun 29 04:34:58 PM PDT 24
Peak memory 215976 kb
Host smart-12e82029-6596-4fea-89ba-9938ab15a23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131027606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2131027606
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1445019765
Short name T305
Test name
Test status
Simulation time 22780910552 ps
CPU time 195.43 seconds
Started Jun 29 04:34:35 PM PDT 24
Finished Jun 29 04:37:51 PM PDT 24
Peak memory 227844 kb
Host smart-e1d87bde-2310-41ae-970d-232a5fc86495
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445019765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1445019765
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2701178677
Short name T172
Test name
Test status
Simulation time 4057619154 ps
CPU time 33.25 seconds
Started Jun 29 04:34:43 PM PDT 24
Finished Jun 29 04:35:18 PM PDT 24
Peak memory 217172 kb
Host smart-8d09bc94-233c-4e64-b2f6-de5500ad5a16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701178677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2701178677
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.972923957
Short name T32
Test name
Test status
Simulation time 27225364041 ps
CPU time 412.15 seconds
Started Jun 29 04:34:43 PM PDT 24
Finished Jun 29 04:41:36 PM PDT 24
Peak memory 226068 kb
Host smart-933a7b20-617e-47db-b5ea-b359d4a2e2bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972923957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.972923957
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3364332898
Short name T147
Test name
Test status
Simulation time 17338099467 ps
CPU time 70.14 seconds
Started Jun 29 04:34:45 PM PDT 24
Finished Jun 29 04:35:56 PM PDT 24
Peak memory 219240 kb
Host smart-f73f9500-ffab-4f40-8887-143fedeceb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364332898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3364332898
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2247251257
Short name T208
Test name
Test status
Simulation time 706184065 ps
CPU time 10.48 seconds
Started Jun 29 04:34:42 PM PDT 24
Finished Jun 29 04:34:53 PM PDT 24
Peak memory 219208 kb
Host smart-5b740f54-8c50-4cc6-b23f-7094f6e86f2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2247251257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2247251257
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1505110744
Short name T79
Test name
Test status
Simulation time 16499761033 ps
CPU time 76.22 seconds
Started Jun 29 04:34:44 PM PDT 24
Finished Jun 29 04:36:01 PM PDT 24
Peak memory 217284 kb
Host smart-c6364707-8382-4ab9-99b3-00e0a9e18f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505110744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1505110744
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2945756745
Short name T230
Test name
Test status
Simulation time 148488096987 ps
CPU time 124.06 seconds
Started Jun 29 04:34:47 PM PDT 24
Finished Jun 29 04:36:51 PM PDT 24
Peak memory 220276 kb
Host smart-5f7ecba0-851e-420d-8d42-e3e7e7aab803
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945756745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2945756745
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2347569657
Short name T303
Test name
Test status
Simulation time 3895867604 ps
CPU time 14.18 seconds
Started Jun 29 04:34:44 PM PDT 24
Finished Jun 29 04:34:59 PM PDT 24
Peak memory 213288 kb
Host smart-b158eaf2-c2d5-4b6c-b32f-2cb68611d2fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347569657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2347569657
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1676878194
Short name T247
Test name
Test status
Simulation time 67321125095 ps
CPU time 311.67 seconds
Started Jun 29 04:34:41 PM PDT 24
Finished Jun 29 04:39:53 PM PDT 24
Peak memory 224208 kb
Host smart-2b9ab60a-fc11-4c91-9a69-c051d955754d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676878194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1676878194
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2037194797
Short name T297
Test name
Test status
Simulation time 15999046661 ps
CPU time 68.6 seconds
Started Jun 29 04:34:44 PM PDT 24
Finished Jun 29 04:35:54 PM PDT 24
Peak memory 219212 kb
Host smart-cfedf424-fce3-4bc0-9072-c8e9b6d56092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037194797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2037194797
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1041751950
Short name T168
Test name
Test status
Simulation time 28308881479 ps
CPU time 33.33 seconds
Started Jun 29 04:34:42 PM PDT 24
Finished Jun 29 04:35:16 PM PDT 24
Peak memory 217736 kb
Host smart-e46f26a2-d41d-429a-9dd1-9b064be64de7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1041751950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1041751950
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2952143581
Short name T20
Test name
Test status
Simulation time 19823289550 ps
CPU time 48.45 seconds
Started Jun 29 04:34:45 PM PDT 24
Finished Jun 29 04:35:34 PM PDT 24
Peak memory 215964 kb
Host smart-8e69e742-77db-4d7b-9324-bb26760554e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952143581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2952143581
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.713768328
Short name T82
Test name
Test status
Simulation time 68437621864 ps
CPU time 48.86 seconds
Started Jun 29 04:34:43 PM PDT 24
Finished Jun 29 04:35:34 PM PDT 24
Peak memory 217656 kb
Host smart-564717e8-7c2f-49a0-8e29-24dc153c9611
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713768328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.713768328
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3680884068
Short name T64
Test name
Test status
Simulation time 45358177641 ps
CPU time 26.48 seconds
Started Jun 29 04:34:43 PM PDT 24
Finished Jun 29 04:35:11 PM PDT 24
Peak memory 217476 kb
Host smart-59506bb7-10da-4de3-87bd-f9fa3bb5c827
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680884068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3680884068
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2010294791
Short name T262
Test name
Test status
Simulation time 58022160349 ps
CPU time 536.98 seconds
Started Jun 29 04:34:43 PM PDT 24
Finished Jun 29 04:43:42 PM PDT 24
Peak memory 224720 kb
Host smart-530485f8-3751-43e9-9fe0-770cbf1f9bea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010294791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2010294791
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3053495936
Short name T38
Test name
Test status
Simulation time 335925591 ps
CPU time 19.44 seconds
Started Jun 29 04:34:44 PM PDT 24
Finished Jun 29 04:35:05 PM PDT 24
Peak memory 219208 kb
Host smart-bb7eef9e-5a54-4f54-b854-5f1fdc91c6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053495936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3053495936
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3827928039
Short name T146
Test name
Test status
Simulation time 732963925 ps
CPU time 10.6 seconds
Started Jun 29 04:34:48 PM PDT 24
Finished Jun 29 04:34:59 PM PDT 24
Peak memory 219288 kb
Host smart-a5a62f29-6af7-45cf-b897-d69966cfa36b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3827928039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3827928039
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1269374076
Short name T314
Test name
Test status
Simulation time 1383147296 ps
CPU time 20.53 seconds
Started Jun 29 04:34:44 PM PDT 24
Finished Jun 29 04:35:06 PM PDT 24
Peak memory 216692 kb
Host smart-c1bb2a5f-73c4-473c-8f14-b9d3d1328809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269374076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1269374076
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3274243341
Short name T231
Test name
Test status
Simulation time 18613912457 ps
CPU time 54.95 seconds
Started Jun 29 04:34:44 PM PDT 24
Finished Jun 29 04:35:40 PM PDT 24
Peak memory 216976 kb
Host smart-f7049395-e4d2-49bc-8d48-dcdedb6de449
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274243341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3274243341
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.809297357
Short name T332
Test name
Test status
Simulation time 4419667314 ps
CPU time 33.77 seconds
Started Jun 29 04:34:43 PM PDT 24
Finished Jun 29 04:35:17 PM PDT 24
Peak memory 217524 kb
Host smart-85076d03-70fd-4e98-91df-6cbc02c0d38e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809297357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.809297357
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.728171755
Short name T197
Test name
Test status
Simulation time 35516975612 ps
CPU time 291.71 seconds
Started Jun 29 04:34:43 PM PDT 24
Finished Jun 29 04:39:36 PM PDT 24
Peak memory 218792 kb
Host smart-6bf7e2fc-58c3-4527-bb9c-1f4968511ce0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728171755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.728171755
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3823747269
Short name T178
Test name
Test status
Simulation time 3838461158 ps
CPU time 28.35 seconds
Started Jun 29 04:34:41 PM PDT 24
Finished Jun 29 04:35:10 PM PDT 24
Peak memory 215696 kb
Host smart-464b9289-f5ad-4af4-91df-615c9e1bfe8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823747269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3823747269
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3731413142
Short name T343
Test name
Test status
Simulation time 603850523 ps
CPU time 14.88 seconds
Started Jun 29 04:34:47 PM PDT 24
Finished Jun 29 04:35:02 PM PDT 24
Peak memory 219196 kb
Host smart-2247db99-2518-4fb0-a217-656382038298
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3731413142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3731413142
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.615980156
Short name T190
Test name
Test status
Simulation time 34090362438 ps
CPU time 74.4 seconds
Started Jun 29 04:34:49 PM PDT 24
Finished Jun 29 04:36:04 PM PDT 24
Peak memory 216552 kb
Host smart-d40a2aed-057b-4afc-aee0-c4e1c753b791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615980156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.615980156
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1525105074
Short name T328
Test name
Test status
Simulation time 3997365236 ps
CPU time 50.59 seconds
Started Jun 29 04:34:44 PM PDT 24
Finished Jun 29 04:35:36 PM PDT 24
Peak memory 219008 kb
Host smart-7418be67-0b69-47d1-8add-6b28a080adc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525105074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1525105074
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.640549776
Short name T254
Test name
Test status
Simulation time 751070349 ps
CPU time 8.46 seconds
Started Jun 29 04:34:11 PM PDT 24
Finished Jun 29 04:34:20 PM PDT 24
Peak memory 217160 kb
Host smart-3ac4812b-b7f8-4019-b059-76ae115d7dbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640549776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.640549776
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.239287843
Short name T42
Test name
Test status
Simulation time 294319217100 ps
CPU time 679.14 seconds
Started Jun 29 04:34:00 PM PDT 24
Finished Jun 29 04:45:20 PM PDT 24
Peak memory 235948 kb
Host smart-a1a5859b-808f-4743-b8a0-fe640ae73b39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239287843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.239287843
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.981623960
Short name T188
Test name
Test status
Simulation time 346555810 ps
CPU time 19.41 seconds
Started Jun 29 04:34:03 PM PDT 24
Finished Jun 29 04:34:23 PM PDT 24
Peak memory 219196 kb
Host smart-74bc0f8c-70b5-4d14-bfc9-8491b999cbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981623960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.981623960
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.4136976288
Short name T10
Test name
Test status
Simulation time 1583298500 ps
CPU time 16.89 seconds
Started Jun 29 04:34:00 PM PDT 24
Finished Jun 29 04:34:17 PM PDT 24
Peak memory 219176 kb
Host smart-c60a91ff-25ae-4d43-ac07-8300aa2e2c60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4136976288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.4136976288
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1257526108
Short name T29
Test name
Test status
Simulation time 2717741480 ps
CPU time 232.89 seconds
Started Jun 29 04:34:03 PM PDT 24
Finished Jun 29 04:37:56 PM PDT 24
Peak memory 237784 kb
Host smart-0695c893-1de8-40d5-8853-0f1bb3b781bc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257526108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1257526108
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1744212120
Short name T347
Test name
Test status
Simulation time 7179595563 ps
CPU time 65.4 seconds
Started Jun 29 04:34:00 PM PDT 24
Finished Jun 29 04:35:06 PM PDT 24
Peak memory 216832 kb
Host smart-39628c25-b510-4a4a-ab8a-6d8e025fcb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744212120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1744212120
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1241549225
Short name T217
Test name
Test status
Simulation time 21199077413 ps
CPU time 94.56 seconds
Started Jun 29 04:34:00 PM PDT 24
Finished Jun 29 04:35:35 PM PDT 24
Peak memory 219236 kb
Host smart-d3c5e1ca-a11b-4d24-8bfb-32ad48336dc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241549225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1241549225
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3538478472
Short name T259
Test name
Test status
Simulation time 1100442654 ps
CPU time 8.42 seconds
Started Jun 29 04:34:42 PM PDT 24
Finished Jun 29 04:34:52 PM PDT 24
Peak memory 217140 kb
Host smart-56d85c08-4065-4f16-a62d-108e1934e213
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538478472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3538478472
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1974604448
Short name T160
Test name
Test status
Simulation time 576221798240 ps
CPU time 574.87 seconds
Started Jun 29 04:34:43 PM PDT 24
Finished Jun 29 04:44:20 PM PDT 24
Peak memory 235688 kb
Host smart-3550cb9f-b3f0-49f7-8773-f2eef420382c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974604448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1974604448
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2859334071
Short name T358
Test name
Test status
Simulation time 44574404754 ps
CPU time 49.18 seconds
Started Jun 29 04:34:46 PM PDT 24
Finished Jun 29 04:35:35 PM PDT 24
Peak memory 219244 kb
Host smart-18523361-e85a-4e81-8d44-d024c6af6e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859334071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2859334071
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.4244247921
Short name T324
Test name
Test status
Simulation time 4048765568 ps
CPU time 33.61 seconds
Started Jun 29 04:34:44 PM PDT 24
Finished Jun 29 04:35:19 PM PDT 24
Peak memory 219264 kb
Host smart-a58e8e2a-e192-4db4-b104-b78e6fa1156c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4244247921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.4244247921
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1446958630
Short name T357
Test name
Test status
Simulation time 348341961 ps
CPU time 19.52 seconds
Started Jun 29 04:34:44 PM PDT 24
Finished Jun 29 04:35:05 PM PDT 24
Peak memory 215968 kb
Host smart-20e730f3-b22c-4044-8aa0-518afbcfd525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446958630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1446958630
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1162363469
Short name T265
Test name
Test status
Simulation time 2017981001 ps
CPU time 75.49 seconds
Started Jun 29 04:34:48 PM PDT 24
Finished Jun 29 04:36:04 PM PDT 24
Peak memory 219380 kb
Host smart-fc65e650-c71f-4364-b355-94e51f03b495
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162363469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1162363469
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2772497502
Short name T225
Test name
Test status
Simulation time 11186872209 ps
CPU time 25.65 seconds
Started Jun 29 04:34:42 PM PDT 24
Finished Jun 29 04:35:08 PM PDT 24
Peak memory 217336 kb
Host smart-b387fdeb-4cf1-45ee-9857-c9d3196db98f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772497502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2772497502
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2460860413
Short name T218
Test name
Test status
Simulation time 205313912945 ps
CPU time 396.06 seconds
Started Jun 29 04:34:46 PM PDT 24
Finished Jun 29 04:41:22 PM PDT 24
Peak memory 219416 kb
Host smart-9b732db5-4b39-43c7-8297-a5f1d7305e68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460860413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2460860413
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1884659261
Short name T312
Test name
Test status
Simulation time 6719222514 ps
CPU time 60.66 seconds
Started Jun 29 04:34:42 PM PDT 24
Finished Jun 29 04:35:43 PM PDT 24
Peak memory 219264 kb
Host smart-6083e803-28a6-4e47-bdcd-85a58eff2d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884659261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1884659261
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2181695499
Short name T124
Test name
Test status
Simulation time 6317678807 ps
CPU time 25.68 seconds
Started Jun 29 04:34:43 PM PDT 24
Finished Jun 29 04:35:10 PM PDT 24
Peak memory 211644 kb
Host smart-9e8e2ba1-86ff-4e96-997d-0b52dc69dd6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2181695499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2181695499
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2071016238
Short name T302
Test name
Test status
Simulation time 7273449675 ps
CPU time 31.88 seconds
Started Jun 29 04:34:44 PM PDT 24
Finished Jun 29 04:35:17 PM PDT 24
Peak memory 216536 kb
Host smart-f5028fd0-6c05-4c90-8e00-876f94b3a5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071016238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2071016238
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1354978246
Short name T258
Test name
Test status
Simulation time 16238773612 ps
CPU time 79.1 seconds
Started Jun 29 04:34:46 PM PDT 24
Finished Jun 29 04:36:06 PM PDT 24
Peak memory 220428 kb
Host smart-d45b50af-77c2-4b08-a634-fb15ad6d4304
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354978246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1354978246
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2863074459
Short name T210
Test name
Test status
Simulation time 1726747111 ps
CPU time 19.28 seconds
Started Jun 29 04:34:51 PM PDT 24
Finished Jun 29 04:35:11 PM PDT 24
Peak memory 217028 kb
Host smart-f2ba9f90-cc2e-4d79-8c31-21c5c6d43205
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863074459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2863074459
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1819704975
Short name T9
Test name
Test status
Simulation time 10290304778 ps
CPU time 157.24 seconds
Started Jun 29 04:34:42 PM PDT 24
Finished Jun 29 04:37:20 PM PDT 24
Peak memory 219388 kb
Host smart-a7facb56-9db5-44b7-9e3d-0118f77dac68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819704975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1819704975
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2564362000
Short name T355
Test name
Test status
Simulation time 1650898033 ps
CPU time 30.35 seconds
Started Jun 29 04:34:48 PM PDT 24
Finished Jun 29 04:35:19 PM PDT 24
Peak memory 219252 kb
Host smart-c5ec6dba-3927-4662-a703-4425c73cd41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564362000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2564362000
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.499016975
Short name T149
Test name
Test status
Simulation time 8606156110 ps
CPU time 31.95 seconds
Started Jun 29 04:34:47 PM PDT 24
Finished Jun 29 04:35:19 PM PDT 24
Peak memory 217620 kb
Host smart-5603f53d-4ede-4465-88ac-7c0ab1c0aeae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=499016975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.499016975
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.676562153
Short name T329
Test name
Test status
Simulation time 431872051 ps
CPU time 21.22 seconds
Started Jun 29 04:34:50 PM PDT 24
Finished Jun 29 04:35:12 PM PDT 24
Peak memory 216444 kb
Host smart-18bc9e8f-1ceb-44c0-a70d-844fd1b520a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676562153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.676562153
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.4165214513
Short name T319
Test name
Test status
Simulation time 3430933010 ps
CPU time 51.04 seconds
Started Jun 29 04:34:46 PM PDT 24
Finished Jun 29 04:35:38 PM PDT 24
Peak memory 219716 kb
Host smart-7eaab5b1-0994-4b1f-84a7-d36645ef8574
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165214513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.4165214513
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2233408611
Short name T68
Test name
Test status
Simulation time 6788505240 ps
CPU time 25.38 seconds
Started Jun 29 04:34:53 PM PDT 24
Finished Jun 29 04:35:19 PM PDT 24
Peak memory 213040 kb
Host smart-43fc0bc3-2834-4a02-8040-291543410f5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233408611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2233408611
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3831544665
Short name T248
Test name
Test status
Simulation time 55662861424 ps
CPU time 667.94 seconds
Started Jun 29 04:34:51 PM PDT 24
Finished Jun 29 04:46:00 PM PDT 24
Peak memory 219412 kb
Host smart-e79c49fe-7875-479d-93e1-3835ca496f53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831544665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3831544665
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2885397230
Short name T150
Test name
Test status
Simulation time 18161174412 ps
CPU time 51.52 seconds
Started Jun 29 04:34:56 PM PDT 24
Finished Jun 29 04:35:48 PM PDT 24
Peak memory 219232 kb
Host smart-634306cb-eff6-4f24-9d66-69e5683411b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885397230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2885397230
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2520178458
Short name T169
Test name
Test status
Simulation time 4883495110 ps
CPU time 24.94 seconds
Started Jun 29 04:34:57 PM PDT 24
Finished Jun 29 04:35:22 PM PDT 24
Peak memory 211544 kb
Host smart-5bfdc11d-2697-4f0b-8782-cccfbd7a6c6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2520178458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2520178458
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2089765759
Short name T246
Test name
Test status
Simulation time 12701409408 ps
CPU time 69.29 seconds
Started Jun 29 04:34:54 PM PDT 24
Finished Jun 29 04:36:04 PM PDT 24
Peak memory 216660 kb
Host smart-7c623a24-a908-409b-9bf8-853ec47e804f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089765759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2089765759
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1922957374
Short name T201
Test name
Test status
Simulation time 4642110125 ps
CPU time 72.02 seconds
Started Jun 29 04:34:54 PM PDT 24
Finished Jun 29 04:36:06 PM PDT 24
Peak memory 219616 kb
Host smart-85b9f901-91f7-4d2b-af07-8eeb77a76999
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922957374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1922957374
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.4045290156
Short name T45
Test name
Test status
Simulation time 21333099530 ps
CPU time 3458.45 seconds
Started Jun 29 04:34:55 PM PDT 24
Finished Jun 29 05:32:34 PM PDT 24
Peak memory 235680 kb
Host smart-e4518c68-e3ae-4c6d-bcf0-cf6f423e74ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045290156 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.4045290156
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3964724954
Short name T138
Test name
Test status
Simulation time 3441189328 ps
CPU time 30.07 seconds
Started Jun 29 04:34:51 PM PDT 24
Finished Jun 29 04:35:22 PM PDT 24
Peak memory 217204 kb
Host smart-e76918cc-9de0-45ad-8ade-3cea1000aa93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964724954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3964724954
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1414316459
Short name T199
Test name
Test status
Simulation time 59001329737 ps
CPU time 271.36 seconds
Started Jun 29 04:34:52 PM PDT 24
Finished Jun 29 04:39:24 PM PDT 24
Peak memory 225572 kb
Host smart-2e187471-8dc8-4ad4-b902-bfff671a89a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414316459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1414316459
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1345055347
Short name T50
Test name
Test status
Simulation time 15663346459 ps
CPU time 59.69 seconds
Started Jun 29 04:34:53 PM PDT 24
Finished Jun 29 04:35:53 PM PDT 24
Peak memory 219224 kb
Host smart-0c1538aa-0410-4eb0-94a2-1674f86b8e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345055347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1345055347
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1089226541
Short name T179
Test name
Test status
Simulation time 2193241262 ps
CPU time 10.44 seconds
Started Jun 29 04:34:53 PM PDT 24
Finished Jun 29 04:35:04 PM PDT 24
Peak memory 219248 kb
Host smart-c9120eb2-3d5f-45c3-b55b-feed8847b550
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1089226541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1089226541
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.614089092
Short name T164
Test name
Test status
Simulation time 3455578508 ps
CPU time 40.58 seconds
Started Jun 29 04:34:48 PM PDT 24
Finished Jun 29 04:35:29 PM PDT 24
Peak memory 216256 kb
Host smart-c0c71ddd-80fd-4a2a-b8bd-5bb3f168e577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614089092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.614089092
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3551368713
Short name T129
Test name
Test status
Simulation time 18471148873 ps
CPU time 157.32 seconds
Started Jun 29 04:34:52 PM PDT 24
Finished Jun 29 04:37:30 PM PDT 24
Peak memory 219280 kb
Host smart-6f249b4f-135b-4471-93fc-2fb4d09c39e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551368713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3551368713
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2815279050
Short name T44
Test name
Test status
Simulation time 38016668705 ps
CPU time 4519.1 seconds
Started Jun 29 04:34:54 PM PDT 24
Finished Jun 29 05:50:15 PM PDT 24
Peak memory 235716 kb
Host smart-41e82e8f-afaa-4cbc-a202-5a56d7f2dd1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815279050 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.2815279050
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.164132537
Short name T298
Test name
Test status
Simulation time 7249234464 ps
CPU time 20.53 seconds
Started Jun 29 04:34:51 PM PDT 24
Finished Jun 29 04:35:12 PM PDT 24
Peak memory 217544 kb
Host smart-0724e1c1-172b-4459-9c13-e3468735b427
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164132537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.164132537
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3833654231
Short name T266
Test name
Test status
Simulation time 191986573619 ps
CPU time 328.62 seconds
Started Jun 29 04:34:50 PM PDT 24
Finished Jun 29 04:40:19 PM PDT 24
Peak memory 235072 kb
Host smart-9f46401a-4563-4574-b44a-6fc9adf03835
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833654231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3833654231
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.23320635
Short name T223
Test name
Test status
Simulation time 21004753327 ps
CPU time 52.22 seconds
Started Jun 29 04:34:52 PM PDT 24
Finished Jun 29 04:35:44 PM PDT 24
Peak memory 218976 kb
Host smart-50190f18-d8ce-4b84-bc74-6b95d4c20886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23320635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.23320635
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3563567627
Short name T127
Test name
Test status
Simulation time 2414795580 ps
CPU time 18.01 seconds
Started Jun 29 04:34:50 PM PDT 24
Finished Jun 29 04:35:08 PM PDT 24
Peak memory 219256 kb
Host smart-b0955384-888b-471d-8670-6b9418dbc0b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3563567627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3563567627
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.4177922299
Short name T299
Test name
Test status
Simulation time 2707228288 ps
CPU time 29.44 seconds
Started Jun 29 04:34:55 PM PDT 24
Finished Jun 29 04:35:25 PM PDT 24
Peak memory 216360 kb
Host smart-e2b0903a-51cc-4e3c-b4e0-1340025b2fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177922299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.4177922299
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.75572091
Short name T270
Test name
Test status
Simulation time 3765185788 ps
CPU time 39.66 seconds
Started Jun 29 04:34:54 PM PDT 24
Finished Jun 29 04:35:34 PM PDT 24
Peak memory 219140 kb
Host smart-80f984c0-b7b8-4801-b772-4666f1c20cd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75572091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 35.rom_ctrl_stress_all.75572091
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.646436361
Short name T251
Test name
Test status
Simulation time 16438218036 ps
CPU time 25.13 seconds
Started Jun 29 04:34:53 PM PDT 24
Finished Jun 29 04:35:19 PM PDT 24
Peak memory 217460 kb
Host smart-ea26585c-0ac1-4b81-9777-42611b45ba0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646436361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.646436361
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1029693148
Short name T335
Test name
Test status
Simulation time 109748222526 ps
CPU time 339.52 seconds
Started Jun 29 04:34:52 PM PDT 24
Finished Jun 29 04:40:32 PM PDT 24
Peak memory 224720 kb
Host smart-7349b17b-63cd-4c53-b7a9-0e3f014b46dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029693148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1029693148
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2116499053
Short name T219
Test name
Test status
Simulation time 2025235007 ps
CPU time 32.88 seconds
Started Jun 29 04:34:54 PM PDT 24
Finished Jun 29 04:35:28 PM PDT 24
Peak memory 219256 kb
Host smart-253573ab-9dca-44c5-8d78-5860f7c2c088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116499053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2116499053
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1365838017
Short name T263
Test name
Test status
Simulation time 175274027 ps
CPU time 10.42 seconds
Started Jun 29 04:34:49 PM PDT 24
Finished Jun 29 04:35:00 PM PDT 24
Peak memory 219216 kb
Host smart-8cd17b27-e6d5-462d-8aba-12ae58bf63a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1365838017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1365838017
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3120471319
Short name T105
Test name
Test status
Simulation time 17262684242 ps
CPU time 56.06 seconds
Started Jun 29 04:34:51 PM PDT 24
Finished Jun 29 04:35:47 PM PDT 24
Peak memory 217864 kb
Host smart-c89804c1-170b-41b5-a774-780cb7123dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120471319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3120471319
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3520537832
Short name T286
Test name
Test status
Simulation time 345225446 ps
CPU time 20.1 seconds
Started Jun 29 04:34:57 PM PDT 24
Finished Jun 29 04:35:17 PM PDT 24
Peak memory 218400 kb
Host smart-829c43a2-2a9c-4d57-abc1-cdec98b28d4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520537832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3520537832
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2270612734
Short name T361
Test name
Test status
Simulation time 13975068198 ps
CPU time 29 seconds
Started Jun 29 04:34:49 PM PDT 24
Finished Jun 29 04:35:19 PM PDT 24
Peak memory 213196 kb
Host smart-8fcc9247-d7d1-43ec-ae2e-89eddbecdb8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270612734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2270612734
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2274557823
Short name T202
Test name
Test status
Simulation time 221519810718 ps
CPU time 476.03 seconds
Started Jun 29 04:34:52 PM PDT 24
Finished Jun 29 04:42:49 PM PDT 24
Peak memory 224968 kb
Host smart-44469401-f4f6-4e62-98fd-96d0da1ff167
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274557823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2274557823
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.633512851
Short name T15
Test name
Test status
Simulation time 2066460578 ps
CPU time 22.77 seconds
Started Jun 29 04:34:54 PM PDT 24
Finished Jun 29 04:35:18 PM PDT 24
Peak memory 219288 kb
Host smart-df499e41-b27e-404b-9b51-04213310134a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633512851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.633512851
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1902502424
Short name T165
Test name
Test status
Simulation time 734479191 ps
CPU time 10.88 seconds
Started Jun 29 04:34:53 PM PDT 24
Finished Jun 29 04:35:05 PM PDT 24
Peak memory 218940 kb
Host smart-b88ecf39-e04b-498b-96b0-1188926870b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1902502424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1902502424
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1367687826
Short name T180
Test name
Test status
Simulation time 24645615663 ps
CPU time 58.99 seconds
Started Jun 29 04:34:54 PM PDT 24
Finished Jun 29 04:35:54 PM PDT 24
Peak memory 216880 kb
Host smart-f9f69396-bff1-40d5-82d4-33ea47e2ed71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367687826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1367687826
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1835209372
Short name T130
Test name
Test status
Simulation time 16767937429 ps
CPU time 33.29 seconds
Started Jun 29 04:34:52 PM PDT 24
Finished Jun 29 04:35:26 PM PDT 24
Peak memory 216656 kb
Host smart-2eb6730b-77ee-437a-95ad-98c035520b99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835209372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1835209372
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1139021417
Short name T49
Test name
Test status
Simulation time 22447206692 ps
CPU time 884.72 seconds
Started Jun 29 04:34:51 PM PDT 24
Finished Jun 29 04:49:37 PM PDT 24
Peak memory 235688 kb
Host smart-1e4fa1da-982a-485a-86ca-3d6f6f3f7625
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139021417 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.1139021417
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.934514984
Short name T5
Test name
Test status
Simulation time 11867723902 ps
CPU time 25.65 seconds
Started Jun 29 04:34:52 PM PDT 24
Finished Jun 29 04:35:18 PM PDT 24
Peak memory 217368 kb
Host smart-276bbd01-2340-49cd-b163-e26eb1580355
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934514984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.934514984
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3031059756
Short name T272
Test name
Test status
Simulation time 95697179497 ps
CPU time 327.78 seconds
Started Jun 29 04:34:52 PM PDT 24
Finished Jun 29 04:40:20 PM PDT 24
Peak memory 234992 kb
Host smart-1a0785e5-8eab-46b3-8303-a02281b4e53f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031059756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3031059756
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2533953774
Short name T275
Test name
Test status
Simulation time 20994554016 ps
CPU time 37.77 seconds
Started Jun 29 04:34:53 PM PDT 24
Finished Jun 29 04:35:31 PM PDT 24
Peak memory 219300 kb
Host smart-78d7c6fb-1e6b-488c-8dd8-04d1fc4164d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533953774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2533953774
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2523239857
Short name T228
Test name
Test status
Simulation time 3426203232 ps
CPU time 28.93 seconds
Started Jun 29 04:34:52 PM PDT 24
Finished Jun 29 04:35:21 PM PDT 24
Peak memory 219240 kb
Host smart-f4e1dd99-63f5-4059-bb82-00bbd2b1e071
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2523239857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2523239857
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2678276740
Short name T340
Test name
Test status
Simulation time 5313169914 ps
CPU time 55.05 seconds
Started Jun 29 04:34:53 PM PDT 24
Finished Jun 29 04:35:49 PM PDT 24
Peak memory 216904 kb
Host smart-81a81494-27b1-4985-83db-bd7e41d39bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678276740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2678276740
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2390056355
Short name T133
Test name
Test status
Simulation time 12514236316 ps
CPU time 60.7 seconds
Started Jun 29 04:34:51 PM PDT 24
Finished Jun 29 04:35:52 PM PDT 24
Peak memory 219232 kb
Host smart-9d9fdf07-245d-4f4a-b31c-774c76ef1693
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390056355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2390056355
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2187142164
Short name T274
Test name
Test status
Simulation time 688191171 ps
CPU time 8.29 seconds
Started Jun 29 04:34:51 PM PDT 24
Finished Jun 29 04:35:00 PM PDT 24
Peak memory 217036 kb
Host smart-c0681a4c-bbe9-4e64-8c12-b7b25365d801
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187142164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2187142164
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.4194625187
Short name T37
Test name
Test status
Simulation time 189401494740 ps
CPU time 986.89 seconds
Started Jun 29 04:34:54 PM PDT 24
Finished Jun 29 04:51:21 PM PDT 24
Peak memory 234108 kb
Host smart-2c70ad6a-1041-4627-bc56-cf81a41d7aa9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194625187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.4194625187
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2296316166
Short name T278
Test name
Test status
Simulation time 3305554749 ps
CPU time 22.64 seconds
Started Jun 29 04:34:50 PM PDT 24
Finished Jun 29 04:35:13 PM PDT 24
Peak memory 219340 kb
Host smart-0bc16a33-1960-43f6-9ecf-fc3540f100c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296316166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2296316166
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3929102539
Short name T2
Test name
Test status
Simulation time 4335597470 ps
CPU time 16.43 seconds
Started Jun 29 04:34:50 PM PDT 24
Finished Jun 29 04:35:07 PM PDT 24
Peak memory 219240 kb
Host smart-1583e9a8-fa0a-4f95-a670-4d246a221898
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3929102539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3929102539
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.3280675741
Short name T352
Test name
Test status
Simulation time 7382255198 ps
CPU time 52.25 seconds
Started Jun 29 04:34:52 PM PDT 24
Finished Jun 29 04:35:45 PM PDT 24
Peak memory 216460 kb
Host smart-ef3f5139-c1b2-4b27-b8dd-72156ab425b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280675741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.3280675741
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2864667529
Short name T57
Test name
Test status
Simulation time 43862272359 ps
CPU time 528.84 seconds
Started Jun 29 04:34:13 PM PDT 24
Finished Jun 29 04:43:02 PM PDT 24
Peak memory 242580 kb
Host smart-93072025-b2a9-4c73-bada-ec7fc48953e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864667529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2864667529
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3301916637
Short name T289
Test name
Test status
Simulation time 16791993840 ps
CPU time 65.76 seconds
Started Jun 29 04:33:59 PM PDT 24
Finished Jun 29 04:35:05 PM PDT 24
Peak memory 219264 kb
Host smart-1194fb55-ae47-45d8-b6b4-c8c23173abd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301916637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3301916637
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3600693093
Short name T220
Test name
Test status
Simulation time 6488754585 ps
CPU time 14.25 seconds
Started Jun 29 04:34:02 PM PDT 24
Finished Jun 29 04:34:16 PM PDT 24
Peak memory 219232 kb
Host smart-8e6504b0-c7d0-414a-8db6-552edf0e1ea2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3600693093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3600693093
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3475493065
Short name T243
Test name
Test status
Simulation time 32742812790 ps
CPU time 57.03 seconds
Started Jun 29 04:34:01 PM PDT 24
Finished Jun 29 04:34:59 PM PDT 24
Peak memory 216400 kb
Host smart-8c7a8147-1fe7-4226-b1d8-63cc3f8ed559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475493065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3475493065
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1311407689
Short name T191
Test name
Test status
Simulation time 25893380742 ps
CPU time 57.8 seconds
Started Jun 29 04:34:00 PM PDT 24
Finished Jun 29 04:34:58 PM PDT 24
Peak memory 216788 kb
Host smart-e5e87ec8-9ec5-4a19-adac-7a47ad5e8a47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311407689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1311407689
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2197018151
Short name T67
Test name
Test status
Simulation time 485173555 ps
CPU time 11.17 seconds
Started Jun 29 04:34:57 PM PDT 24
Finished Jun 29 04:35:09 PM PDT 24
Peak memory 217076 kb
Host smart-9620b737-bda1-471d-b012-b40646b92d94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197018151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2197018151
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1713146880
Short name T326
Test name
Test status
Simulation time 17926256181 ps
CPU time 162.27 seconds
Started Jun 29 04:34:51 PM PDT 24
Finished Jun 29 04:37:34 PM PDT 24
Peak memory 230692 kb
Host smart-9987af66-60c7-414a-a078-9e515f6f5551
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713146880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1713146880
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2577472793
Short name T140
Test name
Test status
Simulation time 30127977592 ps
CPU time 61.46 seconds
Started Jun 29 04:34:53 PM PDT 24
Finished Jun 29 04:35:55 PM PDT 24
Peak memory 219112 kb
Host smart-3cc652aa-7796-4b81-a776-86d6e49ae2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577472793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2577472793
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.919376909
Short name T310
Test name
Test status
Simulation time 185732678 ps
CPU time 10.89 seconds
Started Jun 29 04:34:55 PM PDT 24
Finished Jun 29 04:35:06 PM PDT 24
Peak memory 219196 kb
Host smart-6601cf86-1a85-4554-908e-421085a408fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=919376909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.919376909
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2318349184
Short name T294
Test name
Test status
Simulation time 363244048 ps
CPU time 20.46 seconds
Started Jun 29 04:34:51 PM PDT 24
Finished Jun 29 04:35:12 PM PDT 24
Peak memory 216788 kb
Host smart-17b7905c-91af-48a0-b37a-539ca5ee0b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318349184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2318349184
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2692958059
Short name T206
Test name
Test status
Simulation time 56535067421 ps
CPU time 134.12 seconds
Started Jun 29 04:34:50 PM PDT 24
Finished Jun 29 04:37:05 PM PDT 24
Peak memory 219276 kb
Host smart-7d5617cf-e716-42b5-990a-2ac525eb0165
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692958059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2692958059
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.616456025
Short name T16
Test name
Test status
Simulation time 249535418287 ps
CPU time 2255.71 seconds
Started Jun 29 04:34:52 PM PDT 24
Finished Jun 29 05:12:29 PM PDT 24
Peak memory 250756 kb
Host smart-620110ec-5846-405b-85c2-296f19d73494
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616456025 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.616456025
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2626479648
Short name T323
Test name
Test status
Simulation time 7158374686 ps
CPU time 22.45 seconds
Started Jun 29 04:35:02 PM PDT 24
Finished Jun 29 04:35:25 PM PDT 24
Peak memory 217456 kb
Host smart-1222fdcd-9538-4fb8-9961-d22ba297ff8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626479648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2626479648
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.689079970
Short name T255
Test name
Test status
Simulation time 240650988988 ps
CPU time 771.64 seconds
Started Jun 29 04:35:01 PM PDT 24
Finished Jun 29 04:47:53 PM PDT 24
Peak memory 243044 kb
Host smart-57b5c1ed-c300-422c-a2ca-0b82b9bba0a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689079970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.689079970
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3593559386
Short name T229
Test name
Test status
Simulation time 42738501796 ps
CPU time 44.8 seconds
Started Jun 29 04:35:01 PM PDT 24
Finished Jun 29 04:35:47 PM PDT 24
Peak memory 219184 kb
Host smart-76e07ad2-d152-4ff7-816b-dd9a1ce3858f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593559386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3593559386
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3996864985
Short name T359
Test name
Test status
Simulation time 4348858817 ps
CPU time 34.97 seconds
Started Jun 29 04:35:02 PM PDT 24
Finished Jun 29 04:35:38 PM PDT 24
Peak memory 219244 kb
Host smart-a9eb517a-7163-41c6-ab11-ceaec478c0d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3996864985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3996864985
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1928473326
Short name T316
Test name
Test status
Simulation time 1692404879 ps
CPU time 19.38 seconds
Started Jun 29 04:35:02 PM PDT 24
Finished Jun 29 04:35:22 PM PDT 24
Peak memory 216356 kb
Host smart-4229b149-77c7-4c53-b764-824e4f68f1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928473326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1928473326
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2973249836
Short name T163
Test name
Test status
Simulation time 3434935665 ps
CPU time 37.24 seconds
Started Jun 29 04:35:05 PM PDT 24
Finished Jun 29 04:35:43 PM PDT 24
Peak memory 218708 kb
Host smart-0a38b4f4-d2ed-4012-85bf-c1ae8954048f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973249836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2973249836
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1918799510
Short name T26
Test name
Test status
Simulation time 170659367 ps
CPU time 8.63 seconds
Started Jun 29 04:35:02 PM PDT 24
Finished Jun 29 04:35:12 PM PDT 24
Peak memory 218112 kb
Host smart-fc34e69a-2ad8-4e7b-8a5c-17b660545745
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918799510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1918799510
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2374750505
Short name T134
Test name
Test status
Simulation time 11646449411 ps
CPU time 53.79 seconds
Started Jun 29 04:35:00 PM PDT 24
Finished Jun 29 04:35:55 PM PDT 24
Peak memory 219196 kb
Host smart-e18761f3-d230-49a8-ae43-75848c374670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374750505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2374750505
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2958329276
Short name T291
Test name
Test status
Simulation time 16379293794 ps
CPU time 33.83 seconds
Started Jun 29 04:35:01 PM PDT 24
Finished Jun 29 04:35:36 PM PDT 24
Peak memory 211768 kb
Host smart-8a9fd95d-3a3d-4c89-8928-340ebaffbcc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2958329276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2958329276
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1094156916
Short name T281
Test name
Test status
Simulation time 1704472102 ps
CPU time 20.34 seconds
Started Jun 29 04:35:01 PM PDT 24
Finished Jun 29 04:35:23 PM PDT 24
Peak memory 216076 kb
Host smart-fce9b0f6-1439-451e-8df2-809e9cb875e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094156916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1094156916
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.4187893497
Short name T157
Test name
Test status
Simulation time 46705963433 ps
CPU time 113.81 seconds
Started Jun 29 04:35:04 PM PDT 24
Finished Jun 29 04:36:58 PM PDT 24
Peak memory 220928 kb
Host smart-f239e924-3ffe-4930-8a75-1c5f19ebacd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187893497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.4187893497
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3431775121
Short name T337
Test name
Test status
Simulation time 26347177374 ps
CPU time 31.67 seconds
Started Jun 29 04:35:02 PM PDT 24
Finished Jun 29 04:35:34 PM PDT 24
Peak memory 217484 kb
Host smart-c7934335-e88c-4540-871d-851c6bbe2d4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431775121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3431775121
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2043258103
Short name T4
Test name
Test status
Simulation time 8714334708 ps
CPU time 180.81 seconds
Started Jun 29 04:35:03 PM PDT 24
Finished Jun 29 04:38:05 PM PDT 24
Peak memory 241948 kb
Host smart-8536c960-642e-4719-8792-e31acee501e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043258103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2043258103
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2245760274
Short name T226
Test name
Test status
Simulation time 2061025040 ps
CPU time 33.32 seconds
Started Jun 29 04:35:02 PM PDT 24
Finished Jun 29 04:35:37 PM PDT 24
Peak memory 219200 kb
Host smart-2a172e16-6e07-467b-a4aa-838c7543cec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245760274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2245760274
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3694604585
Short name T271
Test name
Test status
Simulation time 3643948540 ps
CPU time 28.69 seconds
Started Jun 29 04:35:03 PM PDT 24
Finished Jun 29 04:35:32 PM PDT 24
Peak memory 219348 kb
Host smart-ab8ea81f-7215-48fe-a4cd-c4faee8ca211
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3694604585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3694604585
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.788260442
Short name T51
Test name
Test status
Simulation time 984557408 ps
CPU time 20.76 seconds
Started Jun 29 04:35:03 PM PDT 24
Finished Jun 29 04:35:25 PM PDT 24
Peak memory 216620 kb
Host smart-5e086121-e70b-4661-a471-63c5d2243083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788260442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.788260442
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.859756448
Short name T256
Test name
Test status
Simulation time 7698965152 ps
CPU time 76.07 seconds
Started Jun 29 04:35:03 PM PDT 24
Finished Jun 29 04:36:20 PM PDT 24
Peak memory 219276 kb
Host smart-23dd4828-e52b-4e99-83ae-034d1c724332
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859756448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.859756448
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3975212170
Short name T7
Test name
Test status
Simulation time 673628307 ps
CPU time 13.27 seconds
Started Jun 29 04:35:05 PM PDT 24
Finished Jun 29 04:35:19 PM PDT 24
Peak memory 216848 kb
Host smart-fa0da8e2-18e5-4bef-9d71-ee6917159e30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975212170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3975212170
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1981447648
Short name T318
Test name
Test status
Simulation time 47899715861 ps
CPU time 514.09 seconds
Started Jun 29 04:35:03 PM PDT 24
Finished Jun 29 04:43:38 PM PDT 24
Peak memory 234708 kb
Host smart-faab3758-5114-4474-aac3-a56e8b55a0bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981447648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1981447648
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1330572771
Short name T342
Test name
Test status
Simulation time 2235955054 ps
CPU time 33.29 seconds
Started Jun 29 04:35:04 PM PDT 24
Finished Jun 29 04:35:38 PM PDT 24
Peak memory 219228 kb
Host smart-8c1cc272-ed8d-47a5-a96b-e0e6ddadf41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330572771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1330572771
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2698636276
Short name T104
Test name
Test status
Simulation time 30525949425 ps
CPU time 28.08 seconds
Started Jun 29 04:35:02 PM PDT 24
Finished Jun 29 04:35:31 PM PDT 24
Peak memory 219268 kb
Host smart-c7ad1b23-29ff-4b41-a370-8c08457023cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2698636276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2698636276
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.878404837
Short name T301
Test name
Test status
Simulation time 28041297466 ps
CPU time 65.99 seconds
Started Jun 29 04:35:02 PM PDT 24
Finished Jun 29 04:36:09 PM PDT 24
Peak memory 217060 kb
Host smart-5fcddb01-dbff-470d-acfb-adfcbbc53f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878404837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.878404837
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.166287149
Short name T308
Test name
Test status
Simulation time 8558234776 ps
CPU time 111.69 seconds
Started Jun 29 04:35:01 PM PDT 24
Finished Jun 29 04:36:54 PM PDT 24
Peak memory 227484 kb
Host smart-21731975-e9c3-4152-b199-cbff5fd77718
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166287149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.166287149
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.354762351
Short name T249
Test name
Test status
Simulation time 1051604757 ps
CPU time 11.68 seconds
Started Jun 29 04:35:05 PM PDT 24
Finished Jun 29 04:35:17 PM PDT 24
Peak memory 217188 kb
Host smart-0d14857c-81ff-4343-a7f4-be1c3b48378a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354762351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.354762351
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2097825769
Short name T161
Test name
Test status
Simulation time 750194764196 ps
CPU time 574.99 seconds
Started Jun 29 04:35:02 PM PDT 24
Finished Jun 29 04:44:38 PM PDT 24
Peak memory 234060 kb
Host smart-66aaff7f-8908-4349-be06-11720e3ecb19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097825769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2097825769
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3966672015
Short name T144
Test name
Test status
Simulation time 5447886557 ps
CPU time 28.28 seconds
Started Jun 29 04:35:02 PM PDT 24
Finished Jun 29 04:35:31 PM PDT 24
Peak memory 218776 kb
Host smart-0129c4bc-d000-4970-b0a5-3f3b4d04563b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966672015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3966672015
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.69402266
Short name T351
Test name
Test status
Simulation time 3443776131 ps
CPU time 29.43 seconds
Started Jun 29 04:35:00 PM PDT 24
Finished Jun 29 04:35:30 PM PDT 24
Peak memory 219236 kb
Host smart-fd752c6e-c358-47c3-9986-12020c627769
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=69402266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.69402266
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.3823798621
Short name T78
Test name
Test status
Simulation time 16750648824 ps
CPU time 77.67 seconds
Started Jun 29 04:35:05 PM PDT 24
Finished Jun 29 04:36:23 PM PDT 24
Peak memory 217368 kb
Host smart-c0673200-70eb-4947-8c16-5005c155ce06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823798621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.3823798621
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3073610378
Short name T171
Test name
Test status
Simulation time 25803715962 ps
CPU time 67.95 seconds
Started Jun 29 04:35:03 PM PDT 24
Finished Jun 29 04:36:11 PM PDT 24
Peak memory 218404 kb
Host smart-4b5b04a2-4bbb-4dbc-b491-bf3d58cc51ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073610378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3073610378
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1214102339
Short name T66
Test name
Test status
Simulation time 882154140 ps
CPU time 13.95 seconds
Started Jun 29 04:35:04 PM PDT 24
Finished Jun 29 04:35:19 PM PDT 24
Peak memory 217160 kb
Host smart-cc7c8e23-da1a-4689-b74b-a3a80ec54145
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214102339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1214102339
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.186089211
Short name T233
Test name
Test status
Simulation time 69294554774 ps
CPU time 640.68 seconds
Started Jun 29 04:35:02 PM PDT 24
Finished Jun 29 04:45:44 PM PDT 24
Peak memory 234880 kb
Host smart-f9468b9b-aad0-4cce-84fe-8e7914b52cc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186089211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.186089211
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3700826537
Short name T145
Test name
Test status
Simulation time 10705219469 ps
CPU time 50.97 seconds
Started Jun 29 04:35:01 PM PDT 24
Finished Jun 29 04:35:53 PM PDT 24
Peak memory 219316 kb
Host smart-15a433d8-5315-49a3-8466-3e90575abd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700826537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3700826537
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.9622156
Short name T252
Test name
Test status
Simulation time 11617683728 ps
CPU time 24.71 seconds
Started Jun 29 04:35:04 PM PDT 24
Finished Jun 29 04:35:29 PM PDT 24
Peak memory 217596 kb
Host smart-825a4208-54c9-47a0-acdf-86f3fc057b84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=9622156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.9622156
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3319841954
Short name T121
Test name
Test status
Simulation time 6738303567 ps
CPU time 56.27 seconds
Started Jun 29 04:35:02 PM PDT 24
Finished Jun 29 04:35:59 PM PDT 24
Peak memory 216648 kb
Host smart-d8105b50-2a2f-4d75-8a72-2592e341e4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319841954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3319841954
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1359458091
Short name T182
Test name
Test status
Simulation time 60779420380 ps
CPU time 137.73 seconds
Started Jun 29 04:35:02 PM PDT 24
Finished Jun 29 04:37:21 PM PDT 24
Peak memory 220224 kb
Host smart-7db7af2d-2bcc-4135-88e2-c4d130636ac4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359458091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1359458091
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3199629386
Short name T242
Test name
Test status
Simulation time 1375597691 ps
CPU time 8.56 seconds
Started Jun 29 04:35:11 PM PDT 24
Finished Jun 29 04:35:20 PM PDT 24
Peak memory 217196 kb
Host smart-dec96fa8-dbbd-4df1-aafd-39d5fb4d91a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199629386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3199629386
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1404833350
Short name T325
Test name
Test status
Simulation time 4476723625 ps
CPU time 175.48 seconds
Started Jun 29 04:35:09 PM PDT 24
Finished Jun 29 04:38:05 PM PDT 24
Peak memory 225772 kb
Host smart-7b00722a-e748-4d4e-a3e6-3decdca330d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404833350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1404833350
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1493724795
Short name T356
Test name
Test status
Simulation time 5039334738 ps
CPU time 47.15 seconds
Started Jun 29 04:35:13 PM PDT 24
Finished Jun 29 04:36:01 PM PDT 24
Peak memory 219316 kb
Host smart-8dd411e5-4692-4b30-83bb-e566ae6fc970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493724795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1493724795
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2077766058
Short name T222
Test name
Test status
Simulation time 1051060425 ps
CPU time 12.76 seconds
Started Jun 29 04:35:12 PM PDT 24
Finished Jun 29 04:35:26 PM PDT 24
Peak memory 218492 kb
Host smart-0adefa33-6b1a-47ed-9d75-c786d6f19db2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2077766058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2077766058
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2193507811
Short name T213
Test name
Test status
Simulation time 7909161292 ps
CPU time 54.5 seconds
Started Jun 29 04:35:04 PM PDT 24
Finished Jun 29 04:35:59 PM PDT 24
Peak memory 217780 kb
Host smart-16dfd471-0600-49f8-8015-ccba59b8914c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193507811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2193507811
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3869548307
Short name T327
Test name
Test status
Simulation time 203225358 ps
CPU time 15.07 seconds
Started Jun 29 04:35:03 PM PDT 24
Finished Jun 29 04:35:19 PM PDT 24
Peak memory 219220 kb
Host smart-e883bd47-609b-4e74-ba30-0c7eaf7cc994
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869548307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3869548307
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.55376473
Short name T46
Test name
Test status
Simulation time 25824564590 ps
CPU time 1004.02 seconds
Started Jun 29 04:35:12 PM PDT 24
Finished Jun 29 04:51:57 PM PDT 24
Peak memory 235688 kb
Host smart-69906ec1-6fd7-4973-9445-3496aac6f453
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55376473 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.55376473
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.43138817
Short name T346
Test name
Test status
Simulation time 5826431099 ps
CPU time 16.96 seconds
Started Jun 29 04:35:11 PM PDT 24
Finished Jun 29 04:35:29 PM PDT 24
Peak memory 217496 kb
Host smart-0139de98-6d63-4d29-b43f-e7b52dfa4c7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43138817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.43138817
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1881246370
Short name T296
Test name
Test status
Simulation time 396045103453 ps
CPU time 710.07 seconds
Started Jun 29 04:35:08 PM PDT 24
Finished Jun 29 04:46:59 PM PDT 24
Peak memory 227628 kb
Host smart-b7d15fbb-fefe-4314-be8d-d6ea67f32328
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881246370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1881246370
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1229658257
Short name T156
Test name
Test status
Simulation time 2015800396 ps
CPU time 31.05 seconds
Started Jun 29 04:35:12 PM PDT 24
Finished Jun 29 04:35:44 PM PDT 24
Peak memory 218716 kb
Host smart-9ff1d817-0317-424a-a804-524a6c98f5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229658257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1229658257
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.998524140
Short name T183
Test name
Test status
Simulation time 1285823596 ps
CPU time 17.94 seconds
Started Jun 29 04:35:10 PM PDT 24
Finished Jun 29 04:35:29 PM PDT 24
Peak memory 219284 kb
Host smart-3fed4f57-1d57-4950-8724-b4c9b857c10d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=998524140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.998524140
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.517378782
Short name T240
Test name
Test status
Simulation time 8578456606 ps
CPU time 44.09 seconds
Started Jun 29 04:35:14 PM PDT 24
Finished Jun 29 04:35:59 PM PDT 24
Peak memory 217064 kb
Host smart-93e4ccd0-32be-431f-acb5-c30b8b315822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517378782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.517378782
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3834655996
Short name T136
Test name
Test status
Simulation time 3413737632 ps
CPU time 59.65 seconds
Started Jun 29 04:35:10 PM PDT 24
Finished Jun 29 04:36:11 PM PDT 24
Peak memory 216856 kb
Host smart-426bf7bc-011b-430f-a962-79f0076acf0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834655996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3834655996
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2808863641
Short name T320
Test name
Test status
Simulation time 4240336185 ps
CPU time 21.86 seconds
Started Jun 29 04:35:10 PM PDT 24
Finished Jun 29 04:35:32 PM PDT 24
Peak memory 217188 kb
Host smart-c7be0dcd-d480-4af7-a7ee-f93476dc153b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808863641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2808863641
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3400619478
Short name T234
Test name
Test status
Simulation time 38349074405 ps
CPU time 438.85 seconds
Started Jun 29 04:35:10 PM PDT 24
Finished Jun 29 04:42:30 PM PDT 24
Peak memory 239472 kb
Host smart-8ee97d40-55d9-4e4f-b3a5-dbf4ceb438c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400619478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3400619478
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.504175303
Short name T198
Test name
Test status
Simulation time 5296097016 ps
CPU time 52.62 seconds
Started Jun 29 04:35:13 PM PDT 24
Finished Jun 29 04:36:06 PM PDT 24
Peak memory 219284 kb
Host smart-69ac6658-b896-4f04-8153-06214e9dfd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504175303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.504175303
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3913091093
Short name T14
Test name
Test status
Simulation time 3162310116 ps
CPU time 26.27 seconds
Started Jun 29 04:35:15 PM PDT 24
Finished Jun 29 04:35:42 PM PDT 24
Peak memory 219036 kb
Host smart-4c5d8af6-e680-450e-9c86-bcb56ab967fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3913091093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3913091093
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3712134430
Short name T77
Test name
Test status
Simulation time 717769254 ps
CPU time 20.72 seconds
Started Jun 29 04:35:11 PM PDT 24
Finished Jun 29 04:35:33 PM PDT 24
Peak memory 216268 kb
Host smart-b191da1b-9cf7-4228-becd-db2d153dfced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712134430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3712134430
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.666103791
Short name T181
Test name
Test status
Simulation time 16807932979 ps
CPU time 65.98 seconds
Started Jun 29 04:35:12 PM PDT 24
Finished Jun 29 04:36:19 PM PDT 24
Peak memory 218636 kb
Host smart-8c873af5-a758-4f0f-ae21-62599d3a1033
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666103791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.666103791
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.4008124285
Short name T215
Test name
Test status
Simulation time 3603157189 ps
CPU time 30.25 seconds
Started Jun 29 04:34:03 PM PDT 24
Finished Jun 29 04:34:34 PM PDT 24
Peak memory 213208 kb
Host smart-4c3819f0-14a9-4385-ba58-5b5a3f2c1d2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008124285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.4008124285
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.373092135
Short name T276
Test name
Test status
Simulation time 21443982257 ps
CPU time 63.54 seconds
Started Jun 29 04:34:05 PM PDT 24
Finished Jun 29 04:35:09 PM PDT 24
Peak memory 219172 kb
Host smart-e8c9b828-d418-4648-b9cb-747f11459b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373092135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.373092135
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3416719977
Short name T123
Test name
Test status
Simulation time 3763256325 ps
CPU time 30.59 seconds
Started Jun 29 04:34:07 PM PDT 24
Finished Jun 29 04:34:37 PM PDT 24
Peak memory 211332 kb
Host smart-3bf07c96-817a-4ce6-be7f-609c40f54fd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3416719977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3416719977
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.449726196
Short name T81
Test name
Test status
Simulation time 569775795 ps
CPU time 20.15 seconds
Started Jun 29 04:34:13 PM PDT 24
Finished Jun 29 04:34:34 PM PDT 24
Peak memory 216716 kb
Host smart-a44bb411-7bad-470b-a319-734cc2a0db74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449726196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.449726196
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3577307351
Short name T80
Test name
Test status
Simulation time 29828177361 ps
CPU time 121.99 seconds
Started Jun 29 04:34:01 PM PDT 24
Finished Jun 29 04:36:04 PM PDT 24
Peak memory 221780 kb
Host smart-b5de989f-ffd6-4d28-b7d1-7bf3eb9cd16c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577307351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3577307351
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3405589858
Short name T330
Test name
Test status
Simulation time 2933711558 ps
CPU time 24.72 seconds
Started Jun 29 04:34:09 PM PDT 24
Finished Jun 29 04:34:34 PM PDT 24
Peak memory 217092 kb
Host smart-13828827-ae11-4a46-9668-7cfdc8f3dff6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405589858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3405589858
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2991863255
Short name T194
Test name
Test status
Simulation time 12588016505 ps
CPU time 289.5 seconds
Started Jun 29 04:34:04 PM PDT 24
Finished Jun 29 04:38:54 PM PDT 24
Peak memory 237980 kb
Host smart-a40a4734-9758-444a-a5b5-fa89d034a9ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991863255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2991863255
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3865017988
Short name T53
Test name
Test status
Simulation time 5726235910 ps
CPU time 54.56 seconds
Started Jun 29 04:34:08 PM PDT 24
Finished Jun 29 04:35:02 PM PDT 24
Peak memory 219212 kb
Host smart-9d7d2a76-ab06-4193-93f2-3d0f0ef756fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865017988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3865017988
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2095037175
Short name T282
Test name
Test status
Simulation time 1726553059 ps
CPU time 10.02 seconds
Started Jun 29 04:34:01 PM PDT 24
Finished Jun 29 04:34:11 PM PDT 24
Peak memory 219204 kb
Host smart-62681448-6295-4bef-b5b3-bda4e3281995
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2095037175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2095037175
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1378439304
Short name T295
Test name
Test status
Simulation time 720159490 ps
CPU time 20.24 seconds
Started Jun 29 04:34:12 PM PDT 24
Finished Jun 29 04:34:33 PM PDT 24
Peak memory 216176 kb
Host smart-000ea143-f3e8-46e7-953e-e833e6674e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378439304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1378439304
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2928266089
Short name T132
Test name
Test status
Simulation time 1540181354 ps
CPU time 25.71 seconds
Started Jun 29 04:34:02 PM PDT 24
Finished Jun 29 04:34:28 PM PDT 24
Peak memory 219184 kb
Host smart-722c00e2-dc6e-4dc8-a90e-4df0617dec88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928266089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2928266089
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2517516895
Short name T341
Test name
Test status
Simulation time 17758922568 ps
CPU time 28.11 seconds
Started Jun 29 04:34:15 PM PDT 24
Finished Jun 29 04:34:43 PM PDT 24
Peak memory 213156 kb
Host smart-62092196-59fc-41e2-ba75-7cb9c1c86729
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517516895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2517516895
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2065672429
Short name T268
Test name
Test status
Simulation time 132285181817 ps
CPU time 697.74 seconds
Started Jun 29 04:34:11 PM PDT 24
Finished Jun 29 04:45:49 PM PDT 24
Peak memory 237048 kb
Host smart-af8f37b8-5471-40df-88f2-77a07837de3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065672429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2065672429
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3629982276
Short name T40
Test name
Test status
Simulation time 675619022 ps
CPU time 18.9 seconds
Started Jun 29 04:34:07 PM PDT 24
Finished Jun 29 04:34:27 PM PDT 24
Peak memory 219212 kb
Host smart-51e253b4-2381-4c46-b890-884b09747450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629982276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3629982276
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1343899493
Short name T152
Test name
Test status
Simulation time 440962081 ps
CPU time 13.44 seconds
Started Jun 29 04:34:12 PM PDT 24
Finished Jun 29 04:34:26 PM PDT 24
Peak memory 218712 kb
Host smart-e130b4da-e9f4-46fd-a08f-2f04fb51eb39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1343899493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1343899493
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3412752697
Short name T184
Test name
Test status
Simulation time 720299204 ps
CPU time 20.61 seconds
Started Jun 29 04:34:11 PM PDT 24
Finished Jun 29 04:34:32 PM PDT 24
Peak memory 216300 kb
Host smart-1be91d20-3bdd-45a7-8138-159ec1e4e2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412752697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3412752697
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1815019051
Short name T307
Test name
Test status
Simulation time 131386926848 ps
CPU time 140.92 seconds
Started Jun 29 04:34:15 PM PDT 24
Finished Jun 29 04:36:37 PM PDT 24
Peak memory 219248 kb
Host smart-c912684f-6e9e-4760-b3de-c75ef1697036
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815019051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1815019051
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3821992014
Short name T18
Test name
Test status
Simulation time 74295586071 ps
CPU time 2631.45 seconds
Started Jun 29 04:34:10 PM PDT 24
Finished Jun 29 05:18:02 PM PDT 24
Peak memory 252060 kb
Host smart-fc56a742-d216-4c01-aeec-a9f4409d2fb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821992014 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.3821992014
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3687462387
Short name T203
Test name
Test status
Simulation time 466591220 ps
CPU time 11.25 seconds
Started Jun 29 04:34:12 PM PDT 24
Finished Jun 29 04:34:24 PM PDT 24
Peak memory 217136 kb
Host smart-b2871dc0-6f66-46c8-87d2-a5a2e0934378
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687462387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3687462387
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2984317661
Short name T345
Test name
Test status
Simulation time 171221170747 ps
CPU time 850.32 seconds
Started Jun 29 04:34:08 PM PDT 24
Finished Jun 29 04:48:19 PM PDT 24
Peak memory 236348 kb
Host smart-97075ec7-5813-4f34-9542-d55deb9c3a0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984317661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2984317661
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1910911233
Short name T135
Test name
Test status
Simulation time 15674402729 ps
CPU time 43.5 seconds
Started Jun 29 04:34:13 PM PDT 24
Finished Jun 29 04:34:57 PM PDT 24
Peak memory 219112 kb
Host smart-72becd3f-e96f-4f7f-b5f3-bcefe3f3c6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910911233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1910911233
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.963454877
Short name T175
Test name
Test status
Simulation time 666962050 ps
CPU time 10.69 seconds
Started Jun 29 04:34:10 PM PDT 24
Finished Jun 29 04:34:21 PM PDT 24
Peak memory 219176 kb
Host smart-3f3a4695-9bb1-4039-8698-9b90eb884e34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=963454877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.963454877
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.586748749
Short name T238
Test name
Test status
Simulation time 79023877097 ps
CPU time 48.59 seconds
Started Jun 29 04:34:04 PM PDT 24
Finished Jun 29 04:34:53 PM PDT 24
Peak memory 215984 kb
Host smart-04a1f6f9-bc09-4850-8c04-fd07d23480c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586748749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.586748749
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3104592569
Short name T22
Test name
Test status
Simulation time 4440257852 ps
CPU time 36.6 seconds
Started Jun 29 04:34:02 PM PDT 24
Finished Jun 29 04:34:39 PM PDT 24
Peak memory 219276 kb
Host smart-6d6b2f1b-4dae-44a3-a2a1-2618ae1a46fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104592569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3104592569
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3263791444
Short name T158
Test name
Test status
Simulation time 2351884920 ps
CPU time 16.03 seconds
Started Jun 29 04:34:11 PM PDT 24
Finished Jun 29 04:34:27 PM PDT 24
Peak memory 217060 kb
Host smart-c9e85212-ef1e-4278-a3f8-24f4c91d0cef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263791444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3263791444
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3429197594
Short name T267
Test name
Test status
Simulation time 51901149280 ps
CPU time 510.85 seconds
Started Jun 29 04:34:02 PM PDT 24
Finished Jun 29 04:42:34 PM PDT 24
Peak memory 218888 kb
Host smart-efd069a5-68e1-4f33-a932-55875b509655
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429197594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3429197594
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1567812934
Short name T241
Test name
Test status
Simulation time 1269737970 ps
CPU time 19.81 seconds
Started Jun 29 04:34:10 PM PDT 24
Finished Jun 29 04:34:30 PM PDT 24
Peak memory 219212 kb
Host smart-1959fcf2-2650-477e-b1cf-94a8c607fbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567812934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1567812934
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3134125125
Short name T126
Test name
Test status
Simulation time 695547862 ps
CPU time 10.82 seconds
Started Jun 29 04:34:10 PM PDT 24
Finished Jun 29 04:34:21 PM PDT 24
Peak memory 219176 kb
Host smart-68237e9b-f000-41d0-ae39-a060cf57b694
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3134125125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3134125125
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3222980575
Short name T264
Test name
Test status
Simulation time 366067837 ps
CPU time 20.57 seconds
Started Jun 29 04:34:10 PM PDT 24
Finished Jun 29 04:34:31 PM PDT 24
Peak memory 215916 kb
Host smart-e77d4723-8e0f-4502-b66d-afe2e515ba6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222980575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3222980575
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.379785463
Short name T277
Test name
Test status
Simulation time 24267314725 ps
CPU time 98.26 seconds
Started Jun 29 04:34:09 PM PDT 24
Finished Jun 29 04:35:48 PM PDT 24
Peak memory 219248 kb
Host smart-cf60178a-dd65-4320-bd48-3ef91d81c4c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379785463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.379785463
Directory /workspace/9.rom_ctrl_stress_all/latest
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