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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.21 96.89 91.99 97.68 100.00 98.28 97.30 98.37


Total test records in report: 457
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T301 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1010319013 Jun 30 04:47:08 PM PDT 24 Jun 30 04:51:12 PM PDT 24 21375439083 ps
T302 /workspace/coverage/default/16.rom_ctrl_stress_all.2568878258 Jun 30 04:47:09 PM PDT 24 Jun 30 04:47:53 PM PDT 24 1351528161 ps
T303 /workspace/coverage/default/46.rom_ctrl_smoke.498234200 Jun 30 04:48:27 PM PDT 24 Jun 30 04:49:39 PM PDT 24 27565943823 ps
T304 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1319164401 Jun 30 04:48:26 PM PDT 24 Jun 30 04:48:54 PM PDT 24 3032908241 ps
T305 /workspace/coverage/default/47.rom_ctrl_smoke.3659491854 Jun 30 04:48:27 PM PDT 24 Jun 30 04:49:30 PM PDT 24 6307786808 ps
T306 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1087248253 Jun 30 04:47:47 PM PDT 24 Jun 30 04:48:55 PM PDT 24 28567979109 ps
T307 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.177928803 Jun 30 04:46:41 PM PDT 24 Jun 30 04:47:27 PM PDT 24 16356203614 ps
T308 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.535433253 Jun 30 04:47:09 PM PDT 24 Jun 30 04:47:20 PM PDT 24 720491500 ps
T309 /workspace/coverage/default/29.rom_ctrl_alert_test.3699668453 Jun 30 04:47:45 PM PDT 24 Jun 30 04:48:14 PM PDT 24 13504872115 ps
T23 /workspace/coverage/default/0.rom_ctrl_sec_cm.4192135822 Jun 30 04:46:36 PM PDT 24 Jun 30 04:48:54 PM PDT 24 7893957605 ps
T310 /workspace/coverage/default/27.rom_ctrl_stress_all.687641967 Jun 30 04:47:46 PM PDT 24 Jun 30 04:48:17 PM PDT 24 6033738023 ps
T311 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3301674031 Jun 30 04:47:09 PM PDT 24 Jun 30 04:47:31 PM PDT 24 518333862 ps
T312 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.714139323 Jun 30 04:48:06 PM PDT 24 Jun 30 04:59:59 PM PDT 24 287289225522 ps
T28 /workspace/coverage/default/4.rom_ctrl_sec_cm.806137853 Jun 30 04:46:44 PM PDT 24 Jun 30 04:50:35 PM PDT 24 4988801304 ps
T313 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.106888562 Jun 30 04:47:29 PM PDT 24 Jun 30 04:55:00 PM PDT 24 261938276378 ps
T314 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.203533229 Jun 30 04:48:12 PM PDT 24 Jun 30 04:52:49 PM PDT 24 84235197256 ps
T315 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.775704415 Jun 30 04:48:20 PM PDT 24 Jun 30 04:48:46 PM PDT 24 4540113407 ps
T316 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1458598376 Jun 30 04:48:13 PM PDT 24 Jun 30 04:49:22 PM PDT 24 16333820750 ps
T317 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2258133995 Jun 30 04:46:58 PM PDT 24 Jun 30 04:48:01 PM PDT 24 7523704963 ps
T318 /workspace/coverage/default/28.rom_ctrl_alert_test.810431738 Jun 30 04:47:46 PM PDT 24 Jun 30 04:48:02 PM PDT 24 1016281387 ps
T319 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.469408852 Jun 30 04:48:02 PM PDT 24 Jun 30 04:48:38 PM PDT 24 2544087375 ps
T320 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2773108955 Jun 30 04:48:07 PM PDT 24 Jun 30 04:48:37 PM PDT 24 14715495801 ps
T321 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2334802577 Jun 30 04:48:27 PM PDT 24 Jun 30 05:03:44 PM PDT 24 156091912909 ps
T322 /workspace/coverage/default/39.rom_ctrl_smoke.615548891 Jun 30 04:48:14 PM PDT 24 Jun 30 04:48:34 PM PDT 24 348916857 ps
T323 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3345746466 Jun 30 04:47:09 PM PDT 24 Jun 30 04:47:28 PM PDT 24 8929417574 ps
T324 /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.233720941 Jun 30 04:46:37 PM PDT 24 Jun 30 05:27:48 PM PDT 24 11082607734 ps
T325 /workspace/coverage/default/20.rom_ctrl_alert_test.1638982261 Jun 30 04:47:23 PM PDT 24 Jun 30 04:47:32 PM PDT 24 718509440 ps
T326 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.67937552 Jun 30 04:47:56 PM PDT 24 Jun 30 05:04:55 PM PDT 24 101007030233 ps
T327 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2936336483 Jun 30 04:46:36 PM PDT 24 Jun 30 04:47:22 PM PDT 24 4640181214 ps
T328 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2853063443 Jun 30 04:48:18 PM PDT 24 Jun 30 04:54:31 PM PDT 24 36950535369 ps
T329 /workspace/coverage/default/25.rom_ctrl_stress_all.308230413 Jun 30 04:47:38 PM PDT 24 Jun 30 04:47:56 PM PDT 24 1026844032 ps
T330 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3233070691 Jun 30 04:47:03 PM PDT 24 Jun 30 04:54:49 PM PDT 24 44825339421 ps
T331 /workspace/coverage/default/33.rom_ctrl_stress_all.2114467659 Jun 30 04:47:56 PM PDT 24 Jun 30 04:51:10 PM PDT 24 32886527742 ps
T332 /workspace/coverage/default/4.rom_ctrl_smoke.2215229739 Jun 30 04:46:41 PM PDT 24 Jun 30 04:47:49 PM PDT 24 8569666281 ps
T333 /workspace/coverage/default/13.rom_ctrl_smoke.3005943287 Jun 30 04:47:03 PM PDT 24 Jun 30 04:47:54 PM PDT 24 4278943223 ps
T334 /workspace/coverage/default/9.rom_ctrl_stress_all.1431776081 Jun 30 04:46:55 PM PDT 24 Jun 30 04:49:45 PM PDT 24 68258299075 ps
T335 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.4070788929 Jun 30 04:48:36 PM PDT 24 Jun 30 04:59:13 PM PDT 24 57510758298 ps
T336 /workspace/coverage/default/21.rom_ctrl_stress_all.3464492477 Jun 30 04:47:23 PM PDT 24 Jun 30 04:49:01 PM PDT 24 6347820942 ps
T337 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1711658662 Jun 30 04:48:21 PM PDT 24 Jun 30 04:49:00 PM PDT 24 2961817174 ps
T338 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1177198225 Jun 30 04:47:30 PM PDT 24 Jun 30 04:48:34 PM PDT 24 78758511362 ps
T339 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3809643217 Jun 30 04:47:31 PM PDT 24 Jun 30 04:54:51 PM PDT 24 241123756945 ps
T340 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1541742625 Jun 30 04:47:39 PM PDT 24 Jun 30 04:54:24 PM PDT 24 25579603364 ps
T341 /workspace/coverage/default/8.rom_ctrl_alert_test.2281023418 Jun 30 04:46:56 PM PDT 24 Jun 30 04:47:23 PM PDT 24 6301201099 ps
T342 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.4247013916 Jun 30 04:48:34 PM PDT 24 Jun 30 04:49:06 PM PDT 24 7841547242 ps
T343 /workspace/coverage/default/34.rom_ctrl_stress_all.3276054336 Jun 30 04:47:57 PM PDT 24 Jun 30 04:49:27 PM PDT 24 33658576899 ps
T344 /workspace/coverage/default/19.rom_ctrl_alert_test.2005961431 Jun 30 04:47:24 PM PDT 24 Jun 30 04:47:57 PM PDT 24 6316959261 ps
T345 /workspace/coverage/default/48.rom_ctrl_stress_all.3186823533 Jun 30 04:48:32 PM PDT 24 Jun 30 04:49:07 PM PDT 24 544356631 ps
T346 /workspace/coverage/default/5.rom_ctrl_smoke.1654252617 Jun 30 04:46:43 PM PDT 24 Jun 30 04:47:04 PM PDT 24 700586960 ps
T347 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3729744462 Jun 30 04:48:04 PM PDT 24 Jun 30 04:48:52 PM PDT 24 19028140596 ps
T348 /workspace/coverage/default/11.rom_ctrl_alert_test.2977762801 Jun 30 04:47:01 PM PDT 24 Jun 30 04:47:17 PM PDT 24 2054917872 ps
T349 /workspace/coverage/default/8.rom_ctrl_smoke.1760342724 Jun 30 04:46:55 PM PDT 24 Jun 30 04:47:15 PM PDT 24 1426941996 ps
T350 /workspace/coverage/default/10.rom_ctrl_alert_test.1574344089 Jun 30 04:46:56 PM PDT 24 Jun 30 04:47:05 PM PDT 24 688932068 ps
T351 /workspace/coverage/default/49.rom_ctrl_smoke.21913100 Jun 30 04:48:35 PM PDT 24 Jun 30 04:49:09 PM PDT 24 1677375693 ps
T352 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1984482443 Jun 30 04:48:07 PM PDT 24 Jun 30 04:48:18 PM PDT 24 371370840 ps
T353 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3092826095 Jun 30 04:47:57 PM PDT 24 Jun 30 04:48:08 PM PDT 24 1459529239 ps
T354 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1327410990 Jun 30 04:48:02 PM PDT 24 Jun 30 04:54:36 PM PDT 24 90543910050 ps
T355 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2858600536 Jun 30 04:48:12 PM PDT 24 Jun 30 04:55:36 PM PDT 24 35962407978 ps
T356 /workspace/coverage/default/49.rom_ctrl_alert_test.1732352899 Jun 30 04:48:34 PM PDT 24 Jun 30 04:48:44 PM PDT 24 339271235 ps
T357 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3566021990 Jun 30 04:48:32 PM PDT 24 Jun 30 04:48:46 PM PDT 24 2325364373 ps
T358 /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.604376681 Jun 30 04:47:46 PM PDT 24 Jun 30 07:09:49 PM PDT 24 31029391552 ps
T359 /workspace/coverage/default/36.rom_ctrl_alert_test.86774864 Jun 30 04:48:04 PM PDT 24 Jun 30 04:48:13 PM PDT 24 319838253 ps
T29 /workspace/coverage/default/2.rom_ctrl_sec_cm.2880307714 Jun 30 04:46:38 PM PDT 24 Jun 30 04:48:38 PM PDT 24 298969089 ps
T64 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.337001383 Jun 30 04:43:16 PM PDT 24 Jun 30 04:43:31 PM PDT 24 1507016709 ps
T65 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3918706552 Jun 30 04:43:20 PM PDT 24 Jun 30 04:43:58 PM PDT 24 9236993886 ps
T66 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2769637967 Jun 30 04:43:33 PM PDT 24 Jun 30 04:43:54 PM PDT 24 6515929979 ps
T95 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3518548019 Jun 30 04:43:15 PM PDT 24 Jun 30 04:43:41 PM PDT 24 9153378449 ps
T61 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2510306013 Jun 30 04:43:17 PM PDT 24 Jun 30 04:46:00 PM PDT 24 10735065864 ps
T62 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.648897175 Jun 30 04:43:31 PM PDT 24 Jun 30 04:46:28 PM PDT 24 3383496827 ps
T71 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.95158986 Jun 30 04:43:21 PM PDT 24 Jun 30 04:43:49 PM PDT 24 9102087878 ps
T360 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3002752108 Jun 30 04:43:23 PM PDT 24 Jun 30 04:43:52 PM PDT 24 10116800088 ps
T63 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2053125428 Jun 30 04:43:27 PM PDT 24 Jun 30 04:46:03 PM PDT 24 1334210818 ps
T96 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2349248842 Jun 30 04:43:14 PM PDT 24 Jun 30 04:43:39 PM PDT 24 2069311708 ps
T72 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3802509265 Jun 30 04:43:22 PM PDT 24 Jun 30 04:43:38 PM PDT 24 4658138038 ps
T361 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2610481166 Jun 30 04:43:21 PM PDT 24 Jun 30 04:43:46 PM PDT 24 8874685116 ps
T73 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3869910752 Jun 30 04:43:22 PM PDT 24 Jun 30 04:45:30 PM PDT 24 88052226491 ps
T362 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3716705008 Jun 30 04:43:17 PM PDT 24 Jun 30 04:43:49 PM PDT 24 55584345536 ps
T74 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1822791464 Jun 30 04:43:16 PM PDT 24 Jun 30 04:43:43 PM PDT 24 5830058293 ps
T75 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1409840946 Jun 30 04:43:21 PM PDT 24 Jun 30 04:43:44 PM PDT 24 2668154956 ps
T76 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2672917283 Jun 30 04:43:24 PM PDT 24 Jun 30 04:43:42 PM PDT 24 1373165474 ps
T363 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3928740189 Jun 30 04:43:24 PM PDT 24 Jun 30 04:43:59 PM PDT 24 16016026760 ps
T97 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2611536373 Jun 30 04:43:22 PM PDT 24 Jun 30 04:43:49 PM PDT 24 37721146926 ps
T109 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2504634855 Jun 30 04:43:15 PM PDT 24 Jun 30 04:44:53 PM PDT 24 50396477757 ps
T364 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2315168342 Jun 30 04:43:17 PM PDT 24 Jun 30 04:43:49 PM PDT 24 15439135151 ps
T98 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2874397643 Jun 30 04:43:10 PM PDT 24 Jun 30 04:43:32 PM PDT 24 12077110383 ps
T365 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4225570500 Jun 30 04:43:15 PM PDT 24 Jun 30 04:43:24 PM PDT 24 332068869 ps
T366 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.189948222 Jun 30 04:43:16 PM PDT 24 Jun 30 04:43:51 PM PDT 24 13151990025 ps
T367 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4127918247 Jun 30 04:43:14 PM PDT 24 Jun 30 04:43:46 PM PDT 24 14522922243 ps
T110 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1747168025 Jun 30 04:43:04 PM PDT 24 Jun 30 04:44:31 PM PDT 24 1214767103 ps
T368 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3362436097 Jun 30 04:43:22 PM PDT 24 Jun 30 04:43:37 PM PDT 24 857085292 ps
T77 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1878899344 Jun 30 04:43:21 PM PDT 24 Jun 30 04:44:56 PM PDT 24 74020735532 ps
T78 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2803998898 Jun 30 04:43:15 PM PDT 24 Jun 30 04:45:15 PM PDT 24 103512557116 ps
T113 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2710732831 Jun 30 04:43:24 PM PDT 24 Jun 30 04:44:46 PM PDT 24 461665016 ps
T369 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3667899617 Jun 30 04:43:24 PM PDT 24 Jun 30 04:43:49 PM PDT 24 2215232514 ps
T370 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2282233237 Jun 30 04:43:11 PM PDT 24 Jun 30 04:45:13 PM PDT 24 14035975488 ps
T371 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3805963339 Jun 30 04:43:15 PM PDT 24 Jun 30 04:43:53 PM PDT 24 17670475260 ps
T105 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1888724067 Jun 30 04:43:15 PM PDT 24 Jun 30 04:45:00 PM PDT 24 4213821541 ps
T372 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.658804562 Jun 30 04:43:21 PM PDT 24 Jun 30 04:43:36 PM PDT 24 770269134 ps
T373 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1290559287 Jun 30 04:43:16 PM PDT 24 Jun 30 04:43:28 PM PDT 24 487310573 ps
T374 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2240096304 Jun 30 04:43:16 PM PDT 24 Jun 30 04:43:51 PM PDT 24 4152733884 ps
T375 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3185883251 Jun 30 04:43:09 PM PDT 24 Jun 30 04:43:19 PM PDT 24 1128650400 ps
T376 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1535837408 Jun 30 04:43:30 PM PDT 24 Jun 30 04:43:55 PM PDT 24 11538801684 ps
T377 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1639782177 Jun 30 04:43:23 PM PDT 24 Jun 30 04:44:41 PM PDT 24 6537208510 ps
T378 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2825258813 Jun 30 04:43:32 PM PDT 24 Jun 30 04:45:06 PM PDT 24 2492529891 ps
T379 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.4220692723 Jun 30 04:43:33 PM PDT 24 Jun 30 04:44:06 PM PDT 24 3838460994 ps
T380 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3634557300 Jun 30 04:43:21 PM PDT 24 Jun 30 04:43:46 PM PDT 24 5215925401 ps
T381 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2367797729 Jun 30 04:43:14 PM PDT 24 Jun 30 04:43:22 PM PDT 24 174424016 ps
T382 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2268719529 Jun 30 04:43:32 PM PDT 24 Jun 30 04:43:53 PM PDT 24 4872334896 ps
T79 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3099200722 Jun 30 04:43:13 PM PDT 24 Jun 30 04:43:38 PM PDT 24 9946588201 ps
T383 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2927338562 Jun 30 04:43:22 PM PDT 24 Jun 30 04:43:36 PM PDT 24 837182847 ps
T384 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.530454186 Jun 30 04:43:17 PM PDT 24 Jun 30 04:43:42 PM PDT 24 10155344478 ps
T385 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.818293845 Jun 30 04:43:20 PM PDT 24 Jun 30 04:43:46 PM PDT 24 2749390121 ps
T386 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1279963557 Jun 30 04:43:13 PM PDT 24 Jun 30 04:44:38 PM PDT 24 822967269 ps
T387 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2373000200 Jun 30 04:43:23 PM PDT 24 Jun 30 04:44:03 PM PDT 24 29623719240 ps
T388 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2409708544 Jun 30 04:43:11 PM PDT 24 Jun 30 04:43:19 PM PDT 24 174587779 ps
T82 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2795005861 Jun 30 04:43:07 PM PDT 24 Jun 30 04:43:55 PM PDT 24 9602833343 ps
T389 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.622077641 Jun 30 04:43:22 PM PDT 24 Jun 30 04:43:56 PM PDT 24 33602561983 ps
T102 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2449043763 Jun 30 04:43:15 PM PDT 24 Jun 30 04:45:15 PM PDT 24 29285774781 ps
T83 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3475576830 Jun 30 04:43:15 PM PDT 24 Jun 30 04:45:28 PM PDT 24 64426406507 ps
T390 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3132535674 Jun 30 04:43:11 PM PDT 24 Jun 30 04:43:42 PM PDT 24 3287867592 ps
T84 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1433048598 Jun 30 04:43:15 PM PDT 24 Jun 30 04:44:13 PM PDT 24 1053514011 ps
T391 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2991197100 Jun 30 04:43:14 PM PDT 24 Jun 30 04:43:27 PM PDT 24 4132707851 ps
T85 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.93993847 Jun 30 04:43:23 PM PDT 24 Jun 30 04:43:47 PM PDT 24 9760945245 ps
T116 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3934885227 Jun 30 04:43:12 PM PDT 24 Jun 30 04:44:50 PM PDT 24 8906346215 ps
T86 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2803451109 Jun 30 04:43:16 PM PDT 24 Jun 30 04:43:33 PM PDT 24 581991277 ps
T87 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2037355846 Jun 30 04:43:21 PM PDT 24 Jun 30 04:43:30 PM PDT 24 216639865 ps
T392 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1605036778 Jun 30 04:43:11 PM PDT 24 Jun 30 04:43:40 PM PDT 24 6850754739 ps
T393 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.343401369 Jun 30 04:43:08 PM PDT 24 Jun 30 04:43:38 PM PDT 24 3936059410 ps
T394 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.712497217 Jun 30 04:43:16 PM PDT 24 Jun 30 04:43:32 PM PDT 24 1008113814 ps
T395 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3466186871 Jun 30 04:43:16 PM PDT 24 Jun 30 04:43:37 PM PDT 24 3925293968 ps
T103 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1985926904 Jun 30 04:43:18 PM PDT 24 Jun 30 04:44:39 PM PDT 24 966360706 ps
T396 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.154050428 Jun 30 04:43:23 PM PDT 24 Jun 30 04:43:46 PM PDT 24 8675931745 ps
T107 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.4204088159 Jun 30 04:43:14 PM PDT 24 Jun 30 04:45:57 PM PDT 24 3885715110 ps
T397 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.344468750 Jun 30 04:43:11 PM PDT 24 Jun 30 04:43:44 PM PDT 24 4257614986 ps
T398 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.4174193135 Jun 30 04:43:21 PM PDT 24 Jun 30 04:43:58 PM PDT 24 4135103759 ps
T399 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3779132680 Jun 30 04:43:23 PM PDT 24 Jun 30 04:43:44 PM PDT 24 1691837854 ps
T400 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.833855545 Jun 30 04:43:22 PM PDT 24 Jun 30 04:43:42 PM PDT 24 19586497394 ps
T401 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3907832068 Jun 30 04:43:07 PM PDT 24 Jun 30 04:43:32 PM PDT 24 2618628291 ps
T88 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4291546609 Jun 30 04:43:22 PM PDT 24 Jun 30 04:45:30 PM PDT 24 40498039922 ps
T402 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2162523360 Jun 30 04:43:14 PM PDT 24 Jun 30 04:43:32 PM PDT 24 1538591838 ps
T403 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2391108780 Jun 30 04:43:20 PM PDT 24 Jun 30 04:43:29 PM PDT 24 384772683 ps
T404 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2825471867 Jun 30 04:43:24 PM PDT 24 Jun 30 04:43:50 PM PDT 24 16392429078 ps
T405 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2498345583 Jun 30 04:43:17 PM PDT 24 Jun 30 04:43:30 PM PDT 24 353042408 ps
T106 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2242369465 Jun 30 04:43:23 PM PDT 24 Jun 30 04:45:03 PM PDT 24 2892122899 ps
T406 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2242865255 Jun 30 04:43:35 PM PDT 24 Jun 30 04:44:12 PM PDT 24 37940193886 ps
T407 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3387066254 Jun 30 04:43:16 PM PDT 24 Jun 30 04:43:30 PM PDT 24 1478368783 ps
T408 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2510016605 Jun 30 04:43:15 PM PDT 24 Jun 30 04:43:31 PM PDT 24 395001048 ps
T409 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2345375268 Jun 30 04:43:15 PM PDT 24 Jun 30 04:45:08 PM PDT 24 35930906465 ps
T111 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.358241122 Jun 30 04:43:04 PM PDT 24 Jun 30 04:44:21 PM PDT 24 1218612133 ps
T410 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2936377002 Jun 30 04:43:09 PM PDT 24 Jun 30 04:43:17 PM PDT 24 176439293 ps
T411 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4130647220 Jun 30 04:43:29 PM PDT 24 Jun 30 04:43:55 PM PDT 24 14675205258 ps
T412 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2901601855 Jun 30 04:43:22 PM PDT 24 Jun 30 04:43:42 PM PDT 24 3821154974 ps
T89 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2840287642 Jun 30 04:43:23 PM PDT 24 Jun 30 04:45:17 PM PDT 24 71931848759 ps
T413 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1250320605 Jun 30 04:43:16 PM PDT 24 Jun 30 04:43:47 PM PDT 24 45736992698 ps
T414 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.83619579 Jun 30 04:43:16 PM PDT 24 Jun 30 04:43:42 PM PDT 24 2634418978 ps
T415 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1524994292 Jun 30 04:43:24 PM PDT 24 Jun 30 04:43:47 PM PDT 24 1221902682 ps
T416 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1814193888 Jun 30 04:43:15 PM PDT 24 Jun 30 04:46:33 PM PDT 24 47288477438 ps
T417 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.887171555 Jun 30 04:43:13 PM PDT 24 Jun 30 04:44:54 PM PDT 24 13902775745 ps
T418 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.365351869 Jun 30 04:43:16 PM PDT 24 Jun 30 04:43:27 PM PDT 24 187651072 ps
T419 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2604891101 Jun 30 04:43:15 PM PDT 24 Jun 30 04:43:41 PM PDT 24 11250365512 ps
T93 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1754827963 Jun 30 04:43:10 PM PDT 24 Jun 30 04:44:08 PM PDT 24 4305371681 ps
T420 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1273403037 Jun 30 04:43:13 PM PDT 24 Jun 30 04:43:22 PM PDT 24 3297354461 ps
T421 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.503644609 Jun 30 04:43:29 PM PDT 24 Jun 30 04:43:52 PM PDT 24 8914904295 ps
T422 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3808466812 Jun 30 04:43:08 PM PDT 24 Jun 30 04:43:42 PM PDT 24 17026128492 ps
T90 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3118876120 Jun 30 04:43:15 PM PDT 24 Jun 30 04:43:38 PM PDT 24 8949656658 ps
T423 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2648675402 Jun 30 04:43:07 PM PDT 24 Jun 30 04:43:24 PM PDT 24 1267845012 ps
T424 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1383989448 Jun 30 04:43:03 PM PDT 24 Jun 30 04:43:16 PM PDT 24 1362920868 ps
T425 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3830937573 Jun 30 04:43:07 PM PDT 24 Jun 30 04:43:24 PM PDT 24 2767437259 ps
T108 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.156571807 Jun 30 04:43:30 PM PDT 24 Jun 30 04:44:53 PM PDT 24 1115936344 ps
T426 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.833055005 Jun 30 04:43:17 PM PDT 24 Jun 30 04:43:38 PM PDT 24 1889324698 ps
T427 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1835294607 Jun 30 04:43:24 PM PDT 24 Jun 30 04:43:54 PM PDT 24 2667581229 ps
T428 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1471103489 Jun 30 04:43:22 PM PDT 24 Jun 30 04:43:50 PM PDT 24 3488941947 ps
T429 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2808990964 Jun 30 04:43:16 PM PDT 24 Jun 30 04:43:47 PM PDT 24 11144736782 ps
T430 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3322121912 Jun 30 04:43:11 PM PDT 24 Jun 30 04:43:34 PM PDT 24 9772744421 ps
T431 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1700155795 Jun 30 04:43:16 PM PDT 24 Jun 30 04:43:33 PM PDT 24 5128751425 ps
T432 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3362158968 Jun 30 04:43:17 PM PDT 24 Jun 30 04:43:36 PM PDT 24 6438040887 ps
T433 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2999530784 Jun 30 04:43:13 PM PDT 24 Jun 30 04:43:36 PM PDT 24 2489482126 ps
T434 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2224653969 Jun 30 04:43:16 PM PDT 24 Jun 30 04:43:39 PM PDT 24 2009412043 ps
T91 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.122341788 Jun 30 04:43:24 PM PDT 24 Jun 30 04:46:50 PM PDT 24 52198801584 ps
T435 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.74424347 Jun 30 04:43:23 PM PDT 24 Jun 30 04:45:34 PM PDT 24 25750539912 ps
T436 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3218019637 Jun 30 04:43:16 PM PDT 24 Jun 30 04:43:39 PM PDT 24 8527741964 ps
T437 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.784105574 Jun 30 04:43:14 PM PDT 24 Jun 30 04:43:35 PM PDT 24 11368846134 ps
T438 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3008386666 Jun 30 04:43:24 PM PDT 24 Jun 30 04:43:40 PM PDT 24 8182113479 ps
T439 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2848536863 Jun 30 04:43:20 PM PDT 24 Jun 30 04:43:28 PM PDT 24 689145363 ps
T440 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2222461469 Jun 30 04:43:15 PM PDT 24 Jun 30 04:46:29 PM PDT 24 94408487070 ps
T114 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3024069061 Jun 30 04:43:15 PM PDT 24 Jun 30 04:45:58 PM PDT 24 1616533674 ps
T441 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2238309262 Jun 30 04:43:15 PM PDT 24 Jun 30 04:43:28 PM PDT 24 1007016393 ps
T442 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2529621195 Jun 30 04:43:11 PM PDT 24 Jun 30 04:43:33 PM PDT 24 2915165945 ps
T443 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3982072122 Jun 30 04:43:23 PM PDT 24 Jun 30 04:44:10 PM PDT 24 1492851064 ps
T94 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2789544566 Jun 30 04:43:14 PM PDT 24 Jun 30 04:43:23 PM PDT 24 177817902 ps
T444 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.83797672 Jun 30 04:43:07 PM PDT 24 Jun 30 04:43:28 PM PDT 24 1554621722 ps
T104 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1830854215 Jun 30 04:43:23 PM PDT 24 Jun 30 04:44:58 PM PDT 24 6732755012 ps
T445 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2618378164 Jun 30 04:43:11 PM PDT 24 Jun 30 04:45:14 PM PDT 24 10789736608 ps
T446 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1686172204 Jun 30 04:43:17 PM PDT 24 Jun 30 04:43:30 PM PDT 24 427088040 ps
T447 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2631037083 Jun 30 04:43:26 PM PDT 24 Jun 30 04:43:57 PM PDT 24 7895324003 ps
T448 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4037591679 Jun 30 04:43:11 PM PDT 24 Jun 30 04:43:28 PM PDT 24 1337553063 ps
T449 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.992958058 Jun 30 04:43:04 PM PDT 24 Jun 30 04:43:21 PM PDT 24 1435895361 ps
T450 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1759170088 Jun 30 04:43:12 PM PDT 24 Jun 30 04:43:53 PM PDT 24 9156280767 ps
T115 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2578397372 Jun 30 04:43:27 PM PDT 24 Jun 30 04:46:20 PM PDT 24 3793517711 ps
T112 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1516229576 Jun 30 04:43:28 PM PDT 24 Jun 30 04:46:18 PM PDT 24 6601223338 ps
T451 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2171502378 Jun 30 04:43:23 PM PDT 24 Jun 30 04:43:33 PM PDT 24 182341969 ps
T452 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3472477991 Jun 30 04:43:16 PM PDT 24 Jun 30 04:43:50 PM PDT 24 22177235276 ps
T92 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.316857026 Jun 30 04:43:20 PM PDT 24 Jun 30 04:45:09 PM PDT 24 12721036546 ps
T453 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3565037598 Jun 30 04:43:10 PM PDT 24 Jun 30 04:43:29 PM PDT 24 3550358846 ps
T454 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2714698271 Jun 30 04:43:23 PM PDT 24 Jun 30 04:43:33 PM PDT 24 661392916 ps
T455 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1156482557 Jun 30 04:43:07 PM PDT 24 Jun 30 04:43:32 PM PDT 24 8159979857 ps
T456 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.278185811 Jun 30 04:43:16 PM PDT 24 Jun 30 04:43:26 PM PDT 24 174315536 ps
T457 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2079946993 Jun 30 04:43:22 PM PDT 24 Jun 30 04:43:56 PM PDT 24 8585728574 ps

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1692286530
Short name T8
Test name
Test status
Simulation time 205653344099 ps
CPU time 642.82 seconds
Started Jun 30 04:48:09 PM PDT 24
Finished Jun 30 04:58:52 PM PDT 24
Peak memory 236052 kb
Host smart-fca3e008-84b8-424d-834f-2895435904c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692286530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1692286530
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3033822309
Short name T12
Test name
Test status
Simulation time 79393218654 ps
CPU time 6434.73 seconds
Started Jun 30 04:47:09 PM PDT 24
Finished Jun 30 06:34:26 PM PDT 24
Peak memory 235664 kb
Host smart-db7f1e0e-6a52-485d-97cb-c0d1bee6eb88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033822309 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.3033822309
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3362736581
Short name T10
Test name
Test status
Simulation time 15162825658 ps
CPU time 146.6 seconds
Started Jun 30 04:48:08 PM PDT 24
Finished Jun 30 04:50:35 PM PDT 24
Peak memory 220492 kb
Host smart-1e7c51e5-a1c3-4e73-a044-25d4e8331a8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362736581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3362736581
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2053125428
Short name T63
Test name
Test status
Simulation time 1334210818 ps
CPU time 156.24 seconds
Started Jun 30 04:43:27 PM PDT 24
Finished Jun 30 04:46:03 PM PDT 24
Peak memory 214000 kb
Host smart-95896847-3497-4ce2-b7cb-7edf38563350
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053125428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2053125428
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.4093212284
Short name T17
Test name
Test status
Simulation time 199147440924 ps
CPU time 432.56 seconds
Started Jun 30 04:48:03 PM PDT 24
Finished Jun 30 04:55:16 PM PDT 24
Peak memory 234888 kb
Host smart-d0020229-6d13-49f9-a296-1cda304b4c6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093212284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.4093212284
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3407847463
Short name T20
Test name
Test status
Simulation time 2872028785 ps
CPU time 241.6 seconds
Started Jun 30 04:46:58 PM PDT 24
Finished Jun 30 04:51:00 PM PDT 24
Peak memory 238776 kb
Host smart-ae7d4f46-ffa8-463f-aa66-83daab3966c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407847463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3407847463
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2924311454
Short name T21
Test name
Test status
Simulation time 2607596935 ps
CPU time 236.99 seconds
Started Jun 30 04:46:41 PM PDT 24
Finished Jun 30 04:50:39 PM PDT 24
Peak memory 239292 kb
Host smart-765ad657-817e-4722-9362-6abad964985a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924311454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2924311454
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3869910752
Short name T73
Test name
Test status
Simulation time 88052226491 ps
CPU time 126.71 seconds
Started Jun 30 04:43:22 PM PDT 24
Finished Jun 30 04:45:30 PM PDT 24
Peak memory 213904 kb
Host smart-5d0d83c6-7c17-4eb8-96dc-16d610b96dee
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869910752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3869910752
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1516229576
Short name T112
Test name
Test status
Simulation time 6601223338 ps
CPU time 168.73 seconds
Started Jun 30 04:43:28 PM PDT 24
Finished Jun 30 04:46:18 PM PDT 24
Peak memory 214264 kb
Host smart-a05d0d5f-9138-4992-b65a-d08d092bf214
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516229576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1516229576
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.122341788
Short name T91
Test name
Test status
Simulation time 52198801584 ps
CPU time 205.25 seconds
Started Jun 30 04:43:24 PM PDT 24
Finished Jun 30 04:46:50 PM PDT 24
Peak memory 214692 kb
Host smart-a1cb020e-16bd-482c-bab1-db475d5be289
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122341788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.122341788
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.20467325
Short name T69
Test name
Test status
Simulation time 7518559536 ps
CPU time 29.4 seconds
Started Jun 30 04:46:38 PM PDT 24
Finished Jun 30 04:47:08 PM PDT 24
Peak memory 217384 kb
Host smart-df2d9e32-3551-4858-aec9-0955450ecdcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20467325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.20467325
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3483547491
Short name T50
Test name
Test status
Simulation time 1388457841 ps
CPU time 29.25 seconds
Started Jun 30 04:46:36 PM PDT 24
Finished Jun 30 04:47:06 PM PDT 24
Peak memory 218604 kb
Host smart-edbc5a1f-443f-4083-af60-9d573978b71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483547491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3483547491
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1281202914
Short name T6
Test name
Test status
Simulation time 332474442 ps
CPU time 19.42 seconds
Started Jun 30 04:46:36 PM PDT 24
Finished Jun 30 04:46:56 PM PDT 24
Peak memory 219180 kb
Host smart-9805cb71-653b-4f05-a9cb-ce8a35b5c3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281202914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1281202914
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2710732831
Short name T113
Test name
Test status
Simulation time 461665016 ps
CPU time 81.05 seconds
Started Jun 30 04:43:24 PM PDT 24
Finished Jun 30 04:44:46 PM PDT 24
Peak memory 213700 kb
Host smart-861877d4-e5ae-4386-a2ea-9ce29f33bb2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710732831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2710732831
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.358241122
Short name T111
Test name
Test status
Simulation time 1218612133 ps
CPU time 77.66 seconds
Started Jun 30 04:43:04 PM PDT 24
Finished Jun 30 04:44:21 PM PDT 24
Peak memory 213308 kb
Host smart-398ae685-f0d3-4135-96a2-f5163bc101c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358241122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.358241122
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2242369465
Short name T106
Test name
Test status
Simulation time 2892122899 ps
CPU time 99.01 seconds
Started Jun 30 04:43:23 PM PDT 24
Finished Jun 30 04:45:03 PM PDT 24
Peak memory 213468 kb
Host smart-4fd3d43d-22c6-4b43-bc56-6eec4a8cc685
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242369465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2242369465
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3768082921
Short name T99
Test name
Test status
Simulation time 3336869524 ps
CPU time 27.96 seconds
Started Jun 30 04:46:36 PM PDT 24
Finished Jun 30 04:47:05 PM PDT 24
Peak memory 219228 kb
Host smart-bd5f382c-21ca-4850-917e-bf9b401fe8f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3768082921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3768082921
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1109633266
Short name T16
Test name
Test status
Simulation time 20764857342 ps
CPU time 3176.62 seconds
Started Jun 30 04:46:40 PM PDT 24
Finished Jun 30 05:39:37 PM PDT 24
Peak memory 235744 kb
Host smart-7093f8d4-4c99-4e9f-8a89-9cb66fb76abe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109633266 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.1109633266
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.3230006384
Short name T53
Test name
Test status
Simulation time 71257043337 ps
CPU time 678.04 seconds
Started Jun 30 04:46:37 PM PDT 24
Finished Jun 30 04:57:56 PM PDT 24
Peak memory 235840 kb
Host smart-d76bcdf5-f540-4fc1-8686-c093ac468582
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230006384 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.3230006384
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.992958058
Short name T449
Test name
Test status
Simulation time 1435895361 ps
CPU time 16.74 seconds
Started Jun 30 04:43:04 PM PDT 24
Finished Jun 30 04:43:21 PM PDT 24
Peak memory 211484 kb
Host smart-f1736a15-6914-4cfb-be6e-3b9a6237b173
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992958058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.992958058
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3322121912
Short name T430
Test name
Test status
Simulation time 9772744421 ps
CPU time 22.16 seconds
Started Jun 30 04:43:11 PM PDT 24
Finished Jun 30 04:43:34 PM PDT 24
Peak memory 211520 kb
Host smart-09e4d2e5-6187-48c7-97dd-8f92fd7c95f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322121912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3322121912
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3830937573
Short name T425
Test name
Test status
Simulation time 2767437259 ps
CPU time 16.17 seconds
Started Jun 30 04:43:07 PM PDT 24
Finished Jun 30 04:43:24 PM PDT 24
Peak memory 211800 kb
Host smart-c53a4fed-791a-4b45-9fff-b2f4e143648d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830937573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3830937573
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2648675402
Short name T423
Test name
Test status
Simulation time 1267845012 ps
CPU time 16.33 seconds
Started Jun 30 04:43:07 PM PDT 24
Finished Jun 30 04:43:24 PM PDT 24
Peak memory 216888 kb
Host smart-8aec61ea-ca30-43b8-801c-efb7abf51474
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648675402 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2648675402
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3907832068
Short name T401
Test name
Test status
Simulation time 2618628291 ps
CPU time 23.82 seconds
Started Jun 30 04:43:07 PM PDT 24
Finished Jun 30 04:43:32 PM PDT 24
Peak memory 210624 kb
Host smart-ccead594-22fc-4e34-97c2-577e78f2b9df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907832068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3907832068
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4037591679
Short name T448
Test name
Test status
Simulation time 1337553063 ps
CPU time 16.17 seconds
Started Jun 30 04:43:11 PM PDT 24
Finished Jun 30 04:43:28 PM PDT 24
Peak memory 210432 kb
Host smart-25648bb2-df57-4496-b690-a29611abd670
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037591679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.4037591679
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2936377002
Short name T410
Test name
Test status
Simulation time 176439293 ps
CPU time 8.09 seconds
Started Jun 30 04:43:09 PM PDT 24
Finished Jun 30 04:43:17 PM PDT 24
Peak memory 210444 kb
Host smart-afc9bb5c-c7ce-460b-9eda-7640dca2d8cc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936377002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2936377002
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1754827963
Short name T93
Test name
Test status
Simulation time 4305371681 ps
CPU time 57.31 seconds
Started Jun 30 04:43:10 PM PDT 24
Finished Jun 30 04:44:08 PM PDT 24
Peak memory 215760 kb
Host smart-ff268d47-05c6-4451-8220-e3fe33f2333e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754827963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1754827963
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2874397643
Short name T98
Test name
Test status
Simulation time 12077110383 ps
CPU time 21.92 seconds
Started Jun 30 04:43:10 PM PDT 24
Finished Jun 30 04:43:32 PM PDT 24
Peak memory 212620 kb
Host smart-c04d004e-9a36-466e-9839-59fdd8099cb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874397643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2874397643
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1383989448
Short name T424
Test name
Test status
Simulation time 1362920868 ps
CPU time 13.06 seconds
Started Jun 30 04:43:03 PM PDT 24
Finished Jun 30 04:43:16 PM PDT 24
Peak memory 217976 kb
Host smart-cfbc6053-8e2c-42bc-9107-1efd74ee9611
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383989448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1383989448
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1747168025
Short name T110
Test name
Test status
Simulation time 1214767103 ps
CPU time 86.65 seconds
Started Jun 30 04:43:04 PM PDT 24
Finished Jun 30 04:44:31 PM PDT 24
Peak memory 213604 kb
Host smart-d6874f64-d5cb-4a50-8a94-140a89c1cab6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747168025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1747168025
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.712497217
Short name T394
Test name
Test status
Simulation time 1008113814 ps
CPU time 14.43 seconds
Started Jun 30 04:43:16 PM PDT 24
Finished Jun 30 04:43:32 PM PDT 24
Peak memory 210584 kb
Host smart-80bcfad0-b6f9-497f-b67c-86d8866e3d8c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712497217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.712497217
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3808466812
Short name T422
Test name
Test status
Simulation time 17026128492 ps
CPU time 32.85 seconds
Started Jun 30 04:43:08 PM PDT 24
Finished Jun 30 04:43:42 PM PDT 24
Peak memory 211848 kb
Host smart-54b6ebb4-181b-45af-8246-d5546c2f0a48
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808466812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3808466812
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1156482557
Short name T455
Test name
Test status
Simulation time 8159979857 ps
CPU time 24.29 seconds
Started Jun 30 04:43:07 PM PDT 24
Finished Jun 30 04:43:32 PM PDT 24
Peak memory 212060 kb
Host smart-43459e8e-291b-4900-a81d-8ca92e8e5553
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156482557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1156482557
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3218019637
Short name T436
Test name
Test status
Simulation time 8527741964 ps
CPU time 22.07 seconds
Started Jun 30 04:43:16 PM PDT 24
Finished Jun 30 04:43:39 PM PDT 24
Peak memory 216248 kb
Host smart-22f7f40a-0057-45d7-8f54-f10048a0b7f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218019637 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3218019637
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2529621195
Short name T442
Test name
Test status
Simulation time 2915165945 ps
CPU time 22.06 seconds
Started Jun 30 04:43:11 PM PDT 24
Finished Jun 30 04:43:33 PM PDT 24
Peak memory 211476 kb
Host smart-1280fb2e-1753-4cfb-a926-992c607a5a4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529621195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2529621195
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3185883251
Short name T375
Test name
Test status
Simulation time 1128650400 ps
CPU time 9.91 seconds
Started Jun 30 04:43:09 PM PDT 24
Finished Jun 30 04:43:19 PM PDT 24
Peak memory 210444 kb
Host smart-c4bca439-993e-4a0c-883f-f09c2dee5339
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185883251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3185883251
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.343401369
Short name T393
Test name
Test status
Simulation time 3936059410 ps
CPU time 28.85 seconds
Started Jun 30 04:43:08 PM PDT 24
Finished Jun 30 04:43:38 PM PDT 24
Peak memory 210524 kb
Host smart-9f15fc42-546b-4343-bc3d-f3bd7119f438
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343401369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
343401369
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2795005861
Short name T82
Test name
Test status
Simulation time 9602833343 ps
CPU time 46.97 seconds
Started Jun 30 04:43:07 PM PDT 24
Finished Jun 30 04:43:55 PM PDT 24
Peak memory 214692 kb
Host smart-69007941-b685-44eb-9883-0c803d0c879e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795005861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2795005861
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.344468750
Short name T397
Test name
Test status
Simulation time 4257614986 ps
CPU time 32.12 seconds
Started Jun 30 04:43:11 PM PDT 24
Finished Jun 30 04:43:44 PM PDT 24
Peak memory 211980 kb
Host smart-2ddb233c-7c23-46e3-8187-4e0ad18d213c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344468750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.344468750
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.83797672
Short name T444
Test name
Test status
Simulation time 1554621722 ps
CPU time 20.19 seconds
Started Jun 30 04:43:07 PM PDT 24
Finished Jun 30 04:43:28 PM PDT 24
Peak memory 218332 kb
Host smart-8a913c6a-a73d-4ae2-8336-99c54630457e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83797672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.83797672
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2391108780
Short name T403
Test name
Test status
Simulation time 384772683 ps
CPU time 9.07 seconds
Started Jun 30 04:43:20 PM PDT 24
Finished Jun 30 04:43:29 PM PDT 24
Peak memory 216312 kb
Host smart-e2df9f1c-8f62-4720-9363-7bbb3d459d8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391108780 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2391108780
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1471103489
Short name T428
Test name
Test status
Simulation time 3488941947 ps
CPU time 28.12 seconds
Started Jun 30 04:43:22 PM PDT 24
Finished Jun 30 04:43:50 PM PDT 24
Peak memory 211360 kb
Host smart-52744c41-1243-4fe8-8d0a-216e40a6ff5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471103489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1471103489
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2618378164
Short name T445
Test name
Test status
Simulation time 10789736608 ps
CPU time 121.88 seconds
Started Jun 30 04:43:11 PM PDT 24
Finished Jun 30 04:45:14 PM PDT 24
Peak memory 214420 kb
Host smart-fdf21d7a-e40e-4783-a52e-df41ad991d2e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618378164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2618378164
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.95158986
Short name T71
Test name
Test status
Simulation time 9102087878 ps
CPU time 27.94 seconds
Started Jun 30 04:43:21 PM PDT 24
Finished Jun 30 04:43:49 PM PDT 24
Peak memory 212256 kb
Host smart-29592e8a-309c-41b6-9858-08391d3141fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95158986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ct
rl_same_csr_outstanding.95158986
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1835294607
Short name T427
Test name
Test status
Simulation time 2667581229 ps
CPU time 29.13 seconds
Started Jun 30 04:43:24 PM PDT 24
Finished Jun 30 04:43:54 PM PDT 24
Peak memory 217276 kb
Host smart-541376cf-2eb0-493e-9fbc-dbfbe56e45c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835294607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1835294607
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.4204088159
Short name T107
Test name
Test status
Simulation time 3885715110 ps
CPU time 162.59 seconds
Started Jun 30 04:43:14 PM PDT 24
Finished Jun 30 04:45:57 PM PDT 24
Peak memory 214012 kb
Host smart-53ea48b2-2f88-4586-b568-b9359f8a12a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204088159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.4204088159
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3928740189
Short name T363
Test name
Test status
Simulation time 16016026760 ps
CPU time 33.49 seconds
Started Jun 30 04:43:24 PM PDT 24
Finished Jun 30 04:43:59 PM PDT 24
Peak memory 217508 kb
Host smart-61b6a2f1-400d-4dfd-8fef-65aaffdea652
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928740189 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3928740189
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2037355846
Short name T87
Test name
Test status
Simulation time 216639865 ps
CPU time 8.09 seconds
Started Jun 30 04:43:21 PM PDT 24
Finished Jun 30 04:43:30 PM PDT 24
Peak memory 210528 kb
Host smart-3e5a3071-d620-443b-bbb8-ddf916506f3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037355846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2037355846
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3802509265
Short name T72
Test name
Test status
Simulation time 4658138038 ps
CPU time 15.62 seconds
Started Jun 30 04:43:22 PM PDT 24
Finished Jun 30 04:43:38 PM PDT 24
Peak memory 211312 kb
Host smart-b76dbed7-11f9-4621-9816-97ffb06cabd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802509265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3802509265
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.154050428
Short name T396
Test name
Test status
Simulation time 8675931745 ps
CPU time 21.49 seconds
Started Jun 30 04:43:23 PM PDT 24
Finished Jun 30 04:43:46 PM PDT 24
Peak memory 218564 kb
Host smart-1a52fc08-06b9-4204-bc13-7b60c10ffe98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154050428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.154050428
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3779132680
Short name T399
Test name
Test status
Simulation time 1691837854 ps
CPU time 19.23 seconds
Started Jun 30 04:43:23 PM PDT 24
Finished Jun 30 04:43:44 PM PDT 24
Peak memory 215024 kb
Host smart-f52a4a6a-f815-4f23-8629-abdabe28a27c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779132680 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3779132680
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.833855545
Short name T400
Test name
Test status
Simulation time 19586497394 ps
CPU time 20.46 seconds
Started Jun 30 04:43:22 PM PDT 24
Finished Jun 30 04:43:42 PM PDT 24
Peak memory 212160 kb
Host smart-b7552689-535a-4c52-b761-6866ff81597c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833855545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.833855545
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3982072122
Short name T443
Test name
Test status
Simulation time 1492851064 ps
CPU time 46.05 seconds
Started Jun 30 04:43:23 PM PDT 24
Finished Jun 30 04:44:10 PM PDT 24
Peak memory 218740 kb
Host smart-cc2172da-78e2-4dc3-a0c9-bfacc266680b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982072122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3982072122
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2927338562
Short name T383
Test name
Test status
Simulation time 837182847 ps
CPU time 12.7 seconds
Started Jun 30 04:43:22 PM PDT 24
Finished Jun 30 04:43:36 PM PDT 24
Peak memory 212772 kb
Host smart-2f23bf64-5479-4904-bdbe-c20e2c0b124e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927338562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2927338562
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2825471867
Short name T404
Test name
Test status
Simulation time 16392429078 ps
CPU time 24.43 seconds
Started Jun 30 04:43:24 PM PDT 24
Finished Jun 30 04:43:50 PM PDT 24
Peak memory 218472 kb
Host smart-64ac2f91-0784-4ecb-ab7a-a920fa3c8a94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825471867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2825471867
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2578397372
Short name T115
Test name
Test status
Simulation time 3793517711 ps
CPU time 172.31 seconds
Started Jun 30 04:43:27 PM PDT 24
Finished Jun 30 04:46:20 PM PDT 24
Peak memory 213568 kb
Host smart-0cb5945a-f7a2-4b3c-b6d9-e62289facd85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578397372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2578397372
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3362436097
Short name T368
Test name
Test status
Simulation time 857085292 ps
CPU time 13.97 seconds
Started Jun 30 04:43:22 PM PDT 24
Finished Jun 30 04:43:37 PM PDT 24
Peak memory 214964 kb
Host smart-a9292615-3d1c-4cbb-921e-98e4b6d58581
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362436097 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3362436097
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2901601855
Short name T412
Test name
Test status
Simulation time 3821154974 ps
CPU time 19.02 seconds
Started Jun 30 04:43:22 PM PDT 24
Finished Jun 30 04:43:42 PM PDT 24
Peak memory 211704 kb
Host smart-6b3d8145-bbb1-4e8d-b7be-37fe1b7c7e25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901601855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2901601855
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1878899344
Short name T77
Test name
Test status
Simulation time 74020735532 ps
CPU time 95.21 seconds
Started Jun 30 04:43:21 PM PDT 24
Finished Jun 30 04:44:56 PM PDT 24
Peak memory 213764 kb
Host smart-94e3caaa-7cef-4dc2-8b09-eec53245ea20
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878899344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1878899344
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2714698271
Short name T454
Test name
Test status
Simulation time 661392916 ps
CPU time 8.61 seconds
Started Jun 30 04:43:23 PM PDT 24
Finished Jun 30 04:43:33 PM PDT 24
Peak memory 211088 kb
Host smart-6255f8f1-ba33-4bac-bf0c-f914e8efbf4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714698271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2714698271
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2610481166
Short name T361
Test name
Test status
Simulation time 8874685116 ps
CPU time 24.56 seconds
Started Jun 30 04:43:21 PM PDT 24
Finished Jun 30 04:43:46 PM PDT 24
Peak memory 218528 kb
Host smart-a1401710-42cc-4ec0-a7dc-3a7df77d1db1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610481166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2610481166
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1830854215
Short name T104
Test name
Test status
Simulation time 6732755012 ps
CPU time 93.81 seconds
Started Jun 30 04:43:23 PM PDT 24
Finished Jun 30 04:44:58 PM PDT 24
Peak memory 213548 kb
Host smart-70453213-9141-4d29-9aad-d2affb135bbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830854215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1830854215
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1535837408
Short name T376
Test name
Test status
Simulation time 11538801684 ps
CPU time 24.21 seconds
Started Jun 30 04:43:30 PM PDT 24
Finished Jun 30 04:43:55 PM PDT 24
Peak memory 215860 kb
Host smart-645f3009-49d8-4d94-b07e-77ef17386381
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535837408 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1535837408
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2848536863
Short name T439
Test name
Test status
Simulation time 689145363 ps
CPU time 8.53 seconds
Started Jun 30 04:43:20 PM PDT 24
Finished Jun 30 04:43:28 PM PDT 24
Peak memory 211292 kb
Host smart-d11b15d5-8e55-4fe1-88ce-2a4daba1cd23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848536863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2848536863
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.74424347
Short name T435
Test name
Test status
Simulation time 25750539912 ps
CPU time 129.42 seconds
Started Jun 30 04:43:23 PM PDT 24
Finished Jun 30 04:45:34 PM PDT 24
Peak memory 215224 kb
Host smart-44cc4c09-1cb7-485c-9f75-ef29ce9e6988
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74424347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pas
sthru_mem_tl_intg_err.74424347
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3918706552
Short name T65
Test name
Test status
Simulation time 9236993886 ps
CPU time 37.86 seconds
Started Jun 30 04:43:20 PM PDT 24
Finished Jun 30 04:43:58 PM PDT 24
Peak memory 212400 kb
Host smart-f2725c0f-2b62-4bff-a6ba-ba2b09c1f933
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918706552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3918706552
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2242865255
Short name T406
Test name
Test status
Simulation time 37940193886 ps
CPU time 36.76 seconds
Started Jun 30 04:43:35 PM PDT 24
Finished Jun 30 04:44:12 PM PDT 24
Peak memory 218616 kb
Host smart-53fb22d5-1e8d-4c84-b011-194946a55f83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242865255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2242865255
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.658804562
Short name T372
Test name
Test status
Simulation time 770269134 ps
CPU time 14.09 seconds
Started Jun 30 04:43:21 PM PDT 24
Finished Jun 30 04:43:36 PM PDT 24
Peak memory 216140 kb
Host smart-49b580cf-68f9-4958-a116-bc75af5f7271
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658804562 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.658804562
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.93993847
Short name T85
Test name
Test status
Simulation time 9760945245 ps
CPU time 23.5 seconds
Started Jun 30 04:43:23 PM PDT 24
Finished Jun 30 04:43:47 PM PDT 24
Peak memory 211696 kb
Host smart-ccb3e4ef-4f55-48bb-be76-510524e32857
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93993847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.93993847
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1639782177
Short name T377
Test name
Test status
Simulation time 6537208510 ps
CPU time 77.05 seconds
Started Jun 30 04:43:23 PM PDT 24
Finished Jun 30 04:44:41 PM PDT 24
Peak memory 213728 kb
Host smart-faa8c149-2a39-4f28-8be6-38f87221a66f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639782177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1639782177
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.4174193135
Short name T398
Test name
Test status
Simulation time 4135103759 ps
CPU time 36.08 seconds
Started Jun 30 04:43:21 PM PDT 24
Finished Jun 30 04:43:58 PM PDT 24
Peak memory 212284 kb
Host smart-06351c9b-afc7-4a15-a1ce-7cf3a237ba4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174193135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.4174193135
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.4220692723
Short name T379
Test name
Test status
Simulation time 3838460994 ps
CPU time 33.02 seconds
Started Jun 30 04:43:33 PM PDT 24
Finished Jun 30 04:44:06 PM PDT 24
Peak memory 218084 kb
Host smart-156bd819-24e5-470f-8092-8f75e74b2a9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220692723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.4220692723
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2825258813
Short name T378
Test name
Test status
Simulation time 2492529891 ps
CPU time 93.39 seconds
Started Jun 30 04:43:32 PM PDT 24
Finished Jun 30 04:45:06 PM PDT 24
Peak memory 218892 kb
Host smart-75ff6572-da99-4e40-93af-36c0747677de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825258813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2825258813
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2171502378
Short name T451
Test name
Test status
Simulation time 182341969 ps
CPU time 8.7 seconds
Started Jun 30 04:43:23 PM PDT 24
Finished Jun 30 04:43:33 PM PDT 24
Peak memory 213844 kb
Host smart-477a11dc-cc74-4eea-a303-46cd4911a2a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171502378 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2171502378
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2672917283
Short name T76
Test name
Test status
Simulation time 1373165474 ps
CPU time 16.73 seconds
Started Jun 30 04:43:24 PM PDT 24
Finished Jun 30 04:43:42 PM PDT 24
Peak memory 212004 kb
Host smart-f5874fca-958e-4a75-93a9-2f9000456ae2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672917283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2672917283
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.316857026
Short name T92
Test name
Test status
Simulation time 12721036546 ps
CPU time 108.96 seconds
Started Jun 30 04:43:20 PM PDT 24
Finished Jun 30 04:45:09 PM PDT 24
Peak memory 213740 kb
Host smart-999e2d82-7a5a-4f63-b914-9def01ffca0e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316857026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.316857026
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2268719529
Short name T382
Test name
Test status
Simulation time 4872334896 ps
CPU time 20.28 seconds
Started Jun 30 04:43:32 PM PDT 24
Finished Jun 30 04:43:53 PM PDT 24
Peak memory 212724 kb
Host smart-6c55ef9e-7e34-4196-a0c5-31112d6ca2c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268719529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2268719529
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1524994292
Short name T415
Test name
Test status
Simulation time 1221902682 ps
CPU time 21.63 seconds
Started Jun 30 04:43:24 PM PDT 24
Finished Jun 30 04:43:47 PM PDT 24
Peak memory 218348 kb
Host smart-604055e3-37f3-456b-a2b8-0b06897abb43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524994292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1524994292
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.648897175
Short name T62
Test name
Test status
Simulation time 3383496827 ps
CPU time 171.5 seconds
Started Jun 30 04:43:31 PM PDT 24
Finished Jun 30 04:46:28 PM PDT 24
Peak memory 213808 kb
Host smart-6ea5278d-ded7-4c48-9570-6dab500c42f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648897175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.648897175
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2079946993
Short name T457
Test name
Test status
Simulation time 8585728574 ps
CPU time 32.95 seconds
Started Jun 30 04:43:22 PM PDT 24
Finished Jun 30 04:43:56 PM PDT 24
Peak memory 216088 kb
Host smart-79cdf0b2-be6e-450d-92de-c0e94892b9dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079946993 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2079946993
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3008386666
Short name T438
Test name
Test status
Simulation time 8182113479 ps
CPU time 15.14 seconds
Started Jun 30 04:43:24 PM PDT 24
Finished Jun 30 04:43:40 PM PDT 24
Peak memory 211968 kb
Host smart-433285e6-5ab5-4123-915f-ed4eb9d090fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008386666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3008386666
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4291546609
Short name T88
Test name
Test status
Simulation time 40498039922 ps
CPU time 126.92 seconds
Started Jun 30 04:43:22 PM PDT 24
Finished Jun 30 04:45:30 PM PDT 24
Peak memory 214932 kb
Host smart-f8f6ce1c-3734-4202-9ff2-d4895afee3fc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291546609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.4291546609
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2373000200
Short name T387
Test name
Test status
Simulation time 29623719240 ps
CPU time 37.78 seconds
Started Jun 30 04:43:23 PM PDT 24
Finished Jun 30 04:44:03 PM PDT 24
Peak memory 212580 kb
Host smart-a8ce6dd7-f618-441f-9618-d50f3520a268
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373000200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2373000200
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3002752108
Short name T360
Test name
Test status
Simulation time 10116800088 ps
CPU time 28.18 seconds
Started Jun 30 04:43:23 PM PDT 24
Finished Jun 30 04:43:52 PM PDT 24
Peak memory 217704 kb
Host smart-43f10c0e-b9e7-4920-9260-454e86ec7545
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002752108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3002752108
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4130647220
Short name T411
Test name
Test status
Simulation time 14675205258 ps
CPU time 21.17 seconds
Started Jun 30 04:43:29 PM PDT 24
Finished Jun 30 04:43:55 PM PDT 24
Peak memory 218396 kb
Host smart-4d652cb0-ed38-4d3b-8c74-983c692b18fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130647220 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.4130647220
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3634557300
Short name T380
Test name
Test status
Simulation time 5215925401 ps
CPU time 24.76 seconds
Started Jun 30 04:43:21 PM PDT 24
Finished Jun 30 04:43:46 PM PDT 24
Peak memory 211704 kb
Host smart-400a952e-d45b-4618-901e-4aaebd9cbdbe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634557300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3634557300
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2611536373
Short name T97
Test name
Test status
Simulation time 37721146926 ps
CPU time 26.28 seconds
Started Jun 30 04:43:22 PM PDT 24
Finished Jun 30 04:43:49 PM PDT 24
Peak memory 212060 kb
Host smart-f1705b9e-a926-42ba-b673-ba755959791d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611536373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2611536373
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.622077641
Short name T389
Test name
Test status
Simulation time 33602561983 ps
CPU time 33.91 seconds
Started Jun 30 04:43:22 PM PDT 24
Finished Jun 30 04:43:56 PM PDT 24
Peak memory 218720 kb
Host smart-a5438263-fb6b-42c4-8e3d-61ee568b5b97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622077641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.622077641
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.503644609
Short name T421
Test name
Test status
Simulation time 8914904295 ps
CPU time 23.04 seconds
Started Jun 30 04:43:29 PM PDT 24
Finished Jun 30 04:43:52 PM PDT 24
Peak memory 217464 kb
Host smart-6a3bf22e-2af0-48d7-a4f4-bcd303ea7150
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503644609 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.503644609
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2769637967
Short name T66
Test name
Test status
Simulation time 6515929979 ps
CPU time 20.96 seconds
Started Jun 30 04:43:33 PM PDT 24
Finished Jun 30 04:43:54 PM PDT 24
Peak memory 211844 kb
Host smart-eeb99f03-654e-4259-84c5-265a57c1dbd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769637967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2769637967
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2840287642
Short name T89
Test name
Test status
Simulation time 71931848759 ps
CPU time 113.75 seconds
Started Jun 30 04:43:23 PM PDT 24
Finished Jun 30 04:45:17 PM PDT 24
Peak memory 213660 kb
Host smart-a37ba9d2-1d3b-413d-bb05-2db976418f1a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840287642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2840287642
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2631037083
Short name T447
Test name
Test status
Simulation time 7895324003 ps
CPU time 31.27 seconds
Started Jun 30 04:43:26 PM PDT 24
Finished Jun 30 04:43:57 PM PDT 24
Peak memory 212432 kb
Host smart-307182f8-1a1d-4737-aa17-d16be8876b7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631037083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2631037083
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3667899617
Short name T369
Test name
Test status
Simulation time 2215232514 ps
CPU time 23.85 seconds
Started Jun 30 04:43:24 PM PDT 24
Finished Jun 30 04:43:49 PM PDT 24
Peak memory 218860 kb
Host smart-7ecf8c36-1cb7-4080-816c-e3b43b15013d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667899617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3667899617
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.156571807
Short name T108
Test name
Test status
Simulation time 1115936344 ps
CPU time 82.71 seconds
Started Jun 30 04:43:30 PM PDT 24
Finished Jun 30 04:44:53 PM PDT 24
Peak memory 213612 kb
Host smart-297a44e9-5d70-4804-a2db-808a4a9c8016
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156571807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.156571807
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3472477991
Short name T452
Test name
Test status
Simulation time 22177235276 ps
CPU time 32.93 seconds
Started Jun 30 04:43:16 PM PDT 24
Finished Jun 30 04:43:50 PM PDT 24
Peak memory 212032 kb
Host smart-675e9305-800c-428f-b478-f69d5d0fbff4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472477991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3472477991
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1273403037
Short name T420
Test name
Test status
Simulation time 3297354461 ps
CPU time 8.39 seconds
Started Jun 30 04:43:13 PM PDT 24
Finished Jun 30 04:43:22 PM PDT 24
Peak memory 210636 kb
Host smart-6bd503a4-b099-4c74-9583-7bc00041d5c1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273403037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1273403037
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2803451109
Short name T86
Test name
Test status
Simulation time 581991277 ps
CPU time 16.08 seconds
Started Jun 30 04:43:16 PM PDT 24
Finished Jun 30 04:43:33 PM PDT 24
Peak memory 211456 kb
Host smart-e3de00ae-f89f-4075-9e6a-d2169197ebe8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803451109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2803451109
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2991197100
Short name T391
Test name
Test status
Simulation time 4132707851 ps
CPU time 13.08 seconds
Started Jun 30 04:43:14 PM PDT 24
Finished Jun 30 04:43:27 PM PDT 24
Peak memory 213644 kb
Host smart-619df24a-67c1-4d34-99c0-b1b7eed0839a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991197100 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2991197100
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3362158968
Short name T432
Test name
Test status
Simulation time 6438040887 ps
CPU time 18.61 seconds
Started Jun 30 04:43:17 PM PDT 24
Finished Jun 30 04:43:36 PM PDT 24
Peak memory 211956 kb
Host smart-e73f270c-8ed6-428a-869d-c6ac58f44caf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362158968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3362158968
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3387066254
Short name T407
Test name
Test status
Simulation time 1478368783 ps
CPU time 13.16 seconds
Started Jun 30 04:43:16 PM PDT 24
Finished Jun 30 04:43:30 PM PDT 24
Peak memory 210452 kb
Host smart-88911af0-959d-473f-b95c-a5e2534915ef
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387066254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3387066254
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2604891101
Short name T419
Test name
Test status
Simulation time 11250365512 ps
CPU time 25.34 seconds
Started Jun 30 04:43:15 PM PDT 24
Finished Jun 30 04:43:41 PM PDT 24
Peak memory 210724 kb
Host smart-35e69012-7611-4662-9d59-42b94078b7d2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604891101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2604891101
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2282233237
Short name T370
Test name
Test status
Simulation time 14035975488 ps
CPU time 121.43 seconds
Started Jun 30 04:43:11 PM PDT 24
Finished Jun 30 04:45:13 PM PDT 24
Peak memory 214028 kb
Host smart-c3043b1f-901b-44ee-8c02-4db4fa62622e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282233237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2282233237
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2999530784
Short name T433
Test name
Test status
Simulation time 2489482126 ps
CPU time 22.64 seconds
Started Jun 30 04:43:13 PM PDT 24
Finished Jun 30 04:43:36 PM PDT 24
Peak memory 212320 kb
Host smart-4fa9906e-6baa-4818-88d1-35b338754b22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999530784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2999530784
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2498345583
Short name T405
Test name
Test status
Simulation time 353042408 ps
CPU time 11.97 seconds
Started Jun 30 04:43:17 PM PDT 24
Finished Jun 30 04:43:30 PM PDT 24
Peak memory 217064 kb
Host smart-04e17c2e-30f2-4367-9d4b-2700eb69b6c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498345583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2498345583
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3934885227
Short name T116
Test name
Test status
Simulation time 8906346215 ps
CPU time 97 seconds
Started Jun 30 04:43:12 PM PDT 24
Finished Jun 30 04:44:50 PM PDT 24
Peak memory 213864 kb
Host smart-51c86226-bc37-4361-b11d-35b1377a71e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934885227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3934885227
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1409840946
Short name T75
Test name
Test status
Simulation time 2668154956 ps
CPU time 22.86 seconds
Started Jun 30 04:43:21 PM PDT 24
Finished Jun 30 04:43:44 PM PDT 24
Peak memory 211044 kb
Host smart-5021f454-1d96-410d-a648-31de3b531a3a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409840946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1409840946
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.784105574
Short name T437
Test name
Test status
Simulation time 11368846134 ps
CPU time 21 seconds
Started Jun 30 04:43:14 PM PDT 24
Finished Jun 30 04:43:35 PM PDT 24
Peak memory 212032 kb
Host smart-1e0a3422-0b43-485d-8f0a-b717f9c8088d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784105574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.784105574
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2510016605
Short name T408
Test name
Test status
Simulation time 395001048 ps
CPU time 15.17 seconds
Started Jun 30 04:43:15 PM PDT 24
Finished Jun 30 04:43:31 PM PDT 24
Peak memory 211888 kb
Host smart-0291a6ab-1894-4135-a32f-cd02ef38b389
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510016605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2510016605
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3716705008
Short name T362
Test name
Test status
Simulation time 55584345536 ps
CPU time 31.29 seconds
Started Jun 30 04:43:17 PM PDT 24
Finished Jun 30 04:43:49 PM PDT 24
Peak memory 215868 kb
Host smart-b76a295a-4e3c-4648-91d1-95b1acc5ed28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716705008 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3716705008
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2409708544
Short name T388
Test name
Test status
Simulation time 174587779 ps
CPU time 8.01 seconds
Started Jun 30 04:43:11 PM PDT 24
Finished Jun 30 04:43:19 PM PDT 24
Peak memory 210528 kb
Host smart-8e4c6a3e-cc31-483f-807c-2b48e9d72c0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409708544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2409708544
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4225570500
Short name T365
Test name
Test status
Simulation time 332068869 ps
CPU time 8.17 seconds
Started Jun 30 04:43:15 PM PDT 24
Finished Jun 30 04:43:24 PM PDT 24
Peak memory 210452 kb
Host smart-ce4da57d-47fd-472b-a415-496fea1bd2a3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225570500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.4225570500
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2238309262
Short name T441
Test name
Test status
Simulation time 1007016393 ps
CPU time 11.93 seconds
Started Jun 30 04:43:15 PM PDT 24
Finished Jun 30 04:43:28 PM PDT 24
Peak memory 210412 kb
Host smart-e92ad191-a550-42d1-b146-6da87279addf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238309262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2238309262
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3475576830
Short name T83
Test name
Test status
Simulation time 64426406507 ps
CPU time 132.29 seconds
Started Jun 30 04:43:15 PM PDT 24
Finished Jun 30 04:45:28 PM PDT 24
Peak memory 213636 kb
Host smart-f5840b78-dea8-4770-a349-84d4dd40fece
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475576830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3475576830
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.278185811
Short name T456
Test name
Test status
Simulation time 174315536 ps
CPU time 8.09 seconds
Started Jun 30 04:43:16 PM PDT 24
Finished Jun 30 04:43:26 PM PDT 24
Peak memory 211048 kb
Host smart-fe13e85a-52c5-4bc9-857a-d56d94842b56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278185811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.278185811
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4127918247
Short name T367
Test name
Test status
Simulation time 14522922243 ps
CPU time 31.86 seconds
Started Jun 30 04:43:14 PM PDT 24
Finished Jun 30 04:43:46 PM PDT 24
Peak memory 217472 kb
Host smart-ca11d4d0-159c-4874-8fd9-f8dfdbcdc675
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127918247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.4127918247
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.887171555
Short name T417
Test name
Test status
Simulation time 13902775745 ps
CPU time 99.72 seconds
Started Jun 30 04:43:13 PM PDT 24
Finished Jun 30 04:44:54 PM PDT 24
Peak memory 213880 kb
Host smart-972f872e-4212-4442-8887-fd4a6ab4bb92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887171555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.887171555
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1700155795
Short name T431
Test name
Test status
Simulation time 5128751425 ps
CPU time 16.14 seconds
Started Jun 30 04:43:16 PM PDT 24
Finished Jun 30 04:43:33 PM PDT 24
Peak memory 210880 kb
Host smart-6a9fd790-94e7-4d0e-9e25-568978b0b906
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700155795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1700155795
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.337001383
Short name T64
Test name
Test status
Simulation time 1507016709 ps
CPU time 13.82 seconds
Started Jun 30 04:43:16 PM PDT 24
Finished Jun 30 04:43:31 PM PDT 24
Peak memory 210592 kb
Host smart-7f59c95d-08cc-468c-8465-249cb9878006
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337001383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.337001383
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1759170088
Short name T450
Test name
Test status
Simulation time 9156280767 ps
CPU time 40.56 seconds
Started Jun 30 04:43:12 PM PDT 24
Finished Jun 30 04:43:53 PM PDT 24
Peak memory 212236 kb
Host smart-194640ac-e5ad-475b-b556-600cc3a0a5e1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759170088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1759170088
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1686172204
Short name T446
Test name
Test status
Simulation time 427088040 ps
CPU time 11.82 seconds
Started Jun 30 04:43:17 PM PDT 24
Finished Jun 30 04:43:30 PM PDT 24
Peak memory 216132 kb
Host smart-f4550a97-8a0e-4fd7-b050-61acefb62832
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686172204 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1686172204
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1605036778
Short name T392
Test name
Test status
Simulation time 6850754739 ps
CPU time 27.23 seconds
Started Jun 30 04:43:11 PM PDT 24
Finished Jun 30 04:43:40 PM PDT 24
Peak memory 211864 kb
Host smart-5e89d9c8-b95f-45b9-95a3-a9c147deb90d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605036778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1605036778
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2162523360
Short name T402
Test name
Test status
Simulation time 1538591838 ps
CPU time 17.31 seconds
Started Jun 30 04:43:14 PM PDT 24
Finished Jun 30 04:43:32 PM PDT 24
Peak memory 210404 kb
Host smart-39c63cc4-35a5-48ca-a896-6f661797db1c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162523360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2162523360
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2367797729
Short name T381
Test name
Test status
Simulation time 174424016 ps
CPU time 8.22 seconds
Started Jun 30 04:43:14 PM PDT 24
Finished Jun 30 04:43:22 PM PDT 24
Peak memory 210188 kb
Host smart-5936ccf2-1281-44e3-ac54-76c9540f376a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367797729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2367797729
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1814193888
Short name T416
Test name
Test status
Simulation time 47288477438 ps
CPU time 197.73 seconds
Started Jun 30 04:43:15 PM PDT 24
Finished Jun 30 04:46:33 PM PDT 24
Peak memory 214976 kb
Host smart-35125393-d199-43cd-8d74-4379be62cce3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814193888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1814193888
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3518548019
Short name T95
Test name
Test status
Simulation time 9153378449 ps
CPU time 24.95 seconds
Started Jun 30 04:43:15 PM PDT 24
Finished Jun 30 04:43:41 PM PDT 24
Peak memory 212648 kb
Host smart-33635d3c-c3da-4912-8757-1301321d2221
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518548019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3518548019
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3805963339
Short name T371
Test name
Test status
Simulation time 17670475260 ps
CPU time 36.79 seconds
Started Jun 30 04:43:15 PM PDT 24
Finished Jun 30 04:43:53 PM PDT 24
Peak memory 218740 kb
Host smart-46504092-8321-451f-b9a3-af8a261d016f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805963339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3805963339
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2510306013
Short name T61
Test name
Test status
Simulation time 10735065864 ps
CPU time 161.72 seconds
Started Jun 30 04:43:17 PM PDT 24
Finished Jun 30 04:46:00 PM PDT 24
Peak memory 214256 kb
Host smart-64e3b1ed-470d-4afe-89a8-0a290668ab4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510306013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2510306013
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.365351869
Short name T418
Test name
Test status
Simulation time 187651072 ps
CPU time 9.47 seconds
Started Jun 30 04:43:16 PM PDT 24
Finished Jun 30 04:43:27 PM PDT 24
Peak memory 217328 kb
Host smart-b7f43f3e-f99d-46c5-9a09-50eae5889d4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365351869 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.365351869
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1822791464
Short name T74
Test name
Test status
Simulation time 5830058293 ps
CPU time 25.79 seconds
Started Jun 30 04:43:16 PM PDT 24
Finished Jun 30 04:43:43 PM PDT 24
Peak memory 211984 kb
Host smart-c4f9eafe-a164-4828-a325-27a4c242ce04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822791464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1822791464
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2803998898
Short name T78
Test name
Test status
Simulation time 103512557116 ps
CPU time 118.85 seconds
Started Jun 30 04:43:15 PM PDT 24
Finished Jun 30 04:45:15 PM PDT 24
Peak memory 214748 kb
Host smart-b9e72ca6-1f1a-4b67-90d8-b3bdbe25428b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803998898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2803998898
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.530454186
Short name T384
Test name
Test status
Simulation time 10155344478 ps
CPU time 23.48 seconds
Started Jun 30 04:43:17 PM PDT 24
Finished Jun 30 04:43:42 PM PDT 24
Peak memory 212360 kb
Host smart-76d16915-d068-4e62-8222-30f3edfc63ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530454186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.530454186
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.833055005
Short name T426
Test name
Test status
Simulation time 1889324698 ps
CPU time 19.68 seconds
Started Jun 30 04:43:17 PM PDT 24
Finished Jun 30 04:43:38 PM PDT 24
Peak memory 218600 kb
Host smart-812b0976-7c35-42d5-afbf-1e3992e4a2c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833055005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.833055005
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2504634855
Short name T109
Test name
Test status
Simulation time 50396477757 ps
CPU time 96.66 seconds
Started Jun 30 04:43:15 PM PDT 24
Finished Jun 30 04:44:53 PM PDT 24
Peak memory 213776 kb
Host smart-2548f64a-71b3-4ec1-9c40-2d5aa7ed4af0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504634855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2504634855
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.83619579
Short name T414
Test name
Test status
Simulation time 2634418978 ps
CPU time 24.29 seconds
Started Jun 30 04:43:16 PM PDT 24
Finished Jun 30 04:43:42 PM PDT 24
Peak memory 217308 kb
Host smart-70c7c15c-9ae4-42f9-bb8c-64372b2a6574
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83619579 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.83619579
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3099200722
Short name T79
Test name
Test status
Simulation time 9946588201 ps
CPU time 25.06 seconds
Started Jun 30 04:43:13 PM PDT 24
Finished Jun 30 04:43:38 PM PDT 24
Peak memory 212248 kb
Host smart-30135d06-e62f-48b4-8a7e-fb7cea366566
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099200722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3099200722
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2345375268
Short name T409
Test name
Test status
Simulation time 35930906465 ps
CPU time 111.87 seconds
Started Jun 30 04:43:15 PM PDT 24
Finished Jun 30 04:45:08 PM PDT 24
Peak memory 214988 kb
Host smart-307418a3-3bc2-4db5-b2af-6fe4cd824417
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345375268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2345375268
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3466186871
Short name T395
Test name
Test status
Simulation time 3925293968 ps
CPU time 19.9 seconds
Started Jun 30 04:43:16 PM PDT 24
Finished Jun 30 04:43:37 PM PDT 24
Peak memory 212104 kb
Host smart-93c8b373-4fa2-4f30-8629-cc91fd43e26b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466186871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3466186871
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1290559287
Short name T373
Test name
Test status
Simulation time 487310573 ps
CPU time 11.03 seconds
Started Jun 30 04:43:16 PM PDT 24
Finished Jun 30 04:43:28 PM PDT 24
Peak memory 216968 kb
Host smart-a0bf36c4-e2c5-42f1-9a7c-683c042c5dee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290559287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1290559287
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3024069061
Short name T114
Test name
Test status
Simulation time 1616533674 ps
CPU time 162.46 seconds
Started Jun 30 04:43:15 PM PDT 24
Finished Jun 30 04:45:58 PM PDT 24
Peak memory 214904 kb
Host smart-08a2ed41-e5ef-482e-a9bd-7006c74860b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024069061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3024069061
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2224653969
Short name T434
Test name
Test status
Simulation time 2009412043 ps
CPU time 21.75 seconds
Started Jun 30 04:43:16 PM PDT 24
Finished Jun 30 04:43:39 PM PDT 24
Peak memory 217208 kb
Host smart-eb83c6c7-751a-48c8-9eba-739163cb1c1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224653969 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2224653969
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3118876120
Short name T90
Test name
Test status
Simulation time 8949656658 ps
CPU time 21.52 seconds
Started Jun 30 04:43:15 PM PDT 24
Finished Jun 30 04:43:38 PM PDT 24
Peak memory 212288 kb
Host smart-b1494423-d0be-4184-bef9-b5de623baae0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118876120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3118876120
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2222461469
Short name T440
Test name
Test status
Simulation time 94408487070 ps
CPU time 193.57 seconds
Started Jun 30 04:43:15 PM PDT 24
Finished Jun 30 04:46:29 PM PDT 24
Peak memory 215104 kb
Host smart-8fd762ac-f0c5-45af-8f10-f111c0677973
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222461469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2222461469
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2349248842
Short name T96
Test name
Test status
Simulation time 2069311708 ps
CPU time 24.57 seconds
Started Jun 30 04:43:14 PM PDT 24
Finished Jun 30 04:43:39 PM PDT 24
Peak memory 211936 kb
Host smart-0e8a68de-6e9e-4d23-be05-d0667aab92cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349248842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2349248842
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2240096304
Short name T374
Test name
Test status
Simulation time 4152733884 ps
CPU time 33.71 seconds
Started Jun 30 04:43:16 PM PDT 24
Finished Jun 30 04:43:51 PM PDT 24
Peak memory 218308 kb
Host smart-38b04945-b989-4693-a0f9-1d9d1d9108b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240096304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2240096304
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1888724067
Short name T105
Test name
Test status
Simulation time 4213821541 ps
CPU time 103.39 seconds
Started Jun 30 04:43:15 PM PDT 24
Finished Jun 30 04:45:00 PM PDT 24
Peak memory 213516 kb
Host smart-d68962f5-65d2-46bf-83de-9dcfe0074a64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888724067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1888724067
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.818293845
Short name T385
Test name
Test status
Simulation time 2749390121 ps
CPU time 25.26 seconds
Started Jun 30 04:43:20 PM PDT 24
Finished Jun 30 04:43:46 PM PDT 24
Peak memory 217032 kb
Host smart-acd26170-29d8-476c-915c-2f9146c84d42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818293845 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.818293845
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2315168342
Short name T364
Test name
Test status
Simulation time 15439135151 ps
CPU time 31.08 seconds
Started Jun 30 04:43:17 PM PDT 24
Finished Jun 30 04:43:49 PM PDT 24
Peak memory 212084 kb
Host smart-e333304f-b963-4ebd-93e9-c2452f218507
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315168342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2315168342
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2449043763
Short name T102
Test name
Test status
Simulation time 29285774781 ps
CPU time 119.95 seconds
Started Jun 30 04:43:15 PM PDT 24
Finished Jun 30 04:45:15 PM PDT 24
Peak memory 213588 kb
Host smart-51036ba3-8faa-4b2c-bf45-0349fd7e6c1f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449043763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2449043763
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3565037598
Short name T453
Test name
Test status
Simulation time 3550358846 ps
CPU time 19.44 seconds
Started Jun 30 04:43:10 PM PDT 24
Finished Jun 30 04:43:29 PM PDT 24
Peak memory 212176 kb
Host smart-b554220b-2db5-433f-b6b5-a6790fbe0ab7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565037598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3565037598
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.189948222
Short name T366
Test name
Test status
Simulation time 13151990025 ps
CPU time 33.9 seconds
Started Jun 30 04:43:16 PM PDT 24
Finished Jun 30 04:43:51 PM PDT 24
Peak memory 217088 kb
Host smart-a971f138-2997-4234-8151-c3904562a1b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189948222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.189948222
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1279963557
Short name T386
Test name
Test status
Simulation time 822967269 ps
CPU time 85.17 seconds
Started Jun 30 04:43:13 PM PDT 24
Finished Jun 30 04:44:38 PM PDT 24
Peak memory 213504 kb
Host smart-1702391e-f811-4d53-a770-c37909fcf34e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279963557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1279963557
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1250320605
Short name T413
Test name
Test status
Simulation time 45736992698 ps
CPU time 29.01 seconds
Started Jun 30 04:43:16 PM PDT 24
Finished Jun 30 04:43:47 PM PDT 24
Peak memory 215236 kb
Host smart-2318eafb-9fc2-4429-a0d4-32b5ed8b479a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250320605 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1250320605
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2789544566
Short name T94
Test name
Test status
Simulation time 177817902 ps
CPU time 8.09 seconds
Started Jun 30 04:43:14 PM PDT 24
Finished Jun 30 04:43:23 PM PDT 24
Peak memory 210520 kb
Host smart-fa679b40-c7c4-4468-993c-39cedeafa091
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789544566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2789544566
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1433048598
Short name T84
Test name
Test status
Simulation time 1053514011 ps
CPU time 57.04 seconds
Started Jun 30 04:43:15 PM PDT 24
Finished Jun 30 04:44:13 PM PDT 24
Peak memory 213756 kb
Host smart-8b744d2e-fb37-4c00-9f87-71df841712d9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433048598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1433048598
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3132535674
Short name T390
Test name
Test status
Simulation time 3287867592 ps
CPU time 29.68 seconds
Started Jun 30 04:43:11 PM PDT 24
Finished Jun 30 04:43:42 PM PDT 24
Peak memory 212268 kb
Host smart-76a3e342-40a6-41a3-8dae-0fb149dad049
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132535674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3132535674
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2808990964
Short name T429
Test name
Test status
Simulation time 11144736782 ps
CPU time 29.93 seconds
Started Jun 30 04:43:16 PM PDT 24
Finished Jun 30 04:43:47 PM PDT 24
Peak memory 219008 kb
Host smart-dd05f299-2749-49e9-b382-6441c765169a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808990964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2808990964
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1985926904
Short name T103
Test name
Test status
Simulation time 966360706 ps
CPU time 80.74 seconds
Started Jun 30 04:43:18 PM PDT 24
Finished Jun 30 04:44:39 PM PDT 24
Peak memory 213680 kb
Host smart-39a38276-b344-41fa-91fa-5e39a38c73ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985926904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1985926904
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1465728888
Short name T210
Test name
Test status
Simulation time 24523057431 ps
CPU time 19.14 seconds
Started Jun 30 04:46:36 PM PDT 24
Finished Jun 30 04:46:56 PM PDT 24
Peak memory 217504 kb
Host smart-00d91d6c-ad94-4b80-a53d-4bd148860fe3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465728888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1465728888
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.4231249903
Short name T38
Test name
Test status
Simulation time 96758568610 ps
CPU time 993.49 seconds
Started Jun 30 04:46:36 PM PDT 24
Finished Jun 30 05:03:11 PM PDT 24
Peak memory 238136 kb
Host smart-6733dade-d487-44f1-b475-18072b040016
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231249903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.4231249903
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2037085934
Short name T226
Test name
Test status
Simulation time 3622471437 ps
CPU time 30.94 seconds
Started Jun 30 04:46:27 PM PDT 24
Finished Jun 30 04:46:58 PM PDT 24
Peak memory 219272 kb
Host smart-506e1807-8177-443e-9a18-5d7c46ce8e90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2037085934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2037085934
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.4192135822
Short name T23
Test name
Test status
Simulation time 7893957605 ps
CPU time 138.32 seconds
Started Jun 30 04:46:36 PM PDT 24
Finished Jun 30 04:48:54 PM PDT 24
Peak memory 234604 kb
Host smart-d8fef4db-10b5-4b87-9d43-dda78430a0ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192135822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.4192135822
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3559569940
Short name T170
Test name
Test status
Simulation time 7052879219 ps
CPU time 63.2 seconds
Started Jun 30 04:46:27 PM PDT 24
Finished Jun 30 04:47:31 PM PDT 24
Peak memory 216912 kb
Host smart-8dbf92e5-a31f-46f8-ab7a-c8c8e474eafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559569940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3559569940
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.819813104
Short name T147
Test name
Test status
Simulation time 8823971160 ps
CPU time 44.32 seconds
Started Jun 30 04:46:27 PM PDT 24
Finished Jun 30 04:47:12 PM PDT 24
Peak memory 217108 kb
Host smart-f4dc5298-efce-4203-aeeb-684a5a180d42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819813104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.819813104
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2238840304
Short name T42
Test name
Test status
Simulation time 56019131118 ps
CPU time 633.46 seconds
Started Jun 30 04:46:36 PM PDT 24
Finished Jun 30 04:57:10 PM PDT 24
Peak memory 234204 kb
Host smart-f604daf5-4a40-4c44-b2a8-c538db338bfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238840304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2238840304
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.886983002
Short name T22
Test name
Test status
Simulation time 14046019654 ps
CPU time 127.82 seconds
Started Jun 30 04:46:37 PM PDT 24
Finished Jun 30 04:48:46 PM PDT 24
Peak memory 238372 kb
Host smart-f27c72db-0a95-4812-9915-dfaf93cc9bba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886983002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.886983002
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2577852801
Short name T148
Test name
Test status
Simulation time 403158900 ps
CPU time 20.1 seconds
Started Jun 30 04:46:36 PM PDT 24
Finished Jun 30 04:46:56 PM PDT 24
Peak memory 216036 kb
Host smart-4fca1c8a-0a81-440e-90b7-289868102e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577852801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2577852801
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1491756942
Short name T212
Test name
Test status
Simulation time 19999175080 ps
CPU time 111.13 seconds
Started Jun 30 04:46:36 PM PDT 24
Finished Jun 30 04:48:28 PM PDT 24
Peak memory 220032 kb
Host smart-7ac08164-9eed-444b-834f-1090a593503d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491756942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1491756942
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.233720941
Short name T324
Test name
Test status
Simulation time 11082607734 ps
CPU time 2469.89 seconds
Started Jun 30 04:46:37 PM PDT 24
Finished Jun 30 05:27:48 PM PDT 24
Peak memory 228288 kb
Host smart-9434b3c7-5738-4341-a5e2-d1348fc199e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233720941 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.233720941
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1574344089
Short name T350
Test name
Test status
Simulation time 688932068 ps
CPU time 8.41 seconds
Started Jun 30 04:46:56 PM PDT 24
Finished Jun 30 04:47:05 PM PDT 24
Peak memory 217048 kb
Host smart-9a50feee-9ffe-4422-8526-4ea3602d1a50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574344089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1574344089
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2258133995
Short name T317
Test name
Test status
Simulation time 7523704963 ps
CPU time 62.87 seconds
Started Jun 30 04:46:58 PM PDT 24
Finished Jun 30 04:48:01 PM PDT 24
Peak memory 219300 kb
Host smart-1c577006-61a3-4d6c-b2d1-443e361bd80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258133995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2258133995
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1039064307
Short name T49
Test name
Test status
Simulation time 1869749808 ps
CPU time 20.75 seconds
Started Jun 30 04:46:57 PM PDT 24
Finished Jun 30 04:47:18 PM PDT 24
Peak memory 211204 kb
Host smart-4905ee4d-073c-4410-b70d-d821c37be8bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1039064307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1039064307
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1500997246
Short name T266
Test name
Test status
Simulation time 363972854 ps
CPU time 20.23 seconds
Started Jun 30 04:46:56 PM PDT 24
Finished Jun 30 04:47:16 PM PDT 24
Peak memory 216224 kb
Host smart-20e34044-5f04-4e0f-89d8-18a7901f79fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500997246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1500997246
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3171250648
Short name T60
Test name
Test status
Simulation time 4970207339 ps
CPU time 54.08 seconds
Started Jun 30 04:46:54 PM PDT 24
Finished Jun 30 04:47:49 PM PDT 24
Peak memory 217264 kb
Host smart-88b2d47a-395d-4e54-af06-0f1c71534954
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171250648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3171250648
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2977762801
Short name T348
Test name
Test status
Simulation time 2054917872 ps
CPU time 14.87 seconds
Started Jun 30 04:47:01 PM PDT 24
Finished Jun 30 04:47:17 PM PDT 24
Peak memory 216916 kb
Host smart-aca9e910-3f1e-4d43-936a-f0ca66cc1507
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977762801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2977762801
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.95033567
Short name T218
Test name
Test status
Simulation time 222135134862 ps
CPU time 317.09 seconds
Started Jun 30 04:47:03 PM PDT 24
Finished Jun 30 04:52:20 PM PDT 24
Peak memory 239192 kb
Host smart-e765b6a4-d54e-4e09-8d68-845f8419ba37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95033567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_co
rrupt_sig_fatal_chk.95033567
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1240855405
Short name T129
Test name
Test status
Simulation time 13011856918 ps
CPU time 61.27 seconds
Started Jun 30 04:47:02 PM PDT 24
Finished Jun 30 04:48:03 PM PDT 24
Peak memory 219364 kb
Host smart-e3b8c002-ae65-417b-a95f-2aed7b8cd470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240855405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1240855405
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1573431850
Short name T164
Test name
Test status
Simulation time 526195938 ps
CPU time 13.42 seconds
Started Jun 30 04:47:09 PM PDT 24
Finished Jun 30 04:47:24 PM PDT 24
Peak memory 219124 kb
Host smart-0eb6c5f8-5ed2-4da0-8d19-d464de6ffb6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1573431850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1573431850
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.1627825792
Short name T120
Test name
Test status
Simulation time 23364068074 ps
CPU time 63.6 seconds
Started Jun 30 04:46:56 PM PDT 24
Finished Jun 30 04:48:00 PM PDT 24
Peak memory 216168 kb
Host smart-aee928e6-ee07-4672-aa11-98746f9fbb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627825792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1627825792
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3010671430
Short name T33
Test name
Test status
Simulation time 34394314853 ps
CPU time 139.58 seconds
Started Jun 30 04:47:02 PM PDT 24
Finished Jun 30 04:49:22 PM PDT 24
Peak memory 220272 kb
Host smart-8529097f-a2e4-4e3b-bd7f-c974b72eb25e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010671430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3010671430
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2060429182
Short name T54
Test name
Test status
Simulation time 28713151203 ps
CPU time 1043.24 seconds
Started Jun 30 04:47:02 PM PDT 24
Finished Jun 30 05:04:26 PM PDT 24
Peak memory 232764 kb
Host smart-889b998c-a59a-42cc-a81a-10d6db41a167
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060429182 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.2060429182
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1393266003
Short name T291
Test name
Test status
Simulation time 3663267814 ps
CPU time 29.08 seconds
Started Jun 30 04:47:10 PM PDT 24
Finished Jun 30 04:47:40 PM PDT 24
Peak memory 217120 kb
Host smart-4b690f58-7fb2-4021-8eaa-3e267b90200c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393266003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1393266003
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2711772538
Short name T132
Test name
Test status
Simulation time 56940399586 ps
CPU time 238.04 seconds
Started Jun 30 04:47:03 PM PDT 24
Finished Jun 30 04:51:01 PM PDT 24
Peak memory 224616 kb
Host smart-b2c2ab75-f4ca-484a-a5aa-f981f19462e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711772538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2711772538
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2785202040
Short name T223
Test name
Test status
Simulation time 688890301 ps
CPU time 18.79 seconds
Started Jun 30 04:47:09 PM PDT 24
Finished Jun 30 04:47:29 PM PDT 24
Peak memory 219128 kb
Host smart-f4ca73be-efab-4492-b01d-8eec27a8b4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785202040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2785202040
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3855863232
Short name T9
Test name
Test status
Simulation time 5327376348 ps
CPU time 24.24 seconds
Started Jun 30 04:47:09 PM PDT 24
Finished Jun 30 04:47:35 PM PDT 24
Peak memory 211588 kb
Host smart-5cd29d37-8782-41f1-a6ad-8ebeb3ae9027
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3855863232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3855863232
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3589521202
Short name T213
Test name
Test status
Simulation time 2923343992 ps
CPU time 38.06 seconds
Started Jun 30 04:47:02 PM PDT 24
Finished Jun 30 04:47:40 PM PDT 24
Peak memory 216236 kb
Host smart-4415c245-b1b8-4824-b710-4e2e493f21d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589521202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3589521202
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3972418239
Short name T3
Test name
Test status
Simulation time 50412038395 ps
CPU time 136.82 seconds
Started Jun 30 04:47:02 PM PDT 24
Finished Jun 30 04:49:20 PM PDT 24
Peak memory 219288 kb
Host smart-c88c48a9-eb3e-4d11-ac0e-2d881f24e6fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972418239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3972418239
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.4266611750
Short name T150
Test name
Test status
Simulation time 7023468651 ps
CPU time 29.35 seconds
Started Jun 30 04:47:09 PM PDT 24
Finished Jun 30 04:47:40 PM PDT 24
Peak memory 217492 kb
Host smart-0dfdc3f7-c3bd-42fc-b251-ab36b2da68b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266611750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.4266611750
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3233070691
Short name T330
Test name
Test status
Simulation time 44825339421 ps
CPU time 465.42 seconds
Started Jun 30 04:47:03 PM PDT 24
Finished Jun 30 04:54:49 PM PDT 24
Peak memory 236848 kb
Host smart-112c9da7-dd71-480e-8e47-dcc20cc6b1db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233070691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3233070691
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3301674031
Short name T311
Test name
Test status
Simulation time 518333862 ps
CPU time 22.02 seconds
Started Jun 30 04:47:09 PM PDT 24
Finished Jun 30 04:47:31 PM PDT 24
Peak memory 219144 kb
Host smart-cca19c6c-80f3-47bc-a4cc-a89508e1daa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301674031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3301674031
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.4258711220
Short name T300
Test name
Test status
Simulation time 7859162692 ps
CPU time 22.74 seconds
Started Jun 30 04:47:09 PM PDT 24
Finished Jun 30 04:47:32 PM PDT 24
Peak memory 217536 kb
Host smart-b46bcc4e-fd4b-4a67-b0ec-1f990244486b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4258711220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.4258711220
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3005943287
Short name T333
Test name
Test status
Simulation time 4278943223 ps
CPU time 51.22 seconds
Started Jun 30 04:47:03 PM PDT 24
Finished Jun 30 04:47:54 PM PDT 24
Peak memory 216228 kb
Host smart-b19ca8e9-75ed-4039-ad66-50b5ded6570d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005943287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3005943287
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2916912120
Short name T183
Test name
Test status
Simulation time 3339115473 ps
CPU time 27.83 seconds
Started Jun 30 04:47:09 PM PDT 24
Finished Jun 30 04:47:38 PM PDT 24
Peak memory 217172 kb
Host smart-a33e39c2-d6f0-40c1-9127-2feac588a15a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916912120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2916912120
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3987661213
Short name T192
Test name
Test status
Simulation time 51858731194 ps
CPU time 585.6 seconds
Started Jun 30 04:47:09 PM PDT 24
Finished Jun 30 04:56:56 PM PDT 24
Peak memory 219448 kb
Host smart-52827528-5125-423d-83b0-fe5784fc7711
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987661213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3987661213
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.4065415593
Short name T149
Test name
Test status
Simulation time 8432203918 ps
CPU time 66.64 seconds
Started Jun 30 04:47:09 PM PDT 24
Finished Jun 30 04:48:16 PM PDT 24
Peak memory 219264 kb
Host smart-2bf32152-e101-4c1f-aad6-ec1f0fdcdb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065415593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.4065415593
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3345746466
Short name T323
Test name
Test status
Simulation time 8929417574 ps
CPU time 18.22 seconds
Started Jun 30 04:47:09 PM PDT 24
Finished Jun 30 04:47:28 PM PDT 24
Peak memory 212000 kb
Host smart-fa233c7f-862b-43bf-969f-1bc992653475
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3345746466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3345746466
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3657974076
Short name T123
Test name
Test status
Simulation time 710601656 ps
CPU time 20.51 seconds
Started Jun 30 04:47:09 PM PDT 24
Finished Jun 30 04:47:30 PM PDT 24
Peak memory 216428 kb
Host smart-021fdb59-68b5-4547-9afa-ef8e1fb5b716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657974076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3657974076
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3855155894
Short name T249
Test name
Test status
Simulation time 1811431686 ps
CPU time 52.75 seconds
Started Jun 30 04:47:09 PM PDT 24
Finished Jun 30 04:48:03 PM PDT 24
Peak memory 219208 kb
Host smart-c1f5b4e7-056f-4aa3-9757-00293e21b221
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855155894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3855155894
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1043171463
Short name T278
Test name
Test status
Simulation time 6567804658 ps
CPU time 27.56 seconds
Started Jun 30 04:47:08 PM PDT 24
Finished Jun 30 04:47:36 PM PDT 24
Peak memory 217512 kb
Host smart-1145a763-b733-4a87-8bc6-77b83a63aee5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043171463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1043171463
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1144386510
Short name T48
Test name
Test status
Simulation time 33502228990 ps
CPU time 408.96 seconds
Started Jun 30 04:47:09 PM PDT 24
Finished Jun 30 04:53:59 PM PDT 24
Peak memory 237144 kb
Host smart-0177aa0f-8ad1-42c0-b6a1-8460e6694d2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144386510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1144386510
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.4090996149
Short name T165
Test name
Test status
Simulation time 23813073211 ps
CPU time 51.84 seconds
Started Jun 30 04:47:09 PM PDT 24
Finished Jun 30 04:48:02 PM PDT 24
Peak memory 219260 kb
Host smart-5e2a60af-e6c7-4372-b79d-166c09887d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090996149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.4090996149
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.535433253
Short name T308
Test name
Test status
Simulation time 720491500 ps
CPU time 10.61 seconds
Started Jun 30 04:47:09 PM PDT 24
Finished Jun 30 04:47:20 PM PDT 24
Peak memory 219176 kb
Host smart-1ab4530f-eaed-4243-afdb-c102b0f8010a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=535433253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.535433253
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.257622060
Short name T161
Test name
Test status
Simulation time 12422346708 ps
CPU time 57.94 seconds
Started Jun 30 04:47:11 PM PDT 24
Finished Jun 30 04:48:09 PM PDT 24
Peak memory 217016 kb
Host smart-ab6476e2-ccbd-47cb-842a-17cca06f3187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257622060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.257622060
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2470709908
Short name T138
Test name
Test status
Simulation time 2532333612 ps
CPU time 11.49 seconds
Started Jun 30 04:47:11 PM PDT 24
Finished Jun 30 04:47:23 PM PDT 24
Peak memory 214696 kb
Host smart-2b13ba9d-8652-4349-a70b-3012265be071
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470709908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2470709908
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1463786566
Short name T25
Test name
Test status
Simulation time 12792499000 ps
CPU time 28.37 seconds
Started Jun 30 04:47:09 PM PDT 24
Finished Jun 30 04:47:38 PM PDT 24
Peak memory 217508 kb
Host smart-1bf268b3-612f-4b90-b621-9f8e809bd470
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463786566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1463786566
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1010319013
Short name T301
Test name
Test status
Simulation time 21375439083 ps
CPU time 243.83 seconds
Started Jun 30 04:47:08 PM PDT 24
Finished Jun 30 04:51:12 PM PDT 24
Peak memory 219164 kb
Host smart-28fd58b2-7ff4-4a7e-81f8-03bb5a7b887a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010319013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1010319013
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.616470933
Short name T295
Test name
Test status
Simulation time 9290391410 ps
CPU time 68.86 seconds
Started Jun 30 04:47:10 PM PDT 24
Finished Jun 30 04:48:20 PM PDT 24
Peak memory 219248 kb
Host smart-0883bcc2-fae0-4655-b178-b3f5201acfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616470933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.616470933
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1074770166
Short name T264
Test name
Test status
Simulation time 3668861647 ps
CPU time 29.9 seconds
Started Jun 30 04:47:11 PM PDT 24
Finished Jun 30 04:47:41 PM PDT 24
Peak memory 219212 kb
Host smart-f75aefd2-110c-440a-9c6c-4ccc85bddb0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1074770166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1074770166
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.4188019178
Short name T158
Test name
Test status
Simulation time 34284717804 ps
CPU time 84.22 seconds
Started Jun 30 04:47:10 PM PDT 24
Finished Jun 30 04:48:35 PM PDT 24
Peak memory 217164 kb
Host smart-3f4f773b-61e3-479b-a540-f6d73c0a0283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188019178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.4188019178
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2568878258
Short name T302
Test name
Test status
Simulation time 1351528161 ps
CPU time 42.69 seconds
Started Jun 30 04:47:09 PM PDT 24
Finished Jun 30 04:47:53 PM PDT 24
Peak memory 219220 kb
Host smart-b607ae91-1cf9-45ce-afac-4b0ea43a4e00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568878258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2568878258
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2033048508
Short name T31
Test name
Test status
Simulation time 3598387161 ps
CPU time 30.39 seconds
Started Jun 30 04:47:18 PM PDT 24
Finished Jun 30 04:47:49 PM PDT 24
Peak memory 217108 kb
Host smart-48399338-eade-44b7-a0f3-750dedf419bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033048508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2033048508
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.861577827
Short name T184
Test name
Test status
Simulation time 248518581966 ps
CPU time 789.35 seconds
Started Jun 30 04:47:10 PM PDT 24
Finished Jun 30 05:00:20 PM PDT 24
Peak memory 234096 kb
Host smart-30c5fe01-0553-4deb-b2fc-14eab0b9797d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861577827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.861577827
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2741362802
Short name T128
Test name
Test status
Simulation time 170409091159 ps
CPU time 72.55 seconds
Started Jun 30 04:47:18 PM PDT 24
Finished Jun 30 04:48:31 PM PDT 24
Peak memory 219256 kb
Host smart-348fc060-bf92-4570-9d49-3f628cb6718b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741362802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2741362802
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.7169688
Short name T220
Test name
Test status
Simulation time 178410941 ps
CPU time 10.24 seconds
Started Jun 30 04:47:10 PM PDT 24
Finished Jun 30 04:47:21 PM PDT 24
Peak memory 219188 kb
Host smart-42462240-e53d-47c8-bc2e-22d370806923
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=7169688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.7169688
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2937480107
Short name T297
Test name
Test status
Simulation time 24390108012 ps
CPU time 60.43 seconds
Started Jun 30 04:47:09 PM PDT 24
Finished Jun 30 04:48:11 PM PDT 24
Peak memory 215808 kb
Host smart-2b0a9636-25fc-48c3-9716-e57be54d4b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937480107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2937480107
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3486090073
Short name T136
Test name
Test status
Simulation time 47355034537 ps
CPU time 130.27 seconds
Started Jun 30 04:47:09 PM PDT 24
Finished Jun 30 04:49:20 PM PDT 24
Peak memory 219280 kb
Host smart-f9d8f44e-2b0b-4f10-985d-968ac56edb4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486090073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3486090073
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2136811420
Short name T141
Test name
Test status
Simulation time 167330388 ps
CPU time 8.4 seconds
Started Jun 30 04:47:18 PM PDT 24
Finished Jun 30 04:47:27 PM PDT 24
Peak memory 217144 kb
Host smart-4fb7cf6c-ef9a-4d59-81b6-5b8631a6d289
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136811420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2136811420
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.659164209
Short name T235
Test name
Test status
Simulation time 297887903115 ps
CPU time 548.78 seconds
Started Jun 30 04:47:17 PM PDT 24
Finished Jun 30 04:56:26 PM PDT 24
Peak memory 238644 kb
Host smart-f3e3310a-615a-4ddc-bd1c-b6777fac0c90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659164209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.659164209
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.469856677
Short name T228
Test name
Test status
Simulation time 2058286532 ps
CPU time 22.56 seconds
Started Jun 30 04:47:16 PM PDT 24
Finished Jun 30 04:47:38 PM PDT 24
Peak memory 219240 kb
Host smart-77f0954e-2449-42a5-a04f-423b6fc64d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469856677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.469856677
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1352021935
Short name T159
Test name
Test status
Simulation time 762922629 ps
CPU time 10.18 seconds
Started Jun 30 04:47:15 PM PDT 24
Finished Jun 30 04:47:25 PM PDT 24
Peak memory 219280 kb
Host smart-941df970-f726-4c73-954b-b080786ca244
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1352021935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1352021935
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2229896949
Short name T190
Test name
Test status
Simulation time 6748768119 ps
CPU time 56.84 seconds
Started Jun 30 04:47:17 PM PDT 24
Finished Jun 30 04:48:14 PM PDT 24
Peak memory 216700 kb
Host smart-a5a70c54-c35c-4a8b-ae14-2963627d1604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229896949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2229896949
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1383887212
Short name T182
Test name
Test status
Simulation time 13099337900 ps
CPU time 36.87 seconds
Started Jun 30 04:47:18 PM PDT 24
Finished Jun 30 04:47:55 PM PDT 24
Peak memory 214592 kb
Host smart-6759f36b-215b-4d76-b3f9-335ee181c69e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383887212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1383887212
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2005961431
Short name T344
Test name
Test status
Simulation time 6316959261 ps
CPU time 32.5 seconds
Started Jun 30 04:47:24 PM PDT 24
Finished Jun 30 04:47:57 PM PDT 24
Peak memory 217212 kb
Host smart-6aa6fcc2-f336-4612-92a0-202f31a535bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005961431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2005961431
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3830840917
Short name T252
Test name
Test status
Simulation time 22951016382 ps
CPU time 228.54 seconds
Started Jun 30 04:47:16 PM PDT 24
Finished Jun 30 04:51:05 PM PDT 24
Peak memory 238676 kb
Host smart-3fcb3dd4-957e-48b0-99f1-34e2c91418ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830840917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3830840917
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.731512658
Short name T133
Test name
Test status
Simulation time 144076656327 ps
CPU time 63.12 seconds
Started Jun 30 04:47:16 PM PDT 24
Finished Jun 30 04:48:20 PM PDT 24
Peak memory 219300 kb
Host smart-11544706-5cde-4412-8901-260b45412ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731512658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.731512658
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3549764333
Short name T100
Test name
Test status
Simulation time 2654973915 ps
CPU time 14.58 seconds
Started Jun 30 04:47:17 PM PDT 24
Finished Jun 30 04:47:32 PM PDT 24
Peak memory 218700 kb
Host smart-2121453b-5595-47e8-b2eb-8295da3c25bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3549764333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3549764333
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1379777190
Short name T246
Test name
Test status
Simulation time 4112758575 ps
CPU time 44.86 seconds
Started Jun 30 04:47:16 PM PDT 24
Finished Jun 30 04:48:01 PM PDT 24
Peak memory 216300 kb
Host smart-54f7a66a-57b6-4dce-8340-eef93b135085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379777190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1379777190
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.322038724
Short name T283
Test name
Test status
Simulation time 47953013275 ps
CPU time 119.82 seconds
Started Jun 30 04:47:19 PM PDT 24
Finished Jun 30 04:49:19 PM PDT 24
Peak memory 221000 kb
Host smart-674fd3a9-bfc3-4dbe-949a-b9a00a74e57b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322038724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.322038724
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1089058260
Short name T153
Test name
Test status
Simulation time 2226817913 ps
CPU time 21.24 seconds
Started Jun 30 04:46:42 PM PDT 24
Finished Jun 30 04:47:04 PM PDT 24
Peak memory 217108 kb
Host smart-036a8b5e-8997-41d0-9db1-bc0ae2703899
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089058260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1089058260
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3922239370
Short name T199
Test name
Test status
Simulation time 12132576631 ps
CPU time 188.58 seconds
Started Jun 30 04:46:35 PM PDT 24
Finished Jun 30 04:49:44 PM PDT 24
Peak memory 233920 kb
Host smart-25768a93-7e77-41a5-aa70-7407b4de3267
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922239370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3922239370
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2936336483
Short name T327
Test name
Test status
Simulation time 4640181214 ps
CPU time 46.04 seconds
Started Jun 30 04:46:36 PM PDT 24
Finished Jun 30 04:47:22 PM PDT 24
Peak memory 219284 kb
Host smart-b989803d-12ce-45b2-a0b1-cd48eb94256a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936336483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2936336483
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2454768712
Short name T126
Test name
Test status
Simulation time 2061690339 ps
CPU time 22.37 seconds
Started Jun 30 04:46:34 PM PDT 24
Finished Jun 30 04:46:57 PM PDT 24
Peak memory 219228 kb
Host smart-5db1f8f2-dec6-4cb6-a35a-54995f6c6c9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2454768712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2454768712
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2880307714
Short name T29
Test name
Test status
Simulation time 298969089 ps
CPU time 120.28 seconds
Started Jun 30 04:46:38 PM PDT 24
Finished Jun 30 04:48:38 PM PDT 24
Peak memory 235224 kb
Host smart-423f56b3-d53b-41c2-ae05-cf276e2204ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880307714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2880307714
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3015577749
Short name T46
Test name
Test status
Simulation time 4805915739 ps
CPU time 32.04 seconds
Started Jun 30 04:46:36 PM PDT 24
Finished Jun 30 04:47:09 PM PDT 24
Peak memory 216516 kb
Host smart-7317c6d5-831a-428c-8cc7-22f8c79a928c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015577749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3015577749
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.222827843
Short name T168
Test name
Test status
Simulation time 27217548081 ps
CPU time 104.74 seconds
Started Jun 30 04:46:37 PM PDT 24
Finished Jun 30 04:48:22 PM PDT 24
Peak memory 219256 kb
Host smart-6335bb45-8d66-4bf9-80df-3e66b55b24f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222827843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.222827843
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1301809840
Short name T56
Test name
Test status
Simulation time 43442449292 ps
CPU time 1600.52 seconds
Started Jun 30 04:46:38 PM PDT 24
Finished Jun 30 05:13:19 PM PDT 24
Peak memory 235808 kb
Host smart-d3be3764-d136-44d8-9a67-19475b092923
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301809840 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.1301809840
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1638982261
Short name T325
Test name
Test status
Simulation time 718509440 ps
CPU time 8.28 seconds
Started Jun 30 04:47:23 PM PDT 24
Finished Jun 30 04:47:32 PM PDT 24
Peak memory 216996 kb
Host smart-8408076d-7d17-40dd-9ced-f428e64e99e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638982261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1638982261
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.370138648
Short name T237
Test name
Test status
Simulation time 33055977522 ps
CPU time 381.78 seconds
Started Jun 30 04:47:23 PM PDT 24
Finished Jun 30 04:53:46 PM PDT 24
Peak memory 229812 kb
Host smart-08be010c-c1a7-477d-9b4a-19527cecef76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370138648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.370138648
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.598664584
Short name T290
Test name
Test status
Simulation time 4429469203 ps
CPU time 34.39 seconds
Started Jun 30 04:47:24 PM PDT 24
Finished Jun 30 04:47:59 PM PDT 24
Peak memory 219268 kb
Host smart-feb30b27-e0cc-4586-8612-253d693a3680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598664584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.598664584
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2765949120
Short name T231
Test name
Test status
Simulation time 187028637 ps
CPU time 10.61 seconds
Started Jun 30 04:47:22 PM PDT 24
Finished Jun 30 04:47:33 PM PDT 24
Peak memory 219220 kb
Host smart-5c66ecf6-bb39-48e6-93bf-7f371a98cc62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2765949120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2765949120
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2078068425
Short name T236
Test name
Test status
Simulation time 16667684759 ps
CPU time 77.92 seconds
Started Jun 30 04:47:24 PM PDT 24
Finished Jun 30 04:48:42 PM PDT 24
Peak memory 216564 kb
Host smart-b3ee62f5-6abb-47e6-8995-5c110834f0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078068425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2078068425
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.537534041
Short name T180
Test name
Test status
Simulation time 167791374 ps
CPU time 8.55 seconds
Started Jun 30 04:47:30 PM PDT 24
Finished Jun 30 04:47:38 PM PDT 24
Peak memory 217068 kb
Host smart-61e7843c-944a-4602-9334-f5dee4f9153d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537534041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.537534041
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.85909559
Short name T225
Test name
Test status
Simulation time 56554790312 ps
CPU time 304.61 seconds
Started Jun 30 04:47:23 PM PDT 24
Finished Jun 30 04:52:28 PM PDT 24
Peak memory 226008 kb
Host smart-989e561b-4efb-48f6-a52b-cbd595f55500
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85909559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_co
rrupt_sig_fatal_chk.85909559
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.146292997
Short name T135
Test name
Test status
Simulation time 11373208692 ps
CPU time 51.64 seconds
Started Jun 30 04:47:23 PM PDT 24
Finished Jun 30 04:48:15 PM PDT 24
Peak memory 219328 kb
Host smart-4f226652-a33c-4946-8303-8616c38a56a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146292997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.146292997
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1937721559
Short name T30
Test name
Test status
Simulation time 15295539438 ps
CPU time 24.06 seconds
Started Jun 30 04:47:23 PM PDT 24
Finished Jun 30 04:47:48 PM PDT 24
Peak memory 219256 kb
Host smart-729564f8-7eca-4cc9-aa01-350492f78b91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1937721559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1937721559
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2649148962
Short name T121
Test name
Test status
Simulation time 20496020862 ps
CPU time 48.34 seconds
Started Jun 30 04:47:23 PM PDT 24
Finished Jun 30 04:48:12 PM PDT 24
Peak memory 216824 kb
Host smart-30671041-6376-4feb-8eea-ecc7c0799757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649148962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2649148962
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3464492477
Short name T336
Test name
Test status
Simulation time 6347820942 ps
CPU time 97.22 seconds
Started Jun 30 04:47:23 PM PDT 24
Finished Jun 30 04:49:01 PM PDT 24
Peak memory 221644 kb
Host smart-9560caef-e3c7-44bb-b38a-ab8d3b2a2a99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464492477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3464492477
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.3886249369
Short name T14
Test name
Test status
Simulation time 174269202063 ps
CPU time 1667.91 seconds
Started Jun 30 04:47:31 PM PDT 24
Finished Jun 30 05:15:20 PM PDT 24
Peak memory 243912 kb
Host smart-ba51034b-f7fa-4a91-a884-2f2c7fb2d655
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886249369 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.3886249369
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.691047852
Short name T204
Test name
Test status
Simulation time 22792563715 ps
CPU time 20.96 seconds
Started Jun 30 04:47:31 PM PDT 24
Finished Jun 30 04:47:52 PM PDT 24
Peak memory 217420 kb
Host smart-0880b9cf-5316-482f-8b25-147dcf6809bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691047852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.691047852
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.106888562
Short name T313
Test name
Test status
Simulation time 261938276378 ps
CPU time 450.24 seconds
Started Jun 30 04:47:29 PM PDT 24
Finished Jun 30 04:55:00 PM PDT 24
Peak memory 235748 kb
Host smart-eb89a6da-33e8-4de0-9cd6-308d584fa007
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106888562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.106888562
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.354466328
Short name T279
Test name
Test status
Simulation time 3144201187 ps
CPU time 38.24 seconds
Started Jun 30 04:47:30 PM PDT 24
Finished Jun 30 04:48:08 PM PDT 24
Peak memory 219248 kb
Host smart-c9617b52-19be-4858-a469-dc8e115acb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354466328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.354466328
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3031119539
Short name T224
Test name
Test status
Simulation time 3767727602 ps
CPU time 15.43 seconds
Started Jun 30 04:47:31 PM PDT 24
Finished Jun 30 04:47:47 PM PDT 24
Peak memory 219268 kb
Host smart-f120f922-ab2e-4b17-9fd1-9fba03b0150c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3031119539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3031119539
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.3694972576
Short name T11
Test name
Test status
Simulation time 2977839812 ps
CPU time 43.92 seconds
Started Jun 30 04:47:32 PM PDT 24
Finished Jun 30 04:48:16 PM PDT 24
Peak memory 216796 kb
Host smart-fc1778e2-c42f-49d4-90a3-c94c917d0d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694972576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.3694972576
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3050565875
Short name T118
Test name
Test status
Simulation time 3276462246 ps
CPU time 45.01 seconds
Started Jun 30 04:47:32 PM PDT 24
Finished Jun 30 04:48:17 PM PDT 24
Peak memory 216016 kb
Host smart-3661959b-e277-4539-a0fd-d3982cd485f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050565875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3050565875
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3550390221
Short name T286
Test name
Test status
Simulation time 14446108627 ps
CPU time 31.39 seconds
Started Jun 30 04:47:32 PM PDT 24
Finished Jun 30 04:48:04 PM PDT 24
Peak memory 217472 kb
Host smart-1e2fc504-fe2c-4b2e-a4d7-28211f83c095
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550390221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3550390221
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3809643217
Short name T339
Test name
Test status
Simulation time 241123756945 ps
CPU time 439.82 seconds
Started Jun 30 04:47:31 PM PDT 24
Finished Jun 30 04:54:51 PM PDT 24
Peak memory 237992 kb
Host smart-2bdfa659-1a5a-4972-a8a6-34471a527a51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809643217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3809643217
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.632485818
Short name T245
Test name
Test status
Simulation time 2385007568 ps
CPU time 33.54 seconds
Started Jun 30 04:47:32 PM PDT 24
Finished Jun 30 04:48:06 PM PDT 24
Peak memory 219304 kb
Host smart-8f9eb873-9b5e-49c8-991f-fbcf5109cfcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632485818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.632485818
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1574854271
Short name T130
Test name
Test status
Simulation time 16874394199 ps
CPU time 31.27 seconds
Started Jun 30 04:47:33 PM PDT 24
Finished Jun 30 04:48:05 PM PDT 24
Peak memory 211824 kb
Host smart-ac2ea0e4-be9f-4c30-b972-f832ccd4ac48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1574854271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1574854271
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2647223310
Short name T208
Test name
Test status
Simulation time 6329815304 ps
CPU time 63.84 seconds
Started Jun 30 04:47:30 PM PDT 24
Finished Jun 30 04:48:34 PM PDT 24
Peak memory 216684 kb
Host smart-4711d345-e0db-4a75-913d-c0a127f3b3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647223310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2647223310
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3436293560
Short name T18
Test name
Test status
Simulation time 402436786 ps
CPU time 25.12 seconds
Started Jun 30 04:47:32 PM PDT 24
Finished Jun 30 04:47:57 PM PDT 24
Peak memory 217224 kb
Host smart-88d1046b-c530-422b-b947-97ee848c927e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436293560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3436293560
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3226511239
Short name T281
Test name
Test status
Simulation time 167669237 ps
CPU time 8.4 seconds
Started Jun 30 04:47:31 PM PDT 24
Finished Jun 30 04:47:40 PM PDT 24
Peak memory 218156 kb
Host smart-c5fc4609-e546-4410-a1b2-7c5e0e1732cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226511239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3226511239
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.723198207
Short name T195
Test name
Test status
Simulation time 9336454876 ps
CPU time 157.58 seconds
Started Jun 30 04:47:31 PM PDT 24
Finished Jun 30 04:50:09 PM PDT 24
Peak memory 238012 kb
Host smart-37638a5a-68be-4b6b-8717-bf7cb7c2739a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723198207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.723198207
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1177198225
Short name T338
Test name
Test status
Simulation time 78758511362 ps
CPU time 63.52 seconds
Started Jun 30 04:47:30 PM PDT 24
Finished Jun 30 04:48:34 PM PDT 24
Peak memory 219288 kb
Host smart-adf7adc7-7da4-44b7-9558-d0f7ab98b496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177198225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1177198225
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3847118066
Short name T294
Test name
Test status
Simulation time 6921621960 ps
CPU time 15.92 seconds
Started Jun 30 04:47:34 PM PDT 24
Finished Jun 30 04:47:50 PM PDT 24
Peak memory 211964 kb
Host smart-ed0a6085-9f87-454f-acaa-909c22e9597c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3847118066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3847118066
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.945734753
Short name T45
Test name
Test status
Simulation time 6417460811 ps
CPU time 64.73 seconds
Started Jun 30 04:47:32 PM PDT 24
Finished Jun 30 04:48:37 PM PDT 24
Peak memory 216608 kb
Host smart-62bf4772-5b0a-460b-bf21-06c73ce48c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945734753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.945734753
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2942181168
Short name T156
Test name
Test status
Simulation time 1352858950 ps
CPU time 20.37 seconds
Started Jun 30 04:47:31 PM PDT 24
Finished Jun 30 04:47:52 PM PDT 24
Peak memory 218608 kb
Host smart-dd1227a6-6b86-4912-8255-081e02b2d7ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942181168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2942181168
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.4196013406
Short name T55
Test name
Test status
Simulation time 48881838561 ps
CPU time 1842.62 seconds
Started Jun 30 04:47:31 PM PDT 24
Finished Jun 30 05:18:15 PM PDT 24
Peak memory 236092 kb
Host smart-674ff856-8cc1-453d-975c-02eb5e08d1ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196013406 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.4196013406
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.4101144199
Short name T166
Test name
Test status
Simulation time 10670543709 ps
CPU time 23.42 seconds
Started Jun 30 04:47:37 PM PDT 24
Finished Jun 30 04:48:01 PM PDT 24
Peak memory 217372 kb
Host smart-ca80fd08-63af-4447-b105-df8904a6ac8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101144199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.4101144199
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1541742625
Short name T340
Test name
Test status
Simulation time 25579603364 ps
CPU time 404.45 seconds
Started Jun 30 04:47:39 PM PDT 24
Finished Jun 30 04:54:24 PM PDT 24
Peak memory 233848 kb
Host smart-bad33373-0bad-40f4-8599-b8b61c7ba038
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541742625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1541742625
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.339432963
Short name T143
Test name
Test status
Simulation time 55285141231 ps
CPU time 47.5 seconds
Started Jun 30 04:47:38 PM PDT 24
Finished Jun 30 04:48:26 PM PDT 24
Peak memory 219216 kb
Host smart-fa5bde13-d5eb-4832-b670-da4d0a1fbc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339432963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.339432963
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2115208809
Short name T298
Test name
Test status
Simulation time 3544667491 ps
CPU time 30.29 seconds
Started Jun 30 04:47:38 PM PDT 24
Finished Jun 30 04:48:09 PM PDT 24
Peak memory 219304 kb
Host smart-cf40f135-9515-4c04-9db3-d7fe132647a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2115208809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2115208809
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.256753516
Short name T250
Test name
Test status
Simulation time 9049414211 ps
CPU time 59.09 seconds
Started Jun 30 04:47:38 PM PDT 24
Finished Jun 30 04:48:37 PM PDT 24
Peak memory 217368 kb
Host smart-efa5247f-79cf-4064-b1da-ef105b9e04ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256753516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.256753516
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.308230413
Short name T329
Test name
Test status
Simulation time 1026844032 ps
CPU time 17.46 seconds
Started Jun 30 04:47:38 PM PDT 24
Finished Jun 30 04:47:56 PM PDT 24
Peak memory 218932 kb
Host smart-98de143c-6f34-439b-9ad6-c087c592b5e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308230413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.308230413
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.873366014
Short name T242
Test name
Test status
Simulation time 662101686 ps
CPU time 8.17 seconds
Started Jun 30 04:47:38 PM PDT 24
Finished Jun 30 04:47:47 PM PDT 24
Peak memory 216992 kb
Host smart-1e01488c-5215-4cab-8630-f4adb81ca312
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873366014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.873366014
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.59098732
Short name T282
Test name
Test status
Simulation time 59275760436 ps
CPU time 354.23 seconds
Started Jun 30 04:47:38 PM PDT 24
Finished Jun 30 04:53:33 PM PDT 24
Peak memory 225444 kb
Host smart-5d795d4e-5b00-4a39-a7a0-fba79e0aaa54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59098732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_co
rrupt_sig_fatal_chk.59098732
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.452179254
Short name T277
Test name
Test status
Simulation time 7585096923 ps
CPU time 59.94 seconds
Started Jun 30 04:47:38 PM PDT 24
Finished Jun 30 04:48:38 PM PDT 24
Peak memory 219240 kb
Host smart-4aba8e53-9731-4b85-bd97-bfefd1942705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452179254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.452179254
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1426305048
Short name T19
Test name
Test status
Simulation time 4541202924 ps
CPU time 23.27 seconds
Started Jun 30 04:47:37 PM PDT 24
Finished Jun 30 04:48:00 PM PDT 24
Peak memory 211824 kb
Host smart-92186511-a793-44eb-a64d-a1efab71bc03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1426305048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1426305048
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3051716737
Short name T287
Test name
Test status
Simulation time 6727133781 ps
CPU time 41.49 seconds
Started Jun 30 04:47:37 PM PDT 24
Finished Jun 30 04:48:19 PM PDT 24
Peak memory 216752 kb
Host smart-99189512-bb10-482a-b4b7-05ed04bee6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051716737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3051716737
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.227118849
Short name T254
Test name
Test status
Simulation time 174533976 ps
CPU time 8.4 seconds
Started Jun 30 04:47:46 PM PDT 24
Finished Jun 30 04:47:55 PM PDT 24
Peak memory 217220 kb
Host smart-b5c5da55-9ac5-445f-8ac1-8eace540ac0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227118849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.227118849
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.4028004784
Short name T288
Test name
Test status
Simulation time 87651248110 ps
CPU time 437.22 seconds
Started Jun 30 04:47:45 PM PDT 24
Finished Jun 30 04:55:03 PM PDT 24
Peak memory 217944 kb
Host smart-970ab2bd-1f7d-4911-9610-8e0cbc762b00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028004784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.4028004784
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1087248253
Short name T306
Test name
Test status
Simulation time 28567979109 ps
CPU time 67.36 seconds
Started Jun 30 04:47:47 PM PDT 24
Finished Jun 30 04:48:55 PM PDT 24
Peak memory 219112 kb
Host smart-7238b0d2-f410-45c3-834d-7e6591f00752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087248253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1087248253
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1145386159
Short name T134
Test name
Test status
Simulation time 4287371907 ps
CPU time 23.53 seconds
Started Jun 30 04:47:45 PM PDT 24
Finished Jun 30 04:48:09 PM PDT 24
Peak memory 219204 kb
Host smart-4cbb2f1d-b572-4fd2-a531-f968b441fdec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1145386159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1145386159
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2039974049
Short name T273
Test name
Test status
Simulation time 10427216006 ps
CPU time 66.18 seconds
Started Jun 30 04:47:38 PM PDT 24
Finished Jun 30 04:48:45 PM PDT 24
Peak memory 216736 kb
Host smart-bd0f56b9-6e5a-4b1f-8a8c-1a77da7e6f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039974049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2039974049
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.687641967
Short name T310
Test name
Test status
Simulation time 6033738023 ps
CPU time 30.68 seconds
Started Jun 30 04:47:46 PM PDT 24
Finished Jun 30 04:48:17 PM PDT 24
Peak memory 219312 kb
Host smart-74be3cb0-ca06-4241-9df7-59a3f6fe9f1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687641967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.687641967
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.604376681
Short name T358
Test name
Test status
Simulation time 31029391552 ps
CPU time 8521.66 seconds
Started Jun 30 04:47:46 PM PDT 24
Finished Jun 30 07:09:49 PM PDT 24
Peak memory 235480 kb
Host smart-d54b8bfa-d95c-4290-b85f-53a8410f0b58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604376681 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.604376681
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.810431738
Short name T318
Test name
Test status
Simulation time 1016281387 ps
CPU time 15.29 seconds
Started Jun 30 04:47:46 PM PDT 24
Finished Jun 30 04:48:02 PM PDT 24
Peak memory 217000 kb
Host smart-25e5e3f6-bebf-463a-bacd-6ba8e0f8dd1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810431738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.810431738
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.833972093
Short name T217
Test name
Test status
Simulation time 39831495987 ps
CPU time 553.7 seconds
Started Jun 30 04:47:48 PM PDT 24
Finished Jun 30 04:57:02 PM PDT 24
Peak memory 234324 kb
Host smart-ce32e02e-8909-4b98-a16d-ff61616e11c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833972093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.833972093
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3474491675
Short name T155
Test name
Test status
Simulation time 21461165213 ps
CPU time 50.83 seconds
Started Jun 30 04:47:46 PM PDT 24
Finished Jun 30 04:48:38 PM PDT 24
Peak memory 219220 kb
Host smart-c7b6e0d4-6b55-4a26-a6d6-8722cfb2d12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474491675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3474491675
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3129010642
Short name T289
Test name
Test status
Simulation time 674428856 ps
CPU time 12.68 seconds
Started Jun 30 04:47:45 PM PDT 24
Finished Jun 30 04:47:59 PM PDT 24
Peak memory 211032 kb
Host smart-86cac0c4-de02-45f8-b723-0de61d9508bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3129010642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3129010642
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2541466511
Short name T216
Test name
Test status
Simulation time 351355473 ps
CPU time 20.09 seconds
Started Jun 30 04:47:46 PM PDT 24
Finished Jun 30 04:48:07 PM PDT 24
Peak memory 216352 kb
Host smart-e2f46047-46cc-4976-b862-02f3aa65a701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541466511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2541466511
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3923043410
Short name T142
Test name
Test status
Simulation time 7477118400 ps
CPU time 55.58 seconds
Started Jun 30 04:47:45 PM PDT 24
Finished Jun 30 04:48:41 PM PDT 24
Peak memory 219224 kb
Host smart-797e8b45-36da-465f-9821-4705fc3d28ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923043410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3923043410
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.28267009
Short name T52
Test name
Test status
Simulation time 222747681094 ps
CPU time 1963.75 seconds
Started Jun 30 04:47:47 PM PDT 24
Finished Jun 30 05:20:31 PM PDT 24
Peak memory 238064 kb
Host smart-1245410d-75bd-4479-a051-09ab2e4c05f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28267009 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.28267009
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3699668453
Short name T309
Test name
Test status
Simulation time 13504872115 ps
CPU time 27.85 seconds
Started Jun 30 04:47:45 PM PDT 24
Finished Jun 30 04:48:14 PM PDT 24
Peak memory 217476 kb
Host smart-a8d54355-d2b7-4062-b853-47f022fe2f38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699668453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3699668453
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3347590537
Short name T257
Test name
Test status
Simulation time 34407982725 ps
CPU time 276.46 seconds
Started Jun 30 04:47:45 PM PDT 24
Finished Jun 30 04:52:22 PM PDT 24
Peak memory 218208 kb
Host smart-0fee9aea-a69a-4355-8f92-cf79cdfd5d29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347590537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3347590537
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1949916611
Short name T34
Test name
Test status
Simulation time 9179899847 ps
CPU time 34.94 seconds
Started Jun 30 04:47:46 PM PDT 24
Finished Jun 30 04:48:22 PM PDT 24
Peak memory 219200 kb
Host smart-0a6f4b44-83a5-4ea3-9007-d60ad6dd03bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949916611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1949916611
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2067283944
Short name T191
Test name
Test status
Simulation time 4290973092 ps
CPU time 21.99 seconds
Started Jun 30 04:47:46 PM PDT 24
Finished Jun 30 04:48:09 PM PDT 24
Peak memory 219276 kb
Host smart-6a115b80-1b77-4f54-9ff7-032e5f7e5ab5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2067283944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2067283944
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.720604784
Short name T241
Test name
Test status
Simulation time 3771399031 ps
CPU time 42.26 seconds
Started Jun 30 04:47:45 PM PDT 24
Finished Jun 30 04:48:28 PM PDT 24
Peak memory 216228 kb
Host smart-22575812-8064-4e4f-946c-8010dbbd76a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720604784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.720604784
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.981978303
Short name T81
Test name
Test status
Simulation time 5435026631 ps
CPU time 66.92 seconds
Started Jun 30 04:47:46 PM PDT 24
Finished Jun 30 04:48:54 PM PDT 24
Peak memory 219240 kb
Host smart-edddb7bc-8643-41de-9b23-1ca348274f36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981978303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.981978303
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.4047907504
Short name T70
Test name
Test status
Simulation time 177849361 ps
CPU time 8.35 seconds
Started Jun 30 04:46:41 PM PDT 24
Finished Jun 30 04:46:50 PM PDT 24
Peak memory 217092 kb
Host smart-4e97a3f2-604b-475a-8d4e-737be808b834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047907504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.4047907504
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1789776508
Short name T262
Test name
Test status
Simulation time 221133866383 ps
CPU time 1086.84 seconds
Started Jun 30 04:46:39 PM PDT 24
Finished Jun 30 05:04:47 PM PDT 24
Peak memory 226912 kb
Host smart-31ca501f-2028-4b24-9aca-8337234e828e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789776508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1789776508
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3765890065
Short name T284
Test name
Test status
Simulation time 1028247876 ps
CPU time 26.97 seconds
Started Jun 30 04:46:43 PM PDT 24
Finished Jun 30 04:47:11 PM PDT 24
Peak memory 219276 kb
Host smart-88071306-13db-4104-bf28-d9638a2be4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765890065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3765890065
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3628019931
Short name T238
Test name
Test status
Simulation time 4209499687 ps
CPU time 34.05 seconds
Started Jun 30 04:46:44 PM PDT 24
Finished Jun 30 04:47:19 PM PDT 24
Peak memory 219240 kb
Host smart-1ea35f8a-b903-4935-99bf-3e82907c19c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3628019931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3628019931
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2005482819
Short name T272
Test name
Test status
Simulation time 14230631037 ps
CPU time 39.95 seconds
Started Jun 30 04:46:41 PM PDT 24
Finished Jun 30 04:47:22 PM PDT 24
Peak memory 215804 kb
Host smart-656c6ebc-8e98-4a3b-8586-f897ad32b1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005482819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2005482819
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1568877171
Short name T117
Test name
Test status
Simulation time 1799041338 ps
CPU time 49.42 seconds
Started Jun 30 04:46:41 PM PDT 24
Finished Jun 30 04:47:31 PM PDT 24
Peak memory 219244 kb
Host smart-34e3fe5e-2680-4433-9759-cb37abf4ee34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568877171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1568877171
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3695231663
Short name T196
Test name
Test status
Simulation time 661163688 ps
CPU time 8.38 seconds
Started Jun 30 04:47:56 PM PDT 24
Finished Jun 30 04:48:05 PM PDT 24
Peak memory 217148 kb
Host smart-dd7f49ec-00f0-4430-b8ce-c5c11be883d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695231663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3695231663
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1729322256
Short name T39
Test name
Test status
Simulation time 5524853601 ps
CPU time 207.99 seconds
Started Jun 30 04:47:48 PM PDT 24
Finished Jun 30 04:51:16 PM PDT 24
Peak memory 216904 kb
Host smart-bbadbe45-512c-483e-b951-8bdbcbcbfab8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729322256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1729322256
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1912922196
Short name T167
Test name
Test status
Simulation time 2133693092 ps
CPU time 33.09 seconds
Started Jun 30 04:47:57 PM PDT 24
Finished Jun 30 04:48:31 PM PDT 24
Peak memory 219216 kb
Host smart-6f43847c-8c79-4813-9a79-67efe61ba72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912922196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1912922196
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1649166256
Short name T219
Test name
Test status
Simulation time 7984875245 ps
CPU time 33.03 seconds
Started Jun 30 04:47:46 PM PDT 24
Finished Jun 30 04:48:20 PM PDT 24
Peak memory 219344 kb
Host smart-09eb8781-1d19-472e-ba47-b378e59f6c61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1649166256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1649166256
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3677809670
Short name T207
Test name
Test status
Simulation time 3992558886 ps
CPU time 28.79 seconds
Started Jun 30 04:47:47 PM PDT 24
Finished Jun 30 04:48:16 PM PDT 24
Peak memory 215644 kb
Host smart-416aae2a-f43d-4997-9722-3b3b78786380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677809670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3677809670
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3285743964
Short name T35
Test name
Test status
Simulation time 13306224437 ps
CPU time 29.05 seconds
Started Jun 30 04:47:47 PM PDT 24
Finished Jun 30 04:48:16 PM PDT 24
Peak memory 214472 kb
Host smart-766de7b2-fef0-4399-90d9-a2b6bec7e204
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285743964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3285743964
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.566544460
Short name T259
Test name
Test status
Simulation time 931908269 ps
CPU time 14.48 seconds
Started Jun 30 04:47:56 PM PDT 24
Finished Jun 30 04:48:11 PM PDT 24
Peak memory 217004 kb
Host smart-d2ef81b2-8a67-4b0d-8306-9fbe05695b3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566544460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.566544460
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.67937552
Short name T326
Test name
Test status
Simulation time 101007030233 ps
CPU time 1018.93 seconds
Started Jun 30 04:47:56 PM PDT 24
Finished Jun 30 05:04:55 PM PDT 24
Peak memory 234784 kb
Host smart-fd8414df-c376-4ad3-ac26-1638a793c775
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67937552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_co
rrupt_sig_fatal_chk.67937552
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3727877205
Short name T5
Test name
Test status
Simulation time 8514873192 ps
CPU time 32.43 seconds
Started Jun 30 04:47:56 PM PDT 24
Finished Jun 30 04:48:29 PM PDT 24
Peak memory 219276 kb
Host smart-db669025-2652-43c1-a7f3-c86f4f9a604c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727877205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3727877205
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3092826095
Short name T353
Test name
Test status
Simulation time 1459529239 ps
CPU time 10.54 seconds
Started Jun 30 04:47:57 PM PDT 24
Finished Jun 30 04:48:08 PM PDT 24
Peak memory 219224 kb
Host smart-31cb9381-af06-4fce-acba-35e7afca3919
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3092826095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3092826095
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3943168937
Short name T172
Test name
Test status
Simulation time 29360177084 ps
CPU time 39.06 seconds
Started Jun 30 04:47:58 PM PDT 24
Finished Jun 30 04:48:38 PM PDT 24
Peak memory 216644 kb
Host smart-793a647a-f36d-4ab0-b154-8478fbb680d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943168937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3943168937
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1144338224
Short name T270
Test name
Test status
Simulation time 9470234811 ps
CPU time 81.92 seconds
Started Jun 30 04:47:57 PM PDT 24
Finished Jun 30 04:49:20 PM PDT 24
Peak memory 219412 kb
Host smart-f9c158e7-e9a6-4579-a42d-1c0a5e6a17b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144338224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1144338224
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3163897698
Short name T248
Test name
Test status
Simulation time 662122026 ps
CPU time 8.31 seconds
Started Jun 30 04:47:56 PM PDT 24
Finished Jun 30 04:48:05 PM PDT 24
Peak memory 216996 kb
Host smart-6a04be41-e6b7-45b8-94a9-aa2a7e130550
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163897698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3163897698
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1327410990
Short name T354
Test name
Test status
Simulation time 90543910050 ps
CPU time 394.13 seconds
Started Jun 30 04:48:02 PM PDT 24
Finished Jun 30 04:54:36 PM PDT 24
Peak memory 224784 kb
Host smart-eec80385-d4c4-4f8d-ad95-f297720a034f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327410990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1327410990
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1439246026
Short name T137
Test name
Test status
Simulation time 8590838164 ps
CPU time 54.14 seconds
Started Jun 30 04:47:58 PM PDT 24
Finished Jun 30 04:48:53 PM PDT 24
Peak memory 219164 kb
Host smart-da449344-008b-4944-97bd-a892278406fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439246026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1439246026
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.687139020
Short name T296
Test name
Test status
Simulation time 7861982612 ps
CPU time 31.47 seconds
Started Jun 30 04:47:58 PM PDT 24
Finished Jun 30 04:48:30 PM PDT 24
Peak memory 211968 kb
Host smart-13c909b2-b529-4d4f-831e-15d3540f9ba1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=687139020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.687139020
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1013417803
Short name T37
Test name
Test status
Simulation time 14239496895 ps
CPU time 60.51 seconds
Started Jun 30 04:47:57 PM PDT 24
Finished Jun 30 04:48:58 PM PDT 24
Peak memory 216316 kb
Host smart-276e2eb8-204e-4a96-ba1c-df07b7b494cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013417803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1013417803
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2604368706
Short name T197
Test name
Test status
Simulation time 14167934143 ps
CPU time 132.61 seconds
Started Jun 30 04:47:56 PM PDT 24
Finished Jun 30 04:50:09 PM PDT 24
Peak memory 219292 kb
Host smart-2aeb8569-0d58-4c95-9359-b4210ae54f68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604368706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2604368706
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2558500103
Short name T239
Test name
Test status
Simulation time 2704054450 ps
CPU time 24.83 seconds
Started Jun 30 04:47:57 PM PDT 24
Finished Jun 30 04:48:22 PM PDT 24
Peak memory 217272 kb
Host smart-378763f4-b7ee-4375-a06c-bf452c000716
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558500103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2558500103
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2090141060
Short name T187
Test name
Test status
Simulation time 26495169235 ps
CPU time 260.07 seconds
Started Jun 30 04:47:55 PM PDT 24
Finished Jun 30 04:52:15 PM PDT 24
Peak memory 219448 kb
Host smart-2c6b35b2-be8c-4c66-a1f5-4b0127fb1f8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090141060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2090141060
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.469408852
Short name T319
Test name
Test status
Simulation time 2544087375 ps
CPU time 35.13 seconds
Started Jun 30 04:48:02 PM PDT 24
Finished Jun 30 04:48:38 PM PDT 24
Peak memory 219044 kb
Host smart-59f006b5-68ba-4e65-873c-07fc842fa3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469408852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.469408852
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3378876858
Short name T179
Test name
Test status
Simulation time 1333862124 ps
CPU time 11.01 seconds
Started Jun 30 04:47:58 PM PDT 24
Finished Jun 30 04:48:09 PM PDT 24
Peak memory 219536 kb
Host smart-942c0b32-a47c-4372-ac76-684b1444d689
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3378876858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3378876858
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3588662855
Short name T152
Test name
Test status
Simulation time 9667791636 ps
CPU time 33.96 seconds
Started Jun 30 04:48:00 PM PDT 24
Finished Jun 30 04:48:34 PM PDT 24
Peak memory 216844 kb
Host smart-cd6fc7a6-4b98-481e-8c3f-beac53ecef9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588662855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3588662855
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2114467659
Short name T331
Test name
Test status
Simulation time 32886527742 ps
CPU time 193.01 seconds
Started Jun 30 04:47:56 PM PDT 24
Finished Jun 30 04:51:10 PM PDT 24
Peak memory 220416 kb
Host smart-065835e1-af7a-4d6e-80eb-79a275c2699d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114467659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2114467659
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.662831595
Short name T68
Test name
Test status
Simulation time 1315575122 ps
CPU time 10.45 seconds
Started Jun 30 04:48:09 PM PDT 24
Finished Jun 30 04:48:20 PM PDT 24
Peak memory 217032 kb
Host smart-8d4f7b82-7572-440a-ad67-b36a5eb253a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662831595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.662831595
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.43829068
Short name T43
Test name
Test status
Simulation time 5537952741 ps
CPU time 405.31 seconds
Started Jun 30 04:48:05 PM PDT 24
Finished Jun 30 04:54:51 PM PDT 24
Peak memory 240952 kb
Host smart-13782c79-2567-4d7f-9806-3cb4b09a6139
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43829068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_co
rrupt_sig_fatal_chk.43829068
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3729744462
Short name T347
Test name
Test status
Simulation time 19028140596 ps
CPU time 46.86 seconds
Started Jun 30 04:48:04 PM PDT 24
Finished Jun 30 04:48:52 PM PDT 24
Peak memory 219344 kb
Host smart-36c7a319-19f3-4131-9e0b-144a078ea83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729744462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3729744462
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1936410603
Short name T233
Test name
Test status
Simulation time 4367904355 ps
CPU time 32.22 seconds
Started Jun 30 04:48:09 PM PDT 24
Finished Jun 30 04:48:41 PM PDT 24
Peak memory 219260 kb
Host smart-2dca998f-03f2-4dd9-98a1-e646c8ca77c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1936410603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1936410603
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1023400566
Short name T202
Test name
Test status
Simulation time 1344970513 ps
CPU time 19.95 seconds
Started Jun 30 04:47:59 PM PDT 24
Finished Jun 30 04:48:19 PM PDT 24
Peak memory 215484 kb
Host smart-61a89b6e-c30e-494c-861b-91612304995d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023400566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1023400566
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3276054336
Short name T343
Test name
Test status
Simulation time 33658576899 ps
CPU time 89.3 seconds
Started Jun 30 04:47:57 PM PDT 24
Finished Jun 30 04:49:27 PM PDT 24
Peak memory 219292 kb
Host smart-38a53ccd-7889-4989-9deb-6ab3becb640f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276054336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3276054336
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.1394058538
Short name T15
Test name
Test status
Simulation time 96503591838 ps
CPU time 3126.54 seconds
Started Jun 30 04:48:06 PM PDT 24
Finished Jun 30 05:40:14 PM PDT 24
Peak memory 233792 kb
Host smart-b6277761-62ec-4b71-b1ea-dd65a425feb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394058538 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.1394058538
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1539234747
Short name T32
Test name
Test status
Simulation time 15087958308 ps
CPU time 20.96 seconds
Started Jun 30 04:48:04 PM PDT 24
Finished Jun 30 04:48:25 PM PDT 24
Peak memory 217500 kb
Host smart-c1dd5be8-8144-4c8f-bf0a-1995a97f1f1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539234747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1539234747
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3792599556
Short name T41
Test name
Test status
Simulation time 336443987007 ps
CPU time 893.46 seconds
Started Jun 30 04:48:04 PM PDT 24
Finished Jun 30 05:02:58 PM PDT 24
Peak memory 226632 kb
Host smart-37d14dcb-ed29-40a8-bd0d-af082b425803
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792599556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3792599556
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1410447777
Short name T151
Test name
Test status
Simulation time 13338909865 ps
CPU time 58.84 seconds
Started Jun 30 04:48:08 PM PDT 24
Finished Jun 30 04:49:07 PM PDT 24
Peak memory 219228 kb
Host smart-7a6ced1b-4e93-450b-9233-0fa6734c0a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410447777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1410447777
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2773108955
Short name T320
Test name
Test status
Simulation time 14715495801 ps
CPU time 29.61 seconds
Started Jun 30 04:48:07 PM PDT 24
Finished Jun 30 04:48:37 PM PDT 24
Peak memory 219276 kb
Host smart-58e5ce9a-d529-45e5-9c36-5ae70d951781
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2773108955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2773108955
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2430468265
Short name T215
Test name
Test status
Simulation time 7966892631 ps
CPU time 35.32 seconds
Started Jun 30 04:48:03 PM PDT 24
Finished Jun 30 04:48:39 PM PDT 24
Peak memory 217140 kb
Host smart-64c48792-fe1a-4fae-8056-33a3889e25f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430468265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2430468265
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3017147992
Short name T292
Test name
Test status
Simulation time 1743718787 ps
CPU time 56.34 seconds
Started Jun 30 04:48:06 PM PDT 24
Finished Jun 30 04:49:02 PM PDT 24
Peak memory 219324 kb
Host smart-f932162c-9677-4e69-a90e-e41782afd235
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017147992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3017147992
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.86774864
Short name T359
Test name
Test status
Simulation time 319838253 ps
CPU time 8.31 seconds
Started Jun 30 04:48:04 PM PDT 24
Finished Jun 30 04:48:13 PM PDT 24
Peak memory 216984 kb
Host smart-bcc42f19-919e-43cc-9e89-d7c452ed62e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86774864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.86774864
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.714139323
Short name T312
Test name
Test status
Simulation time 287289225522 ps
CPU time 712.94 seconds
Started Jun 30 04:48:06 PM PDT 24
Finished Jun 30 04:59:59 PM PDT 24
Peak memory 234544 kb
Host smart-6429ff98-12ae-4dc1-b982-b87fd93df190
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714139323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.714139323
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2851297637
Short name T169
Test name
Test status
Simulation time 6183462599 ps
CPU time 35.34 seconds
Started Jun 30 04:48:04 PM PDT 24
Finished Jun 30 04:48:40 PM PDT 24
Peak memory 219284 kb
Host smart-f990938b-195a-4970-b841-2c2db708e93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851297637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2851297637
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1984482443
Short name T352
Test name
Test status
Simulation time 371370840 ps
CPU time 10.31 seconds
Started Jun 30 04:48:07 PM PDT 24
Finished Jun 30 04:48:18 PM PDT 24
Peak memory 219156 kb
Host smart-98b64dab-bfae-4d17-9213-5df8395b9c48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1984482443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1984482443
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.533983339
Short name T58
Test name
Test status
Simulation time 2117950718 ps
CPU time 23.82 seconds
Started Jun 30 04:48:04 PM PDT 24
Finished Jun 30 04:48:28 PM PDT 24
Peak memory 215620 kb
Host smart-df9f9a77-49ad-4574-b17c-d81518baf3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533983339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.533983339
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1712689279
Short name T145
Test name
Test status
Simulation time 552417227 ps
CPU time 33.29 seconds
Started Jun 30 04:48:06 PM PDT 24
Finished Jun 30 04:48:40 PM PDT 24
Peak memory 219196 kb
Host smart-b1e60203-a26a-4f79-a2c1-32eef1e90f6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712689279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1712689279
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2599666388
Short name T140
Test name
Test status
Simulation time 28286753439 ps
CPU time 26.28 seconds
Started Jun 30 04:48:08 PM PDT 24
Finished Jun 30 04:48:35 PM PDT 24
Peak memory 217456 kb
Host smart-288f41f1-717b-4632-8f90-5e9e44769191
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599666388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2599666388
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1738556947
Short name T7
Test name
Test status
Simulation time 6152975852 ps
CPU time 28.93 seconds
Started Jun 30 04:48:05 PM PDT 24
Finished Jun 30 04:48:35 PM PDT 24
Peak memory 219304 kb
Host smart-001a73e2-0131-4de7-ba5e-c344c5f995c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738556947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1738556947
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.549284382
Short name T267
Test name
Test status
Simulation time 2493016793 ps
CPU time 23.96 seconds
Started Jun 30 04:48:09 PM PDT 24
Finished Jun 30 04:48:33 PM PDT 24
Peak memory 219276 kb
Host smart-7e700858-36aa-484f-a4b0-a0213a8ce1ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=549284382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.549284382
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.738411889
Short name T276
Test name
Test status
Simulation time 1734308487 ps
CPU time 20.38 seconds
Started Jun 30 04:48:04 PM PDT 24
Finished Jun 30 04:48:25 PM PDT 24
Peak memory 216404 kb
Host smart-721a9c12-0b64-4eb0-88f6-2f24baa933e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738411889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.738411889
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.4249415962
Short name T206
Test name
Test status
Simulation time 1257229134 ps
CPU time 12.82 seconds
Started Jun 30 04:48:13 PM PDT 24
Finished Jun 30 04:48:26 PM PDT 24
Peak memory 217112 kb
Host smart-a70f41dd-677d-46c2-8fe3-a6efc176288c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249415962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.4249415962
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1810373852
Short name T247
Test name
Test status
Simulation time 3575468898 ps
CPU time 41.58 seconds
Started Jun 30 04:48:06 PM PDT 24
Finished Jun 30 04:48:48 PM PDT 24
Peak memory 219244 kb
Host smart-cf576b38-972a-4829-9006-d35f92fba1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810373852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1810373852
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2453728117
Short name T189
Test name
Test status
Simulation time 3862845142 ps
CPU time 31.01 seconds
Started Jun 30 04:48:06 PM PDT 24
Finished Jun 30 04:48:37 PM PDT 24
Peak memory 219336 kb
Host smart-7ff3c6cd-0480-44ad-b7a1-96fd9d18beb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2453728117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2453728117
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.1059915234
Short name T227
Test name
Test status
Simulation time 15840835061 ps
CPU time 47.31 seconds
Started Jun 30 04:48:05 PM PDT 24
Finished Jun 30 04:48:53 PM PDT 24
Peak memory 216240 kb
Host smart-01eaa1e4-57dd-43e2-84ee-d3e7e0ddb18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059915234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1059915234
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.4238708904
Short name T229
Test name
Test status
Simulation time 5616628914 ps
CPU time 27.58 seconds
Started Jun 30 04:48:03 PM PDT 24
Finished Jun 30 04:48:31 PM PDT 24
Peak memory 214800 kb
Host smart-b0057996-52ca-498a-a122-d826741bc639
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238708904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.4238708904
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.220220436
Short name T175
Test name
Test status
Simulation time 4135196812 ps
CPU time 33.14 seconds
Started Jun 30 04:48:11 PM PDT 24
Finished Jun 30 04:48:45 PM PDT 24
Peak memory 217232 kb
Host smart-a9993c78-ec8b-4866-aa49-cd818d3c7370
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220220436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.220220436
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1244148223
Short name T194
Test name
Test status
Simulation time 11253574348 ps
CPU time 185.9 seconds
Started Jun 30 04:48:11 PM PDT 24
Finished Jun 30 04:51:17 PM PDT 24
Peak memory 240024 kb
Host smart-085b577b-e20a-4769-908e-ce517b4846f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244148223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1244148223
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1517507080
Short name T275
Test name
Test status
Simulation time 6851176125 ps
CPU time 39.67 seconds
Started Jun 30 04:48:15 PM PDT 24
Finished Jun 30 04:48:55 PM PDT 24
Peak memory 219128 kb
Host smart-48aa3970-2a53-4ffa-afec-a1e5665e2fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517507080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1517507080
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1715674370
Short name T163
Test name
Test status
Simulation time 10562848576 ps
CPU time 26.22 seconds
Started Jun 30 04:48:13 PM PDT 24
Finished Jun 30 04:48:40 PM PDT 24
Peak memory 219300 kb
Host smart-f2eef941-9fc4-49f5-ae0c-6eff7cda6f56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1715674370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1715674370
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.615548891
Short name T322
Test name
Test status
Simulation time 348916857 ps
CPU time 20.17 seconds
Started Jun 30 04:48:14 PM PDT 24
Finished Jun 30 04:48:34 PM PDT 24
Peak memory 215952 kb
Host smart-0612873d-851f-48ad-a9b2-0d9fe691930a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615548891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.615548891
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.582059418
Short name T101
Test name
Test status
Simulation time 31439020318 ps
CPU time 97.51 seconds
Started Jun 30 04:48:11 PM PDT 24
Finished Jun 30 04:49:49 PM PDT 24
Peak memory 227532 kb
Host smart-f4481fba-f861-4220-8830-b142a5639b6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582059418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.582059418
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.4016502343
Short name T24
Test name
Test status
Simulation time 11436935708 ps
CPU time 26.33 seconds
Started Jun 30 04:46:41 PM PDT 24
Finished Jun 30 04:47:09 PM PDT 24
Peak memory 213248 kb
Host smart-741ba22e-58cf-4bc5-bb59-aeba9cd79bc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016502343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.4016502343
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.177928803
Short name T307
Test name
Test status
Simulation time 16356203614 ps
CPU time 44.42 seconds
Started Jun 30 04:46:41 PM PDT 24
Finished Jun 30 04:47:27 PM PDT 24
Peak memory 219132 kb
Host smart-5f7a4621-97a4-4eb4-b262-11a25a9a68b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177928803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.177928803
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.870207441
Short name T144
Test name
Test status
Simulation time 8546361643 ps
CPU time 33.12 seconds
Started Jun 30 04:46:42 PM PDT 24
Finished Jun 30 04:47:16 PM PDT 24
Peak memory 219300 kb
Host smart-18f754cf-bb27-4e76-99c7-ca1309366d02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=870207441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.870207441
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.806137853
Short name T28
Test name
Test status
Simulation time 4988801304 ps
CPU time 230.89 seconds
Started Jun 30 04:46:44 PM PDT 24
Finished Jun 30 04:50:35 PM PDT 24
Peak memory 236164 kb
Host smart-e04d62c5-2895-4ba6-a6f9-a300cdbaffa7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806137853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.806137853
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2215229739
Short name T332
Test name
Test status
Simulation time 8569666281 ps
CPU time 67.04 seconds
Started Jun 30 04:46:41 PM PDT 24
Finished Jun 30 04:47:49 PM PDT 24
Peak memory 216888 kb
Host smart-2c9e3dc1-d04f-4343-920e-5ad9fc45cbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215229739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2215229739
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1709888680
Short name T193
Test name
Test status
Simulation time 2604836896 ps
CPU time 21.74 seconds
Started Jun 30 04:46:43 PM PDT 24
Finished Jun 30 04:47:05 PM PDT 24
Peak memory 219316 kb
Host smart-6dd5ff18-af28-4fb3-bc34-527eb2de5a4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709888680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1709888680
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3056984919
Short name T230
Test name
Test status
Simulation time 6494361775 ps
CPU time 18.73 seconds
Started Jun 30 04:48:16 PM PDT 24
Finished Jun 30 04:48:35 PM PDT 24
Peak memory 217388 kb
Host smart-dce6cbe3-d389-4c66-8129-274ed7cc5670
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056984919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3056984919
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2858600536
Short name T355
Test name
Test status
Simulation time 35962407978 ps
CPU time 443.6 seconds
Started Jun 30 04:48:12 PM PDT 24
Finished Jun 30 04:55:36 PM PDT 24
Peak memory 219452 kb
Host smart-d6184753-d2a4-4899-a871-65a93edd9395
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858600536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2858600536
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1458598376
Short name T316
Test name
Test status
Simulation time 16333820750 ps
CPU time 68.76 seconds
Started Jun 30 04:48:13 PM PDT 24
Finished Jun 30 04:49:22 PM PDT 24
Peak memory 219300 kb
Host smart-5c02e762-b56f-468c-800b-42ec3d65fcf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458598376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1458598376
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3476888678
Short name T160
Test name
Test status
Simulation time 2240039839 ps
CPU time 16.82 seconds
Started Jun 30 04:48:13 PM PDT 24
Finished Jun 30 04:48:30 PM PDT 24
Peak memory 219336 kb
Host smart-7aab652c-1401-4f7d-a51f-5e10b15767bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3476888678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3476888678
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3208543551
Short name T173
Test name
Test status
Simulation time 30119912155 ps
CPU time 78.28 seconds
Started Jun 30 04:48:12 PM PDT 24
Finished Jun 30 04:49:30 PM PDT 24
Peak memory 215948 kb
Host smart-1e4c4714-9242-48b5-8aa2-7f5dd42dc771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208543551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3208543551
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3531450456
Short name T154
Test name
Test status
Simulation time 7512453206 ps
CPU time 81.34 seconds
Started Jun 30 04:48:17 PM PDT 24
Finished Jun 30 04:49:38 PM PDT 24
Peak memory 219292 kb
Host smart-098426e9-d072-48dc-9fb4-c4355c212978
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531450456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3531450456
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3512272747
Short name T186
Test name
Test status
Simulation time 2338542335 ps
CPU time 16.06 seconds
Started Jun 30 04:48:13 PM PDT 24
Finished Jun 30 04:48:30 PM PDT 24
Peak memory 217152 kb
Host smart-f188b432-1a1d-40d6-915e-678045ad4ac5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512272747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3512272747
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.401536758
Short name T51
Test name
Test status
Simulation time 155425694151 ps
CPU time 337.66 seconds
Started Jun 30 04:48:15 PM PDT 24
Finished Jun 30 04:53:53 PM PDT 24
Peak memory 235040 kb
Host smart-4725d86b-e974-43ac-aff4-f7c976cb5029
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401536758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.401536758
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2619622599
Short name T1
Test name
Test status
Simulation time 9123095232 ps
CPU time 49.44 seconds
Started Jun 30 04:48:13 PM PDT 24
Finished Jun 30 04:49:03 PM PDT 24
Peak memory 219268 kb
Host smart-c5954919-2225-4214-95a9-8de60a01760d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619622599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2619622599
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2755481460
Short name T209
Test name
Test status
Simulation time 1439072837 ps
CPU time 14.85 seconds
Started Jun 30 04:48:14 PM PDT 24
Finished Jun 30 04:48:29 PM PDT 24
Peak memory 219280 kb
Host smart-cd4d87ba-98b1-4607-ae6b-65104f8f49d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2755481460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2755481460
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.28099356
Short name T260
Test name
Test status
Simulation time 3085050875 ps
CPU time 20.54 seconds
Started Jun 30 04:48:13 PM PDT 24
Finished Jun 30 04:48:34 PM PDT 24
Peak memory 217368 kb
Host smart-9a88a6ca-17c0-43e0-8d62-ef6531ac9429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28099356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.28099356
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2081252394
Short name T57
Test name
Test status
Simulation time 790996818 ps
CPU time 23.8 seconds
Started Jun 30 04:48:14 PM PDT 24
Finished Jun 30 04:48:38 PM PDT 24
Peak memory 219208 kb
Host smart-e811a3d1-1045-4765-879d-f1a2b15d0b23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081252394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2081252394
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3615075622
Short name T185
Test name
Test status
Simulation time 16974371566 ps
CPU time 24.15 seconds
Started Jun 30 04:48:20 PM PDT 24
Finished Jun 30 04:48:44 PM PDT 24
Peak memory 217408 kb
Host smart-dd21f9a5-2e61-48c0-8642-db21fff8aa10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615075622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3615075622
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.203533229
Short name T314
Test name
Test status
Simulation time 84235197256 ps
CPU time 276.39 seconds
Started Jun 30 04:48:12 PM PDT 24
Finished Jun 30 04:52:49 PM PDT 24
Peak memory 224756 kb
Host smart-34470a52-dd84-4fa1-82a1-2afb3946147f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203533229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.203533229
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2213165370
Short name T255
Test name
Test status
Simulation time 689542002 ps
CPU time 19.82 seconds
Started Jun 30 04:48:12 PM PDT 24
Finished Jun 30 04:48:32 PM PDT 24
Peak memory 219208 kb
Host smart-ae34be53-129a-49a2-9332-a87e24864a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213165370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2213165370
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3919645006
Short name T124
Test name
Test status
Simulation time 14732171550 ps
CPU time 29.69 seconds
Started Jun 30 04:48:12 PM PDT 24
Finished Jun 30 04:48:42 PM PDT 24
Peak memory 219284 kb
Host smart-016bb55a-321a-42e2-81a3-8383db3a97bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3919645006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3919645006
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1153739536
Short name T119
Test name
Test status
Simulation time 24714331628 ps
CPU time 32.3 seconds
Started Jun 30 04:48:17 PM PDT 24
Finished Jun 30 04:48:49 PM PDT 24
Peak memory 217348 kb
Host smart-7728a138-45af-46fd-ada7-78b3863a6fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153739536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1153739536
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2672184933
Short name T122
Test name
Test status
Simulation time 2934899779 ps
CPU time 43.13 seconds
Started Jun 30 04:48:16 PM PDT 24
Finished Jun 30 04:49:00 PM PDT 24
Peak memory 219312 kb
Host smart-316f579f-5a99-4b36-aae6-a7255943e871
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672184933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2672184933
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2889129415
Short name T27
Test name
Test status
Simulation time 14750638082 ps
CPU time 28.86 seconds
Started Jun 30 04:48:19 PM PDT 24
Finished Jun 30 04:48:49 PM PDT 24
Peak memory 217364 kb
Host smart-f4ffb42d-ca21-42e8-8229-fa47f2ff60a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889129415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2889129415
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.747416323
Short name T44
Test name
Test status
Simulation time 3785268105 ps
CPU time 285.05 seconds
Started Jun 30 04:48:20 PM PDT 24
Finished Jun 30 04:53:06 PM PDT 24
Peak memory 236896 kb
Host smart-79b7d3b0-2356-4faf-b137-c740a40827fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747416323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.747416323
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3225255745
Short name T201
Test name
Test status
Simulation time 671830310 ps
CPU time 23.59 seconds
Started Jun 30 04:48:18 PM PDT 24
Finished Jun 30 04:48:42 PM PDT 24
Peak memory 215608 kb
Host smart-df6f3a3f-a95a-48a9-b5a3-151a74a8da16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225255745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3225255745
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.775704415
Short name T315
Test name
Test status
Simulation time 4540113407 ps
CPU time 25.16 seconds
Started Jun 30 04:48:20 PM PDT 24
Finished Jun 30 04:48:46 PM PDT 24
Peak memory 211972 kb
Host smart-fb4a6abc-8e01-4b11-80f2-1cb53f57b733
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=775704415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.775704415
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.897785654
Short name T243
Test name
Test status
Simulation time 378965719 ps
CPU time 19.65 seconds
Started Jun 30 04:48:21 PM PDT 24
Finished Jun 30 04:48:41 PM PDT 24
Peak memory 216560 kb
Host smart-a7846745-0c13-44b7-b49a-a81a4ec6640e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897785654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.897785654
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1552638253
Short name T2
Test name
Test status
Simulation time 30043256818 ps
CPU time 126.12 seconds
Started Jun 30 04:48:20 PM PDT 24
Finished Jun 30 04:50:27 PM PDT 24
Peak memory 221124 kb
Host smart-3433b5b5-15ce-4343-b861-f9c39fafab2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552638253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1552638253
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3281277415
Short name T139
Test name
Test status
Simulation time 1177878528 ps
CPU time 8.58 seconds
Started Jun 30 04:48:19 PM PDT 24
Finished Jun 30 04:48:28 PM PDT 24
Peak memory 213168 kb
Host smart-15e76d7f-d647-4e90-811c-556894ea4b93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281277415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3281277415
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2853063443
Short name T328
Test name
Test status
Simulation time 36950535369 ps
CPU time 372.74 seconds
Started Jun 30 04:48:18 PM PDT 24
Finished Jun 30 04:54:31 PM PDT 24
Peak memory 239964 kb
Host smart-05325392-a374-4833-a364-9823b4ac06da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853063443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2853063443
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1711658662
Short name T337
Test name
Test status
Simulation time 2961817174 ps
CPU time 38.28 seconds
Started Jun 30 04:48:21 PM PDT 24
Finished Jun 30 04:49:00 PM PDT 24
Peak memory 219308 kb
Host smart-05872f91-3be2-474e-ab04-11b6d82eb073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711658662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1711658662
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.237377753
Short name T274
Test name
Test status
Simulation time 5559810994 ps
CPU time 26.28 seconds
Started Jun 30 04:48:19 PM PDT 24
Finished Jun 30 04:48:46 PM PDT 24
Peak memory 211728 kb
Host smart-6167d1c9-d212-46c2-aadc-80e16d7e7c5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=237377753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.237377753
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.711314452
Short name T234
Test name
Test status
Simulation time 28773303753 ps
CPU time 61.25 seconds
Started Jun 30 04:48:23 PM PDT 24
Finished Jun 30 04:49:24 PM PDT 24
Peak memory 216648 kb
Host smart-94fad01d-0ff1-4555-a001-f9e7a96554d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711314452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.711314452
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.415070132
Short name T261
Test name
Test status
Simulation time 55769773825 ps
CPU time 83.55 seconds
Started Jun 30 04:48:20 PM PDT 24
Finished Jun 30 04:49:44 PM PDT 24
Peak memory 219316 kb
Host smart-30c848f5-896e-47b7-b3c7-cb3d34980b25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415070132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.415070132
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.8287290
Short name T26
Test name
Test status
Simulation time 7004558409 ps
CPU time 28.71 seconds
Started Jun 30 04:48:18 PM PDT 24
Finished Jun 30 04:48:47 PM PDT 24
Peak memory 217388 kb
Host smart-50b76c22-51ca-48f3-b98a-b96162b832a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8287290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.8287290
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.4172379160
Short name T299
Test name
Test status
Simulation time 33494118055 ps
CPU time 364.68 seconds
Started Jun 30 04:48:19 PM PDT 24
Finished Jun 30 04:54:24 PM PDT 24
Peak memory 214804 kb
Host smart-632ad5db-049c-40ee-bc02-f7c8d6578436
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172379160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.4172379160
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2747579
Short name T263
Test name
Test status
Simulation time 6229817437 ps
CPU time 53.99 seconds
Started Jun 30 04:48:19 PM PDT 24
Finished Jun 30 04:49:13 PM PDT 24
Peak memory 219320 kb
Host smart-6a06fbba-b25d-4bcc-8f0a-d8d3fd2cacab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2747579
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3124580633
Short name T178
Test name
Test status
Simulation time 4139478861 ps
CPU time 16.48 seconds
Started Jun 30 04:48:23 PM PDT 24
Finished Jun 30 04:48:40 PM PDT 24
Peak memory 219276 kb
Host smart-ddc9f83b-f5a7-449d-bbfa-c6720cd81bfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3124580633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3124580633
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.3380986911
Short name T59
Test name
Test status
Simulation time 1651746115 ps
CPU time 30.6 seconds
Started Jun 30 04:48:20 PM PDT 24
Finished Jun 30 04:48:51 PM PDT 24
Peak memory 215920 kb
Host smart-ef09548c-3c4c-4a7f-9bb2-0f72bec2ff88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380986911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.3380986911
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2504557000
Short name T36
Test name
Test status
Simulation time 1025912924 ps
CPU time 10.08 seconds
Started Jun 30 04:48:32 PM PDT 24
Finished Jun 30 04:48:42 PM PDT 24
Peak memory 216976 kb
Host smart-d463a9e8-7b3f-424e-b400-7de9b0ffb8f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504557000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2504557000
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3747352768
Short name T293
Test name
Test status
Simulation time 37791567143 ps
CPU time 248.07 seconds
Started Jun 30 04:48:26 PM PDT 24
Finished Jun 30 04:52:35 PM PDT 24
Peak memory 237728 kb
Host smart-6b91fb02-4eb6-449d-aad9-1498bb2be7d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747352768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3747352768
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1543730433
Short name T232
Test name
Test status
Simulation time 5959517241 ps
CPU time 39.33 seconds
Started Jun 30 04:48:28 PM PDT 24
Finished Jun 30 04:49:08 PM PDT 24
Peak memory 218780 kb
Host smart-92d8aaaa-3aea-4bc5-85fd-fad161bdcc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543730433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1543730433
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1319164401
Short name T304
Test name
Test status
Simulation time 3032908241 ps
CPU time 26.98 seconds
Started Jun 30 04:48:26 PM PDT 24
Finished Jun 30 04:48:54 PM PDT 24
Peak memory 219300 kb
Host smart-3e006393-7f1b-4123-b0bf-e7dc33c5da6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1319164401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1319164401
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.498234200
Short name T303
Test name
Test status
Simulation time 27565943823 ps
CPU time 71.67 seconds
Started Jun 30 04:48:27 PM PDT 24
Finished Jun 30 04:49:39 PM PDT 24
Peak memory 215872 kb
Host smart-658fc4fb-6761-4989-93b4-50d72ddfda43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498234200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.498234200
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2151080889
Short name T4
Test name
Test status
Simulation time 8144935939 ps
CPU time 66.94 seconds
Started Jun 30 04:48:26 PM PDT 24
Finished Jun 30 04:49:33 PM PDT 24
Peak memory 221012 kb
Host smart-a2e32c1b-a1b7-4b80-88f9-6a281710d850
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151080889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2151080889
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2435755976
Short name T174
Test name
Test status
Simulation time 25190347138 ps
CPU time 27.78 seconds
Started Jun 30 04:48:26 PM PDT 24
Finished Jun 30 04:48:54 PM PDT 24
Peak memory 217396 kb
Host smart-854fc6ae-5f46-4871-a57e-7e24ae35b5d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435755976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2435755976
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2334802577
Short name T321
Test name
Test status
Simulation time 156091912909 ps
CPU time 916.73 seconds
Started Jun 30 04:48:27 PM PDT 24
Finished Jun 30 05:03:44 PM PDT 24
Peak memory 225844 kb
Host smart-ac644e2c-7cb1-4574-94f4-65752200d4a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334802577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2334802577
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.492228115
Short name T127
Test name
Test status
Simulation time 353343558 ps
CPU time 19.04 seconds
Started Jun 30 04:48:26 PM PDT 24
Finished Jun 30 04:48:45 PM PDT 24
Peak memory 219196 kb
Host smart-ac15ceb4-370f-4ba6-8e45-cc61c11a0a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492228115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.492228115
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3566021990
Short name T357
Test name
Test status
Simulation time 2325364373 ps
CPU time 13.65 seconds
Started Jun 30 04:48:32 PM PDT 24
Finished Jun 30 04:48:46 PM PDT 24
Peak memory 219260 kb
Host smart-cb6535e1-bf2a-49d3-84c5-96cc7d81c5c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3566021990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3566021990
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3659491854
Short name T305
Test name
Test status
Simulation time 6307786808 ps
CPU time 62.45 seconds
Started Jun 30 04:48:27 PM PDT 24
Finished Jun 30 04:49:30 PM PDT 24
Peak memory 217488 kb
Host smart-80f89ecb-ef66-41e4-9ebb-d47831108e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659491854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3659491854
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.917244191
Short name T80
Test name
Test status
Simulation time 1354836731 ps
CPU time 33.34 seconds
Started Jun 30 04:48:28 PM PDT 24
Finished Jun 30 04:49:02 PM PDT 24
Peak memory 219216 kb
Host smart-0299670f-e2e3-46d8-9421-b0c80a9f66ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917244191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.917244191
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1130096950
Short name T258
Test name
Test status
Simulation time 5658074940 ps
CPU time 25.17 seconds
Started Jun 30 04:48:34 PM PDT 24
Finished Jun 30 04:49:00 PM PDT 24
Peak memory 217512 kb
Host smart-ba9f04fc-476c-43e5-aeb0-0c927309e916
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130096950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1130096950
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.202849429
Short name T268
Test name
Test status
Simulation time 173142936029 ps
CPU time 570.23 seconds
Started Jun 30 04:48:28 PM PDT 24
Finished Jun 30 04:57:59 PM PDT 24
Peak memory 234576 kb
Host smart-b1bfd129-48c9-4b5b-b4de-d381607bb66a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202849429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.202849429
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.968370987
Short name T285
Test name
Test status
Simulation time 24592638300 ps
CPU time 54.6 seconds
Started Jun 30 04:48:29 PM PDT 24
Finished Jun 30 04:49:24 PM PDT 24
Peak memory 219272 kb
Host smart-ca93d4f9-c25f-46e5-b6aa-df6d49b6502d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968370987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.968370987
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.500637132
Short name T222
Test name
Test status
Simulation time 2985526166 ps
CPU time 15.1 seconds
Started Jun 30 04:48:26 PM PDT 24
Finished Jun 30 04:48:42 PM PDT 24
Peak memory 219196 kb
Host smart-8efbc16b-b922-4e0b-a14f-8aa0aa0cb81a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=500637132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.500637132
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2186269633
Short name T221
Test name
Test status
Simulation time 707090421 ps
CPU time 19.89 seconds
Started Jun 30 04:48:26 PM PDT 24
Finished Jun 30 04:48:47 PM PDT 24
Peak memory 216372 kb
Host smart-1dd34829-5dff-4812-aa4a-261233f6a966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186269633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2186269633
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3186823533
Short name T345
Test name
Test status
Simulation time 544356631 ps
CPU time 34.11 seconds
Started Jun 30 04:48:32 PM PDT 24
Finished Jun 30 04:49:07 PM PDT 24
Peak memory 219212 kb
Host smart-aeec3360-c0cb-4ffe-9c9a-c6ad0dc6f04b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186823533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3186823533
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1732352899
Short name T356
Test name
Test status
Simulation time 339271235 ps
CPU time 8.54 seconds
Started Jun 30 04:48:34 PM PDT 24
Finished Jun 30 04:48:44 PM PDT 24
Peak memory 217152 kb
Host smart-9e26c153-52e5-4c7d-9099-8ca33ca639bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732352899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1732352899
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.4070788929
Short name T335
Test name
Test status
Simulation time 57510758298 ps
CPU time 636.88 seconds
Started Jun 30 04:48:36 PM PDT 24
Finished Jun 30 04:59:13 PM PDT 24
Peak memory 233752 kb
Host smart-d8e96125-789f-45b9-a1c2-ab8870fa460d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070788929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.4070788929
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.4014563873
Short name T251
Test name
Test status
Simulation time 838861167 ps
CPU time 25.2 seconds
Started Jun 30 04:48:34 PM PDT 24
Finished Jun 30 04:49:00 PM PDT 24
Peak memory 218788 kb
Host smart-ee4746fe-ba41-41e3-b7a4-a8aef8ab1291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014563873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.4014563873
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.4247013916
Short name T342
Test name
Test status
Simulation time 7841547242 ps
CPU time 31.34 seconds
Started Jun 30 04:48:34 PM PDT 24
Finished Jun 30 04:49:06 PM PDT 24
Peak memory 219280 kb
Host smart-51d79a83-7097-49ef-a6a3-bca4692603a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4247013916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.4247013916
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.21913100
Short name T351
Test name
Test status
Simulation time 1677375693 ps
CPU time 33.5 seconds
Started Jun 30 04:48:35 PM PDT 24
Finished Jun 30 04:49:09 PM PDT 24
Peak memory 215988 kb
Host smart-386ea07f-56ed-4213-9c5a-820d57309d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21913100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.21913100
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2675848624
Short name T203
Test name
Test status
Simulation time 15249112432 ps
CPU time 153.04 seconds
Started Jun 30 04:48:34 PM PDT 24
Finished Jun 30 04:51:07 PM PDT 24
Peak memory 221684 kb
Host smart-9f8ee44e-021b-48a2-a7e1-1f6227e17e9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675848624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2675848624
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2351154051
Short name T240
Test name
Test status
Simulation time 3397986186 ps
CPU time 28.54 seconds
Started Jun 30 04:46:39 PM PDT 24
Finished Jun 30 04:47:08 PM PDT 24
Peak memory 217224 kb
Host smart-cd414a65-5ab5-48e4-85d5-fec0afa175db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351154051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2351154051
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.875956167
Short name T253
Test name
Test status
Simulation time 9748215148 ps
CPU time 324.27 seconds
Started Jun 30 04:46:40 PM PDT 24
Finished Jun 30 04:52:05 PM PDT 24
Peak memory 239540 kb
Host smart-5ed300b1-e927-4cee-a0bd-fea629c77a67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875956167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.875956167
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1101980348
Short name T47
Test name
Test status
Simulation time 332111104 ps
CPU time 19.5 seconds
Started Jun 30 04:46:42 PM PDT 24
Finished Jun 30 04:47:03 PM PDT 24
Peak memory 219212 kb
Host smart-f56be87c-6845-4c1e-b2ab-b93359994f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101980348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1101980348
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.681737122
Short name T181
Test name
Test status
Simulation time 1070691214 ps
CPU time 11.42 seconds
Started Jun 30 04:46:43 PM PDT 24
Finished Jun 30 04:46:55 PM PDT 24
Peak memory 211560 kb
Host smart-b4e60e5a-1255-4bf3-9166-45501ace913a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=681737122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.681737122
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1654252617
Short name T346
Test name
Test status
Simulation time 700586960 ps
CPU time 20.3 seconds
Started Jun 30 04:46:43 PM PDT 24
Finished Jun 30 04:47:04 PM PDT 24
Peak memory 215908 kb
Host smart-3dee842d-20bc-4e5f-803e-b7afc56ad5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654252617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1654252617
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.709356754
Short name T146
Test name
Test status
Simulation time 2931048142 ps
CPU time 32.08 seconds
Started Jun 30 04:46:41 PM PDT 24
Finished Jun 30 04:47:14 PM PDT 24
Peak memory 214668 kb
Host smart-df4c337b-3156-458e-b1ce-3d5c1b021367
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709356754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.709356754
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.926801807
Short name T13
Test name
Test status
Simulation time 29454899415 ps
CPU time 1152.94 seconds
Started Jun 30 04:46:42 PM PDT 24
Finished Jun 30 05:05:56 PM PDT 24
Peak memory 235700 kb
Host smart-b45e218d-5765-41fa-b005-6880a0c6925f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926801807 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.926801807
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3387717907
Short name T67
Test name
Test status
Simulation time 4230691696 ps
CPU time 31.85 seconds
Started Jun 30 04:46:49 PM PDT 24
Finished Jun 30 04:47:21 PM PDT 24
Peak memory 216460 kb
Host smart-53bc7815-c33c-4611-ad6c-192a67fca2ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387717907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3387717907
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1125250092
Short name T198
Test name
Test status
Simulation time 132879357577 ps
CPU time 388.47 seconds
Started Jun 30 04:46:53 PM PDT 24
Finished Jun 30 04:53:21 PM PDT 24
Peak memory 233780 kb
Host smart-d2329b17-2411-4116-a416-540688c4bd65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125250092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1125250092
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3367399777
Short name T171
Test name
Test status
Simulation time 13521881282 ps
CPU time 38.64 seconds
Started Jun 30 04:46:48 PM PDT 24
Finished Jun 30 04:47:27 PM PDT 24
Peak memory 219276 kb
Host smart-b3f4ed04-75ea-4dda-8662-c2a6a9a1daa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367399777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3367399777
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.579732809
Short name T244
Test name
Test status
Simulation time 691925445 ps
CPU time 9.87 seconds
Started Jun 30 04:46:51 PM PDT 24
Finished Jun 30 04:47:01 PM PDT 24
Peak memory 219184 kb
Host smart-96bc8bad-e48f-435f-9838-c80870d93980
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=579732809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.579732809
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2747759095
Short name T131
Test name
Test status
Simulation time 76497677500 ps
CPU time 78.68 seconds
Started Jun 30 04:46:47 PM PDT 24
Finished Jun 30 04:48:07 PM PDT 24
Peak memory 215784 kb
Host smart-b1451683-5c64-40eb-afd4-cdf3154708cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747759095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2747759095
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1563041168
Short name T280
Test name
Test status
Simulation time 23834842727 ps
CPU time 109.55 seconds
Started Jun 30 04:46:52 PM PDT 24
Finished Jun 30 04:48:42 PM PDT 24
Peak memory 219264 kb
Host smart-8bb3a8da-162d-4f7e-ac22-26b560a6163e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563041168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1563041168
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.583100189
Short name T188
Test name
Test status
Simulation time 1808747340 ps
CPU time 20.2 seconds
Started Jun 30 04:46:47 PM PDT 24
Finished Jun 30 04:47:08 PM PDT 24
Peak memory 217080 kb
Host smart-1ae6ffad-1415-40da-a08d-282cb9b2c4f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583100189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.583100189
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2203802839
Short name T200
Test name
Test status
Simulation time 458430732360 ps
CPU time 477.07 seconds
Started Jun 30 04:46:52 PM PDT 24
Finished Jun 30 04:54:49 PM PDT 24
Peak memory 227936 kb
Host smart-eb5396c7-749e-4e23-8289-127ec8efaf2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203802839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2203802839
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3308422764
Short name T211
Test name
Test status
Simulation time 1588962472 ps
CPU time 28.67 seconds
Started Jun 30 04:46:47 PM PDT 24
Finished Jun 30 04:47:16 PM PDT 24
Peak memory 219172 kb
Host smart-9767d682-4a57-4961-91d8-9088b9e5628c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308422764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3308422764
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1138562195
Short name T125
Test name
Test status
Simulation time 4165196383 ps
CPU time 30.79 seconds
Started Jun 30 04:46:49 PM PDT 24
Finished Jun 30 04:47:21 PM PDT 24
Peak memory 219308 kb
Host smart-ed7e2f85-33e1-44de-a08f-532a94ccdff3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1138562195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1138562195
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1670520009
Short name T271
Test name
Test status
Simulation time 44569708228 ps
CPU time 47 seconds
Started Jun 30 04:46:49 PM PDT 24
Finished Jun 30 04:47:36 PM PDT 24
Peak memory 216888 kb
Host smart-23238df9-54c9-4cc2-904e-d74673f25630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670520009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1670520009
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2267007100
Short name T157
Test name
Test status
Simulation time 891941558 ps
CPU time 52.48 seconds
Started Jun 30 04:46:49 PM PDT 24
Finished Jun 30 04:47:42 PM PDT 24
Peak memory 219520 kb
Host smart-e433b429-9bbe-4b34-a525-7bc7d277cb65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267007100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2267007100
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2281023418
Short name T341
Test name
Test status
Simulation time 6301201099 ps
CPU time 26.65 seconds
Started Jun 30 04:46:56 PM PDT 24
Finished Jun 30 04:47:23 PM PDT 24
Peak memory 217380 kb
Host smart-9a56f07d-0455-4074-84fd-056e42f673c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281023418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2281023418
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.427411148
Short name T40
Test name
Test status
Simulation time 87605983208 ps
CPU time 449.32 seconds
Started Jun 30 04:46:55 PM PDT 24
Finished Jun 30 04:54:25 PM PDT 24
Peak memory 238860 kb
Host smart-ad2697bc-3158-4043-b5b0-5a247ddc56c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427411148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.427411148
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2053015797
Short name T265
Test name
Test status
Simulation time 5582644219 ps
CPU time 52.34 seconds
Started Jun 30 04:46:55 PM PDT 24
Finished Jun 30 04:47:48 PM PDT 24
Peak memory 219280 kb
Host smart-5150652c-d318-47c5-844d-46433aacf11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053015797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2053015797
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1374779037
Short name T177
Test name
Test status
Simulation time 691770659 ps
CPU time 10.39 seconds
Started Jun 30 04:46:53 PM PDT 24
Finished Jun 30 04:47:04 PM PDT 24
Peak memory 219236 kb
Host smart-d694972e-8f0b-4cf5-80ce-066e01758f66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1374779037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1374779037
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1760342724
Short name T349
Test name
Test status
Simulation time 1426941996 ps
CPU time 19.94 seconds
Started Jun 30 04:46:55 PM PDT 24
Finished Jun 30 04:47:15 PM PDT 24
Peak memory 216616 kb
Host smart-ebcbad56-a984-42d5-bfa7-f2a40e272f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760342724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1760342724
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3163169822
Short name T176
Test name
Test status
Simulation time 44418853580 ps
CPU time 149.47 seconds
Started Jun 30 04:46:55 PM PDT 24
Finished Jun 30 04:49:25 PM PDT 24
Peak memory 219636 kb
Host smart-5ab9f241-ae66-46f0-a2ff-bb37b03df421
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163169822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3163169822
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3251324952
Short name T162
Test name
Test status
Simulation time 13020262534 ps
CPU time 28.27 seconds
Started Jun 30 04:46:57 PM PDT 24
Finished Jun 30 04:47:26 PM PDT 24
Peak memory 217356 kb
Host smart-af6e1ab8-6b09-420a-9bc1-094d93ea14eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251324952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3251324952
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.734718397
Short name T269
Test name
Test status
Simulation time 192363423351 ps
CPU time 522.47 seconds
Started Jun 30 04:46:55 PM PDT 24
Finished Jun 30 04:55:38 PM PDT 24
Peak memory 227608 kb
Host smart-15c68686-0be0-4478-85e7-81d0254b3876
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734718397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.734718397
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3803240973
Short name T205
Test name
Test status
Simulation time 11667285234 ps
CPU time 39.09 seconds
Started Jun 30 04:46:57 PM PDT 24
Finished Jun 30 04:47:37 PM PDT 24
Peak memory 219304 kb
Host smart-207ad9af-e1f6-4b24-ae0a-865f3d80732a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803240973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3803240973
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1943057287
Short name T256
Test name
Test status
Simulation time 524979813 ps
CPU time 11.96 seconds
Started Jun 30 04:46:59 PM PDT 24
Finished Jun 30 04:47:11 PM PDT 24
Peak memory 219216 kb
Host smart-92499557-0360-4f14-9715-7a3fb54e4752
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1943057287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1943057287
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.4035636277
Short name T214
Test name
Test status
Simulation time 366852011 ps
CPU time 19.79 seconds
Started Jun 30 04:46:57 PM PDT 24
Finished Jun 30 04:47:17 PM PDT 24
Peak memory 216048 kb
Host smart-61853e67-33ec-4251-accd-edca388cd32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035636277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.4035636277
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1431776081
Short name T334
Test name
Test status
Simulation time 68258299075 ps
CPU time 168.99 seconds
Started Jun 30 04:46:55 PM PDT 24
Finished Jun 30 04:49:45 PM PDT 24
Peak memory 219320 kb
Host smart-77c5d65d-6ef7-4c00-ba81-ce72219207a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431776081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1431776081
Directory /workspace/9.rom_ctrl_stress_all/latest
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