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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.28 96.89 92.13 97.68 100.00 98.62 97.30 98.37


Total test records in report: 456
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T28 /workspace/coverage/default/2.rom_ctrl_sec_cm.1476202675 Jul 01 10:50:07 AM PDT 24 Jul 01 10:54:00 AM PDT 24 623846528 ps
T300 /workspace/coverage/default/6.rom_ctrl_alert_test.2973056216 Jul 01 10:50:12 AM PDT 24 Jul 01 10:50:47 AM PDT 24 17256347730 ps
T301 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3403249799 Jul 01 10:50:41 AM PDT 24 Jul 01 10:51:24 AM PDT 24 7695020640 ps
T302 /workspace/coverage/default/25.rom_ctrl_smoke.67293560 Jul 01 10:50:32 AM PDT 24 Jul 01 10:51:38 AM PDT 24 8551194583 ps
T303 /workspace/coverage/default/10.rom_ctrl_stress_all.3783340608 Jul 01 10:50:45 AM PDT 24 Jul 01 10:51:56 AM PDT 24 17799005720 ps
T304 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3876094083 Jul 01 10:50:57 AM PDT 24 Jul 01 10:51:16 AM PDT 24 3757163006 ps
T305 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1265574747 Jul 01 10:50:13 AM PDT 24 Jul 01 10:56:32 AM PDT 24 32146108117 ps
T306 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2952410873 Jul 01 10:50:35 AM PDT 24 Jul 01 10:50:59 AM PDT 24 1034322621 ps
T307 /workspace/coverage/default/8.rom_ctrl_smoke.2893349688 Jul 01 10:50:19 AM PDT 24 Jul 01 10:50:57 AM PDT 24 2398561135 ps
T308 /workspace/coverage/default/4.rom_ctrl_alert_test.1007445831 Jul 01 10:50:12 AM PDT 24 Jul 01 10:50:37 AM PDT 24 8255211076 ps
T309 /workspace/coverage/default/25.rom_ctrl_alert_test.1769289331 Jul 01 10:50:29 AM PDT 24 Jul 01 10:50:49 AM PDT 24 12278202803 ps
T63 /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.3235832025 Jul 01 10:50:37 AM PDT 24 Jul 01 10:55:30 AM PDT 24 11453503743 ps
T310 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3010760521 Jul 01 10:50:22 AM PDT 24 Jul 01 10:50:46 AM PDT 24 2437736501 ps
T311 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2831137868 Jul 01 10:50:39 AM PDT 24 Jul 01 10:51:10 AM PDT 24 3963374880 ps
T312 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.145087387 Jul 01 10:50:12 AM PDT 24 Jul 01 10:50:48 AM PDT 24 34154844456 ps
T313 /workspace/coverage/default/18.rom_ctrl_alert_test.1832261894 Jul 01 10:50:21 AM PDT 24 Jul 01 10:50:40 AM PDT 24 10747974327 ps
T314 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1037273014 Jul 01 10:50:35 AM PDT 24 Jul 01 10:51:29 AM PDT 24 5747736950 ps
T315 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2982434832 Jul 01 10:50:59 AM PDT 24 Jul 01 10:51:20 AM PDT 24 349994640 ps
T316 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2337313190 Jul 01 10:50:58 AM PDT 24 Jul 01 10:57:28 AM PDT 24 41302507327 ps
T317 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1347277341 Jul 01 10:50:58 AM PDT 24 Jul 01 10:51:19 AM PDT 24 704495638 ps
T64 /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.2656217902 Jul 01 10:50:57 AM PDT 24 Jul 01 12:06:04 PM PDT 24 52554971556 ps
T318 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1683032992 Jul 01 10:50:12 AM PDT 24 Jul 01 10:53:49 AM PDT 24 17935201347 ps
T319 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3345451788 Jul 01 10:50:45 AM PDT 24 Jul 01 10:55:18 AM PDT 24 6769247292 ps
T320 /workspace/coverage/default/24.rom_ctrl_alert_test.2016730770 Jul 01 10:50:29 AM PDT 24 Jul 01 10:50:40 AM PDT 24 1376834344 ps
T321 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.647868278 Jul 01 10:50:40 AM PDT 24 Jul 01 10:51:13 AM PDT 24 3957395539 ps
T322 /workspace/coverage/default/39.rom_ctrl_smoke.2138003566 Jul 01 10:50:58 AM PDT 24 Jul 01 10:51:40 AM PDT 24 3630319674 ps
T323 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1121031692 Jul 01 10:50:59 AM PDT 24 Jul 01 10:51:15 AM PDT 24 621506018 ps
T324 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2623824711 Jul 01 10:50:54 AM PDT 24 Jul 01 10:51:12 AM PDT 24 4489985396 ps
T325 /workspace/coverage/default/26.rom_ctrl_alert_test.3922373618 Jul 01 10:50:43 AM PDT 24 Jul 01 10:50:57 AM PDT 24 768639465 ps
T326 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3440589710 Jul 01 10:50:33 AM PDT 24 Jul 01 10:51:10 AM PDT 24 16430651486 ps
T327 /workspace/coverage/default/41.rom_ctrl_stress_all.1697980729 Jul 01 10:50:47 AM PDT 24 Jul 01 10:51:26 AM PDT 24 740119954 ps
T328 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.4171448278 Jul 01 10:50:17 AM PDT 24 Jul 01 10:50:29 AM PDT 24 351534940 ps
T329 /workspace/coverage/default/0.rom_ctrl_stress_all.1959261211 Jul 01 10:49:59 AM PDT 24 Jul 01 10:50:31 AM PDT 24 3427781638 ps
T330 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1443001932 Jul 01 10:50:54 AM PDT 24 Jul 01 11:02:23 AM PDT 24 78955318134 ps
T331 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.4023991341 Jul 01 10:50:40 AM PDT 24 Jul 01 11:00:25 AM PDT 24 54099942092 ps
T332 /workspace/coverage/default/15.rom_ctrl_stress_all.2270215478 Jul 01 10:50:19 AM PDT 24 Jul 01 10:51:27 AM PDT 24 11226269605 ps
T333 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3911956636 Jul 01 10:50:56 AM PDT 24 Jul 01 10:51:18 AM PDT 24 7255841364 ps
T334 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2722637639 Jul 01 10:50:03 AM PDT 24 Jul 01 10:50:32 AM PDT 24 12698977691 ps
T335 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.694879622 Jul 01 10:50:38 AM PDT 24 Jul 01 10:51:05 AM PDT 24 17367509484 ps
T336 /workspace/coverage/default/49.rom_ctrl_alert_test.1702957339 Jul 01 10:50:57 AM PDT 24 Jul 01 10:51:18 AM PDT 24 30124150465 ps
T56 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1737520588 Jul 01 10:50:16 AM PDT 24 Jul 01 10:51:12 AM PDT 24 55773817705 ps
T337 /workspace/coverage/default/37.rom_ctrl_stress_all.1565037544 Jul 01 10:50:56 AM PDT 24 Jul 01 10:52:16 AM PDT 24 6254335323 ps
T338 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2573126960 Jul 01 10:50:56 AM PDT 24 Jul 01 10:51:25 AM PDT 24 12730054323 ps
T339 /workspace/coverage/default/43.rom_ctrl_smoke.3799860224 Jul 01 10:50:50 AM PDT 24 Jul 01 10:51:53 AM PDT 24 26013589392 ps
T29 /workspace/coverage/default/4.rom_ctrl_sec_cm.35473099 Jul 01 10:50:10 AM PDT 24 Jul 01 10:52:37 AM PDT 24 42396454834 ps
T340 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2537002965 Jul 01 10:50:50 AM PDT 24 Jul 01 11:00:48 AM PDT 24 49994239297 ps
T341 /workspace/coverage/default/33.rom_ctrl_alert_test.2801880978 Jul 01 10:50:35 AM PDT 24 Jul 01 10:51:05 AM PDT 24 3637562188 ps
T342 /workspace/coverage/default/13.rom_ctrl_alert_test.1577472581 Jul 01 10:50:21 AM PDT 24 Jul 01 10:50:53 AM PDT 24 8531436895 ps
T343 /workspace/coverage/default/13.rom_ctrl_stress_all.1028872368 Jul 01 10:50:12 AM PDT 24 Jul 01 10:50:36 AM PDT 24 2338286279 ps
T344 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1166578107 Jul 01 10:50:13 AM PDT 24 Jul 01 10:50:39 AM PDT 24 5933408592 ps
T345 /workspace/coverage/default/37.rom_ctrl_alert_test.312383325 Jul 01 10:50:57 AM PDT 24 Jul 01 10:51:27 AM PDT 24 3195210493 ps
T346 /workspace/coverage/default/47.rom_ctrl_stress_all.1323197789 Jul 01 10:51:00 AM PDT 24 Jul 01 10:52:39 AM PDT 24 39655495288 ps
T347 /workspace/coverage/default/44.rom_ctrl_alert_test.573946222 Jul 01 10:50:56 AM PDT 24 Jul 01 10:51:17 AM PDT 24 8186212661 ps
T348 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1897144291 Jul 01 10:50:59 AM PDT 24 Jul 01 10:51:32 AM PDT 24 3848056205 ps
T349 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2385223944 Jul 01 10:50:19 AM PDT 24 Jul 01 11:01:00 AM PDT 24 53451269579 ps
T350 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.848677682 Jul 01 10:50:09 AM PDT 24 Jul 01 11:00:50 AM PDT 24 174449332808 ps
T351 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3573430423 Jul 01 10:50:32 AM PDT 24 Jul 01 10:50:57 AM PDT 24 5064317015 ps
T352 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1037497577 Jul 01 10:50:59 AM PDT 24 Jul 01 10:51:11 AM PDT 24 728419294 ps
T353 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2095795941 Jul 01 10:51:00 AM PDT 24 Jul 01 10:52:00 AM PDT 24 37045286087 ps
T354 /workspace/coverage/default/37.rom_ctrl_smoke.2341409965 Jul 01 10:50:57 AM PDT 24 Jul 01 10:51:47 AM PDT 24 4764385791 ps
T355 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.784490838 Jul 01 10:50:40 AM PDT 24 Jul 01 10:51:35 AM PDT 24 27552123639 ps
T356 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2225948129 Jul 01 10:32:54 AM PDT 24 Jul 01 10:33:09 AM PDT 24 1195474858 ps
T76 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2258882797 Jul 01 10:32:55 AM PDT 24 Jul 01 10:33:22 AM PDT 24 8158365119 ps
T77 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1781751397 Jul 01 10:33:05 AM PDT 24 Jul 01 10:34:37 AM PDT 24 37028731717 ps
T78 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2924913732 Jul 01 10:33:06 AM PDT 24 Jul 01 10:33:15 AM PDT 24 750138808 ps
T81 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3628690232 Jul 01 10:33:10 AM PDT 24 Jul 01 10:34:08 AM PDT 24 1081153255 ps
T82 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1412537416 Jul 01 10:33:09 AM PDT 24 Jul 01 10:34:17 AM PDT 24 4740867556 ps
T83 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2893035461 Jul 01 10:32:54 AM PDT 24 Jul 01 10:33:19 AM PDT 24 2997749133 ps
T84 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2936432181 Jul 01 10:33:03 AM PDT 24 Jul 01 10:34:55 AM PDT 24 191694472350 ps
T65 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.4015278517 Jul 01 10:33:15 AM PDT 24 Jul 01 10:33:37 AM PDT 24 1334187058 ps
T357 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.388943432 Jul 01 10:33:02 AM PDT 24 Jul 01 10:33:18 AM PDT 24 2297494155 ps
T72 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2268366996 Jul 01 10:33:12 AM PDT 24 Jul 01 10:34:33 AM PDT 24 484126948 ps
T85 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3381011909 Jul 01 10:33:09 AM PDT 24 Jul 01 10:33:40 AM PDT 24 22015728897 ps
T358 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.97401729 Jul 01 10:33:20 AM PDT 24 Jul 01 10:33:32 AM PDT 24 1409341703 ps
T359 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.36929214 Jul 01 10:33:14 AM PDT 24 Jul 01 10:33:35 AM PDT 24 1549967001 ps
T360 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1714449360 Jul 01 10:33:13 AM PDT 24 Jul 01 10:33:50 AM PDT 24 8719765374 ps
T361 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3870722775 Jul 01 10:33:20 AM PDT 24 Jul 01 10:33:40 AM PDT 24 6875694357 ps
T362 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3541465269 Jul 01 10:33:14 AM PDT 24 Jul 01 10:33:34 AM PDT 24 3344610397 ps
T103 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3134698492 Jul 01 10:33:18 AM PDT 24 Jul 01 10:34:31 AM PDT 24 39850532425 ps
T86 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1997709811 Jul 01 10:33:08 AM PDT 24 Jul 01 10:33:17 AM PDT 24 174442397 ps
T73 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2872900545 Jul 01 10:33:08 AM PDT 24 Jul 01 10:35:48 AM PDT 24 7017745319 ps
T363 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.204018790 Jul 01 10:33:06 AM PDT 24 Jul 01 10:33:16 AM PDT 24 688422850 ps
T104 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3211082788 Jul 01 10:33:11 AM PDT 24 Jul 01 10:33:36 AM PDT 24 8458083096 ps
T87 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2792323300 Jul 01 10:33:07 AM PDT 24 Jul 01 10:35:43 AM PDT 24 18072624244 ps
T74 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3971429868 Jul 01 10:33:08 AM PDT 24 Jul 01 10:34:38 AM PDT 24 6527763566 ps
T88 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3412134485 Jul 01 10:32:55 AM PDT 24 Jul 01 10:33:34 AM PDT 24 709190922 ps
T108 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.4022422798 Jul 01 10:33:11 AM PDT 24 Jul 01 10:35:49 AM PDT 24 1193762021 ps
T109 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2658698687 Jul 01 10:33:08 AM PDT 24 Jul 01 10:34:52 AM PDT 24 15958543428 ps
T113 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1101969666 Jul 01 10:33:09 AM PDT 24 Jul 01 10:34:42 AM PDT 24 16782310194 ps
T364 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1010021189 Jul 01 10:33:10 AM PDT 24 Jul 01 10:33:44 AM PDT 24 3894951742 ps
T365 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1542780921 Jul 01 10:33:03 AM PDT 24 Jul 01 10:33:19 AM PDT 24 2119737159 ps
T89 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1111846246 Jul 01 10:33:13 AM PDT 24 Jul 01 10:33:24 AM PDT 24 688603667 ps
T105 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1812146025 Jul 01 10:33:07 AM PDT 24 Jul 01 10:33:40 AM PDT 24 6893138695 ps
T366 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3626374239 Jul 01 10:32:58 AM PDT 24 Jul 01 10:33:27 AM PDT 24 19821250197 ps
T110 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1984086310 Jul 01 10:33:09 AM PDT 24 Jul 01 10:36:05 AM PDT 24 7497402548 ps
T106 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.790207173 Jul 01 10:33:10 AM PDT 24 Jul 01 10:33:23 AM PDT 24 1971269307 ps
T367 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.826311033 Jul 01 10:33:13 AM PDT 24 Jul 01 10:33:32 AM PDT 24 7767489768 ps
T121 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4272099640 Jul 01 10:33:11 AM PDT 24 Jul 01 10:36:00 AM PDT 24 11030618079 ps
T368 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.194747557 Jul 01 10:32:54 AM PDT 24 Jul 01 10:34:13 AM PDT 24 34815410382 ps
T369 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3239539050 Jul 01 10:33:11 AM PDT 24 Jul 01 10:33:30 AM PDT 24 7649479296 ps
T370 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.203790924 Jul 01 10:33:11 AM PDT 24 Jul 01 10:33:47 AM PDT 24 17142369862 ps
T100 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.33572713 Jul 01 10:33:14 AM PDT 24 Jul 01 10:33:41 AM PDT 24 12265418060 ps
T371 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2763223433 Jul 01 10:32:54 AM PDT 24 Jul 01 10:33:24 AM PDT 24 12815552022 ps
T372 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2398346666 Jul 01 10:33:11 AM PDT 24 Jul 01 10:33:49 AM PDT 24 18862470790 ps
T93 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.838763136 Jul 01 10:33:12 AM PDT 24 Jul 01 10:35:02 AM PDT 24 30954329805 ps
T94 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4147337779 Jul 01 10:33:13 AM PDT 24 Jul 01 10:34:13 AM PDT 24 21368859556 ps
T373 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.398365075 Jul 01 10:33:08 AM PDT 24 Jul 01 10:33:30 AM PDT 24 6618408104 ps
T374 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1005967574 Jul 01 10:33:11 AM PDT 24 Jul 01 10:33:21 AM PDT 24 176337669 ps
T375 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.4138615912 Jul 01 10:32:53 AM PDT 24 Jul 01 10:33:10 AM PDT 24 1476628881 ps
T376 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3725637303 Jul 01 10:33:17 AM PDT 24 Jul 01 10:34:48 AM PDT 24 6714179975 ps
T377 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1292731542 Jul 01 10:33:03 AM PDT 24 Jul 01 10:33:28 AM PDT 24 5552699736 ps
T378 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.707063741 Jul 01 10:33:07 AM PDT 24 Jul 01 10:33:16 AM PDT 24 313817701 ps
T379 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2295508770 Jul 01 10:33:07 AM PDT 24 Jul 01 10:33:40 AM PDT 24 14248905437 ps
T380 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.619764021 Jul 01 10:33:14 AM PDT 24 Jul 01 10:33:27 AM PDT 24 172807491 ps
T381 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2909014564 Jul 01 10:33:07 AM PDT 24 Jul 01 10:33:16 AM PDT 24 332094476 ps
T382 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.4294759977 Jul 01 10:33:06 AM PDT 24 Jul 01 10:33:18 AM PDT 24 167651541 ps
T119 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3349869766 Jul 01 10:33:00 AM PDT 24 Jul 01 10:35:38 AM PDT 24 3291836020 ps
T383 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1255525101 Jul 01 10:32:49 AM PDT 24 Jul 01 10:33:27 AM PDT 24 8526663869 ps
T116 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1192887182 Jul 01 10:33:19 AM PDT 24 Jul 01 10:34:53 AM PDT 24 3345677204 ps
T384 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.160110919 Jul 01 10:33:20 AM PDT 24 Jul 01 10:33:59 AM PDT 24 4223768331 ps
T385 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.484174524 Jul 01 10:32:52 AM PDT 24 Jul 01 10:33:00 AM PDT 24 1376309880 ps
T386 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1408438994 Jul 01 10:33:06 AM PDT 24 Jul 01 10:35:11 AM PDT 24 35616285891 ps
T387 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2044555443 Jul 01 10:32:52 AM PDT 24 Jul 01 10:33:26 AM PDT 24 18490075136 ps
T118 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1542731873 Jul 01 10:33:11 AM PDT 24 Jul 01 10:35:56 AM PDT 24 2410975364 ps
T388 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3219270216 Jul 01 10:33:13 AM PDT 24 Jul 01 10:33:39 AM PDT 24 2632222924 ps
T95 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3635639432 Jul 01 10:33:12 AM PDT 24 Jul 01 10:35:59 AM PDT 24 35445048405 ps
T389 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3776989192 Jul 01 10:33:01 AM PDT 24 Jul 01 10:34:21 AM PDT 24 26339893120 ps
T390 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1168884782 Jul 01 10:33:07 AM PDT 24 Jul 01 10:33:17 AM PDT 24 186333952 ps
T391 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.744074941 Jul 01 10:33:09 AM PDT 24 Jul 01 10:33:30 AM PDT 24 1457709293 ps
T392 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1026608137 Jul 01 10:33:09 AM PDT 24 Jul 01 10:33:26 AM PDT 24 1275572564 ps
T393 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1197229134 Jul 01 10:32:54 AM PDT 24 Jul 01 10:33:18 AM PDT 24 8770448533 ps
T394 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2978077747 Jul 01 10:33:00 AM PDT 24 Jul 01 10:33:25 AM PDT 24 26926166618 ps
T395 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2353457057 Jul 01 10:33:07 AM PDT 24 Jul 01 10:33:39 AM PDT 24 6838853282 ps
T396 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2825693043 Jul 01 10:33:00 AM PDT 24 Jul 01 10:33:12 AM PDT 24 980897110 ps
T96 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.23561043 Jul 01 10:33:15 AM PDT 24 Jul 01 10:33:54 AM PDT 24 690997350 ps
T397 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.422022547 Jul 01 10:33:14 AM PDT 24 Jul 01 10:33:51 AM PDT 24 4293179145 ps
T398 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.916494962 Jul 01 10:33:19 AM PDT 24 Jul 01 10:33:30 AM PDT 24 737003572 ps
T399 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.4249518207 Jul 01 10:33:17 AM PDT 24 Jul 01 10:33:31 AM PDT 24 1217471522 ps
T97 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.231459111 Jul 01 10:33:19 AM PDT 24 Jul 01 10:33:57 AM PDT 24 2882856587 ps
T400 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.870832243 Jul 01 10:33:07 AM PDT 24 Jul 01 10:33:35 AM PDT 24 5689648787 ps
T401 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3119553652 Jul 01 10:33:11 AM PDT 24 Jul 01 10:33:28 AM PDT 24 526285576 ps
T98 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2432382834 Jul 01 10:32:54 AM PDT 24 Jul 01 10:33:27 AM PDT 24 16476731916 ps
T99 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3633787682 Jul 01 10:32:56 AM PDT 24 Jul 01 10:33:33 AM PDT 24 3718187955 ps
T402 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.267827812 Jul 01 10:32:49 AM PDT 24 Jul 01 10:33:18 AM PDT 24 3340969877 ps
T111 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1637710652 Jul 01 10:32:54 AM PDT 24 Jul 01 10:35:32 AM PDT 24 5244525264 ps
T403 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3080193301 Jul 01 10:33:11 AM PDT 24 Jul 01 10:33:42 AM PDT 24 14298689893 ps
T404 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.20085623 Jul 01 10:32:54 AM PDT 24 Jul 01 10:33:13 AM PDT 24 594818203 ps
T405 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2761946394 Jul 01 10:32:54 AM PDT 24 Jul 01 10:33:25 AM PDT 24 3957408737 ps
T406 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3326838560 Jul 01 10:32:59 AM PDT 24 Jul 01 10:33:22 AM PDT 24 10954458063 ps
T407 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.97695119 Jul 01 10:33:11 AM PDT 24 Jul 01 10:33:35 AM PDT 24 3275744166 ps
T408 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2049541178 Jul 01 10:33:16 AM PDT 24 Jul 01 10:35:42 AM PDT 24 31337932371 ps
T117 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3878021802 Jul 01 10:33:23 AM PDT 24 Jul 01 10:36:02 AM PDT 24 6386798328 ps
T112 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4199669306 Jul 01 10:33:07 AM PDT 24 Jul 01 10:34:30 AM PDT 24 351251659 ps
T409 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2925276874 Jul 01 10:33:12 AM PDT 24 Jul 01 10:33:27 AM PDT 24 1367376802 ps
T410 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2277243851 Jul 01 10:33:14 AM PDT 24 Jul 01 10:33:37 AM PDT 24 2318154508 ps
T114 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2987470886 Jul 01 10:32:58 AM PDT 24 Jul 01 10:35:49 AM PDT 24 7546881862 ps
T411 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1563279407 Jul 01 10:32:52 AM PDT 24 Jul 01 10:33:19 AM PDT 24 6223813461 ps
T412 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3195877747 Jul 01 10:33:13 AM PDT 24 Jul 01 10:33:38 AM PDT 24 2571449794 ps
T413 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2677446294 Jul 01 10:32:50 AM PDT 24 Jul 01 10:33:07 AM PDT 24 2349950120 ps
T414 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4245984675 Jul 01 10:33:03 AM PDT 24 Jul 01 10:33:12 AM PDT 24 176776650 ps
T415 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.710481332 Jul 01 10:33:36 AM PDT 24 Jul 01 10:34:01 AM PDT 24 5781709283 ps
T416 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2457962395 Jul 01 10:33:10 AM PDT 24 Jul 01 10:33:30 AM PDT 24 1907314590 ps
T102 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.382537099 Jul 01 10:33:01 AM PDT 24 Jul 01 10:34:49 AM PDT 24 52975493740 ps
T417 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3895282226 Jul 01 10:33:07 AM PDT 24 Jul 01 10:35:08 AM PDT 24 62944045056 ps
T418 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3475809043 Jul 01 10:33:07 AM PDT 24 Jul 01 10:33:29 AM PDT 24 1974065740 ps
T419 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1425277046 Jul 01 10:32:54 AM PDT 24 Jul 01 10:33:05 AM PDT 24 250599159 ps
T420 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.149693355 Jul 01 10:33:15 AM PDT 24 Jul 01 10:33:49 AM PDT 24 25110412205 ps
T421 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.29454081 Jul 01 10:33:04 AM PDT 24 Jul 01 10:33:22 AM PDT 24 8184171247 ps
T422 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4249541313 Jul 01 10:33:13 AM PDT 24 Jul 01 10:33:23 AM PDT 24 736930602 ps
T423 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2938384647 Jul 01 10:33:10 AM PDT 24 Jul 01 10:33:34 AM PDT 24 5834279695 ps
T424 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3977466459 Jul 01 10:33:06 AM PDT 24 Jul 01 10:33:25 AM PDT 24 6553262523 ps
T425 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3314864986 Jul 01 10:33:11 AM PDT 24 Jul 01 10:33:30 AM PDT 24 3081673442 ps
T426 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2018927982 Jul 01 10:32:52 AM PDT 24 Jul 01 10:33:01 AM PDT 24 1647515373 ps
T427 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3987955414 Jul 01 10:33:16 AM PDT 24 Jul 01 10:33:26 AM PDT 24 365324834 ps
T428 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1960060722 Jul 01 10:33:09 AM PDT 24 Jul 01 10:34:39 AM PDT 24 16459339305 ps
T429 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.610568655 Jul 01 10:33:12 AM PDT 24 Jul 01 10:33:28 AM PDT 24 2510432627 ps
T430 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1079577933 Jul 01 10:33:11 AM PDT 24 Jul 01 10:33:22 AM PDT 24 172505992 ps
T431 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4051977560 Jul 01 10:33:05 AM PDT 24 Jul 01 10:33:26 AM PDT 24 3438661990 ps
T432 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3771695558 Jul 01 10:33:07 AM PDT 24 Jul 01 10:33:41 AM PDT 24 4298207913 ps
T120 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2885411526 Jul 01 10:32:54 AM PDT 24 Jul 01 10:35:25 AM PDT 24 1150764635 ps
T115 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.500895820 Jul 01 10:33:03 AM PDT 24 Jul 01 10:35:46 AM PDT 24 32065041273 ps
T433 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.599830147 Jul 01 10:33:13 AM PDT 24 Jul 01 10:33:44 AM PDT 24 3840092537 ps
T101 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1851464727 Jul 01 10:33:15 AM PDT 24 Jul 01 10:33:25 AM PDT 24 176024582 ps
T434 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.131982846 Jul 01 10:33:12 AM PDT 24 Jul 01 10:33:46 AM PDT 24 3776478905 ps
T435 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.760750813 Jul 01 10:33:11 AM PDT 24 Jul 01 10:33:34 AM PDT 24 2265474422 ps
T436 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2063969217 Jul 01 10:33:11 AM PDT 24 Jul 01 10:33:39 AM PDT 24 3068794486 ps
T437 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2625383086 Jul 01 10:33:14 AM PDT 24 Jul 01 10:33:39 AM PDT 24 3323154476 ps
T438 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2315317727 Jul 01 10:33:13 AM PDT 24 Jul 01 10:35:54 AM PDT 24 3199361270 ps
T439 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2970459306 Jul 01 10:33:18 AM PDT 24 Jul 01 10:35:12 AM PDT 24 37059856569 ps
T440 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2736130164 Jul 01 10:33:02 AM PDT 24 Jul 01 10:33:37 AM PDT 24 20067471290 ps
T441 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2412604136 Jul 01 10:33:10 AM PDT 24 Jul 01 10:33:31 AM PDT 24 1861931284 ps
T442 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3089134152 Jul 01 10:32:49 AM PDT 24 Jul 01 10:33:19 AM PDT 24 21696167662 ps
T443 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.942148237 Jul 01 10:32:59 AM PDT 24 Jul 01 10:33:23 AM PDT 24 2705091039 ps
T444 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.815855125 Jul 01 10:33:15 AM PDT 24 Jul 01 10:33:26 AM PDT 24 998586884 ps
T445 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3284534997 Jul 01 10:33:12 AM PDT 24 Jul 01 10:35:50 AM PDT 24 4984356376 ps
T446 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3274717451 Jul 01 10:33:09 AM PDT 24 Jul 01 10:33:25 AM PDT 24 1132220742 ps
T447 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1750013933 Jul 01 10:33:24 AM PDT 24 Jul 01 10:34:00 AM PDT 24 16001910947 ps
T448 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1355646327 Jul 01 10:33:12 AM PDT 24 Jul 01 10:33:48 AM PDT 24 4973630525 ps
T449 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.213398134 Jul 01 10:33:13 AM PDT 24 Jul 01 10:33:42 AM PDT 24 6530061586 ps
T450 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3471169647 Jul 01 10:33:14 AM PDT 24 Jul 01 10:33:42 AM PDT 24 2966646008 ps
T451 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1563069845 Jul 01 10:33:07 AM PDT 24 Jul 01 10:33:26 AM PDT 24 1467896520 ps
T452 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2842869316 Jul 01 10:32:56 AM PDT 24 Jul 01 10:33:09 AM PDT 24 1199542613 ps
T453 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1181199704 Jul 01 10:33:05 AM PDT 24 Jul 01 10:33:33 AM PDT 24 12121685410 ps
T454 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1452770396 Jul 01 10:33:11 AM PDT 24 Jul 01 10:33:28 AM PDT 24 1367018658 ps
T455 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1534869842 Jul 01 10:33:10 AM PDT 24 Jul 01 10:33:43 AM PDT 24 12071948012 ps
T456 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.42911012 Jul 01 10:32:53 AM PDT 24 Jul 01 10:33:06 AM PDT 24 7012957628 ps

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1646237492
Short name T6
Test name
Test status
Simulation time 17313068786 ps
CPU time 177.78 seconds
Started Jul 01 10:51:01 AM PDT 24
Finished Jul 01 10:54:00 AM PDT 24
Peak memory 221884 kb
Host smart-d681f5f0-a80b-4bb9-8d1b-fefc161ef50a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646237492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1646237492
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.3396639167
Short name T13
Test name
Test status
Simulation time 166020413823 ps
CPU time 1806 seconds
Started Jul 01 10:51:07 AM PDT 24
Finished Jul 01 11:21:14 AM PDT 24
Peak memory 244996 kb
Host smart-918e0c02-8bda-4252-b5be-8ed255378958
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396639167 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.3396639167
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1483936192
Short name T19
Test name
Test status
Simulation time 188704145202 ps
CPU time 561.68 seconds
Started Jul 01 10:51:00 AM PDT 24
Finished Jul 01 11:00:23 AM PDT 24
Peak memory 218624 kb
Host smart-3db22ba2-472f-4063-b1f2-adcea756366b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483936192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1483936192
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3396515430
Short name T53
Test name
Test status
Simulation time 17168607209 ps
CPU time 68.32 seconds
Started Jul 01 10:50:55 AM PDT 24
Finished Jul 01 10:52:04 AM PDT 24
Peak memory 217964 kb
Host smart-bf9bfacf-e61d-49df-b6ee-36d93181ea44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396515430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3396515430
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3783978164
Short name T18
Test name
Test status
Simulation time 10139146179 ps
CPU time 177.66 seconds
Started Jul 01 10:50:12 AM PDT 24
Finished Jul 01 10:53:13 AM PDT 24
Peak memory 238204 kb
Host smart-8bcf5624-b1c6-43ca-b445-29cac48ef64d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783978164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3783978164
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2872900545
Short name T73
Test name
Test status
Simulation time 7017745319 ps
CPU time 159.76 seconds
Started Jul 01 10:33:08 AM PDT 24
Finished Jul 01 10:35:48 AM PDT 24
Peak memory 218844 kb
Host smart-4949a61a-4883-4a49-a417-c767aec40642
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872900545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2872900545
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.1995839452
Short name T15
Test name
Test status
Simulation time 174769384936 ps
CPU time 959.73 seconds
Started Jul 01 10:50:35 AM PDT 24
Finished Jul 01 11:06:35 AM PDT 24
Peak memory 235816 kb
Host smart-11333627-3fc3-4260-bcd3-3e62c5c51180
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995839452 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.1995839452
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2768107529
Short name T21
Test name
Test status
Simulation time 2132654617 ps
CPU time 128.83 seconds
Started Jul 01 10:50:11 AM PDT 24
Finished Jul 01 10:52:23 AM PDT 24
Peak memory 237424 kb
Host smart-c2d72f07-7e50-49d2-8d1b-e4c66b413f82
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768107529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2768107529
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1781751397
Short name T77
Test name
Test status
Simulation time 37028731717 ps
CPU time 91.41 seconds
Started Jul 01 10:33:05 AM PDT 24
Finished Jul 01 10:34:37 AM PDT 24
Peak memory 213612 kb
Host smart-411e0060-3e48-49d9-8f94-909f9135673c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781751397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1781751397
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.42950203
Short name T25
Test name
Test status
Simulation time 422437915 ps
CPU time 11.25 seconds
Started Jul 01 10:50:43 AM PDT 24
Finished Jul 01 10:50:54 AM PDT 24
Peak memory 217164 kb
Host smart-cddc86e5-0eb2-487a-a5fc-93d6f6d17920
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42950203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.42950203
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2987470886
Short name T114
Test name
Test status
Simulation time 7546881862 ps
CPU time 170.35 seconds
Started Jul 01 10:32:58 AM PDT 24
Finished Jul 01 10:35:49 AM PDT 24
Peak memory 213148 kb
Host smart-6d67d35e-61fc-4d0f-bd63-398afded96bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987470886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2987470886
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.4030202045
Short name T11
Test name
Test status
Simulation time 679260823 ps
CPU time 20.92 seconds
Started Jul 01 10:50:09 AM PDT 24
Finished Jul 01 10:50:33 AM PDT 24
Peak memory 217440 kb
Host smart-cff67239-240d-43e8-a479-a0e03b9a8d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030202045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.4030202045
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3041596626
Short name T4
Test name
Test status
Simulation time 12265570270 ps
CPU time 56.48 seconds
Started Jul 01 10:50:38 AM PDT 24
Finished Jul 01 10:51:35 AM PDT 24
Peak memory 219392 kb
Host smart-d7d1c694-1bb9-4f55-8f5f-89cbca254b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041596626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3041596626
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1103649723
Short name T8
Test name
Test status
Simulation time 7108829171 ps
CPU time 186.33 seconds
Started Jul 01 10:50:09 AM PDT 24
Finished Jul 01 10:53:18 AM PDT 24
Peak memory 233880 kb
Host smart-16961839-c9db-4dfa-83c2-b13c594d35b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103649723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1103649723
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.4286384797
Short name T217
Test name
Test status
Simulation time 661685034 ps
CPU time 19.66 seconds
Started Jul 01 10:50:26 AM PDT 24
Finished Jul 01 10:50:46 AM PDT 24
Peak memory 219292 kb
Host smart-5bcc603f-1854-4332-8f30-fef288c29e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286384797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.4286384797
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1737520588
Short name T56
Test name
Test status
Simulation time 55773817705 ps
CPU time 53.7 seconds
Started Jul 01 10:50:16 AM PDT 24
Finished Jul 01 10:51:12 AM PDT 24
Peak memory 219404 kb
Host smart-a05b1b25-28f4-4809-934c-dfbf40870150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737520588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1737520588
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3971429868
Short name T74
Test name
Test status
Simulation time 6527763566 ps
CPU time 89.18 seconds
Started Jul 01 10:33:08 AM PDT 24
Finished Jul 01 10:34:38 AM PDT 24
Peak memory 213644 kb
Host smart-0382645e-1bc5-44ed-a4c8-364610cd395e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971429868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3971429868
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1542731873
Short name T118
Test name
Test status
Simulation time 2410975364 ps
CPU time 162.69 seconds
Started Jul 01 10:33:11 AM PDT 24
Finished Jul 01 10:35:56 AM PDT 24
Peak memory 213924 kb
Host smart-f973932e-f4ed-409c-b9ab-30170479d59f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542731873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1542731873
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2432382834
Short name T98
Test name
Test status
Simulation time 16476731916 ps
CPU time 32.21 seconds
Started Jul 01 10:32:54 AM PDT 24
Finished Jul 01 10:33:27 AM PDT 24
Peak memory 211720 kb
Host smart-fec62630-759e-466e-b2de-782f235659eb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432382834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2432382834
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2792323300
Short name T87
Test name
Test status
Simulation time 18072624244 ps
CPU time 154.95 seconds
Started Jul 01 10:33:07 AM PDT 24
Finished Jul 01 10:35:43 AM PDT 24
Peak memory 215340 kb
Host smart-9f111cb4-2e1c-4e46-9626-6f202ba73b7e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792323300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2792323300
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2412604136
Short name T441
Test name
Test status
Simulation time 1861931284 ps
CPU time 19.75 seconds
Started Jul 01 10:33:10 AM PDT 24
Finished Jul 01 10:33:31 AM PDT 24
Peak memory 211160 kb
Host smart-052e356a-607d-44c6-951d-4f2b5299264e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412604136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2412604136
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1542780921
Short name T365
Test name
Test status
Simulation time 2119737159 ps
CPU time 15.31 seconds
Started Jul 01 10:33:03 AM PDT 24
Finished Jul 01 10:33:19 AM PDT 24
Peak memory 211884 kb
Host smart-b4e62bfb-fb2b-492e-8d44-2e3d6fc8d411
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542780921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1542780921
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1197229134
Short name T393
Test name
Test status
Simulation time 8770448533 ps
CPU time 23.25 seconds
Started Jul 01 10:32:54 AM PDT 24
Finished Jul 01 10:33:18 AM PDT 24
Peak memory 218472 kb
Host smart-b7ae08b3-000a-4ebe-990b-dbcacfcb1851
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197229134 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1197229134
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2924913732
Short name T78
Test name
Test status
Simulation time 750138808 ps
CPU time 8.34 seconds
Started Jul 01 10:33:06 AM PDT 24
Finished Jul 01 10:33:15 AM PDT 24
Peak memory 210508 kb
Host smart-c8ba35dd-b2dd-4978-bb02-acdaecbc96cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924913732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2924913732
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.942148237
Short name T443
Test name
Test status
Simulation time 2705091039 ps
CPU time 23.55 seconds
Started Jul 01 10:32:59 AM PDT 24
Finished Jul 01 10:33:23 AM PDT 24
Peak memory 210512 kb
Host smart-b3d87e8b-d41a-47f0-92ff-50772d6e8f7d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942148237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.942148237
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1563279407
Short name T411
Test name
Test status
Simulation time 6223813461 ps
CPU time 25.56 seconds
Started Jul 01 10:32:52 AM PDT 24
Finished Jul 01 10:33:19 AM PDT 24
Peak memory 210704 kb
Host smart-c146bfa7-6b51-4a64-a39f-8d89c7fa7684
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563279407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1563279407
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2258882797
Short name T76
Test name
Test status
Simulation time 8158365119 ps
CPU time 25.89 seconds
Started Jul 01 10:32:55 AM PDT 24
Finished Jul 01 10:33:22 AM PDT 24
Peak memory 211636 kb
Host smart-381e3aa1-929e-49ba-a4c5-19630d64f622
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258882797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2258882797
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.20085623
Short name T404
Test name
Test status
Simulation time 594818203 ps
CPU time 17.2 seconds
Started Jul 01 10:32:54 AM PDT 24
Finished Jul 01 10:33:13 AM PDT 24
Peak memory 218432 kb
Host smart-8c950350-f229-46d2-8aa0-e39190a7a695
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20085623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.20085623
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.267827812
Short name T402
Test name
Test status
Simulation time 3340969877 ps
CPU time 27.67 seconds
Started Jul 01 10:32:49 AM PDT 24
Finished Jul 01 10:33:18 AM PDT 24
Peak memory 211260 kb
Host smart-c4989d9b-19cb-4fd1-8daf-0cda90b13823
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267827812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.267827812
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3475809043
Short name T418
Test name
Test status
Simulation time 1974065740 ps
CPU time 20.35 seconds
Started Jul 01 10:33:07 AM PDT 24
Finished Jul 01 10:33:29 AM PDT 24
Peak memory 211236 kb
Host smart-7e67048b-07a3-4494-af4a-ef1c879fcf5d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475809043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3475809043
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1255525101
Short name T383
Test name
Test status
Simulation time 8526663869 ps
CPU time 38.03 seconds
Started Jul 01 10:32:49 AM PDT 24
Finished Jul 01 10:33:27 AM PDT 24
Peak memory 211744 kb
Host smart-5d7ea708-5bbb-4d90-ad15-e3ad96ffc528
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255525101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1255525101
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2063969217
Short name T436
Test name
Test status
Simulation time 3068794486 ps
CPU time 26.39 seconds
Started Jul 01 10:33:11 AM PDT 24
Finished Jul 01 10:33:39 AM PDT 24
Peak memory 216720 kb
Host smart-c60a9c3c-4ddb-47cc-8218-0a7a4c47755d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063969217 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2063969217
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3326838560
Short name T406
Test name
Test status
Simulation time 10954458063 ps
CPU time 22.82 seconds
Started Jul 01 10:32:59 AM PDT 24
Finished Jul 01 10:33:22 AM PDT 24
Peak memory 212068 kb
Host smart-5b92a31c-c30e-4ffa-83cb-dc823b408cf1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326838560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3326838560
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2225948129
Short name T356
Test name
Test status
Simulation time 1195474858 ps
CPU time 15.03 seconds
Started Jul 01 10:32:54 AM PDT 24
Finished Jul 01 10:33:09 AM PDT 24
Peak memory 210444 kb
Host smart-7e07e559-93eb-44f6-8769-aa7f8d7e474e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225948129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2225948129
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2763223433
Short name T371
Test name
Test status
Simulation time 12815552022 ps
CPU time 28.41 seconds
Started Jul 01 10:32:54 AM PDT 24
Finished Jul 01 10:33:24 AM PDT 24
Peak memory 210824 kb
Host smart-a941bc87-df57-42f5-be03-2fd1c55138d7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763223433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2763223433
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3412134485
Short name T88
Test name
Test status
Simulation time 709190922 ps
CPU time 37.46 seconds
Started Jul 01 10:32:55 AM PDT 24
Finished Jul 01 10:33:34 AM PDT 24
Peak memory 213844 kb
Host smart-1590f2d4-3ac5-4f1d-9786-c53fb36084da
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412134485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3412134485
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2677446294
Short name T413
Test name
Test status
Simulation time 2349950120 ps
CPU time 16.32 seconds
Started Jul 01 10:32:50 AM PDT 24
Finished Jul 01 10:33:07 AM PDT 24
Peak memory 212408 kb
Host smart-f46b607b-e34e-4bac-9b35-ee38ef6952ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677446294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2677446294
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2736130164
Short name T440
Test name
Test status
Simulation time 20067471290 ps
CPU time 35.21 seconds
Started Jul 01 10:33:02 AM PDT 24
Finished Jul 01 10:33:37 AM PDT 24
Peak memory 217588 kb
Host smart-e3292130-ecc0-40ee-ab50-ff5e23459280
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736130164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2736130164
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1101969666
Short name T113
Test name
Test status
Simulation time 16782310194 ps
CPU time 91.6 seconds
Started Jul 01 10:33:09 AM PDT 24
Finished Jul 01 10:34:42 AM PDT 24
Peak memory 213700 kb
Host smart-c52b2b9a-5cdd-4d3f-8650-b6b2d28a1426
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101969666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1101969666
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3195877747
Short name T412
Test name
Test status
Simulation time 2571449794 ps
CPU time 22.79 seconds
Started Jul 01 10:33:13 AM PDT 24
Finished Jul 01 10:33:38 AM PDT 24
Peak memory 217748 kb
Host smart-ed5d4ec7-d457-4091-90cf-7fabf17963c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195877747 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3195877747
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1452770396
Short name T454
Test name
Test status
Simulation time 1367018658 ps
CPU time 14.77 seconds
Started Jul 01 10:33:11 AM PDT 24
Finished Jul 01 10:33:28 AM PDT 24
Peak memory 210972 kb
Host smart-8468c64b-76ac-42cd-9fc4-e307bbe8edf7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452770396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1452770396
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1408438994
Short name T386
Test name
Test status
Simulation time 35616285891 ps
CPU time 124.11 seconds
Started Jul 01 10:33:06 AM PDT 24
Finished Jul 01 10:35:11 AM PDT 24
Peak memory 214908 kb
Host smart-8f50744d-9580-425e-9947-1e7857df2a42
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408438994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1408438994
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.131982846
Short name T434
Test name
Test status
Simulation time 3776478905 ps
CPU time 32.59 seconds
Started Jul 01 10:33:12 AM PDT 24
Finished Jul 01 10:33:46 AM PDT 24
Peak memory 212272 kb
Host smart-0ebf6f3a-6aa7-4905-9990-e8128955cba5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131982846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.131982846
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.97695119
Short name T407
Test name
Test status
Simulation time 3275744166 ps
CPU time 21.79 seconds
Started Jul 01 10:33:11 AM PDT 24
Finished Jul 01 10:33:35 AM PDT 24
Peak memory 218264 kb
Host smart-17b9acf0-5060-4917-8c27-edf066045435
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97695119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.97695119
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4249541313
Short name T422
Test name
Test status
Simulation time 736930602 ps
CPU time 8.58 seconds
Started Jul 01 10:33:13 AM PDT 24
Finished Jul 01 10:33:23 AM PDT 24
Peak memory 216404 kb
Host smart-663409d8-8e43-4f1c-9e73-fa62b5c37b34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249541313 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.4249541313
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.826311033
Short name T367
Test name
Test status
Simulation time 7767489768 ps
CPU time 16.94 seconds
Started Jul 01 10:33:13 AM PDT 24
Finished Jul 01 10:33:32 AM PDT 24
Peak memory 212196 kb
Host smart-42b6412a-d484-4bb8-a156-e9a3ad843515
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826311033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.826311033
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4147337779
Short name T94
Test name
Test status
Simulation time 21368859556 ps
CPU time 58.16 seconds
Started Jul 01 10:33:13 AM PDT 24
Finished Jul 01 10:34:13 AM PDT 24
Peak memory 213688 kb
Host smart-8d741808-9bc6-4aa3-af27-a4aff50630f5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147337779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.4147337779
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1111846246
Short name T89
Test name
Test status
Simulation time 688603667 ps
CPU time 8.62 seconds
Started Jul 01 10:33:13 AM PDT 24
Finished Jul 01 10:33:24 AM PDT 24
Peak memory 211264 kb
Host smart-15b22a4e-1f19-48d5-bf57-3628f306bb82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111846246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1111846246
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.203790924
Short name T370
Test name
Test status
Simulation time 17142369862 ps
CPU time 33.3 seconds
Started Jul 01 10:33:11 AM PDT 24
Finished Jul 01 10:33:47 AM PDT 24
Peak memory 218400 kb
Host smart-f9aa784f-a9fb-4414-8354-3abe152de712
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203790924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.203790924
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2315317727
Short name T438
Test name
Test status
Simulation time 3199361270 ps
CPU time 159.28 seconds
Started Jul 01 10:33:13 AM PDT 24
Finished Jul 01 10:35:54 AM PDT 24
Peak memory 214320 kb
Host smart-a9f21ca4-fcba-4f40-ba3d-febc1def069f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315317727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2315317727
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1355646327
Short name T448
Test name
Test status
Simulation time 4973630525 ps
CPU time 33.53 seconds
Started Jul 01 10:33:12 AM PDT 24
Finished Jul 01 10:33:48 AM PDT 24
Peak memory 218316 kb
Host smart-afceea6a-c67c-4382-ac30-de79e52d1892
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355646327 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1355646327
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.4249518207
Short name T399
Test name
Test status
Simulation time 1217471522 ps
CPU time 11.95 seconds
Started Jul 01 10:33:17 AM PDT 24
Finished Jul 01 10:33:31 AM PDT 24
Peak memory 210476 kb
Host smart-b3f73d12-8f74-4a7a-8fd1-3eecf00fc70d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249518207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.4249518207
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1412537416
Short name T82
Test name
Test status
Simulation time 4740867556 ps
CPU time 67.3 seconds
Started Jul 01 10:33:09 AM PDT 24
Finished Jul 01 10:34:17 AM PDT 24
Peak memory 214216 kb
Host smart-f6201f53-c6b2-4fa4-aebc-fc1359e9054e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412537416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1412537416
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.790207173
Short name T106
Test name
Test status
Simulation time 1971269307 ps
CPU time 11.75 seconds
Started Jul 01 10:33:10 AM PDT 24
Finished Jul 01 10:33:23 AM PDT 24
Peak memory 211256 kb
Host smart-0e11511e-1aa7-4845-8d1b-fa139343e26d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790207173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.790207173
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1750013933
Short name T447
Test name
Test status
Simulation time 16001910947 ps
CPU time 34.03 seconds
Started Jul 01 10:33:24 AM PDT 24
Finished Jul 01 10:34:00 AM PDT 24
Peak memory 218416 kb
Host smart-40da4596-4913-494c-a687-99cf6a7c1b61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750013933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1750013933
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2268366996
Short name T72
Test name
Test status
Simulation time 484126948 ps
CPU time 79.58 seconds
Started Jul 01 10:33:12 AM PDT 24
Finished Jul 01 10:34:33 AM PDT 24
Peak memory 213320 kb
Host smart-94fb4fa5-d8f5-41b6-a60d-d7128511baa0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268366996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2268366996
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.707063741
Short name T378
Test name
Test status
Simulation time 313817701 ps
CPU time 8.11 seconds
Started Jul 01 10:33:07 AM PDT 24
Finished Jul 01 10:33:16 AM PDT 24
Peak memory 214128 kb
Host smart-afd792dd-a447-4799-bdf2-916c7e181e83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707063741 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.707063741
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1292731542
Short name T377
Test name
Test status
Simulation time 5552699736 ps
CPU time 25.2 seconds
Started Jul 01 10:33:03 AM PDT 24
Finished Jul 01 10:33:28 AM PDT 24
Peak memory 210648 kb
Host smart-ccdf6cf4-79f4-4806-b54d-e9ce6ab5d42e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292731542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1292731542
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.231459111
Short name T97
Test name
Test status
Simulation time 2882856587 ps
CPU time 36.42 seconds
Started Jul 01 10:33:19 AM PDT 24
Finished Jul 01 10:33:57 AM PDT 24
Peak memory 213096 kb
Host smart-b178e7ad-fbfc-473e-a252-b6ed02fb97de
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231459111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.231459111
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1812146025
Short name T105
Test name
Test status
Simulation time 6893138695 ps
CPU time 31.46 seconds
Started Jul 01 10:33:07 AM PDT 24
Finished Jul 01 10:33:40 AM PDT 24
Peak memory 212576 kb
Host smart-8410d9bf-cbe6-4c14-8ddd-6722d33b426f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812146025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1812146025
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.619764021
Short name T380
Test name
Test status
Simulation time 172807491 ps
CPU time 10.95 seconds
Started Jul 01 10:33:14 AM PDT 24
Finished Jul 01 10:33:27 AM PDT 24
Peak memory 217056 kb
Host smart-18744cf9-f9d8-413c-a3e7-445d222bde0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619764021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.619764021
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3870722775
Short name T361
Test name
Test status
Simulation time 6875694357 ps
CPU time 18.08 seconds
Started Jul 01 10:33:20 AM PDT 24
Finished Jul 01 10:33:40 AM PDT 24
Peak memory 217988 kb
Host smart-a66c5566-92be-4628-8020-c4c88828f592
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870722775 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3870722775
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1997709811
Short name T86
Test name
Test status
Simulation time 174442397 ps
CPU time 7.84 seconds
Started Jul 01 10:33:08 AM PDT 24
Finished Jul 01 10:33:17 AM PDT 24
Peak memory 210532 kb
Host smart-f085aa81-a0b6-4719-b7cc-c27269e81027
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997709811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1997709811
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2049541178
Short name T408
Test name
Test status
Simulation time 31337932371 ps
CPU time 144.32 seconds
Started Jul 01 10:33:16 AM PDT 24
Finished Jul 01 10:35:42 AM PDT 24
Peak memory 214748 kb
Host smart-5029b91b-40df-41ff-9dc7-a35d26eb19f5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049541178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2049541178
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.149693355
Short name T420
Test name
Test status
Simulation time 25110412205 ps
CPU time 30.68 seconds
Started Jul 01 10:33:15 AM PDT 24
Finished Jul 01 10:33:49 AM PDT 24
Peak memory 212536 kb
Host smart-6ccf9aec-cac7-46ec-adae-df5da215b4a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149693355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.149693355
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1714449360
Short name T360
Test name
Test status
Simulation time 8719765374 ps
CPU time 35.33 seconds
Started Jul 01 10:33:13 AM PDT 24
Finished Jul 01 10:33:50 AM PDT 24
Peak memory 217208 kb
Host smart-b13f803e-ce7c-41fb-8ac4-d2fe560e6590
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714449360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1714449360
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1984086310
Short name T110
Test name
Test status
Simulation time 7497402548 ps
CPU time 174.8 seconds
Started Jul 01 10:33:09 AM PDT 24
Finished Jul 01 10:36:05 AM PDT 24
Peak memory 214224 kb
Host smart-22798634-7368-4cee-a992-c87a5d150351
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984086310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1984086310
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.710481332
Short name T415
Test name
Test status
Simulation time 5781709283 ps
CPU time 24.77 seconds
Started Jul 01 10:33:36 AM PDT 24
Finished Jul 01 10:34:01 AM PDT 24
Peak memory 217516 kb
Host smart-7e678fb6-9e33-49c9-b4c9-40f39e97159a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710481332 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.710481332
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2925276874
Short name T409
Test name
Test status
Simulation time 1367376802 ps
CPU time 12.72 seconds
Started Jul 01 10:33:12 AM PDT 24
Finished Jul 01 10:33:27 AM PDT 24
Peak memory 211024 kb
Host smart-9bc26d59-7089-4b6d-befd-7487ef584b33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925276874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2925276874
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.838763136
Short name T93
Test name
Test status
Simulation time 30954329805 ps
CPU time 107.28 seconds
Started Jul 01 10:33:12 AM PDT 24
Finished Jul 01 10:35:02 AM PDT 24
Peak memory 214748 kb
Host smart-d3295672-862e-4a0d-b86e-48ac81919593
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838763136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.838763136
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3119553652
Short name T401
Test name
Test status
Simulation time 526285576 ps
CPU time 14.71 seconds
Started Jul 01 10:33:11 AM PDT 24
Finished Jul 01 10:33:28 AM PDT 24
Peak memory 212216 kb
Host smart-fa97be00-7929-4699-ac4b-de75de74296d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119553652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3119553652
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.388943432
Short name T357
Test name
Test status
Simulation time 2297494155 ps
CPU time 15.06 seconds
Started Jul 01 10:33:02 AM PDT 24
Finished Jul 01 10:33:18 AM PDT 24
Peak memory 218872 kb
Host smart-28dc9ac6-4154-466d-8102-baa159e6303e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388943432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.388943432
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3725637303
Short name T376
Test name
Test status
Simulation time 6714179975 ps
CPU time 89.66 seconds
Started Jul 01 10:33:17 AM PDT 24
Finished Jul 01 10:34:48 AM PDT 24
Peak memory 212428 kb
Host smart-270b6ab2-bb80-4025-ab0c-30be81023c97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725637303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3725637303
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.213398134
Short name T449
Test name
Test status
Simulation time 6530061586 ps
CPU time 27.28 seconds
Started Jul 01 10:33:13 AM PDT 24
Finished Jul 01 10:33:42 AM PDT 24
Peak memory 217496 kb
Host smart-2d3f49a4-6ac8-4984-9bec-67a3d957cda8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213398134 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.213398134
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3314864986
Short name T425
Test name
Test status
Simulation time 3081673442 ps
CPU time 16.98 seconds
Started Jul 01 10:33:11 AM PDT 24
Finished Jul 01 10:33:30 AM PDT 24
Peak memory 211960 kb
Host smart-3e68422b-be12-4d83-8d49-f3ae1a43315f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314864986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3314864986
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1960060722
Short name T428
Test name
Test status
Simulation time 16459339305 ps
CPU time 89.59 seconds
Started Jul 01 10:33:09 AM PDT 24
Finished Jul 01 10:34:39 AM PDT 24
Peak memory 214112 kb
Host smart-c17c27aa-8408-4fd4-a56c-b1a2fea354ab
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960060722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1960060722
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.599830147
Short name T433
Test name
Test status
Simulation time 3840092537 ps
CPU time 30.13 seconds
Started Jul 01 10:33:13 AM PDT 24
Finished Jul 01 10:33:44 AM PDT 24
Peak memory 212356 kb
Host smart-45be42e2-dfea-4c3c-8132-430c7fe1a22a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599830147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.599830147
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.422022547
Short name T397
Test name
Test status
Simulation time 4293179145 ps
CPU time 34.88 seconds
Started Jul 01 10:33:14 AM PDT 24
Finished Jul 01 10:33:51 AM PDT 24
Peak memory 218248 kb
Host smart-4ad41e78-5eb0-45b1-8a40-f644714a54fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422022547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.422022547
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1192887182
Short name T116
Test name
Test status
Simulation time 3345677204 ps
CPU time 91.77 seconds
Started Jul 01 10:33:19 AM PDT 24
Finished Jul 01 10:34:53 AM PDT 24
Peak memory 213484 kb
Host smart-33544e53-df89-49b3-95a8-212911b23eaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192887182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1192887182
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4245984675
Short name T414
Test name
Test status
Simulation time 176776650 ps
CPU time 8.62 seconds
Started Jul 01 10:33:03 AM PDT 24
Finished Jul 01 10:33:12 AM PDT 24
Peak memory 214556 kb
Host smart-94e69291-f769-4e4a-b668-9908efb1b2bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245984675 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.4245984675
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3381011909
Short name T85
Test name
Test status
Simulation time 22015728897 ps
CPU time 29.57 seconds
Started Jul 01 10:33:09 AM PDT 24
Finished Jul 01 10:33:40 AM PDT 24
Peak memory 211516 kb
Host smart-bf088f79-9c12-4788-bee3-2cdf5e8d79b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381011909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3381011909
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3134698492
Short name T103
Test name
Test status
Simulation time 39850532425 ps
CPU time 70.8 seconds
Started Jul 01 10:33:18 AM PDT 24
Finished Jul 01 10:34:31 AM PDT 24
Peak memory 213720 kb
Host smart-f1f3eb2a-9c58-4a42-b688-324c61c41077
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134698492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3134698492
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3219270216
Short name T388
Test name
Test status
Simulation time 2632222924 ps
CPU time 24.72 seconds
Started Jul 01 10:33:13 AM PDT 24
Finished Jul 01 10:33:39 AM PDT 24
Peak memory 212180 kb
Host smart-71b1a727-0f68-455f-aaee-6c8b4f130c57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219270216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3219270216
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2938384647
Short name T423
Test name
Test status
Simulation time 5834279695 ps
CPU time 21.63 seconds
Started Jul 01 10:33:10 AM PDT 24
Finished Jul 01 10:33:34 AM PDT 24
Peak memory 218784 kb
Host smart-218474b4-d3e0-4f10-b1a2-eb027caaf4e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938384647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2938384647
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3878021802
Short name T117
Test name
Test status
Simulation time 6386798328 ps
CPU time 158.59 seconds
Started Jul 01 10:33:23 AM PDT 24
Finished Jul 01 10:36:02 AM PDT 24
Peak memory 214216 kb
Host smart-98ec42e3-fffe-44eb-ad55-7f89f2ee6a27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878021802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3878021802
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.916494962
Short name T398
Test name
Test status
Simulation time 737003572 ps
CPU time 9.32 seconds
Started Jul 01 10:33:19 AM PDT 24
Finished Jul 01 10:33:30 AM PDT 24
Peak memory 216804 kb
Host smart-3dcf239c-8c63-4659-811a-90c4d015f464
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916494962 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.916494962
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2457962395
Short name T416
Test name
Test status
Simulation time 1907314590 ps
CPU time 18.95 seconds
Started Jul 01 10:33:10 AM PDT 24
Finished Jul 01 10:33:30 AM PDT 24
Peak memory 210616 kb
Host smart-e2b45436-96b1-4356-8993-3fa41a553758
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457962395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2457962395
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2936432181
Short name T84
Test name
Test status
Simulation time 191694472350 ps
CPU time 110.66 seconds
Started Jul 01 10:33:03 AM PDT 24
Finished Jul 01 10:34:55 AM PDT 24
Peak memory 213736 kb
Host smart-b68e8799-6932-4d08-8ef3-11f40ad37150
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936432181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2936432181
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1005967574
Short name T374
Test name
Test status
Simulation time 176337669 ps
CPU time 8.23 seconds
Started Jul 01 10:33:11 AM PDT 24
Finished Jul 01 10:33:21 AM PDT 24
Peak memory 210676 kb
Host smart-52ab8ef7-cfa6-4c6c-b1e4-1e45b516a625
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005967574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1005967574
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.160110919
Short name T384
Test name
Test status
Simulation time 4223768331 ps
CPU time 36.51 seconds
Started Jul 01 10:33:20 AM PDT 24
Finished Jul 01 10:33:59 AM PDT 24
Peak memory 218556 kb
Host smart-c53a4c90-9eba-4861-8b07-97d1e01652ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160110919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.160110919
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3987955414
Short name T427
Test name
Test status
Simulation time 365324834 ps
CPU time 8.82 seconds
Started Jul 01 10:33:16 AM PDT 24
Finished Jul 01 10:33:26 AM PDT 24
Peak memory 216220 kb
Host smart-b40d8d3d-c6d5-41b3-85f1-eec3f8fcd29b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987955414 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3987955414
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.33572713
Short name T100
Test name
Test status
Simulation time 12265418060 ps
CPU time 25.46 seconds
Started Jul 01 10:33:14 AM PDT 24
Finished Jul 01 10:33:41 AM PDT 24
Peak memory 211860 kb
Host smart-a810c8a8-b232-4465-b4d0-cba809c8a857
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33572713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.33572713
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2970459306
Short name T439
Test name
Test status
Simulation time 37059856569 ps
CPU time 112.35 seconds
Started Jul 01 10:33:18 AM PDT 24
Finished Jul 01 10:35:12 AM PDT 24
Peak memory 214976 kb
Host smart-fb83f1c6-3a4b-4910-80e3-00786dd2f187
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970459306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2970459306
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.610568655
Short name T429
Test name
Test status
Simulation time 2510432627 ps
CPU time 13.63 seconds
Started Jul 01 10:33:12 AM PDT 24
Finished Jul 01 10:33:28 AM PDT 24
Peak memory 212272 kb
Host smart-043e7842-0936-4f47-973d-c26e09fe1cdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610568655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.610568655
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.36929214
Short name T359
Test name
Test status
Simulation time 1549967001 ps
CPU time 19.51 seconds
Started Jul 01 10:33:14 AM PDT 24
Finished Jul 01 10:33:35 AM PDT 24
Peak memory 217016 kb
Host smart-d7ec0aef-eed1-4609-a519-089b15ca40c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36929214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.36929214
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4199669306
Short name T112
Test name
Test status
Simulation time 351251659 ps
CPU time 81.47 seconds
Started Jul 01 10:33:07 AM PDT 24
Finished Jul 01 10:34:30 AM PDT 24
Peak memory 214648 kb
Host smart-4ee9c4ce-f1a0-415e-8bac-30e0f6fef110
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199669306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.4199669306
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2761946394
Short name T405
Test name
Test status
Simulation time 3957408737 ps
CPU time 30.27 seconds
Started Jul 01 10:32:54 AM PDT 24
Finished Jul 01 10:33:25 AM PDT 24
Peak memory 210964 kb
Host smart-fb993ac9-0cbd-4219-ae8b-a451c8edbd02
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761946394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2761946394
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.42911012
Short name T456
Test name
Test status
Simulation time 7012957628 ps
CPU time 11.85 seconds
Started Jul 01 10:32:53 AM PDT 24
Finished Jul 01 10:33:06 AM PDT 24
Peak memory 210964 kb
Host smart-9c0becbe-2fa5-40b8-b242-ed61b67ba67c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42911012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_ba
sh.42911012
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3633787682
Short name T99
Test name
Test status
Simulation time 3718187955 ps
CPU time 36.38 seconds
Started Jul 01 10:32:56 AM PDT 24
Finished Jul 01 10:33:33 AM PDT 24
Peak memory 211592 kb
Host smart-072ee64d-8014-452c-925f-af3ceb7986b8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633787682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3633787682
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1563069845
Short name T451
Test name
Test status
Simulation time 1467896520 ps
CPU time 17.71 seconds
Started Jul 01 10:33:07 AM PDT 24
Finished Jul 01 10:33:26 AM PDT 24
Peak memory 216768 kb
Host smart-970baffb-65c1-4b9a-a5da-1cccb42f7a47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563069845 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1563069845
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2018927982
Short name T426
Test name
Test status
Simulation time 1647515373 ps
CPU time 7.92 seconds
Started Jul 01 10:32:52 AM PDT 24
Finished Jul 01 10:33:01 AM PDT 24
Peak memory 210460 kb
Host smart-0745dea6-16e7-489d-93a6-736c447eb8b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018927982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2018927982
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.398365075
Short name T373
Test name
Test status
Simulation time 6618408104 ps
CPU time 21.15 seconds
Started Jul 01 10:33:08 AM PDT 24
Finished Jul 01 10:33:30 AM PDT 24
Peak memory 210728 kb
Host smart-4765adca-667e-4a8d-b93a-724223dc4bb8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398365075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.398365075
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3089134152
Short name T442
Test name
Test status
Simulation time 21696167662 ps
CPU time 29.33 seconds
Started Jul 01 10:32:49 AM PDT 24
Finished Jul 01 10:33:19 AM PDT 24
Peak memory 210680 kb
Host smart-a379e7cc-df74-43f3-bcc3-23c796d948b1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089134152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3089134152
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1425277046
Short name T419
Test name
Test status
Simulation time 250599159 ps
CPU time 9.98 seconds
Started Jul 01 10:32:54 AM PDT 24
Finished Jul 01 10:33:05 AM PDT 24
Peak memory 211412 kb
Host smart-1e93e24a-86cc-40e1-9ebf-069e147a05f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425277046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1425277046
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2295508770
Short name T379
Test name
Test status
Simulation time 14248905437 ps
CPU time 32.11 seconds
Started Jul 01 10:33:07 AM PDT 24
Finished Jul 01 10:33:40 AM PDT 24
Peak memory 218100 kb
Host smart-ee243bdb-a432-4545-a4da-61587f9ef1fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295508770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2295508770
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2885411526
Short name T120
Test name
Test status
Simulation time 1150764635 ps
CPU time 150.77 seconds
Started Jul 01 10:32:54 AM PDT 24
Finished Jul 01 10:35:25 AM PDT 24
Peak memory 212764 kb
Host smart-0c46d232-279e-4b40-91d4-ef9d0982df98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885411526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2885411526
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.760750813
Short name T435
Test name
Test status
Simulation time 2265474422 ps
CPU time 20.64 seconds
Started Jul 01 10:33:11 AM PDT 24
Finished Jul 01 10:33:34 AM PDT 24
Peak memory 211240 kb
Host smart-66d4547b-3d8f-4a38-818c-f13ad62dcd24
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760750813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.760750813
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2842869316
Short name T452
Test name
Test status
Simulation time 1199542613 ps
CPU time 12.44 seconds
Started Jul 01 10:32:56 AM PDT 24
Finished Jul 01 10:33:09 AM PDT 24
Peak memory 210584 kb
Host smart-d7f6d56d-3019-4028-9ca3-31f03a5342b2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842869316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2842869316
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.870832243
Short name T400
Test name
Test status
Simulation time 5689648787 ps
CPU time 26.98 seconds
Started Jul 01 10:33:07 AM PDT 24
Finished Jul 01 10:33:35 AM PDT 24
Peak memory 211420 kb
Host smart-ee6a6a63-3918-41d7-b5ab-c4e7ceb88f86
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870832243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.870832243
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1168884782
Short name T390
Test name
Test status
Simulation time 186333952 ps
CPU time 8.92 seconds
Started Jul 01 10:33:07 AM PDT 24
Finished Jul 01 10:33:17 AM PDT 24
Peak memory 216808 kb
Host smart-67f8ca18-d690-4fa1-8162-ef20a2b27643
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168884782 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1168884782
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2909014564
Short name T381
Test name
Test status
Simulation time 332094476 ps
CPU time 8.38 seconds
Started Jul 01 10:33:07 AM PDT 24
Finished Jul 01 10:33:16 AM PDT 24
Peak memory 210584 kb
Host smart-70833e66-2ca4-487f-b3a7-f66600dd0a27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909014564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2909014564
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.484174524
Short name T385
Test name
Test status
Simulation time 1376309880 ps
CPU time 7.76 seconds
Started Jul 01 10:32:52 AM PDT 24
Finished Jul 01 10:33:00 AM PDT 24
Peak memory 210412 kb
Host smart-4195be52-1745-47a8-b538-facfca6f6d2d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484174524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.484174524
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.29454081
Short name T421
Test name
Test status
Simulation time 8184171247 ps
CPU time 17.2 seconds
Started Jul 01 10:33:04 AM PDT 24
Finished Jul 01 10:33:22 AM PDT 24
Peak memory 210428 kb
Host smart-3a8f8ad9-21fa-421d-a958-ca2ee2e82d3d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29454081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.29454081
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.382537099
Short name T102
Test name
Test status
Simulation time 52975493740 ps
CPU time 107.71 seconds
Started Jul 01 10:33:01 AM PDT 24
Finished Jul 01 10:34:49 AM PDT 24
Peak memory 213860 kb
Host smart-da841026-c002-4148-84cd-f2f1fcf11d33
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382537099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.382537099
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2893035461
Short name T83
Test name
Test status
Simulation time 2997749133 ps
CPU time 24.67 seconds
Started Jul 01 10:32:54 AM PDT 24
Finished Jul 01 10:33:19 AM PDT 24
Peak memory 212128 kb
Host smart-c58ecf7c-4489-4309-99bd-32bee9118ef0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893035461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2893035461
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4051977560
Short name T431
Test name
Test status
Simulation time 3438661990 ps
CPU time 20.17 seconds
Started Jul 01 10:33:05 AM PDT 24
Finished Jul 01 10:33:26 AM PDT 24
Peak memory 218068 kb
Host smart-19ab18e3-e391-489c-9ed8-17f2e8f254c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051977560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.4051977560
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1637710652
Short name T111
Test name
Test status
Simulation time 5244525264 ps
CPU time 157.84 seconds
Started Jul 01 10:32:54 AM PDT 24
Finished Jul 01 10:35:32 AM PDT 24
Peak memory 214116 kb
Host smart-67eead7d-4d29-4795-bfb1-391ad79d2222
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637710652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1637710652
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.4138615912
Short name T375
Test name
Test status
Simulation time 1476628881 ps
CPU time 16.99 seconds
Started Jul 01 10:32:53 AM PDT 24
Finished Jul 01 10:33:10 AM PDT 24
Peak memory 211272 kb
Host smart-fa467b78-57da-49a1-a0ba-b95d9e59ab58
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138615912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.4138615912
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1079577933
Short name T430
Test name
Test status
Simulation time 172505992 ps
CPU time 8.22 seconds
Started Jul 01 10:33:11 AM PDT 24
Finished Jul 01 10:33:22 AM PDT 24
Peak memory 210584 kb
Host smart-49a23988-b0d9-4d72-a2db-93b7c65c4804
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079577933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1079577933
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1010021189
Short name T364
Test name
Test status
Simulation time 3894951742 ps
CPU time 32.33 seconds
Started Jul 01 10:33:10 AM PDT 24
Finished Jul 01 10:33:44 AM PDT 24
Peak memory 211204 kb
Host smart-a6aaa070-951c-4fa9-b37b-4a6837ce104f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010021189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1010021189
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3977466459
Short name T424
Test name
Test status
Simulation time 6553262523 ps
CPU time 18.86 seconds
Started Jul 01 10:33:06 AM PDT 24
Finished Jul 01 10:33:25 AM PDT 24
Peak memory 218852 kb
Host smart-6e49be00-5ae8-4fd3-a55b-336b85172737
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977466459 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3977466459
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3239539050
Short name T369
Test name
Test status
Simulation time 7649479296 ps
CPU time 16.31 seconds
Started Jul 01 10:33:11 AM PDT 24
Finished Jul 01 10:33:30 AM PDT 24
Peak memory 212256 kb
Host smart-cb3b1a51-6e9b-4d7c-a533-04b3b78fe3a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239539050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3239539050
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.204018790
Short name T363
Test name
Test status
Simulation time 688422850 ps
CPU time 8.27 seconds
Started Jul 01 10:33:06 AM PDT 24
Finished Jul 01 10:33:16 AM PDT 24
Peak memory 210456 kb
Host smart-a1938a73-4774-416f-903c-7c7ac7638bd4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204018790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.204018790
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3541465269
Short name T362
Test name
Test status
Simulation time 3344610397 ps
CPU time 17.95 seconds
Started Jul 01 10:33:14 AM PDT 24
Finished Jul 01 10:33:34 AM PDT 24
Peak memory 210508 kb
Host smart-73e3854e-5384-44b9-a17c-3fffc70e85d6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541465269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3541465269
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3628690232
Short name T81
Test name
Test status
Simulation time 1081153255 ps
CPU time 55.87 seconds
Started Jul 01 10:33:10 AM PDT 24
Finished Jul 01 10:34:08 AM PDT 24
Peak memory 214808 kb
Host smart-d1c989b7-57b1-4820-a3d6-9cbdb08cfea6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628690232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3628690232
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2825693043
Short name T396
Test name
Test status
Simulation time 980897110 ps
CPU time 11.54 seconds
Started Jul 01 10:33:00 AM PDT 24
Finished Jul 01 10:33:12 AM PDT 24
Peak memory 211156 kb
Host smart-384ba776-59d1-42dd-a59d-52aa9c2defbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825693043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2825693043
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2044555443
Short name T387
Test name
Test status
Simulation time 18490075136 ps
CPU time 32.77 seconds
Started Jul 01 10:32:52 AM PDT 24
Finished Jul 01 10:33:26 AM PDT 24
Peak memory 217364 kb
Host smart-453f3dae-babc-4ec1-b6bb-f85be7841823
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044555443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2044555443
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3349869766
Short name T119
Test name
Test status
Simulation time 3291836020 ps
CPU time 157.82 seconds
Started Jul 01 10:33:00 AM PDT 24
Finished Jul 01 10:35:38 AM PDT 24
Peak memory 213908 kb
Host smart-0d13e4ad-4917-405a-99bc-9e6c4ad0ba50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349869766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3349869766
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2625383086
Short name T437
Test name
Test status
Simulation time 3323154476 ps
CPU time 18.43 seconds
Started Jul 01 10:33:14 AM PDT 24
Finished Jul 01 10:33:39 AM PDT 24
Peak memory 216972 kb
Host smart-d50e27f1-9774-467f-b95c-a8cc33657d1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625383086 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2625383086
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1851464727
Short name T101
Test name
Test status
Simulation time 176024582 ps
CPU time 7.83 seconds
Started Jul 01 10:33:15 AM PDT 24
Finished Jul 01 10:33:25 AM PDT 24
Peak memory 210592 kb
Host smart-39a159dc-50ea-48c8-a6a5-9b60110b670b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851464727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1851464727
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.23561043
Short name T96
Test name
Test status
Simulation time 690997350 ps
CPU time 37.75 seconds
Started Jul 01 10:33:15 AM PDT 24
Finished Jul 01 10:33:54 AM PDT 24
Peak memory 213600 kb
Host smart-2eddca6e-4e08-4b4b-b964-07830b371e45
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23561043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pass
thru_mem_tl_intg_err.23561043
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2353457057
Short name T395
Test name
Test status
Simulation time 6838853282 ps
CPU time 31.21 seconds
Started Jul 01 10:33:07 AM PDT 24
Finished Jul 01 10:33:39 AM PDT 24
Peak memory 212696 kb
Host smart-452e3d96-5d27-4478-a95b-406d2c6ca955
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353457057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2353457057
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.744074941
Short name T391
Test name
Test status
Simulation time 1457709293 ps
CPU time 19.47 seconds
Started Jul 01 10:33:09 AM PDT 24
Finished Jul 01 10:33:30 AM PDT 24
Peak memory 218804 kb
Host smart-d163a23a-3baf-4c4f-877d-ed5302bf3d0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744074941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.744074941
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4272099640
Short name T121
Test name
Test status
Simulation time 11030618079 ps
CPU time 167.59 seconds
Started Jul 01 10:33:11 AM PDT 24
Finished Jul 01 10:36:00 AM PDT 24
Peak memory 213008 kb
Host smart-0499f151-3349-455b-8516-2fdf6d39ed66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272099640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.4272099640
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2978077747
Short name T394
Test name
Test status
Simulation time 26926166618 ps
CPU time 25.44 seconds
Started Jul 01 10:33:00 AM PDT 24
Finished Jul 01 10:33:25 AM PDT 24
Peak memory 214376 kb
Host smart-b456b9b0-4046-4f43-ace7-26bbd3f9618c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978077747 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2978077747
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1026608137
Short name T392
Test name
Test status
Simulation time 1275572564 ps
CPU time 15.65 seconds
Started Jul 01 10:33:09 AM PDT 24
Finished Jul 01 10:33:26 AM PDT 24
Peak memory 210492 kb
Host smart-e5d0177d-9d94-43cb-afbb-c1c53315f13a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026608137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1026608137
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3776989192
Short name T389
Test name
Test status
Simulation time 26339893120 ps
CPU time 78.85 seconds
Started Jul 01 10:33:01 AM PDT 24
Finished Jul 01 10:34:21 AM PDT 24
Peak memory 213652 kb
Host smart-b22239d9-89c3-48b7-b692-af94fc25ceeb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776989192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3776989192
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3274717451
Short name T446
Test name
Test status
Simulation time 1132220742 ps
CPU time 14.39 seconds
Started Jul 01 10:33:09 AM PDT 24
Finished Jul 01 10:33:25 AM PDT 24
Peak memory 211044 kb
Host smart-7de07300-ad78-4108-af36-7763f0a141f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274717451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3274717451
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.4015278517
Short name T65
Test name
Test status
Simulation time 1334187058 ps
CPU time 20.34 seconds
Started Jul 01 10:33:15 AM PDT 24
Finished Jul 01 10:33:37 AM PDT 24
Peak memory 217276 kb
Host smart-0724d05f-bc58-4d8d-a230-149359022ec5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015278517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.4015278517
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.4022422798
Short name T108
Test name
Test status
Simulation time 1193762021 ps
CPU time 155.56 seconds
Started Jul 01 10:33:11 AM PDT 24
Finished Jul 01 10:35:49 AM PDT 24
Peak memory 213948 kb
Host smart-cc88a039-cb64-4969-83b3-3a9910b41809
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022422798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.4022422798
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3471169647
Short name T450
Test name
Test status
Simulation time 2966646008 ps
CPU time 26.05 seconds
Started Jul 01 10:33:14 AM PDT 24
Finished Jul 01 10:33:42 AM PDT 24
Peak memory 217804 kb
Host smart-199e79e3-15e3-464f-9680-17369ef8b38b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471169647 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3471169647
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2277243851
Short name T410
Test name
Test status
Simulation time 2318154508 ps
CPU time 21.27 seconds
Started Jul 01 10:33:14 AM PDT 24
Finished Jul 01 10:33:37 AM PDT 24
Peak memory 211304 kb
Host smart-430a9c4d-681f-48a0-84b0-b621935d26f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277243851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2277243851
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3635639432
Short name T95
Test name
Test status
Simulation time 35445048405 ps
CPU time 165.36 seconds
Started Jul 01 10:33:12 AM PDT 24
Finished Jul 01 10:35:59 AM PDT 24
Peak memory 215288 kb
Host smart-b4ad80b0-c883-48c4-aa0c-626de0e39021
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635639432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3635639432
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3211082788
Short name T104
Test name
Test status
Simulation time 8458083096 ps
CPU time 22.55 seconds
Started Jul 01 10:33:11 AM PDT 24
Finished Jul 01 10:33:36 AM PDT 24
Peak memory 212300 kb
Host smart-766bebfc-de88-49f0-9fff-d2d0bdae8204
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211082788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3211082788
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.4294759977
Short name T382
Test name
Test status
Simulation time 167651541 ps
CPU time 11.48 seconds
Started Jul 01 10:33:06 AM PDT 24
Finished Jul 01 10:33:18 AM PDT 24
Peak memory 217000 kb
Host smart-99b64566-e068-4d84-a2ae-cb68e47684ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294759977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.4294759977
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2658698687
Short name T109
Test name
Test status
Simulation time 15958543428 ps
CPU time 103.55 seconds
Started Jul 01 10:33:08 AM PDT 24
Finished Jul 01 10:34:52 AM PDT 24
Peak memory 214904 kb
Host smart-be645303-3c99-4cc9-9bc3-90b2a8ecad73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658698687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2658698687
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.815855125
Short name T444
Test name
Test status
Simulation time 998586884 ps
CPU time 9.7 seconds
Started Jul 01 10:33:15 AM PDT 24
Finished Jul 01 10:33:26 AM PDT 24
Peak memory 217532 kb
Host smart-c6043f8a-c468-43cb-b24e-727e44c0f37b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815855125 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.815855125
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3626374239
Short name T366
Test name
Test status
Simulation time 19821250197 ps
CPU time 28.52 seconds
Started Jul 01 10:32:58 AM PDT 24
Finished Jul 01 10:33:27 AM PDT 24
Peak memory 211684 kb
Host smart-3e88e5aa-c8fd-4e12-bc81-5203091b71db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626374239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3626374239
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.194747557
Short name T368
Test name
Test status
Simulation time 34815410382 ps
CPU time 77.9 seconds
Started Jul 01 10:32:54 AM PDT 24
Finished Jul 01 10:34:13 AM PDT 24
Peak memory 213796 kb
Host smart-1ff888c4-be71-40ea-b351-f814c0656fc7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194747557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.194747557
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3080193301
Short name T403
Test name
Test status
Simulation time 14298689893 ps
CPU time 28.52 seconds
Started Jul 01 10:33:11 AM PDT 24
Finished Jul 01 10:33:42 AM PDT 24
Peak memory 212344 kb
Host smart-19c52555-3e74-4507-a711-712c16bc1721
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080193301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3080193301
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1181199704
Short name T453
Test name
Test status
Simulation time 12121685410 ps
CPU time 28.22 seconds
Started Jul 01 10:33:05 AM PDT 24
Finished Jul 01 10:33:33 AM PDT 24
Peak memory 217700 kb
Host smart-ac885c75-dc66-40c7-8e37-94e8761292d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181199704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1181199704
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.500895820
Short name T115
Test name
Test status
Simulation time 32065041273 ps
CPU time 162.07 seconds
Started Jul 01 10:33:03 AM PDT 24
Finished Jul 01 10:35:46 AM PDT 24
Peak memory 214224 kb
Host smart-ea2c8e9c-96e1-47d0-9de7-89203eb93811
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500895820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.500895820
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.97401729
Short name T358
Test name
Test status
Simulation time 1409341703 ps
CPU time 10.67 seconds
Started Jul 01 10:33:20 AM PDT 24
Finished Jul 01 10:33:32 AM PDT 24
Peak memory 216156 kb
Host smart-32758b55-797a-4113-a19f-5f7d390e7e3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97401729 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.97401729
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3771695558
Short name T432
Test name
Test status
Simulation time 4298207913 ps
CPU time 32.38 seconds
Started Jul 01 10:33:07 AM PDT 24
Finished Jul 01 10:33:41 AM PDT 24
Peak memory 211880 kb
Host smart-133a6888-24b7-4a8c-b207-a33357b6d76c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771695558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3771695558
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3895282226
Short name T417
Test name
Test status
Simulation time 62944045056 ps
CPU time 120.01 seconds
Started Jul 01 10:33:07 AM PDT 24
Finished Jul 01 10:35:08 AM PDT 24
Peak memory 213948 kb
Host smart-9cd81154-b655-4120-9c49-e7e964434393
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895282226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3895282226
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1534869842
Short name T455
Test name
Test status
Simulation time 12071948012 ps
CPU time 31.82 seconds
Started Jul 01 10:33:10 AM PDT 24
Finished Jul 01 10:33:43 AM PDT 24
Peak memory 212384 kb
Host smart-09c4f3d1-007d-454c-bfc6-bb2ecb9f13c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534869842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1534869842
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2398346666
Short name T372
Test name
Test status
Simulation time 18862470790 ps
CPU time 35.67 seconds
Started Jul 01 10:33:11 AM PDT 24
Finished Jul 01 10:33:49 AM PDT 24
Peak memory 218548 kb
Host smart-114f1db5-c98a-495f-8750-c870dbbd437b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398346666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2398346666
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3284534997
Short name T445
Test name
Test status
Simulation time 4984356376 ps
CPU time 156.38 seconds
Started Jul 01 10:33:12 AM PDT 24
Finished Jul 01 10:35:50 AM PDT 24
Peak memory 214048 kb
Host smart-6f9b5d12-29c5-4ccf-922b-4d158ebdd970
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284534997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3284534997
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.4285350893
Short name T246
Test name
Test status
Simulation time 835350262 ps
CPU time 13.76 seconds
Started Jul 01 10:50:10 AM PDT 24
Finished Jul 01 10:50:28 AM PDT 24
Peak memory 217096 kb
Host smart-3ed3ef9e-7a8d-4916-a7a3-bea2b1183ae7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285350893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.4285350893
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.914043406
Short name T39
Test name
Test status
Simulation time 54357333698 ps
CPU time 597.94 seconds
Started Jul 01 10:50:03 AM PDT 24
Finished Jul 01 11:00:01 AM PDT 24
Peak memory 226388 kb
Host smart-b9456e07-ba49-48ab-b7e8-9fdc678d8e5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914043406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.914043406
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3031117488
Short name T295
Test name
Test status
Simulation time 4545610060 ps
CPU time 28.65 seconds
Started Jul 01 10:50:09 AM PDT 24
Finished Jul 01 10:50:41 AM PDT 24
Peak memory 218608 kb
Host smart-f765457b-aa0c-4480-8e3b-03c98f4c0973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031117488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3031117488
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1913528944
Short name T235
Test name
Test status
Simulation time 738671515 ps
CPU time 10.65 seconds
Started Jul 01 10:50:12 AM PDT 24
Finished Jul 01 10:50:26 AM PDT 24
Peak memory 219036 kb
Host smart-e4160fb0-15a2-4ecc-8b63-f3cd0614e85c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1913528944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1913528944
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2100803438
Short name T20
Test name
Test status
Simulation time 2588172921 ps
CPU time 131.77 seconds
Started Jul 01 10:50:01 AM PDT 24
Finished Jul 01 10:52:14 AM PDT 24
Peak memory 239080 kb
Host smart-bc0ee1a2-2305-4eee-abdc-43f5d4ef096e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100803438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2100803438
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1219555263
Short name T226
Test name
Test status
Simulation time 1373264291 ps
CPU time 19.8 seconds
Started Jul 01 10:50:16 AM PDT 24
Finished Jul 01 10:50:38 AM PDT 24
Peak memory 216752 kb
Host smart-4bdd0f59-dbee-47f3-8cf9-1c8ff0792680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219555263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1219555263
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1959261211
Short name T329
Test name
Test status
Simulation time 3427781638 ps
CPU time 31.56 seconds
Started Jul 01 10:49:59 AM PDT 24
Finished Jul 01 10:50:31 AM PDT 24
Peak memory 219244 kb
Host smart-393688ad-91a7-4757-88eb-93d89c29e1d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959261211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1959261211
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1542905185
Short name T174
Test name
Test status
Simulation time 3251678047 ps
CPU time 27.74 seconds
Started Jul 01 10:50:11 AM PDT 24
Finished Jul 01 10:50:42 AM PDT 24
Peak memory 217156 kb
Host smart-5da8205e-8a5a-4b07-8201-44e84660fd45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542905185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1542905185
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1064570442
Short name T256
Test name
Test status
Simulation time 116429125377 ps
CPU time 399.14 seconds
Started Jul 01 10:50:09 AM PDT 24
Finished Jul 01 10:56:51 AM PDT 24
Peak memory 234196 kb
Host smart-3bfb892c-117c-4cb3-9222-bdf00f26cd6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064570442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1064570442
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3944516261
Short name T160
Test name
Test status
Simulation time 2654139442 ps
CPU time 24.77 seconds
Started Jul 01 10:50:11 AM PDT 24
Finished Jul 01 10:50:40 AM PDT 24
Peak memory 218984 kb
Host smart-583cab6d-600b-4916-9ad5-008d4d70be2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944516261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3944516261
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2895183372
Short name T142
Test name
Test status
Simulation time 3368016131 ps
CPU time 26.08 seconds
Started Jul 01 10:50:04 AM PDT 24
Finished Jul 01 10:50:31 AM PDT 24
Peak memory 211368 kb
Host smart-969a733b-43a2-4d3c-9b01-4d60b7e7abef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2895183372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2895183372
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.908739125
Short name T22
Test name
Test status
Simulation time 907740817 ps
CPU time 115.8 seconds
Started Jul 01 10:50:13 AM PDT 24
Finished Jul 01 10:52:12 AM PDT 24
Peak memory 237296 kb
Host smart-f5348cc9-8df5-4ff7-8cc3-d23722c6def7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908739125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.908739125
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.669140209
Short name T179
Test name
Test status
Simulation time 14156638105 ps
CPU time 37.68 seconds
Started Jul 01 10:50:09 AM PDT 24
Finished Jul 01 10:50:50 AM PDT 24
Peak memory 214748 kb
Host smart-917416b4-3d9d-45dc-95be-35bf51f21ae2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669140209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.669140209
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1331817193
Short name T46
Test name
Test status
Simulation time 9067801155 ps
CPU time 24.56 seconds
Started Jul 01 10:50:08 AM PDT 24
Finished Jul 01 10:50:35 AM PDT 24
Peak memory 217548 kb
Host smart-4420fa38-53c6-4dc1-ac2e-c878203059b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331817193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1331817193
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.737373815
Short name T237
Test name
Test status
Simulation time 18997552259 ps
CPU time 47.57 seconds
Started Jul 01 10:50:31 AM PDT 24
Finished Jul 01 10:51:19 AM PDT 24
Peak memory 219384 kb
Host smart-f2a8b224-c1db-4643-947f-8b6646c4ed6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737373815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.737373815
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2573081194
Short name T107
Test name
Test status
Simulation time 8284974408 ps
CPU time 32.32 seconds
Started Jul 01 10:50:09 AM PDT 24
Finished Jul 01 10:50:45 AM PDT 24
Peak memory 219400 kb
Host smart-3a919654-5134-4f76-beb6-b5d2379b650c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2573081194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2573081194
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1171047780
Short name T266
Test name
Test status
Simulation time 349559273 ps
CPU time 20.3 seconds
Started Jul 01 10:50:22 AM PDT 24
Finished Jul 01 10:50:43 AM PDT 24
Peak memory 217604 kb
Host smart-c90c4631-5796-473d-85bf-a06c4c01e0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171047780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1171047780
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3783340608
Short name T303
Test name
Test status
Simulation time 17799005720 ps
CPU time 70.91 seconds
Started Jul 01 10:50:45 AM PDT 24
Finished Jul 01 10:51:56 AM PDT 24
Peak memory 219488 kb
Host smart-033b57dd-3579-4d39-887c-4c555759c7c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783340608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3783340608
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2283554639
Short name T7
Test name
Test status
Simulation time 46225797088 ps
CPU time 25.81 seconds
Started Jul 01 10:50:31 AM PDT 24
Finished Jul 01 10:50:57 AM PDT 24
Peak memory 217456 kb
Host smart-a8f6c847-a83f-4dab-98f3-43eb7d374a11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283554639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2283554639
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.4158514430
Short name T254
Test name
Test status
Simulation time 280129712652 ps
CPU time 460.78 seconds
Started Jul 01 10:50:39 AM PDT 24
Finished Jul 01 10:58:21 AM PDT 24
Peak memory 233816 kb
Host smart-f744e119-618d-4d0b-b8d5-f2f699d41830
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158514430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.4158514430
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.541543426
Short name T1
Test name
Test status
Simulation time 7613411609 ps
CPU time 23.08 seconds
Started Jul 01 10:50:12 AM PDT 24
Finished Jul 01 10:50:38 AM PDT 24
Peak memory 217944 kb
Host smart-f6747a9b-8764-4bd2-8c1a-5cab438201b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=541543426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.541543426
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3120440282
Short name T141
Test name
Test status
Simulation time 15740940422 ps
CPU time 64.1 seconds
Started Jul 01 10:50:09 AM PDT 24
Finished Jul 01 10:51:16 AM PDT 24
Peak memory 216044 kb
Host smart-c9264487-fb56-45c3-9af6-b91e14d81102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120440282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3120440282
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2253840363
Short name T204
Test name
Test status
Simulation time 373951317 ps
CPU time 17.98 seconds
Started Jul 01 10:50:42 AM PDT 24
Finished Jul 01 10:51:01 AM PDT 24
Peak memory 218868 kb
Host smart-0aa807f0-050c-44f9-8592-9947874381f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253840363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2253840363
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3485543413
Short name T173
Test name
Test status
Simulation time 5539848079 ps
CPU time 29.76 seconds
Started Jul 01 10:50:14 AM PDT 24
Finished Jul 01 10:50:47 AM PDT 24
Peak memory 217580 kb
Host smart-08c94de5-6d52-475d-9924-1a3c13e3f5a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485543413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3485543413
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1091571759
Short name T252
Test name
Test status
Simulation time 125754681469 ps
CPU time 590.26 seconds
Started Jul 01 10:50:28 AM PDT 24
Finished Jul 01 11:00:19 AM PDT 24
Peak memory 227252 kb
Host smart-a61d5b7b-7809-4fe5-8421-9692f31cca7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091571759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1091571759
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3392949008
Short name T236
Test name
Test status
Simulation time 2385639441 ps
CPU time 28.2 seconds
Started Jul 01 10:50:24 AM PDT 24
Finished Jul 01 10:50:53 AM PDT 24
Peak memory 218768 kb
Host smart-e72b0094-4169-443d-9176-6f0820502cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392949008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3392949008
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.4270131709
Short name T156
Test name
Test status
Simulation time 460511046 ps
CPU time 12.91 seconds
Started Jul 01 10:50:31 AM PDT 24
Finished Jul 01 10:50:44 AM PDT 24
Peak memory 218472 kb
Host smart-6ac28cb7-2289-426f-b7e7-24107d20c4f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4270131709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.4270131709
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1200486564
Short name T240
Test name
Test status
Simulation time 2051488379 ps
CPU time 28.11 seconds
Started Jul 01 10:50:14 AM PDT 24
Finished Jul 01 10:50:45 AM PDT 24
Peak memory 216260 kb
Host smart-936c37a9-19df-4c7c-88bb-05384f4b2932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200486564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1200486564
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1577472581
Short name T342
Test name
Test status
Simulation time 8531436895 ps
CPU time 30.62 seconds
Started Jul 01 10:50:21 AM PDT 24
Finished Jul 01 10:50:53 AM PDT 24
Peak memory 217604 kb
Host smart-c170e031-2283-4492-a216-ff2659d5df4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577472581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1577472581
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2424586066
Short name T42
Test name
Test status
Simulation time 4300538102 ps
CPU time 284.38 seconds
Started Jul 01 10:50:13 AM PDT 24
Finished Jul 01 10:55:01 AM PDT 24
Peak memory 238780 kb
Host smart-93b9c957-e6ef-45d0-9aec-bf6bceb5ba90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424586066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2424586066
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2854358997
Short name T215
Test name
Test status
Simulation time 14153683218 ps
CPU time 38.63 seconds
Started Jul 01 10:50:19 AM PDT 24
Finished Jul 01 10:50:58 AM PDT 24
Peak memory 219396 kb
Host smart-28357ab2-fa97-426e-ae68-7c17d8abe913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854358997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2854358997
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.221196896
Short name T127
Test name
Test status
Simulation time 187127543 ps
CPU time 10.29 seconds
Started Jul 01 10:50:44 AM PDT 24
Finished Jul 01 10:50:55 AM PDT 24
Peak memory 219312 kb
Host smart-90fdb0a0-cc1b-4ea8-824c-3332c41e1728
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=221196896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.221196896
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3107730087
Short name T216
Test name
Test status
Simulation time 4539485561 ps
CPU time 56.95 seconds
Started Jul 01 10:50:28 AM PDT 24
Finished Jul 01 10:51:26 AM PDT 24
Peak memory 216676 kb
Host smart-aa0aaf5a-cedb-4753-8fc5-f7742e2ba89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107730087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3107730087
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1028872368
Short name T343
Test name
Test status
Simulation time 2338286279 ps
CPU time 20.51 seconds
Started Jul 01 10:50:12 AM PDT 24
Finished Jul 01 10:50:36 AM PDT 24
Peak memory 217652 kb
Host smart-a245ec40-67c4-4758-b7d9-bb8509f4b1b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028872368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1028872368
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3568141493
Short name T166
Test name
Test status
Simulation time 4920798492 ps
CPU time 23.63 seconds
Started Jul 01 10:50:21 AM PDT 24
Finished Jul 01 10:50:45 AM PDT 24
Peak memory 217572 kb
Host smart-6d16ca0f-3a0e-4cb4-b8e4-793dea772d70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568141493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3568141493
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1457738525
Short name T43
Test name
Test status
Simulation time 869651393583 ps
CPU time 469.71 seconds
Started Jul 01 10:50:17 AM PDT 24
Finished Jul 01 10:58:08 AM PDT 24
Peak memory 240588 kb
Host smart-571fccfd-b665-47a5-83b2-6a3545036944
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457738525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1457738525
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1193724044
Short name T230
Test name
Test status
Simulation time 21215176252 ps
CPU time 45.55 seconds
Started Jul 01 10:50:33 AM PDT 24
Finished Jul 01 10:51:20 AM PDT 24
Peak memory 219124 kb
Host smart-574d88b3-f002-42f1-85db-0e8a15acfb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193724044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1193724044
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3388244789
Short name T283
Test name
Test status
Simulation time 3533587909 ps
CPU time 30.04 seconds
Started Jul 01 10:50:16 AM PDT 24
Finished Jul 01 10:50:48 AM PDT 24
Peak memory 219388 kb
Host smart-8fb89ce3-7826-4464-a914-91bdd4b17131
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3388244789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3388244789
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1451629808
Short name T281
Test name
Test status
Simulation time 16452823305 ps
CPU time 44.32 seconds
Started Jul 01 10:50:15 AM PDT 24
Finished Jul 01 10:51:02 AM PDT 24
Peak memory 215600 kb
Host smart-f023fe8c-ad88-427c-9881-db54e79597d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451629808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1451629808
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3054761138
Short name T228
Test name
Test status
Simulation time 13249775390 ps
CPU time 98.6 seconds
Started Jul 01 10:50:14 AM PDT 24
Finished Jul 01 10:51:56 AM PDT 24
Peak memory 219384 kb
Host smart-82c81cea-255e-4b21-a87b-1236a4627123
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054761138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3054761138
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3898006524
Short name T206
Test name
Test status
Simulation time 5700137633 ps
CPU time 33.98 seconds
Started Jul 01 10:50:17 AM PDT 24
Finished Jul 01 10:50:53 AM PDT 24
Peak memory 217696 kb
Host smart-5011e9b1-f460-4a46-9607-197453b0d4dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898006524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3898006524
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2385223944
Short name T349
Test name
Test status
Simulation time 53451269579 ps
CPU time 640.56 seconds
Started Jul 01 10:50:19 AM PDT 24
Finished Jul 01 11:01:00 AM PDT 24
Peak memory 218084 kb
Host smart-1588bdf1-3d23-4a2a-9023-c6f7abd6c725
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385223944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2385223944
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3433857491
Short name T132
Test name
Test status
Simulation time 38380187839 ps
CPU time 35.78 seconds
Started Jul 01 10:50:18 AM PDT 24
Finished Jul 01 10:50:55 AM PDT 24
Peak memory 219384 kb
Host smart-d65b7068-a21a-4587-b355-6f4bcf32e4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433857491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3433857491
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.4068592993
Short name T294
Test name
Test status
Simulation time 735445611 ps
CPU time 10.71 seconds
Started Jul 01 10:50:19 AM PDT 24
Finished Jul 01 10:50:31 AM PDT 24
Peak memory 219260 kb
Host smart-52b453e2-af2b-40a6-9cfe-c08ad3d4a575
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4068592993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.4068592993
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.2844306827
Short name T172
Test name
Test status
Simulation time 2604514965 ps
CPU time 31.14 seconds
Started Jul 01 10:50:18 AM PDT 24
Finished Jul 01 10:50:50 AM PDT 24
Peak memory 216384 kb
Host smart-216e7e7c-4255-4548-bbc9-2bbe4a628f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844306827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2844306827
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2270215478
Short name T332
Test name
Test status
Simulation time 11226269605 ps
CPU time 68 seconds
Started Jul 01 10:50:19 AM PDT 24
Finished Jul 01 10:51:27 AM PDT 24
Peak memory 217596 kb
Host smart-35b3d2e8-9eba-4c70-b731-93c89ce5eccd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270215478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2270215478
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3182538119
Short name T24
Test name
Test status
Simulation time 3993687108 ps
CPU time 30.18 seconds
Started Jul 01 10:50:19 AM PDT 24
Finished Jul 01 10:50:50 AM PDT 24
Peak memory 217208 kb
Host smart-fc919cbe-357a-45b4-868a-592430b88c48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182538119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3182538119
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1039282789
Short name T35
Test name
Test status
Simulation time 45435260612 ps
CPU time 449.32 seconds
Started Jul 01 10:50:17 AM PDT 24
Finished Jul 01 10:57:48 AM PDT 24
Peak memory 236888 kb
Host smart-8ee789d0-f659-4d0d-939e-25941f764d5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039282789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1039282789
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2818941357
Short name T23
Test name
Test status
Simulation time 8061099166 ps
CPU time 63.82 seconds
Started Jul 01 10:50:18 AM PDT 24
Finished Jul 01 10:51:23 AM PDT 24
Peak memory 219380 kb
Host smart-f29c4b3e-03a0-4705-befb-c740207b0390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818941357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2818941357
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1645885827
Short name T208
Test name
Test status
Simulation time 4154173347 ps
CPU time 30.6 seconds
Started Jul 01 10:50:19 AM PDT 24
Finished Jul 01 10:50:51 AM PDT 24
Peak memory 219404 kb
Host smart-57ae2525-fa8a-4ca8-8176-2d074cb9c207
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1645885827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1645885827
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.711268422
Short name T48
Test name
Test status
Simulation time 8376353749 ps
CPU time 64.72 seconds
Started Jul 01 10:50:46 AM PDT 24
Finished Jul 01 10:51:51 AM PDT 24
Peak memory 216860 kb
Host smart-9d9a7a6b-858b-4c4f-bbbc-82884db4cccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711268422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.711268422
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1140971764
Short name T233
Test name
Test status
Simulation time 11588119264 ps
CPU time 55.99 seconds
Started Jul 01 10:50:19 AM PDT 24
Finished Jul 01 10:51:16 AM PDT 24
Peak memory 217548 kb
Host smart-cdbdc81d-3f21-4cbc-b5ae-1c489c3f686b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140971764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1140971764
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.886148436
Short name T280
Test name
Test status
Simulation time 170875169 ps
CPU time 8.34 seconds
Started Jul 01 10:50:22 AM PDT 24
Finished Jul 01 10:50:31 AM PDT 24
Peak memory 217052 kb
Host smart-e9e57e86-268e-4926-b1c5-f72e28ad9d27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886148436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.886148436
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1753509649
Short name T150
Test name
Test status
Simulation time 8056375494 ps
CPU time 306.85 seconds
Started Jul 01 10:50:23 AM PDT 24
Finished Jul 01 10:55:31 AM PDT 24
Peak memory 240436 kb
Host smart-27b15bd6-d215-4e3c-bb12-87bb00a5e7c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753509649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1753509649
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3010760521
Short name T310
Test name
Test status
Simulation time 2437736501 ps
CPU time 23.78 seconds
Started Jul 01 10:50:22 AM PDT 24
Finished Jul 01 10:50:46 AM PDT 24
Peak memory 219356 kb
Host smart-8763463f-9b5c-4f17-9519-09e0fdaa58fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010760521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3010760521
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.575470241
Short name T276
Test name
Test status
Simulation time 17086539973 ps
CPU time 34.27 seconds
Started Jul 01 10:50:39 AM PDT 24
Finished Jul 01 10:51:14 AM PDT 24
Peak memory 211756 kb
Host smart-d4d349ba-7418-4b99-b858-8dc06c8c1b16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=575470241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.575470241
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.512063067
Short name T158
Test name
Test status
Simulation time 16728598211 ps
CPU time 74.69 seconds
Started Jul 01 10:50:45 AM PDT 24
Finished Jul 01 10:52:00 AM PDT 24
Peak memory 216804 kb
Host smart-34e91433-639d-4514-b2d2-91ff5fe06fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512063067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.512063067
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1831967046
Short name T32
Test name
Test status
Simulation time 20395649295 ps
CPU time 59.57 seconds
Started Jul 01 10:50:20 AM PDT 24
Finished Jul 01 10:51:20 AM PDT 24
Peak memory 219376 kb
Host smart-9cbc8989-c07b-4afc-8a96-db4fe744d3ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831967046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1831967046
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1832261894
Short name T313
Test name
Test status
Simulation time 10747974327 ps
CPU time 19.41 seconds
Started Jul 01 10:50:21 AM PDT 24
Finished Jul 01 10:50:40 AM PDT 24
Peak memory 217632 kb
Host smart-476b0209-b815-4d90-b688-eb43181dc81f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832261894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1832261894
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1527750683
Short name T261
Test name
Test status
Simulation time 91219287944 ps
CPU time 462.96 seconds
Started Jul 01 10:50:29 AM PDT 24
Finished Jul 01 10:58:13 AM PDT 24
Peak memory 232756 kb
Host smart-1f5a3673-9c40-4640-9622-016b7df78d7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527750683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1527750683
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2000791708
Short name T50
Test name
Test status
Simulation time 365100005 ps
CPU time 19.61 seconds
Started Jul 01 10:50:24 AM PDT 24
Finished Jul 01 10:50:44 AM PDT 24
Peak memory 219292 kb
Host smart-b203351b-7237-4e31-b01b-d2c42abce6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000791708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2000791708
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3586650236
Short name T151
Test name
Test status
Simulation time 18294920603 ps
CPU time 16.06 seconds
Started Jul 01 10:50:27 AM PDT 24
Finished Jul 01 10:50:43 AM PDT 24
Peak memory 219112 kb
Host smart-141e3696-84c1-46e6-a4d7-c70cf3790125
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3586650236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3586650236
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2974156945
Short name T164
Test name
Test status
Simulation time 1429997654 ps
CPU time 19.99 seconds
Started Jul 01 10:50:45 AM PDT 24
Finished Jul 01 10:51:05 AM PDT 24
Peak memory 215932 kb
Host smart-b50fa2c5-6ea2-436b-a0b3-d262cd26b4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974156945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2974156945
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2185855789
Short name T147
Test name
Test status
Simulation time 38279990527 ps
CPU time 217.15 seconds
Started Jul 01 10:50:30 AM PDT 24
Finished Jul 01 10:54:08 AM PDT 24
Peak memory 222536 kb
Host smart-3c6a8da8-71e1-4a5b-a3f5-160b813b923c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185855789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2185855789
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3031585811
Short name T251
Test name
Test status
Simulation time 48269849957 ps
CPU time 31.08 seconds
Started Jul 01 10:50:43 AM PDT 24
Finished Jul 01 10:51:14 AM PDT 24
Peak memory 217460 kb
Host smart-63761fab-846b-4bbe-bda6-6359d7a118e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031585811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3031585811
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3424089101
Short name T273
Test name
Test status
Simulation time 63970219069 ps
CPU time 331.59 seconds
Started Jul 01 10:50:24 AM PDT 24
Finished Jul 01 10:55:56 AM PDT 24
Peak memory 219416 kb
Host smart-6d52a21b-ee70-4ce6-b837-c590f22f641d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424089101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3424089101
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2562827424
Short name T128
Test name
Test status
Simulation time 3958110924 ps
CPU time 25.69 seconds
Started Jul 01 10:50:20 AM PDT 24
Finished Jul 01 10:50:46 AM PDT 24
Peak memory 219236 kb
Host smart-1013fe85-9c18-4e81-afcc-b752a567d35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562827424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2562827424
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1314708485
Short name T177
Test name
Test status
Simulation time 176192704 ps
CPU time 10.32 seconds
Started Jul 01 10:50:21 AM PDT 24
Finished Jul 01 10:50:33 AM PDT 24
Peak memory 219288 kb
Host smart-b04c4661-d0c7-4184-849e-6a7eef71109a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1314708485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1314708485
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3605681227
Short name T284
Test name
Test status
Simulation time 41110772993 ps
CPU time 57.23 seconds
Started Jul 01 10:50:48 AM PDT 24
Finished Jul 01 10:51:45 AM PDT 24
Peak memory 217252 kb
Host smart-8f46d944-34f1-4f34-b3e7-ab77ce37f43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605681227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3605681227
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.382505661
Short name T139
Test name
Test status
Simulation time 13264253723 ps
CPU time 54.44 seconds
Started Jul 01 10:50:37 AM PDT 24
Finished Jul 01 10:51:32 AM PDT 24
Peak memory 219228 kb
Host smart-99f36402-3297-499c-9e82-3d8ef8cc7d21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382505661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.382505661
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1585985613
Short name T270
Test name
Test status
Simulation time 5853645436 ps
CPU time 18.43 seconds
Started Jul 01 10:50:09 AM PDT 24
Finished Jul 01 10:50:31 AM PDT 24
Peak memory 217472 kb
Host smart-b28a0069-0c55-44da-a8cd-dc89a087d440
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585985613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1585985613
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1456918077
Short name T167
Test name
Test status
Simulation time 32866939662 ps
CPU time 388.17 seconds
Started Jul 01 10:50:11 AM PDT 24
Finished Jul 01 10:56:43 AM PDT 24
Peak memory 238092 kb
Host smart-c93796eb-5a0c-4a95-989b-70ff507a993e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456918077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1456918077
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3831939556
Short name T190
Test name
Test status
Simulation time 1377230287 ps
CPU time 19.33 seconds
Started Jul 01 10:50:13 AM PDT 24
Finished Jul 01 10:50:36 AM PDT 24
Peak memory 219208 kb
Host smart-b8661684-41fe-4fc3-87bf-9aae728168ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831939556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3831939556
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1281774959
Short name T234
Test name
Test status
Simulation time 1778620928 ps
CPU time 19.77 seconds
Started Jul 01 10:50:09 AM PDT 24
Finished Jul 01 10:50:32 AM PDT 24
Peak memory 211248 kb
Host smart-09cafe56-e9f9-4f7b-8a02-ee27f8e46285
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1281774959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1281774959
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1476202675
Short name T28
Test name
Test status
Simulation time 623846528 ps
CPU time 231.86 seconds
Started Jul 01 10:50:07 AM PDT 24
Finished Jul 01 10:54:00 AM PDT 24
Peak memory 237968 kb
Host smart-4a99bf73-2523-4bdd-8447-11596ca6131a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476202675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1476202675
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2232840991
Short name T188
Test name
Test status
Simulation time 6120137806 ps
CPU time 55.48 seconds
Started Jul 01 10:50:08 AM PDT 24
Finished Jul 01 10:51:07 AM PDT 24
Peak memory 217084 kb
Host smart-1449ed43-71bb-4b6e-93c2-fa763069dcb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232840991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2232840991
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.617031411
Short name T31
Test name
Test status
Simulation time 4205392258 ps
CPU time 42.58 seconds
Started Jul 01 10:50:13 AM PDT 24
Finished Jul 01 10:50:59 AM PDT 24
Peak memory 216600 kb
Host smart-ebe6858c-4b64-41bd-8b2f-28c1400f0846
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617031411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.617031411
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1686136009
Short name T60
Test name
Test status
Simulation time 180920893654 ps
CPU time 1698.3 seconds
Started Jul 01 10:50:08 AM PDT 24
Finished Jul 01 11:18:29 AM PDT 24
Peak memory 244008 kb
Host smart-79f0c74d-9c6b-40b2-b0a6-47965d8b3f4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686136009 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.1686136009
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1475814218
Short name T185
Test name
Test status
Simulation time 15292918463 ps
CPU time 29.52 seconds
Started Jul 01 10:50:36 AM PDT 24
Finished Jul 01 10:51:06 AM PDT 24
Peak memory 217564 kb
Host smart-c7adae15-9f32-403e-b5db-6d7825cf06c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475814218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1475814218
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3411049187
Short name T189
Test name
Test status
Simulation time 199814774317 ps
CPU time 549.16 seconds
Started Jul 01 10:50:24 AM PDT 24
Finished Jul 01 10:59:34 AM PDT 24
Peak memory 217784 kb
Host smart-fc649748-dafe-46d6-ba40-db18772ab203
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411049187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3411049187
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1522539327
Short name T278
Test name
Test status
Simulation time 346075028 ps
CPU time 19.31 seconds
Started Jul 01 10:50:44 AM PDT 24
Finished Jul 01 10:51:04 AM PDT 24
Peak memory 219328 kb
Host smart-fef50f94-5648-4d6e-ace5-a75ac1e7bb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522539327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1522539327
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2599120858
Short name T34
Test name
Test status
Simulation time 182155429 ps
CPU time 10.3 seconds
Started Jul 01 10:50:40 AM PDT 24
Finished Jul 01 10:50:51 AM PDT 24
Peak memory 219252 kb
Host smart-fcff15bd-7d46-4e57-9fe6-e65ea6d7bb00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2599120858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2599120858
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3352044298
Short name T143
Test name
Test status
Simulation time 2796312271 ps
CPU time 19.45 seconds
Started Jul 01 10:50:25 AM PDT 24
Finished Jul 01 10:50:45 AM PDT 24
Peak memory 217496 kb
Host smart-e67654ad-5a59-45e2-9971-86aa9d198df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352044298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3352044298
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2883505604
Short name T144
Test name
Test status
Simulation time 13092448559 ps
CPU time 72.02 seconds
Started Jul 01 10:50:22 AM PDT 24
Finished Jul 01 10:51:35 AM PDT 24
Peak memory 219424 kb
Host smart-7dcbc025-4ca7-4212-a427-1c7b1254f220
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883505604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2883505604
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.907371561
Short name T51
Test name
Test status
Simulation time 3863787879 ps
CPU time 30.22 seconds
Started Jul 01 10:50:38 AM PDT 24
Finished Jul 01 10:51:09 AM PDT 24
Peak memory 217276 kb
Host smart-10de4f9b-2c52-4a9a-8ccf-e888da0b01fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907371561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.907371561
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.715149990
Short name T45
Test name
Test status
Simulation time 9869485562 ps
CPU time 323.35 seconds
Started Jul 01 10:50:20 AM PDT 24
Finished Jul 01 10:55:44 AM PDT 24
Peak memory 219492 kb
Host smart-6bab800a-c594-417f-94b5-fd87743b54b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715149990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.715149990
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.4091349346
Short name T239
Test name
Test status
Simulation time 24894996693 ps
CPU time 53.76 seconds
Started Jul 01 10:50:43 AM PDT 24
Finished Jul 01 10:51:37 AM PDT 24
Peak memory 219340 kb
Host smart-909554be-4080-4be5-9b3c-11db42e9b451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091349346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.4091349346
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1916841033
Short name T10
Test name
Test status
Simulation time 21242035469 ps
CPU time 19.17 seconds
Started Jul 01 10:50:36 AM PDT 24
Finished Jul 01 10:50:55 AM PDT 24
Peak memory 217720 kb
Host smart-81c52875-2eae-4b4f-81b1-3950dd101569
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1916841033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1916841033
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2253128211
Short name T67
Test name
Test status
Simulation time 4096059897 ps
CPU time 47.44 seconds
Started Jul 01 10:50:37 AM PDT 24
Finished Jul 01 10:51:25 AM PDT 24
Peak memory 216172 kb
Host smart-01d544d7-c333-4cfe-ba38-d4a93d1f26cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253128211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2253128211
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2333898739
Short name T227
Test name
Test status
Simulation time 28925534700 ps
CPU time 203.12 seconds
Started Jul 01 10:50:28 AM PDT 24
Finished Jul 01 10:53:52 AM PDT 24
Peak memory 222760 kb
Host smart-24054097-0bb8-432b-8da1-f6ed1fb69351
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333898739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2333898739
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.3235832025
Short name T63
Test name
Test status
Simulation time 11453503743 ps
CPU time 292.85 seconds
Started Jul 01 10:50:37 AM PDT 24
Finished Jul 01 10:55:30 AM PDT 24
Peak memory 224340 kb
Host smart-0a1b98e7-3e92-4294-ad15-d7273f32c838
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235832025 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.3235832025
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2809748334
Short name T223
Test name
Test status
Simulation time 601709129 ps
CPU time 12.35 seconds
Started Jul 01 10:50:32 AM PDT 24
Finished Jul 01 10:50:44 AM PDT 24
Peak memory 217180 kb
Host smart-8fe95e93-2c87-42b1-a821-fd8a06210ad9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809748334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2809748334
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.4023991341
Short name T331
Test name
Test status
Simulation time 54099942092 ps
CPU time 583.66 seconds
Started Jul 01 10:50:40 AM PDT 24
Finished Jul 01 11:00:25 AM PDT 24
Peak memory 233932 kb
Host smart-fdfee282-ecdd-47a8-b01d-09e2cb96fe80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023991341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.4023991341
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3684214993
Short name T161
Test name
Test status
Simulation time 1270537181 ps
CPU time 19.16 seconds
Started Jul 01 10:50:25 AM PDT 24
Finished Jul 01 10:50:45 AM PDT 24
Peak memory 219176 kb
Host smart-be9d5e91-8e05-4eae-889a-c6b7ec57f457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684214993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3684214993
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.694879622
Short name T335
Test name
Test status
Simulation time 17367509484 ps
CPU time 26.26 seconds
Started Jul 01 10:50:38 AM PDT 24
Finished Jul 01 10:51:05 AM PDT 24
Peak memory 219256 kb
Host smart-e4cdca32-d736-4ac2-9263-81f43e4b9c40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=694879622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.694879622
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2158930894
Short name T183
Test name
Test status
Simulation time 71621403905 ps
CPU time 75.67 seconds
Started Jul 01 10:50:37 AM PDT 24
Finished Jul 01 10:51:53 AM PDT 24
Peak memory 216716 kb
Host smart-9652e192-e402-43f9-bc57-8a2afa03eecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158930894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2158930894
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2653626182
Short name T231
Test name
Test status
Simulation time 1048696296 ps
CPU time 33.62 seconds
Started Jul 01 10:50:27 AM PDT 24
Finished Jul 01 10:51:01 AM PDT 24
Peak memory 219296 kb
Host smart-43ff7b29-9bf5-4f7e-838a-08cf40a771b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653626182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2653626182
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1043062764
Short name T210
Test name
Test status
Simulation time 369010609 ps
CPU time 8.37 seconds
Started Jul 01 10:50:32 AM PDT 24
Finished Jul 01 10:50:41 AM PDT 24
Peak memory 217128 kb
Host smart-c03967a3-bd2d-43e6-99c4-18258b3b03fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043062764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1043062764
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.656230328
Short name T299
Test name
Test status
Simulation time 222160063857 ps
CPU time 1109.27 seconds
Started Jul 01 10:50:27 AM PDT 24
Finished Jul 01 11:08:57 AM PDT 24
Peak memory 234236 kb
Host smart-e3465e41-ba06-409e-8e74-6ce43cf19a67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656230328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.656230328
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2425350048
Short name T267
Test name
Test status
Simulation time 5016013837 ps
CPU time 48.39 seconds
Started Jul 01 10:50:34 AM PDT 24
Finished Jul 01 10:51:23 AM PDT 24
Peak memory 219368 kb
Host smart-4e529cfc-237a-4f7f-9df5-06d62da018c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425350048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2425350048
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3762247606
Short name T137
Test name
Test status
Simulation time 4450450763 ps
CPU time 33.22 seconds
Started Jul 01 10:50:50 AM PDT 24
Finished Jul 01 10:51:24 AM PDT 24
Peak memory 219488 kb
Host smart-b23edd73-59dd-4623-92a9-409ae9914913
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3762247606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3762247606
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3816729669
Short name T49
Test name
Test status
Simulation time 1384911892 ps
CPU time 28.52 seconds
Started Jul 01 10:50:30 AM PDT 24
Finished Jul 01 10:50:59 AM PDT 24
Peak memory 216340 kb
Host smart-5b45d84b-09db-4e98-84ab-ed62ba31f14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816729669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3816729669
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2405119792
Short name T136
Test name
Test status
Simulation time 2170900099 ps
CPU time 25.66 seconds
Started Jul 01 10:50:27 AM PDT 24
Finished Jul 01 10:50:53 AM PDT 24
Peak memory 214632 kb
Host smart-b1975d50-04e7-429a-bc39-d054399c5af5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405119792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2405119792
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2016730770
Short name T320
Test name
Test status
Simulation time 1376834344 ps
CPU time 10.22 seconds
Started Jul 01 10:50:29 AM PDT 24
Finished Jul 01 10:50:40 AM PDT 24
Peak memory 213212 kb
Host smart-bc40bd0f-f2c6-4838-a674-4d5cefe1bc2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016730770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2016730770
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1382552041
Short name T44
Test name
Test status
Simulation time 36938867948 ps
CPU time 411.62 seconds
Started Jul 01 10:50:28 AM PDT 24
Finished Jul 01 10:57:20 AM PDT 24
Peak memory 219508 kb
Host smart-ba17bc10-d790-4b3d-bfbb-4c957cd59c6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382552041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1382552041
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1037273014
Short name T314
Test name
Test status
Simulation time 5747736950 ps
CPU time 53.41 seconds
Started Jul 01 10:50:35 AM PDT 24
Finished Jul 01 10:51:29 AM PDT 24
Peak memory 219384 kb
Host smart-bc1a84c5-bfec-47a4-8ef6-cb6164ec5519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037273014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1037273014
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1964815753
Short name T265
Test name
Test status
Simulation time 717691397 ps
CPU time 10.15 seconds
Started Jul 01 10:50:55 AM PDT 24
Finished Jul 01 10:51:05 AM PDT 24
Peak memory 219400 kb
Host smart-0ea89041-9d68-49f7-9b1b-940c6b47bd43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1964815753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1964815753
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3523106922
Short name T255
Test name
Test status
Simulation time 7056215195 ps
CPU time 44.1 seconds
Started Jul 01 10:50:47 AM PDT 24
Finished Jul 01 10:51:32 AM PDT 24
Peak memory 216800 kb
Host smart-e8bbfc0b-3005-438d-bd95-6112876326ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523106922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3523106922
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.4267032405
Short name T260
Test name
Test status
Simulation time 19227462427 ps
CPU time 151.85 seconds
Started Jul 01 10:50:29 AM PDT 24
Finished Jul 01 10:53:02 AM PDT 24
Peak memory 220920 kb
Host smart-533f5ba6-96ef-4743-b1e4-c20c387595e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267032405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.4267032405
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1769289331
Short name T309
Test name
Test status
Simulation time 12278202803 ps
CPU time 19.47 seconds
Started Jul 01 10:50:29 AM PDT 24
Finished Jul 01 10:50:49 AM PDT 24
Peak memory 217568 kb
Host smart-cb5e8ebb-d9ab-408f-abe4-117f405f634c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769289331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1769289331
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3192267490
Short name T38
Test name
Test status
Simulation time 3346993924 ps
CPU time 213.49 seconds
Started Jul 01 10:50:25 AM PDT 24
Finished Jul 01 10:53:59 AM PDT 24
Peak memory 229316 kb
Host smart-c5b76960-8012-4a5d-bc05-8ec020af0037
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192267490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3192267490
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3403249799
Short name T301
Test name
Test status
Simulation time 7695020640 ps
CPU time 42.34 seconds
Started Jul 01 10:50:41 AM PDT 24
Finished Jul 01 10:51:24 AM PDT 24
Peak memory 219272 kb
Host smart-97dfbfc0-0cf8-4425-8424-cbb19c767ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403249799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3403249799
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3138996765
Short name T168
Test name
Test status
Simulation time 5865885352 ps
CPU time 18.94 seconds
Started Jul 01 10:50:27 AM PDT 24
Finished Jul 01 10:50:47 AM PDT 24
Peak memory 217792 kb
Host smart-e0c00804-efce-41fc-8bf3-69f45258d7ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3138996765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3138996765
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.67293560
Short name T302
Test name
Test status
Simulation time 8551194583 ps
CPU time 65.61 seconds
Started Jul 01 10:50:32 AM PDT 24
Finished Jul 01 10:51:38 AM PDT 24
Peak memory 217440 kb
Host smart-1e507ef4-2ca9-44cf-8f5a-65713199e58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67293560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.67293560
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1202786371
Short name T178
Test name
Test status
Simulation time 10787208749 ps
CPU time 41.35 seconds
Started Jul 01 10:50:35 AM PDT 24
Finished Jul 01 10:51:17 AM PDT 24
Peak memory 219416 kb
Host smart-19ec0411-dd18-49dd-a0b5-b600f7f6c8ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202786371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1202786371
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3922373618
Short name T325
Test name
Test status
Simulation time 768639465 ps
CPU time 13.79 seconds
Started Jul 01 10:50:43 AM PDT 24
Finished Jul 01 10:50:57 AM PDT 24
Peak memory 217048 kb
Host smart-727e5108-cb20-4d80-9ba8-40a24eaec542
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922373618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3922373618
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2732300923
Short name T135
Test name
Test status
Simulation time 17477888285 ps
CPU time 444.35 seconds
Started Jul 01 10:50:31 AM PDT 24
Finished Jul 01 10:57:56 AM PDT 24
Peak memory 230864 kb
Host smart-deb529e1-2ca2-42f4-8319-56c41312dfcd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732300923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2732300923
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3589688533
Short name T152
Test name
Test status
Simulation time 580321122 ps
CPU time 19.12 seconds
Started Jul 01 10:50:44 AM PDT 24
Finished Jul 01 10:51:03 AM PDT 24
Peak memory 219312 kb
Host smart-cbbd18ee-ff5e-45e8-8e52-6e24371eabcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589688533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3589688533
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2109482491
Short name T218
Test name
Test status
Simulation time 29272522439 ps
CPU time 22.7 seconds
Started Jul 01 10:50:55 AM PDT 24
Finished Jul 01 10:51:18 AM PDT 24
Peak memory 218016 kb
Host smart-2be36ed5-32b1-4896-959f-f7d4bc3384ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2109482491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2109482491
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.193009138
Short name T287
Test name
Test status
Simulation time 1502863632 ps
CPU time 20.31 seconds
Started Jul 01 10:50:54 AM PDT 24
Finished Jul 01 10:51:15 AM PDT 24
Peak memory 215972 kb
Host smart-8492a083-11b8-4a2a-bf56-d39cfed04140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193009138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.193009138
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2277589899
Short name T131
Test name
Test status
Simulation time 8581888932 ps
CPU time 113.45 seconds
Started Jul 01 10:50:51 AM PDT 24
Finished Jul 01 10:52:45 AM PDT 24
Peak memory 220448 kb
Host smart-e30c7466-9855-45fb-84c8-459dd8d679ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277589899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2277589899
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.4148309470
Short name T80
Test name
Test status
Simulation time 1265555329 ps
CPU time 13.28 seconds
Started Jul 01 10:50:39 AM PDT 24
Finished Jul 01 10:50:53 AM PDT 24
Peak memory 217236 kb
Host smart-7ad50221-9604-4624-9d6e-aeca60cd5640
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148309470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.4148309470
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3396135624
Short name T171
Test name
Test status
Simulation time 13730631729 ps
CPU time 241.86 seconds
Started Jul 01 10:50:31 AM PDT 24
Finished Jul 01 10:54:33 AM PDT 24
Peak memory 234724 kb
Host smart-e30b5650-1707-447a-b39d-d4d76dcd11a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396135624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3396135624
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3440589710
Short name T326
Test name
Test status
Simulation time 16430651486 ps
CPU time 36.1 seconds
Started Jul 01 10:50:33 AM PDT 24
Finished Jul 01 10:51:10 AM PDT 24
Peak memory 219336 kb
Host smart-b500b7e3-1602-4fa3-b52b-5373951d21ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440589710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3440589710
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.4215585678
Short name T202
Test name
Test status
Simulation time 183519618 ps
CPU time 10.18 seconds
Started Jul 01 10:50:56 AM PDT 24
Finished Jul 01 10:51:08 AM PDT 24
Peak memory 219300 kb
Host smart-b82de04e-3709-4178-8e5a-87b3b8384146
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4215585678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.4215585678
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.1718861231
Short name T12
Test name
Test status
Simulation time 1502101545 ps
CPU time 19.24 seconds
Started Jul 01 10:50:33 AM PDT 24
Finished Jul 01 10:50:53 AM PDT 24
Peak memory 216552 kb
Host smart-9ff5a505-9668-4b9d-97d4-a636bae1d072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718861231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.1718861231
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1438330581
Short name T122
Test name
Test status
Simulation time 14553620403 ps
CPU time 35.57 seconds
Started Jul 01 10:50:31 AM PDT 24
Finished Jul 01 10:51:07 AM PDT 24
Peak memory 214660 kb
Host smart-c205ee3f-e201-41ef-92a8-973b4f14427c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438330581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1438330581
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.789329121
Short name T271
Test name
Test status
Simulation time 4093058440 ps
CPU time 19.97 seconds
Started Jul 01 10:50:32 AM PDT 24
Finished Jul 01 10:50:52 AM PDT 24
Peak memory 217252 kb
Host smart-f9f6a9d1-bf60-47f3-af33-8aed6ef2276b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789329121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.789329121
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.292194102
Short name T36
Test name
Test status
Simulation time 4537240681 ps
CPU time 278.61 seconds
Started Jul 01 10:50:39 AM PDT 24
Finished Jul 01 10:55:19 AM PDT 24
Peak memory 238568 kb
Host smart-0b22157d-fecc-46aa-845b-2041a37509c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292194102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.292194102
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.584815840
Short name T212
Test name
Test status
Simulation time 17873779895 ps
CPU time 32.72 seconds
Started Jul 01 10:50:51 AM PDT 24
Finished Jul 01 10:51:24 AM PDT 24
Peak memory 218996 kb
Host smart-30ab6327-44a3-4ec1-94f4-3851731a1bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584815840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.584815840
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3573430423
Short name T351
Test name
Test status
Simulation time 5064317015 ps
CPU time 24 seconds
Started Jul 01 10:50:32 AM PDT 24
Finished Jul 01 10:50:57 AM PDT 24
Peak memory 211600 kb
Host smart-1db6c926-2ccf-4d58-bcd5-10e5c4b89d6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3573430423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3573430423
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2728444709
Short name T2
Test name
Test status
Simulation time 4832133390 ps
CPU time 37.3 seconds
Started Jul 01 10:50:51 AM PDT 24
Finished Jul 01 10:51:29 AM PDT 24
Peak memory 217008 kb
Host smart-59c9dd0a-1db7-4891-84c7-b1234658b064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728444709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2728444709
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2417591403
Short name T5
Test name
Test status
Simulation time 790938948 ps
CPU time 28.98 seconds
Started Jul 01 10:50:56 AM PDT 24
Finished Jul 01 10:51:26 AM PDT 24
Peak memory 219276 kb
Host smart-2f65133e-a816-4628-af16-a9eb58468bf7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417591403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2417591403
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2221369746
Short name T59
Test name
Test status
Simulation time 54509966718 ps
CPU time 6668.25 seconds
Started Jul 01 10:50:32 AM PDT 24
Finished Jul 01 12:41:42 PM PDT 24
Peak memory 234600 kb
Host smart-e422c6a7-adb4-4bef-8b66-9c50b63dba5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221369746 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.2221369746
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3808252047
Short name T79
Test name
Test status
Simulation time 918168335 ps
CPU time 14.41 seconds
Started Jul 01 10:50:33 AM PDT 24
Finished Jul 01 10:50:48 AM PDT 24
Peak memory 217156 kb
Host smart-3ad90312-ec2d-4234-b252-6b8a9395bd4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808252047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3808252047
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3786375200
Short name T289
Test name
Test status
Simulation time 4980098948 ps
CPU time 185.74 seconds
Started Jul 01 10:50:34 AM PDT 24
Finished Jul 01 10:53:40 AM PDT 24
Peak memory 240196 kb
Host smart-de3f2468-c6e1-4768-9e1e-9b11d6f864d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786375200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3786375200
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.487351402
Short name T26
Test name
Test status
Simulation time 72062367776 ps
CPU time 40.57 seconds
Started Jul 01 10:50:42 AM PDT 24
Finished Jul 01 10:51:23 AM PDT 24
Peak memory 219388 kb
Host smart-c6002206-3ae6-4fdb-b10b-002b8cad7c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487351402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.487351402
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2771230793
Short name T70
Test name
Test status
Simulation time 348173641 ps
CPU time 10.46 seconds
Started Jul 01 10:50:37 AM PDT 24
Finished Jul 01 10:50:48 AM PDT 24
Peak memory 219416 kb
Host smart-2e171086-73a5-4ea0-9afb-9bcb0a548b7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2771230793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2771230793
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1791588122
Short name T244
Test name
Test status
Simulation time 4778278257 ps
CPU time 47.97 seconds
Started Jul 01 10:50:35 AM PDT 24
Finished Jul 01 10:51:23 AM PDT 24
Peak memory 217032 kb
Host smart-8dfd5a8a-35da-4d45-ab80-01449ad40455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791588122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1791588122
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2250575655
Short name T176
Test name
Test status
Simulation time 8302526178 ps
CPU time 33.5 seconds
Started Jul 01 10:50:33 AM PDT 24
Finished Jul 01 10:51:07 AM PDT 24
Peak memory 219384 kb
Host smart-a6323474-2140-45e4-81e2-6e8658fbd3f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250575655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2250575655
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1647575800
Short name T259
Test name
Test status
Simulation time 54628898486 ps
CPU time 27.46 seconds
Started Jul 01 10:50:08 AM PDT 24
Finished Jul 01 10:50:44 AM PDT 24
Peak memory 217960 kb
Host smart-6f19508d-2ced-4d62-a52d-b5ff0fd4f06c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647575800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1647575800
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.621040505
Short name T224
Test name
Test status
Simulation time 68829947087 ps
CPU time 689.51 seconds
Started Jul 01 10:50:10 AM PDT 24
Finished Jul 01 11:01:43 AM PDT 24
Peak memory 234344 kb
Host smart-10574aea-47e3-42d6-bb1c-6aeddf5a1aab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621040505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.621040505
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.966635989
Short name T275
Test name
Test status
Simulation time 24275098527 ps
CPU time 57.94 seconds
Started Jul 01 10:50:07 AM PDT 24
Finished Jul 01 10:51:06 AM PDT 24
Peak memory 219408 kb
Host smart-ac208bb5-c94c-491a-80e4-fa61ec9683ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966635989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.966635989
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.414930528
Short name T37
Test name
Test status
Simulation time 21067740121 ps
CPU time 27.26 seconds
Started Jul 01 10:49:58 AM PDT 24
Finished Jul 01 10:50:26 AM PDT 24
Peak memory 211964 kb
Host smart-f09728d8-f25d-4161-9eca-d421a5b9e59f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=414930528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.414930528
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2803027419
Short name T247
Test name
Test status
Simulation time 680249474 ps
CPU time 25.91 seconds
Started Jul 01 10:50:13 AM PDT 24
Finished Jul 01 10:50:42 AM PDT 24
Peak memory 216580 kb
Host smart-01179dee-1e2d-444f-b2a4-10024e5913ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803027419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2803027419
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3322168425
Short name T199
Test name
Test status
Simulation time 40898212197 ps
CPU time 94.34 seconds
Started Jul 01 10:50:09 AM PDT 24
Finished Jul 01 10:51:46 AM PDT 24
Peak memory 219604 kb
Host smart-f0e7f479-7206-4ae2-8eba-9ab4db36df03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322168425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3322168425
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.171806233
Short name T243
Test name
Test status
Simulation time 3562751854 ps
CPU time 27.6 seconds
Started Jul 01 10:50:34 AM PDT 24
Finished Jul 01 10:51:02 AM PDT 24
Peak memory 217168 kb
Host smart-f3bc3672-3fe8-4120-b8b0-7f66bb51e955
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171806233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.171806233
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2537002965
Short name T340
Test name
Test status
Simulation time 49994239297 ps
CPU time 597.2 seconds
Started Jul 01 10:50:50 AM PDT 24
Finished Jul 01 11:00:48 AM PDT 24
Peak memory 239092 kb
Host smart-b6c5abea-9fd3-4e8f-8f1d-dfc408be27a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537002965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2537002965
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2952410873
Short name T306
Test name
Test status
Simulation time 1034322621 ps
CPU time 23.02 seconds
Started Jul 01 10:50:35 AM PDT 24
Finished Jul 01 10:50:59 AM PDT 24
Peak memory 219288 kb
Host smart-78ac16d5-f5eb-452a-bfe0-06d4f8f4b974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952410873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2952410873
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1468095976
Short name T186
Test name
Test status
Simulation time 1151277399 ps
CPU time 10.26 seconds
Started Jul 01 10:50:37 AM PDT 24
Finished Jul 01 10:50:48 AM PDT 24
Peak memory 219300 kb
Host smart-b35ca382-5c4a-48f1-99d3-1ae6c1162afd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1468095976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1468095976
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3842486807
Short name T27
Test name
Test status
Simulation time 786270826 ps
CPU time 19.44 seconds
Started Jul 01 10:50:57 AM PDT 24
Finished Jul 01 10:51:17 AM PDT 24
Peak memory 217400 kb
Host smart-8880fe3d-c8be-4d44-86e4-b235c66a3078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842486807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3842486807
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1104886187
Short name T187
Test name
Test status
Simulation time 41097794832 ps
CPU time 138.09 seconds
Started Jul 01 10:50:51 AM PDT 24
Finished Jul 01 10:53:10 AM PDT 24
Peak memory 220968 kb
Host smart-a482164d-50b4-4b07-a750-2c8481631c75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104886187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1104886187
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.327429163
Short name T124
Test name
Test status
Simulation time 2916182145 ps
CPU time 25.86 seconds
Started Jul 01 10:50:54 AM PDT 24
Finished Jul 01 10:51:21 AM PDT 24
Peak memory 217284 kb
Host smart-2fc18524-2985-4abe-9ff1-5feadbf8993d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327429163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.327429163
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3694596182
Short name T211
Test name
Test status
Simulation time 15184681411 ps
CPU time 265.69 seconds
Started Jul 01 10:50:33 AM PDT 24
Finished Jul 01 10:54:59 AM PDT 24
Peak memory 244584 kb
Host smart-9a1e27f8-961a-440c-acb2-0d3907d6421d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694596182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3694596182
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.422515375
Short name T200
Test name
Test status
Simulation time 13721691066 ps
CPU time 47.94 seconds
Started Jul 01 10:50:33 AM PDT 24
Finished Jul 01 10:51:21 AM PDT 24
Peak memory 219404 kb
Host smart-e39a76a3-a624-40bd-83b7-a6948174d3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422515375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.422515375
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2831137868
Short name T311
Test name
Test status
Simulation time 3963374880 ps
CPU time 30.8 seconds
Started Jul 01 10:50:39 AM PDT 24
Finished Jul 01 10:51:10 AM PDT 24
Peak memory 219404 kb
Host smart-66ad5ec3-a47e-4717-b8bf-a72054c178ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2831137868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2831137868
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3244378487
Short name T282
Test name
Test status
Simulation time 394486258 ps
CPU time 19.99 seconds
Started Jul 01 10:51:00 AM PDT 24
Finished Jul 01 10:51:21 AM PDT 24
Peak memory 216592 kb
Host smart-101d03bc-4922-43fa-91b0-572a431c5f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244378487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3244378487
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3279204390
Short name T75
Test name
Test status
Simulation time 45334973827 ps
CPU time 130.71 seconds
Started Jul 01 10:50:34 AM PDT 24
Finished Jul 01 10:52:45 AM PDT 24
Peak memory 221524 kb
Host smart-197c9dbe-5d27-41e6-8c9a-bf64d0733857
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279204390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3279204390
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.590024581
Short name T47
Test name
Test status
Simulation time 27431980241 ps
CPU time 30.46 seconds
Started Jul 01 10:50:53 AM PDT 24
Finished Jul 01 10:51:24 AM PDT 24
Peak memory 217524 kb
Host smart-b0b66df0-7fc1-4808-a968-bf1ce0b30dce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590024581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.590024581
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1454746388
Short name T41
Test name
Test status
Simulation time 92745854494 ps
CPU time 225.78 seconds
Started Jul 01 10:50:58 AM PDT 24
Finished Jul 01 10:54:45 AM PDT 24
Peak memory 216860 kb
Host smart-66b3e41c-c4a4-416f-9f28-833b73b1eadc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454746388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1454746388
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1876408749
Short name T145
Test name
Test status
Simulation time 29376133929 ps
CPU time 62.2 seconds
Started Jul 01 10:50:41 AM PDT 24
Finished Jul 01 10:51:44 AM PDT 24
Peak memory 219284 kb
Host smart-f97988a1-3e22-4cec-8b66-abe2de90e475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876408749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1876408749
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3216592736
Short name T229
Test name
Test status
Simulation time 349525169 ps
CPU time 10.37 seconds
Started Jul 01 10:50:37 AM PDT 24
Finished Jul 01 10:50:48 AM PDT 24
Peak memory 219300 kb
Host smart-9956e3d5-4425-4fe6-93a7-c6ab709f7e55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3216592736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3216592736
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1486966608
Short name T130
Test name
Test status
Simulation time 7109178379 ps
CPU time 62.23 seconds
Started Jul 01 10:50:34 AM PDT 24
Finished Jul 01 10:51:37 AM PDT 24
Peak memory 216200 kb
Host smart-92e997a4-9779-4aa8-a855-75849d01b4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486966608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1486966608
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3728114989
Short name T248
Test name
Test status
Simulation time 20908876460 ps
CPU time 186.84 seconds
Started Jul 01 10:50:36 AM PDT 24
Finished Jul 01 10:53:44 AM PDT 24
Peak memory 220268 kb
Host smart-9eec1c76-14fe-44c8-8452-dc01e2b5b145
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728114989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3728114989
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2801880978
Short name T341
Test name
Test status
Simulation time 3637562188 ps
CPU time 29.1 seconds
Started Jul 01 10:50:35 AM PDT 24
Finished Jul 01 10:51:05 AM PDT 24
Peak memory 217340 kb
Host smart-c33a2f92-24c8-4147-a23d-b7f96ed4bd94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801880978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2801880978
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2337313190
Short name T316
Test name
Test status
Simulation time 41302507327 ps
CPU time 388.4 seconds
Started Jul 01 10:50:58 AM PDT 24
Finished Jul 01 10:57:28 AM PDT 24
Peak memory 234988 kb
Host smart-4702c39a-ff94-45c3-9862-ec1d823d98b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337313190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2337313190
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.4011889983
Short name T238
Test name
Test status
Simulation time 7864306351 ps
CPU time 63.45 seconds
Started Jul 01 10:50:35 AM PDT 24
Finished Jul 01 10:51:38 AM PDT 24
Peak memory 219368 kb
Host smart-c39a4de0-bd2e-440a-ab5f-c61096092fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011889983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.4011889983
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.511912220
Short name T159
Test name
Test status
Simulation time 360673828 ps
CPU time 12.54 seconds
Started Jul 01 10:50:54 AM PDT 24
Finished Jul 01 10:51:07 AM PDT 24
Peak memory 218564 kb
Host smart-e39528df-37ba-4dfe-8f9b-ade101ac23df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=511912220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.511912220
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3337404208
Short name T129
Test name
Test status
Simulation time 45060773331 ps
CPU time 85.32 seconds
Started Jul 01 10:50:36 AM PDT 24
Finished Jul 01 10:52:02 AM PDT 24
Peak memory 216700 kb
Host smart-b4421dd2-6a00-4622-878e-35949a4c16fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337404208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3337404208
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.301522380
Short name T194
Test name
Test status
Simulation time 13222764823 ps
CPU time 111.03 seconds
Started Jul 01 10:50:49 AM PDT 24
Finished Jul 01 10:52:41 AM PDT 24
Peak memory 219308 kb
Host smart-413371f5-0c83-4999-9213-82156a002b28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301522380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.301522380
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3996505500
Short name T291
Test name
Test status
Simulation time 25959409161 ps
CPU time 28.54 seconds
Started Jul 01 10:51:00 AM PDT 24
Finished Jul 01 10:51:30 AM PDT 24
Peak memory 217444 kb
Host smart-c2967d20-df3e-439f-8ab6-48e56a8b2fb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996505500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3996505500
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2261879623
Short name T250
Test name
Test status
Simulation time 21732814693 ps
CPU time 267.27 seconds
Started Jul 01 10:50:36 AM PDT 24
Finished Jul 01 10:55:04 AM PDT 24
Peak memory 239064 kb
Host smart-ca2ea4dc-2d36-4732-9d82-eda6fa776b64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261879623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2261879623
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1973875053
Short name T71
Test name
Test status
Simulation time 14101184965 ps
CPU time 30.35 seconds
Started Jul 01 10:50:35 AM PDT 24
Finished Jul 01 10:51:07 AM PDT 24
Peak memory 219372 kb
Host smart-acfa7785-1e9b-48c8-be26-80a86783745a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1973875053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1973875053
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.998011802
Short name T258
Test name
Test status
Simulation time 4949249081 ps
CPU time 20.01 seconds
Started Jul 01 10:51:00 AM PDT 24
Finished Jul 01 10:51:22 AM PDT 24
Peak memory 217208 kb
Host smart-94aead4a-d32d-4dc5-93ce-f58ff9ac5a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998011802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.998011802
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2754476803
Short name T263
Test name
Test status
Simulation time 38520906221 ps
CPU time 122.44 seconds
Started Jul 01 10:50:55 AM PDT 24
Finished Jul 01 10:52:58 AM PDT 24
Peak memory 220564 kb
Host smart-f616cc39-78cd-4d88-9c71-d80d3b4d718a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754476803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2754476803
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1156756755
Short name T225
Test name
Test status
Simulation time 332313283 ps
CPU time 8.53 seconds
Started Jul 01 10:51:00 AM PDT 24
Finished Jul 01 10:51:10 AM PDT 24
Peak memory 217076 kb
Host smart-e123eecf-eab9-48eb-8dda-ae1273dbfbb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156756755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1156756755
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1443001932
Short name T330
Test name
Test status
Simulation time 78955318134 ps
CPU time 689.23 seconds
Started Jul 01 10:50:54 AM PDT 24
Finished Jul 01 11:02:23 AM PDT 24
Peak memory 219556 kb
Host smart-23ad80e2-457b-45c7-9f1e-6a8dfc534368
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443001932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1443001932
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.988604610
Short name T52
Test name
Test status
Simulation time 1940763270 ps
CPU time 19.73 seconds
Started Jul 01 10:50:40 AM PDT 24
Finished Jul 01 10:51:01 AM PDT 24
Peak memory 219308 kb
Host smart-b0f50fd8-62f0-4909-9a74-fb9370be9cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988604610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.988604610
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.922670267
Short name T279
Test name
Test status
Simulation time 3597548434 ps
CPU time 28.5 seconds
Started Jul 01 10:50:56 AM PDT 24
Finished Jul 01 10:51:25 AM PDT 24
Peak memory 211488 kb
Host smart-3fa2ae21-6f6e-44c5-98e2-679f2eaf103c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=922670267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.922670267
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1877947426
Short name T222
Test name
Test status
Simulation time 8571874448 ps
CPU time 70 seconds
Started Jul 01 10:50:35 AM PDT 24
Finished Jul 01 10:51:46 AM PDT 24
Peak memory 216852 kb
Host smart-76b9fcac-cc67-42a8-8ae9-fa24ea3a6858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877947426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1877947426
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2782536152
Short name T181
Test name
Test status
Simulation time 22064792693 ps
CPU time 61.25 seconds
Started Jul 01 10:50:41 AM PDT 24
Finished Jul 01 10:51:43 AM PDT 24
Peak memory 219380 kb
Host smart-4b31b048-dd5f-431b-9eaf-61d15e9f9b26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782536152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2782536152
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2381025991
Short name T209
Test name
Test status
Simulation time 8358978694 ps
CPU time 30.14 seconds
Started Jul 01 10:50:41 AM PDT 24
Finished Jul 01 10:51:12 AM PDT 24
Peak memory 217560 kb
Host smart-cb5fb9c1-73f6-428a-b48b-d96488be6387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381025991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2381025991
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1543790386
Short name T285
Test name
Test status
Simulation time 243127586800 ps
CPU time 659.18 seconds
Started Jul 01 10:50:47 AM PDT 24
Finished Jul 01 11:01:47 AM PDT 24
Peak memory 233876 kb
Host smart-d4d286b1-fef2-41f9-8203-417e6e029ad1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543790386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1543790386
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.784490838
Short name T355
Test name
Test status
Simulation time 27552123639 ps
CPU time 54.32 seconds
Started Jul 01 10:50:40 AM PDT 24
Finished Jul 01 10:51:35 AM PDT 24
Peak memory 219384 kb
Host smart-e7c983db-299b-412b-a475-c4eb0d24ca9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784490838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.784490838
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.647868278
Short name T321
Test name
Test status
Simulation time 3957395539 ps
CPU time 32.33 seconds
Started Jul 01 10:50:40 AM PDT 24
Finished Jul 01 10:51:13 AM PDT 24
Peak memory 219372 kb
Host smart-1b9b66ac-e69c-4566-866a-b78461534e7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=647868278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.647868278
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3660039177
Short name T16
Test name
Test status
Simulation time 879769465 ps
CPU time 25.96 seconds
Started Jul 01 10:50:57 AM PDT 24
Finished Jul 01 10:51:25 AM PDT 24
Peak memory 216984 kb
Host smart-c3dfca69-7f76-4352-a237-dad76f1fcd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660039177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3660039177
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2310885949
Short name T163
Test name
Test status
Simulation time 5724523527 ps
CPU time 45.53 seconds
Started Jul 01 10:50:38 AM PDT 24
Finished Jul 01 10:51:24 AM PDT 24
Peak memory 219380 kb
Host smart-970c3513-c44e-4b71-bc1b-272e2c7c8b08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310885949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2310885949
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.312383325
Short name T345
Test name
Test status
Simulation time 3195210493 ps
CPU time 27.88 seconds
Started Jul 01 10:50:57 AM PDT 24
Finished Jul 01 10:51:27 AM PDT 24
Peak memory 217264 kb
Host smart-d3ded8dd-c994-480b-9a0d-ce59d751be2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312383325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.312383325
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3960665803
Short name T195
Test name
Test status
Simulation time 153148301855 ps
CPU time 389.49 seconds
Started Jul 01 10:50:55 AM PDT 24
Finished Jul 01 10:57:25 AM PDT 24
Peak memory 215024 kb
Host smart-052c5aa1-a115-4630-97a0-084a5579aba1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960665803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3960665803
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.891117623
Short name T277
Test name
Test status
Simulation time 8570610635 ps
CPU time 31.59 seconds
Started Jul 01 10:50:57 AM PDT 24
Finished Jul 01 10:51:30 AM PDT 24
Peak memory 219376 kb
Host smart-ecdf440e-fba9-427d-aea7-2d529a46b5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891117623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.891117623
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3911956636
Short name T333
Test name
Test status
Simulation time 7255841364 ps
CPU time 20.89 seconds
Started Jul 01 10:50:56 AM PDT 24
Finished Jul 01 10:51:18 AM PDT 24
Peak memory 219352 kb
Host smart-1a92917e-2d75-4766-8758-957c98397865
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3911956636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3911956636
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2341409965
Short name T354
Test name
Test status
Simulation time 4764385791 ps
CPU time 48.63 seconds
Started Jul 01 10:50:57 AM PDT 24
Finished Jul 01 10:51:47 AM PDT 24
Peak memory 216776 kb
Host smart-a3197b75-2aea-4bf4-a112-15be4766294a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341409965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2341409965
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1565037544
Short name T337
Test name
Test status
Simulation time 6254335323 ps
CPU time 79.53 seconds
Started Jul 01 10:50:56 AM PDT 24
Finished Jul 01 10:52:16 AM PDT 24
Peak memory 219388 kb
Host smart-8c056d90-881a-48f8-96f9-f7a17e2837c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565037544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1565037544
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1219996054
Short name T274
Test name
Test status
Simulation time 135021187331 ps
CPU time 420.03 seconds
Started Jul 01 10:50:41 AM PDT 24
Finished Jul 01 10:57:42 AM PDT 24
Peak memory 216888 kb
Host smart-774fc1c4-2cf2-4ea1-a971-6c2baa2236ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219996054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1219996054
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.839442341
Short name T197
Test name
Test status
Simulation time 8504382804 ps
CPU time 44.54 seconds
Started Jul 01 10:50:58 AM PDT 24
Finished Jul 01 10:51:45 AM PDT 24
Peak memory 219308 kb
Host smart-aac4dd16-c161-4775-aa1c-25b75e8a64c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839442341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.839442341
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.982752231
Short name T193
Test name
Test status
Simulation time 13287506069 ps
CPU time 30.75 seconds
Started Jul 01 10:50:41 AM PDT 24
Finished Jul 01 10:51:13 AM PDT 24
Peak memory 219360 kb
Host smart-693dbd7a-2e95-44ae-ac76-7de59ba849d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=982752231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.982752231
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2908973565
Short name T68
Test name
Test status
Simulation time 8571954610 ps
CPU time 50.88 seconds
Started Jul 01 10:50:44 AM PDT 24
Finished Jul 01 10:51:36 AM PDT 24
Peak memory 216676 kb
Host smart-8179bdc6-ad83-41e3-a106-2b406668103e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908973565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2908973565
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1514521067
Short name T184
Test name
Test status
Simulation time 6322299139 ps
CPU time 26 seconds
Started Jul 01 10:50:53 AM PDT 24
Finished Jul 01 10:51:20 AM PDT 24
Peak memory 217600 kb
Host smart-47fa3064-6913-42de-92cd-d483d31daa57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514521067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1514521067
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3379582570
Short name T55
Test name
Test status
Simulation time 35238082510 ps
CPU time 349.3 seconds
Started Jul 01 10:50:58 AM PDT 24
Finished Jul 01 10:56:49 AM PDT 24
Peak memory 216832 kb
Host smart-f217b5e9-d657-445b-814a-dff7aac4445b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379582570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3379582570
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1662999851
Short name T148
Test name
Test status
Simulation time 28870287225 ps
CPU time 50.29 seconds
Started Jul 01 10:50:53 AM PDT 24
Finished Jul 01 10:51:44 AM PDT 24
Peak memory 219360 kb
Host smart-0e47a8a3-42cb-49bd-a51a-5617f92c65ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662999851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1662999851
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2623824711
Short name T324
Test name
Test status
Simulation time 4489985396 ps
CPU time 17.84 seconds
Started Jul 01 10:50:54 AM PDT 24
Finished Jul 01 10:51:12 AM PDT 24
Peak memory 219380 kb
Host smart-70f307d1-95ca-4c53-8e99-1cc7ba7dc44a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2623824711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2623824711
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2138003566
Short name T322
Test name
Test status
Simulation time 3630319674 ps
CPU time 40.39 seconds
Started Jul 01 10:50:58 AM PDT 24
Finished Jul 01 10:51:40 AM PDT 24
Peak memory 216596 kb
Host smart-7cc19fed-f0f3-4195-8009-5057c025fc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138003566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2138003566
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2593021239
Short name T203
Test name
Test status
Simulation time 13134217211 ps
CPU time 129.88 seconds
Started Jul 01 10:50:43 AM PDT 24
Finished Jul 01 10:52:53 AM PDT 24
Peak memory 221180 kb
Host smart-f53a2439-bbeb-4700-a7a2-e8a656100bba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593021239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2593021239
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1007445831
Short name T308
Test name
Test status
Simulation time 8255211076 ps
CPU time 21.32 seconds
Started Jul 01 10:50:12 AM PDT 24
Finished Jul 01 10:50:37 AM PDT 24
Peak memory 217480 kb
Host smart-e236b071-9a35-4df2-9b1e-14c477bcba1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007445831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1007445831
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1265574747
Short name T305
Test name
Test status
Simulation time 32146108117 ps
CPU time 376.63 seconds
Started Jul 01 10:50:13 AM PDT 24
Finished Jul 01 10:56:32 AM PDT 24
Peak memory 231744 kb
Host smart-2299e32a-f4c0-4ee9-a958-f8d42cc325fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265574747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1265574747
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1931364476
Short name T140
Test name
Test status
Simulation time 11635383415 ps
CPU time 36.15 seconds
Started Jul 01 10:50:07 AM PDT 24
Finished Jul 01 10:50:45 AM PDT 24
Peak memory 219340 kb
Host smart-ecdfed05-f6c8-41b2-9f90-1773cbf90c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931364476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1931364476
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2722637639
Short name T334
Test name
Test status
Simulation time 12698977691 ps
CPU time 28.42 seconds
Started Jul 01 10:50:03 AM PDT 24
Finished Jul 01 10:50:32 AM PDT 24
Peak memory 211620 kb
Host smart-ee803fbd-bd79-4373-b483-45c00e65a6f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2722637639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2722637639
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.35473099
Short name T29
Test name
Test status
Simulation time 42396454834 ps
CPU time 143.56 seconds
Started Jul 01 10:50:10 AM PDT 24
Finished Jul 01 10:52:37 AM PDT 24
Peak memory 238356 kb
Host smart-a703a341-6e2d-4684-93d6-7ebf4af62fc9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35473099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.35473099
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.146536927
Short name T198
Test name
Test status
Simulation time 4047241617 ps
CPU time 34.75 seconds
Started Jul 01 10:50:00 AM PDT 24
Finished Jul 01 10:50:36 AM PDT 24
Peak memory 216420 kb
Host smart-efcd53a9-2961-4c69-aee1-f04b97d8352c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146536927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.146536927
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.4233430319
Short name T91
Test name
Test status
Simulation time 1455684599 ps
CPU time 32.26 seconds
Started Jul 01 10:50:09 AM PDT 24
Finished Jul 01 10:50:44 AM PDT 24
Peak memory 215536 kb
Host smart-f4ab8d6b-d9a1-4cfa-a9a6-08b5d311f44a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233430319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.4233430319
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2561435083
Short name T61
Test name
Test status
Simulation time 35754768649 ps
CPU time 1358.46 seconds
Started Jul 01 10:50:21 AM PDT 24
Finished Jul 01 11:13:00 AM PDT 24
Peak memory 232516 kb
Host smart-c3cd3cc9-7f51-4f3b-a4e1-caf4b9679e2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561435083 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.2561435083
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3342345136
Short name T192
Test name
Test status
Simulation time 7042084592 ps
CPU time 28.72 seconds
Started Jul 01 10:50:54 AM PDT 24
Finished Jul 01 10:51:23 AM PDT 24
Peak memory 217548 kb
Host smart-df9f27f1-6f6c-422a-b857-38d7acad4a0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342345136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3342345136
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1300253946
Short name T219
Test name
Test status
Simulation time 236075428664 ps
CPU time 409.84 seconds
Started Jul 01 10:50:41 AM PDT 24
Finished Jul 01 10:57:32 AM PDT 24
Peak memory 239504 kb
Host smart-4fec3727-ee8e-4dc2-abe8-1c92be2059b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300253946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1300253946
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1120122171
Short name T180
Test name
Test status
Simulation time 10436698938 ps
CPU time 35.02 seconds
Started Jul 01 10:50:43 AM PDT 24
Finished Jul 01 10:51:18 AM PDT 24
Peak memory 219252 kb
Host smart-6dbee6a5-33f1-447a-a3d5-aed56cd9fd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120122171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1120122171
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.573579656
Short name T290
Test name
Test status
Simulation time 13202788150 ps
CPU time 29.63 seconds
Started Jul 01 10:50:45 AM PDT 24
Finished Jul 01 10:51:16 AM PDT 24
Peak memory 212044 kb
Host smart-2b18405f-c6f5-4e8e-9e14-ab663beafa84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=573579656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.573579656
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3755597161
Short name T170
Test name
Test status
Simulation time 4193780116 ps
CPU time 47.99 seconds
Started Jul 01 10:50:59 AM PDT 24
Finished Jul 01 10:51:49 AM PDT 24
Peak memory 216624 kb
Host smart-ff2b8739-ff54-4d52-b37a-220d688d5c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755597161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3755597161
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3826329836
Short name T241
Test name
Test status
Simulation time 21596965910 ps
CPU time 125.22 seconds
Started Jul 01 10:50:58 AM PDT 24
Finished Jul 01 10:53:05 AM PDT 24
Peak memory 227816 kb
Host smart-496a85db-86b9-447d-8c89-b4852fb6f440
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826329836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3826329836
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.230434862
Short name T245
Test name
Test status
Simulation time 1854797781 ps
CPU time 12.21 seconds
Started Jul 01 10:50:59 AM PDT 24
Finished Jul 01 10:51:13 AM PDT 24
Peak memory 217100 kb
Host smart-ca2af31d-6bd5-4523-ae4e-aace6b667c33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230434862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.230434862
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3367282014
Short name T205
Test name
Test status
Simulation time 36302378443 ps
CPU time 430.29 seconds
Started Jul 01 10:50:45 AM PDT 24
Finished Jul 01 10:57:56 AM PDT 24
Peak memory 239112 kb
Host smart-b81eeffa-86ff-4c10-8e4a-61223b417e9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367282014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3367282014
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1815135967
Short name T182
Test name
Test status
Simulation time 14023220878 ps
CPU time 57.49 seconds
Started Jul 01 10:51:01 AM PDT 24
Finished Jul 01 10:52:00 AM PDT 24
Peak memory 219336 kb
Host smart-60d7fd9d-2a68-420e-8a14-cd914b95e922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815135967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1815135967
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.342177246
Short name T249
Test name
Test status
Simulation time 2551107542 ps
CPU time 24.61 seconds
Started Jul 01 10:50:58 AM PDT 24
Finished Jul 01 10:51:25 AM PDT 24
Peak memory 211308 kb
Host smart-db545360-87e3-4783-a2a6-a4fe25cd3850
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=342177246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.342177246
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.623400132
Short name T123
Test name
Test status
Simulation time 1432361797 ps
CPU time 20.42 seconds
Started Jul 01 10:50:41 AM PDT 24
Finished Jul 01 10:51:02 AM PDT 24
Peak memory 216656 kb
Host smart-bc9ed30b-c1c0-4da1-a637-d2f766f4b2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623400132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.623400132
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1697980729
Short name T327
Test name
Test status
Simulation time 740119954 ps
CPU time 39.27 seconds
Started Jul 01 10:50:47 AM PDT 24
Finished Jul 01 10:51:26 AM PDT 24
Peak memory 219332 kb
Host smart-8f38642b-c2c4-4404-80e9-4ed031a25b0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697980729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1697980729
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.621227616
Short name T9
Test name
Test status
Simulation time 3728794496 ps
CPU time 26.4 seconds
Started Jul 01 10:50:50 AM PDT 24
Finished Jul 01 10:51:17 AM PDT 24
Peak memory 217152 kb
Host smart-88dc1668-acf4-4666-8a44-5093220f11a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621227616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.621227616
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3345451788
Short name T319
Test name
Test status
Simulation time 6769247292 ps
CPU time 272.14 seconds
Started Jul 01 10:50:45 AM PDT 24
Finished Jul 01 10:55:18 AM PDT 24
Peak memory 234348 kb
Host smart-78a82a10-df42-492d-a984-58c8ad0e673b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345451788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3345451788
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2731403449
Short name T146
Test name
Test status
Simulation time 7861219941 ps
CPU time 65 seconds
Started Jul 01 10:50:46 AM PDT 24
Finished Jul 01 10:51:51 AM PDT 24
Peak memory 219356 kb
Host smart-c1115602-ae2a-438c-9544-4575a624172c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731403449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2731403449
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1897144291
Short name T348
Test name
Test status
Simulation time 3848056205 ps
CPU time 30.88 seconds
Started Jul 01 10:50:59 AM PDT 24
Finished Jul 01 10:51:32 AM PDT 24
Peak memory 219388 kb
Host smart-6c6dd706-9bc1-4e84-95f7-0db4da84d407
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1897144291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1897144291
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1525650407
Short name T165
Test name
Test status
Simulation time 15078225428 ps
CPU time 152.63 seconds
Started Jul 01 10:50:56 AM PDT 24
Finished Jul 01 10:53:29 AM PDT 24
Peak memory 219416 kb
Host smart-3a859b5e-e48d-427e-b0f2-4e698009a304
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525650407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1525650407
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.829850917
Short name T207
Test name
Test status
Simulation time 688050455 ps
CPU time 8.21 seconds
Started Jul 01 10:50:44 AM PDT 24
Finished Jul 01 10:50:53 AM PDT 24
Peak memory 217020 kb
Host smart-9d00acbb-0c31-4048-984f-d968cefad95e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829850917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.829850917
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2216914028
Short name T69
Test name
Test status
Simulation time 17102424156 ps
CPU time 289.68 seconds
Started Jul 01 10:50:46 AM PDT 24
Finished Jul 01 10:55:37 AM PDT 24
Peak memory 219580 kb
Host smart-5480d226-5fce-4c5b-a96b-2aa3d5b48779
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216914028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2216914028
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1347277341
Short name T317
Test name
Test status
Simulation time 704495638 ps
CPU time 18.49 seconds
Started Jul 01 10:50:58 AM PDT 24
Finished Jul 01 10:51:19 AM PDT 24
Peak memory 219312 kb
Host smart-a885cfcc-5829-4439-8d30-9cd3b97c3bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347277341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1347277341
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1037497577
Short name T352
Test name
Test status
Simulation time 728419294 ps
CPU time 10.39 seconds
Started Jul 01 10:50:59 AM PDT 24
Finished Jul 01 10:51:11 AM PDT 24
Peak memory 219300 kb
Host smart-5d0cd365-dec3-4690-a552-c0ab5e228ff1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1037497577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1037497577
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3799860224
Short name T339
Test name
Test status
Simulation time 26013589392 ps
CPU time 62.31 seconds
Started Jul 01 10:50:50 AM PDT 24
Finished Jul 01 10:51:53 AM PDT 24
Peak memory 216940 kb
Host smart-94d0eaa7-65ea-4e48-a4e6-053bf399ac32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799860224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3799860224
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.2656217902
Short name T64
Test name
Test status
Simulation time 52554971556 ps
CPU time 4504.7 seconds
Started Jul 01 10:50:57 AM PDT 24
Finished Jul 01 12:06:04 PM PDT 24
Peak memory 244044 kb
Host smart-41634514-4863-4306-bd70-13d7d0576bb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656217902 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.2656217902
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.573946222
Short name T347
Test name
Test status
Simulation time 8186212661 ps
CPU time 20.41 seconds
Started Jul 01 10:50:56 AM PDT 24
Finished Jul 01 10:51:17 AM PDT 24
Peak memory 217468 kb
Host smart-cd75e949-5da5-4fca-9c33-decf977b9ef4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573946222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.573946222
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.385531874
Short name T286
Test name
Test status
Simulation time 350987858335 ps
CPU time 923.25 seconds
Started Jul 01 10:51:01 AM PDT 24
Finished Jul 01 11:06:26 AM PDT 24
Peak memory 239172 kb
Host smart-76a2ba27-ed22-4e5d-af90-ebbbd4d194b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385531874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.385531874
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2968078062
Short name T293
Test name
Test status
Simulation time 2742956487 ps
CPU time 36.09 seconds
Started Jul 01 10:50:50 AM PDT 24
Finished Jul 01 10:51:27 AM PDT 24
Peak memory 219316 kb
Host smart-6db3cc58-7cf9-49b9-922c-5f6ef08e1036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968078062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2968078062
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3920794050
Short name T157
Test name
Test status
Simulation time 4986280617 ps
CPU time 19.41 seconds
Started Jul 01 10:50:48 AM PDT 24
Finished Jul 01 10:51:08 AM PDT 24
Peak memory 211700 kb
Host smart-efb52fe8-2135-4100-a731-639673a60bc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3920794050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3920794050
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2292118117
Short name T30
Test name
Test status
Simulation time 5164959842 ps
CPU time 50.65 seconds
Started Jul 01 10:50:47 AM PDT 24
Finished Jul 01 10:51:38 AM PDT 24
Peak memory 216888 kb
Host smart-68931d7c-2ea5-4a53-9e2a-95a4bbbd6d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292118117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2292118117
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.3089001379
Short name T14
Test name
Test status
Simulation time 40057279182 ps
CPU time 1893.5 seconds
Started Jul 01 10:50:49 AM PDT 24
Finished Jul 01 11:22:23 AM PDT 24
Peak memory 235804 kb
Host smart-99a6b149-b0f9-42ca-a091-be951cf6214f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089001379 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.3089001379
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3589724099
Short name T126
Test name
Test status
Simulation time 6139545710 ps
CPU time 16.53 seconds
Started Jul 01 10:51:05 AM PDT 24
Finished Jul 01 10:51:22 AM PDT 24
Peak memory 213264 kb
Host smart-34381c02-c12f-4391-b95c-558a1467dfd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589724099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3589724099
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3558148401
Short name T298
Test name
Test status
Simulation time 53513097015 ps
CPU time 608.3 seconds
Started Jul 01 10:51:01 AM PDT 24
Finished Jul 01 11:01:11 AM PDT 24
Peak memory 219208 kb
Host smart-870b3c43-e778-4b1c-b55d-ec098c204467
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558148401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3558148401
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2753986752
Short name T57
Test name
Test status
Simulation time 25335837182 ps
CPU time 50.77 seconds
Started Jul 01 10:50:58 AM PDT 24
Finished Jul 01 10:51:51 AM PDT 24
Peak memory 219248 kb
Host smart-236aadf9-9da7-4588-a9bc-ecc326108e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753986752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2753986752
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3510735894
Short name T133
Test name
Test status
Simulation time 1085983977 ps
CPU time 10.76 seconds
Started Jul 01 10:50:49 AM PDT 24
Finished Jul 01 10:51:00 AM PDT 24
Peak memory 219288 kb
Host smart-ffe47254-75f9-4d4b-87e9-ebbf185b5851
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3510735894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3510735894
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1587440761
Short name T221
Test name
Test status
Simulation time 363378529 ps
CPU time 20.48 seconds
Started Jul 01 10:50:58 AM PDT 24
Finished Jul 01 10:51:20 AM PDT 24
Peak memory 216544 kb
Host smart-52d3b195-eb20-4dfb-b277-6d76213a66e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587440761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1587440761
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1392905016
Short name T288
Test name
Test status
Simulation time 9066133261 ps
CPU time 75.14 seconds
Started Jul 01 10:50:56 AM PDT 24
Finished Jul 01 10:52:13 AM PDT 24
Peak memory 220304 kb
Host smart-951180ed-3a5f-47cc-acb9-43ac1c033f9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392905016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1392905016
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.3726073693
Short name T62
Test name
Test status
Simulation time 30963279766 ps
CPU time 1142.04 seconds
Started Jul 01 10:50:57 AM PDT 24
Finished Jul 01 11:10:01 AM PDT 24
Peak memory 232488 kb
Host smart-8e31c770-cb33-446a-bc4d-a2f45f7a97db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726073693 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.3726073693
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3738358215
Short name T153
Test name
Test status
Simulation time 339080886 ps
CPU time 8.03 seconds
Started Jul 01 10:50:57 AM PDT 24
Finished Jul 01 10:51:07 AM PDT 24
Peak memory 213156 kb
Host smart-faf98f20-a6b5-47e9-ab27-5462f73def34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738358215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3738358215
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2982434832
Short name T315
Test name
Test status
Simulation time 349994640 ps
CPU time 19.01 seconds
Started Jul 01 10:50:59 AM PDT 24
Finished Jul 01 10:51:20 AM PDT 24
Peak memory 219316 kb
Host smart-bf42162a-3e68-4303-9b90-8ed072321d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982434832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2982434832
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3010752495
Short name T213
Test name
Test status
Simulation time 5520542240 ps
CPU time 26.27 seconds
Started Jul 01 10:51:01 AM PDT 24
Finished Jul 01 10:51:28 AM PDT 24
Peak memory 219604 kb
Host smart-c9c7b0c3-c8ed-489b-93cb-659aa8464ed7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3010752495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3010752495
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1044095914
Short name T257
Test name
Test status
Simulation time 4717831042 ps
CPU time 34.3 seconds
Started Jul 01 10:50:57 AM PDT 24
Finished Jul 01 10:51:32 AM PDT 24
Peak memory 216632 kb
Host smart-a8ad511d-493b-4758-a3ee-dab4d4cd5e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044095914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1044095914
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1073228422
Short name T92
Test name
Test status
Simulation time 714773488 ps
CPU time 37.34 seconds
Started Jul 01 10:50:58 AM PDT 24
Finished Jul 01 10:51:37 AM PDT 24
Peak memory 219352 kb
Host smart-969a8972-8a85-492b-a927-41cc252b03d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073228422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1073228422
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1031384953
Short name T292
Test name
Test status
Simulation time 2774206626 ps
CPU time 25.02 seconds
Started Jul 01 10:51:09 AM PDT 24
Finished Jul 01 10:51:36 AM PDT 24
Peak memory 217204 kb
Host smart-60d5378a-0f54-42d9-a317-6a3ba5fd8616
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031384953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1031384953
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3319520800
Short name T125
Test name
Test status
Simulation time 12485844546 ps
CPU time 314.72 seconds
Started Jul 01 10:51:01 AM PDT 24
Finished Jul 01 10:56:17 AM PDT 24
Peak memory 243168 kb
Host smart-c0e3c04f-0daf-4591-a802-c3cca5463ad9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319520800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3319520800
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2304439304
Short name T268
Test name
Test status
Simulation time 14353134639 ps
CPU time 61.11 seconds
Started Jul 01 10:51:01 AM PDT 24
Finished Jul 01 10:52:03 AM PDT 24
Peak memory 219212 kb
Host smart-55514813-92a1-41c3-8c17-dc0b3085e202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304439304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2304439304
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3876094083
Short name T304
Test name
Test status
Simulation time 3757163006 ps
CPU time 17.3 seconds
Started Jul 01 10:50:57 AM PDT 24
Finished Jul 01 10:51:16 AM PDT 24
Peak memory 211204 kb
Host smart-9bcd5b39-6f8a-413f-a351-f1fce09aec9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3876094083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3876094083
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1552437101
Short name T253
Test name
Test status
Simulation time 3737383002 ps
CPU time 45.26 seconds
Started Jul 01 10:50:58 AM PDT 24
Finished Jul 01 10:51:45 AM PDT 24
Peak memory 216632 kb
Host smart-c73ce6f8-9d00-40c4-8bdb-4ff09efe974e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552437101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1552437101
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1323197789
Short name T346
Test name
Test status
Simulation time 39655495288 ps
CPU time 97.14 seconds
Started Jul 01 10:51:00 AM PDT 24
Finished Jul 01 10:52:39 AM PDT 24
Peak memory 219388 kb
Host smart-c6261f48-974a-40bf-a170-ec9525028e7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323197789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1323197789
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.83823922
Short name T297
Test name
Test status
Simulation time 662141675 ps
CPU time 8.12 seconds
Started Jul 01 10:51:00 AM PDT 24
Finished Jul 01 10:51:09 AM PDT 24
Peak memory 217100 kb
Host smart-68c9ebb9-1379-4ff5-8fed-8c53c537b6de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83823922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.83823922
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2093663446
Short name T191
Test name
Test status
Simulation time 240517497787 ps
CPU time 428.76 seconds
Started Jul 01 10:51:00 AM PDT 24
Finished Jul 01 10:58:10 AM PDT 24
Peak memory 225592 kb
Host smart-c85adb2e-af69-432f-baac-209457eda05a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093663446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2093663446
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.65575034
Short name T66
Test name
Test status
Simulation time 10711167001 ps
CPU time 50.38 seconds
Started Jul 01 10:51:05 AM PDT 24
Finished Jul 01 10:51:56 AM PDT 24
Peak memory 219412 kb
Host smart-bb08ede4-a8f6-49c8-b1f5-617fce493d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65575034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.65575034
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2573126960
Short name T338
Test name
Test status
Simulation time 12730054323 ps
CPU time 27.62 seconds
Started Jul 01 10:50:56 AM PDT 24
Finished Jul 01 10:51:25 AM PDT 24
Peak memory 211632 kb
Host smart-49741fa5-8415-4fe1-bf8d-3be646ffc86e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2573126960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2573126960
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3850463706
Short name T269
Test name
Test status
Simulation time 705400180 ps
CPU time 19.71 seconds
Started Jul 01 10:51:02 AM PDT 24
Finished Jul 01 10:51:23 AM PDT 24
Peak memory 216392 kb
Host smart-34b6f45c-f9b5-480f-bc37-66712cf8eb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850463706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3850463706
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3038372933
Short name T175
Test name
Test status
Simulation time 4870031368 ps
CPU time 40.33 seconds
Started Jul 01 10:50:57 AM PDT 24
Finished Jul 01 10:51:39 AM PDT 24
Peak memory 219368 kb
Host smart-9b64b5cd-1243-4954-af03-84c10c9a3890
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038372933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3038372933
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1702957339
Short name T336
Test name
Test status
Simulation time 30124150465 ps
CPU time 19.83 seconds
Started Jul 01 10:50:57 AM PDT 24
Finished Jul 01 10:51:18 AM PDT 24
Peak memory 217584 kb
Host smart-9f5c171a-2de2-4c16-8a12-67f6aed79d2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702957339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1702957339
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.986009420
Short name T40
Test name
Test status
Simulation time 75406943732 ps
CPU time 770.18 seconds
Started Jul 01 10:51:09 AM PDT 24
Finished Jul 01 11:04:01 AM PDT 24
Peak memory 235332 kb
Host smart-14da5e1b-8536-4290-96fe-0a357c932646
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986009420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.986009420
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2095795941
Short name T353
Test name
Test status
Simulation time 37045286087 ps
CPU time 58.68 seconds
Started Jul 01 10:51:00 AM PDT 24
Finished Jul 01 10:52:00 AM PDT 24
Peak memory 219312 kb
Host smart-f8bfd8e0-31d2-426b-9e1c-29da83e9433e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095795941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2095795941
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1121031692
Short name T323
Test name
Test status
Simulation time 621506018 ps
CPU time 14.22 seconds
Started Jul 01 10:50:59 AM PDT 24
Finished Jul 01 10:51:15 AM PDT 24
Peak memory 219280 kb
Host smart-d76a0a02-bf4d-4f96-a2f2-869038273a53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1121031692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1121031692
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1684778736
Short name T296
Test name
Test status
Simulation time 2672644380 ps
CPU time 23.56 seconds
Started Jul 01 10:51:00 AM PDT 24
Finished Jul 01 10:51:25 AM PDT 24
Peak memory 216956 kb
Host smart-bbaee43a-ce09-4f64-a5cd-b9025093f9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684778736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1684778736
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1620434138
Short name T220
Test name
Test status
Simulation time 18132762686 ps
CPU time 48.11 seconds
Started Jul 01 10:50:59 AM PDT 24
Finished Jul 01 10:51:49 AM PDT 24
Peak memory 216784 kb
Host smart-596b9eac-8b6c-4966-b535-7a2c53287987
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620434138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1620434138
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1880998085
Short name T134
Test name
Test status
Simulation time 2934897761 ps
CPU time 14.06 seconds
Started Jul 01 10:50:04 AM PDT 24
Finished Jul 01 10:50:19 AM PDT 24
Peak memory 217200 kb
Host smart-79145453-07bc-4d9e-890a-4668dc0b398c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880998085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1880998085
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.319832876
Short name T232
Test name
Test status
Simulation time 349696410 ps
CPU time 19.08 seconds
Started Jul 01 10:50:11 AM PDT 24
Finished Jul 01 10:50:34 AM PDT 24
Peak memory 219312 kb
Host smart-8d160f60-06d6-49eb-ac26-53283519ca8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319832876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.319832876
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.625262852
Short name T169
Test name
Test status
Simulation time 6302096259 ps
CPU time 19.83 seconds
Started Jul 01 10:50:12 AM PDT 24
Finished Jul 01 10:50:35 AM PDT 24
Peak memory 219344 kb
Host smart-a7ae0c8e-5911-4d66-8b14-21aafde93803
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=625262852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.625262852
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1514321275
Short name T154
Test name
Test status
Simulation time 14744727645 ps
CPU time 42.3 seconds
Started Jul 01 10:50:13 AM PDT 24
Finished Jul 01 10:50:59 AM PDT 24
Peak memory 216848 kb
Host smart-5c647d62-e004-447d-b704-0a21418fd7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514321275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1514321275
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2864640430
Short name T162
Test name
Test status
Simulation time 11253373210 ps
CPU time 84.12 seconds
Started Jul 01 10:50:09 AM PDT 24
Finished Jul 01 10:51:36 AM PDT 24
Peak memory 220208 kb
Host smart-91e206f1-a535-46d1-96ca-ade551f0c54c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864640430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2864640430
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2973056216
Short name T300
Test name
Test status
Simulation time 17256347730 ps
CPU time 31.9 seconds
Started Jul 01 10:50:12 AM PDT 24
Finished Jul 01 10:50:47 AM PDT 24
Peak memory 217560 kb
Host smart-cd11055c-1f2a-47ba-be5a-9c61462187ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973056216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2973056216
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1514826804
Short name T58
Test name
Test status
Simulation time 186477498315 ps
CPU time 432.82 seconds
Started Jul 01 10:50:17 AM PDT 24
Finished Jul 01 10:57:31 AM PDT 24
Peak memory 236824 kb
Host smart-cf042ef8-0585-4738-9a5d-820854f16a91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514826804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1514826804
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2958096120
Short name T196
Test name
Test status
Simulation time 27255005638 ps
CPU time 59.46 seconds
Started Jul 01 10:50:12 AM PDT 24
Finished Jul 01 10:51:15 AM PDT 24
Peak memory 219400 kb
Host smart-f3b0cf03-4956-4d1c-af4d-7883ed8f9663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958096120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2958096120
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1166578107
Short name T344
Test name
Test status
Simulation time 5933408592 ps
CPU time 23.12 seconds
Started Jul 01 10:50:13 AM PDT 24
Finished Jul 01 10:50:39 AM PDT 24
Peak memory 217612 kb
Host smart-56165b2d-0a72-4c91-a5fb-832379870eb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1166578107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1166578107
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2663508107
Short name T17
Test name
Test status
Simulation time 6959333665 ps
CPU time 66.09 seconds
Started Jul 01 10:50:30 AM PDT 24
Finished Jul 01 10:51:37 AM PDT 24
Peak memory 216600 kb
Host smart-02d91d6f-fa7e-4cd4-bd6e-ee0a98c405e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663508107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2663508107
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1487759325
Short name T3
Test name
Test status
Simulation time 39122937293 ps
CPU time 84.02 seconds
Started Jul 01 10:50:04 AM PDT 24
Finished Jul 01 10:51:29 AM PDT 24
Peak memory 219380 kb
Host smart-7dbcec50-c52f-4a92-8c0a-2d703a2c4981
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487759325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1487759325
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1600892194
Short name T262
Test name
Test status
Simulation time 1118384643 ps
CPU time 15.37 seconds
Started Jul 01 10:50:11 AM PDT 24
Finished Jul 01 10:50:30 AM PDT 24
Peak memory 217060 kb
Host smart-9f3ea61b-84b9-4ef4-a69d-2f597bb16d1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600892194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1600892194
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1683032992
Short name T318
Test name
Test status
Simulation time 17935201347 ps
CPU time 213.13 seconds
Started Jul 01 10:50:12 AM PDT 24
Finished Jul 01 10:53:49 AM PDT 24
Peak memory 233928 kb
Host smart-54f218c7-d520-4500-a98f-215600f5290f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683032992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1683032992
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1573341420
Short name T138
Test name
Test status
Simulation time 15724969691 ps
CPU time 42.87 seconds
Started Jul 01 10:50:12 AM PDT 24
Finished Jul 01 10:50:59 AM PDT 24
Peak memory 217672 kb
Host smart-fb6354e4-5a44-463f-bfaa-f35d92cf7dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573341420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1573341420
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1791142064
Short name T155
Test name
Test status
Simulation time 16513599647 ps
CPU time 32.69 seconds
Started Jul 01 10:50:13 AM PDT 24
Finished Jul 01 10:50:49 AM PDT 24
Peak memory 211768 kb
Host smart-0a6f696b-ad93-459a-a3af-c12136fed70e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1791142064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1791142064
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.409065617
Short name T214
Test name
Test status
Simulation time 25504605854 ps
CPU time 56.27 seconds
Started Jul 01 10:50:13 AM PDT 24
Finished Jul 01 10:51:13 AM PDT 24
Peak memory 217356 kb
Host smart-0ed904e1-0414-4b62-8e10-946b0d497eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409065617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.409065617
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1756895802
Short name T90
Test name
Test status
Simulation time 35996700977 ps
CPU time 93.49 seconds
Started Jul 01 10:50:14 AM PDT 24
Finished Jul 01 10:51:51 AM PDT 24
Peak memory 219312 kb
Host smart-582248d8-b8bc-4437-9b1e-2070a6be8bbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756895802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1756895802
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3411382643
Short name T264
Test name
Test status
Simulation time 3538297565 ps
CPU time 29.41 seconds
Started Jul 01 10:50:11 AM PDT 24
Finished Jul 01 10:50:45 AM PDT 24
Peak memory 217520 kb
Host smart-8e2d1eef-5e94-4a19-b7d9-51b2681ff4c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411382643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3411382643
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.848677682
Short name T350
Test name
Test status
Simulation time 174449332808 ps
CPU time 637.92 seconds
Started Jul 01 10:50:09 AM PDT 24
Finished Jul 01 11:00:50 AM PDT 24
Peak memory 217048 kb
Host smart-b36b298d-61d7-4819-a459-6d8dfe942304
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848677682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.848677682
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.145087387
Short name T312
Test name
Test status
Simulation time 34154844456 ps
CPU time 33.07 seconds
Started Jul 01 10:50:12 AM PDT 24
Finished Jul 01 10:50:48 AM PDT 24
Peak memory 219360 kb
Host smart-c50fafe7-3e08-44be-bf2f-6a5314578521
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=145087387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.145087387
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2893349688
Short name T307
Test name
Test status
Simulation time 2398561135 ps
CPU time 37.3 seconds
Started Jul 01 10:50:19 AM PDT 24
Finished Jul 01 10:50:57 AM PDT 24
Peak memory 216300 kb
Host smart-ddba6baa-3359-451b-a1ca-1dc100336a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893349688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2893349688
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1077728557
Short name T33
Test name
Test status
Simulation time 5280679708 ps
CPU time 68.14 seconds
Started Jul 01 10:50:22 AM PDT 24
Finished Jul 01 10:51:31 AM PDT 24
Peak memory 220084 kb
Host smart-51f21926-41c0-478d-b6da-7ba9f5483a53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077728557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1077728557
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1931782098
Short name T201
Test name
Test status
Simulation time 689179866 ps
CPU time 8.33 seconds
Started Jul 01 10:50:16 AM PDT 24
Finished Jul 01 10:50:27 AM PDT 24
Peak memory 217092 kb
Host smart-5a077206-f4e9-4072-acbd-a862078a181f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931782098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1931782098
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.4122408152
Short name T242
Test name
Test status
Simulation time 237191926861 ps
CPU time 360.57 seconds
Started Jul 01 10:50:16 AM PDT 24
Finished Jul 01 10:56:19 AM PDT 24
Peak memory 228200 kb
Host smart-4881e6de-d6e4-42ef-9290-712fd8fe38d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122408152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.4122408152
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.38310441
Short name T272
Test name
Test status
Simulation time 1374656246 ps
CPU time 18.75 seconds
Started Jul 01 10:50:14 AM PDT 24
Finished Jul 01 10:50:36 AM PDT 24
Peak memory 219192 kb
Host smart-efe1c5de-9b98-4c3c-b290-1b930c379c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38310441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.38310441
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.4171448278
Short name T328
Test name
Test status
Simulation time 351534940 ps
CPU time 10.3 seconds
Started Jul 01 10:50:17 AM PDT 24
Finished Jul 01 10:50:29 AM PDT 24
Peak memory 219300 kb
Host smart-1be2ead3-966e-4561-8219-777c8a702314
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4171448278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.4171448278
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1894313170
Short name T149
Test name
Test status
Simulation time 6868374433 ps
CPU time 20.66 seconds
Started Jul 01 10:50:09 AM PDT 24
Finished Jul 01 10:50:33 AM PDT 24
Peak memory 217800 kb
Host smart-a7aa9a6a-2551-4fee-97b8-c06b2bbf870f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894313170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1894313170
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1924466378
Short name T54
Test name
Test status
Simulation time 19855758507 ps
CPU time 61.35 seconds
Started Jul 01 10:50:11 AM PDT 24
Finished Jul 01 10:51:15 AM PDT 24
Peak memory 219260 kb
Host smart-33ad5a54-d420-4aea-98a3-7863da338f61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924466378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1924466378
Directory /workspace/9.rom_ctrl_stress_all/latest
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