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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.21 96.89 91.99 97.68 100.00 98.28 97.30 98.37


Total test records in report: 454
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T302 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1872257293 Jul 01 04:29:28 PM PDT 24 Jul 01 04:30:02 PM PDT 24 3505112998 ps
T303 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2706331811 Jul 01 04:29:32 PM PDT 24 Jul 01 04:37:55 PM PDT 24 97081635088 ps
T304 /workspace/coverage/default/42.rom_ctrl_smoke.1507424659 Jul 01 04:29:49 PM PDT 24 Jul 01 04:31:00 PM PDT 24 6079404590 ps
T29 /workspace/coverage/default/1.rom_ctrl_sec_cm.1405294119 Jul 01 04:29:07 PM PDT 24 Jul 01 04:33:29 PM PDT 24 16420214266 ps
T305 /workspace/coverage/default/34.rom_ctrl_stress_all.1552912105 Jul 01 04:29:47 PM PDT 24 Jul 01 04:33:43 PM PDT 24 83839752622 ps
T306 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1903470659 Jul 01 04:29:45 PM PDT 24 Jul 01 04:51:28 PM PDT 24 249230377898 ps
T307 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.938303189 Jul 01 04:29:37 PM PDT 24 Jul 01 04:30:13 PM PDT 24 22746214623 ps
T308 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1684539122 Jul 01 04:29:47 PM PDT 24 Jul 01 04:31:01 PM PDT 24 7355933000 ps
T309 /workspace/coverage/default/42.rom_ctrl_alert_test.231670032 Jul 01 04:29:44 PM PDT 24 Jul 01 04:30:15 PM PDT 24 1909057616 ps
T310 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3214541001 Jul 01 04:29:44 PM PDT 24 Jul 01 04:30:15 PM PDT 24 332499286 ps
T311 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.814494193 Jul 01 04:29:40 PM PDT 24 Jul 01 04:30:08 PM PDT 24 1508391843 ps
T312 /workspace/coverage/default/5.rom_ctrl_alert_test.465204112 Jul 01 04:29:14 PM PDT 24 Jul 01 04:29:42 PM PDT 24 2588842402 ps
T313 /workspace/coverage/default/44.rom_ctrl_smoke.3378437788 Jul 01 04:29:54 PM PDT 24 Jul 01 04:31:13 PM PDT 24 7258458543 ps
T314 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.4041223950 Jul 01 04:29:22 PM PDT 24 Jul 01 04:30:10 PM PDT 24 14877012376 ps
T315 /workspace/coverage/default/13.rom_ctrl_alert_test.998102898 Jul 01 04:29:22 PM PDT 24 Jul 01 04:30:03 PM PDT 24 81458992744 ps
T316 /workspace/coverage/default/36.rom_ctrl_alert_test.1965907869 Jul 01 04:30:16 PM PDT 24 Jul 01 04:30:55 PM PDT 24 8244323205 ps
T317 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3450866186 Jul 01 04:29:31 PM PDT 24 Jul 01 04:33:40 PM PDT 24 3774170042 ps
T318 /workspace/coverage/default/49.rom_ctrl_alert_test.853338255 Jul 01 04:29:49 PM PDT 24 Jul 01 04:30:23 PM PDT 24 10675047177 ps
T319 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2063393324 Jul 01 04:29:57 PM PDT 24 Jul 01 04:37:58 PM PDT 24 178958100912 ps
T320 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1586104850 Jul 01 04:29:39 PM PDT 24 Jul 01 04:30:31 PM PDT 24 8342817450 ps
T321 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.497741183 Jul 01 04:29:38 PM PDT 24 Jul 01 04:35:45 PM PDT 24 70867850261 ps
T51 /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.724302233 Jul 01 04:29:31 PM PDT 24 Jul 01 05:51:25 PM PDT 24 53755572619 ps
T322 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.614248344 Jul 01 04:29:41 PM PDT 24 Jul 01 04:30:10 PM PDT 24 1374355752 ps
T323 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3348507483 Jul 01 04:29:27 PM PDT 24 Jul 01 04:29:58 PM PDT 24 4877897696 ps
T324 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1342052281 Jul 01 04:29:11 PM PDT 24 Jul 01 04:33:24 PM PDT 24 16354173357 ps
T325 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2190073185 Jul 01 04:28:56 PM PDT 24 Jul 01 04:29:20 PM PDT 24 319992090 ps
T52 /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2698869536 Jul 01 04:29:42 PM PDT 24 Jul 01 05:46:30 PM PDT 24 105615088617 ps
T326 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1909815889 Jul 01 04:29:47 PM PDT 24 Jul 01 04:30:28 PM PDT 24 13788427451 ps
T327 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2249266564 Jul 01 04:29:44 PM PDT 24 Jul 01 04:30:09 PM PDT 24 843285547 ps
T328 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1683704171 Jul 01 04:31:18 PM PDT 24 Jul 01 04:32:20 PM PDT 24 5280824643 ps
T329 /workspace/coverage/default/5.rom_ctrl_smoke.3063944483 Jul 01 04:29:11 PM PDT 24 Jul 01 04:29:41 PM PDT 24 1315683154 ps
T330 /workspace/coverage/default/18.rom_ctrl_stress_all.2617186387 Jul 01 04:29:40 PM PDT 24 Jul 01 04:30:48 PM PDT 24 6563022948 ps
T331 /workspace/coverage/default/15.rom_ctrl_stress_all.168044539 Jul 01 04:29:29 PM PDT 24 Jul 01 04:31:05 PM PDT 24 8548720118 ps
T332 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3927337228 Jul 01 04:29:43 PM PDT 24 Jul 01 04:30:12 PM PDT 24 4661534134 ps
T333 /workspace/coverage/default/19.rom_ctrl_alert_test.3408979319 Jul 01 04:29:44 PM PDT 24 Jul 01 04:30:06 PM PDT 24 517336808 ps
T334 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.10157796 Jul 01 04:29:45 PM PDT 24 Jul 01 04:30:14 PM PDT 24 925531895 ps
T335 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.807002399 Jul 01 04:29:46 PM PDT 24 Jul 01 04:30:17 PM PDT 24 1500057582 ps
T336 /workspace/coverage/default/47.rom_ctrl_alert_test.284339226 Jul 01 04:29:48 PM PDT 24 Jul 01 04:30:28 PM PDT 24 3302553241 ps
T337 /workspace/coverage/default/19.rom_ctrl_smoke.341621629 Jul 01 04:29:40 PM PDT 24 Jul 01 04:30:38 PM PDT 24 10654519206 ps
T338 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3759376598 Jul 01 04:30:59 PM PDT 24 Jul 01 04:31:53 PM PDT 24 13640123685 ps
T339 /workspace/coverage/default/1.rom_ctrl_stress_all.1852028941 Jul 01 04:29:21 PM PDT 24 Jul 01 04:31:17 PM PDT 24 29600448879 ps
T340 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1977117413 Jul 01 04:29:35 PM PDT 24 Jul 01 04:32:37 PM PDT 24 14691955598 ps
T341 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3113613136 Jul 01 04:29:54 PM PDT 24 Jul 01 04:31:07 PM PDT 24 27908649645 ps
T342 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3292556569 Jul 01 04:29:19 PM PDT 24 Jul 01 04:30:21 PM PDT 24 38989287261 ps
T343 /workspace/coverage/default/38.rom_ctrl_alert_test.1885090787 Jul 01 04:29:41 PM PDT 24 Jul 01 04:30:18 PM PDT 24 3352506579 ps
T344 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1857916151 Jul 01 04:29:19 PM PDT 24 Jul 01 04:36:04 PM PDT 24 87205720507 ps
T30 /workspace/coverage/default/0.rom_ctrl_sec_cm.2648037409 Jul 01 04:29:10 PM PDT 24 Jul 01 04:33:07 PM PDT 24 1180510250 ps
T16 /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.4236103381 Jul 01 04:29:43 PM PDT 24 Jul 01 05:06:28 PM PDT 24 65605816255 ps
T345 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.428862406 Jul 01 04:29:24 PM PDT 24 Jul 01 04:29:42 PM PDT 24 340637928 ps
T346 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2263354993 Jul 01 04:29:26 PM PDT 24 Jul 01 04:29:52 PM PDT 24 2999605873 ps
T347 /workspace/coverage/default/48.rom_ctrl_alert_test.3756891162 Jul 01 04:30:00 PM PDT 24 Jul 01 04:30:27 PM PDT 24 5201495057 ps
T348 /workspace/coverage/default/29.rom_ctrl_stress_all.1151400677 Jul 01 04:29:43 PM PDT 24 Jul 01 04:31:55 PM PDT 24 114313711328 ps
T349 /workspace/coverage/default/35.rom_ctrl_alert_test.1856131661 Jul 01 04:29:41 PM PDT 24 Jul 01 04:29:59 PM PDT 24 345544839 ps
T350 /workspace/coverage/default/22.rom_ctrl_stress_all.3100568062 Jul 01 04:29:39 PM PDT 24 Jul 01 04:31:46 PM PDT 24 12916879593 ps
T351 /workspace/coverage/default/14.rom_ctrl_stress_all.2741175792 Jul 01 04:29:16 PM PDT 24 Jul 01 04:33:06 PM PDT 24 28683958137 ps
T352 /workspace/coverage/default/13.rom_ctrl_stress_all.179194882 Jul 01 04:29:38 PM PDT 24 Jul 01 04:30:09 PM PDT 24 1594779843 ps
T353 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3076477545 Jul 01 04:29:36 PM PDT 24 Jul 01 04:37:12 PM PDT 24 94309339552 ps
T354 /workspace/coverage/default/23.rom_ctrl_stress_all.927326312 Jul 01 04:29:37 PM PDT 24 Jul 01 04:30:51 PM PDT 24 35132588372 ps
T355 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.649992953 Jul 01 04:29:29 PM PDT 24 Jul 01 04:29:46 PM PDT 24 725354950 ps
T356 /workspace/coverage/default/21.rom_ctrl_stress_all.2692986305 Jul 01 04:29:36 PM PDT 24 Jul 01 04:30:06 PM PDT 24 404745520 ps
T53 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.33703517 Jul 01 04:26:36 PM PDT 24 Jul 01 04:29:17 PM PDT 24 912884067 ps
T66 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1693864447 Jul 01 04:27:49 PM PDT 24 Jul 01 04:28:20 PM PDT 24 24715993084 ps
T67 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.328491326 Jul 01 04:26:57 PM PDT 24 Jul 01 04:27:20 PM PDT 24 1498767963 ps
T357 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.69153085 Jul 01 04:26:52 PM PDT 24 Jul 01 04:27:11 PM PDT 24 660987476 ps
T96 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1622096214 Jul 01 04:26:36 PM PDT 24 Jul 01 04:26:52 PM PDT 24 719203231 ps
T54 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2576386261 Jul 01 04:26:50 PM PDT 24 Jul 01 04:27:14 PM PDT 24 1646950488 ps
T73 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1173360314 Jul 01 04:26:37 PM PDT 24 Jul 01 04:27:06 PM PDT 24 2067499901 ps
T358 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3543034266 Jul 01 04:27:38 PM PDT 24 Jul 01 04:28:00 PM PDT 24 1406377164 ps
T74 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2582895470 Jul 01 04:26:49 PM PDT 24 Jul 01 04:27:25 PM PDT 24 11382753880 ps
T64 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.953100175 Jul 01 04:26:49 PM PDT 24 Jul 01 04:28:42 PM PDT 24 4048449658 ps
T100 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1399960187 Jul 01 04:26:37 PM PDT 24 Jul 01 04:29:21 PM PDT 24 90108220666 ps
T359 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.4275705428 Jul 01 04:26:44 PM PDT 24 Jul 01 04:27:20 PM PDT 24 3363238532 ps
T65 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2675846601 Jul 01 04:27:05 PM PDT 24 Jul 01 04:30:17 PM PDT 24 4187064425 ps
T105 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4198097378 Jul 01 04:27:04 PM PDT 24 Jul 01 04:28:40 PM PDT 24 916248710 ps
T75 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.276656319 Jul 01 04:27:02 PM PDT 24 Jul 01 04:27:40 PM PDT 24 8837493302 ps
T360 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2017012608 Jul 01 04:26:52 PM PDT 24 Jul 01 04:27:31 PM PDT 24 6643347639 ps
T101 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3857989384 Jul 01 04:26:34 PM PDT 24 Jul 01 04:29:48 PM PDT 24 28176975173 ps
T361 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1807113346 Jul 01 04:26:52 PM PDT 24 Jul 01 04:27:23 PM PDT 24 7893847805 ps
T362 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3812565717 Jul 01 04:26:51 PM PDT 24 Jul 01 04:27:25 PM PDT 24 2328546903 ps
T97 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1594054134 Jul 01 04:26:41 PM PDT 24 Jul 01 04:27:18 PM PDT 24 4106651078 ps
T102 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1860971686 Jul 01 04:26:53 PM PDT 24 Jul 01 04:28:34 PM PDT 24 9209138468 ps
T363 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1097834274 Jul 01 04:26:54 PM PDT 24 Jul 01 04:27:36 PM PDT 24 32811282549 ps
T364 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1092094884 Jul 01 04:27:01 PM PDT 24 Jul 01 04:27:25 PM PDT 24 1018608873 ps
T115 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.738983863 Jul 01 04:27:33 PM PDT 24 Jul 01 04:29:02 PM PDT 24 1129832586 ps
T365 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3069458362 Jul 01 04:26:47 PM PDT 24 Jul 01 04:27:25 PM PDT 24 13792153565 ps
T366 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.54634273 Jul 01 04:26:37 PM PDT 24 Jul 01 04:27:02 PM PDT 24 1004476935 ps
T76 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2086630727 Jul 01 04:26:52 PM PDT 24 Jul 01 04:27:59 PM PDT 24 2153931034 ps
T106 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1395144005 Jul 01 04:26:59 PM PDT 24 Jul 01 04:28:56 PM PDT 24 4547562755 ps
T367 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3780220156 Jul 01 04:26:48 PM PDT 24 Jul 01 04:27:23 PM PDT 24 2740706092 ps
T108 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2522729915 Jul 01 04:26:34 PM PDT 24 Jul 01 04:29:33 PM PDT 24 7456456252 ps
T368 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1002337966 Jul 01 04:27:02 PM PDT 24 Jul 01 04:27:39 PM PDT 24 8927339961 ps
T369 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2998098775 Jul 01 04:26:41 PM PDT 24 Jul 01 04:27:17 PM PDT 24 14348282055 ps
T370 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.724118955 Jul 01 04:26:51 PM PDT 24 Jul 01 04:27:32 PM PDT 24 3931716295 ps
T98 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.658057175 Jul 01 04:26:59 PM PDT 24 Jul 01 04:27:40 PM PDT 24 15375935436 ps
T99 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.859153294 Jul 01 04:26:58 PM PDT 24 Jul 01 04:27:35 PM PDT 24 2495416022 ps
T77 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3211287933 Jul 01 04:26:36 PM PDT 24 Jul 01 04:26:58 PM PDT 24 1085481589 ps
T78 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1197854749 Jul 01 04:27:00 PM PDT 24 Jul 01 04:27:42 PM PDT 24 3442805557 ps
T79 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.577305048 Jul 01 04:27:09 PM PDT 24 Jul 01 04:29:15 PM PDT 24 13050896336 ps
T371 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3786244426 Jul 01 04:26:49 PM PDT 24 Jul 01 04:29:44 PM PDT 24 2291247951 ps
T372 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1606720098 Jul 01 04:26:57 PM PDT 24 Jul 01 04:27:41 PM PDT 24 17102648932 ps
T373 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3818667427 Jul 01 04:26:49 PM PDT 24 Jul 01 04:27:10 PM PDT 24 169270031 ps
T374 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2787045692 Jul 01 04:27:18 PM PDT 24 Jul 01 04:27:41 PM PDT 24 349536659 ps
T375 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1261315985 Jul 01 04:26:33 PM PDT 24 Jul 01 04:27:11 PM PDT 24 38623770085 ps
T376 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.849850851 Jul 01 04:26:48 PM PDT 24 Jul 01 04:27:31 PM PDT 24 4268573080 ps
T377 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3596501108 Jul 01 04:26:41 PM PDT 24 Jul 01 04:26:56 PM PDT 24 174254568 ps
T80 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4122401114 Jul 01 04:27:08 PM PDT 24 Jul 01 04:28:07 PM PDT 24 1039813846 ps
T81 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.171909036 Jul 01 04:26:41 PM PDT 24 Jul 01 04:29:26 PM PDT 24 87226663420 ps
T82 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1457924212 Jul 01 04:26:52 PM PDT 24 Jul 01 04:28:15 PM PDT 24 54023417268 ps
T378 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1430589833 Jul 01 04:26:45 PM PDT 24 Jul 01 04:27:14 PM PDT 24 6768130480 ps
T379 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.4188593500 Jul 01 04:27:08 PM PDT 24 Jul 01 04:27:55 PM PDT 24 16318113825 ps
T87 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4201860584 Jul 01 04:26:48 PM PDT 24 Jul 01 04:27:23 PM PDT 24 3099854121 ps
T380 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1833337460 Jul 01 04:26:58 PM PDT 24 Jul 01 04:27:46 PM PDT 24 16758935999 ps
T381 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1080271204 Jul 01 04:27:11 PM PDT 24 Jul 01 04:29:14 PM PDT 24 12461285037 ps
T382 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3391602844 Jul 01 04:27:03 PM PDT 24 Jul 01 04:27:46 PM PDT 24 3829235667 ps
T383 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4216398983 Jul 01 04:26:53 PM PDT 24 Jul 01 04:27:31 PM PDT 24 6416869493 ps
T107 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2506843012 Jul 01 04:26:51 PM PDT 24 Jul 01 04:29:50 PM PDT 24 3720502156 ps
T384 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2313791643 Jul 01 04:26:42 PM PDT 24 Jul 01 04:27:16 PM PDT 24 6662211505 ps
T385 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2789372009 Jul 01 04:26:58 PM PDT 24 Jul 01 04:27:54 PM PDT 24 7865187863 ps
T386 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.489641965 Jul 01 04:27:02 PM PDT 24 Jul 01 04:27:45 PM PDT 24 13670194840 ps
T387 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1539879967 Jul 01 04:26:41 PM PDT 24 Jul 01 04:27:11 PM PDT 24 8854867146 ps
T110 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.722458311 Jul 01 04:26:54 PM PDT 24 Jul 01 04:29:36 PM PDT 24 1226530442 ps
T112 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3895315614 Jul 01 04:26:47 PM PDT 24 Jul 01 04:29:31 PM PDT 24 1232585242 ps
T388 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.834866631 Jul 01 04:27:14 PM PDT 24 Jul 01 04:28:02 PM PDT 24 3244263313 ps
T111 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4025963396 Jul 01 04:26:37 PM PDT 24 Jul 01 04:29:29 PM PDT 24 2779655308 ps
T88 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1472517169 Jul 01 04:26:43 PM PDT 24 Jul 01 04:27:23 PM PDT 24 4220363447 ps
T389 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1090476212 Jul 01 04:27:16 PM PDT 24 Jul 01 04:27:41 PM PDT 24 345848425 ps
T390 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1951566183 Jul 01 04:26:53 PM PDT 24 Jul 01 04:27:28 PM PDT 24 6409638144 ps
T391 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2420253297 Jul 01 04:26:48 PM PDT 24 Jul 01 04:27:13 PM PDT 24 1398801780 ps
T89 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2364183928 Jul 01 04:26:51 PM PDT 24 Jul 01 04:29:10 PM PDT 24 16460837337 ps
T392 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1980090089 Jul 01 04:26:56 PM PDT 24 Jul 01 04:27:22 PM PDT 24 5126248778 ps
T109 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3597479913 Jul 01 04:27:20 PM PDT 24 Jul 01 04:30:30 PM PDT 24 17609948409 ps
T90 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1295863120 Jul 01 04:26:57 PM PDT 24 Jul 01 04:27:18 PM PDT 24 167564360 ps
T393 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3069643687 Jul 01 04:27:00 PM PDT 24 Jul 01 04:27:24 PM PDT 24 761734041 ps
T394 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2222375098 Jul 01 04:27:04 PM PDT 24 Jul 01 04:27:44 PM PDT 24 3455284792 ps
T91 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4085025135 Jul 01 04:27:00 PM PDT 24 Jul 01 04:27:36 PM PDT 24 4192130332 ps
T113 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3862385995 Jul 01 04:26:42 PM PDT 24 Jul 01 04:28:32 PM PDT 24 3973250591 ps
T395 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2235565811 Jul 01 04:26:50 PM PDT 24 Jul 01 04:27:16 PM PDT 24 1074699656 ps
T396 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2142970257 Jul 01 04:26:57 PM PDT 24 Jul 01 04:27:29 PM PDT 24 1707149782 ps
T397 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3901826194 Jul 01 04:26:37 PM PDT 24 Jul 01 04:27:15 PM PDT 24 15729683381 ps
T398 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2244271294 Jul 01 04:26:57 PM PDT 24 Jul 01 04:27:36 PM PDT 24 12448705374 ps
T399 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2712881541 Jul 01 04:26:48 PM PDT 24 Jul 01 04:27:25 PM PDT 24 3517735376 ps
T400 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3194724735 Jul 01 04:26:36 PM PDT 24 Jul 01 04:27:02 PM PDT 24 6239895676 ps
T401 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2326953046 Jul 01 04:26:42 PM PDT 24 Jul 01 04:27:20 PM PDT 24 36104822702 ps
T402 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1798263181 Jul 01 04:26:38 PM PDT 24 Jul 01 04:27:11 PM PDT 24 3156863121 ps
T403 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3650130645 Jul 01 04:26:50 PM PDT 24 Jul 01 04:27:19 PM PDT 24 10180169747 ps
T404 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2371682990 Jul 01 04:27:04 PM PDT 24 Jul 01 04:30:08 PM PDT 24 39509713772 ps
T405 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2329265599 Jul 01 04:26:58 PM PDT 24 Jul 01 04:27:31 PM PDT 24 2064303910 ps
T117 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2151867529 Jul 01 04:26:35 PM PDT 24 Jul 01 04:29:31 PM PDT 24 16894941430 ps
T406 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.548932857 Jul 01 04:26:48 PM PDT 24 Jul 01 04:27:28 PM PDT 24 11335196790 ps
T407 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2434252440 Jul 01 04:26:55 PM PDT 24 Jul 01 04:28:02 PM PDT 24 1041911051 ps
T408 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2846170138 Jul 01 04:26:37 PM PDT 24 Jul 01 04:26:56 PM PDT 24 1829172861 ps
T114 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3213927249 Jul 01 04:27:04 PM PDT 24 Jul 01 04:30:08 PM PDT 24 12353474813 ps
T116 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3168370523 Jul 01 04:26:48 PM PDT 24 Jul 01 04:29:32 PM PDT 24 499265453 ps
T409 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3261945168 Jul 01 04:26:59 PM PDT 24 Jul 01 04:29:38 PM PDT 24 31175576624 ps
T93 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3800641695 Jul 01 04:26:47 PM PDT 24 Jul 01 04:27:21 PM PDT 24 3080266631 ps
T410 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2195744870 Jul 01 04:27:01 PM PDT 24 Jul 01 04:28:10 PM PDT 24 1217871358 ps
T411 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.304335686 Jul 01 04:26:53 PM PDT 24 Jul 01 04:27:33 PM PDT 24 12237537062 ps
T412 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2171535367 Jul 01 04:27:06 PM PDT 24 Jul 01 04:27:43 PM PDT 24 10334908769 ps
T413 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1380900260 Jul 01 04:27:12 PM PDT 24 Jul 01 04:27:42 PM PDT 24 4818687184 ps
T95 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3587353340 Jul 01 04:26:50 PM PDT 24 Jul 01 04:27:15 PM PDT 24 926502271 ps
T414 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3189995331 Jul 01 04:26:40 PM PDT 24 Jul 01 04:27:11 PM PDT 24 11729177716 ps
T415 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2186543636 Jul 01 04:26:30 PM PDT 24 Jul 01 04:27:02 PM PDT 24 2548464644 ps
T416 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3818085042 Jul 01 04:26:53 PM PDT 24 Jul 01 04:27:30 PM PDT 24 6603023433 ps
T417 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2992296992 Jul 01 04:26:48 PM PDT 24 Jul 01 04:27:06 PM PDT 24 688719018 ps
T94 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3273430765 Jul 01 04:26:56 PM PDT 24 Jul 01 04:28:04 PM PDT 24 4142730655 ps
T418 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.161436457 Jul 01 04:26:47 PM PDT 24 Jul 01 04:29:23 PM PDT 24 14789468745 ps
T419 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1148993942 Jul 01 04:27:03 PM PDT 24 Jul 01 04:27:42 PM PDT 24 2645360106 ps
T420 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.791715958 Jul 01 04:26:54 PM PDT 24 Jul 01 04:27:19 PM PDT 24 680027179 ps
T421 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2121339823 Jul 01 04:26:38 PM PDT 24 Jul 01 04:27:13 PM PDT 24 3517569391 ps
T422 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.448105182 Jul 01 04:27:05 PM PDT 24 Jul 01 04:27:45 PM PDT 24 2301914029 ps
T423 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2984828545 Jul 01 04:26:39 PM PDT 24 Jul 01 04:27:20 PM PDT 24 3952720436 ps
T424 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2380845071 Jul 01 04:27:13 PM PDT 24 Jul 01 04:27:57 PM PDT 24 6518608502 ps
T425 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.901764323 Jul 01 04:27:00 PM PDT 24 Jul 01 04:27:44 PM PDT 24 5430330614 ps
T426 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3255721849 Jul 01 04:26:41 PM PDT 24 Jul 01 04:27:19 PM PDT 24 8226979708 ps
T427 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2831411229 Jul 01 04:26:52 PM PDT 24 Jul 01 04:27:15 PM PDT 24 697646392 ps
T428 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.207214250 Jul 01 04:27:13 PM PDT 24 Jul 01 04:28:24 PM PDT 24 1056594335 ps
T429 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3802923840 Jul 01 04:26:38 PM PDT 24 Jul 01 04:27:09 PM PDT 24 4225272648 ps
T430 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2564788344 Jul 01 04:26:57 PM PDT 24 Jul 01 04:27:21 PM PDT 24 660965323 ps
T431 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.654137495 Jul 01 04:26:49 PM PDT 24 Jul 01 04:27:26 PM PDT 24 7179803284 ps
T432 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.4126003885 Jul 01 04:26:53 PM PDT 24 Jul 01 04:27:13 PM PDT 24 198587209 ps
T433 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1193505813 Jul 01 04:26:48 PM PDT 24 Jul 01 04:27:05 PM PDT 24 394351044 ps
T434 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3194256794 Jul 01 04:26:41 PM PDT 24 Jul 01 04:28:43 PM PDT 24 67454109289 ps
T104 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4100266402 Jul 01 04:26:49 PM PDT 24 Jul 01 04:29:50 PM PDT 24 11584377354 ps
T435 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.604858872 Jul 01 04:26:42 PM PDT 24 Jul 01 04:27:15 PM PDT 24 9149852366 ps
T436 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.706178265 Jul 01 04:27:04 PM PDT 24 Jul 01 04:27:39 PM PDT 24 2135946077 ps
T437 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.86039364 Jul 01 04:26:55 PM PDT 24 Jul 01 04:29:37 PM PDT 24 15950384952 ps
T438 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2333849039 Jul 01 04:27:02 PM PDT 24 Jul 01 04:28:35 PM PDT 24 950921591 ps
T439 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4026028635 Jul 01 04:26:51 PM PDT 24 Jul 01 04:27:31 PM PDT 24 14924905189 ps
T440 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1743758206 Jul 01 04:26:46 PM PDT 24 Jul 01 04:27:25 PM PDT 24 3803396318 ps
T441 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3819779908 Jul 01 04:27:43 PM PDT 24 Jul 01 04:28:30 PM PDT 24 16973773499 ps
T92 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1155706593 Jul 01 04:26:44 PM PDT 24 Jul 01 04:27:13 PM PDT 24 2148845852 ps
T442 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3261559707 Jul 01 04:26:51 PM PDT 24 Jul 01 04:27:10 PM PDT 24 825791658 ps
T443 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3186930753 Jul 01 04:26:57 PM PDT 24 Jul 01 04:27:26 PM PDT 24 1386795389 ps
T444 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2933778149 Jul 01 04:26:44 PM PDT 24 Jul 01 04:27:05 PM PDT 24 660923643 ps
T445 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.4081077725 Jul 01 04:27:06 PM PDT 24 Jul 01 04:29:21 PM PDT 24 11805675731 ps
T446 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3003061133 Jul 01 04:26:51 PM PDT 24 Jul 01 04:27:14 PM PDT 24 668580864 ps
T447 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2146676073 Jul 01 04:27:36 PM PDT 24 Jul 01 04:28:05 PM PDT 24 3115628014 ps
T448 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1414814384 Jul 01 04:26:46 PM PDT 24 Jul 01 04:27:16 PM PDT 24 8176492082 ps
T449 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3781804628 Jul 01 04:26:49 PM PDT 24 Jul 01 04:27:27 PM PDT 24 3861592502 ps
T450 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.327127912 Jul 01 04:26:36 PM PDT 24 Jul 01 04:27:03 PM PDT 24 7516830831 ps
T451 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.941317318 Jul 01 04:26:43 PM PDT 24 Jul 01 04:27:22 PM PDT 24 4707603955 ps
T452 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3018205028 Jul 01 04:26:55 PM PDT 24 Jul 01 04:27:28 PM PDT 24 4623427472 ps
T453 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1613034861 Jul 01 04:26:50 PM PDT 24 Jul 01 04:27:23 PM PDT 24 28927867943 ps
T454 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1324468888 Jul 01 04:26:58 PM PDT 24 Jul 01 04:27:31 PM PDT 24 9436133969 ps

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1943262635
Short name T10
Test name
Test status
Simulation time 20772987629 ps
CPU time 361.82 seconds
Started Jul 01 04:29:39 PM PDT 24
Finished Jul 01 04:35:47 PM PDT 24
Peak memory 234764 kb
Host smart-999aec60-0391-4d25-a2b1-f30aab8b0986
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943262635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1943262635
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.3054198999
Short name T13
Test name
Test status
Simulation time 118754135259 ps
CPU time 4052.19 seconds
Started Jul 01 04:30:07 PM PDT 24
Finished Jul 01 05:37:55 PM PDT 24
Peak memory 235144 kb
Host smart-e02f50b2-94b7-49ec-955b-893952b4a2e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054198999 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.3054198999
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.4149378769
Short name T11
Test name
Test status
Simulation time 67211265703 ps
CPU time 142.57 seconds
Started Jul 01 04:29:19 PM PDT 24
Finished Jul 01 04:31:50 PM PDT 24
Peak memory 219680 kb
Host smart-83d6351e-d51f-4dea-b9c4-7d1333fe2541
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149378769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.4149378769
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.607405061
Short name T38
Test name
Test status
Simulation time 97991114270 ps
CPU time 587.79 seconds
Started Jul 01 04:29:30 PM PDT 24
Finished Jul 01 04:39:24 PM PDT 24
Peak memory 238512 kb
Host smart-7e1689e9-9b17-4dd9-992c-06e339a55442
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607405061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.607405061
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.80675152
Short name T121
Test name
Test status
Simulation time 728576102 ps
CPU time 10.58 seconds
Started Jul 01 04:29:17 PM PDT 24
Finished Jul 01 04:29:36 PM PDT 24
Peak memory 219220 kb
Host smart-8040c93b-6469-4188-bab2-2440d9f42c15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=80675152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.80675152
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2675846601
Short name T65
Test name
Test status
Simulation time 4187064425 ps
CPU time 176.91 seconds
Started Jul 01 04:27:05 PM PDT 24
Finished Jul 01 04:30:17 PM PDT 24
Peak memory 213868 kb
Host smart-47776d30-1f53-43e4-942a-b2de000106e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675846601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2675846601
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.107203818
Short name T43
Test name
Test status
Simulation time 2586263597 ps
CPU time 22.77 seconds
Started Jul 01 04:29:28 PM PDT 24
Finished Jul 01 04:29:57 PM PDT 24
Peak memory 217212 kb
Host smart-bbf59c80-ebc4-476f-a3d5-2bc970799f06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107203818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.107203818
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3280801800
Short name T18
Test name
Test status
Simulation time 362477885 ps
CPU time 20.61 seconds
Started Jul 01 04:29:46 PM PDT 24
Finished Jul 01 04:30:18 PM PDT 24
Peak memory 216324 kb
Host smart-e383f72f-7eff-4cb5-a8cf-885aa587976c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280801800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3280801800
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.108981464
Short name T128
Test name
Test status
Simulation time 7468058215 ps
CPU time 85.07 seconds
Started Jul 01 04:29:39 PM PDT 24
Finished Jul 01 04:31:12 PM PDT 24
Peak memory 220616 kb
Host smart-098ab234-0bf6-48de-9e5c-4764551731b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108981464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.108981464
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2150496166
Short name T26
Test name
Test status
Simulation time 3903844342 ps
CPU time 240.73 seconds
Started Jul 01 04:29:03 PM PDT 24
Finished Jul 01 04:33:15 PM PDT 24
Peak memory 235968 kb
Host smart-17f7bfa5-ccbb-48a1-8e37-84a96436924b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150496166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2150496166
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.577305048
Short name T79
Test name
Test status
Simulation time 13050896336 ps
CPU time 112.12 seconds
Started Jul 01 04:27:09 PM PDT 24
Finished Jul 01 04:29:15 PM PDT 24
Peak memory 213920 kb
Host smart-cc3510e2-f1ba-4f81-b4cd-8617994d3776
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577305048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.577305048
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3597479913
Short name T109
Test name
Test status
Simulation time 17609948409 ps
CPU time 177.32 seconds
Started Jul 01 04:27:20 PM PDT 24
Finished Jul 01 04:30:30 PM PDT 24
Peak memory 214496 kb
Host smart-33fce461-fdb9-4f4c-b80a-aa39d10260e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597479913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3597479913
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.33703517
Short name T53
Test name
Test status
Simulation time 912884067 ps
CPU time 153.57 seconds
Started Jul 01 04:26:36 PM PDT 24
Finished Jul 01 04:29:17 PM PDT 24
Peak memory 213944 kb
Host smart-a6c08d74-d7a7-4850-9fa3-124d8826a6a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33703517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_intg
_err.33703517
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3198506458
Short name T35
Test name
Test status
Simulation time 11549402915 ps
CPU time 25.14 seconds
Started Jul 01 04:29:43 PM PDT 24
Finished Jul 01 04:30:19 PM PDT 24
Peak memory 211868 kb
Host smart-aa9bb51b-e851-4eda-a59f-8bfef02f8d9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3198506458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3198506458
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.4287215227
Short name T33
Test name
Test status
Simulation time 26198841280 ps
CPU time 57.92 seconds
Started Jul 01 04:29:17 PM PDT 24
Finished Jul 01 04:30:24 PM PDT 24
Peak memory 219284 kb
Host smart-7441bb2f-80af-4628-aa05-c41d17b9c9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287215227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.4287215227
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.660155886
Short name T145
Test name
Test status
Simulation time 8213537272 ps
CPU time 43.47 seconds
Started Jul 01 04:29:34 PM PDT 24
Finished Jul 01 04:30:23 PM PDT 24
Peak memory 219288 kb
Host smart-3001615e-24c9-4a4e-9538-2b5ea36589a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660155886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.660155886
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1622096214
Short name T96
Test name
Test status
Simulation time 719203231 ps
CPU time 8.03 seconds
Started Jul 01 04:26:36 PM PDT 24
Finished Jul 01 04:26:52 PM PDT 24
Peak memory 211032 kb
Host smart-b25b8ae7-d666-4d0b-a17a-b322f3572fb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622096214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1622096214
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4100266402
Short name T104
Test name
Test status
Simulation time 11584377354 ps
CPU time 171.6 seconds
Started Jul 01 04:26:49 PM PDT 24
Finished Jul 01 04:29:50 PM PDT 24
Peak memory 213200 kb
Host smart-447dff35-3da7-4b88-8697-258b21bd4efb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100266402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.4100266402
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2662108621
Short name T134
Test name
Test status
Simulation time 37496249833 ps
CPU time 331.55 seconds
Started Jul 01 04:29:20 PM PDT 24
Finished Jul 01 04:35:00 PM PDT 24
Peak memory 239060 kb
Host smart-d07555d8-c827-4e5f-a13c-e32aeaf89ac7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662108621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2662108621
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.4236103381
Short name T16
Test name
Test status
Simulation time 65605816255 ps
CPU time 2193.7 seconds
Started Jul 01 04:29:43 PM PDT 24
Finished Jul 01 05:06:28 PM PDT 24
Peak memory 235700 kb
Host smart-5efab01b-a16e-47d4-b44f-20021c06f99f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236103381 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.4236103381
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3911378141
Short name T169
Test name
Test status
Simulation time 28850575812 ps
CPU time 74.17 seconds
Started Jul 01 04:29:34 PM PDT 24
Finished Jul 01 04:30:54 PM PDT 24
Peak memory 216492 kb
Host smart-8df34d4d-e834-47fa-afea-a0e15d56f109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911378141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3911378141
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2313791643
Short name T384
Test name
Test status
Simulation time 6662211505 ps
CPU time 26.55 seconds
Started Jul 01 04:26:42 PM PDT 24
Finished Jul 01 04:27:16 PM PDT 24
Peak memory 211880 kb
Host smart-c6a1b745-0cfd-4750-942b-d181f1c314fa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313791643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2313791643
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2121339823
Short name T421
Test name
Test status
Simulation time 3517569391 ps
CPU time 27.79 seconds
Started Jul 01 04:26:38 PM PDT 24
Finished Jul 01 04:27:13 PM PDT 24
Peak memory 211132 kb
Host smart-dad91499-7b43-4e04-ac09-17d8a9935183
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121339823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2121339823
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2831411229
Short name T427
Test name
Test status
Simulation time 697646392 ps
CPU time 12.06 seconds
Started Jul 01 04:26:52 PM PDT 24
Finished Jul 01 04:27:15 PM PDT 24
Peak memory 211020 kb
Host smart-adbcb69b-2a2d-418a-916a-21fb4b690cf7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831411229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2831411229
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2998098775
Short name T369
Test name
Test status
Simulation time 14348282055 ps
CPU time 28.59 seconds
Started Jul 01 04:26:41 PM PDT 24
Finished Jul 01 04:27:17 PM PDT 24
Peak memory 217604 kb
Host smart-169e6e27-582f-4fbb-93f6-791420766ef4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998098775 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2998098775
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1472517169
Short name T88
Test name
Test status
Simulation time 4220363447 ps
CPU time 31.95 seconds
Started Jul 01 04:26:43 PM PDT 24
Finished Jul 01 04:27:23 PM PDT 24
Peak memory 211880 kb
Host smart-cf34f50c-7305-46bb-a23a-68d45f3279ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472517169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1472517169
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1430589833
Short name T378
Test name
Test status
Simulation time 6768130480 ps
CPU time 20.97 seconds
Started Jul 01 04:26:45 PM PDT 24
Finished Jul 01 04:27:14 PM PDT 24
Peak memory 210804 kb
Host smart-002445b2-d8d8-4950-acb8-b235482615f9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430589833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1430589833
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3802923840
Short name T429
Test name
Test status
Simulation time 4225272648 ps
CPU time 23.75 seconds
Started Jul 01 04:26:38 PM PDT 24
Finished Jul 01 04:27:09 PM PDT 24
Peak memory 210528 kb
Host smart-1eea4372-5091-43de-a019-257f75ec43b6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802923840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3802923840
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2195744870
Short name T410
Test name
Test status
Simulation time 1217871358 ps
CPU time 57.01 seconds
Started Jul 01 04:27:01 PM PDT 24
Finished Jul 01 04:28:10 PM PDT 24
Peak memory 213680 kb
Host smart-a729f366-7ec6-44ae-9f5f-e62c3c59a625
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195744870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2195744870
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.327127912
Short name T450
Test name
Test status
Simulation time 7516830831 ps
CPU time 19.2 seconds
Started Jul 01 04:26:36 PM PDT 24
Finished Jul 01 04:27:03 PM PDT 24
Peak memory 212648 kb
Host smart-1d5816a9-195f-4c7c-8dfc-83a36147c3f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327127912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.327127912
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4026028635
Short name T439
Test name
Test status
Simulation time 14924905189 ps
CPU time 29.42 seconds
Started Jul 01 04:26:51 PM PDT 24
Finished Jul 01 04:27:31 PM PDT 24
Peak memory 219012 kb
Host smart-01d91e7e-75f3-49da-a44a-a8906adcca61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026028635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.4026028635
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2186543636
Short name T415
Test name
Test status
Simulation time 2548464644 ps
CPU time 23.7 seconds
Started Jul 01 04:26:30 PM PDT 24
Finished Jul 01 04:27:02 PM PDT 24
Peak memory 210996 kb
Host smart-51eb2588-3ce9-4f3d-bbef-8e0e2a597713
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186543636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2186543636
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1807113346
Short name T361
Test name
Test status
Simulation time 7893847805 ps
CPU time 19.57 seconds
Started Jul 01 04:26:52 PM PDT 24
Finished Jul 01 04:27:23 PM PDT 24
Peak memory 211564 kb
Host smart-3a96cb3d-84ec-44b4-b9cd-4e64b23771a1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807113346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1807113346
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4085025135
Short name T91
Test name
Test status
Simulation time 4192130332 ps
CPU time 23.46 seconds
Started Jul 01 04:27:00 PM PDT 24
Finished Jul 01 04:27:36 PM PDT 24
Peak memory 210476 kb
Host smart-c7ae2066-c584-4bb6-b5ba-3f4760d81ad7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085025135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.4085025135
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1261315985
Short name T375
Test name
Test status
Simulation time 38623770085 ps
CPU time 30.96 seconds
Started Jul 01 04:26:33 PM PDT 24
Finished Jul 01 04:27:11 PM PDT 24
Peak memory 217112 kb
Host smart-1ce0b218-5537-49e1-9a0b-a4723fedaa41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261315985 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1261315985
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2846170138
Short name T408
Test name
Test status
Simulation time 1829172861 ps
CPU time 11.65 seconds
Started Jul 01 04:26:37 PM PDT 24
Finished Jul 01 04:26:56 PM PDT 24
Peak memory 210684 kb
Host smart-2deb9a83-4c29-48f3-9b62-10f505905376
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846170138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2846170138
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.724118955
Short name T370
Test name
Test status
Simulation time 3931716295 ps
CPU time 30.68 seconds
Started Jul 01 04:26:51 PM PDT 24
Finished Jul 01 04:27:32 PM PDT 24
Peak memory 210712 kb
Host smart-0c42a244-5dfc-4b17-8912-63c1c81046cf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724118955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.724118955
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3255721849
Short name T426
Test name
Test status
Simulation time 8226979708 ps
CPU time 31.13 seconds
Started Jul 01 04:26:41 PM PDT 24
Finished Jul 01 04:27:19 PM PDT 24
Peak memory 210812 kb
Host smart-a35bc5d9-b8c8-43e2-b313-31f2b5f2f79e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255721849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3255721849
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1399960187
Short name T100
Test name
Test status
Simulation time 90108220666 ps
CPU time 156.23 seconds
Started Jul 01 04:26:37 PM PDT 24
Finished Jul 01 04:29:21 PM PDT 24
Peak memory 215044 kb
Host smart-1a71d109-0973-4f51-8577-5fe426d076e9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399960187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1399960187
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3818667427
Short name T373
Test name
Test status
Simulation time 169270031 ps
CPU time 11.45 seconds
Started Jul 01 04:26:49 PM PDT 24
Finished Jul 01 04:27:10 PM PDT 24
Peak memory 217196 kb
Host smart-aad760c9-556c-48b1-9d38-20f12314dfcc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818667427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3818667427
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2522729915
Short name T108
Test name
Test status
Simulation time 7456456252 ps
CPU time 172.17 seconds
Started Jul 01 04:26:34 PM PDT 24
Finished Jul 01 04:29:33 PM PDT 24
Peak memory 214236 kb
Host smart-57daf287-2f9f-4b63-9268-099f6116ac8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522729915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2522729915
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3018205028
Short name T452
Test name
Test status
Simulation time 4623427472 ps
CPU time 21.26 seconds
Started Jul 01 04:26:55 PM PDT 24
Finished Jul 01 04:27:28 PM PDT 24
Peak memory 218096 kb
Host smart-4ffa1f20-2999-412e-9fd5-ffd13a9561bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018205028 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3018205028
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1613034861
Short name T453
Test name
Test status
Simulation time 28927867943 ps
CPU time 22 seconds
Started Jul 01 04:26:50 PM PDT 24
Finished Jul 01 04:27:23 PM PDT 24
Peak memory 211984 kb
Host smart-4257eb01-b722-4f8a-8770-1940b5bc5c7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613034861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1613034861
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1457924212
Short name T82
Test name
Test status
Simulation time 54023417268 ps
CPU time 72.62 seconds
Started Jul 01 04:26:52 PM PDT 24
Finished Jul 01 04:28:15 PM PDT 24
Peak memory 213848 kb
Host smart-ac7789c8-6ff2-473a-9628-5e406d700ede
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457924212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1457924212
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1693864447
Short name T66
Test name
Test status
Simulation time 24715993084 ps
CPU time 23.82 seconds
Started Jul 01 04:27:49 PM PDT 24
Finished Jul 01 04:28:20 PM PDT 24
Peak memory 212352 kb
Host smart-9b157739-c02a-45c6-b503-44d1b31e9b29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693864447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1693864447
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2017012608
Short name T360
Test name
Test status
Simulation time 6643347639 ps
CPU time 27.45 seconds
Started Jul 01 04:26:52 PM PDT 24
Finished Jul 01 04:27:31 PM PDT 24
Peak memory 217320 kb
Host smart-6c31354b-a872-4a6f-a108-881c86fbade3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017012608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2017012608
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2506843012
Short name T107
Test name
Test status
Simulation time 3720502156 ps
CPU time 168.13 seconds
Started Jul 01 04:26:51 PM PDT 24
Finished Jul 01 04:29:50 PM PDT 24
Peak memory 218888 kb
Host smart-2f70243e-2a99-4f9f-ae16-167d685ab3b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506843012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2506843012
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2787045692
Short name T374
Test name
Test status
Simulation time 349536659 ps
CPU time 10.3 seconds
Started Jul 01 04:27:18 PM PDT 24
Finished Jul 01 04:27:41 PM PDT 24
Peak memory 213220 kb
Host smart-45d71c3f-6880-4709-9f07-f720a3c429e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787045692 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2787045692
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4201860584
Short name T87
Test name
Test status
Simulation time 3099854121 ps
CPU time 26.13 seconds
Started Jul 01 04:26:48 PM PDT 24
Finished Jul 01 04:27:23 PM PDT 24
Peak memory 211656 kb
Host smart-14befac0-5fbe-4a2e-aaf7-395323a9708f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201860584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.4201860584
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1324468888
Short name T454
Test name
Test status
Simulation time 9436133969 ps
CPU time 22.21 seconds
Started Jul 01 04:26:58 PM PDT 24
Finished Jul 01 04:27:31 PM PDT 24
Peak memory 212280 kb
Host smart-b61ab4fc-4d9d-4532-8723-e080ad81f6ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324468888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1324468888
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1090476212
Short name T389
Test name
Test status
Simulation time 345848425 ps
CPU time 11.36 seconds
Started Jul 01 04:27:16 PM PDT 24
Finished Jul 01 04:27:41 PM PDT 24
Peak memory 217340 kb
Host smart-773b9b47-fd53-41bf-a842-c6d218768f41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090476212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1090476212
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2371682990
Short name T404
Test name
Test status
Simulation time 39509713772 ps
CPU time 169.99 seconds
Started Jul 01 04:27:04 PM PDT 24
Finished Jul 01 04:30:08 PM PDT 24
Peak memory 214260 kb
Host smart-24b4a47d-def4-415d-a40c-bdfc84e340f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371682990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2371682990
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3543034266
Short name T358
Test name
Test status
Simulation time 1406377164 ps
CPU time 11.52 seconds
Started Jul 01 04:27:38 PM PDT 24
Finished Jul 01 04:28:00 PM PDT 24
Peak memory 217220 kb
Host smart-5d3da13d-cd9b-409a-866e-499a89c74eb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543034266 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3543034266
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3800641695
Short name T93
Test name
Test status
Simulation time 3080266631 ps
CPU time 25.41 seconds
Started Jul 01 04:26:47 PM PDT 24
Finished Jul 01 04:27:21 PM PDT 24
Peak memory 211436 kb
Host smart-5ddb719b-e0db-4e94-a21a-2e4316fdfb0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800641695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3800641695
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1860971686
Short name T102
Test name
Test status
Simulation time 9209138468 ps
CPU time 90.02 seconds
Started Jul 01 04:26:53 PM PDT 24
Finished Jul 01 04:28:34 PM PDT 24
Peak memory 213788 kb
Host smart-ca2a5d04-0fad-4f66-9b5f-fc21c8cd9c6c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860971686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1860971686
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.448105182
Short name T422
Test name
Test status
Simulation time 2301914029 ps
CPU time 25.69 seconds
Started Jul 01 04:27:05 PM PDT 24
Finished Jul 01 04:27:45 PM PDT 24
Peak memory 212264 kb
Host smart-7d589a53-49ec-4bb8-b643-6629788763e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448105182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.448105182
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.834866631
Short name T388
Test name
Test status
Simulation time 3244263313 ps
CPU time 33.63 seconds
Started Jul 01 04:27:14 PM PDT 24
Finished Jul 01 04:28:02 PM PDT 24
Peak memory 218632 kb
Host smart-a3aec7ea-8585-4672-a70e-1a03817242a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834866631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.834866631
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3786244426
Short name T371
Test name
Test status
Simulation time 2291247951 ps
CPU time 164.55 seconds
Started Jul 01 04:26:49 PM PDT 24
Finished Jul 01 04:29:44 PM PDT 24
Peak memory 213880 kb
Host smart-e5b6d12e-c5c5-4b50-b11d-624afa0566fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786244426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3786244426
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3391602844
Short name T382
Test name
Test status
Simulation time 3829235667 ps
CPU time 29.99 seconds
Started Jul 01 04:27:03 PM PDT 24
Finished Jul 01 04:27:46 PM PDT 24
Peak memory 216152 kb
Host smart-03648c63-8fc7-44b1-83f8-b39e6e7a22f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391602844 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3391602844
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.654137495
Short name T431
Test name
Test status
Simulation time 7179803284 ps
CPU time 26.88 seconds
Started Jul 01 04:26:49 PM PDT 24
Finished Jul 01 04:27:26 PM PDT 24
Peak memory 211732 kb
Host smart-1af9ae19-2f1b-4200-b972-ae8b61c1a23b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654137495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.654137495
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3273430765
Short name T94
Test name
Test status
Simulation time 4142730655 ps
CPU time 56.26 seconds
Started Jul 01 04:26:56 PM PDT 24
Finished Jul 01 04:28:04 PM PDT 24
Peak memory 214108 kb
Host smart-ae96656a-9bbb-4afa-a45d-ca1d85279ae5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273430765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3273430765
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2146676073
Short name T447
Test name
Test status
Simulation time 3115628014 ps
CPU time 18.4 seconds
Started Jul 01 04:27:36 PM PDT 24
Finished Jul 01 04:28:05 PM PDT 24
Peak memory 211884 kb
Host smart-8259bd65-416f-4fcd-ac3b-b6b9fa0e61af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146676073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2146676073
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3781804628
Short name T449
Test name
Test status
Simulation time 3861592502 ps
CPU time 28.19 seconds
Started Jul 01 04:26:49 PM PDT 24
Finished Jul 01 04:27:27 PM PDT 24
Peak memory 218352 kb
Host smart-6f413ca5-9487-408e-aa1d-2baa63f7212f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781804628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3781804628
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1092094884
Short name T364
Test name
Test status
Simulation time 1018608873 ps
CPU time 11.94 seconds
Started Jul 01 04:27:01 PM PDT 24
Finished Jul 01 04:27:25 PM PDT 24
Peak memory 218856 kb
Host smart-f964b2f9-ab2c-4653-8d03-73e7d2801ddd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092094884 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1092094884
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.706178265
Short name T436
Test name
Test status
Simulation time 2135946077 ps
CPU time 20.61 seconds
Started Jul 01 04:27:04 PM PDT 24
Finished Jul 01 04:27:39 PM PDT 24
Peak memory 211292 kb
Host smart-2156acda-4455-427f-a8c4-5e66a011719d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706178265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.706178265
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2364183928
Short name T89
Test name
Test status
Simulation time 16460837337 ps
CPU time 129.65 seconds
Started Jul 01 04:26:51 PM PDT 24
Finished Jul 01 04:29:10 PM PDT 24
Peak memory 214124 kb
Host smart-625f9618-3f93-4294-8c31-01fcd52ec11a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364183928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2364183928
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2380845071
Short name T424
Test name
Test status
Simulation time 6518608502 ps
CPU time 29.84 seconds
Started Jul 01 04:27:13 PM PDT 24
Finished Jul 01 04:27:57 PM PDT 24
Peak memory 212580 kb
Host smart-6ab0762e-3835-4541-961e-620d1ad76f24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380845071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2380845071
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.304335686
Short name T411
Test name
Test status
Simulation time 12237537062 ps
CPU time 28.94 seconds
Started Jul 01 04:26:53 PM PDT 24
Finished Jul 01 04:27:33 PM PDT 24
Peak memory 218512 kb
Host smart-4bb1727f-83bf-4799-bb28-e0b27e8a0ab9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304335686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.304335686
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.738983863
Short name T115
Test name
Test status
Simulation time 1129832586 ps
CPU time 79.2 seconds
Started Jul 01 04:27:33 PM PDT 24
Finished Jul 01 04:29:02 PM PDT 24
Peak memory 213588 kb
Host smart-363962a0-7835-411f-8278-14ef519404f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738983863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.738983863
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2235565811
Short name T395
Test name
Test status
Simulation time 1074699656 ps
CPU time 15.15 seconds
Started Jul 01 04:26:50 PM PDT 24
Finished Jul 01 04:27:16 PM PDT 24
Peak memory 213480 kb
Host smart-0aa7ef77-5c31-4205-ba49-706e9ac1b216
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235565811 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2235565811
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2329265599
Short name T405
Test name
Test status
Simulation time 2064303910 ps
CPU time 20.57 seconds
Started Jul 01 04:26:58 PM PDT 24
Finished Jul 01 04:27:31 PM PDT 24
Peak memory 211900 kb
Host smart-7caea169-2f56-408a-9753-495db0bb52c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329265599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2329265599
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.161436457
Short name T418
Test name
Test status
Simulation time 14789468745 ps
CPU time 147.23 seconds
Started Jul 01 04:26:47 PM PDT 24
Finished Jul 01 04:29:23 PM PDT 24
Peak memory 215088 kb
Host smart-46fa1bef-1066-4abe-a937-40136a66be7b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161436457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.161436457
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3650130645
Short name T403
Test name
Test status
Simulation time 10180169747 ps
CPU time 18.94 seconds
Started Jul 01 04:26:50 PM PDT 24
Finished Jul 01 04:27:19 PM PDT 24
Peak memory 212524 kb
Host smart-5c112db8-9908-45e8-99e5-2cc5826f8f5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650130645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3650130645
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2576386261
Short name T54
Test name
Test status
Simulation time 1646950488 ps
CPU time 14.66 seconds
Started Jul 01 04:26:50 PM PDT 24
Finished Jul 01 04:27:14 PM PDT 24
Peak memory 218068 kb
Host smart-89973d4e-1bef-48d1-9a73-43e0db5e5229
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576386261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2576386261
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3895315614
Short name T112
Test name
Test status
Simulation time 1232585242 ps
CPU time 154.5 seconds
Started Jul 01 04:26:47 PM PDT 24
Finished Jul 01 04:29:31 PM PDT 24
Peak memory 213996 kb
Host smart-188bc144-fe8a-403a-96e5-27d1b1d46667
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895315614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3895315614
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3069643687
Short name T393
Test name
Test status
Simulation time 761734041 ps
CPU time 10.82 seconds
Started Jul 01 04:27:00 PM PDT 24
Finished Jul 01 04:27:24 PM PDT 24
Peak memory 218836 kb
Host smart-39e5f130-6bd9-45f0-9e11-481331a0b968
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069643687 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3069643687
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2171535367
Short name T412
Test name
Test status
Simulation time 10334908769 ps
CPU time 22.22 seconds
Started Jul 01 04:27:06 PM PDT 24
Finished Jul 01 04:27:43 PM PDT 24
Peak memory 211852 kb
Host smart-3eae1e54-4c16-48de-8bd2-7145a0d6a06b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171535367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2171535367
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.4081077725
Short name T445
Test name
Test status
Simulation time 11805675731 ps
CPU time 120.49 seconds
Started Jul 01 04:27:06 PM PDT 24
Finished Jul 01 04:29:21 PM PDT 24
Peak memory 215296 kb
Host smart-ce5b68fa-1509-42a3-97aa-28d9770ead97
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081077725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.4081077725
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.658057175
Short name T98
Test name
Test status
Simulation time 15375935436 ps
CPU time 28.2 seconds
Started Jul 01 04:26:59 PM PDT 24
Finished Jul 01 04:27:40 PM PDT 24
Peak memory 212624 kb
Host smart-a9096957-2e3e-4e45-a713-9f04611e68b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658057175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.658057175
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1833337460
Short name T380
Test name
Test status
Simulation time 16758935999 ps
CPU time 36.96 seconds
Started Jul 01 04:26:58 PM PDT 24
Finished Jul 01 04:27:46 PM PDT 24
Peak memory 217716 kb
Host smart-932cce33-b9db-460c-898a-826142161068
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833337460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1833337460
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3812565717
Short name T362
Test name
Test status
Simulation time 2328546903 ps
CPU time 23.3 seconds
Started Jul 01 04:26:51 PM PDT 24
Finished Jul 01 04:27:25 PM PDT 24
Peak memory 217128 kb
Host smart-0750b157-686a-48a5-ab14-5f57399a29a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812565717 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3812565717
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1980090089
Short name T392
Test name
Test status
Simulation time 5126248778 ps
CPU time 14.15 seconds
Started Jul 01 04:26:56 PM PDT 24
Finished Jul 01 04:27:22 PM PDT 24
Peak memory 210960 kb
Host smart-ad3779ff-3d8f-4661-8c46-abf184ee36f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980090089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1980090089
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4122401114
Short name T80
Test name
Test status
Simulation time 1039813846 ps
CPU time 43.41 seconds
Started Jul 01 04:27:08 PM PDT 24
Finished Jul 01 04:28:07 PM PDT 24
Peak memory 213832 kb
Host smart-1b559925-72b0-4002-ac0b-c0ab8ec3356a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122401114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.4122401114
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2222375098
Short name T394
Test name
Test status
Simulation time 3455284792 ps
CPU time 27.39 seconds
Started Jul 01 04:27:04 PM PDT 24
Finished Jul 01 04:27:44 PM PDT 24
Peak memory 211912 kb
Host smart-de8c7e30-55f9-48d5-b3a2-04ac2a963dfe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222375098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2222375098
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3819779908
Short name T441
Test name
Test status
Simulation time 16973773499 ps
CPU time 37.89 seconds
Started Jul 01 04:27:43 PM PDT 24
Finished Jul 01 04:28:30 PM PDT 24
Peak memory 218568 kb
Host smart-b2dfbab3-036d-4af7-a02a-319c7dbdce32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819779908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3819779908
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3213927249
Short name T114
Test name
Test status
Simulation time 12353474813 ps
CPU time 170.85 seconds
Started Jul 01 04:27:04 PM PDT 24
Finished Jul 01 04:30:08 PM PDT 24
Peak memory 214372 kb
Host smart-6c050290-cd1c-4c03-9e76-767181f8fe91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213927249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3213927249
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2142970257
Short name T396
Test name
Test status
Simulation time 1707149782 ps
CPU time 19.52 seconds
Started Jul 01 04:26:57 PM PDT 24
Finished Jul 01 04:27:29 PM PDT 24
Peak memory 218368 kb
Host smart-769873e1-bfe7-48be-8393-f62e7d73b1eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142970257 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2142970257
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.328491326
Short name T67
Test name
Test status
Simulation time 1498767963 ps
CPU time 10.56 seconds
Started Jul 01 04:26:57 PM PDT 24
Finished Jul 01 04:27:20 PM PDT 24
Peak memory 211164 kb
Host smart-d63e897c-d29e-44d5-b099-acd9fd7782b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328491326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.328491326
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1080271204
Short name T381
Test name
Test status
Simulation time 12461285037 ps
CPU time 108.33 seconds
Started Jul 01 04:27:11 PM PDT 24
Finished Jul 01 04:29:14 PM PDT 24
Peak memory 213776 kb
Host smart-a4b43f5b-54e1-4da5-8b90-f2a8ae7a3ffe
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080271204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1080271204
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.276656319
Short name T75
Test name
Test status
Simulation time 8837493302 ps
CPU time 25.76 seconds
Started Jul 01 04:27:02 PM PDT 24
Finished Jul 01 04:27:40 PM PDT 24
Peak memory 211432 kb
Host smart-c9ff8221-0351-4c30-b5ae-6213eb1dc022
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276656319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.276656319
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.489641965
Short name T386
Test name
Test status
Simulation time 13670194840 ps
CPU time 31.25 seconds
Started Jul 01 04:27:02 PM PDT 24
Finished Jul 01 04:27:45 PM PDT 24
Peak memory 218620 kb
Host smart-9bc80f7c-22af-440e-beab-220a453c699c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489641965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.489641965
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1395144005
Short name T106
Test name
Test status
Simulation time 4547562755 ps
CPU time 104.66 seconds
Started Jul 01 04:26:59 PM PDT 24
Finished Jul 01 04:28:56 PM PDT 24
Peak memory 212732 kb
Host smart-02401f6d-fb25-42d4-8a37-e3eefec80352
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395144005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1395144005
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.4188593500
Short name T379
Test name
Test status
Simulation time 16318113825 ps
CPU time 32.81 seconds
Started Jul 01 04:27:08 PM PDT 24
Finished Jul 01 04:27:55 PM PDT 24
Peak memory 217636 kb
Host smart-5105fc1b-7465-46bc-ace9-a22ae4252360
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188593500 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.4188593500
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1295863120
Short name T90
Test name
Test status
Simulation time 167564360 ps
CPU time 8.42 seconds
Started Jul 01 04:26:57 PM PDT 24
Finished Jul 01 04:27:18 PM PDT 24
Peak memory 210776 kb
Host smart-72eea696-05fc-4678-9306-544edf79c75e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295863120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1295863120
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.207214250
Short name T428
Test name
Test status
Simulation time 1056594335 ps
CPU time 56.8 seconds
Started Jul 01 04:27:13 PM PDT 24
Finished Jul 01 04:28:24 PM PDT 24
Peak memory 214760 kb
Host smart-404f8332-2e93-40c9-ade7-19e5042624ce
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207214250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.207214250
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1197854749
Short name T78
Test name
Test status
Simulation time 3442805557 ps
CPU time 29.02 seconds
Started Jul 01 04:27:00 PM PDT 24
Finished Jul 01 04:27:42 PM PDT 24
Peak memory 212460 kb
Host smart-6241f35a-11f0-495a-922e-9dc45c5e0c9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197854749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1197854749
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1951566183
Short name T390
Test name
Test status
Simulation time 6409638144 ps
CPU time 23.87 seconds
Started Jul 01 04:26:53 PM PDT 24
Finished Jul 01 04:27:28 PM PDT 24
Peak memory 218668 kb
Host smart-922a853d-3c92-4cf2-8dee-0492b6480b2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951566183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1951566183
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2333849039
Short name T438
Test name
Test status
Simulation time 950921591 ps
CPU time 81.35 seconds
Started Jul 01 04:27:02 PM PDT 24
Finished Jul 01 04:28:35 PM PDT 24
Peak memory 213560 kb
Host smart-189512ec-b19d-44a7-9dcb-b1bab3c9c72f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333849039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2333849039
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3596501108
Short name T377
Test name
Test status
Simulation time 174254568 ps
CPU time 7.93 seconds
Started Jul 01 04:26:41 PM PDT 24
Finished Jul 01 04:26:56 PM PDT 24
Peak memory 210532 kb
Host smart-310f9137-732f-4dc7-a352-b37b62752e82
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596501108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3596501108
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.69153085
Short name T357
Test name
Test status
Simulation time 660987476 ps
CPU time 8.28 seconds
Started Jul 01 04:26:52 PM PDT 24
Finished Jul 01 04:27:11 PM PDT 24
Peak memory 210596 kb
Host smart-02b9a25a-d2dd-42ab-89aa-ba5c1ef6488e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69153085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_ba
sh.69153085
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.604858872
Short name T435
Test name
Test status
Simulation time 9149852366 ps
CPU time 25.25 seconds
Started Jul 01 04:26:42 PM PDT 24
Finished Jul 01 04:27:15 PM PDT 24
Peak memory 210624 kb
Host smart-e0a16c78-f749-4891-b2df-e5611cd8a2c5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604858872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.604858872
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1798263181
Short name T402
Test name
Test status
Simulation time 3156863121 ps
CPU time 25.84 seconds
Started Jul 01 04:26:38 PM PDT 24
Finished Jul 01 04:27:11 PM PDT 24
Peak memory 216052 kb
Host smart-f2a1bdfe-1ef2-4d2b-b202-09c7b7804348
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798263181 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1798263181
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1539879967
Short name T387
Test name
Test status
Simulation time 8854867146 ps
CPU time 22.47 seconds
Started Jul 01 04:26:41 PM PDT 24
Finished Jul 01 04:27:11 PM PDT 24
Peak memory 210952 kb
Host smart-20cfe4f1-d0d0-4e9b-9043-a434b24dca79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539879967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1539879967
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.849850851
Short name T376
Test name
Test status
Simulation time 4268573080 ps
CPU time 32.83 seconds
Started Jul 01 04:26:48 PM PDT 24
Finished Jul 01 04:27:31 PM PDT 24
Peak memory 210536 kb
Host smart-0ffc8962-8684-450e-b796-152662d31d93
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849850851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.849850851
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3818085042
Short name T416
Test name
Test status
Simulation time 6603023433 ps
CPU time 26.65 seconds
Started Jul 01 04:26:53 PM PDT 24
Finished Jul 01 04:27:30 PM PDT 24
Peak memory 210524 kb
Host smart-8d613171-8cdc-4daf-b41b-9e36a27c6c08
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818085042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3818085042
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3857989384
Short name T101
Test name
Test status
Simulation time 28176975173 ps
CPU time 186.57 seconds
Started Jul 01 04:26:34 PM PDT 24
Finished Jul 01 04:29:48 PM PDT 24
Peak memory 214892 kb
Host smart-948f4f95-b934-4b72-90d2-44eb64d98952
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857989384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3857989384
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2712881541
Short name T399
Test name
Test status
Simulation time 3517735376 ps
CPU time 27.45 seconds
Started Jul 01 04:26:48 PM PDT 24
Finished Jul 01 04:27:25 PM PDT 24
Peak memory 212132 kb
Host smart-1526b519-111c-476f-bb73-aa193376f1a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712881541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2712881541
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.54634273
Short name T366
Test name
Test status
Simulation time 1004476935 ps
CPU time 17.33 seconds
Started Jul 01 04:26:37 PM PDT 24
Finished Jul 01 04:27:02 PM PDT 24
Peak memory 217036 kb
Host smart-a59f6a79-99ed-4f84-b06a-ca25f6ec1968
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54634273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.54634273
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3211287933
Short name T77
Test name
Test status
Simulation time 1085481589 ps
CPU time 15.26 seconds
Started Jul 01 04:26:36 PM PDT 24
Finished Jul 01 04:26:58 PM PDT 24
Peak memory 211316 kb
Host smart-fd71ab64-06e4-490c-84c9-3da0dc25c54a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211287933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3211287933
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3194724735
Short name T400
Test name
Test status
Simulation time 6239895676 ps
CPU time 18.2 seconds
Started Jul 01 04:26:36 PM PDT 24
Finished Jul 01 04:27:02 PM PDT 24
Peak memory 211896 kb
Host smart-cb8fd68d-b76b-4607-96aa-9c674971b666
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194724735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3194724735
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2984828545
Short name T423
Test name
Test status
Simulation time 3952720436 ps
CPU time 33.95 seconds
Started Jul 01 04:26:39 PM PDT 24
Finished Jul 01 04:27:20 PM PDT 24
Peak memory 211304 kb
Host smart-8c1c0517-77b2-42af-aa2e-0e3fe4a14a5d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984828545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2984828545
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1380900260
Short name T413
Test name
Test status
Simulation time 4818687184 ps
CPU time 16.15 seconds
Started Jul 01 04:27:12 PM PDT 24
Finished Jul 01 04:27:42 PM PDT 24
Peak memory 218184 kb
Host smart-abaf6870-4b11-43ed-b559-03cc63ad1009
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380900260 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1380900260
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3003061133
Short name T446
Test name
Test status
Simulation time 668580864 ps
CPU time 12.72 seconds
Started Jul 01 04:26:51 PM PDT 24
Finished Jul 01 04:27:14 PM PDT 24
Peak memory 211336 kb
Host smart-1a2ccfaa-bcc0-481b-bcab-9f59d9e4583d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003061133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3003061133
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3069458362
Short name T365
Test name
Test status
Simulation time 13792153565 ps
CPU time 28.67 seconds
Started Jul 01 04:26:47 PM PDT 24
Finished Jul 01 04:27:25 PM PDT 24
Peak memory 210548 kb
Host smart-8ba6ceaf-96eb-473b-a7f9-f673fe0812a3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069458362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3069458362
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1148993942
Short name T419
Test name
Test status
Simulation time 2645360106 ps
CPU time 24.72 seconds
Started Jul 01 04:27:03 PM PDT 24
Finished Jul 01 04:27:42 PM PDT 24
Peak memory 210712 kb
Host smart-ecf6f58c-c390-4dc6-b474-6dc6a812e98c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148993942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1148993942
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.171909036
Short name T81
Test name
Test status
Simulation time 87226663420 ps
CPU time 157.19 seconds
Started Jul 01 04:26:41 PM PDT 24
Finished Jul 01 04:29:26 PM PDT 24
Peak memory 214780 kb
Host smart-f2c65409-8a6e-44b4-986d-518eb926d876
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171909036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.171909036
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.859153294
Short name T99
Test name
Test status
Simulation time 2495416022 ps
CPU time 25.81 seconds
Started Jul 01 04:26:58 PM PDT 24
Finished Jul 01 04:27:35 PM PDT 24
Peak memory 212304 kb
Host smart-d325b2a8-73e3-4f9b-a521-1cb315357212
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859153294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.859153294
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2420253297
Short name T391
Test name
Test status
Simulation time 1398801780 ps
CPU time 15.45 seconds
Started Jul 01 04:26:48 PM PDT 24
Finished Jul 01 04:27:13 PM PDT 24
Peak memory 218276 kb
Host smart-a786bde8-5689-42dd-b950-c5d5fbd81c3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420253297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2420253297
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2151867529
Short name T117
Test name
Test status
Simulation time 16894941430 ps
CPU time 168.09 seconds
Started Jul 01 04:26:35 PM PDT 24
Finished Jul 01 04:29:31 PM PDT 24
Peak memory 214012 kb
Host smart-5efae803-0fed-45e9-98b0-3b037c026c8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151867529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2151867529
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1606720098
Short name T372
Test name
Test status
Simulation time 17102648932 ps
CPU time 32.42 seconds
Started Jul 01 04:26:57 PM PDT 24
Finished Jul 01 04:27:41 PM PDT 24
Peak memory 212332 kb
Host smart-a22c9d32-c130-40f8-b377-4ecc0fb55fd0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606720098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1606720098
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3189995331
Short name T414
Test name
Test status
Simulation time 11729177716 ps
CPU time 24.18 seconds
Started Jul 01 04:26:40 PM PDT 24
Finished Jul 01 04:27:11 PM PDT 24
Peak memory 211808 kb
Host smart-96fae883-6b83-4973-bfb5-3a30f5deeffa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189995331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3189995331
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.901764323
Short name T425
Test name
Test status
Simulation time 5430330614 ps
CPU time 31.68 seconds
Started Jul 01 04:27:00 PM PDT 24
Finished Jul 01 04:27:44 PM PDT 24
Peak memory 211772 kb
Host smart-3e6f67c8-5868-4eb5-bdf1-b39874d468fe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901764323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.901764323
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3186930753
Short name T443
Test name
Test status
Simulation time 1386795389 ps
CPU time 16.84 seconds
Started Jul 01 04:26:57 PM PDT 24
Finished Jul 01 04:27:26 PM PDT 24
Peak memory 215992 kb
Host smart-c50a8271-30ee-43b9-a423-7615ad7eff4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186930753 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3186930753
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2244271294
Short name T398
Test name
Test status
Simulation time 12448705374 ps
CPU time 26.75 seconds
Started Jul 01 04:26:57 PM PDT 24
Finished Jul 01 04:27:36 PM PDT 24
Peak memory 211952 kb
Host smart-ca62e044-dad9-42bb-a1cf-fcbbf8030edb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244271294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2244271294
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2992296992
Short name T417
Test name
Test status
Simulation time 688719018 ps
CPU time 8.48 seconds
Started Jul 01 04:26:48 PM PDT 24
Finished Jul 01 04:27:06 PM PDT 24
Peak memory 210648 kb
Host smart-8d4fd739-f6ae-47b0-9703-2d52224dd085
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992296992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2992296992
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1097834274
Short name T363
Test name
Test status
Simulation time 32811282549 ps
CPU time 31.35 seconds
Started Jul 01 04:26:54 PM PDT 24
Finished Jul 01 04:27:36 PM PDT 24
Peak memory 210524 kb
Host smart-ac6e3698-4059-476b-adae-fa952ab508a3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097834274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1097834274
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2086630727
Short name T76
Test name
Test status
Simulation time 2153931034 ps
CPU time 56.43 seconds
Started Jul 01 04:26:52 PM PDT 24
Finished Jul 01 04:27:59 PM PDT 24
Peak memory 213728 kb
Host smart-f87571a9-658a-4db1-8fd8-e58d93077e6e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086630727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2086630727
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1193505813
Short name T433
Test name
Test status
Simulation time 394351044 ps
CPU time 8.34 seconds
Started Jul 01 04:26:48 PM PDT 24
Finished Jul 01 04:27:05 PM PDT 24
Peak memory 211092 kb
Host smart-08c08479-ff52-4147-8474-5dd10ae9f3f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193505813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1193505813
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2564788344
Short name T430
Test name
Test status
Simulation time 660965323 ps
CPU time 12.84 seconds
Started Jul 01 04:26:57 PM PDT 24
Finished Jul 01 04:27:21 PM PDT 24
Peak memory 217268 kb
Host smart-5c4266d1-7677-4425-93c3-17a637b50793
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564788344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2564788344
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.722458311
Short name T110
Test name
Test status
Simulation time 1226530442 ps
CPU time 151.07 seconds
Started Jul 01 04:26:54 PM PDT 24
Finished Jul 01 04:29:36 PM PDT 24
Peak memory 213992 kb
Host smart-75d737ab-1e6f-4a3f-afe1-ed36a7097b7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722458311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.722458311
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.548932857
Short name T406
Test name
Test status
Simulation time 11335196790 ps
CPU time 29.94 seconds
Started Jul 01 04:26:48 PM PDT 24
Finished Jul 01 04:27:28 PM PDT 24
Peak memory 215880 kb
Host smart-b95f9ff0-be5e-4ef4-a474-e0656af211d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548932857 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.548932857
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1155706593
Short name T92
Test name
Test status
Simulation time 2148845852 ps
CPU time 20.96 seconds
Started Jul 01 04:26:44 PM PDT 24
Finished Jul 01 04:27:13 PM PDT 24
Peak memory 211696 kb
Host smart-fe291813-3845-4963-91f9-79af3ae80327
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155706593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1155706593
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3194256794
Short name T434
Test name
Test status
Simulation time 67454109289 ps
CPU time 115.12 seconds
Started Jul 01 04:26:41 PM PDT 24
Finished Jul 01 04:28:43 PM PDT 24
Peak memory 213736 kb
Host smart-1580cc95-3e97-4a3c-be2f-64cc3d1952a5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194256794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3194256794
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3901826194
Short name T397
Test name
Test status
Simulation time 15729683381 ps
CPU time 30.23 seconds
Started Jul 01 04:26:37 PM PDT 24
Finished Jul 01 04:27:15 PM PDT 24
Peak memory 212936 kb
Host smart-fde1f839-f72d-4add-91ad-f01e3756d543
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901826194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3901826194
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2789372009
Short name T385
Test name
Test status
Simulation time 7865187863 ps
CPU time 37.69 seconds
Started Jul 01 04:26:58 PM PDT 24
Finished Jul 01 04:27:54 PM PDT 24
Peak memory 217652 kb
Host smart-f6402f03-c5d1-4c6a-88b0-d1fd110adc80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789372009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2789372009
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4025963396
Short name T111
Test name
Test status
Simulation time 2779655308 ps
CPU time 165.1 seconds
Started Jul 01 04:26:37 PM PDT 24
Finished Jul 01 04:29:29 PM PDT 24
Peak memory 213884 kb
Host smart-ac25bce2-0862-4678-9d68-fce91ffadc49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025963396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.4025963396
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.4275705428
Short name T359
Test name
Test status
Simulation time 3363238532 ps
CPU time 28.27 seconds
Started Jul 01 04:26:44 PM PDT 24
Finished Jul 01 04:27:20 PM PDT 24
Peak memory 216520 kb
Host smart-5c441eca-43f2-4560-8605-415e96ba68d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275705428 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.4275705428
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2582895470
Short name T74
Test name
Test status
Simulation time 11382753880 ps
CPU time 25.05 seconds
Started Jul 01 04:26:49 PM PDT 24
Finished Jul 01 04:27:25 PM PDT 24
Peak memory 212116 kb
Host smart-991adafa-22c5-486a-b2c9-ac697ec1258e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582895470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2582895470
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3261945168
Short name T409
Test name
Test status
Simulation time 31175576624 ps
CPU time 146.31 seconds
Started Jul 01 04:26:59 PM PDT 24
Finished Jul 01 04:29:38 PM PDT 24
Peak memory 215204 kb
Host smart-b3929425-aaff-420b-b455-1a7612d341a6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261945168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3261945168
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1594054134
Short name T97
Test name
Test status
Simulation time 4106651078 ps
CPU time 29.8 seconds
Started Jul 01 04:26:41 PM PDT 24
Finished Jul 01 04:27:18 PM PDT 24
Peak memory 212324 kb
Host smart-b2374ba8-6abc-46bc-9893-ea185ed052a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594054134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1594054134
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2933778149
Short name T444
Test name
Test status
Simulation time 660923643 ps
CPU time 12.24 seconds
Started Jul 01 04:26:44 PM PDT 24
Finished Jul 01 04:27:05 PM PDT 24
Peak memory 217280 kb
Host smart-fc3caa0e-b86a-45ac-b2a3-604bcfcafd9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933778149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2933778149
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.953100175
Short name T64
Test name
Test status
Simulation time 4048449658 ps
CPU time 102.75 seconds
Started Jul 01 04:26:49 PM PDT 24
Finished Jul 01 04:28:42 PM PDT 24
Peak memory 213456 kb
Host smart-51015650-26bf-42a4-a7ad-bcd84a8ea016
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953100175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.953100175
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4216398983
Short name T383
Test name
Test status
Simulation time 6416869493 ps
CPU time 27.12 seconds
Started Jul 01 04:26:53 PM PDT 24
Finished Jul 01 04:27:31 PM PDT 24
Peak memory 217844 kb
Host smart-f7e0ce9b-f16a-4878-b8c9-9b3675e5c9d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216398983 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.4216398983
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1743758206
Short name T440
Test name
Test status
Simulation time 3803396318 ps
CPU time 30.19 seconds
Started Jul 01 04:26:46 PM PDT 24
Finished Jul 01 04:27:25 PM PDT 24
Peak memory 211748 kb
Host smart-4692d373-07d9-4741-9929-b4f26201bfd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743758206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1743758206
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1414814384
Short name T448
Test name
Test status
Simulation time 8176492082 ps
CPU time 21.23 seconds
Started Jul 01 04:26:46 PM PDT 24
Finished Jul 01 04:27:16 PM PDT 24
Peak memory 212484 kb
Host smart-52b13271-77d6-42d1-a07e-c58c78afccc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414814384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1414814384
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2326953046
Short name T401
Test name
Test status
Simulation time 36104822702 ps
CPU time 29.89 seconds
Started Jul 01 04:26:42 PM PDT 24
Finished Jul 01 04:27:20 PM PDT 24
Peak memory 218732 kb
Host smart-7e626b49-9ab0-47ad-ac29-bbab5f75be11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326953046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2326953046
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3862385995
Short name T113
Test name
Test status
Simulation time 3973250591 ps
CPU time 102.28 seconds
Started Jul 01 04:26:42 PM PDT 24
Finished Jul 01 04:28:32 PM PDT 24
Peak memory 213504 kb
Host smart-93a4e30b-7d25-4efc-aee0-4f4fb4ae4309
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862385995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3862385995
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1173360314
Short name T73
Test name
Test status
Simulation time 2067499901 ps
CPU time 21.23 seconds
Started Jul 01 04:26:37 PM PDT 24
Finished Jul 01 04:27:06 PM PDT 24
Peak memory 215136 kb
Host smart-3a95dea0-3717-4f08-8f6d-0f1c1f4ca11d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173360314 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1173360314
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3261559707
Short name T442
Test name
Test status
Simulation time 825791658 ps
CPU time 8.28 seconds
Started Jul 01 04:26:51 PM PDT 24
Finished Jul 01 04:27:10 PM PDT 24
Peak memory 210596 kb
Host smart-e5331657-1d5f-4a27-a4d4-81b6134c7e12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261559707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3261559707
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2434252440
Short name T407
Test name
Test status
Simulation time 1041911051 ps
CPU time 55.4 seconds
Started Jul 01 04:26:55 PM PDT 24
Finished Jul 01 04:28:02 PM PDT 24
Peak memory 213728 kb
Host smart-115d497b-847c-4c83-8b9d-3fa206e33375
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434252440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2434252440
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.941317318
Short name T451
Test name
Test status
Simulation time 4707603955 ps
CPU time 31.65 seconds
Started Jul 01 04:26:43 PM PDT 24
Finished Jul 01 04:27:22 PM PDT 24
Peak memory 212384 kb
Host smart-44f801f2-3d71-40c2-bdd8-2bcfbf770907
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941317318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.941317318
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1002337966
Short name T368
Test name
Test status
Simulation time 8927339961 ps
CPU time 23.95 seconds
Started Jul 01 04:27:02 PM PDT 24
Finished Jul 01 04:27:39 PM PDT 24
Peak memory 217244 kb
Host smart-65fb2796-a845-4358-9acf-6d4991a1f1a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002337966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1002337966
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4198097378
Short name T105
Test name
Test status
Simulation time 916248710 ps
CPU time 82.55 seconds
Started Jul 01 04:27:04 PM PDT 24
Finished Jul 01 04:28:40 PM PDT 24
Peak memory 213656 kb
Host smart-51cdbe74-0590-47fc-b58e-a78b0707bf8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198097378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.4198097378
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.4126003885
Short name T432
Test name
Test status
Simulation time 198587209 ps
CPU time 9.33 seconds
Started Jul 01 04:26:53 PM PDT 24
Finished Jul 01 04:27:13 PM PDT 24
Peak memory 216760 kb
Host smart-14849580-90ae-43be-b81f-81341a7e3287
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126003885 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.4126003885
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3587353340
Short name T95
Test name
Test status
Simulation time 926502271 ps
CPU time 14.23 seconds
Started Jul 01 04:26:50 PM PDT 24
Finished Jul 01 04:27:15 PM PDT 24
Peak memory 210588 kb
Host smart-56c5a797-60aa-428d-aea4-ae471b97911f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587353340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3587353340
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.86039364
Short name T437
Test name
Test status
Simulation time 15950384952 ps
CPU time 149.8 seconds
Started Jul 01 04:26:55 PM PDT 24
Finished Jul 01 04:29:37 PM PDT 24
Peak memory 215536 kb
Host smart-e2ceba08-efbb-4826-a8af-c9eaef50bf20
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86039364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pass
thru_mem_tl_intg_err.86039364
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.791715958
Short name T420
Test name
Test status
Simulation time 680027179 ps
CPU time 14.03 seconds
Started Jul 01 04:26:54 PM PDT 24
Finished Jul 01 04:27:19 PM PDT 24
Peak memory 212100 kb
Host smart-1ee922c7-7adb-4e21-92f0-f230cf44d394
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791715958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.791715958
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3780220156
Short name T367
Test name
Test status
Simulation time 2740706092 ps
CPU time 25.68 seconds
Started Jul 01 04:26:48 PM PDT 24
Finished Jul 01 04:27:23 PM PDT 24
Peak memory 218020 kb
Host smart-81b78012-905b-46d1-bf82-6ebd75c8d5b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780220156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3780220156
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3168370523
Short name T116
Test name
Test status
Simulation time 499265453 ps
CPU time 154.24 seconds
Started Jul 01 04:26:48 PM PDT 24
Finished Jul 01 04:29:32 PM PDT 24
Peak memory 213840 kb
Host smart-f78de166-b763-4106-9a88-72ad41813137
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168370523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3168370523
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.663470733
Short name T225
Test name
Test status
Simulation time 4198248679 ps
CPU time 34.54 seconds
Started Jul 01 04:29:08 PM PDT 24
Finished Jul 01 04:29:53 PM PDT 24
Peak memory 217360 kb
Host smart-a79a1928-6d18-49aa-8dbb-85df84fb5fc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663470733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.663470733
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1669945351
Short name T232
Test name
Test status
Simulation time 11625404069 ps
CPU time 202.76 seconds
Started Jul 01 04:29:09 PM PDT 24
Finished Jul 01 04:32:41 PM PDT 24
Peak memory 237072 kb
Host smart-4b547913-d31b-4382-a581-4d1c3abb25b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669945351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1669945351
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.4078671914
Short name T171
Test name
Test status
Simulation time 5359960198 ps
CPU time 33.99 seconds
Started Jul 01 04:29:43 PM PDT 24
Finished Jul 01 04:30:28 PM PDT 24
Peak memory 219312 kb
Host smart-d964bcae-e870-490d-84e4-df0a4aadee63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078671914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.4078671914
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2093993299
Short name T23
Test name
Test status
Simulation time 4624946711 ps
CPU time 23.42 seconds
Started Jul 01 04:29:40 PM PDT 24
Finished Jul 01 04:30:11 PM PDT 24
Peak memory 211960 kb
Host smart-5d7cc9c7-4edf-4fd4-8c65-c8089489635f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2093993299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2093993299
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2648037409
Short name T30
Test name
Test status
Simulation time 1180510250 ps
CPU time 228.04 seconds
Started Jul 01 04:29:10 PM PDT 24
Finished Jul 01 04:33:07 PM PDT 24
Peak memory 238308 kb
Host smart-6ebf9c9f-1601-4df2-8e69-3be4f72203dd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648037409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2648037409
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3901396988
Short name T140
Test name
Test status
Simulation time 357305687 ps
CPU time 20.88 seconds
Started Jul 01 04:29:09 PM PDT 24
Finished Jul 01 04:29:39 PM PDT 24
Peak memory 216160 kb
Host smart-a3b2f435-94e1-4696-bba6-08cde010e9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901396988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3901396988
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3267129221
Short name T271
Test name
Test status
Simulation time 12183536633 ps
CPU time 71.35 seconds
Started Jul 01 04:29:04 PM PDT 24
Finished Jul 01 04:30:26 PM PDT 24
Peak memory 218128 kb
Host smart-6771634a-e877-4238-8679-3bb63ff4f2a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267129221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3267129221
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.97968150
Short name T265
Test name
Test status
Simulation time 3991094114 ps
CPU time 31.04 seconds
Started Jul 01 04:29:28 PM PDT 24
Finished Jul 01 04:30:05 PM PDT 24
Peak memory 213356 kb
Host smart-a7340c79-6d3e-4236-a22c-885001742aea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97968150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.97968150
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2116131929
Short name T248
Test name
Test status
Simulation time 530882720693 ps
CPU time 857.42 seconds
Started Jul 01 04:29:18 PM PDT 24
Finished Jul 01 04:43:45 PM PDT 24
Peak memory 225012 kb
Host smart-b4803b57-7ec1-498b-8ac2-38a4c6714049
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116131929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2116131929
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3292556569
Short name T342
Test name
Test status
Simulation time 38989287261 ps
CPU time 52.91 seconds
Started Jul 01 04:29:19 PM PDT 24
Finished Jul 01 04:30:21 PM PDT 24
Peak memory 219376 kb
Host smart-ddf46d6a-a969-45cf-83ea-c3dbce346b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292556569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3292556569
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2190073185
Short name T325
Test name
Test status
Simulation time 319992090 ps
CPU time 10.6 seconds
Started Jul 01 04:28:56 PM PDT 24
Finished Jul 01 04:29:20 PM PDT 24
Peak memory 219216 kb
Host smart-6d979de8-d542-40ed-baa4-6f4acc41a944
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2190073185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2190073185
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1405294119
Short name T29
Test name
Test status
Simulation time 16420214266 ps
CPU time 251.64 seconds
Started Jul 01 04:29:07 PM PDT 24
Finished Jul 01 04:33:29 PM PDT 24
Peak memory 238348 kb
Host smart-ff4ac96d-3f62-45e7-a340-e75d71b312a2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405294119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1405294119
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1118543277
Short name T7
Test name
Test status
Simulation time 8914481882 ps
CPU time 35.41 seconds
Started Jul 01 04:29:04 PM PDT 24
Finished Jul 01 04:29:51 PM PDT 24
Peak memory 215504 kb
Host smart-bfa6660f-7c67-496f-9079-80e10ec01e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118543277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1118543277
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1852028941
Short name T339
Test name
Test status
Simulation time 29600448879 ps
CPU time 107.64 seconds
Started Jul 01 04:29:21 PM PDT 24
Finished Jul 01 04:31:17 PM PDT 24
Peak memory 220572 kb
Host smart-67c5578b-729f-4012-8df9-c79ccde00c49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852028941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1852028941
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2689543212
Short name T229
Test name
Test status
Simulation time 16116723240 ps
CPU time 30.19 seconds
Started Jul 01 04:29:19 PM PDT 24
Finished Jul 01 04:29:58 PM PDT 24
Peak memory 213380 kb
Host smart-331e48c3-b282-48e0-8e41-370c359c7f95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689543212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2689543212
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1350035356
Short name T180
Test name
Test status
Simulation time 15456577539 ps
CPU time 17.87 seconds
Started Jul 01 04:29:29 PM PDT 24
Finished Jul 01 04:29:53 PM PDT 24
Peak memory 211848 kb
Host smart-846852ca-235c-40ed-b5ca-528336047fc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1350035356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1350035356
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3425828423
Short name T258
Test name
Test status
Simulation time 3291960997 ps
CPU time 44.99 seconds
Started Jul 01 04:29:20 PM PDT 24
Finished Jul 01 04:30:13 PM PDT 24
Peak memory 217248 kb
Host smart-2ee77fc9-b5f8-449e-98da-3cfc758c1d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425828423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3425828423
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3103770321
Short name T301
Test name
Test status
Simulation time 16251214917 ps
CPU time 88.43 seconds
Started Jul 01 04:29:30 PM PDT 24
Finished Jul 01 04:31:04 PM PDT 24
Peak memory 218048 kb
Host smart-8eae37ad-988a-4cdd-96e0-f9202d92eed1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103770321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3103770321
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.297564768
Short name T2
Test name
Test status
Simulation time 13731718240 ps
CPU time 24.05 seconds
Started Jul 01 04:29:32 PM PDT 24
Finished Jul 01 04:30:02 PM PDT 24
Peak memory 217632 kb
Host smart-43c1a067-9ba5-4826-ac02-6035e9d23fd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297564768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.297564768
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1251115109
Short name T231
Test name
Test status
Simulation time 157968924180 ps
CPU time 631.86 seconds
Started Jul 01 04:29:43 PM PDT 24
Finished Jul 01 04:40:25 PM PDT 24
Peak memory 235904 kb
Host smart-a529b914-b7b8-44c7-84e6-7da2acbaea2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251115109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1251115109
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.494936344
Short name T211
Test name
Test status
Simulation time 184099826 ps
CPU time 10.61 seconds
Started Jul 01 04:29:38 PM PDT 24
Finished Jul 01 04:29:55 PM PDT 24
Peak memory 219360 kb
Host smart-5c9dd582-911f-490a-ac5c-50a81f36cb1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=494936344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.494936344
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.638597187
Short name T239
Test name
Test status
Simulation time 4119098165 ps
CPU time 34.77 seconds
Started Jul 01 04:29:30 PM PDT 24
Finished Jul 01 04:30:11 PM PDT 24
Peak memory 216600 kb
Host smart-035f459c-3b6e-4b81-86f1-4888b1646d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638597187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.638597187
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.26054457
Short name T205
Test name
Test status
Simulation time 6619250832 ps
CPU time 27.45 seconds
Started Jul 01 04:29:17 PM PDT 24
Finished Jul 01 04:29:54 PM PDT 24
Peak memory 217364 kb
Host smart-8956031a-dedd-4820-96cc-c247d62a3303
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26054457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.26054457
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3450866186
Short name T317
Test name
Test status
Simulation time 3774170042 ps
CPU time 243.64 seconds
Started Jul 01 04:29:31 PM PDT 24
Finished Jul 01 04:33:40 PM PDT 24
Peak memory 226748 kb
Host smart-cd769dc0-33bf-443a-b62b-4a3a680ffd81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450866186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3450866186
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2263354993
Short name T346
Test name
Test status
Simulation time 2999605873 ps
CPU time 18.84 seconds
Started Jul 01 04:29:26 PM PDT 24
Finished Jul 01 04:29:52 PM PDT 24
Peak memory 219276 kb
Host smart-c311855f-2d35-4f37-b768-66f753ade410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263354993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2263354993
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.938303189
Short name T307
Test name
Test status
Simulation time 22746214623 ps
CPU time 30.98 seconds
Started Jul 01 04:29:37 PM PDT 24
Finished Jul 01 04:30:13 PM PDT 24
Peak memory 212024 kb
Host smart-bf1c8c84-f157-49d3-8838-8e39c4c17a7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=938303189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.938303189
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1998500965
Short name T141
Test name
Test status
Simulation time 20430605376 ps
CPU time 119.17 seconds
Started Jul 01 04:29:17 PM PDT 24
Finished Jul 01 04:31:25 PM PDT 24
Peak memory 219308 kb
Host smart-cb824edf-d798-4c68-b656-9a83cd4f19e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998500965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1998500965
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.998102898
Short name T315
Test name
Test status
Simulation time 81458992744 ps
CPU time 32.52 seconds
Started Jul 01 04:29:22 PM PDT 24
Finished Jul 01 04:30:03 PM PDT 24
Peak memory 217500 kb
Host smart-21afe25b-8817-4188-b6ce-826ba9c14edd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998102898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.998102898
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3997608892
Short name T60
Test name
Test status
Simulation time 201483159953 ps
CPU time 1007.44 seconds
Started Jul 01 04:29:23 PM PDT 24
Finished Jul 01 04:46:18 PM PDT 24
Peak memory 237960 kb
Host smart-64d9f31f-ad2e-46cf-bdd0-25f13ae41f23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997608892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3997608892
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.903181877
Short name T161
Test name
Test status
Simulation time 32029426843 ps
CPU time 66.36 seconds
Started Jul 01 04:29:29 PM PDT 24
Finished Jul 01 04:30:42 PM PDT 24
Peak memory 219284 kb
Host smart-ea1fa827-6376-4216-ab8d-04bd6c94df50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903181877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.903181877
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3905504394
Short name T207
Test name
Test status
Simulation time 1414215361 ps
CPU time 19.41 seconds
Started Jul 01 04:29:41 PM PDT 24
Finished Jul 01 04:30:09 PM PDT 24
Peak memory 211208 kb
Host smart-cce27878-c6c8-4ed3-813d-c9c9b2a6cbf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3905504394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3905504394
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2124150041
Short name T273
Test name
Test status
Simulation time 22936473583 ps
CPU time 51.86 seconds
Started Jul 01 04:29:38 PM PDT 24
Finished Jul 01 04:30:36 PM PDT 24
Peak memory 218360 kb
Host smart-b40d88a6-a2de-452b-aef9-8e3e86f37749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124150041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2124150041
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.179194882
Short name T352
Test name
Test status
Simulation time 1594779843 ps
CPU time 24.43 seconds
Started Jul 01 04:29:38 PM PDT 24
Finished Jul 01 04:30:09 PM PDT 24
Peak memory 219232 kb
Host smart-693cc656-492d-4301-b3fb-6e89ebc367ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179194882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.179194882
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1076300145
Short name T220
Test name
Test status
Simulation time 3388006353 ps
CPU time 28.81 seconds
Started Jul 01 04:29:14 PM PDT 24
Finished Jul 01 04:29:52 PM PDT 24
Peak memory 217208 kb
Host smart-67c3d306-2510-4be4-8c96-ac09c3e769ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076300145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1076300145
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1480615319
Short name T139
Test name
Test status
Simulation time 106848339655 ps
CPU time 291.85 seconds
Started Jul 01 04:29:27 PM PDT 24
Finished Jul 01 04:34:26 PM PDT 24
Peak memory 237772 kb
Host smart-0e43e592-e42e-4318-8cc7-718c04390b89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480615319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1480615319
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1143616326
Short name T292
Test name
Test status
Simulation time 17768542336 ps
CPU time 45.81 seconds
Started Jul 01 04:29:34 PM PDT 24
Finished Jul 01 04:30:25 PM PDT 24
Peak memory 219216 kb
Host smart-fae5edbc-58df-44c8-9809-698105432c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143616326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1143616326
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3024573965
Short name T300
Test name
Test status
Simulation time 2225966805 ps
CPU time 22.29 seconds
Started Jul 01 04:29:19 PM PDT 24
Finished Jul 01 04:29:50 PM PDT 24
Peak memory 219268 kb
Host smart-4ff67de4-2106-480c-ad74-27842bbac441
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3024573965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3024573965
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.4076307469
Short name T85
Test name
Test status
Simulation time 688871094 ps
CPU time 20.12 seconds
Started Jul 01 04:29:40 PM PDT 24
Finished Jul 01 04:30:10 PM PDT 24
Peak memory 216080 kb
Host smart-a5b50b0b-96ac-4aab-9a76-269652eb8347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076307469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.4076307469
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2741175792
Short name T351
Test name
Test status
Simulation time 28683958137 ps
CPU time 220.37 seconds
Started Jul 01 04:29:16 PM PDT 24
Finished Jul 01 04:33:06 PM PDT 24
Peak memory 221916 kb
Host smart-facf5fc7-87ab-4324-80b2-4e224a333e55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741175792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2741175792
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2167880251
Short name T71
Test name
Test status
Simulation time 3653658570 ps
CPU time 28.97 seconds
Started Jul 01 04:29:36 PM PDT 24
Finished Jul 01 04:30:10 PM PDT 24
Peak memory 217216 kb
Host smart-9b2d9bee-c362-4a8a-b3a8-41c5d7ea17fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167880251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2167880251
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1590460092
Short name T213
Test name
Test status
Simulation time 57808229663 ps
CPU time 641.15 seconds
Started Jul 01 04:29:31 PM PDT 24
Finished Jul 01 04:40:18 PM PDT 24
Peak memory 243068 kb
Host smart-5cef7589-7380-473c-858d-8d2a2150c450
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590460092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1590460092
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1225200342
Short name T42
Test name
Test status
Simulation time 661618127 ps
CPU time 19.23 seconds
Started Jul 01 04:29:15 PM PDT 24
Finished Jul 01 04:29:43 PM PDT 24
Peak memory 219244 kb
Host smart-6e3d18d9-8a6d-4cd6-89ab-a690e318bf71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225200342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1225200342
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3604056258
Short name T217
Test name
Test status
Simulation time 4967980732 ps
CPU time 26.63 seconds
Started Jul 01 04:29:36 PM PDT 24
Finished Jul 01 04:30:08 PM PDT 24
Peak memory 219284 kb
Host smart-4baaa623-1687-4f24-90c8-2d1532013c65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3604056258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3604056258
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1884537543
Short name T151
Test name
Test status
Simulation time 12290812466 ps
CPU time 66.35 seconds
Started Jul 01 04:29:23 PM PDT 24
Finished Jul 01 04:30:37 PM PDT 24
Peak memory 216620 kb
Host smart-eea7457c-6677-4a41-bbc9-084c38bf9385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884537543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1884537543
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.168044539
Short name T331
Test name
Test status
Simulation time 8548720118 ps
CPU time 89.91 seconds
Started Jul 01 04:29:29 PM PDT 24
Finished Jul 01 04:31:05 PM PDT 24
Peak memory 219296 kb
Host smart-4fe2802e-b1a3-4ba0-a951-1e6c5d495b07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168044539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.168044539
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2578140418
Short name T269
Test name
Test status
Simulation time 4952861001 ps
CPU time 20.16 seconds
Started Jul 01 04:29:34 PM PDT 24
Finished Jul 01 04:29:59 PM PDT 24
Peak memory 217564 kb
Host smart-bbc91827-a024-47c8-9000-8c4cacb6f180
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578140418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2578140418
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.256320370
Short name T47
Test name
Test status
Simulation time 50596133488 ps
CPU time 535.07 seconds
Started Jul 01 04:29:42 PM PDT 24
Finished Jul 01 04:38:48 PM PDT 24
Peak memory 238100 kb
Host smart-ce5cc0d4-5e57-4d7d-ae09-f2bb6f5ac47a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256320370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.256320370
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.285919140
Short name T182
Test name
Test status
Simulation time 1736644701 ps
CPU time 19.32 seconds
Started Jul 01 04:29:38 PM PDT 24
Finished Jul 01 04:30:04 PM PDT 24
Peak memory 219268 kb
Host smart-3f49e8ca-c6f0-428e-b77e-ae6738bee50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285919140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.285919140
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3391978199
Short name T237
Test name
Test status
Simulation time 364505127 ps
CPU time 10.62 seconds
Started Jul 01 04:29:22 PM PDT 24
Finished Jul 01 04:29:41 PM PDT 24
Peak memory 219224 kb
Host smart-00252a03-fbcd-4358-8575-d1b6e3825063
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3391978199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3391978199
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3212261900
Short name T9
Test name
Test status
Simulation time 1379921148 ps
CPU time 19.81 seconds
Started Jul 01 04:29:25 PM PDT 24
Finished Jul 01 04:29:52 PM PDT 24
Peak memory 216204 kb
Host smart-e94033cc-dd6a-4e2b-9155-d6471a04813a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212261900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3212261900
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1476075230
Short name T143
Test name
Test status
Simulation time 13802529412 ps
CPU time 31.52 seconds
Started Jul 01 04:29:33 PM PDT 24
Finished Jul 01 04:30:10 PM PDT 24
Peak memory 216576 kb
Host smart-a1c09790-40e0-4f95-994e-e7dc986f7ed6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476075230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1476075230
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.724302233
Short name T51
Test name
Test status
Simulation time 53755572619 ps
CPU time 4908.15 seconds
Started Jul 01 04:29:31 PM PDT 24
Finished Jul 01 05:51:25 PM PDT 24
Peak memory 235760 kb
Host smart-37d79fe4-e701-45d5-a5e4-e0657bc2379e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724302233 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.724302233
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2532415550
Short name T209
Test name
Test status
Simulation time 2235497906 ps
CPU time 15.64 seconds
Started Jul 01 04:29:23 PM PDT 24
Finished Jul 01 04:29:47 PM PDT 24
Peak memory 213252 kb
Host smart-c2e4cf7a-2f6d-4d9c-89fa-565a89e47a3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532415550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2532415550
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.894727147
Short name T167
Test name
Test status
Simulation time 38553408018 ps
CPU time 320.18 seconds
Started Jul 01 04:29:24 PM PDT 24
Finished Jul 01 04:34:53 PM PDT 24
Peak memory 233772 kb
Host smart-f4fca914-77ce-49da-82ab-93dd69b1db7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894727147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.894727147
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2334604799
Short name T157
Test name
Test status
Simulation time 27884576139 ps
CPU time 51.44 seconds
Started Jul 01 04:29:46 PM PDT 24
Finished Jul 01 04:30:49 PM PDT 24
Peak memory 219180 kb
Host smart-4221064f-9a86-4062-90ce-12ab8a1f9fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334604799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2334604799
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.428862406
Short name T345
Test name
Test status
Simulation time 340637928 ps
CPU time 10.37 seconds
Started Jul 01 04:29:24 PM PDT 24
Finished Jul 01 04:29:42 PM PDT 24
Peak memory 219216 kb
Host smart-b0b4642c-23a0-4c94-a7c1-7af5b77af2dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=428862406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.428862406
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.810655069
Short name T59
Test name
Test status
Simulation time 10527282549 ps
CPU time 49.97 seconds
Started Jul 01 04:29:26 PM PDT 24
Finished Jul 01 04:30:23 PM PDT 24
Peak memory 216316 kb
Host smart-942c0366-59f6-4afe-b84f-3d94322ec9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810655069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.810655069
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2552195104
Short name T247
Test name
Test status
Simulation time 6250249411 ps
CPU time 35.86 seconds
Started Jul 01 04:29:26 PM PDT 24
Finished Jul 01 04:30:09 PM PDT 24
Peak memory 219360 kb
Host smart-bf3cd0b2-3849-4e7f-8539-98da91fc8b18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552195104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2552195104
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2473972313
Short name T137
Test name
Test status
Simulation time 1091268450 ps
CPU time 15.84 seconds
Started Jul 01 04:29:28 PM PDT 24
Finished Jul 01 04:29:50 PM PDT 24
Peak memory 217196 kb
Host smart-f59f78d8-3606-4c33-8f36-04ebf3dd0bb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473972313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2473972313
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1977117413
Short name T340
Test name
Test status
Simulation time 14691955598 ps
CPU time 176.91 seconds
Started Jul 01 04:29:35 PM PDT 24
Finished Jul 01 04:32:37 PM PDT 24
Peak memory 219456 kb
Host smart-cef38506-5f69-434e-b373-9e3e16578671
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977117413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1977117413
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.4041223950
Short name T314
Test name
Test status
Simulation time 14877012376 ps
CPU time 39.92 seconds
Started Jul 01 04:29:22 PM PDT 24
Finished Jul 01 04:30:10 PM PDT 24
Peak memory 219172 kb
Host smart-df2a9540-bac2-45df-ae1d-25adec2195ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041223950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.4041223950
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3040894813
Short name T119
Test name
Test status
Simulation time 262825540 ps
CPU time 10.45 seconds
Started Jul 01 04:29:27 PM PDT 24
Finished Jul 01 04:29:44 PM PDT 24
Peak memory 219204 kb
Host smart-494abd17-f4f6-4551-a87e-c832175fbbc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3040894813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3040894813
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.4253189370
Short name T238
Test name
Test status
Simulation time 17074250520 ps
CPU time 49.15 seconds
Started Jul 01 04:29:14 PM PDT 24
Finished Jul 01 04:30:13 PM PDT 24
Peak memory 216652 kb
Host smart-2c50c6cd-3f56-47e1-8261-94d479814ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253189370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.4253189370
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2617186387
Short name T330
Test name
Test status
Simulation time 6563022948 ps
CPU time 60.62 seconds
Started Jul 01 04:29:40 PM PDT 24
Finished Jul 01 04:30:48 PM PDT 24
Peak memory 217376 kb
Host smart-e59453aa-eaca-4dd8-b940-fb8ecf57787c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617186387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2617186387
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3408979319
Short name T333
Test name
Test status
Simulation time 517336808 ps
CPU time 11.5 seconds
Started Jul 01 04:29:44 PM PDT 24
Finished Jul 01 04:30:06 PM PDT 24
Peak memory 217060 kb
Host smart-2fef0ad4-4086-4937-a83d-f5067061f614
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408979319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3408979319
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3076477545
Short name T353
Test name
Test status
Simulation time 94309339552 ps
CPU time 450.19 seconds
Started Jul 01 04:29:36 PM PDT 24
Finished Jul 01 04:37:12 PM PDT 24
Peak memory 227988 kb
Host smart-e2ad5b19-9f01-4a31-87e0-9a18b175dad1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076477545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3076477545
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.614248344
Short name T322
Test name
Test status
Simulation time 1374355752 ps
CPU time 19.17 seconds
Started Jul 01 04:29:41 PM PDT 24
Finished Jul 01 04:30:10 PM PDT 24
Peak memory 219192 kb
Host smart-f6595bdd-e189-49cd-b507-f23c9ffdb4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614248344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.614248344
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.341621629
Short name T337
Test name
Test status
Simulation time 10654519206 ps
CPU time 50.5 seconds
Started Jul 01 04:29:40 PM PDT 24
Finished Jul 01 04:30:38 PM PDT 24
Peak memory 215968 kb
Host smart-b1d46e03-93af-4e12-b3d9-74815ea11c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341621629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.341621629
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1720653063
Short name T206
Test name
Test status
Simulation time 40216864569 ps
CPU time 84.76 seconds
Started Jul 01 04:29:42 PM PDT 24
Finished Jul 01 04:31:17 PM PDT 24
Peak memory 219932 kb
Host smart-411c7796-bd88-4d07-acbe-79cab3bd4f14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720653063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1720653063
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1317337701
Short name T243
Test name
Test status
Simulation time 14039453733 ps
CPU time 29.6 seconds
Started Jul 01 04:29:38 PM PDT 24
Finished Jul 01 04:30:13 PM PDT 24
Peak memory 213184 kb
Host smart-78bd0c18-e23e-4f2f-91a3-72f31ea98d2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317337701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1317337701
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3126037015
Short name T252
Test name
Test status
Simulation time 235740195660 ps
CPU time 576.24 seconds
Started Jul 01 04:29:41 PM PDT 24
Finished Jul 01 04:39:26 PM PDT 24
Peak memory 239468 kb
Host smart-4d8a7c8b-99a4-4c5c-aa3a-bb381b74d6d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126037015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3126037015
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.772457755
Short name T214
Test name
Test status
Simulation time 15428279988 ps
CPU time 62.03 seconds
Started Jul 01 04:29:23 PM PDT 24
Finished Jul 01 04:30:33 PM PDT 24
Peak memory 219300 kb
Host smart-ca89cca3-4949-464e-aeae-39e5a9c89e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772457755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.772457755
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.894028010
Short name T242
Test name
Test status
Simulation time 12213157308 ps
CPU time 27.98 seconds
Started Jul 01 04:29:18 PM PDT 24
Finished Jul 01 04:29:55 PM PDT 24
Peak memory 217624 kb
Host smart-350af5d3-1f79-45a3-a812-478a14cb53b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=894028010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.894028010
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1529056778
Short name T27
Test name
Test status
Simulation time 16166428912 ps
CPU time 240.08 seconds
Started Jul 01 04:29:38 PM PDT 24
Finished Jul 01 04:33:44 PM PDT 24
Peak memory 236244 kb
Host smart-09784f47-cb00-4af5-b015-74e48e3cb972
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529056778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1529056778
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3426594209
Short name T46
Test name
Test status
Simulation time 2368032652 ps
CPU time 29.47 seconds
Started Jul 01 04:29:05 PM PDT 24
Finished Jul 01 04:29:45 PM PDT 24
Peak memory 216556 kb
Host smart-a63d6763-de83-4e1e-9602-65b853a1bd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426594209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3426594209
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1101917771
Short name T276
Test name
Test status
Simulation time 18491395447 ps
CPU time 111.28 seconds
Started Jul 01 04:28:57 PM PDT 24
Finished Jul 01 04:31:02 PM PDT 24
Peak memory 221084 kb
Host smart-8d687b66-f312-4942-84a6-39e0f8b98372
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101917771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1101917771
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.454414987
Short name T187
Test name
Test status
Simulation time 1907543997 ps
CPU time 19.57 seconds
Started Jul 01 04:29:37 PM PDT 24
Finished Jul 01 04:30:01 PM PDT 24
Peak memory 217052 kb
Host smart-3e2dff75-cea5-4104-bc68-4a138a45ad1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454414987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.454414987
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2868357326
Short name T190
Test name
Test status
Simulation time 248344829123 ps
CPU time 487.52 seconds
Started Jul 01 04:29:43 PM PDT 24
Finished Jul 01 04:38:01 PM PDT 24
Peak memory 234980 kb
Host smart-1a227ddf-e56f-43ac-9315-0efcab797698
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868357326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2868357326
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3264343893
Short name T1
Test name
Test status
Simulation time 4789288169 ps
CPU time 27.28 seconds
Started Jul 01 04:29:20 PM PDT 24
Finished Jul 01 04:29:56 PM PDT 24
Peak memory 219288 kb
Host smart-4af092de-a69b-4063-b8bc-aa2e108d7807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264343893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3264343893
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.4158525831
Short name T118
Test name
Test status
Simulation time 2041114350 ps
CPU time 16.07 seconds
Started Jul 01 04:29:35 PM PDT 24
Finished Jul 01 04:29:56 PM PDT 24
Peak memory 211092 kb
Host smart-089522a1-668d-4bd6-9c24-259a6e1f9e5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4158525831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.4158525831
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.772218641
Short name T83
Test name
Test status
Simulation time 7916636928 ps
CPU time 67.81 seconds
Started Jul 01 04:29:44 PM PDT 24
Finished Jul 01 04:31:03 PM PDT 24
Peak memory 217304 kb
Host smart-ee22e49d-2580-4fd8-bb55-09e178aa0789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772218641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.772218641
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3298428459
Short name T195
Test name
Test status
Simulation time 3603959514 ps
CPU time 34.41 seconds
Started Jul 01 04:29:22 PM PDT 24
Finished Jul 01 04:30:04 PM PDT 24
Peak memory 219312 kb
Host smart-16c9ad2d-247d-46df-8047-73d69e212e04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298428459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3298428459
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.35657732
Short name T297
Test name
Test status
Simulation time 8153601172 ps
CPU time 31.18 seconds
Started Jul 01 04:29:24 PM PDT 24
Finished Jul 01 04:30:03 PM PDT 24
Peak memory 217356 kb
Host smart-4fef9a1d-ec0a-440c-bd32-4258a2d5aa2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35657732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.35657732
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3117532719
Short name T19
Test name
Test status
Simulation time 38733784272 ps
CPU time 530.03 seconds
Started Jul 01 04:29:34 PM PDT 24
Finished Jul 01 04:38:29 PM PDT 24
Peak memory 235472 kb
Host smart-128f3b23-10ac-48a5-b26f-001648b818d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117532719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3117532719
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3160728098
Short name T219
Test name
Test status
Simulation time 2358223078 ps
CPU time 18.85 seconds
Started Jul 01 04:29:29 PM PDT 24
Finished Jul 01 04:29:54 PM PDT 24
Peak memory 219288 kb
Host smart-403c1380-5e83-4100-ae47-682923c659e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160728098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3160728098
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.10157796
Short name T334
Test name
Test status
Simulation time 925531895 ps
CPU time 16.1 seconds
Started Jul 01 04:29:45 PM PDT 24
Finished Jul 01 04:30:14 PM PDT 24
Peak memory 211288 kb
Host smart-362c0e87-06f7-4e08-897e-7042215666b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=10157796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.10157796
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3172995283
Short name T188
Test name
Test status
Simulation time 1902409939 ps
CPU time 20.28 seconds
Started Jul 01 04:29:36 PM PDT 24
Finished Jul 01 04:30:01 PM PDT 24
Peak memory 216320 kb
Host smart-a69b7bf5-6900-418e-a308-b3bd67c86543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172995283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3172995283
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2692986305
Short name T356
Test name
Test status
Simulation time 404745520 ps
CPU time 25.41 seconds
Started Jul 01 04:29:36 PM PDT 24
Finished Jul 01 04:30:06 PM PDT 24
Peak memory 219256 kb
Host smart-8bd33811-f0f1-48f2-94f7-d0ab1d560d59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692986305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2692986305
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3661008965
Short name T215
Test name
Test status
Simulation time 14254293399 ps
CPU time 25.2 seconds
Started Jul 01 04:29:39 PM PDT 24
Finished Jul 01 04:30:11 PM PDT 24
Peak memory 213248 kb
Host smart-92f74fe6-3410-4a1f-a656-1a8436aa7c17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661008965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3661008965
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1202793413
Short name T282
Test name
Test status
Simulation time 148603600527 ps
CPU time 301.14 seconds
Started Jul 01 04:29:42 PM PDT 24
Finished Jul 01 04:34:54 PM PDT 24
Peak memory 237288 kb
Host smart-2344e548-5645-4421-a2d8-113343927d66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202793413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1202793413
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2501961640
Short name T56
Test name
Test status
Simulation time 17095672729 ps
CPU time 46.85 seconds
Started Jul 01 04:29:40 PM PDT 24
Finished Jul 01 04:30:36 PM PDT 24
Peak memory 219216 kb
Host smart-a1377e16-bcea-4bb6-ba2a-1cde6fa88dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501961640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2501961640
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.649992953
Short name T355
Test name
Test status
Simulation time 725354950 ps
CPU time 10.6 seconds
Started Jul 01 04:29:29 PM PDT 24
Finished Jul 01 04:29:46 PM PDT 24
Peak memory 219248 kb
Host smart-cffe0a37-9632-4dda-b86d-1a28f3214a8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=649992953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.649992953
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2659550193
Short name T84
Test name
Test status
Simulation time 1804019773 ps
CPU time 20.36 seconds
Started Jul 01 04:29:34 PM PDT 24
Finished Jul 01 04:29:59 PM PDT 24
Peak memory 216344 kb
Host smart-52a4e721-703f-4c8a-a66d-47126801c607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659550193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2659550193
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3100568062
Short name T350
Test name
Test status
Simulation time 12916879593 ps
CPU time 119.47 seconds
Started Jul 01 04:29:39 PM PDT 24
Finished Jul 01 04:31:46 PM PDT 24
Peak memory 221148 kb
Host smart-4df8db64-3b90-480a-af28-c2faf8ce3514
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100568062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3100568062
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3631797404
Short name T236
Test name
Test status
Simulation time 119566565962 ps
CPU time 223.73 seconds
Started Jul 01 04:29:31 PM PDT 24
Finished Jul 01 04:33:20 PM PDT 24
Peak memory 232688 kb
Host smart-e20aa2d8-fd40-4a03-97e3-364535f22634
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631797404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3631797404
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2741332519
Short name T45
Test name
Test status
Simulation time 18905752639 ps
CPU time 51.41 seconds
Started Jul 01 04:29:46 PM PDT 24
Finished Jul 01 04:30:49 PM PDT 24
Peak memory 219092 kb
Host smart-087a5efc-1421-48e3-bfca-34b5b9662f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741332519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2741332519
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.814494193
Short name T311
Test name
Test status
Simulation time 1508391843 ps
CPU time 18.91 seconds
Started Jul 01 04:29:40 PM PDT 24
Finished Jul 01 04:30:08 PM PDT 24
Peak memory 219220 kb
Host smart-3189df14-6dc9-4c56-8766-a072f8958a0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=814494193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.814494193
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1347309244
Short name T127
Test name
Test status
Simulation time 3495194389 ps
CPU time 25.87 seconds
Started Jul 01 04:29:40 PM PDT 24
Finished Jul 01 04:30:15 PM PDT 24
Peak memory 217024 kb
Host smart-8cec4bc3-acbd-4985-b355-1f8d44cced99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347309244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1347309244
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.927326312
Short name T354
Test name
Test status
Simulation time 35132588372 ps
CPU time 68.75 seconds
Started Jul 01 04:29:37 PM PDT 24
Finished Jul 01 04:30:51 PM PDT 24
Peak memory 217728 kb
Host smart-e3b11362-4f29-4452-8ad3-32bcd1032c4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927326312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.927326312
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.2395357138
Short name T50
Test name
Test status
Simulation time 190654846333 ps
CPU time 1927.7 seconds
Started Jul 01 04:29:32 PM PDT 24
Finished Jul 01 05:01:46 PM PDT 24
Peak memory 244904 kb
Host smart-abfc2821-0369-49c0-b24f-ec7b016d936d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395357138 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.2395357138
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2163816138
Short name T295
Test name
Test status
Simulation time 17029381229 ps
CPU time 32.26 seconds
Started Jul 01 04:29:37 PM PDT 24
Finished Jul 01 04:30:14 PM PDT 24
Peak memory 217368 kb
Host smart-6f0ff9ff-246c-4d65-9e5e-892cfb5d57ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163816138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2163816138
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3004800552
Short name T31
Test name
Test status
Simulation time 27914203890 ps
CPU time 389.7 seconds
Started Jul 01 04:29:39 PM PDT 24
Finished Jul 01 04:36:16 PM PDT 24
Peak memory 242000 kb
Host smart-4c55193b-b428-4952-91aa-f34b6206a3ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004800552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3004800552
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1114421826
Short name T6
Test name
Test status
Simulation time 704303328 ps
CPU time 18.82 seconds
Started Jul 01 04:29:24 PM PDT 24
Finished Jul 01 04:29:51 PM PDT 24
Peak memory 219168 kb
Host smart-d6bf4481-610d-4d13-a461-afb51d8e454a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114421826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1114421826
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.920256612
Short name T288
Test name
Test status
Simulation time 251274286 ps
CPU time 10.35 seconds
Started Jul 01 04:29:28 PM PDT 24
Finished Jul 01 04:29:45 PM PDT 24
Peak memory 219208 kb
Host smart-36f66448-842a-40dc-8d50-0e19a7ed4e0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=920256612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.920256612
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.4039281548
Short name T254
Test name
Test status
Simulation time 12100457863 ps
CPU time 38.61 seconds
Started Jul 01 04:29:33 PM PDT 24
Finished Jul 01 04:30:17 PM PDT 24
Peak memory 219036 kb
Host smart-92e4d7d8-60bc-4496-bd8d-494010494143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039281548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.4039281548
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3809061313
Short name T63
Test name
Test status
Simulation time 4284127501 ps
CPU time 42.1 seconds
Started Jul 01 04:29:44 PM PDT 24
Finished Jul 01 04:30:38 PM PDT 24
Peak memory 219264 kb
Host smart-e889336b-d178-4a8b-abdf-402388714f59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809061313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3809061313
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1265546135
Short name T200
Test name
Test status
Simulation time 1795305862 ps
CPU time 14.34 seconds
Started Jul 01 04:29:36 PM PDT 24
Finished Jul 01 04:29:56 PM PDT 24
Peak memory 213196 kb
Host smart-b46466b7-129b-406d-b7c1-b423546d0523
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265546135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1265546135
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1150675759
Short name T203
Test name
Test status
Simulation time 210896768588 ps
CPU time 539.28 seconds
Started Jul 01 04:29:37 PM PDT 24
Finished Jul 01 04:38:42 PM PDT 24
Peak memory 240444 kb
Host smart-a6657077-6802-4d1a-967f-cda67b4ddb65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150675759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1150675759
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.869975113
Short name T227
Test name
Test status
Simulation time 6166605770 ps
CPU time 29.6 seconds
Started Jul 01 04:29:33 PM PDT 24
Finished Jul 01 04:30:08 PM PDT 24
Peak memory 219384 kb
Host smart-14ee2f24-a08f-48bf-a160-a0bec7a33c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869975113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.869975113
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1318859958
Short name T246
Test name
Test status
Simulation time 29300679306 ps
CPU time 23.19 seconds
Started Jul 01 04:29:41 PM PDT 24
Finished Jul 01 04:30:14 PM PDT 24
Peak memory 212268 kb
Host smart-77fddb0d-8c37-4c45-90d9-6bae140b2f68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1318859958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1318859958
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1094704136
Short name T275
Test name
Test status
Simulation time 1431913340 ps
CPU time 20.1 seconds
Started Jul 01 04:29:36 PM PDT 24
Finished Jul 01 04:30:02 PM PDT 24
Peak memory 215952 kb
Host smart-749c5423-e4fe-43d3-97ba-b152fc580e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094704136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1094704136
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2813885553
Short name T130
Test name
Test status
Simulation time 19808167999 ps
CPU time 116.76 seconds
Started Jul 01 04:29:22 PM PDT 24
Finished Jul 01 04:31:28 PM PDT 24
Peak memory 220192 kb
Host smart-af03ede3-2787-4148-b73a-f22ca5be1260
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813885553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2813885553
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2698869536
Short name T52
Test name
Test status
Simulation time 105615088617 ps
CPU time 4598.67 seconds
Started Jul 01 04:29:42 PM PDT 24
Finished Jul 01 05:46:30 PM PDT 24
Peak memory 235744 kb
Host smart-33f1cb87-087c-4405-a49f-0a9b63183835
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698869536 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.2698869536
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1533189244
Short name T267
Test name
Test status
Simulation time 10591983587 ps
CPU time 24.64 seconds
Started Jul 01 04:29:45 PM PDT 24
Finished Jul 01 04:30:21 PM PDT 24
Peak memory 217396 kb
Host smart-52a864a2-0184-4fa8-8c34-6c2482f070c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533189244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1533189244
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3607613466
Short name T48
Test name
Test status
Simulation time 36009685828 ps
CPU time 334.36 seconds
Started Jul 01 04:29:40 PM PDT 24
Finished Jul 01 04:35:22 PM PDT 24
Peak memory 226496 kb
Host smart-0346581c-fed9-4121-9a1b-1cc051e0d7c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607613466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3607613466
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.807002399
Short name T335
Test name
Test status
Simulation time 1500057582 ps
CPU time 18.88 seconds
Started Jul 01 04:29:46 PM PDT 24
Finished Jul 01 04:30:17 PM PDT 24
Peak memory 219208 kb
Host smart-a68b7aa2-2e33-4340-9b7e-c7bdccd894c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807002399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.807002399
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1872257293
Short name T302
Test name
Test status
Simulation time 3505112998 ps
CPU time 27.6 seconds
Started Jul 01 04:29:28 PM PDT 24
Finished Jul 01 04:30:02 PM PDT 24
Peak memory 219308 kb
Host smart-7b33de94-99d3-467f-af0a-32ab8ff66ac4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1872257293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1872257293
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.74263577
Short name T259
Test name
Test status
Simulation time 731959846 ps
CPU time 20.6 seconds
Started Jul 01 04:29:41 PM PDT 24
Finished Jul 01 04:30:11 PM PDT 24
Peak memory 216284 kb
Host smart-b4b4b683-256e-4a02-ae2b-81785a305ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74263577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.74263577
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.4278696633
Short name T133
Test name
Test status
Simulation time 1966639847 ps
CPU time 23.35 seconds
Started Jul 01 04:29:23 PM PDT 24
Finished Jul 01 04:29:55 PM PDT 24
Peak memory 214516 kb
Host smart-96a4eaf2-6489-4ea3-a56b-a2b336c00781
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278696633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.4278696633
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1486502871
Short name T160
Test name
Test status
Simulation time 28686375430 ps
CPU time 22.74 seconds
Started Jul 01 04:29:41 PM PDT 24
Finished Jul 01 04:30:13 PM PDT 24
Peak memory 213364 kb
Host smart-11220093-c5d7-438d-8acc-6e85b832e796
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486502871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1486502871
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3106871397
Short name T262
Test name
Test status
Simulation time 107764060156 ps
CPU time 1046.95 seconds
Started Jul 01 04:29:38 PM PDT 24
Finished Jul 01 04:47:11 PM PDT 24
Peak memory 225388 kb
Host smart-76a98eeb-0c40-4e2b-88be-79aa188c4d34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106871397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3106871397
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2951817174
Short name T8
Test name
Test status
Simulation time 8876473385 ps
CPU time 38.8 seconds
Started Jul 01 04:29:40 PM PDT 24
Finished Jul 01 04:30:28 PM PDT 24
Peak memory 219256 kb
Host smart-b1555d05-c2a4-45f2-962f-cc8fdb695cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951817174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2951817174
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1390377696
Short name T280
Test name
Test status
Simulation time 2250712793 ps
CPU time 22.61 seconds
Started Jul 01 04:29:45 PM PDT 24
Finished Jul 01 04:30:19 PM PDT 24
Peak memory 219312 kb
Host smart-a0461a4e-2d9f-4fd1-827e-6d0a095ffcf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1390377696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1390377696
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2863241155
Short name T257
Test name
Test status
Simulation time 30535675308 ps
CPU time 58.05 seconds
Started Jul 01 04:29:36 PM PDT 24
Finished Jul 01 04:30:39 PM PDT 24
Peak memory 217304 kb
Host smart-92f6fc43-9369-48b0-b866-260c284b57f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863241155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2863241155
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2835438312
Short name T149
Test name
Test status
Simulation time 169018141 ps
CPU time 8.18 seconds
Started Jul 01 04:29:46 PM PDT 24
Finished Jul 01 04:30:06 PM PDT 24
Peak memory 217028 kb
Host smart-2bcfb169-6eae-439a-b174-94c920df2f03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835438312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2835438312
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2448927683
Short name T249
Test name
Test status
Simulation time 695164696 ps
CPU time 24.31 seconds
Started Jul 01 04:29:38 PM PDT 24
Finished Jul 01 04:30:08 PM PDT 24
Peak memory 219408 kb
Host smart-080591db-3e76-4110-87d3-905520951785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448927683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2448927683
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2822351237
Short name T103
Test name
Test status
Simulation time 2927246838 ps
CPU time 25.3 seconds
Started Jul 01 04:29:33 PM PDT 24
Finished Jul 01 04:30:04 PM PDT 24
Peak memory 219280 kb
Host smart-7ce80dd1-464a-4d82-af8b-9debd1f6fbe6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2822351237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2822351237
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2015607425
Short name T204
Test name
Test status
Simulation time 30141453706 ps
CPU time 69.67 seconds
Started Jul 01 04:29:46 PM PDT 24
Finished Jul 01 04:31:07 PM PDT 24
Peak memory 216232 kb
Host smart-bd79573b-ca50-4121-b396-baaf5af4c004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015607425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2015607425
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2419954743
Short name T261
Test name
Test status
Simulation time 61748325870 ps
CPU time 142.21 seconds
Started Jul 01 04:29:40 PM PDT 24
Finished Jul 01 04:32:10 PM PDT 24
Peak memory 227552 kb
Host smart-dbe38979-c906-4717-9ecb-ead5a266e837
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419954743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2419954743
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.375315221
Short name T183
Test name
Test status
Simulation time 850484623 ps
CPU time 14.38 seconds
Started Jul 01 04:29:39 PM PDT 24
Finished Jul 01 04:29:59 PM PDT 24
Peak memory 216988 kb
Host smart-b9de83bd-b598-4854-b486-e571fc5ad3aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375315221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.375315221
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.4061419008
Short name T174
Test name
Test status
Simulation time 95922996855 ps
CPU time 407.54 seconds
Started Jul 01 04:29:46 PM PDT 24
Finished Jul 01 04:36:49 PM PDT 24
Peak memory 241036 kb
Host smart-47691231-784c-4bb4-b261-be52adf8ae6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061419008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.4061419008
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1684539122
Short name T308
Test name
Test status
Simulation time 7355933000 ps
CPU time 63.07 seconds
Started Jul 01 04:29:47 PM PDT 24
Finished Jul 01 04:31:01 PM PDT 24
Peak memory 219496 kb
Host smart-15a8df6f-bf65-4d6c-9a5e-6a97afe8a512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684539122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1684539122
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3447550669
Short name T260
Test name
Test status
Simulation time 6940075296 ps
CPU time 19.57 seconds
Started Jul 01 04:29:43 PM PDT 24
Finished Jul 01 04:30:14 PM PDT 24
Peak memory 211588 kb
Host smart-2e61be97-d6d3-4334-952f-52265c76a211
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3447550669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3447550669
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2599278418
Short name T126
Test name
Test status
Simulation time 25760879294 ps
CPU time 53.23 seconds
Started Jul 01 04:29:50 PM PDT 24
Finished Jul 01 04:30:55 PM PDT 24
Peak memory 217224 kb
Host smart-40b42864-657b-447c-8d7e-b0dabdb11580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599278418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2599278418
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1151400677
Short name T348
Test name
Test status
Simulation time 114313711328 ps
CPU time 120.01 seconds
Started Jul 01 04:29:43 PM PDT 24
Finished Jul 01 04:31:55 PM PDT 24
Peak memory 219576 kb
Host smart-7333eb96-8b79-4a72-9f7e-8bbde280fb13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151400677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1151400677
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3530979546
Short name T69
Test name
Test status
Simulation time 6855874107 ps
CPU time 28.29 seconds
Started Jul 01 04:29:12 PM PDT 24
Finished Jul 01 04:29:49 PM PDT 24
Peak memory 217500 kb
Host smart-a881f34a-7c72-4f21-a4ad-fb598c6bd5e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530979546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3530979546
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1857916151
Short name T344
Test name
Test status
Simulation time 87205720507 ps
CPU time 396.68 seconds
Started Jul 01 04:29:19 PM PDT 24
Finished Jul 01 04:36:04 PM PDT 24
Peak memory 216892 kb
Host smart-4b365580-1c7e-4334-8805-a7a6292d7102
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857916151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1857916151
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3299013080
Short name T58
Test name
Test status
Simulation time 346107453 ps
CPU time 19.47 seconds
Started Jul 01 04:29:12 PM PDT 24
Finished Jul 01 04:29:41 PM PDT 24
Peak memory 219228 kb
Host smart-dbd2b209-9ed8-47c8-9aa4-8aa94bbfe415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299013080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3299013080
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3048229550
Short name T175
Test name
Test status
Simulation time 4611438667 ps
CPU time 18.86 seconds
Started Jul 01 04:28:57 PM PDT 24
Finished Jul 01 04:29:31 PM PDT 24
Peak memory 219308 kb
Host smart-74401bda-a747-49d5-ba35-438b733c84a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3048229550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3048229550
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.201883377
Short name T28
Test name
Test status
Simulation time 4821257069 ps
CPU time 239.52 seconds
Started Jul 01 04:29:04 PM PDT 24
Finished Jul 01 04:33:15 PM PDT 24
Peak memory 238356 kb
Host smart-695ba6d5-0e39-4038-9335-53108dcc49ea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201883377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.201883377
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3580319375
Short name T228
Test name
Test status
Simulation time 1265335427 ps
CPU time 19.48 seconds
Started Jul 01 04:29:41 PM PDT 24
Finished Jul 01 04:30:10 PM PDT 24
Peak memory 215912 kb
Host smart-10820e29-1bba-4f7a-8aa6-7575811996fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580319375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3580319375
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2653626744
Short name T202
Test name
Test status
Simulation time 10506792220 ps
CPU time 35.62 seconds
Started Jul 01 04:29:42 PM PDT 24
Finished Jul 01 04:30:28 PM PDT 24
Peak memory 217040 kb
Host smart-1fa84c43-9e04-4cfb-a8ef-8a43b26d91e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653626744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2653626744
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1902609061
Short name T152
Test name
Test status
Simulation time 231356638 ps
CPU time 8.09 seconds
Started Jul 01 04:29:35 PM PDT 24
Finished Jul 01 04:29:48 PM PDT 24
Peak memory 217256 kb
Host smart-3bed8a53-5145-4257-b389-5f2cec74f7f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902609061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1902609061
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2108627032
Short name T153
Test name
Test status
Simulation time 33873972437 ps
CPU time 379.66 seconds
Started Jul 01 04:29:37 PM PDT 24
Finished Jul 01 04:36:02 PM PDT 24
Peak memory 225488 kb
Host smart-6cc256a2-ad0e-44a3-86b9-106728b16435
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108627032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2108627032
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2472619286
Short name T197
Test name
Test status
Simulation time 18157826766 ps
CPU time 49.18 seconds
Started Jul 01 04:29:41 PM PDT 24
Finished Jul 01 04:30:39 PM PDT 24
Peak memory 219304 kb
Host smart-e1591038-43f5-4c06-99f7-00db3c0c3174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472619286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2472619286
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1742484967
Short name T290
Test name
Test status
Simulation time 3444456016 ps
CPU time 30.25 seconds
Started Jul 01 04:29:43 PM PDT 24
Finished Jul 01 04:30:24 PM PDT 24
Peak memory 211544 kb
Host smart-b057cf45-992b-4fb5-bf46-91b7d45d2905
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1742484967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1742484967
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3399519429
Short name T155
Test name
Test status
Simulation time 5258809587 ps
CPU time 61.73 seconds
Started Jul 01 04:29:44 PM PDT 24
Finished Jul 01 04:30:57 PM PDT 24
Peak memory 216592 kb
Host smart-d7888fd0-e340-47bf-aa80-90222daec6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399519429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3399519429
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.885217255
Short name T132
Test name
Test status
Simulation time 1796612487 ps
CPU time 66.89 seconds
Started Jul 01 04:29:42 PM PDT 24
Finished Jul 01 04:30:58 PM PDT 24
Peak memory 227432 kb
Host smart-99bc4848-97ee-47ea-aef1-e08e795fee05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885217255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.885217255
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2567762698
Short name T234
Test name
Test status
Simulation time 174269249 ps
CPU time 8.13 seconds
Started Jul 01 04:29:46 PM PDT 24
Finished Jul 01 04:30:06 PM PDT 24
Peak memory 217060 kb
Host smart-f4a6974e-a0fe-4816-a9d4-93d79a2359fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567762698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2567762698
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2503211372
Short name T148
Test name
Test status
Simulation time 66325447433 ps
CPU time 627.63 seconds
Started Jul 01 04:29:45 PM PDT 24
Finished Jul 01 04:40:25 PM PDT 24
Peak memory 242444 kb
Host smart-247c3746-dfda-47bb-8b68-b3596311db37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503211372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2503211372
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2364935655
Short name T62
Test name
Test status
Simulation time 332641630 ps
CPU time 18.79 seconds
Started Jul 01 04:29:39 PM PDT 24
Finished Jul 01 04:30:03 PM PDT 24
Peak memory 219180 kb
Host smart-7c197bc2-67ec-49c9-b4d8-133686a89dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364935655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2364935655
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.123631580
Short name T201
Test name
Test status
Simulation time 39004200098 ps
CPU time 26.73 seconds
Started Jul 01 04:29:39 PM PDT 24
Finished Jul 01 04:30:13 PM PDT 24
Peak memory 219268 kb
Host smart-d1be36be-9b25-4bd1-ad07-24cce7aa21c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=123631580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.123631580
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1299246740
Short name T185
Test name
Test status
Simulation time 342048987 ps
CPU time 21.19 seconds
Started Jul 01 04:29:45 PM PDT 24
Finished Jul 01 04:30:18 PM PDT 24
Peak memory 216524 kb
Host smart-a5ae4d2f-1754-4128-bd0d-e6b7ff191433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299246740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1299246740
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3279884285
Short name T61
Test name
Test status
Simulation time 13786717953 ps
CPU time 63.19 seconds
Started Jul 01 04:29:41 PM PDT 24
Finished Jul 01 04:30:54 PM PDT 24
Peak memory 218388 kb
Host smart-2bc09968-11f1-47a2-94d8-c32a77ff09a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279884285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3279884285
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1893824257
Short name T289
Test name
Test status
Simulation time 6667151429 ps
CPU time 27.4 seconds
Started Jul 01 04:29:44 PM PDT 24
Finished Jul 01 04:30:23 PM PDT 24
Peak memory 217512 kb
Host smart-d0914187-9bfc-413f-b4e9-c6b848dc0fb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893824257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1893824257
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2643700382
Short name T284
Test name
Test status
Simulation time 57624306755 ps
CPU time 383.44 seconds
Started Jul 01 04:29:46 PM PDT 24
Finished Jul 01 04:36:21 PM PDT 24
Peak memory 228704 kb
Host smart-f85d67d7-0712-4601-81b8-a8b97f3b0fb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643700382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2643700382
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1341426718
Short name T221
Test name
Test status
Simulation time 332487756 ps
CPU time 19.47 seconds
Started Jul 01 04:29:43 PM PDT 24
Finished Jul 01 04:30:18 PM PDT 24
Peak memory 219360 kb
Host smart-85db861e-d393-47e0-8aca-8ac3fb5edeef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341426718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1341426718
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2249266564
Short name T327
Test name
Test status
Simulation time 843285547 ps
CPU time 13.34 seconds
Started Jul 01 04:29:44 PM PDT 24
Finished Jul 01 04:30:09 PM PDT 24
Peak memory 218544 kb
Host smart-f53dc5ec-9c4d-4364-b17b-b2ce16842b73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2249266564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2249266564
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2400123361
Short name T264
Test name
Test status
Simulation time 1065459112 ps
CPU time 23.35 seconds
Started Jul 01 04:29:42 PM PDT 24
Finished Jul 01 04:30:22 PM PDT 24
Peak memory 216768 kb
Host smart-6b077e48-18ad-429f-a72a-63261294fe30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400123361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2400123361
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.289818886
Short name T156
Test name
Test status
Simulation time 10634033282 ps
CPU time 70.96 seconds
Started Jul 01 04:29:45 PM PDT 24
Finished Jul 01 04:31:08 PM PDT 24
Peak memory 220428 kb
Host smart-fcec983c-0716-4007-b75f-cae4c41ef074
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289818886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.289818886
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2899565837
Short name T72
Test name
Test status
Simulation time 11717366182 ps
CPU time 25.68 seconds
Started Jul 01 04:29:43 PM PDT 24
Finished Jul 01 04:30:19 PM PDT 24
Peak memory 217404 kb
Host smart-220eb537-0449-4482-b6c9-1308e9d72532
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899565837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2899565837
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1160805771
Short name T279
Test name
Test status
Simulation time 79164309592 ps
CPU time 774.31 seconds
Started Jul 01 04:29:43 PM PDT 24
Finished Jul 01 04:42:48 PM PDT 24
Peak memory 214740 kb
Host smart-7f239b5a-ad01-4194-b68e-baa4965e4933
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160805771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1160805771
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3413133779
Short name T34
Test name
Test status
Simulation time 13622866180 ps
CPU time 40.21 seconds
Started Jul 01 04:29:35 PM PDT 24
Finished Jul 01 04:30:20 PM PDT 24
Peak memory 219100 kb
Host smart-41cfbb63-6500-41f6-ba7f-b51a6711deb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413133779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3413133779
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1928091137
Short name T191
Test name
Test status
Simulation time 4352216912 ps
CPU time 32.94 seconds
Started Jul 01 04:29:31 PM PDT 24
Finished Jul 01 04:30:10 PM PDT 24
Peak memory 219316 kb
Host smart-915bef09-32cb-44bc-9b49-9234dceb5837
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1928091137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1928091137
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1461796125
Short name T222
Test name
Test status
Simulation time 1894376744 ps
CPU time 33.91 seconds
Started Jul 01 04:29:35 PM PDT 24
Finished Jul 01 04:30:14 PM PDT 24
Peak memory 216024 kb
Host smart-3de65b6a-b2f7-4866-a2a3-1bcc21af7ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461796125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1461796125
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3149648165
Short name T281
Test name
Test status
Simulation time 29515548492 ps
CPU time 71.83 seconds
Started Jul 01 04:29:29 PM PDT 24
Finished Jul 01 04:30:47 PM PDT 24
Peak memory 218532 kb
Host smart-39d8d30b-05d8-41a3-83fe-acc57bc65ace
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149648165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3149648165
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.282661466
Short name T210
Test name
Test status
Simulation time 14207057321 ps
CPU time 15.3 seconds
Started Jul 01 04:29:42 PM PDT 24
Finished Jul 01 04:30:08 PM PDT 24
Peak memory 213216 kb
Host smart-ca2978ba-6f8b-4fb2-9453-71a1eca2cb90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282661466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.282661466
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.4242736663
Short name T274
Test name
Test status
Simulation time 137342858417 ps
CPU time 501.45 seconds
Started Jul 01 04:29:46 PM PDT 24
Finished Jul 01 04:38:19 PM PDT 24
Peak memory 219476 kb
Host smart-ec11f66f-6cff-41c2-953d-83dfce1a9e9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242736663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.4242736663
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.4060163451
Short name T226
Test name
Test status
Simulation time 2617245119 ps
CPU time 35.03 seconds
Started Jul 01 04:29:45 PM PDT 24
Finished Jul 01 04:30:32 PM PDT 24
Peak memory 219212 kb
Host smart-24357687-728e-497f-86c0-7ff57dc767a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060163451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.4060163451
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2776058100
Short name T299
Test name
Test status
Simulation time 20763835278 ps
CPU time 30.37 seconds
Started Jul 01 04:29:39 PM PDT 24
Finished Jul 01 04:30:16 PM PDT 24
Peak memory 216844 kb
Host smart-576615bd-1540-4ec2-abcc-dd29c0b12fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776058100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2776058100
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1552912105
Short name T305
Test name
Test status
Simulation time 83839752622 ps
CPU time 223.47 seconds
Started Jul 01 04:29:47 PM PDT 24
Finished Jul 01 04:33:43 PM PDT 24
Peak memory 221424 kb
Host smart-b4266ddf-340c-41a8-b90a-8f241e5211ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552912105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1552912105
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1856131661
Short name T349
Test name
Test status
Simulation time 345544839 ps
CPU time 8.33 seconds
Started Jul 01 04:29:41 PM PDT 24
Finished Jul 01 04:29:59 PM PDT 24
Peak memory 217136 kb
Host smart-026458b6-bc21-403e-bbb6-db38e826b118
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856131661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1856131661
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3027911714
Short name T39
Test name
Test status
Simulation time 67271690665 ps
CPU time 309.42 seconds
Started Jul 01 04:30:00 PM PDT 24
Finished Jul 01 04:35:22 PM PDT 24
Peak memory 236836 kb
Host smart-2e423039-f44e-4916-a904-cc80d932da40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027911714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3027911714
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3214541001
Short name T310
Test name
Test status
Simulation time 332499286 ps
CPU time 19.33 seconds
Started Jul 01 04:29:44 PM PDT 24
Finished Jul 01 04:30:15 PM PDT 24
Peak memory 219220 kb
Host smart-23d9e3dc-3c3e-4f97-996d-616c68414254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214541001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3214541001
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1694221693
Short name T131
Test name
Test status
Simulation time 4479176759 ps
CPU time 31.23 seconds
Started Jul 01 04:29:45 PM PDT 24
Finished Jul 01 04:30:28 PM PDT 24
Peak memory 219248 kb
Host smart-1b158376-e927-4af5-ae47-c2af0f36c460
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1694221693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1694221693
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1861057923
Short name T129
Test name
Test status
Simulation time 870897799 ps
CPU time 25.55 seconds
Started Jul 01 04:29:41 PM PDT 24
Finished Jul 01 04:30:15 PM PDT 24
Peak memory 217572 kb
Host smart-91112088-8362-4181-96b1-0ad989b9beb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861057923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1861057923
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.115657505
Short name T173
Test name
Test status
Simulation time 3061227294 ps
CPU time 84.87 seconds
Started Jul 01 04:30:13 PM PDT 24
Finished Jul 01 04:31:56 PM PDT 24
Peak memory 229756 kb
Host smart-3d24ceb2-9242-49e1-ae63-b81133567343
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115657505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.115657505
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.580026997
Short name T14
Test name
Test status
Simulation time 68134249536 ps
CPU time 602.77 seconds
Started Jul 01 04:29:47 PM PDT 24
Finished Jul 01 04:40:02 PM PDT 24
Peak memory 231768 kb
Host smart-fd256725-b8c7-46b0-a826-179d20625ebf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580026997 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.580026997
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1965907869
Short name T316
Test name
Test status
Simulation time 8244323205 ps
CPU time 22.07 seconds
Started Jul 01 04:30:16 PM PDT 24
Finished Jul 01 04:30:55 PM PDT 24
Peak memory 217784 kb
Host smart-8b33128a-a3a3-41c2-9425-663638485891
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965907869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1965907869
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3124230143
Short name T20
Test name
Test status
Simulation time 12752769491 ps
CPU time 366.34 seconds
Started Jul 01 04:29:44 PM PDT 24
Finished Jul 01 04:36:03 PM PDT 24
Peak memory 235068 kb
Host smart-54c8dce1-0284-47ff-9c8d-979e299f4d4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124230143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3124230143
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1831327740
Short name T189
Test name
Test status
Simulation time 34991550648 ps
CPU time 68.26 seconds
Started Jul 01 04:29:46 PM PDT 24
Finished Jul 01 04:31:06 PM PDT 24
Peak memory 219252 kb
Host smart-8b14f40f-fcba-44ae-9a2f-43ab61fffacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831327740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1831327740
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2600299470
Short name T296
Test name
Test status
Simulation time 357802837 ps
CPU time 10.61 seconds
Started Jul 01 04:30:12 PM PDT 24
Finished Jul 01 04:30:40 PM PDT 24
Peak memory 219252 kb
Host smart-c7ef9311-b75a-486e-be35-640ec781a272
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2600299470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2600299470
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2820288342
Short name T125
Test name
Test status
Simulation time 349029700 ps
CPU time 20.92 seconds
Started Jul 01 04:30:11 PM PDT 24
Finished Jul 01 04:30:49 PM PDT 24
Peak memory 216500 kb
Host smart-a7fffab9-8c00-426a-9992-b96d5a2da115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820288342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2820288342
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2098056321
Short name T150
Test name
Test status
Simulation time 4588155399 ps
CPU time 17.28 seconds
Started Jul 01 04:29:38 PM PDT 24
Finished Jul 01 04:30:01 PM PDT 24
Peak memory 214772 kb
Host smart-b69a352c-4e12-45ef-8cb3-80a23296ee14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098056321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2098056321
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.327829805
Short name T70
Test name
Test status
Simulation time 172800297 ps
CPU time 8.45 seconds
Started Jul 01 04:29:58 PM PDT 24
Finished Jul 01 04:30:18 PM PDT 24
Peak memory 217032 kb
Host smart-44291ce5-c29d-404f-8bd6-7e48f9d606d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327829805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.327829805
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.521497678
Short name T233
Test name
Test status
Simulation time 9763746115 ps
CPU time 252.3 seconds
Started Jul 01 04:29:39 PM PDT 24
Finished Jul 01 04:33:59 PM PDT 24
Peak memory 234400 kb
Host smart-3e08ea09-5c09-4751-b2b3-d42a064ca682
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521497678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.521497678
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1359322710
Short name T272
Test name
Test status
Simulation time 13362871088 ps
CPU time 56 seconds
Started Jul 01 04:29:47 PM PDT 24
Finished Jul 01 04:30:55 PM PDT 24
Peak memory 219284 kb
Host smart-248ca8cb-2cba-48b5-927d-d8f525965fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359322710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1359322710
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1096693169
Short name T123
Test name
Test status
Simulation time 4525005462 ps
CPU time 16.66 seconds
Started Jul 01 04:29:47 PM PDT 24
Finished Jul 01 04:30:16 PM PDT 24
Peak memory 217824 kb
Host smart-3344ffed-490a-45f4-948e-7a36f7380266
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1096693169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1096693169
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1267125076
Short name T147
Test name
Test status
Simulation time 717097568 ps
CPU time 19.88 seconds
Started Jul 01 04:29:42 PM PDT 24
Finished Jul 01 04:30:14 PM PDT 24
Peak memory 216252 kb
Host smart-ee2929e0-0288-48b6-893a-f67259836285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267125076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1267125076
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2866057710
Short name T144
Test name
Test status
Simulation time 60363617440 ps
CPU time 46.08 seconds
Started Jul 01 04:29:45 PM PDT 24
Finished Jul 01 04:30:43 PM PDT 24
Peak memory 219292 kb
Host smart-22485db5-e79c-4ddd-bd56-e2e591235c62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866057710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2866057710
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1885090787
Short name T343
Test name
Test status
Simulation time 3352506579 ps
CPU time 27.83 seconds
Started Jul 01 04:29:41 PM PDT 24
Finished Jul 01 04:30:18 PM PDT 24
Peak memory 217064 kb
Host smart-c317e46e-2c2d-46e6-bce6-17859fdfd3cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885090787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1885090787
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3272495036
Short name T250
Test name
Test status
Simulation time 166906207676 ps
CPU time 576.3 seconds
Started Jul 01 04:29:43 PM PDT 24
Finished Jul 01 04:39:31 PM PDT 24
Peak memory 234512 kb
Host smart-cb7038c7-c052-4cd0-9819-75694bf01850
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272495036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3272495036
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.677043949
Short name T164
Test name
Test status
Simulation time 346451602 ps
CPU time 19.01 seconds
Started Jul 01 04:29:45 PM PDT 24
Finished Jul 01 04:30:16 PM PDT 24
Peak memory 219092 kb
Host smart-2f525352-cda4-459d-ad1c-df4de80a75ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677043949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.677043949
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3735877879
Short name T4
Test name
Test status
Simulation time 17201646282 ps
CPU time 33.78 seconds
Started Jul 01 04:29:50 PM PDT 24
Finished Jul 01 04:30:35 PM PDT 24
Peak memory 211968 kb
Host smart-7991ad1b-bc79-46ef-ba6d-534b3ae46c25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3735877879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3735877879
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2288914707
Short name T270
Test name
Test status
Simulation time 347939490 ps
CPU time 20.27 seconds
Started Jul 01 04:29:43 PM PDT 24
Finished Jul 01 04:30:15 PM PDT 24
Peak memory 216016 kb
Host smart-82104bed-ee4f-4580-ab44-d9014465ed76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288914707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2288914707
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2339474105
Short name T86
Test name
Test status
Simulation time 16743617645 ps
CPU time 166.82 seconds
Started Jul 01 04:29:46 PM PDT 24
Finished Jul 01 04:32:44 PM PDT 24
Peak memory 220788 kb
Host smart-6a805258-817b-459a-85b0-d43fd1cdb925
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339474105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2339474105
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.780998738
Short name T212
Test name
Test status
Simulation time 3024126842 ps
CPU time 25.08 seconds
Started Jul 01 04:29:43 PM PDT 24
Finished Jul 01 04:30:20 PM PDT 24
Peak memory 217104 kb
Host smart-bc004559-34e2-4320-a845-5362e154a71c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780998738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.780998738
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2231899282
Short name T165
Test name
Test status
Simulation time 4424810011 ps
CPU time 47.37 seconds
Started Jul 01 04:30:13 PM PDT 24
Finished Jul 01 04:31:17 PM PDT 24
Peak memory 219248 kb
Host smart-711f3864-27e2-43fd-94e1-13678645ab27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231899282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2231899282
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.700797477
Short name T263
Test name
Test status
Simulation time 1724713870 ps
CPU time 19.76 seconds
Started Jul 01 04:29:48 PM PDT 24
Finished Jul 01 04:30:20 PM PDT 24
Peak memory 219220 kb
Host smart-c5d5e0ae-5678-4da7-a96e-13b1ca2abbf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=700797477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.700797477
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.4332770
Short name T32
Test name
Test status
Simulation time 19038876908 ps
CPU time 59.79 seconds
Started Jul 01 04:30:16 PM PDT 24
Finished Jul 01 04:31:33 PM PDT 24
Peak memory 215812 kb
Host smart-0c529bc7-64b1-42db-b89a-31099da08c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4332770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.4332770
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1052479844
Short name T146
Test name
Test status
Simulation time 24305637324 ps
CPU time 122.77 seconds
Started Jul 01 04:29:57 PM PDT 24
Finished Jul 01 04:32:10 PM PDT 24
Peak memory 221420 kb
Host smart-9fd345f9-dd46-4323-b241-0b5158c0a055
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052479844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1052479844
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.493544001
Short name T36
Test name
Test status
Simulation time 3996197593 ps
CPU time 31.48 seconds
Started Jul 01 04:29:14 PM PDT 24
Finished Jul 01 04:29:55 PM PDT 24
Peak memory 217056 kb
Host smart-89dd4b11-e990-4e1b-b18f-a823a46a29a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493544001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.493544001
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1342052281
Short name T324
Test name
Test status
Simulation time 16354173357 ps
CPU time 243.9 seconds
Started Jul 01 04:29:11 PM PDT 24
Finished Jul 01 04:33:24 PM PDT 24
Peak memory 241376 kb
Host smart-f0bd44b5-8ea8-47b4-9f39-1419aa1e7ba5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342052281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1342052281
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3362697097
Short name T196
Test name
Test status
Simulation time 6405139717 ps
CPU time 57.99 seconds
Started Jul 01 04:28:57 PM PDT 24
Finished Jul 01 04:30:09 PM PDT 24
Peak memory 219444 kb
Host smart-5e966fc2-0f73-45a7-988a-3c163fabfa5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362697097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3362697097
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.4125386336
Short name T178
Test name
Test status
Simulation time 181899464 ps
CPU time 10.62 seconds
Started Jul 01 04:28:58 PM PDT 24
Finished Jul 01 04:29:23 PM PDT 24
Peak memory 219248 kb
Host smart-7defe1d0-48f6-4080-b3ac-96182183cdf8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4125386336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.4125386336
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1773285799
Short name T194
Test name
Test status
Simulation time 24718206603 ps
CPU time 60.75 seconds
Started Jul 01 04:29:07 PM PDT 24
Finished Jul 01 04:30:18 PM PDT 24
Peak memory 216784 kb
Host smart-f8b6d878-0498-4bfb-91c8-97649c5e0ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773285799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1773285799
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2818680125
Short name T192
Test name
Test status
Simulation time 6743910943 ps
CPU time 66.75 seconds
Started Jul 01 04:29:23 PM PDT 24
Finished Jul 01 04:30:38 PM PDT 24
Peak memory 217448 kb
Host smart-3e2528ad-f6f6-4101-8ce1-44b481f9c831
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818680125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2818680125
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3730338776
Short name T159
Test name
Test status
Simulation time 15539826655 ps
CPU time 27.71 seconds
Started Jul 01 04:29:43 PM PDT 24
Finished Jul 01 04:30:21 PM PDT 24
Peak memory 217612 kb
Host smart-d435484d-5463-4278-899c-a944de7749ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730338776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3730338776
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3817138494
Short name T40
Test name
Test status
Simulation time 363123938706 ps
CPU time 423.82 seconds
Started Jul 01 04:29:50 PM PDT 24
Finished Jul 01 04:37:05 PM PDT 24
Peak memory 225820 kb
Host smart-a83be104-4d63-4bca-bbb4-3beca8598477
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817138494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3817138494
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3536240501
Short name T166
Test name
Test status
Simulation time 13646890900 ps
CPU time 38.78 seconds
Started Jul 01 04:29:47 PM PDT 24
Finished Jul 01 04:30:37 PM PDT 24
Peak memory 219288 kb
Host smart-36af629c-5a53-425f-ac2a-14810c29058f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536240501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3536240501
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3024755166
Short name T278
Test name
Test status
Simulation time 7538511332 ps
CPU time 20.35 seconds
Started Jul 01 04:29:42 PM PDT 24
Finished Jul 01 04:30:14 PM PDT 24
Peak memory 211956 kb
Host smart-15bde782-feca-4ff5-a40d-af47b963e93f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3024755166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3024755166
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3554772056
Short name T255
Test name
Test status
Simulation time 4785312928 ps
CPU time 47.04 seconds
Started Jul 01 04:29:49 PM PDT 24
Finished Jul 01 04:30:49 PM PDT 24
Peak memory 215936 kb
Host smart-ade18f09-a606-4b25-a39b-44c96bf71849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554772056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3554772056
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3847153834
Short name T5
Test name
Test status
Simulation time 8468197218 ps
CPU time 32.13 seconds
Started Jul 01 04:30:02 PM PDT 24
Finished Jul 01 04:30:47 PM PDT 24
Peak memory 217460 kb
Host smart-e83b59e0-5ea6-42db-ae2c-dd158914beba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847153834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3847153834
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2063393324
Short name T319
Test name
Test status
Simulation time 178958100912 ps
CPU time 469.92 seconds
Started Jul 01 04:29:57 PM PDT 24
Finished Jul 01 04:37:58 PM PDT 24
Peak memory 225932 kb
Host smart-d8ee65e6-89e9-42f1-8156-a1163fdddb99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063393324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2063393324
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3101911884
Short name T24
Test name
Test status
Simulation time 4969326747 ps
CPU time 47.17 seconds
Started Jul 01 04:29:49 PM PDT 24
Finished Jul 01 04:30:47 PM PDT 24
Peak memory 219304 kb
Host smart-c58b2188-9861-4aa0-8bab-d4792d1bab07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101911884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3101911884
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3324394957
Short name T287
Test name
Test status
Simulation time 1600937460 ps
CPU time 18.46 seconds
Started Jul 01 04:29:45 PM PDT 24
Finished Jul 01 04:30:15 PM PDT 24
Peak memory 219200 kb
Host smart-19e5069d-b5ab-40a4-9d44-e723cd22aa74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3324394957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3324394957
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2650630767
Short name T245
Test name
Test status
Simulation time 1376211274 ps
CPU time 19.27 seconds
Started Jul 01 04:30:59 PM PDT 24
Finished Jul 01 04:31:29 PM PDT 24
Peak memory 214972 kb
Host smart-f297f168-f8b0-404a-831a-f243828f5473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650630767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2650630767
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2054157502
Short name T224
Test name
Test status
Simulation time 11587053841 ps
CPU time 107.8 seconds
Started Jul 01 04:30:59 PM PDT 24
Finished Jul 01 04:32:58 PM PDT 24
Peak memory 217916 kb
Host smart-1e93825e-69fc-4df9-b496-16ab480ef409
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054157502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2054157502
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.231670032
Short name T309
Test name
Test status
Simulation time 1909057616 ps
CPU time 19.85 seconds
Started Jul 01 04:29:44 PM PDT 24
Finished Jul 01 04:30:15 PM PDT 24
Peak memory 217052 kb
Host smart-23d48426-9efe-4fd9-8cf9-ed87b0d122a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231670032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.231670032
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2951728255
Short name T41
Test name
Test status
Simulation time 21796067572 ps
CPU time 294.16 seconds
Started Jul 01 04:30:59 PM PDT 24
Finished Jul 01 04:36:04 PM PDT 24
Peak memory 215952 kb
Host smart-d0153990-5511-411e-983a-8640eb6d56a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951728255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2951728255
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3845982741
Short name T286
Test name
Test status
Simulation time 19697381982 ps
CPU time 49.21 seconds
Started Jul 01 04:29:49 PM PDT 24
Finished Jul 01 04:30:51 PM PDT 24
Peak memory 219292 kb
Host smart-7a11eb35-2460-4c2e-bd07-11ba4c511ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845982741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3845982741
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3927337228
Short name T332
Test name
Test status
Simulation time 4661534134 ps
CPU time 17.37 seconds
Started Jul 01 04:29:43 PM PDT 24
Finished Jul 01 04:30:12 PM PDT 24
Peak memory 212088 kb
Host smart-c356059e-0a6c-433d-8ceb-9601b51eeb67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3927337228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3927337228
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1507424659
Short name T304
Test name
Test status
Simulation time 6079404590 ps
CPU time 54.75 seconds
Started Jul 01 04:29:49 PM PDT 24
Finished Jul 01 04:31:00 PM PDT 24
Peak memory 216708 kb
Host smart-a69a525b-10aa-4d6f-aa8d-722982df7835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507424659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1507424659
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3901888022
Short name T142
Test name
Test status
Simulation time 1098605037 ps
CPU time 20.07 seconds
Started Jul 01 04:30:59 PM PDT 24
Finished Jul 01 04:31:30 PM PDT 24
Peak memory 217592 kb
Host smart-725e6116-a84f-492b-a5dd-75062997b8a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901888022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3901888022
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.476492282
Short name T3
Test name
Test status
Simulation time 2590922707 ps
CPU time 24.79 seconds
Started Jul 01 04:29:53 PM PDT 24
Finished Jul 01 04:30:29 PM PDT 24
Peak memory 213420 kb
Host smart-f0eea319-105a-4741-aaf5-eebb36c2af4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476492282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.476492282
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1268430627
Short name T193
Test name
Test status
Simulation time 282449883824 ps
CPU time 717.1 seconds
Started Jul 01 04:29:43 PM PDT 24
Finished Jul 01 04:41:52 PM PDT 24
Peak memory 234060 kb
Host smart-b57eadad-dfe9-457e-b1b9-c40e32ae9c5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268430627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1268430627
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1683704171
Short name T328
Test name
Test status
Simulation time 5280824643 ps
CPU time 49.83 seconds
Started Jul 01 04:31:18 PM PDT 24
Finished Jul 01 04:32:20 PM PDT 24
Peak memory 218976 kb
Host smart-e1cbe0f2-4233-4303-9a97-fe2044545f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683704171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1683704171
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1551988811
Short name T186
Test name
Test status
Simulation time 4219943576 ps
CPU time 31.92 seconds
Started Jul 01 04:30:59 PM PDT 24
Finished Jul 01 04:31:42 PM PDT 24
Peak memory 217224 kb
Host smart-6313da2e-df19-40af-87b1-1b0aee168b55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1551988811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1551988811
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2015856710
Short name T293
Test name
Test status
Simulation time 678807195 ps
CPU time 19.69 seconds
Started Jul 01 04:29:41 PM PDT 24
Finished Jul 01 04:30:10 PM PDT 24
Peak memory 216676 kb
Host smart-f2424804-4290-4866-adad-01b43fa69f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015856710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2015856710
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.759104591
Short name T55
Test name
Test status
Simulation time 13895202343 ps
CPU time 131.74 seconds
Started Jul 01 04:29:44 PM PDT 24
Finished Jul 01 04:32:07 PM PDT 24
Peak memory 220132 kb
Host smart-358ddcda-6344-47a3-b0bf-61cc8a16c798
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759104591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.759104591
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1467371282
Short name T235
Test name
Test status
Simulation time 4058808128 ps
CPU time 31.53 seconds
Started Jul 01 04:29:40 PM PDT 24
Finished Jul 01 04:30:19 PM PDT 24
Peak memory 217192 kb
Host smart-b7762be2-4d8f-430c-9af2-5e4c2766c1a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467371282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1467371282
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1903470659
Short name T306
Test name
Test status
Simulation time 249230377898 ps
CPU time 1290.23 seconds
Started Jul 01 04:29:45 PM PDT 24
Finished Jul 01 04:51:28 PM PDT 24
Peak memory 238192 kb
Host smart-c487ee82-efa2-404a-8524-0662aacae564
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903470659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1903470659
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1324822814
Short name T44
Test name
Test status
Simulation time 41053759894 ps
CPU time 34.14 seconds
Started Jul 01 04:31:14 PM PDT 24
Finished Jul 01 04:32:00 PM PDT 24
Peak memory 218688 kb
Host smart-d7871524-3b93-49d0-b543-2cb354327efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324822814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1324822814
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2499210240
Short name T199
Test name
Test status
Simulation time 2579989488 ps
CPU time 25.17 seconds
Started Jul 01 04:29:47 PM PDT 24
Finished Jul 01 04:30:24 PM PDT 24
Peak memory 211732 kb
Host smart-49aa75af-b320-4de2-8afc-7b9be885f5d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2499210240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2499210240
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3378437788
Short name T313
Test name
Test status
Simulation time 7258458543 ps
CPU time 67.79 seconds
Started Jul 01 04:29:54 PM PDT 24
Finished Jul 01 04:31:13 PM PDT 24
Peak memory 217496 kb
Host smart-de194b2b-50c6-407e-8c36-a1ff9e02ca8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378437788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3378437788
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2131623702
Short name T162
Test name
Test status
Simulation time 16504468497 ps
CPU time 31.8 seconds
Started Jul 01 04:30:59 PM PDT 24
Finished Jul 01 04:31:42 PM PDT 24
Peak memory 217160 kb
Host smart-dc207847-e113-4754-9c7f-10fa8fa81915
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131623702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2131623702
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.547002946
Short name T154
Test name
Test status
Simulation time 8223674083 ps
CPU time 31.17 seconds
Started Jul 01 04:29:47 PM PDT 24
Finished Jul 01 04:30:30 PM PDT 24
Peak memory 217388 kb
Host smart-19336424-4de6-4e9a-8732-602d2e70420b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547002946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.547002946
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.810027617
Short name T136
Test name
Test status
Simulation time 36928643415 ps
CPU time 584.32 seconds
Started Jul 01 04:31:14 PM PDT 24
Finished Jul 01 04:41:10 PM PDT 24
Peak memory 237200 kb
Host smart-5c380786-94b0-4444-a2ec-9e6fc05c4a23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810027617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.810027617
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3759376598
Short name T338
Test name
Test status
Simulation time 13640123685 ps
CPU time 43.05 seconds
Started Jul 01 04:30:59 PM PDT 24
Finished Jul 01 04:31:53 PM PDT 24
Peak memory 217888 kb
Host smart-3b1a1e40-ebf8-4403-9241-172348071337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759376598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3759376598
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.4148279533
Short name T283
Test name
Test status
Simulation time 6346889893 ps
CPU time 17.44 seconds
Started Jul 01 04:29:50 PM PDT 24
Finished Jul 01 04:30:19 PM PDT 24
Peak memory 219268 kb
Host smart-e01ef0b1-de34-426b-b5da-528a9bb8b89a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4148279533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.4148279533
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1276841815
Short name T277
Test name
Test status
Simulation time 8244097585 ps
CPU time 34.29 seconds
Started Jul 01 04:30:07 PM PDT 24
Finished Jul 01 04:30:57 PM PDT 24
Peak memory 216588 kb
Host smart-45877fd0-4421-4db2-8884-75c74904ed2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276841815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1276841815
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3094804868
Short name T135
Test name
Test status
Simulation time 47644406865 ps
CPU time 144.5 seconds
Started Jul 01 04:29:43 PM PDT 24
Finished Jul 01 04:32:19 PM PDT 24
Peak memory 220144 kb
Host smart-cd8f4e29-e055-45ef-8d21-13a0b2676558
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094804868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3094804868
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3912894489
Short name T230
Test name
Test status
Simulation time 1028847410 ps
CPU time 10.24 seconds
Started Jul 01 04:30:05 PM PDT 24
Finished Jul 01 04:30:30 PM PDT 24
Peak memory 217004 kb
Host smart-3d680e11-9369-4376-9e65-989950cface1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912894489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3912894489
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.4106831068
Short name T218
Test name
Test status
Simulation time 2954535212 ps
CPU time 169.17 seconds
Started Jul 01 04:29:50 PM PDT 24
Finished Jul 01 04:32:51 PM PDT 24
Peak memory 219456 kb
Host smart-12bafe31-ecec-4206-b955-2e0446b91002
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106831068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.4106831068
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1312496194
Short name T170
Test name
Test status
Simulation time 11713875255 ps
CPU time 35.79 seconds
Started Jul 01 04:30:03 PM PDT 24
Finished Jul 01 04:30:52 PM PDT 24
Peak memory 219392 kb
Host smart-24b3bd6b-a9aa-4ee4-8445-e58ed8506d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312496194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1312496194
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.4099975542
Short name T179
Test name
Test status
Simulation time 184456615 ps
CPU time 10.57 seconds
Started Jul 01 04:30:04 PM PDT 24
Finished Jul 01 04:30:28 PM PDT 24
Peak memory 219252 kb
Host smart-dcc799f7-6d9c-4f38-b299-4831dd5d26a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4099975542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.4099975542
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.801679603
Short name T198
Test name
Test status
Simulation time 16442006682 ps
CPU time 49.74 seconds
Started Jul 01 04:29:44 PM PDT 24
Finished Jul 01 04:30:45 PM PDT 24
Peak memory 216908 kb
Host smart-dd3f3143-a9af-4415-8a3d-f40fcb919a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801679603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.801679603
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2048358547
Short name T240
Test name
Test status
Simulation time 69609973911 ps
CPU time 58.26 seconds
Started Jul 01 04:29:44 PM PDT 24
Finished Jul 01 04:30:54 PM PDT 24
Peak memory 217680 kb
Host smart-e1e5bb82-8c84-41ec-a5f4-d6230d472caf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048358547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2048358547
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.284339226
Short name T336
Test name
Test status
Simulation time 3302553241 ps
CPU time 28.03 seconds
Started Jul 01 04:29:48 PM PDT 24
Finished Jul 01 04:30:28 PM PDT 24
Peak memory 217096 kb
Host smart-2bd279bd-f38b-4328-a258-cf9afda40926
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284339226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.284339226
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.4168495190
Short name T285
Test name
Test status
Simulation time 205279775615 ps
CPU time 551.71 seconds
Started Jul 01 04:29:59 PM PDT 24
Finished Jul 01 04:39:23 PM PDT 24
Peak memory 230096 kb
Host smart-632309bf-65a0-4f36-974a-e6fd4856bfd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168495190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.4168495190
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2601332194
Short name T163
Test name
Test status
Simulation time 540565106 ps
CPU time 21.58 seconds
Started Jul 01 04:29:52 PM PDT 24
Finished Jul 01 04:30:26 PM PDT 24
Peak memory 219292 kb
Host smart-8a850dd7-3567-4aba-8c7a-b32764768029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601332194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2601332194
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2933049855
Short name T294
Test name
Test status
Simulation time 2830577705 ps
CPU time 25.7 seconds
Started Jul 01 04:29:43 PM PDT 24
Finished Jul 01 04:30:19 PM PDT 24
Peak memory 219288 kb
Host smart-4c03af60-f67e-4b41-8ccf-4c3c844680e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2933049855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2933049855
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1436708339
Short name T37
Test name
Test status
Simulation time 6779251792 ps
CPU time 59.5 seconds
Started Jul 01 04:30:11 PM PDT 24
Finished Jul 01 04:31:28 PM PDT 24
Peak memory 216572 kb
Host smart-9adfda62-b70e-411c-bfe6-73e497028ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436708339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1436708339
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2033982725
Short name T120
Test name
Test status
Simulation time 5185091652 ps
CPU time 25.96 seconds
Started Jul 01 04:29:51 PM PDT 24
Finished Jul 01 04:30:28 PM PDT 24
Peak memory 214788 kb
Host smart-4f481aed-ec10-45c7-a7e1-4ad3560a73fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033982725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2033982725
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3756891162
Short name T347
Test name
Test status
Simulation time 5201495057 ps
CPU time 15.55 seconds
Started Jul 01 04:30:00 PM PDT 24
Finished Jul 01 04:30:27 PM PDT 24
Peak memory 217528 kb
Host smart-ac037e16-92d1-415a-b3f5-90dcef2795dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756891162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3756891162
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1304280003
Short name T216
Test name
Test status
Simulation time 27020607277 ps
CPU time 395.09 seconds
Started Jul 01 04:29:51 PM PDT 24
Finished Jul 01 04:36:39 PM PDT 24
Peak memory 240660 kb
Host smart-ec829583-6c74-40ea-a2d0-142c06e7b54f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304280003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1304280003
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3113613136
Short name T341
Test name
Test status
Simulation time 27908649645 ps
CPU time 61.46 seconds
Started Jul 01 04:29:54 PM PDT 24
Finished Jul 01 04:31:07 PM PDT 24
Peak memory 219312 kb
Host smart-fc43ba22-a350-4412-aa22-ef77e147cbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113613136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3113613136
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1909815889
Short name T326
Test name
Test status
Simulation time 13788427451 ps
CPU time 29.4 seconds
Started Jul 01 04:29:47 PM PDT 24
Finished Jul 01 04:30:28 PM PDT 24
Peak memory 219308 kb
Host smart-c64b4c9b-ae69-4c1e-84b9-079d7de9c9d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1909815889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1909815889
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.853338255
Short name T318
Test name
Test status
Simulation time 10675047177 ps
CPU time 23 seconds
Started Jul 01 04:29:49 PM PDT 24
Finished Jul 01 04:30:23 PM PDT 24
Peak memory 217408 kb
Host smart-f252f367-843a-4468-b83b-e59856b02976
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853338255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.853338255
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3978303117
Short name T25
Test name
Test status
Simulation time 121786463571 ps
CPU time 292.66 seconds
Started Jul 01 04:29:57 PM PDT 24
Finished Jul 01 04:35:01 PM PDT 24
Peak memory 235552 kb
Host smart-58450988-0769-4803-ad90-7a5edfb719d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978303117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3978303117
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2716671286
Short name T181
Test name
Test status
Simulation time 26769970760 ps
CPU time 58.94 seconds
Started Jul 01 04:29:59 PM PDT 24
Finished Jul 01 04:31:09 PM PDT 24
Peak memory 219452 kb
Host smart-defa0a1a-444e-42d7-85c5-dc700625a64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716671286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2716671286
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.391184971
Short name T22
Test name
Test status
Simulation time 2008404977 ps
CPU time 20.51 seconds
Started Jul 01 04:30:20 PM PDT 24
Finished Jul 01 04:30:56 PM PDT 24
Peak memory 219300 kb
Host smart-6aef2846-d59f-4945-b7ba-70f64d531ffd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=391184971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.391184971
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1446952128
Short name T12
Test name
Test status
Simulation time 2643935254 ps
CPU time 41.66 seconds
Started Jul 01 04:30:03 PM PDT 24
Finished Jul 01 04:30:58 PM PDT 24
Peak memory 216500 kb
Host smart-cdfefcb4-fc6a-4db1-a73c-6a84d5d8b926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446952128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1446952128
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3376057950
Short name T168
Test name
Test status
Simulation time 9985818919 ps
CPU time 89.67 seconds
Started Jul 01 04:29:47 PM PDT 24
Finished Jul 01 04:31:28 PM PDT 24
Peak memory 219276 kb
Host smart-89419cd8-a406-489d-a35c-5737f39be108
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376057950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3376057950
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2511111861
Short name T49
Test name
Test status
Simulation time 32490910475 ps
CPU time 1255.41 seconds
Started Jul 01 04:29:55 PM PDT 24
Finished Jul 01 04:51:02 PM PDT 24
Peak memory 235740 kb
Host smart-cf3e9590-03ea-42d8-8092-22c4949260d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511111861 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.2511111861
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.465204112
Short name T312
Test name
Test status
Simulation time 2588842402 ps
CPU time 19.18 seconds
Started Jul 01 04:29:14 PM PDT 24
Finished Jul 01 04:29:42 PM PDT 24
Peak memory 217212 kb
Host smart-6fc1eb9d-a02f-4736-89ca-10806276e808
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465204112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.465204112
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1303549244
Short name T268
Test name
Test status
Simulation time 3307060010 ps
CPU time 226.68 seconds
Started Jul 01 04:29:17 PM PDT 24
Finished Jul 01 04:33:13 PM PDT 24
Peak memory 225668 kb
Host smart-26fea38d-5ca1-4e43-9838-8aa3e2f840b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303549244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1303549244
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1586104850
Short name T320
Test name
Test status
Simulation time 8342817450 ps
CPU time 45.3 seconds
Started Jul 01 04:29:39 PM PDT 24
Finished Jul 01 04:30:31 PM PDT 24
Peak memory 219288 kb
Host smart-fc1476e9-2681-4f5a-9c63-3d548e8070f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586104850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1586104850
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3348507483
Short name T323
Test name
Test status
Simulation time 4877897696 ps
CPU time 24.01 seconds
Started Jul 01 04:29:27 PM PDT 24
Finished Jul 01 04:29:58 PM PDT 24
Peak memory 219312 kb
Host smart-4fa7cde7-0a4f-4a61-830e-3679c8603489
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3348507483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3348507483
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3063944483
Short name T329
Test name
Test status
Simulation time 1315683154 ps
CPU time 20.5 seconds
Started Jul 01 04:29:11 PM PDT 24
Finished Jul 01 04:29:41 PM PDT 24
Peak memory 215500 kb
Host smart-5715f969-d2c5-499e-a9a1-7302ab3559d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063944483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3063944483
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3628751063
Short name T251
Test name
Test status
Simulation time 770151859 ps
CPU time 44.97 seconds
Started Jul 01 04:29:08 PM PDT 24
Finished Jul 01 04:30:03 PM PDT 24
Peak memory 219212 kb
Host smart-66a23a03-1a63-47f3-b805-99e082ab60c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628751063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3628751063
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3281146157
Short name T68
Test name
Test status
Simulation time 2787803083 ps
CPU time 16.76 seconds
Started Jul 01 04:29:20 PM PDT 24
Finished Jul 01 04:29:46 PM PDT 24
Peak memory 217160 kb
Host smart-0a22acec-868c-4e2f-b7a5-943fefb9d930
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281146157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3281146157
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2706331811
Short name T303
Test name
Test status
Simulation time 97081635088 ps
CPU time 497.25 seconds
Started Jul 01 04:29:32 PM PDT 24
Finished Jul 01 04:37:55 PM PDT 24
Peak memory 219276 kb
Host smart-27af920c-3400-4a22-9aab-5f78da43444d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706331811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2706331811
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3330049051
Short name T223
Test name
Test status
Simulation time 9023468870 ps
CPU time 31.52 seconds
Started Jul 01 04:29:25 PM PDT 24
Finished Jul 01 04:30:05 PM PDT 24
Peak memory 219308 kb
Host smart-79302efb-1c75-48e1-a2c4-92f5d38bd7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330049051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3330049051
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3931428224
Short name T57
Test name
Test status
Simulation time 3193450202 ps
CPU time 27.23 seconds
Started Jul 01 04:29:06 PM PDT 24
Finished Jul 01 04:29:43 PM PDT 24
Peak memory 211700 kb
Host smart-72bdacae-2b13-4d9a-b878-dbdadbbdca40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3931428224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3931428224
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1813372017
Short name T158
Test name
Test status
Simulation time 5565624028 ps
CPU time 49.68 seconds
Started Jul 01 04:29:10 PM PDT 24
Finished Jul 01 04:30:10 PM PDT 24
Peak memory 216556 kb
Host smart-0c95dff8-1151-4a29-9724-e49505031c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813372017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1813372017
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3234200332
Short name T21
Test name
Test status
Simulation time 774439241 ps
CPU time 31.96 seconds
Started Jul 01 04:29:18 PM PDT 24
Finished Jul 01 04:29:59 PM PDT 24
Peak memory 219236 kb
Host smart-b6cb9e5c-8379-407d-aa76-6db2f0663fe2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234200332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3234200332
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1287548572
Short name T176
Test name
Test status
Simulation time 45807104576 ps
CPU time 23.54 seconds
Started Jul 01 04:29:25 PM PDT 24
Finished Jul 01 04:29:56 PM PDT 24
Peak memory 217524 kb
Host smart-f85d2575-459b-468b-b2df-34c5ca902de9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287548572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1287548572
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3604813148
Short name T138
Test name
Test status
Simulation time 8326608583 ps
CPU time 131.1 seconds
Started Jul 01 04:29:34 PM PDT 24
Finished Jul 01 04:31:51 PM PDT 24
Peak memory 219748 kb
Host smart-66410b8f-d37a-41c3-9f0d-c89a19033101
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604813148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3604813148
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1416981209
Short name T298
Test name
Test status
Simulation time 17641184931 ps
CPU time 45.76 seconds
Started Jul 01 04:29:21 PM PDT 24
Finished Jul 01 04:30:15 PM PDT 24
Peak memory 219292 kb
Host smart-9edf4223-ef6e-4349-80dd-d712c02c3d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416981209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1416981209
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1724523256
Short name T256
Test name
Test status
Simulation time 383801589 ps
CPU time 10.97 seconds
Started Jul 01 04:29:16 PM PDT 24
Finished Jul 01 04:29:37 PM PDT 24
Peak memory 219416 kb
Host smart-d4362e13-cf03-4223-9acc-37726e7776c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1724523256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1724523256
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3671105962
Short name T122
Test name
Test status
Simulation time 5265194324 ps
CPU time 49.61 seconds
Started Jul 01 04:29:10 PM PDT 24
Finished Jul 01 04:30:10 PM PDT 24
Peak memory 216528 kb
Host smart-57c9bbf1-3ade-4702-92ed-dcf3caa16eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671105962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3671105962
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1548193799
Short name T184
Test name
Test status
Simulation time 176073376 ps
CPU time 8.41 seconds
Started Jul 01 04:29:19 PM PDT 24
Finished Jul 01 04:29:36 PM PDT 24
Peak memory 216948 kb
Host smart-7e5ca258-da62-46a1-b08e-650e4dbc1987
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548193799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1548193799
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1228234387
Short name T266
Test name
Test status
Simulation time 9774767088 ps
CPU time 178.71 seconds
Started Jul 01 04:29:16 PM PDT 24
Finished Jul 01 04:32:23 PM PDT 24
Peak memory 238028 kb
Host smart-fed9c6c1-3719-4efa-afa8-4428caadb2f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228234387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1228234387
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3537114115
Short name T253
Test name
Test status
Simulation time 721221515 ps
CPU time 19.26 seconds
Started Jul 01 04:29:29 PM PDT 24
Finished Jul 01 04:29:55 PM PDT 24
Peak memory 219200 kb
Host smart-0a307fa8-431e-4d6e-9739-47929f34ce02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537114115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3537114115
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1274225753
Short name T291
Test name
Test status
Simulation time 3366744348 ps
CPU time 15.68 seconds
Started Jul 01 04:29:22 PM PDT 24
Finished Jul 01 04:29:45 PM PDT 24
Peak memory 219268 kb
Host smart-6b114eea-3058-4036-8358-41d44d767dfe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1274225753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1274225753
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1214317671
Short name T208
Test name
Test status
Simulation time 10545879578 ps
CPU time 59.58 seconds
Started Jul 01 04:29:26 PM PDT 24
Finished Jul 01 04:30:33 PM PDT 24
Peak memory 216304 kb
Host smart-55420729-e745-486f-8672-82a3372d0e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214317671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1214317671
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1973862470
Short name T241
Test name
Test status
Simulation time 12062239817 ps
CPU time 72.38 seconds
Started Jul 01 04:29:27 PM PDT 24
Finished Jul 01 04:30:46 PM PDT 24
Peak memory 219324 kb
Host smart-f066f808-52d8-4e49-a397-ade0ce81fd17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973862470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1973862470
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2754922642
Short name T244
Test name
Test status
Simulation time 8275606692 ps
CPU time 20.39 seconds
Started Jul 01 04:29:20 PM PDT 24
Finished Jul 01 04:29:49 PM PDT 24
Peak memory 217048 kb
Host smart-27f0f366-6a91-4581-927e-f3bc5a2aec55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754922642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2754922642
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.497741183
Short name T321
Test name
Test status
Simulation time 70867850261 ps
CPU time 361.88 seconds
Started Jul 01 04:29:38 PM PDT 24
Finished Jul 01 04:35:45 PM PDT 24
Peak memory 219440 kb
Host smart-69ab236a-f6d7-4fb5-af60-ebbb85309c76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497741183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.497741183
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3173896898
Short name T172
Test name
Test status
Simulation time 16320295793 ps
CPU time 43.82 seconds
Started Jul 01 04:29:15 PM PDT 24
Finished Jul 01 04:30:07 PM PDT 24
Peak memory 219308 kb
Host smart-8d899834-e334-4bc8-8e1f-d2304d9b2a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173896898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3173896898
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2274991352
Short name T177
Test name
Test status
Simulation time 1872555607 ps
CPU time 16.52 seconds
Started Jul 01 04:29:31 PM PDT 24
Finished Jul 01 04:29:53 PM PDT 24
Peak memory 219192 kb
Host smart-bfd1ba73-da15-4f11-af77-26e0065bdfb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2274991352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2274991352
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2229914752
Short name T17
Test name
Test status
Simulation time 360271772 ps
CPU time 20.23 seconds
Started Jul 01 04:29:22 PM PDT 24
Finished Jul 01 04:29:51 PM PDT 24
Peak memory 216140 kb
Host smart-a16d0b6e-3281-4556-b68c-9f9a59514dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229914752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2229914752
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3119335061
Short name T124
Test name
Test status
Simulation time 5362600719 ps
CPU time 57.1 seconds
Started Jul 01 04:29:23 PM PDT 24
Finished Jul 01 04:30:28 PM PDT 24
Peak memory 219264 kb
Host smart-ed68eb05-4035-41e5-914f-c392e5833fff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119335061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3119335061
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.2777096382
Short name T15
Test name
Test status
Simulation time 48035182188 ps
CPU time 818.17 seconds
Started Jul 01 04:29:21 PM PDT 24
Finished Jul 01 04:43:07 PM PDT 24
Peak memory 235676 kb
Host smart-ad7e5bc2-d281-4866-a11a-4fd44d8bf873
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777096382 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.2777096382
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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