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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.25 96.89 92.13 97.68 100.00 98.62 97.30 98.14


Total test records in report: 457
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T299 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2392176819 Jul 02 07:49:45 AM PDT 24 Jul 02 07:50:51 AM PDT 24 25206020843 ps
T300 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3609207572 Jul 02 07:49:35 AM PDT 24 Jul 02 07:49:47 AM PDT 24 723213477 ps
T301 /workspace/coverage/default/34.rom_ctrl_alert_test.1966183980 Jul 02 07:49:45 AM PDT 24 Jul 02 07:50:26 AM PDT 24 15381014493 ps
T302 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2988448906 Jul 02 07:49:36 AM PDT 24 Jul 02 07:49:48 AM PDT 24 478755068 ps
T303 /workspace/coverage/default/9.rom_ctrl_stress_all.1608729060 Jul 02 07:49:25 AM PDT 24 Jul 02 07:49:44 AM PDT 24 429137714 ps
T304 /workspace/coverage/default/40.rom_ctrl_smoke.1699056886 Jul 02 07:49:46 AM PDT 24 Jul 02 07:51:09 AM PDT 24 6524590143 ps
T305 /workspace/coverage/default/17.rom_ctrl_stress_all.547189885 Jul 02 07:49:35 AM PDT 24 Jul 02 07:52:36 AM PDT 24 74030719674 ps
T306 /workspace/coverage/default/5.rom_ctrl_alert_test.45912462 Jul 02 07:49:12 AM PDT 24 Jul 02 07:49:32 AM PDT 24 6824835164 ps
T307 /workspace/coverage/default/7.rom_ctrl_alert_test.2485486169 Jul 02 07:49:08 AM PDT 24 Jul 02 07:49:18 AM PDT 24 169222950 ps
T308 /workspace/coverage/default/8.rom_ctrl_stress_all.305103622 Jul 02 07:49:17 AM PDT 24 Jul 02 07:52:48 AM PDT 24 71905338410 ps
T309 /workspace/coverage/default/4.rom_ctrl_alert_test.2418313293 Jul 02 07:49:23 AM PDT 24 Jul 02 07:49:32 AM PDT 24 174375983 ps
T310 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3271593684 Jul 02 07:49:47 AM PDT 24 Jul 02 07:50:28 AM PDT 24 22606152610 ps
T311 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1813074541 Jul 02 07:49:42 AM PDT 24 Jul 02 08:04:08 AM PDT 24 285655583780 ps
T312 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2648539585 Jul 02 07:49:46 AM PDT 24 Jul 02 07:54:10 AM PDT 24 18873393575 ps
T313 /workspace/coverage/default/19.rom_ctrl_alert_test.4068234512 Jul 02 07:49:39 AM PDT 24 Jul 02 07:50:02 AM PDT 24 5284452852 ps
T314 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.649488589 Jul 02 07:49:46 AM PDT 24 Jul 02 07:50:28 AM PDT 24 7559073898 ps
T315 /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2486336215 Jul 02 07:49:11 AM PDT 24 Jul 02 08:19:42 AM PDT 24 46915285013 ps
T316 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1396979653 Jul 02 07:49:12 AM PDT 24 Jul 02 07:49:28 AM PDT 24 2466440543 ps
T317 /workspace/coverage/default/30.rom_ctrl_alert_test.2734755203 Jul 02 07:49:45 AM PDT 24 Jul 02 07:50:13 AM PDT 24 1749023937 ps
T318 /workspace/coverage/default/49.rom_ctrl_alert_test.2379024486 Jul 02 07:49:56 AM PDT 24 Jul 02 07:50:33 AM PDT 24 3285795639 ps
T319 /workspace/coverage/default/42.rom_ctrl_stress_all.1681772205 Jul 02 07:49:40 AM PDT 24 Jul 02 07:50:11 AM PDT 24 375046682 ps
T27 /workspace/coverage/default/2.rom_ctrl_sec_cm.3426642523 Jul 02 07:49:11 AM PDT 24 Jul 02 07:51:10 AM PDT 24 449479347 ps
T320 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.4077296255 Jul 02 07:49:24 AM PDT 24 Jul 02 07:49:50 AM PDT 24 42405484142 ps
T321 /workspace/coverage/default/16.rom_ctrl_alert_test.512409907 Jul 02 07:49:39 AM PDT 24 Jul 02 07:50:12 AM PDT 24 16756146937 ps
T322 /workspace/coverage/default/37.rom_ctrl_stress_all.2136769617 Jul 02 07:49:41 AM PDT 24 Jul 02 07:51:47 AM PDT 24 12802858461 ps
T323 /workspace/coverage/default/23.rom_ctrl_alert_test.2844928521 Jul 02 07:49:42 AM PDT 24 Jul 02 07:50:19 AM PDT 24 4269904663 ps
T324 /workspace/coverage/default/5.rom_ctrl_smoke.376908449 Jul 02 07:49:19 AM PDT 24 Jul 02 07:49:43 AM PDT 24 2094916074 ps
T325 /workspace/coverage/default/3.rom_ctrl_stress_all.1401554761 Jul 02 07:49:03 AM PDT 24 Jul 02 07:49:40 AM PDT 24 13969751644 ps
T326 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1824608389 Jul 02 07:49:43 AM PDT 24 Jul 02 07:53:24 AM PDT 24 3740167901 ps
T327 /workspace/coverage/default/0.rom_ctrl_stress_all.407471291 Jul 02 07:49:08 AM PDT 24 Jul 02 07:49:43 AM PDT 24 14163553411 ps
T328 /workspace/coverage/default/30.rom_ctrl_stress_all.3728533594 Jul 02 07:49:46 AM PDT 24 Jul 02 07:50:54 AM PDT 24 10108645047 ps
T329 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2080970350 Jul 02 07:49:15 AM PDT 24 Jul 02 08:02:16 AM PDT 24 225145696315 ps
T330 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2788114656 Jul 02 07:49:42 AM PDT 24 Jul 02 07:50:35 AM PDT 24 18839264876 ps
T331 /workspace/coverage/default/4.rom_ctrl_smoke.3137001483 Jul 02 07:49:02 AM PDT 24 Jul 02 07:49:59 AM PDT 24 10205093839 ps
T332 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1106059367 Jul 02 07:49:18 AM PDT 24 Jul 02 07:54:27 AM PDT 24 189419421394 ps
T333 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2267231676 Jul 02 07:49:49 AM PDT 24 Jul 02 07:50:30 AM PDT 24 12939846519 ps
T334 /workspace/coverage/default/39.rom_ctrl_stress_all.1030035736 Jul 02 07:49:41 AM PDT 24 Jul 02 07:50:46 AM PDT 24 5589479068 ps
T335 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.4252488539 Jul 02 07:49:43 AM PDT 24 Jul 02 07:50:22 AM PDT 24 4108003152 ps
T336 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2608313489 Jul 02 07:49:44 AM PDT 24 Jul 02 07:50:02 AM PDT 24 707174071 ps
T337 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1511860639 Jul 02 07:49:39 AM PDT 24 Jul 02 07:49:52 AM PDT 24 186448709 ps
T338 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1733570916 Jul 02 07:49:07 AM PDT 24 Jul 02 07:49:28 AM PDT 24 688424440 ps
T339 /workspace/coverage/default/44.rom_ctrl_smoke.321881149 Jul 02 07:49:43 AM PDT 24 Jul 02 07:50:30 AM PDT 24 5611355546 ps
T340 /workspace/coverage/default/19.rom_ctrl_stress_all.3901564040 Jul 02 07:49:38 AM PDT 24 Jul 02 07:51:00 AM PDT 24 26781555167 ps
T341 /workspace/coverage/default/28.rom_ctrl_stress_all.1943993479 Jul 02 07:49:46 AM PDT 24 Jul 02 07:51:52 AM PDT 24 39490662943 ps
T342 /workspace/coverage/default/33.rom_ctrl_alert_test.3245277977 Jul 02 07:49:41 AM PDT 24 Jul 02 07:49:51 AM PDT 24 174521264 ps
T15 /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.4130244943 Jul 02 07:49:43 AM PDT 24 Jul 02 07:59:25 AM PDT 24 59702716401 ps
T343 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.554297835 Jul 02 07:49:25 AM PDT 24 Jul 02 07:50:01 AM PDT 24 2466466973 ps
T344 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3627375994 Jul 02 07:49:45 AM PDT 24 Jul 02 07:50:14 AM PDT 24 332559670 ps
T345 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2193706590 Jul 02 07:49:42 AM PDT 24 Jul 02 07:50:33 AM PDT 24 16442007569 ps
T346 /workspace/coverage/default/21.rom_ctrl_smoke.4063657092 Jul 02 07:49:38 AM PDT 24 Jul 02 07:50:46 AM PDT 24 8566339293 ps
T347 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.796020726 Jul 02 07:49:03 AM PDT 24 Jul 02 07:52:29 AM PDT 24 8978999219 ps
T348 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3882979205 Jul 02 07:49:10 AM PDT 24 Jul 02 07:49:43 AM PDT 24 7488044999 ps
T349 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1109679034 Jul 02 07:49:51 AM PDT 24 Jul 02 07:50:40 AM PDT 24 6353507811 ps
T350 /workspace/coverage/default/26.rom_ctrl_alert_test.3720293791 Jul 02 07:49:47 AM PDT 24 Jul 02 07:50:15 AM PDT 24 5053856989 ps
T351 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3401545777 Jul 02 07:49:25 AM PDT 24 Jul 02 07:57:53 AM PDT 24 147603797447 ps
T352 /workspace/coverage/default/47.rom_ctrl_smoke.3583315761 Jul 02 07:50:02 AM PDT 24 Jul 02 07:50:55 AM PDT 24 3620937033 ps
T353 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.128606397 Jul 02 07:49:42 AM PDT 24 Jul 02 07:50:19 AM PDT 24 3618019418 ps
T354 /workspace/coverage/default/20.rom_ctrl_stress_all.3237221765 Jul 02 07:49:39 AM PDT 24 Jul 02 07:51:17 AM PDT 24 32860997393 ps
T355 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1700554840 Jul 02 07:49:43 AM PDT 24 Jul 02 08:01:29 AM PDT 24 250578893032 ps
T356 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.4057566059 Jul 02 07:49:53 AM PDT 24 Jul 02 07:50:40 AM PDT 24 5805626132 ps
T357 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3572502855 Jul 02 07:49:46 AM PDT 24 Jul 02 07:50:52 AM PDT 24 27796747549 ps
T358 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.325915171 Jul 02 07:49:43 AM PDT 24 Jul 02 07:55:18 AM PDT 24 57884204312 ps
T58 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1127208581 Jul 02 07:52:23 AM PDT 24 Jul 02 07:53:01 AM PDT 24 15078560659 ps
T59 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1266523424 Jul 02 07:52:05 AM PDT 24 Jul 02 07:52:28 AM PDT 24 8225282573 ps
T359 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2748093731 Jul 02 07:52:20 AM PDT 24 Jul 02 07:52:43 AM PDT 24 1578222165 ps
T360 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1655127035 Jul 02 07:52:14 AM PDT 24 Jul 02 07:52:40 AM PDT 24 1861611149 ps
T361 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3313048156 Jul 02 07:51:54 AM PDT 24 Jul 02 07:52:15 AM PDT 24 3400448957 ps
T60 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.841678884 Jul 02 07:52:05 AM PDT 24 Jul 02 07:53:04 AM PDT 24 1105544620 ps
T362 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.771199393 Jul 02 07:52:06 AM PDT 24 Jul 02 07:52:42 AM PDT 24 4254024549 ps
T66 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1331762543 Jul 02 07:52:13 AM PDT 24 Jul 02 07:52:44 AM PDT 24 15151325125 ps
T363 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.47684908 Jul 02 07:52:22 AM PDT 24 Jul 02 07:52:42 AM PDT 24 5293425030 ps
T364 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1603573524 Jul 02 07:52:03 AM PDT 24 Jul 02 07:52:27 AM PDT 24 10386199195 ps
T97 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1462881368 Jul 02 07:52:09 AM PDT 24 Jul 02 07:52:42 AM PDT 24 14934651076 ps
T67 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2702350310 Jul 02 07:52:04 AM PDT 24 Jul 02 07:53:03 AM PDT 24 21997628403 ps
T98 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2848144502 Jul 02 07:52:24 AM PDT 24 Jul 02 07:52:50 AM PDT 24 1449775904 ps
T55 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.827073372 Jul 02 07:51:57 AM PDT 24 Jul 02 07:53:33 AM PDT 24 2582223235 ps
T68 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3086753004 Jul 02 07:51:59 AM PDT 24 Jul 02 07:52:20 AM PDT 24 16416635363 ps
T365 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.419398382 Jul 02 07:52:11 AM PDT 24 Jul 02 07:52:43 AM PDT 24 3791739229 ps
T366 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.943045773 Jul 02 07:51:59 AM PDT 24 Jul 02 07:52:29 AM PDT 24 13669074841 ps
T103 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2154967246 Jul 02 07:52:04 AM PDT 24 Jul 02 07:52:14 AM PDT 24 2056726185 ps
T56 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4019791832 Jul 02 07:52:10 AM PDT 24 Jul 02 07:53:31 AM PDT 24 1210565604 ps
T69 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2741272559 Jul 02 07:52:05 AM PDT 24 Jul 02 07:52:33 AM PDT 24 5982266897 ps
T70 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.218745981 Jul 02 07:51:50 AM PDT 24 Jul 02 07:52:25 AM PDT 24 11282837934 ps
T71 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1002713572 Jul 02 07:52:23 AM PDT 24 Jul 02 07:53:10 AM PDT 24 724914280 ps
T57 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.546355965 Jul 02 07:52:05 AM PDT 24 Jul 02 07:53:50 AM PDT 24 8310840601 ps
T367 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1021533890 Jul 02 07:52:09 AM PDT 24 Jul 02 07:52:24 AM PDT 24 171649313 ps
T368 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3998783464 Jul 02 07:52:24 AM PDT 24 Jul 02 07:52:49 AM PDT 24 3636163205 ps
T99 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4247061667 Jul 02 07:52:11 AM PDT 24 Jul 02 07:52:51 AM PDT 24 2852223922 ps
T369 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1024762363 Jul 02 07:52:08 AM PDT 24 Jul 02 07:52:30 AM PDT 24 1954671236 ps
T106 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3973219764 Jul 02 07:52:22 AM PDT 24 Jul 02 07:54:04 AM PDT 24 3164002317 ps
T72 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3541659959 Jul 02 07:52:13 AM PDT 24 Jul 02 07:52:53 AM PDT 24 6256352813 ps
T105 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3601253749 Jul 02 07:52:01 AM PDT 24 Jul 02 07:54:51 AM PDT 24 2898752214 ps
T370 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.502090232 Jul 02 07:52:06 AM PDT 24 Jul 02 07:52:35 AM PDT 24 13306626174 ps
T371 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2893260287 Jul 02 07:52:11 AM PDT 24 Jul 02 07:52:41 AM PDT 24 2744664412 ps
T372 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.964914620 Jul 02 07:52:23 AM PDT 24 Jul 02 07:52:59 AM PDT 24 5488443657 ps
T100 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1813891030 Jul 02 07:52:12 AM PDT 24 Jul 02 07:52:27 AM PDT 24 987486385 ps
T373 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2445453368 Jul 02 07:52:00 AM PDT 24 Jul 02 07:52:21 AM PDT 24 904441493 ps
T374 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3762883174 Jul 02 07:52:06 AM PDT 24 Jul 02 07:53:35 AM PDT 24 6092422438 ps
T375 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2525348809 Jul 02 07:52:05 AM PDT 24 Jul 02 07:52:22 AM PDT 24 347474193 ps
T73 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3209668684 Jul 02 07:52:06 AM PDT 24 Jul 02 07:52:33 AM PDT 24 5842812302 ps
T81 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3901805363 Jul 02 07:51:58 AM PDT 24 Jul 02 07:53:12 AM PDT 24 5658534860 ps
T101 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3927406953 Jul 02 07:52:18 AM PDT 24 Jul 02 07:52:28 AM PDT 24 660284700 ps
T376 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3829934236 Jul 02 07:52:17 AM PDT 24 Jul 02 07:52:45 AM PDT 24 9457144426 ps
T377 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3993000337 Jul 02 07:52:14 AM PDT 24 Jul 02 07:52:30 AM PDT 24 3415497751 ps
T112 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.385763257 Jul 02 07:52:02 AM PDT 24 Jul 02 07:54:41 AM PDT 24 6410336203 ps
T82 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3198481962 Jul 02 07:52:01 AM PDT 24 Jul 02 07:52:30 AM PDT 24 3301984843 ps
T83 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3168945557 Jul 02 07:52:18 AM PDT 24 Jul 02 07:53:20 AM PDT 24 12385819567 ps
T378 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3625787562 Jul 02 07:52:09 AM PDT 24 Jul 02 07:52:25 AM PDT 24 2405372295 ps
T84 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3188290155 Jul 02 07:52:21 AM PDT 24 Jul 02 07:52:30 AM PDT 24 331813930 ps
T379 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3285112954 Jul 02 07:52:20 AM PDT 24 Jul 02 07:52:40 AM PDT 24 655284371 ps
T380 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1197413315 Jul 02 07:52:20 AM PDT 24 Jul 02 07:52:48 AM PDT 24 4748380241 ps
T85 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2059739713 Jul 02 07:52:13 AM PDT 24 Jul 02 07:52:23 AM PDT 24 177869851 ps
T381 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2817739856 Jul 02 07:51:54 AM PDT 24 Jul 02 07:52:16 AM PDT 24 1530806129 ps
T102 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.105663022 Jul 02 07:52:16 AM PDT 24 Jul 02 07:52:50 AM PDT 24 23591928766 ps
T382 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.771342222 Jul 02 07:52:27 AM PDT 24 Jul 02 07:53:05 AM PDT 24 4596338966 ps
T383 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2610960186 Jul 02 07:52:00 AM PDT 24 Jul 02 07:52:14 AM PDT 24 1963723611 ps
T384 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1196720102 Jul 02 07:52:05 AM PDT 24 Jul 02 07:52:35 AM PDT 24 7612225628 ps
T385 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3118253243 Jul 02 07:52:09 AM PDT 24 Jul 02 07:52:18 AM PDT 24 338996756 ps
T107 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1965459486 Jul 02 07:52:16 AM PDT 24 Jul 02 07:55:10 AM PDT 24 5560907879 ps
T386 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1119815963 Jul 02 07:52:00 AM PDT 24 Jul 02 07:52:18 AM PDT 24 5956737456 ps
T387 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2551189279 Jul 02 07:52:05 AM PDT 24 Jul 02 07:52:39 AM PDT 24 3194733358 ps
T388 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2495307850 Jul 02 07:52:03 AM PDT 24 Jul 02 07:52:31 AM PDT 24 12701247000 ps
T389 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3274414257 Jul 02 07:52:23 AM PDT 24 Jul 02 07:52:50 AM PDT 24 17075047692 ps
T390 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.697923156 Jul 02 07:52:22 AM PDT 24 Jul 02 07:52:40 AM PDT 24 3058204214 ps
T391 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3810508661 Jul 02 07:52:03 AM PDT 24 Jul 02 07:52:15 AM PDT 24 1870555836 ps
T392 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1794491262 Jul 02 07:51:53 AM PDT 24 Jul 02 07:52:26 AM PDT 24 12752444716 ps
T393 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3927302414 Jul 02 07:52:24 AM PDT 24 Jul 02 07:52:57 AM PDT 24 25928771782 ps
T394 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2522355381 Jul 02 07:52:24 AM PDT 24 Jul 02 07:53:04 AM PDT 24 17419872929 ps
T395 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1462996939 Jul 02 07:52:24 AM PDT 24 Jul 02 07:52:57 AM PDT 24 4184136712 ps
T396 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1883641395 Jul 02 07:51:53 AM PDT 24 Jul 02 07:52:15 AM PDT 24 7010301869 ps
T397 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3198191608 Jul 02 07:52:05 AM PDT 24 Jul 02 07:52:27 AM PDT 24 8209857065 ps
T398 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2353366107 Jul 02 07:52:08 AM PDT 24 Jul 02 07:52:19 AM PDT 24 197708794 ps
T399 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1706408351 Jul 02 07:52:11 AM PDT 24 Jul 02 07:53:47 AM PDT 24 4350561767 ps
T400 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2317208929 Jul 02 07:52:03 AM PDT 24 Jul 02 07:52:31 AM PDT 24 3060030824 ps
T91 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2121677362 Jul 02 07:52:08 AM PDT 24 Jul 02 07:52:41 AM PDT 24 4264106984 ps
T401 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2338748502 Jul 02 07:52:18 AM PDT 24 Jul 02 07:55:12 AM PDT 24 3797626477 ps
T402 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.616372102 Jul 02 07:52:06 AM PDT 24 Jul 02 07:52:26 AM PDT 24 3736824816 ps
T403 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.564362505 Jul 02 07:52:05 AM PDT 24 Jul 02 07:52:33 AM PDT 24 6128971032 ps
T404 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.192290613 Jul 02 07:51:59 AM PDT 24 Jul 02 07:52:20 AM PDT 24 1190015351 ps
T89 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1050465764 Jul 02 07:52:26 AM PDT 24 Jul 02 07:54:23 AM PDT 24 11604802303 ps
T405 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4034113279 Jul 02 07:51:53 AM PDT 24 Jul 02 07:52:26 AM PDT 24 3292274195 ps
T406 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1331231823 Jul 02 07:52:16 AM PDT 24 Jul 02 07:52:28 AM PDT 24 750641236 ps
T407 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1699803824 Jul 02 07:51:54 AM PDT 24 Jul 02 07:52:09 AM PDT 24 344830391 ps
T408 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3149738296 Jul 02 07:51:56 AM PDT 24 Jul 02 07:52:23 AM PDT 24 4668207806 ps
T409 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.942425937 Jul 02 07:52:14 AM PDT 24 Jul 02 07:52:43 AM PDT 24 3474129120 ps
T410 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3337853762 Jul 02 07:52:11 AM PDT 24 Jul 02 07:52:21 AM PDT 24 369225464 ps
T411 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3422923633 Jul 02 07:52:22 AM PDT 24 Jul 02 07:52:51 AM PDT 24 11563224896 ps
T92 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1778745906 Jul 02 07:52:13 AM PDT 24 Jul 02 07:53:10 AM PDT 24 1341966868 ps
T412 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4121134477 Jul 02 07:52:05 AM PDT 24 Jul 02 07:52:14 AM PDT 24 174285673 ps
T413 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1615483183 Jul 02 07:52:05 AM PDT 24 Jul 02 07:52:30 AM PDT 24 2629573735 ps
T108 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1066441721 Jul 02 07:52:28 AM PDT 24 Jul 02 07:55:16 AM PDT 24 372490934 ps
T414 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3503231401 Jul 02 07:52:03 AM PDT 24 Jul 02 07:52:16 AM PDT 24 506118731 ps
T415 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.271683824 Jul 02 07:51:59 AM PDT 24 Jul 02 07:53:51 AM PDT 24 46710533874 ps
T416 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1190753790 Jul 02 07:52:02 AM PDT 24 Jul 02 07:52:24 AM PDT 24 8499484076 ps
T417 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3849990542 Jul 02 07:52:22 AM PDT 24 Jul 02 07:52:43 AM PDT 24 6168095999 ps
T418 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.478898582 Jul 02 07:52:24 AM PDT 24 Jul 02 07:53:05 AM PDT 24 3761702437 ps
T419 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2661085091 Jul 02 07:52:04 AM PDT 24 Jul 02 07:52:28 AM PDT 24 48974034641 ps
T109 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2948687573 Jul 02 07:52:24 AM PDT 24 Jul 02 07:53:53 AM PDT 24 268123956 ps
T420 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2547324340 Jul 02 07:52:08 AM PDT 24 Jul 02 07:52:53 AM PDT 24 4058804797 ps
T421 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.759697194 Jul 02 07:52:06 AM PDT 24 Jul 02 07:52:43 AM PDT 24 8190210637 ps
T90 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3631262090 Jul 02 07:52:14 AM PDT 24 Jul 02 07:53:50 AM PDT 24 10058740480 ps
T111 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2818685728 Jul 02 07:52:26 AM PDT 24 Jul 02 07:53:58 AM PDT 24 2431611842 ps
T422 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3946065782 Jul 02 07:52:24 AM PDT 24 Jul 02 07:52:40 AM PDT 24 256236778 ps
T423 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1800318667 Jul 02 07:52:08 AM PDT 24 Jul 02 07:52:25 AM PDT 24 687507496 ps
T424 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2532318570 Jul 02 07:51:57 AM PDT 24 Jul 02 07:52:15 AM PDT 24 500948565 ps
T110 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3977435335 Jul 02 07:52:13 AM PDT 24 Jul 02 07:55:08 AM PDT 24 6525658122 ps
T425 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1005486760 Jul 02 07:51:49 AM PDT 24 Jul 02 07:52:16 AM PDT 24 31195941147 ps
T426 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.334337981 Jul 02 07:52:03 AM PDT 24 Jul 02 07:52:32 AM PDT 24 7246056016 ps
T427 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3775101143 Jul 02 07:52:23 AM PDT 24 Jul 02 07:52:40 AM PDT 24 344028251 ps
T428 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3173132257 Jul 02 07:52:06 AM PDT 24 Jul 02 07:52:43 AM PDT 24 4023252648 ps
T86 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2954587094 Jul 02 07:52:02 AM PDT 24 Jul 02 07:52:12 AM PDT 24 688189700 ps
T429 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.194493916 Jul 02 07:52:16 AM PDT 24 Jul 02 07:52:46 AM PDT 24 7303606595 ps
T430 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1297662579 Jul 02 07:52:19 AM PDT 24 Jul 02 07:52:37 AM PDT 24 2621174629 ps
T431 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1199393903 Jul 02 07:52:11 AM PDT 24 Jul 02 07:54:45 AM PDT 24 305022164 ps
T432 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1910135873 Jul 02 07:52:01 AM PDT 24 Jul 02 07:52:34 AM PDT 24 45139233469 ps
T93 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.910829026 Jul 02 07:52:27 AM PDT 24 Jul 02 07:54:03 AM PDT 24 15772676121 ps
T433 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.264968850 Jul 02 07:52:13 AM PDT 24 Jul 02 07:52:42 AM PDT 24 3268341035 ps
T434 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4195845133 Jul 02 07:52:13 AM PDT 24 Jul 02 07:52:29 AM PDT 24 524138424 ps
T435 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3298626696 Jul 02 07:52:28 AM PDT 24 Jul 02 07:53:09 AM PDT 24 5962266879 ps
T436 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2536615750 Jul 02 07:52:03 AM PDT 24 Jul 02 07:52:35 AM PDT 24 4073350202 ps
T437 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2379215118 Jul 02 07:52:08 AM PDT 24 Jul 02 07:52:21 AM PDT 24 660221635 ps
T94 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3430317733 Jul 02 07:52:31 AM PDT 24 Jul 02 07:54:01 AM PDT 24 6588974304 ps
T438 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3319035386 Jul 02 07:52:05 AM PDT 24 Jul 02 07:54:56 AM PDT 24 3141517153 ps
T439 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2473885072 Jul 02 07:52:08 AM PDT 24 Jul 02 07:52:36 AM PDT 24 3617405416 ps
T440 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.920593195 Jul 02 07:52:16 AM PDT 24 Jul 02 07:52:45 AM PDT 24 13744605347 ps
T113 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2411669042 Jul 02 07:52:22 AM PDT 24 Jul 02 07:55:02 AM PDT 24 2557568072 ps
T441 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1957282514 Jul 02 07:51:57 AM PDT 24 Jul 02 07:55:13 AM PDT 24 25102514753 ps
T96 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.537601440 Jul 02 07:52:15 AM PDT 24 Jul 02 07:52:54 AM PDT 24 3617398448 ps
T95 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2822577013 Jul 02 07:52:13 AM PDT 24 Jul 02 07:54:35 AM PDT 24 26226919513 ps
T442 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.418374017 Jul 02 07:51:58 AM PDT 24 Jul 02 07:52:31 AM PDT 24 7593669811 ps
T443 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.55094834 Jul 02 07:52:24 AM PDT 24 Jul 02 07:52:44 AM PDT 24 2298291953 ps
T444 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2799517596 Jul 02 07:52:11 AM PDT 24 Jul 02 07:52:50 AM PDT 24 2553379246 ps
T445 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3035630588 Jul 02 07:52:06 AM PDT 24 Jul 02 07:52:32 AM PDT 24 15503556287 ps
T87 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3516238259 Jul 02 07:52:01 AM PDT 24 Jul 02 07:52:31 AM PDT 24 7022875753 ps
T446 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1231108732 Jul 02 07:52:02 AM PDT 24 Jul 02 07:52:12 AM PDT 24 1831914678 ps
T447 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3187588686 Jul 02 07:52:01 AM PDT 24 Jul 02 07:54:49 AM PDT 24 9679885655 ps
T88 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3716702461 Jul 02 07:52:07 AM PDT 24 Jul 02 07:52:31 AM PDT 24 7533254193 ps
T448 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2260805204 Jul 02 07:52:25 AM PDT 24 Jul 02 07:52:47 AM PDT 24 345565118 ps
T449 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3917387431 Jul 02 07:52:16 AM PDT 24 Jul 02 07:55:13 AM PDT 24 5482440095 ps
T450 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.4080288369 Jul 02 07:52:22 AM PDT 24 Jul 02 07:52:33 AM PDT 24 691318946 ps
T451 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3271173477 Jul 02 07:52:09 AM PDT 24 Jul 02 07:52:31 AM PDT 24 14256269461 ps
T452 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.631438237 Jul 02 07:52:07 AM PDT 24 Jul 02 07:52:28 AM PDT 24 8499620914 ps
T453 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2083747871 Jul 02 07:52:06 AM PDT 24 Jul 02 07:53:03 AM PDT 24 4258876205 ps
T454 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1388006863 Jul 02 07:52:00 AM PDT 24 Jul 02 07:53:28 AM PDT 24 4149827515 ps
T455 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2885516307 Jul 02 07:52:03 AM PDT 24 Jul 02 07:52:19 AM PDT 24 500061335 ps
T456 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.84314225 Jul 02 07:52:26 AM PDT 24 Jul 02 07:53:01 AM PDT 24 2456009092 ps
T457 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3341502161 Jul 02 07:51:56 AM PDT 24 Jul 02 07:53:37 AM PDT 24 2746322790 ps

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.3123533437
Short name T8
Test name
Test status
Simulation time 48025254520 ps
CPU time 2051.8 seconds
Started Jul 02 07:49:38 AM PDT 24
Finished Jul 02 08:23:52 AM PDT 24
Peak memory 240496 kb
Host smart-40a92745-bd57-45cc-b28c-bc26ca910442
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123533437 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.3123533437
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.154802300
Short name T7
Test name
Test status
Simulation time 758322872087 ps
CPU time 500.76 seconds
Started Jul 02 07:50:00 AM PDT 24
Finished Jul 02 07:58:26 AM PDT 24
Peak memory 234528 kb
Host smart-f7e6d48e-eddc-4a51-9bc5-26a88e165b58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154802300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.154802300
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3601253749
Short name T105
Test name
Test status
Simulation time 2898752214 ps
CPU time 167.91 seconds
Started Jul 02 07:52:01 AM PDT 24
Finished Jul 02 07:54:51 AM PDT 24
Peak memory 213952 kb
Host smart-0d39fb82-b967-405a-8448-5008964aaca5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601253749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3601253749
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2538128018
Short name T37
Test name
Test status
Simulation time 12015215919 ps
CPU time 210.38 seconds
Started Jul 02 07:49:35 AM PDT 24
Finished Jul 02 07:53:07 AM PDT 24
Peak memory 224764 kb
Host smart-e94c7a1b-cb1c-490b-be6d-986bec72b8c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538128018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2538128018
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1432548705
Short name T16
Test name
Test status
Simulation time 4011027457 ps
CPU time 43.16 seconds
Started Jul 02 07:49:29 AM PDT 24
Finished Jul 02 07:50:14 AM PDT 24
Peak memory 215564 kb
Host smart-1d535895-32e0-4cc6-ae9e-cc8e63013c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432548705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1432548705
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2998933618
Short name T23
Test name
Test status
Simulation time 7619586437 ps
CPU time 239.17 seconds
Started Jul 02 07:49:07 AM PDT 24
Finished Jul 02 07:53:07 AM PDT 24
Peak memory 238268 kb
Host smart-785d384b-4fb0-4c4c-9b6d-c284f98f8a13
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998933618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2998933618
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.841678884
Short name T60
Test name
Test status
Simulation time 1105544620 ps
CPU time 57.08 seconds
Started Jul 02 07:52:05 AM PDT 24
Finished Jul 02 07:53:04 AM PDT 24
Peak memory 214000 kb
Host smart-78ec2b20-da3a-4d9a-b917-b2195470e731
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841678884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.841678884
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1066441721
Short name T108
Test name
Test status
Simulation time 372490934 ps
CPU time 155.37 seconds
Started Jul 02 07:52:28 AM PDT 24
Finished Jul 02 07:55:16 AM PDT 24
Peak memory 213816 kb
Host smart-a0d5c2ce-39fc-487a-9ed2-bfd06607dce0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066441721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1066441721
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.252970286
Short name T32
Test name
Test status
Simulation time 3397248319 ps
CPU time 28.54 seconds
Started Jul 02 07:49:05 AM PDT 24
Finished Jul 02 07:49:35 AM PDT 24
Peak memory 217068 kb
Host smart-00535ddb-b974-46e4-b383-fb1022685f1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252970286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.252970286
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1917521836
Short name T114
Test name
Test status
Simulation time 5775332215 ps
CPU time 54.85 seconds
Started Jul 02 07:49:33 AM PDT 24
Finished Jul 02 07:50:29 AM PDT 24
Peak memory 219376 kb
Host smart-8caf33fc-d68b-408f-8e73-e54cca4df98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917521836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1917521836
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1733570916
Short name T338
Test name
Test status
Simulation time 688424440 ps
CPU time 19.5 seconds
Started Jul 02 07:49:07 AM PDT 24
Finished Jul 02 07:49:28 AM PDT 24
Peak memory 219232 kb
Host smart-dd6a475b-7af2-46ac-b149-e450572be40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733570916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1733570916
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2148676701
Short name T45
Test name
Test status
Simulation time 8666115601 ps
CPU time 68.96 seconds
Started Jul 02 07:49:39 AM PDT 24
Finished Jul 02 07:50:49 AM PDT 24
Peak memory 219240 kb
Host smart-3878dd0b-c228-4d8c-8882-18bd3cf559a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148676701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2148676701
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2818685728
Short name T111
Test name
Test status
Simulation time 2431611842 ps
CPU time 80.25 seconds
Started Jul 02 07:52:26 AM PDT 24
Finished Jul 02 07:53:58 AM PDT 24
Peak memory 213272 kb
Host smart-5e7447b2-7834-41b7-9780-a9000fb0c8a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818685728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2818685728
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3168945557
Short name T83
Test name
Test status
Simulation time 12385819567 ps
CPU time 61 seconds
Started Jul 02 07:52:18 AM PDT 24
Finished Jul 02 07:53:20 AM PDT 24
Peak memory 213880 kb
Host smart-d9fe146e-09b3-4b8f-9fa0-2ac1119eb3b0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168945557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3168945557
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3749544712
Short name T77
Test name
Test status
Simulation time 7260626076 ps
CPU time 66.17 seconds
Started Jul 02 07:49:17 AM PDT 24
Finished Jul 02 07:50:25 AM PDT 24
Peak memory 216864 kb
Host smart-d642ef5e-b927-474a-8625-102930111b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749544712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3749544712
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2338748502
Short name T401
Test name
Test status
Simulation time 3797626477 ps
CPU time 172.64 seconds
Started Jul 02 07:52:18 AM PDT 24
Finished Jul 02 07:55:12 AM PDT 24
Peak memory 213856 kb
Host smart-28138b16-e6f9-49eb-a68d-b91e83dc1c33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338748502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2338748502
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.4130244943
Short name T15
Test name
Test status
Simulation time 59702716401 ps
CPU time 573.96 seconds
Started Jul 02 07:49:43 AM PDT 24
Finished Jul 02 07:59:25 AM PDT 24
Peak memory 235744 kb
Host smart-86d07434-ce3b-42e1-a89c-fcef8a6663d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130244943 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.4130244943
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3086753004
Short name T68
Test name
Test status
Simulation time 16416635363 ps
CPU time 18 seconds
Started Jul 02 07:51:59 AM PDT 24
Finished Jul 02 07:52:20 AM PDT 24
Peak memory 212004 kb
Host smart-88164d54-be63-47ae-8fb1-e9cf01937175
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086753004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3086753004
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2817739856
Short name T381
Test name
Test status
Simulation time 1530806129 ps
CPU time 18.3 seconds
Started Jul 02 07:51:54 AM PDT 24
Finished Jul 02 07:52:16 AM PDT 24
Peak memory 210672 kb
Host smart-2d7dc6d9-a19c-4e70-a197-860726eaae94
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817739856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2817739856
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2532318570
Short name T424
Test name
Test status
Simulation time 500948565 ps
CPU time 15.08 seconds
Started Jul 02 07:51:57 AM PDT 24
Finished Jul 02 07:52:15 AM PDT 24
Peak memory 210680 kb
Host smart-4acbc62e-9daf-4f38-8ed2-630022521da1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532318570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2532318570
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3271173477
Short name T451
Test name
Test status
Simulation time 14256269461 ps
CPU time 21.46 seconds
Started Jul 02 07:52:09 AM PDT 24
Finished Jul 02 07:52:31 AM PDT 24
Peak memory 216412 kb
Host smart-68c710ad-ba0c-4157-8a91-f0c944feb31b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271173477 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3271173477
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3198191608
Short name T397
Test name
Test status
Simulation time 8209857065 ps
CPU time 20.26 seconds
Started Jul 02 07:52:05 AM PDT 24
Finished Jul 02 07:52:27 AM PDT 24
Peak memory 212416 kb
Host smart-0550b901-9617-4cf8-9aa9-213da6daf8c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198191608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3198191608
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4034113279
Short name T405
Test name
Test status
Simulation time 3292274195 ps
CPU time 28.66 seconds
Started Jul 02 07:51:53 AM PDT 24
Finished Jul 02 07:52:26 AM PDT 24
Peak memory 210608 kb
Host smart-2c3e40ed-7f55-4962-a413-d25d29bb6d5e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034113279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.4034113279
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2495307850
Short name T388
Test name
Test status
Simulation time 12701247000 ps
CPU time 26.55 seconds
Started Jul 02 07:52:03 AM PDT 24
Finished Jul 02 07:52:31 AM PDT 24
Peak memory 210612 kb
Host smart-aa1c52b0-a151-4204-8753-f42cbaff2923
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495307850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2495307850
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1388006863
Short name T454
Test name
Test status
Simulation time 4149827515 ps
CPU time 85.65 seconds
Started Jul 02 07:52:00 AM PDT 24
Finished Jul 02 07:53:28 AM PDT 24
Peak memory 215764 kb
Host smart-ce2e8163-d2e0-4f38-89ab-c379f597420b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388006863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1388006863
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.218745981
Short name T70
Test name
Test status
Simulation time 11282837934 ps
CPU time 29.98 seconds
Started Jul 02 07:51:50 AM PDT 24
Finished Jul 02 07:52:25 AM PDT 24
Peak memory 212540 kb
Host smart-cf86232a-3b29-46c5-96d0-b3ef35e224d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218745981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.218745981
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1005486760
Short name T425
Test name
Test status
Simulation time 31195941147 ps
CPU time 22.47 seconds
Started Jul 02 07:51:49 AM PDT 24
Finished Jul 02 07:52:16 AM PDT 24
Peak memory 218696 kb
Host smart-2653adda-6a77-4916-80eb-147b2cb19360
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005486760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1005486760
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3187588686
Short name T447
Test name
Test status
Simulation time 9679885655 ps
CPU time 166 seconds
Started Jul 02 07:52:01 AM PDT 24
Finished Jul 02 07:54:49 AM PDT 24
Peak memory 214284 kb
Host smart-c67171c0-d306-457b-8bf5-32d4daa6255a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187588686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3187588686
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3625787562
Short name T378
Test name
Test status
Simulation time 2405372295 ps
CPU time 15.66 seconds
Started Jul 02 07:52:09 AM PDT 24
Finished Jul 02 07:52:25 AM PDT 24
Peak memory 211296 kb
Host smart-be37f660-f586-49dc-b008-b7cc9e974042
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625787562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3625787562
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.771199393
Short name T362
Test name
Test status
Simulation time 4254024549 ps
CPU time 34.27 seconds
Started Jul 02 07:52:06 AM PDT 24
Finished Jul 02 07:52:42 AM PDT 24
Peak memory 210740 kb
Host smart-fb7b2c75-a060-40ab-9048-6eba022b7b15
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771199393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.771199393
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1699803824
Short name T407
Test name
Test status
Simulation time 344830391 ps
CPU time 11.45 seconds
Started Jul 02 07:51:54 AM PDT 24
Finished Jul 02 07:52:09 AM PDT 24
Peak memory 211432 kb
Host smart-4cc7765e-65b9-4e9d-9cd7-b773e8825abc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699803824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1699803824
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1190753790
Short name T416
Test name
Test status
Simulation time 8499484076 ps
CPU time 20.83 seconds
Started Jul 02 07:52:02 AM PDT 24
Finished Jul 02 07:52:24 AM PDT 24
Peak memory 215184 kb
Host smart-e94ef493-e742-4436-8691-c26d0570548f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190753790 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1190753790
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3198481962
Short name T82
Test name
Test status
Simulation time 3301984843 ps
CPU time 26.9 seconds
Started Jul 02 07:52:01 AM PDT 24
Finished Jul 02 07:52:30 AM PDT 24
Peak memory 211496 kb
Host smart-0d85cc0c-e504-4aa4-bf6d-ab76fc60ba8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198481962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3198481962
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2610960186
Short name T383
Test name
Test status
Simulation time 1963723611 ps
CPU time 11.52 seconds
Started Jul 02 07:52:00 AM PDT 24
Finished Jul 02 07:52:14 AM PDT 24
Peak memory 210444 kb
Host smart-a6a71b5a-c660-4ee0-b061-9160708e6ab7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610960186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2610960186
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3149738296
Short name T408
Test name
Test status
Simulation time 4668207806 ps
CPU time 24.14 seconds
Started Jul 02 07:51:56 AM PDT 24
Finished Jul 02 07:52:23 AM PDT 24
Peak memory 210556 kb
Host smart-dd1002bc-8056-48e5-90f5-b3e24e100613
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149738296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3149738296
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3901805363
Short name T81
Test name
Test status
Simulation time 5658534860 ps
CPU time 71.15 seconds
Started Jul 02 07:51:58 AM PDT 24
Finished Jul 02 07:53:12 AM PDT 24
Peak memory 214024 kb
Host smart-369cd5d2-802d-4c23-af14-032af7660fa2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901805363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3901805363
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1910135873
Short name T432
Test name
Test status
Simulation time 45139233469 ps
CPU time 30.57 seconds
Started Jul 02 07:52:01 AM PDT 24
Finished Jul 02 07:52:34 AM PDT 24
Peak memory 212572 kb
Host smart-42cb40c8-7d29-44da-8369-d2c20dcececd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910135873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1910135873
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3313048156
Short name T361
Test name
Test status
Simulation time 3400448957 ps
CPU time 16.9 seconds
Started Jul 02 07:51:54 AM PDT 24
Finished Jul 02 07:52:15 AM PDT 24
Peak memory 218992 kb
Host smart-3c25f0ed-6c4f-48cc-9835-ee8f9e5d6c19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313048156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3313048156
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.827073372
Short name T55
Test name
Test status
Simulation time 2582223235 ps
CPU time 92.92 seconds
Started Jul 02 07:51:57 AM PDT 24
Finished Jul 02 07:53:33 AM PDT 24
Peak memory 218832 kb
Host smart-aa71f8c6-37f6-4137-bba0-a7aa83d22822
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827073372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.827073372
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1127208581
Short name T58
Test name
Test status
Simulation time 15078560659 ps
CPU time 30.52 seconds
Started Jul 02 07:52:23 AM PDT 24
Finished Jul 02 07:53:01 AM PDT 24
Peak memory 217364 kb
Host smart-163b16a5-327a-433c-9d66-1fe26985a8c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127208581 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1127208581
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2536615750
Short name T436
Test name
Test status
Simulation time 4073350202 ps
CPU time 30.71 seconds
Started Jul 02 07:52:03 AM PDT 24
Finished Jul 02 07:52:35 AM PDT 24
Peak memory 211344 kb
Host smart-1a7b92aa-41a4-44d5-9809-eb2c8d9bdeb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536615750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2536615750
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4121134477
Short name T412
Test name
Test status
Simulation time 174285673 ps
CPU time 8.27 seconds
Started Jul 02 07:52:05 AM PDT 24
Finished Jul 02 07:52:14 AM PDT 24
Peak memory 210928 kb
Host smart-d94238aa-3767-46c2-846d-1c019f6f3fa2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121134477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.4121134477
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1800318667
Short name T423
Test name
Test status
Simulation time 687507496 ps
CPU time 16.72 seconds
Started Jul 02 07:52:08 AM PDT 24
Finished Jul 02 07:52:25 AM PDT 24
Peak memory 217620 kb
Host smart-effd5e9d-35c2-464a-956d-33d0cab9b4f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800318667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1800318667
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2551189279
Short name T387
Test name
Test status
Simulation time 3194733358 ps
CPU time 27.72 seconds
Started Jul 02 07:52:05 AM PDT 24
Finished Jul 02 07:52:39 AM PDT 24
Peak memory 216036 kb
Host smart-cf0eb309-c0f1-4f2a-8261-3d9c7d5d0dc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551189279 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2551189279
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.502090232
Short name T370
Test name
Test status
Simulation time 13306626174 ps
CPU time 27.4 seconds
Started Jul 02 07:52:06 AM PDT 24
Finished Jul 02 07:52:35 AM PDT 24
Peak memory 212280 kb
Host smart-9882021f-5ec0-455c-b39b-627946a29fcd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502090232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.502090232
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2702350310
Short name T67
Test name
Test status
Simulation time 21997628403 ps
CPU time 57.73 seconds
Started Jul 02 07:52:04 AM PDT 24
Finished Jul 02 07:53:03 AM PDT 24
Peak memory 213876 kb
Host smart-30701378-f02e-420d-b862-72b1986cf8d2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702350310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2702350310
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1813891030
Short name T100
Test name
Test status
Simulation time 987486385 ps
CPU time 14.66 seconds
Started Jul 02 07:52:12 AM PDT 24
Finished Jul 02 07:52:27 AM PDT 24
Peak memory 211016 kb
Host smart-310cc66c-e6ea-4a3b-ac4e-7493cbfd4b69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813891030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1813891030
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3998783464
Short name T368
Test name
Test status
Simulation time 3636163205 ps
CPU time 17.13 seconds
Started Jul 02 07:52:24 AM PDT 24
Finished Jul 02 07:52:49 AM PDT 24
Peak memory 218292 kb
Host smart-ad607be2-8fe8-4a80-8fcc-31245451469d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998783464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3998783464
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.546355965
Short name T57
Test name
Test status
Simulation time 8310840601 ps
CPU time 103.68 seconds
Started Jul 02 07:52:05 AM PDT 24
Finished Jul 02 07:53:50 AM PDT 24
Peak memory 213972 kb
Host smart-1d005cb7-38ed-4a2f-a3a4-edb97d8f9ed2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546355965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.546355965
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.419398382
Short name T365
Test name
Test status
Simulation time 3791739229 ps
CPU time 30.39 seconds
Started Jul 02 07:52:11 AM PDT 24
Finished Jul 02 07:52:43 AM PDT 24
Peak memory 217852 kb
Host smart-294a086a-bc75-4905-b292-c7236be28542
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419398382 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.419398382
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.759697194
Short name T421
Test name
Test status
Simulation time 8190210637 ps
CPU time 31.48 seconds
Started Jul 02 07:52:06 AM PDT 24
Finished Jul 02 07:52:43 AM PDT 24
Peak memory 212036 kb
Host smart-adb4c818-4604-467d-a4c1-c06b0436a055
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759697194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.759697194
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3541659959
Short name T72
Test name
Test status
Simulation time 6256352813 ps
CPU time 38.19 seconds
Started Jul 02 07:52:13 AM PDT 24
Finished Jul 02 07:52:53 AM PDT 24
Peak memory 214132 kb
Host smart-984790f5-5cbd-4e76-b2b6-1f03b2b4d065
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541659959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3541659959
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3422923633
Short name T411
Test name
Test status
Simulation time 11563224896 ps
CPU time 24.22 seconds
Started Jul 02 07:52:22 AM PDT 24
Finished Jul 02 07:52:51 AM PDT 24
Peak memory 212564 kb
Host smart-2f69e6ce-c74b-4436-80ff-988f697b81fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422923633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3422923633
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2379215118
Short name T437
Test name
Test status
Simulation time 660221635 ps
CPU time 12.76 seconds
Started Jul 02 07:52:08 AM PDT 24
Finished Jul 02 07:52:21 AM PDT 24
Peak memory 217208 kb
Host smart-13944ec2-81a4-422b-bf78-4efef4aa4bfc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379215118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2379215118
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3762883174
Short name T374
Test name
Test status
Simulation time 6092422438 ps
CPU time 87.83 seconds
Started Jul 02 07:52:06 AM PDT 24
Finished Jul 02 07:53:35 AM PDT 24
Peak memory 213816 kb
Host smart-ef5bf3d3-be50-4580-b54d-50a6610f3b58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762883174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3762883174
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.964914620
Short name T372
Test name
Test status
Simulation time 5488443657 ps
CPU time 28.29 seconds
Started Jul 02 07:52:23 AM PDT 24
Finished Jul 02 07:52:59 AM PDT 24
Peak memory 217600 kb
Host smart-5ca63b63-fa29-44a8-99df-c312c52f648f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964914620 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.964914620
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3993000337
Short name T377
Test name
Test status
Simulation time 3415497751 ps
CPU time 14.01 seconds
Started Jul 02 07:52:14 AM PDT 24
Finished Jul 02 07:52:30 AM PDT 24
Peak memory 211240 kb
Host smart-733a639d-2991-42b0-be41-6db7167eab92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993000337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3993000337
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3631262090
Short name T90
Test name
Test status
Simulation time 10058740480 ps
CPU time 93.75 seconds
Started Jul 02 07:52:14 AM PDT 24
Finished Jul 02 07:53:50 AM PDT 24
Peak memory 213928 kb
Host smart-3398d146-25bb-4d9b-9eb0-2a2d4c3f0ec4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631262090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3631262090
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.55094834
Short name T443
Test name
Test status
Simulation time 2298291953 ps
CPU time 12 seconds
Started Jul 02 07:52:24 AM PDT 24
Finished Jul 02 07:52:44 AM PDT 24
Peak memory 211236 kb
Host smart-a4069af7-d2d0-4f3b-ab0e-57b2c0b5828b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55094834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ct
rl_same_csr_outstanding.55094834
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1197413315
Short name T380
Test name
Test status
Simulation time 4748380241 ps
CPU time 26.44 seconds
Started Jul 02 07:52:20 AM PDT 24
Finished Jul 02 07:52:48 AM PDT 24
Peak memory 217564 kb
Host smart-c5badc83-5c6a-4679-b0d2-1bf9b4e54bdd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197413315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1197413315
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3917387431
Short name T449
Test name
Test status
Simulation time 5482440095 ps
CPU time 175.57 seconds
Started Jul 02 07:52:16 AM PDT 24
Finished Jul 02 07:55:13 AM PDT 24
Peak memory 214112 kb
Host smart-a9d46b12-57f2-40a2-8bcc-a2116c404ed8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917387431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3917387431
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3927302414
Short name T393
Test name
Test status
Simulation time 25928771782 ps
CPU time 27.02 seconds
Started Jul 02 07:52:24 AM PDT 24
Finished Jul 02 07:52:57 AM PDT 24
Peak memory 217276 kb
Host smart-439e9bf4-6686-4d1f-b010-706f6bc4e5a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927302414 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3927302414
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2059739713
Short name T85
Test name
Test status
Simulation time 177869851 ps
CPU time 8.05 seconds
Started Jul 02 07:52:13 AM PDT 24
Finished Jul 02 07:52:23 AM PDT 24
Peak memory 210728 kb
Host smart-a2e938ab-e25e-4de6-bc7d-12f699422d35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059739713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2059739713
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3430317733
Short name T94
Test name
Test status
Simulation time 6588974304 ps
CPU time 76.97 seconds
Started Jul 02 07:52:31 AM PDT 24
Finished Jul 02 07:54:01 AM PDT 24
Peak memory 214140 kb
Host smart-ff7a2450-6ee0-42ae-acac-244f5237a0ae
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430317733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3430317733
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.105663022
Short name T102
Test name
Test status
Simulation time 23591928766 ps
CPU time 32.01 seconds
Started Jul 02 07:52:16 AM PDT 24
Finished Jul 02 07:52:50 AM PDT 24
Peak memory 212208 kb
Host smart-f6ef7861-1c12-4586-8cdd-438b2d12aa7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105663022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.105663022
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3829934236
Short name T376
Test name
Test status
Simulation time 9457144426 ps
CPU time 26.79 seconds
Started Jul 02 07:52:17 AM PDT 24
Finished Jul 02 07:52:45 AM PDT 24
Peak memory 218756 kb
Host smart-f486f0e1-3254-4888-b43a-bbbe9a3cecf1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829934236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3829934236
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1965459486
Short name T107
Test name
Test status
Simulation time 5560907879 ps
CPU time 172.13 seconds
Started Jul 02 07:52:16 AM PDT 24
Finished Jul 02 07:55:10 AM PDT 24
Peak memory 214180 kb
Host smart-449acef8-2de8-406a-a255-dc9bd66974ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965459486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1965459486
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3337853762
Short name T410
Test name
Test status
Simulation time 369225464 ps
CPU time 9.55 seconds
Started Jul 02 07:52:11 AM PDT 24
Finished Jul 02 07:52:21 AM PDT 24
Peak memory 216924 kb
Host smart-0f7b19f9-ce70-4aaa-b436-f2b4a4c2f981
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337853762 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3337853762
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2848144502
Short name T98
Test name
Test status
Simulation time 1449775904 ps
CPU time 17.25 seconds
Started Jul 02 07:52:24 AM PDT 24
Finished Jul 02 07:52:50 AM PDT 24
Peak memory 211900 kb
Host smart-45d66edd-e288-4072-85fa-d5e912f8d0fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848144502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2848144502
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.537601440
Short name T96
Test name
Test status
Simulation time 3617398448 ps
CPU time 38.04 seconds
Started Jul 02 07:52:15 AM PDT 24
Finished Jul 02 07:52:54 AM PDT 24
Peak memory 213800 kb
Host smart-b9e20ec6-d445-4541-a9ea-d370f8e85e9f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537601440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.537601440
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.84314225
Short name T456
Test name
Test status
Simulation time 2456009092 ps
CPU time 23.06 seconds
Started Jul 02 07:52:26 AM PDT 24
Finished Jul 02 07:53:01 AM PDT 24
Peak memory 212276 kb
Host smart-52500b8d-9758-41eb-bb34-a15f4431b202
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84314225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ct
rl_same_csr_outstanding.84314225
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3285112954
Short name T379
Test name
Test status
Simulation time 655284371 ps
CPU time 18.74 seconds
Started Jul 02 07:52:20 AM PDT 24
Finished Jul 02 07:52:40 AM PDT 24
Peak memory 217424 kb
Host smart-3fb6b6aa-7447-469e-ae2f-f6446066fd27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285112954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3285112954
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2948687573
Short name T109
Test name
Test status
Simulation time 268123956 ps
CPU time 79.85 seconds
Started Jul 02 07:52:24 AM PDT 24
Finished Jul 02 07:53:53 AM PDT 24
Peak memory 212472 kb
Host smart-bb1b4153-f971-493a-b4c0-9f23f36fcb64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948687573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2948687573
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2473885072
Short name T439
Test name
Test status
Simulation time 3617405416 ps
CPU time 27.68 seconds
Started Jul 02 07:52:08 AM PDT 24
Finished Jul 02 07:52:36 AM PDT 24
Peak memory 216684 kb
Host smart-43005911-dc66-4b40-8232-3e61504918a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473885072 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2473885072
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2121677362
Short name T91
Test name
Test status
Simulation time 4264106984 ps
CPU time 31.78 seconds
Started Jul 02 07:52:08 AM PDT 24
Finished Jul 02 07:52:41 AM PDT 24
Peak memory 211676 kb
Host smart-9bdc6cff-d167-4ac3-9ab0-b8f9dce0cee3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121677362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2121677362
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.910829026
Short name T93
Test name
Test status
Simulation time 15772676121 ps
CPU time 84.74 seconds
Started Jul 02 07:52:27 AM PDT 24
Finished Jul 02 07:54:03 AM PDT 24
Peak memory 214180 kb
Host smart-02b91ff5-80ae-459a-a096-ca783151e794
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910829026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.910829026
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3927406953
Short name T101
Test name
Test status
Simulation time 660284700 ps
CPU time 8.46 seconds
Started Jul 02 07:52:18 AM PDT 24
Finished Jul 02 07:52:28 AM PDT 24
Peak memory 211076 kb
Host smart-cfa661d9-815d-4749-b1c7-d74a7c376afc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927406953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3927406953
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1655127035
Short name T360
Test name
Test status
Simulation time 1861611149 ps
CPU time 23.75 seconds
Started Jul 02 07:52:14 AM PDT 24
Finished Jul 02 07:52:40 AM PDT 24
Peak memory 218480 kb
Host smart-38a269dd-a6b5-4b65-9e57-7da7551c137c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655127035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1655127035
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.920593195
Short name T440
Test name
Test status
Simulation time 13744605347 ps
CPU time 27.51 seconds
Started Jul 02 07:52:16 AM PDT 24
Finished Jul 02 07:52:45 AM PDT 24
Peak memory 214620 kb
Host smart-882f5745-c323-4129-a51a-176ac8ef9f95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920593195 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.920593195
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3209668684
Short name T73
Test name
Test status
Simulation time 5842812302 ps
CPU time 25.81 seconds
Started Jul 02 07:52:06 AM PDT 24
Finished Jul 02 07:52:33 AM PDT 24
Peak memory 211796 kb
Host smart-66282341-5834-4bb7-bcc7-72e01bcf580f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209668684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3209668684
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2822577013
Short name T95
Test name
Test status
Simulation time 26226919513 ps
CPU time 139.65 seconds
Started Jul 02 07:52:13 AM PDT 24
Finished Jul 02 07:54:35 AM PDT 24
Peak memory 215448 kb
Host smart-79f362b1-7e1e-4741-9966-4be856127b21
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822577013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2822577013
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2522355381
Short name T394
Test name
Test status
Simulation time 17419872929 ps
CPU time 31.17 seconds
Started Jul 02 07:52:24 AM PDT 24
Finished Jul 02 07:53:04 AM PDT 24
Peak memory 212624 kb
Host smart-eaeaba05-bfea-445e-83d6-1848eb92b58b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522355381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2522355381
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.697923156
Short name T390
Test name
Test status
Simulation time 3058204214 ps
CPU time 16.43 seconds
Started Jul 02 07:52:22 AM PDT 24
Finished Jul 02 07:52:40 AM PDT 24
Peak memory 217104 kb
Host smart-821a0d1d-d582-41b3-9890-7ddd502eab0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697923156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.697923156
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3977435335
Short name T110
Test name
Test status
Simulation time 6525658122 ps
CPU time 174.09 seconds
Started Jul 02 07:52:13 AM PDT 24
Finished Jul 02 07:55:08 AM PDT 24
Peak memory 214180 kb
Host smart-4ff81a83-f496-4b6b-af5b-fefaf08662f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977435335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3977435335
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.47684908
Short name T363
Test name
Test status
Simulation time 5293425030 ps
CPU time 16.66 seconds
Started Jul 02 07:52:22 AM PDT 24
Finished Jul 02 07:52:42 AM PDT 24
Peak memory 215384 kb
Host smart-e68001d8-12ec-4e6f-866c-7505dbe35ad2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47684908 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.47684908
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3274414257
Short name T389
Test name
Test status
Simulation time 17075047692 ps
CPU time 20.63 seconds
Started Jul 02 07:52:23 AM PDT 24
Finished Jul 02 07:52:50 AM PDT 24
Peak memory 212396 kb
Host smart-11476022-6c5d-4c67-a5f5-9d3f0d6a8bf1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274414257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3274414257
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2547324340
Short name T420
Test name
Test status
Simulation time 4058804797 ps
CPU time 44.34 seconds
Started Jul 02 07:52:08 AM PDT 24
Finished Jul 02 07:52:53 AM PDT 24
Peak memory 213564 kb
Host smart-77e59efc-4936-424e-b543-3919cd2f7795
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547324340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2547324340
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1331762543
Short name T66
Test name
Test status
Simulation time 15151325125 ps
CPU time 29.23 seconds
Started Jul 02 07:52:13 AM PDT 24
Finished Jul 02 07:52:44 AM PDT 24
Peak memory 212596 kb
Host smart-4ada7e9d-b95e-4997-8992-1b2eb5c08e47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331762543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1331762543
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2260805204
Short name T448
Test name
Test status
Simulation time 345565118 ps
CPU time 11.19 seconds
Started Jul 02 07:52:25 AM PDT 24
Finished Jul 02 07:52:47 AM PDT 24
Peak memory 217132 kb
Host smart-535bba15-ef14-4f06-9910-81c7ab786cbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260805204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2260805204
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3298626696
Short name T435
Test name
Test status
Simulation time 5962266879 ps
CPU time 29.38 seconds
Started Jul 02 07:52:28 AM PDT 24
Finished Jul 02 07:53:09 AM PDT 24
Peak memory 217508 kb
Host smart-32be051e-0d9a-4913-9f5f-3eaba80fcd29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298626696 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3298626696
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1462996939
Short name T395
Test name
Test status
Simulation time 4184136712 ps
CPU time 24 seconds
Started Jul 02 07:52:24 AM PDT 24
Finished Jul 02 07:52:57 AM PDT 24
Peak memory 210716 kb
Host smart-07813f54-d5a3-47ee-887b-cb9426cf1478
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462996939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1462996939
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1002713572
Short name T71
Test name
Test status
Simulation time 724914280 ps
CPU time 39.29 seconds
Started Jul 02 07:52:23 AM PDT 24
Finished Jul 02 07:53:10 AM PDT 24
Peak memory 213960 kb
Host smart-452831a1-fb3e-4e68-aeda-7040ad4fb165
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002713572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1002713572
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.771342222
Short name T382
Test name
Test status
Simulation time 4596338966 ps
CPU time 26.49 seconds
Started Jul 02 07:52:27 AM PDT 24
Finished Jul 02 07:53:05 AM PDT 24
Peak memory 212652 kb
Host smart-90c7f3f6-9be7-4801-9076-84812051a835
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771342222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.771342222
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.478898582
Short name T418
Test name
Test status
Simulation time 3761702437 ps
CPU time 32.16 seconds
Started Jul 02 07:52:24 AM PDT 24
Finished Jul 02 07:53:05 AM PDT 24
Peak memory 218344 kb
Host smart-2673e22b-525f-49cd-9cac-5a90b127a94a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478898582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.478898582
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3973219764
Short name T106
Test name
Test status
Simulation time 3164002317 ps
CPU time 97.99 seconds
Started Jul 02 07:52:22 AM PDT 24
Finished Jul 02 07:54:04 AM PDT 24
Peak memory 213632 kb
Host smart-63e02a67-ffa5-4f49-a0f7-c1991fd03c82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973219764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3973219764
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2954587094
Short name T86
Test name
Test status
Simulation time 688189700 ps
CPU time 8.36 seconds
Started Jul 02 07:52:02 AM PDT 24
Finished Jul 02 07:52:12 AM PDT 24
Peak memory 210592 kb
Host smart-6cf8ff8d-c567-4207-a2c4-c9be62d77ca9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954587094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2954587094
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1231108732
Short name T446
Test name
Test status
Simulation time 1831914678 ps
CPU time 8.36 seconds
Started Jul 02 07:52:02 AM PDT 24
Finished Jul 02 07:52:12 AM PDT 24
Peak memory 210960 kb
Host smart-d1f0aa14-3ab9-4234-9704-cf125e2e3e52
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231108732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1231108732
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3716702461
Short name T88
Test name
Test status
Simulation time 7533254193 ps
CPU time 23.08 seconds
Started Jul 02 07:52:07 AM PDT 24
Finished Jul 02 07:52:31 AM PDT 24
Peak memory 210732 kb
Host smart-9673e1a7-9bb1-400c-ae19-675816ef03bd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716702461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3716702461
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.418374017
Short name T442
Test name
Test status
Simulation time 7593669811 ps
CPU time 30.49 seconds
Started Jul 02 07:51:58 AM PDT 24
Finished Jul 02 07:52:31 AM PDT 24
Peak memory 217520 kb
Host smart-f12eddab-a007-4290-8360-8e03745a0255
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418374017 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.418374017
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3810508661
Short name T391
Test name
Test status
Simulation time 1870555836 ps
CPU time 11.09 seconds
Started Jul 02 07:52:03 AM PDT 24
Finished Jul 02 07:52:15 AM PDT 24
Peak memory 210488 kb
Host smart-e9e534c7-5189-43c6-a5da-0637f15adaa4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810508661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3810508661
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1615483183
Short name T413
Test name
Test status
Simulation time 2629573735 ps
CPU time 24.64 seconds
Started Jul 02 07:52:05 AM PDT 24
Finished Jul 02 07:52:30 AM PDT 24
Peak memory 210508 kb
Host smart-775f8884-0055-488f-9e70-1389e78372b4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615483183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1615483183
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3503231401
Short name T414
Test name
Test status
Simulation time 506118731 ps
CPU time 11.51 seconds
Started Jul 02 07:52:03 AM PDT 24
Finished Jul 02 07:52:16 AM PDT 24
Peak memory 210444 kb
Host smart-de61da08-1c37-402c-b62b-d8c5e342657b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503231401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3503231401
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1957282514
Short name T441
Test name
Test status
Simulation time 25102514753 ps
CPU time 193.43 seconds
Started Jul 02 07:51:57 AM PDT 24
Finished Jul 02 07:55:13 AM PDT 24
Peak memory 215128 kb
Host smart-f76b4f87-6650-4f20-abc1-1bc1fa76a823
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957282514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1957282514
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2661085091
Short name T419
Test name
Test status
Simulation time 48974034641 ps
CPU time 23.35 seconds
Started Jul 02 07:52:04 AM PDT 24
Finished Jul 02 07:52:28 AM PDT 24
Peak memory 212552 kb
Host smart-ad909225-01f9-433c-9cc2-b9b5b9f8ca51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661085091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2661085091
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2445453368
Short name T373
Test name
Test status
Simulation time 904441493 ps
CPU time 18.5 seconds
Started Jul 02 07:52:00 AM PDT 24
Finished Jul 02 07:52:21 AM PDT 24
Peak memory 218460 kb
Host smart-e22c7958-e296-428c-a295-48023a16c5cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445453368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2445453368
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.385763257
Short name T112
Test name
Test status
Simulation time 6410336203 ps
CPU time 157.14 seconds
Started Jul 02 07:52:02 AM PDT 24
Finished Jul 02 07:54:41 AM PDT 24
Peak memory 214288 kb
Host smart-4e39fb51-c7e6-44a1-b1b1-6a625d5ad413
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385763257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.385763257
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3516238259
Short name T87
Test name
Test status
Simulation time 7022875753 ps
CPU time 27.62 seconds
Started Jul 02 07:52:01 AM PDT 24
Finished Jul 02 07:52:31 AM PDT 24
Peak memory 211844 kb
Host smart-192cb85c-c3ce-4432-bfac-035e3fcad8ea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516238259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3516238259
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2741272559
Short name T69
Test name
Test status
Simulation time 5982266897 ps
CPU time 26.39 seconds
Started Jul 02 07:52:05 AM PDT 24
Finished Jul 02 07:52:33 AM PDT 24
Peak memory 212128 kb
Host smart-c5de438e-9e52-4d28-a310-6f7c41239ed3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741272559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2741272559
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3775101143
Short name T427
Test name
Test status
Simulation time 344028251 ps
CPU time 11.64 seconds
Started Jul 02 07:52:23 AM PDT 24
Finished Jul 02 07:52:40 AM PDT 24
Peak memory 211480 kb
Host smart-13097c73-e975-45a7-824e-5b71a02904b2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775101143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3775101143
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1794491262
Short name T392
Test name
Test status
Simulation time 12752444716 ps
CPU time 28.3 seconds
Started Jul 02 07:51:53 AM PDT 24
Finished Jul 02 07:52:26 AM PDT 24
Peak memory 218220 kb
Host smart-e778ed83-5eeb-4f76-9cee-28924c787b3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794491262 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1794491262
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1266523424
Short name T59
Test name
Test status
Simulation time 8225282573 ps
CPU time 20.94 seconds
Started Jul 02 07:52:05 AM PDT 24
Finished Jul 02 07:52:28 AM PDT 24
Peak memory 212120 kb
Host smart-d2ae0401-11c0-48bb-8e36-b4a53d89b173
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266523424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1266523424
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1119815963
Short name T386
Test name
Test status
Simulation time 5956737456 ps
CPU time 16.46 seconds
Started Jul 02 07:52:00 AM PDT 24
Finished Jul 02 07:52:18 AM PDT 24
Peak memory 210720 kb
Host smart-2d0d9981-8a67-4d34-aa55-18481b24102e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119815963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1119815963
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1024762363
Short name T369
Test name
Test status
Simulation time 1954671236 ps
CPU time 15.04 seconds
Started Jul 02 07:52:08 AM PDT 24
Finished Jul 02 07:52:30 AM PDT 24
Peak memory 210808 kb
Host smart-e756dc53-5518-405a-a7aa-d8c4f1d84799
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024762363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1024762363
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2083747871
Short name T453
Test name
Test status
Simulation time 4258876205 ps
CPU time 55.75 seconds
Started Jul 02 07:52:06 AM PDT 24
Finished Jul 02 07:53:03 AM PDT 24
Peak memory 215676 kb
Host smart-0cdfb465-4d2f-43d4-bc7b-fcd900e7a857
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083747871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2083747871
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1883641395
Short name T396
Test name
Test status
Simulation time 7010301869 ps
CPU time 17.16 seconds
Started Jul 02 07:51:53 AM PDT 24
Finished Jul 02 07:52:15 AM PDT 24
Peak memory 211368 kb
Host smart-71abd1e3-ff2d-42d1-8d68-230216338c5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883641395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1883641395
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2885516307
Short name T455
Test name
Test status
Simulation time 500061335 ps
CPU time 14.75 seconds
Started Jul 02 07:52:03 AM PDT 24
Finished Jul 02 07:52:19 AM PDT 24
Peak memory 217152 kb
Host smart-48d548e1-7cf6-4f18-850c-a1ab8ba2dd23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885516307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2885516307
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3341502161
Short name T457
Test name
Test status
Simulation time 2746322790 ps
CPU time 97.14 seconds
Started Jul 02 07:51:56 AM PDT 24
Finished Jul 02 07:53:37 AM PDT 24
Peak memory 213332 kb
Host smart-2253843e-b710-434e-b8ba-72d3e50a2808
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341502161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3341502161
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3118253243
Short name T385
Test name
Test status
Simulation time 338996756 ps
CPU time 8.08 seconds
Started Jul 02 07:52:09 AM PDT 24
Finished Jul 02 07:52:18 AM PDT 24
Peak memory 210572 kb
Host smart-1a1e8ab6-a02b-42b9-a599-0afa50d96312
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118253243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3118253243
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2154967246
Short name T103
Test name
Test status
Simulation time 2056726185 ps
CPU time 8.57 seconds
Started Jul 02 07:52:04 AM PDT 24
Finished Jul 02 07:52:14 AM PDT 24
Peak memory 210580 kb
Host smart-51fd9756-2fbd-4ef9-95ad-d8e6abef4bbc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154967246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2154967246
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2525348809
Short name T375
Test name
Test status
Simulation time 347474193 ps
CPU time 15.37 seconds
Started Jul 02 07:52:05 AM PDT 24
Finished Jul 02 07:52:22 AM PDT 24
Peak memory 211896 kb
Host smart-8f9f7364-5600-47e6-81b8-4fecd312ccc4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525348809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2525348809
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3849990542
Short name T417
Test name
Test status
Simulation time 6168095999 ps
CPU time 17.84 seconds
Started Jul 02 07:52:22 AM PDT 24
Finished Jul 02 07:52:43 AM PDT 24
Peak memory 217012 kb
Host smart-44b04df0-06a7-47c1-bd0b-ce84a259a6d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849990542 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3849990542
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.564362505
Short name T403
Test name
Test status
Simulation time 6128971032 ps
CPU time 25.93 seconds
Started Jul 02 07:52:05 AM PDT 24
Finished Jul 02 07:52:33 AM PDT 24
Peak memory 211968 kb
Host smart-54bfbf73-82a8-4ce5-b696-5a16485263a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564362505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.564362505
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.631438237
Short name T452
Test name
Test status
Simulation time 8499620914 ps
CPU time 20.8 seconds
Started Jul 02 07:52:07 AM PDT 24
Finished Jul 02 07:52:28 AM PDT 24
Peak memory 210564 kb
Host smart-ff2493ee-bc09-4264-9803-e618da86460d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631438237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.631438237
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.942425937
Short name T409
Test name
Test status
Simulation time 3474129120 ps
CPU time 27.09 seconds
Started Jul 02 07:52:14 AM PDT 24
Finished Jul 02 07:52:43 AM PDT 24
Peak memory 210504 kb
Host smart-144ca36f-8e1d-4b62-b079-fdf954b53c35
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942425937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
942425937
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.271683824
Short name T415
Test name
Test status
Simulation time 46710533874 ps
CPU time 109.46 seconds
Started Jul 02 07:51:59 AM PDT 24
Finished Jul 02 07:53:51 AM PDT 24
Peak memory 214828 kb
Host smart-17be75fd-5b7d-4858-a24f-35631f44f78c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271683824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.271683824
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3173132257
Short name T428
Test name
Test status
Simulation time 4023252648 ps
CPU time 35.26 seconds
Started Jul 02 07:52:06 AM PDT 24
Finished Jul 02 07:52:43 AM PDT 24
Peak memory 212396 kb
Host smart-5d93ffa0-37fb-43db-8bf5-c93bb8cb9d5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173132257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3173132257
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1603573524
Short name T364
Test name
Test status
Simulation time 10386199195 ps
CPU time 22.47 seconds
Started Jul 02 07:52:03 AM PDT 24
Finished Jul 02 07:52:27 AM PDT 24
Peak memory 218812 kb
Host smart-407fbed2-ce40-4cef-a9a3-5af67c01629e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603573524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1603573524
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1706408351
Short name T399
Test name
Test status
Simulation time 4350561767 ps
CPU time 94.85 seconds
Started Jul 02 07:52:11 AM PDT 24
Finished Jul 02 07:53:47 AM PDT 24
Peak memory 213824 kb
Host smart-66c40f3b-e62c-4e9e-8212-554127d50e34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706408351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1706408351
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.943045773
Short name T366
Test name
Test status
Simulation time 13669074841 ps
CPU time 27.33 seconds
Started Jul 02 07:51:59 AM PDT 24
Finished Jul 02 07:52:29 AM PDT 24
Peak memory 215400 kb
Host smart-1ea814fa-c72a-4857-8d90-3d2965a3152a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943045773 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.943045773
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.264968850
Short name T433
Test name
Test status
Simulation time 3268341035 ps
CPU time 26.87 seconds
Started Jul 02 07:52:13 AM PDT 24
Finished Jul 02 07:52:42 AM PDT 24
Peak memory 211200 kb
Host smart-c63f20de-9d25-4ead-9c95-7c4ce87e0919
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264968850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.264968850
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4247061667
Short name T99
Test name
Test status
Simulation time 2852223922 ps
CPU time 38.43 seconds
Started Jul 02 07:52:11 AM PDT 24
Finished Jul 02 07:52:51 AM PDT 24
Peak memory 213044 kb
Host smart-e4174705-4f12-4944-a0be-9b7e6de20f9e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247061667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.4247061667
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1462881368
Short name T97
Test name
Test status
Simulation time 14934651076 ps
CPU time 32.1 seconds
Started Jul 02 07:52:09 AM PDT 24
Finished Jul 02 07:52:42 AM PDT 24
Peak memory 212340 kb
Host smart-1e35523f-31de-4689-be80-e16b2fb4f466
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462881368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1462881368
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4195845133
Short name T434
Test name
Test status
Simulation time 524138424 ps
CPU time 15.21 seconds
Started Jul 02 07:52:13 AM PDT 24
Finished Jul 02 07:52:29 AM PDT 24
Peak memory 217248 kb
Host smart-4b2e4027-5a5c-4784-8fc8-5931781087e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195845133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.4195845133
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4019791832
Short name T56
Test name
Test status
Simulation time 1210565604 ps
CPU time 80.91 seconds
Started Jul 02 07:52:10 AM PDT 24
Finished Jul 02 07:53:31 AM PDT 24
Peak memory 213580 kb
Host smart-f6c11ef4-eb4f-4740-be46-f7c77174388c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019791832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.4019791832
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.616372102
Short name T402
Test name
Test status
Simulation time 3736824816 ps
CPU time 19.3 seconds
Started Jul 02 07:52:06 AM PDT 24
Finished Jul 02 07:52:26 AM PDT 24
Peak memory 215608 kb
Host smart-1dbeb3be-3e91-44fe-b75e-0c92a5ca8b6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616372102 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.616372102
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.194493916
Short name T429
Test name
Test status
Simulation time 7303606595 ps
CPU time 28.92 seconds
Started Jul 02 07:52:16 AM PDT 24
Finished Jul 02 07:52:46 AM PDT 24
Peak memory 212244 kb
Host smart-9c5d5938-047f-4ed5-adb5-34d7bbf00a89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194493916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.194493916
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1050465764
Short name T89
Test name
Test status
Simulation time 11604802303 ps
CPU time 106.62 seconds
Started Jul 02 07:52:26 AM PDT 24
Finished Jul 02 07:54:23 AM PDT 24
Peak memory 214128 kb
Host smart-50ce2aa5-02c8-4708-9913-dee48e6f1909
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050465764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1050465764
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3946065782
Short name T422
Test name
Test status
Simulation time 256236778 ps
CPU time 9.82 seconds
Started Jul 02 07:52:24 AM PDT 24
Finished Jul 02 07:52:40 AM PDT 24
Peak memory 211164 kb
Host smart-e09bf036-3177-4f60-a025-e79a03f7d43d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946065782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3946065782
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1331231823
Short name T406
Test name
Test status
Simulation time 750641236 ps
CPU time 11.24 seconds
Started Jul 02 07:52:16 AM PDT 24
Finished Jul 02 07:52:28 AM PDT 24
Peak memory 217176 kb
Host smart-6222cbbf-0849-4870-947a-b2cab875bd39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331231823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1331231823
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1199393903
Short name T431
Test name
Test status
Simulation time 305022164 ps
CPU time 153.61 seconds
Started Jul 02 07:52:11 AM PDT 24
Finished Jul 02 07:54:45 AM PDT 24
Peak memory 213788 kb
Host smart-af3b3881-3c50-4bcd-bf40-6f196f79885e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199393903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1199393903
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.334337981
Short name T426
Test name
Test status
Simulation time 7246056016 ps
CPU time 28.28 seconds
Started Jul 02 07:52:03 AM PDT 24
Finished Jul 02 07:52:32 AM PDT 24
Peak memory 214888 kb
Host smart-36fd5720-4e2f-4faa-8bde-6c10f970804c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334337981 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.334337981
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1196720102
Short name T384
Test name
Test status
Simulation time 7612225628 ps
CPU time 29.81 seconds
Started Jul 02 07:52:05 AM PDT 24
Finished Jul 02 07:52:35 AM PDT 24
Peak memory 211952 kb
Host smart-e3a67e94-f7ba-44f4-9e15-488420c95864
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196720102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1196720102
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2799517596
Short name T444
Test name
Test status
Simulation time 2553379246 ps
CPU time 37.95 seconds
Started Jul 02 07:52:11 AM PDT 24
Finished Jul 02 07:52:50 AM PDT 24
Peak memory 213728 kb
Host smart-ecf28e6f-0fd4-4e8f-a721-9ae031f5ec3b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799517596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2799517596
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.192290613
Short name T404
Test name
Test status
Simulation time 1190015351 ps
CPU time 18.81 seconds
Started Jul 02 07:51:59 AM PDT 24
Finished Jul 02 07:52:20 AM PDT 24
Peak memory 212220 kb
Host smart-6b66c695-81dd-43ee-b0c7-595d1b0227de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192290613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.192290613
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2748093731
Short name T359
Test name
Test status
Simulation time 1578222165 ps
CPU time 22.3 seconds
Started Jul 02 07:52:20 AM PDT 24
Finished Jul 02 07:52:43 AM PDT 24
Peak memory 218828 kb
Host smart-53426d49-694c-41cb-8792-c4218358e53a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748093731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2748093731
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2353366107
Short name T398
Test name
Test status
Simulation time 197708794 ps
CPU time 9.83 seconds
Started Jul 02 07:52:08 AM PDT 24
Finished Jul 02 07:52:19 AM PDT 24
Peak memory 216668 kb
Host smart-0ab52fac-0bb8-4b78-b1ce-cc8509b8db58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353366107 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2353366107
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3035630588
Short name T445
Test name
Test status
Simulation time 15503556287 ps
CPU time 24.84 seconds
Started Jul 02 07:52:06 AM PDT 24
Finished Jul 02 07:52:32 AM PDT 24
Peak memory 212252 kb
Host smart-25d23cd9-aaf1-41d3-b771-664641a00f30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035630588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3035630588
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1778745906
Short name T92
Test name
Test status
Simulation time 1341966868 ps
CPU time 55.36 seconds
Started Jul 02 07:52:13 AM PDT 24
Finished Jul 02 07:53:10 AM PDT 24
Peak memory 214880 kb
Host smart-33397355-db02-46f6-bade-a41a111b7777
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778745906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1778745906
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2317208929
Short name T400
Test name
Test status
Simulation time 3060030824 ps
CPU time 26.28 seconds
Started Jul 02 07:52:03 AM PDT 24
Finished Jul 02 07:52:31 AM PDT 24
Peak memory 212332 kb
Host smart-1c7d017f-d2ab-4d8e-a848-9366d900fcba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317208929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2317208929
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2893260287
Short name T371
Test name
Test status
Simulation time 2744664412 ps
CPU time 28.6 seconds
Started Jul 02 07:52:11 AM PDT 24
Finished Jul 02 07:52:41 AM PDT 24
Peak memory 218336 kb
Host smart-de7576ef-6c7b-483d-a017-c55961b0c951
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893260287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2893260287
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3319035386
Short name T438
Test name
Test status
Simulation time 3141517153 ps
CPU time 170.58 seconds
Started Jul 02 07:52:05 AM PDT 24
Finished Jul 02 07:54:56 AM PDT 24
Peak memory 213832 kb
Host smart-6f66925c-9006-41e4-8131-ca57e04c755b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319035386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3319035386
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.4080288369
Short name T450
Test name
Test status
Simulation time 691318946 ps
CPU time 8.79 seconds
Started Jul 02 07:52:22 AM PDT 24
Finished Jul 02 07:52:33 AM PDT 24
Peak memory 218880 kb
Host smart-15b085c9-4612-4b4f-93bd-2b0233c2938c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080288369 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.4080288369
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3188290155
Short name T84
Test name
Test status
Simulation time 331813930 ps
CPU time 8.19 seconds
Started Jul 02 07:52:21 AM PDT 24
Finished Jul 02 07:52:30 AM PDT 24
Peak memory 210528 kb
Host smart-9967b6ec-40e0-45d6-b1e0-89ab5fa33524
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188290155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3188290155
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1297662579
Short name T430
Test name
Test status
Simulation time 2621174629 ps
CPU time 16.5 seconds
Started Jul 02 07:52:19 AM PDT 24
Finished Jul 02 07:52:37 AM PDT 24
Peak memory 211280 kb
Host smart-8e2d221e-e390-4ef0-bf50-e0c3dc4bcc9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297662579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1297662579
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1021533890
Short name T367
Test name
Test status
Simulation time 171649313 ps
CPU time 13.82 seconds
Started Jul 02 07:52:09 AM PDT 24
Finished Jul 02 07:52:24 AM PDT 24
Peak memory 218520 kb
Host smart-77d664b2-a50c-41a9-95cb-10094249212e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021533890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1021533890
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2411669042
Short name T113
Test name
Test status
Simulation time 2557568072 ps
CPU time 158.03 seconds
Started Jul 02 07:52:22 AM PDT 24
Finished Jul 02 07:55:02 AM PDT 24
Peak memory 213728 kb
Host smart-7f0ca9bc-d7d7-4f61-9e0b-376cc87d9f12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411669042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2411669042
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3399627151
Short name T247
Test name
Test status
Simulation time 40394107092 ps
CPU time 566.56 seconds
Started Jul 02 07:49:27 AM PDT 24
Finished Jul 02 07:58:54 AM PDT 24
Peak memory 238976 kb
Host smart-7854174c-98e0-458d-a562-15d1893f3ccc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399627151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3399627151
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2177650330
Short name T254
Test name
Test status
Simulation time 9921156866 ps
CPU time 46.12 seconds
Started Jul 02 07:49:18 AM PDT 24
Finished Jul 02 07:50:05 AM PDT 24
Peak memory 219276 kb
Host smart-f82f77cf-9ffd-40bc-bb56-1cab5052cf42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177650330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2177650330
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1104289004
Short name T116
Test name
Test status
Simulation time 310667029 ps
CPU time 10.25 seconds
Started Jul 02 07:49:01 AM PDT 24
Finished Jul 02 07:49:14 AM PDT 24
Peak memory 219204 kb
Host smart-87e1055c-3ca0-4eb7-ada7-167bca50c62c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1104289004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1104289004
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2068658307
Short name T26
Test name
Test status
Simulation time 4355851914 ps
CPU time 237.52 seconds
Started Jul 02 07:49:08 AM PDT 24
Finished Jul 02 07:53:07 AM PDT 24
Peak memory 235280 kb
Host smart-314cbc1a-bcf6-4715-9c4c-aaec4c965667
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068658307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2068658307
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.870275621
Short name T144
Test name
Test status
Simulation time 18669772954 ps
CPU time 45.97 seconds
Started Jul 02 07:49:14 AM PDT 24
Finished Jul 02 07:50:00 AM PDT 24
Peak memory 216136 kb
Host smart-cc37bca5-3cef-4de0-9f2c-39b836eeb748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870275621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.870275621
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.407471291
Short name T327
Test name
Test status
Simulation time 14163553411 ps
CPU time 33.61 seconds
Started Jul 02 07:49:08 AM PDT 24
Finished Jul 02 07:49:43 AM PDT 24
Peak memory 219096 kb
Host smart-ac894ddb-254e-4e02-90b4-eae2e5286c73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407471291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.407471291
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3665993553
Short name T201
Test name
Test status
Simulation time 1611355223 ps
CPU time 13.07 seconds
Started Jul 02 07:49:12 AM PDT 24
Finished Jul 02 07:49:26 AM PDT 24
Peak memory 216964 kb
Host smart-78b7971c-16a8-4ad9-8afa-09b24dcc55c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665993553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3665993553
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1501939262
Short name T33
Test name
Test status
Simulation time 34139881956 ps
CPU time 408.66 seconds
Started Jul 02 07:49:02 AM PDT 24
Finished Jul 02 07:55:53 AM PDT 24
Peak memory 236228 kb
Host smart-8b2b76e4-f3cc-453c-9a3c-da98408cbec2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501939262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1501939262
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1396979653
Short name T316
Test name
Test status
Simulation time 2466440543 ps
CPU time 14.88 seconds
Started Jul 02 07:49:12 AM PDT 24
Finished Jul 02 07:49:28 AM PDT 24
Peak memory 218696 kb
Host smart-a091dd6d-174a-4e4c-b9a7-409492d67f8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1396979653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1396979653
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1167301509
Short name T148
Test name
Test status
Simulation time 4673478576 ps
CPU time 28.03 seconds
Started Jul 02 07:49:12 AM PDT 24
Finished Jul 02 07:49:41 AM PDT 24
Peak memory 216784 kb
Host smart-6cf38856-9fc0-45cc-b700-71a8205f71fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167301509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1167301509
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1385887939
Short name T248
Test name
Test status
Simulation time 6630387486 ps
CPU time 92.63 seconds
Started Jul 02 07:49:18 AM PDT 24
Finished Jul 02 07:50:51 AM PDT 24
Peak memory 219832 kb
Host smart-4a8324fd-800c-4905-bc87-2523f757c8c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385887939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1385887939
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3004293127
Short name T151
Test name
Test status
Simulation time 2213862048 ps
CPU time 11.92 seconds
Started Jul 02 07:49:24 AM PDT 24
Finished Jul 02 07:49:36 AM PDT 24
Peak memory 217056 kb
Host smart-15faca1f-2501-487a-9e67-66e3bedd0ffb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004293127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3004293127
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.260026416
Short name T38
Test name
Test status
Simulation time 505822565144 ps
CPU time 870.71 seconds
Started Jul 02 07:49:20 AM PDT 24
Finished Jul 02 08:03:52 AM PDT 24
Peak memory 234672 kb
Host smart-1b550ec3-8e72-453a-840c-66b9c3ba789c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260026416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.260026416
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2329437638
Short name T156
Test name
Test status
Simulation time 6290540900 ps
CPU time 57.14 seconds
Started Jul 02 07:49:29 AM PDT 24
Finished Jul 02 07:50:27 AM PDT 24
Peak memory 219324 kb
Host smart-70cf7e10-248b-4699-8339-08285208b93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329437638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2329437638
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1965802181
Short name T267
Test name
Test status
Simulation time 7997439558 ps
CPU time 31.37 seconds
Started Jul 02 07:49:29 AM PDT 24
Finished Jul 02 07:50:02 AM PDT 24
Peak memory 219276 kb
Host smart-b5cfca08-a993-4e97-bdaf-5d4fd1a1868f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1965802181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1965802181
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1770488896
Short name T206
Test name
Test status
Simulation time 523396503 ps
CPU time 13.93 seconds
Started Jul 02 07:49:32 AM PDT 24
Finished Jul 02 07:49:47 AM PDT 24
Peak memory 219100 kb
Host smart-ed2fa80a-acfe-49c6-b45f-4df1ee585e78
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770488896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1770488896
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1959742599
Short name T292
Test name
Test status
Simulation time 1302663530 ps
CPU time 14.34 seconds
Started Jul 02 07:49:19 AM PDT 24
Finished Jul 02 07:49:35 AM PDT 24
Peak memory 217084 kb
Host smart-07a52dc8-dc1f-4ab1-a536-7c9664f98c08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959742599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1959742599
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.107198041
Short name T257
Test name
Test status
Simulation time 64917721444 ps
CPU time 659.26 seconds
Started Jul 02 07:49:44 AM PDT 24
Finished Jul 02 08:00:52 AM PDT 24
Peak memory 241944 kb
Host smart-52c78e56-72c3-40e8-bc72-240e2930117a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107198041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.107198041
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1719006651
Short name T179
Test name
Test status
Simulation time 13630009039 ps
CPU time 40.36 seconds
Started Jul 02 07:49:34 AM PDT 24
Finished Jul 02 07:50:15 AM PDT 24
Peak memory 219216 kb
Host smart-153ef820-598d-4193-b137-0f9e641f3c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719006651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1719006651
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3328591397
Short name T137
Test name
Test status
Simulation time 1018449498 ps
CPU time 11.98 seconds
Started Jul 02 07:49:26 AM PDT 24
Finished Jul 02 07:49:39 AM PDT 24
Peak memory 219220 kb
Host smart-4ac360b4-1f8f-476b-843c-9474ce519392
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3328591397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3328591397
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2892570213
Short name T134
Test name
Test status
Simulation time 25760016510 ps
CPU time 56.17 seconds
Started Jul 02 07:49:22 AM PDT 24
Finished Jul 02 07:50:18 AM PDT 24
Peak memory 216524 kb
Host smart-9dc5ab9d-a134-434e-8e00-f277ad9d4b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892570213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2892570213
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3524505812
Short name T283
Test name
Test status
Simulation time 425752022 ps
CPU time 22.59 seconds
Started Jul 02 07:49:17 AM PDT 24
Finished Jul 02 07:49:41 AM PDT 24
Peak memory 217960 kb
Host smart-24027f4a-58c7-42d9-a710-2393e6809c60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524505812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3524505812
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.4205526401
Short name T231
Test name
Test status
Simulation time 11098538197 ps
CPU time 18.42 seconds
Started Jul 02 07:49:33 AM PDT 24
Finished Jul 02 07:49:53 AM PDT 24
Peak memory 217672 kb
Host smart-1227a45a-b41b-458b-8b81-17c27ccccfd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205526401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.4205526401
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.154756220
Short name T160
Test name
Test status
Simulation time 100402214345 ps
CPU time 456.53 seconds
Started Jul 02 07:49:23 AM PDT 24
Finished Jul 02 07:57:01 AM PDT 24
Peak memory 235712 kb
Host smart-e170c4fc-3b29-47a7-975d-3c615f2ae34e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154756220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.154756220
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.236055163
Short name T236
Test name
Test status
Simulation time 16480888864 ps
CPU time 32.24 seconds
Started Jul 02 07:49:27 AM PDT 24
Finished Jul 02 07:50:01 AM PDT 24
Peak memory 219292 kb
Host smart-7fb7d1d0-1cfe-4b39-88b2-1caefb439a78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=236055163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.236055163
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1246091231
Short name T34
Test name
Test status
Simulation time 2500735051 ps
CPU time 35.7 seconds
Started Jul 02 07:49:23 AM PDT 24
Finished Jul 02 07:49:59 AM PDT 24
Peak memory 216280 kb
Host smart-c285ab09-ebc1-4b42-b7e6-81fc5908bc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246091231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1246091231
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2253619562
Short name T161
Test name
Test status
Simulation time 253992526 ps
CPU time 10 seconds
Started Jul 02 07:49:23 AM PDT 24
Finished Jul 02 07:49:34 AM PDT 24
Peak memory 217052 kb
Host smart-d5fb2107-be61-44a2-9ede-232923a8a9f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253619562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2253619562
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.554297835
Short name T343
Test name
Test status
Simulation time 2466466973 ps
CPU time 34.82 seconds
Started Jul 02 07:49:25 AM PDT 24
Finished Jul 02 07:50:01 AM PDT 24
Peak memory 219228 kb
Host smart-72861ce6-8ea8-49f0-9306-027f70049448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554297835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.554297835
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3313923962
Short name T294
Test name
Test status
Simulation time 8686549508 ps
CPU time 19.81 seconds
Started Jul 02 07:49:36 AM PDT 24
Finished Jul 02 07:49:57 AM PDT 24
Peak memory 219264 kb
Host smart-bd9e3428-f962-4b86-bbf5-880b1d226e88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3313923962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3313923962
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.519710311
Short name T244
Test name
Test status
Simulation time 1122630503 ps
CPU time 20.28 seconds
Started Jul 02 07:49:33 AM PDT 24
Finished Jul 02 07:49:54 AM PDT 24
Peak memory 216692 kb
Host smart-d1ccb43a-1d57-4242-8da2-d6a057b7ce61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519710311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.519710311
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3022751243
Short name T130
Test name
Test status
Simulation time 117591192035 ps
CPU time 182.57 seconds
Started Jul 02 07:49:31 AM PDT 24
Finished Jul 02 07:52:35 AM PDT 24
Peak memory 219308 kb
Host smart-d3004d45-cd16-469a-b220-091da26384d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022751243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3022751243
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2332743114
Short name T63
Test name
Test status
Simulation time 2058208924 ps
CPU time 8.17 seconds
Started Jul 02 07:49:38 AM PDT 24
Finished Jul 02 07:49:48 AM PDT 24
Peak memory 217004 kb
Host smart-49cb106b-b6c3-4c03-b2b3-694e01d2b390
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332743114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2332743114
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1069188339
Short name T165
Test name
Test status
Simulation time 242914366731 ps
CPU time 509.87 seconds
Started Jul 02 07:49:31 AM PDT 24
Finished Jul 02 07:58:03 AM PDT 24
Peak memory 230772 kb
Host smart-db80d000-009f-4beb-af46-65163515475c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069188339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1069188339
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.459357843
Short name T122
Test name
Test status
Simulation time 32806419796 ps
CPU time 68.82 seconds
Started Jul 02 07:49:25 AM PDT 24
Finished Jul 02 07:50:35 AM PDT 24
Peak memory 219248 kb
Host smart-ed6df4a8-1d9c-464a-b884-805af4b2331e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459357843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.459357843
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.510982664
Short name T203
Test name
Test status
Simulation time 11130141520 ps
CPU time 25.94 seconds
Started Jul 02 07:49:38 AM PDT 24
Finished Jul 02 07:50:06 AM PDT 24
Peak memory 217632 kb
Host smart-b76ec0e6-c242-4277-958e-a7ae73a47578
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=510982664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.510982664
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.889071985
Short name T264
Test name
Test status
Simulation time 854855235 ps
CPU time 24.95 seconds
Started Jul 02 07:49:33 AM PDT 24
Finished Jul 02 07:49:59 AM PDT 24
Peak memory 215876 kb
Host smart-a55a69d1-ab76-418b-9b4f-40e604ab46bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889071985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.889071985
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3852456237
Short name T209
Test name
Test status
Simulation time 5549209431 ps
CPU time 29.02 seconds
Started Jul 02 07:49:24 AM PDT 24
Finished Jul 02 07:49:54 AM PDT 24
Peak memory 214540 kb
Host smart-8430f17b-80f6-4289-8716-4e741270de11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852456237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3852456237
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1164985863
Short name T176
Test name
Test status
Simulation time 277673208 ps
CPU time 8.27 seconds
Started Jul 02 07:49:43 AM PDT 24
Finished Jul 02 07:49:59 AM PDT 24
Peak memory 217120 kb
Host smart-42992d97-6809-41c0-aa33-d5ac62685180
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164985863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1164985863
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1012813877
Short name T208
Test name
Test status
Simulation time 43431617349 ps
CPU time 189.7 seconds
Started Jul 02 07:49:34 AM PDT 24
Finished Jul 02 07:52:45 AM PDT 24
Peak memory 219508 kb
Host smart-521f9aec-fb94-450c-8871-ad1bc539b2ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012813877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1012813877
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1784978298
Short name T169
Test name
Test status
Simulation time 4960593215 ps
CPU time 49.07 seconds
Started Jul 02 07:49:39 AM PDT 24
Finished Jul 02 07:50:29 AM PDT 24
Peak memory 219308 kb
Host smart-d6c196c7-e894-4860-b9a5-8e58aaa54ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784978298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1784978298
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3360683776
Short name T42
Test name
Test status
Simulation time 36185021713 ps
CPU time 31.57 seconds
Started Jul 02 07:49:42 AM PDT 24
Finished Jul 02 07:50:20 AM PDT 24
Peak memory 219220 kb
Host smart-538d2e59-2939-41f7-8d60-e4ce41032922
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3360683776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3360683776
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1446432547
Short name T182
Test name
Test status
Simulation time 10423764189 ps
CPU time 50.73 seconds
Started Jul 02 07:49:44 AM PDT 24
Finished Jul 02 07:50:45 AM PDT 24
Peak memory 216596 kb
Host smart-739307b5-809c-4a11-b73f-fa37348340f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446432547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1446432547
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1933961835
Short name T218
Test name
Test status
Simulation time 1114809734 ps
CPU time 37.3 seconds
Started Jul 02 07:49:31 AM PDT 24
Finished Jul 02 07:50:10 AM PDT 24
Peak memory 219232 kb
Host smart-6f9135f5-f624-4ade-a692-c6459cebd6f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933961835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1933961835
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.512409907
Short name T321
Test name
Test status
Simulation time 16756146937 ps
CPU time 31.13 seconds
Started Jul 02 07:49:39 AM PDT 24
Finished Jul 02 07:50:12 AM PDT 24
Peak memory 217500 kb
Host smart-94746b66-b0e8-4344-b743-38e91a3f4aee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512409907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.512409907
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.672438
Short name T36
Test name
Test status
Simulation time 204823582519 ps
CPU time 963.84 seconds
Started Jul 02 07:49:35 AM PDT 24
Finished Jul 02 08:05:41 AM PDT 24
Peak memory 225668 kb
Host smart-d22504af-e334-48c7-9ff5-730ca514e7f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_si
g_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_corr
upt_sig_fatal_chk.672438
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1902254259
Short name T6
Test name
Test status
Simulation time 8223797693 ps
CPU time 45.05 seconds
Started Jul 02 07:49:23 AM PDT 24
Finished Jul 02 07:50:09 AM PDT 24
Peak memory 219300 kb
Host smart-ac1254f4-aab9-4bf1-b5be-6193cfed0fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902254259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1902254259
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.4077296255
Short name T320
Test name
Test status
Simulation time 42405484142 ps
CPU time 25.71 seconds
Started Jul 02 07:49:24 AM PDT 24
Finished Jul 02 07:49:50 AM PDT 24
Peak memory 211976 kb
Host smart-4ac8a70a-39e7-4ddb-bc99-01e190468a1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4077296255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.4077296255
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.687065357
Short name T74
Test name
Test status
Simulation time 8947200656 ps
CPU time 104.94 seconds
Started Jul 02 07:49:23 AM PDT 24
Finished Jul 02 07:51:09 AM PDT 24
Peak memory 219320 kb
Host smart-36d9a449-727c-4f24-b5c2-c6592b55c6d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687065357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.687065357
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.919034799
Short name T174
Test name
Test status
Simulation time 18560354596 ps
CPU time 24.72 seconds
Started Jul 02 07:49:46 AM PDT 24
Finished Jul 02 07:50:21 AM PDT 24
Peak memory 213232 kb
Host smart-bf1a689f-b9be-4b31-9d48-88ba007bbc43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919034799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.919034799
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3401545777
Short name T351
Test name
Test status
Simulation time 147603797447 ps
CPU time 506.59 seconds
Started Jul 02 07:49:25 AM PDT 24
Finished Jul 02 07:57:53 AM PDT 24
Peak memory 217800 kb
Host smart-367c6cf2-c48b-4f0f-a1fa-dd498359252f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401545777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3401545777
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1528813896
Short name T129
Test name
Test status
Simulation time 8073866375 ps
CPU time 32.95 seconds
Started Jul 02 07:49:39 AM PDT 24
Finished Jul 02 07:50:14 AM PDT 24
Peak memory 217576 kb
Host smart-19b08966-5a6e-4f43-b7ee-56fd9864cce7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1528813896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1528813896
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3028383799
Short name T281
Test name
Test status
Simulation time 14075828420 ps
CPU time 67.79 seconds
Started Jul 02 07:49:41 AM PDT 24
Finished Jul 02 07:50:53 AM PDT 24
Peak memory 216680 kb
Host smart-5ded2f3a-cf8f-4b3c-b391-f0a682df7e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028383799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3028383799
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.547189885
Short name T305
Test name
Test status
Simulation time 74030719674 ps
CPU time 179.91 seconds
Started Jul 02 07:49:35 AM PDT 24
Finished Jul 02 07:52:36 AM PDT 24
Peak memory 220960 kb
Host smart-ffea4a80-ec82-4d6f-9175-797982ce9013
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547189885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.547189885
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2485481180
Short name T217
Test name
Test status
Simulation time 5550594259 ps
CPU time 24.16 seconds
Started Jul 02 07:49:43 AM PDT 24
Finished Jul 02 07:50:15 AM PDT 24
Peak memory 216816 kb
Host smart-a0991be0-5346-4ba9-b32d-9027c73d6520
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485481180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2485481180
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.4252982019
Short name T1
Test name
Test status
Simulation time 249040645447 ps
CPU time 525.54 seconds
Started Jul 02 07:49:38 AM PDT 24
Finished Jul 02 07:58:25 AM PDT 24
Peak memory 239108 kb
Host smart-b1b64620-f4f9-48ed-8667-a84822ec1b40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252982019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.4252982019
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2193706590
Short name T345
Test name
Test status
Simulation time 16442007569 ps
CPU time 47.66 seconds
Started Jul 02 07:49:42 AM PDT 24
Finished Jul 02 07:50:33 AM PDT 24
Peak memory 219272 kb
Host smart-379f546e-527c-4911-8a5d-270c5361a7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193706590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2193706590
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2488317446
Short name T242
Test name
Test status
Simulation time 2290392382 ps
CPU time 12.99 seconds
Started Jul 02 07:49:35 AM PDT 24
Finished Jul 02 07:49:49 AM PDT 24
Peak memory 219280 kb
Host smart-f214a660-a380-4619-8c63-a0a5fe19be12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2488317446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2488317446
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.4047106628
Short name T28
Test name
Test status
Simulation time 7899068992 ps
CPU time 70.31 seconds
Started Jul 02 07:49:41 AM PDT 24
Finished Jul 02 07:50:54 AM PDT 24
Peak memory 216448 kb
Host smart-d3107133-fa0b-4678-befa-e90432b57de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047106628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.4047106628
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1713773928
Short name T230
Test name
Test status
Simulation time 3590960639 ps
CPU time 36.26 seconds
Started Jul 02 07:49:43 AM PDT 24
Finished Jul 02 07:50:27 AM PDT 24
Peak memory 219184 kb
Host smart-da9244b2-c13a-4df3-992e-eba081663c24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713773928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1713773928
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.1025353066
Short name T50
Test name
Test status
Simulation time 11870333422 ps
CPU time 459.64 seconds
Started Jul 02 07:49:33 AM PDT 24
Finished Jul 02 07:57:14 AM PDT 24
Peak memory 228236 kb
Host smart-2c5faa6a-7012-4be3-9f94-d3df7cc051ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025353066 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.1025353066
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.4068234512
Short name T313
Test name
Test status
Simulation time 5284452852 ps
CPU time 20.62 seconds
Started Jul 02 07:49:39 AM PDT 24
Finished Jul 02 07:50:02 AM PDT 24
Peak memory 217340 kb
Host smart-e29f6c0f-e696-4351-bb21-f4c815dbdbae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068234512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.4068234512
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.125425738
Short name T275
Test name
Test status
Simulation time 4128785999 ps
CPU time 223.35 seconds
Started Jul 02 07:49:34 AM PDT 24
Finished Jul 02 07:53:18 AM PDT 24
Peak memory 224364 kb
Host smart-9dc0b49c-d5d4-4e33-af5f-5ead92eea3f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125425738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.125425738
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2220600266
Short name T291
Test name
Test status
Simulation time 15360239531 ps
CPU time 63.68 seconds
Started Jul 02 07:49:40 AM PDT 24
Finished Jul 02 07:50:46 AM PDT 24
Peak memory 219300 kb
Host smart-5706a2fc-b0f8-490c-b91f-a56f9ea362f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220600266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2220600266
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3391000749
Short name T186
Test name
Test status
Simulation time 17816999599 ps
CPU time 34.19 seconds
Started Jul 02 07:49:38 AM PDT 24
Finished Jul 02 07:50:14 AM PDT 24
Peak memory 219280 kb
Host smart-264cc7c2-7788-4a71-bfc0-4bb88e9a39bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3391000749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3391000749
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3901564040
Short name T340
Test name
Test status
Simulation time 26781555167 ps
CPU time 81.02 seconds
Started Jul 02 07:49:38 AM PDT 24
Finished Jul 02 07:51:00 AM PDT 24
Peak memory 219292 kb
Host smart-906716e8-e159-4758-9971-dde9287b9631
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901564040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3901564040
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3409478139
Short name T3
Test name
Test status
Simulation time 510765336 ps
CPU time 11.94 seconds
Started Jul 02 07:49:06 AM PDT 24
Finished Jul 02 07:49:19 AM PDT 24
Peak memory 216872 kb
Host smart-3942dae4-fec4-4bbe-8e05-6ae1901f2f7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409478139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3409478139
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3879712469
Short name T155
Test name
Test status
Simulation time 138490151097 ps
CPU time 406.67 seconds
Started Jul 02 07:49:23 AM PDT 24
Finished Jul 02 07:56:11 AM PDT 24
Peak memory 234772 kb
Host smart-d57ea97c-6b19-4c42-8239-4994d0c6ee66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879712469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3879712469
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3023151988
Short name T258
Test name
Test status
Simulation time 35887314157 ps
CPU time 55.77 seconds
Started Jul 02 07:49:11 AM PDT 24
Finished Jul 02 07:50:07 AM PDT 24
Peak memory 219248 kb
Host smart-a0b5f677-8eba-4c86-978b-879607a9818f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023151988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3023151988
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3865524924
Short name T210
Test name
Test status
Simulation time 769306569 ps
CPU time 15.25 seconds
Started Jul 02 07:49:02 AM PDT 24
Finished Jul 02 07:49:19 AM PDT 24
Peak memory 219204 kb
Host smart-aabd5be5-253c-46f1-b4f6-2a9d619a6e46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3865524924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3865524924
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3426642523
Short name T27
Test name
Test status
Simulation time 449479347 ps
CPU time 118.21 seconds
Started Jul 02 07:49:11 AM PDT 24
Finished Jul 02 07:51:10 AM PDT 24
Peak memory 238724 kb
Host smart-afaa9ea6-f651-4115-8ef8-07268836e088
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426642523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3426642523
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.609827102
Short name T149
Test name
Test status
Simulation time 1721631867 ps
CPU time 32.04 seconds
Started Jul 02 07:49:09 AM PDT 24
Finished Jul 02 07:49:42 AM PDT 24
Peak memory 216120 kb
Host smart-d5a12b61-247b-4bbb-8b31-3003139326d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609827102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.609827102
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1403741421
Short name T75
Test name
Test status
Simulation time 39293822162 ps
CPU time 193.32 seconds
Started Jul 02 07:49:03 AM PDT 24
Finished Jul 02 07:52:19 AM PDT 24
Peak memory 220728 kb
Host smart-f98c76e6-97f5-4828-84d1-0571d2b02b7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403741421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1403741421
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2132038999
Short name T25
Test name
Test status
Simulation time 6033043612 ps
CPU time 27.63 seconds
Started Jul 02 07:49:28 AM PDT 24
Finished Jul 02 07:49:57 AM PDT 24
Peak memory 217324 kb
Host smart-03be9c6b-a1ab-4c09-b2b9-d00262e593ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132038999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2132038999
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2067359873
Short name T232
Test name
Test status
Simulation time 66869404837 ps
CPU time 331.89 seconds
Started Jul 02 07:49:33 AM PDT 24
Finished Jul 02 07:55:07 AM PDT 24
Peak memory 235128 kb
Host smart-f3005473-254b-44a6-9022-68d7a7f34f0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067359873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2067359873
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.4036268758
Short name T225
Test name
Test status
Simulation time 7799932953 ps
CPU time 29.82 seconds
Started Jul 02 07:49:35 AM PDT 24
Finished Jul 02 07:50:07 AM PDT 24
Peak memory 219364 kb
Host smart-cdbc8733-ba8a-4daa-9a99-1c6f35791ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036268758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.4036268758
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2988448906
Short name T302
Test name
Test status
Simulation time 478755068 ps
CPU time 10.16 seconds
Started Jul 02 07:49:36 AM PDT 24
Finished Jul 02 07:49:48 AM PDT 24
Peak memory 219120 kb
Host smart-30469137-94bd-42a5-947b-b8691ff035de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2988448906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2988448906
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3230419448
Short name T241
Test name
Test status
Simulation time 702892957 ps
CPU time 19.35 seconds
Started Jul 02 07:49:43 AM PDT 24
Finished Jul 02 07:50:09 AM PDT 24
Peak memory 216728 kb
Host smart-f1118380-4860-4337-834e-519f393a8519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230419448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3230419448
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3237221765
Short name T354
Test name
Test status
Simulation time 32860997393 ps
CPU time 96.7 seconds
Started Jul 02 07:49:39 AM PDT 24
Finished Jul 02 07:51:17 AM PDT 24
Peak memory 220536 kb
Host smart-efa83333-9db4-44de-b43d-123fda8f04b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237221765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3237221765
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.3113124177
Short name T12
Test name
Test status
Simulation time 299510087621 ps
CPU time 2844.83 seconds
Started Jul 02 07:49:44 AM PDT 24
Finished Jul 02 08:37:19 AM PDT 24
Peak memory 252112 kb
Host smart-244d65ce-2125-477a-b0d3-6f044c93c79a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113124177 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.3113124177
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1796014299
Short name T175
Test name
Test status
Simulation time 7922553393 ps
CPU time 20.88 seconds
Started Jul 02 07:49:41 AM PDT 24
Finished Jul 02 07:50:04 AM PDT 24
Peak memory 213216 kb
Host smart-8bd61de4-0fed-4280-8286-dbd6f6b1c26c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796014299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1796014299
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2072911798
Short name T195
Test name
Test status
Simulation time 206144937552 ps
CPU time 595.49 seconds
Started Jul 02 07:49:43 AM PDT 24
Finished Jul 02 07:59:45 AM PDT 24
Peak memory 233596 kb
Host smart-bdb9fa2b-af1a-48a7-9930-fef468fb1ef1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072911798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2072911798
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3133021954
Short name T119
Test name
Test status
Simulation time 4895410554 ps
CPU time 47.68 seconds
Started Jul 02 07:49:40 AM PDT 24
Finished Jul 02 07:50:30 AM PDT 24
Peak memory 219288 kb
Host smart-64d4f4e6-c250-492b-8c4d-357263902960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133021954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3133021954
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.121709137
Short name T30
Test name
Test status
Simulation time 4285422818 ps
CPU time 34.59 seconds
Started Jul 02 07:49:48 AM PDT 24
Finished Jul 02 07:50:33 AM PDT 24
Peak memory 219580 kb
Host smart-fdba20de-8445-4493-8b82-543c58586b5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=121709137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.121709137
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.4063657092
Short name T346
Test name
Test status
Simulation time 8566339293 ps
CPU time 66.51 seconds
Started Jul 02 07:49:38 AM PDT 24
Finished Jul 02 07:50:46 AM PDT 24
Peak memory 216532 kb
Host smart-95f83c36-9067-49c2-beee-c36602511020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063657092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.4063657092
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1087636789
Short name T127
Test name
Test status
Simulation time 12790247131 ps
CPU time 55.92 seconds
Started Jul 02 07:49:42 AM PDT 24
Finished Jul 02 07:50:43 AM PDT 24
Peak memory 218368 kb
Host smart-36ccb34c-10b8-4153-8447-609b2420eb62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087636789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1087636789
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2473465140
Short name T54
Test name
Test status
Simulation time 47030618639 ps
CPU time 1917.67 seconds
Started Jul 02 07:49:47 AM PDT 24
Finished Jul 02 08:21:56 AM PDT 24
Peak memory 243948 kb
Host smart-be620075-9f44-4661-88c2-d604311e842a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473465140 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.2473465140
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3360650898
Short name T152
Test name
Test status
Simulation time 2645389652 ps
CPU time 24.34 seconds
Started Jul 02 07:49:47 AM PDT 24
Finished Jul 02 07:50:22 AM PDT 24
Peak memory 217196 kb
Host smart-00e64d7e-48d7-4482-aafd-596c12817a9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360650898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3360650898
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.4199002574
Short name T167
Test name
Test status
Simulation time 117126826467 ps
CPU time 271.29 seconds
Started Jul 02 07:49:44 AM PDT 24
Finished Jul 02 07:54:25 AM PDT 24
Peak memory 237688 kb
Host smart-7bd1d502-16bb-45b3-b984-995595ed7589
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199002574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.4199002574
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3908253204
Short name T284
Test name
Test status
Simulation time 4105958725 ps
CPU time 31.81 seconds
Started Jul 02 07:49:43 AM PDT 24
Finished Jul 02 07:50:21 AM PDT 24
Peak memory 219264 kb
Host smart-19c762e4-df92-4135-896d-7c4a24b99e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908253204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3908253204
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2209082696
Short name T181
Test name
Test status
Simulation time 4114849794 ps
CPU time 22.93 seconds
Started Jul 02 07:49:40 AM PDT 24
Finished Jul 02 07:50:05 AM PDT 24
Peak memory 211328 kb
Host smart-cdb14192-ed00-47e5-96a1-142be5ff4147
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2209082696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2209082696
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.3985600941
Short name T279
Test name
Test status
Simulation time 6634385180 ps
CPU time 65.27 seconds
Started Jul 02 07:49:45 AM PDT 24
Finished Jul 02 07:51:00 AM PDT 24
Peak memory 217244 kb
Host smart-9a9fedbd-1969-47f8-a791-a886023977ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985600941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.3985600941
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1671484603
Short name T29
Test name
Test status
Simulation time 62125693934 ps
CPU time 68.83 seconds
Started Jul 02 07:49:38 AM PDT 24
Finished Jul 02 07:50:48 AM PDT 24
Peak memory 219280 kb
Host smart-15ff25c6-ac77-4eb8-877c-9edfb183f2e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671484603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1671484603
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2844928521
Short name T323
Test name
Test status
Simulation time 4269904663 ps
CPU time 31.68 seconds
Started Jul 02 07:49:42 AM PDT 24
Finished Jul 02 07:50:19 AM PDT 24
Peak memory 217036 kb
Host smart-069f25ee-a4f4-4f02-ae9d-d2556630d6e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844928521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2844928521
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1813074541
Short name T311
Test name
Test status
Simulation time 285655583780 ps
CPU time 860.22 seconds
Started Jul 02 07:49:42 AM PDT 24
Finished Jul 02 08:04:08 AM PDT 24
Peak memory 216996 kb
Host smart-18f19e58-f1b6-42e4-a57d-9f06c30ac07e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813074541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1813074541
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.143821714
Short name T10
Test name
Test status
Simulation time 24116658247 ps
CPU time 45.85 seconds
Started Jul 02 07:49:44 AM PDT 24
Finished Jul 02 07:50:38 AM PDT 24
Peak memory 219284 kb
Host smart-c204ee74-bb14-40f4-99c4-ec5a6e949dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143821714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.143821714
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.4047838562
Short name T226
Test name
Test status
Simulation time 254061298 ps
CPU time 10.51 seconds
Started Jul 02 07:49:37 AM PDT 24
Finished Jul 02 07:49:48 AM PDT 24
Peak memory 219204 kb
Host smart-e4522789-c80a-4766-a418-f7328f94e4bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4047838562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.4047838562
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3111392796
Short name T13
Test name
Test status
Simulation time 1388233726 ps
CPU time 20.69 seconds
Started Jul 02 07:49:47 AM PDT 24
Finished Jul 02 07:50:18 AM PDT 24
Peak memory 216624 kb
Host smart-87f6982c-3692-4985-a2c7-2d1542b87655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111392796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3111392796
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.188667303
Short name T235
Test name
Test status
Simulation time 5020970106 ps
CPU time 62.53 seconds
Started Jul 02 07:49:41 AM PDT 24
Finished Jul 02 07:50:46 AM PDT 24
Peak memory 216552 kb
Host smart-d7c1b6de-0e5c-4ddd-96f7-580a5b90e9b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188667303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.188667303
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2537184316
Short name T265
Test name
Test status
Simulation time 7448869600 ps
CPU time 22.45 seconds
Started Jul 02 07:49:34 AM PDT 24
Finished Jul 02 07:49:58 AM PDT 24
Peak memory 217364 kb
Host smart-a0bc5c29-a48d-4f0d-b697-04a949415503
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537184316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2537184316
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3179411794
Short name T270
Test name
Test status
Simulation time 63741308009 ps
CPU time 262.53 seconds
Started Jul 02 07:49:42 AM PDT 24
Finished Jul 02 07:54:08 AM PDT 24
Peak memory 241740 kb
Host smart-fefda9ee-b7f0-4237-84f0-500abdd4520b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179411794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3179411794
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1201715539
Short name T158
Test name
Test status
Simulation time 4929382710 ps
CPU time 48.34 seconds
Started Jul 02 07:49:43 AM PDT 24
Finished Jul 02 07:50:38 AM PDT 24
Peak memory 219200 kb
Host smart-d14b00ec-5604-4748-98a5-2522e8d0182f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201715539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1201715539
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1926801550
Short name T18
Test name
Test status
Simulation time 240700934 ps
CPU time 10.11 seconds
Started Jul 02 07:49:45 AM PDT 24
Finished Jul 02 07:50:04 AM PDT 24
Peak memory 219236 kb
Host smart-edaa3658-01cc-45a2-b02b-76aac11a89b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1926801550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1926801550
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3359369149
Short name T239
Test name
Test status
Simulation time 36288826777 ps
CPU time 54.08 seconds
Started Jul 02 07:49:38 AM PDT 24
Finished Jul 02 07:50:34 AM PDT 24
Peak memory 216160 kb
Host smart-1599b6e0-300c-4d1d-9f4d-afcb5a5395c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359369149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3359369149
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2647068663
Short name T197
Test name
Test status
Simulation time 1458608083 ps
CPU time 45 seconds
Started Jul 02 07:49:42 AM PDT 24
Finished Jul 02 07:50:31 AM PDT 24
Peak memory 220088 kb
Host smart-3ed2f72d-ea9e-467f-87d2-008a2c5c6920
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647068663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2647068663
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.4251176897
Short name T173
Test name
Test status
Simulation time 687949912 ps
CPU time 8.26 seconds
Started Jul 02 07:49:42 AM PDT 24
Finished Jul 02 07:49:54 AM PDT 24
Peak memory 217084 kb
Host smart-bdb2ab49-3c15-4979-96a6-0eac204b41d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251176897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.4251176897
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3989503389
Short name T272
Test name
Test status
Simulation time 4306595015 ps
CPU time 277.67 seconds
Started Jul 02 07:49:42 AM PDT 24
Finished Jul 02 07:54:32 AM PDT 24
Peak memory 234508 kb
Host smart-ebba9e41-e8da-4018-9143-5cd63b85afe5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989503389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3989503389
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2426724373
Short name T124
Test name
Test status
Simulation time 18402285644 ps
CPU time 47.53 seconds
Started Jul 02 07:49:45 AM PDT 24
Finished Jul 02 07:50:42 AM PDT 24
Peak memory 219288 kb
Host smart-fd1b2a0b-69ab-447c-aab2-5609c9e62b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426724373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2426724373
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.4291713246
Short name T202
Test name
Test status
Simulation time 15747367075 ps
CPU time 31.6 seconds
Started Jul 02 07:49:41 AM PDT 24
Finished Jul 02 07:50:16 AM PDT 24
Peak memory 219300 kb
Host smart-63f37846-d9e4-4ccd-9bf5-31ee9d8d7c33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4291713246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.4291713246
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1130060674
Short name T142
Test name
Test status
Simulation time 30063034574 ps
CPU time 75.5 seconds
Started Jul 02 07:49:45 AM PDT 24
Finished Jul 02 07:51:09 AM PDT 24
Peak memory 215960 kb
Host smart-43345c3e-51d9-4c95-9646-2c574ff06c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130060674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1130060674
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3638678952
Short name T171
Test name
Test status
Simulation time 5568581940 ps
CPU time 69.17 seconds
Started Jul 02 07:49:45 AM PDT 24
Finished Jul 02 07:51:05 AM PDT 24
Peak memory 220460 kb
Host smart-8380ce4e-b587-4fed-95fe-1777ccc5aba5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638678952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3638678952
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3720293791
Short name T350
Test name
Test status
Simulation time 5053856989 ps
CPU time 17.15 seconds
Started Jul 02 07:49:47 AM PDT 24
Finished Jul 02 07:50:15 AM PDT 24
Peak memory 217788 kb
Host smart-f7ca19d2-5f65-43f5-8211-827903127150
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720293791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3720293791
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3875965829
Short name T261
Test name
Test status
Simulation time 106827801063 ps
CPU time 325.7 seconds
Started Jul 02 07:49:45 AM PDT 24
Finished Jul 02 07:55:20 AM PDT 24
Peak memory 228608 kb
Host smart-8f7740f8-d1f8-4e24-943d-6faca75ad703
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875965829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3875965829
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1181247541
Short name T40
Test name
Test status
Simulation time 332609885 ps
CPU time 19.37 seconds
Started Jul 02 07:49:45 AM PDT 24
Finished Jul 02 07:50:14 AM PDT 24
Peak memory 219224 kb
Host smart-857af6b7-1fcb-4b80-a538-931382bacdad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181247541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1181247541
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2621176108
Short name T135
Test name
Test status
Simulation time 961005399 ps
CPU time 10.12 seconds
Started Jul 02 07:49:43 AM PDT 24
Finished Jul 02 07:50:01 AM PDT 24
Peak memory 219296 kb
Host smart-4af90957-f7ea-4c17-9712-00430f9f7d53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2621176108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2621176108
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.136008401
Short name T277
Test name
Test status
Simulation time 34704188811 ps
CPU time 61.86 seconds
Started Jul 02 07:49:41 AM PDT 24
Finished Jul 02 07:50:45 AM PDT 24
Peak memory 218788 kb
Host smart-fb2f3f03-6b8f-4721-a29e-b969c80db8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136008401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.136008401
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2890263573
Short name T215
Test name
Test status
Simulation time 54885695501 ps
CPU time 92.18 seconds
Started Jul 02 07:49:50 AM PDT 24
Finished Jul 02 07:51:33 AM PDT 24
Peak memory 220688 kb
Host smart-a3552f8c-9b77-4ada-903d-0bfa187bf6b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890263573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2890263573
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1297893468
Short name T9
Test name
Test status
Simulation time 8876170633 ps
CPU time 21.22 seconds
Started Jul 02 07:49:47 AM PDT 24
Finished Jul 02 07:50:19 AM PDT 24
Peak memory 217308 kb
Host smart-1f188821-40ff-4846-9a84-b4bcb73c4b8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297893468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1297893468
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.4127528134
Short name T252
Test name
Test status
Simulation time 63687957738 ps
CPU time 587.33 seconds
Started Jul 02 07:49:46 AM PDT 24
Finished Jul 02 07:59:49 AM PDT 24
Peak memory 247512 kb
Host smart-96f4734f-a760-45c4-9947-655f514da555
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127528134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.4127528134
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2109414220
Short name T46
Test name
Test status
Simulation time 6284291730 ps
CPU time 53.83 seconds
Started Jul 02 07:49:44 AM PDT 24
Finished Jul 02 07:50:46 AM PDT 24
Peak memory 219232 kb
Host smart-db44d204-6f2d-4210-bf7c-8c6dd8669068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109414220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2109414220
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.77849356
Short name T185
Test name
Test status
Simulation time 590196462 ps
CPU time 14.43 seconds
Started Jul 02 07:49:38 AM PDT 24
Finished Jul 02 07:49:54 AM PDT 24
Peak memory 219124 kb
Host smart-339588d0-aa96-488e-9113-fdcdfe31634e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=77849356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.77849356
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3751289555
Short name T138
Test name
Test status
Simulation time 21864161735 ps
CPU time 49 seconds
Started Jul 02 07:49:45 AM PDT 24
Finished Jul 02 07:50:43 AM PDT 24
Peak memory 215988 kb
Host smart-3c2bc7a4-abd9-4527-bb6b-a5fe03826a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751289555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3751289555
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1690312877
Short name T229
Test name
Test status
Simulation time 2819700505 ps
CPU time 52.92 seconds
Started Jul 02 07:49:36 AM PDT 24
Finished Jul 02 07:50:30 AM PDT 24
Peak memory 219288 kb
Host smart-fd4033d7-892e-4747-83b4-2b8064888ec6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690312877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1690312877
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1407695028
Short name T256
Test name
Test status
Simulation time 4919000132 ps
CPU time 30.55 seconds
Started Jul 02 07:49:46 AM PDT 24
Finished Jul 02 07:50:28 AM PDT 24
Peak memory 213220 kb
Host smart-ccb10827-522f-4a34-9f8c-e7385b17ecf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407695028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1407695028
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.325915171
Short name T358
Test name
Test status
Simulation time 57884204312 ps
CPU time 326.92 seconds
Started Jul 02 07:49:43 AM PDT 24
Finished Jul 02 07:55:18 AM PDT 24
Peak memory 234924 kb
Host smart-6faebda0-abc4-4626-b2f1-609749a8f4bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325915171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.325915171
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.777050806
Short name T44
Test name
Test status
Simulation time 4909510866 ps
CPU time 48.14 seconds
Started Jul 02 07:49:46 AM PDT 24
Finished Jul 02 07:50:46 AM PDT 24
Peak memory 219356 kb
Host smart-da18d1c2-c788-4b4d-be28-f0c8fdca5074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777050806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.777050806
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1881548330
Short name T278
Test name
Test status
Simulation time 2303813649 ps
CPU time 16.99 seconds
Started Jul 02 07:49:46 AM PDT 24
Finished Jul 02 07:50:14 AM PDT 24
Peak memory 219320 kb
Host smart-92b7c16f-dfa8-4500-b8f5-2e646482ecee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1881548330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1881548330
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3375701396
Short name T249
Test name
Test status
Simulation time 1386726894 ps
CPU time 20.71 seconds
Started Jul 02 07:49:50 AM PDT 24
Finished Jul 02 07:50:21 AM PDT 24
Peak memory 216360 kb
Host smart-ab1242ee-660a-4a10-a639-83c9eace7767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375701396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3375701396
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1943993479
Short name T341
Test name
Test status
Simulation time 39490662943 ps
CPU time 115.93 seconds
Started Jul 02 07:49:46 AM PDT 24
Finished Jul 02 07:51:52 AM PDT 24
Peak memory 227476 kb
Host smart-a6415a32-9962-4499-b1d3-f601a2e01336
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943993479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1943993479
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1366584946
Short name T118
Test name
Test status
Simulation time 8473381596 ps
CPU time 31.3 seconds
Started Jul 02 07:49:41 AM PDT 24
Finished Jul 02 07:50:15 AM PDT 24
Peak memory 217488 kb
Host smart-d606da26-d623-4cba-9d8b-ff2a5f47eb60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366584946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1366584946
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1700554840
Short name T355
Test name
Test status
Simulation time 250578893032 ps
CPU time 697.87 seconds
Started Jul 02 07:49:43 AM PDT 24
Finished Jul 02 08:01:29 AM PDT 24
Peak memory 239772 kb
Host smart-e7ec815b-191a-4189-b034-af15cae9ee88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700554840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1700554840
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1757454590
Short name T289
Test name
Test status
Simulation time 13680874085 ps
CPU time 39.85 seconds
Started Jul 02 07:49:45 AM PDT 24
Finished Jul 02 07:50:35 AM PDT 24
Peak memory 219248 kb
Host smart-d88c90c3-2f3f-4f1a-bbb7-e699370c9bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757454590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1757454590
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.128606397
Short name T353
Test name
Test status
Simulation time 3618019418 ps
CPU time 31.18 seconds
Started Jul 02 07:49:42 AM PDT 24
Finished Jul 02 07:50:19 AM PDT 24
Peak memory 219272 kb
Host smart-7b93c5b7-4652-4a3b-8953-687562f2c35d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=128606397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.128606397
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1983633113
Short name T194
Test name
Test status
Simulation time 1662110639 ps
CPU time 33.37 seconds
Started Jul 02 07:49:45 AM PDT 24
Finished Jul 02 07:50:28 AM PDT 24
Peak memory 215732 kb
Host smart-031fedc6-06d3-4953-b075-6630116699f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983633113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1983633113
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2158442031
Short name T43
Test name
Test status
Simulation time 14018469109 ps
CPU time 37.82 seconds
Started Jul 02 07:49:46 AM PDT 24
Finished Jul 02 07:50:34 AM PDT 24
Peak memory 219188 kb
Host smart-1b071c5d-8f89-4a03-9e53-04af66487c17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158442031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2158442031
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3163121686
Short name T51
Test name
Test status
Simulation time 20631633299 ps
CPU time 7083.75 seconds
Started Jul 02 07:49:44 AM PDT 24
Finished Jul 02 09:47:58 AM PDT 24
Peak memory 229544 kb
Host smart-9061b1a3-7a4e-4936-aac5-fbb52697399f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163121686 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3163121686
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.496627259
Short name T136
Test name
Test status
Simulation time 345438885 ps
CPU time 8.4 seconds
Started Jul 02 07:49:03 AM PDT 24
Finished Jul 02 07:49:13 AM PDT 24
Peak memory 217364 kb
Host smart-76b88ee0-7dc8-42e1-9aa2-5fffe59e5130
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496627259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.496627259
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.796020726
Short name T347
Test name
Test status
Simulation time 8978999219 ps
CPU time 203.88 seconds
Started Jul 02 07:49:03 AM PDT 24
Finished Jul 02 07:52:29 AM PDT 24
Peak memory 228308 kb
Host smart-d90c36da-eef5-43b0-96ac-f77394cc6e84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796020726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.796020726
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3882979205
Short name T348
Test name
Test status
Simulation time 7488044999 ps
CPU time 31.8 seconds
Started Jul 02 07:49:10 AM PDT 24
Finished Jul 02 07:49:43 AM PDT 24
Peak memory 219296 kb
Host smart-37bfa031-dc7e-4f6e-af2c-57de286aff10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882979205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3882979205
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1127218454
Short name T260
Test name
Test status
Simulation time 913135425 ps
CPU time 16.9 seconds
Started Jul 02 07:49:19 AM PDT 24
Finished Jul 02 07:49:36 AM PDT 24
Peak memory 219212 kb
Host smart-aa930e8c-286a-4ff6-a2a6-a9bd74e1a1d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1127218454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1127218454
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1362249817
Short name T22
Test name
Test status
Simulation time 1271241639 ps
CPU time 233.06 seconds
Started Jul 02 07:49:02 AM PDT 24
Finished Jul 02 07:53:02 AM PDT 24
Peak memory 238016 kb
Host smart-4de33d54-1d22-4121-8e4a-1766200cb8f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362249817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1362249817
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2568063424
Short name T271
Test name
Test status
Simulation time 7554844167 ps
CPU time 62.23 seconds
Started Jul 02 07:49:10 AM PDT 24
Finished Jul 02 07:50:12 AM PDT 24
Peak memory 216684 kb
Host smart-c7dd6fe0-6626-4599-843a-2072c68bfe47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568063424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2568063424
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1401554761
Short name T325
Test name
Test status
Simulation time 13969751644 ps
CPU time 35.15 seconds
Started Jul 02 07:49:03 AM PDT 24
Finished Jul 02 07:49:40 AM PDT 24
Peak memory 212088 kb
Host smart-77c33b56-979d-403b-8fe4-d6be63d979ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401554761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1401554761
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2734755203
Short name T317
Test name
Test status
Simulation time 1749023937 ps
CPU time 19.12 seconds
Started Jul 02 07:49:45 AM PDT 24
Finished Jul 02 07:50:13 AM PDT 24
Peak memory 217020 kb
Host smart-e8381e29-a15c-42fc-ab69-6a9095f563d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734755203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2734755203
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2180876762
Short name T223
Test name
Test status
Simulation time 2091794120 ps
CPU time 172.79 seconds
Started Jul 02 07:49:44 AM PDT 24
Finished Jul 02 07:52:44 AM PDT 24
Peak memory 236824 kb
Host smart-71bb0be7-64fd-4190-a017-192ba3218d17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180876762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2180876762
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.474588320
Short name T287
Test name
Test status
Simulation time 3112052172 ps
CPU time 38.08 seconds
Started Jul 02 07:49:38 AM PDT 24
Finished Jul 02 07:50:18 AM PDT 24
Peak memory 219268 kb
Host smart-4575bf71-10fb-4d7c-b496-d66cd26e3f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474588320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.474588320
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3271593684
Short name T310
Test name
Test status
Simulation time 22606152610 ps
CPU time 30.49 seconds
Started Jul 02 07:49:47 AM PDT 24
Finished Jul 02 07:50:28 AM PDT 24
Peak memory 219332 kb
Host smart-ed4d661e-d35a-4d27-8ed5-528046995490
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3271593684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3271593684
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3182566794
Short name T263
Test name
Test status
Simulation time 3433516977 ps
CPU time 39.2 seconds
Started Jul 02 07:49:45 AM PDT 24
Finished Jul 02 07:50:40 AM PDT 24
Peak memory 216200 kb
Host smart-4c6c6517-ba1b-4d97-9edd-daf194a42d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182566794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3182566794
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3728533594
Short name T328
Test name
Test status
Simulation time 10108645047 ps
CPU time 56.95 seconds
Started Jul 02 07:49:46 AM PDT 24
Finished Jul 02 07:50:54 AM PDT 24
Peak memory 217272 kb
Host smart-d38f182c-420b-458b-ba8b-0ce1b83a677e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728533594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3728533594
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.4194847812
Short name T62
Test name
Test status
Simulation time 591516607 ps
CPU time 8.4 seconds
Started Jul 02 07:49:46 AM PDT 24
Finished Jul 02 07:50:04 AM PDT 24
Peak memory 217080 kb
Host smart-a7691474-d71c-4497-b7f4-ca45a6750f79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194847812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.4194847812
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1120686924
Short name T133
Test name
Test status
Simulation time 21947564259 ps
CPU time 356.32 seconds
Started Jul 02 07:49:47 AM PDT 24
Finished Jul 02 07:55:54 AM PDT 24
Peak memory 226136 kb
Host smart-58fe0fff-5b82-4af6-8b76-d8cc3bcd8f61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120686924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1120686924
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3627375994
Short name T344
Test name
Test status
Simulation time 332559670 ps
CPU time 18.83 seconds
Started Jul 02 07:49:45 AM PDT 24
Finished Jul 02 07:50:14 AM PDT 24
Peak memory 219228 kb
Host smart-f7fa69ba-c66f-42bb-aa38-4017ff63589a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627375994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3627375994
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2608313489
Short name T336
Test name
Test status
Simulation time 707174071 ps
CPU time 10.57 seconds
Started Jul 02 07:49:44 AM PDT 24
Finished Jul 02 07:50:02 AM PDT 24
Peak memory 219236 kb
Host smart-2386e50c-474c-4dbc-8fd1-94889017b72f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2608313489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2608313489
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3850623325
Short name T296
Test name
Test status
Simulation time 28885196076 ps
CPU time 68.4 seconds
Started Jul 02 07:49:43 AM PDT 24
Finished Jul 02 07:50:59 AM PDT 24
Peak memory 215996 kb
Host smart-92f7a4f1-e42c-4553-a02a-c84342d13150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850623325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3850623325
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.710440007
Short name T288
Test name
Test status
Simulation time 8713039581 ps
CPU time 75.02 seconds
Started Jul 02 07:49:46 AM PDT 24
Finished Jul 02 07:51:12 AM PDT 24
Peak memory 218088 kb
Host smart-65b212fd-58c1-4ca6-9960-fa1ae32eb15d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710440007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.710440007
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1029708188
Short name T234
Test name
Test status
Simulation time 11241308521 ps
CPU time 24.67 seconds
Started Jul 02 07:49:44 AM PDT 24
Finished Jul 02 07:50:18 AM PDT 24
Peak memory 213236 kb
Host smart-b6703aa8-7cb4-46e0-bf7f-ae804cf592fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029708188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1029708188
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2648539585
Short name T312
Test name
Test status
Simulation time 18873393575 ps
CPU time 252.48 seconds
Started Jul 02 07:49:46 AM PDT 24
Finished Jul 02 07:54:10 AM PDT 24
Peak memory 236236 kb
Host smart-8e4a1be5-3994-4362-81af-8eb537b4eabd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648539585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2648539585
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3572502855
Short name T357
Test name
Test status
Simulation time 27796747549 ps
CPU time 56.52 seconds
Started Jul 02 07:49:46 AM PDT 24
Finished Jul 02 07:50:52 AM PDT 24
Peak memory 219292 kb
Host smart-e53fac12-c43b-4945-b115-2fac9429be00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572502855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3572502855
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2241560671
Short name T4
Test name
Test status
Simulation time 3217977764 ps
CPU time 28.82 seconds
Started Jul 02 07:49:48 AM PDT 24
Finished Jul 02 07:50:28 AM PDT 24
Peak memory 219332 kb
Host smart-6eb8883f-0b8e-44a9-be52-181e33d5ea9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2241560671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2241560671
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2086764561
Short name T268
Test name
Test status
Simulation time 22404213646 ps
CPU time 65.21 seconds
Started Jul 02 07:49:43 AM PDT 24
Finished Jul 02 07:50:56 AM PDT 24
Peak memory 217640 kb
Host smart-ecf5b567-aaf9-44d9-a83b-0a8ec0a42d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086764561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2086764561
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1420215816
Short name T163
Test name
Test status
Simulation time 1063962805 ps
CPU time 29.66 seconds
Started Jul 02 07:50:40 AM PDT 24
Finished Jul 02 07:51:13 AM PDT 24
Peak memory 217668 kb
Host smart-3d352121-bdde-487b-8d94-06665ed6f650
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420215816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1420215816
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.617101972
Short name T52
Test name
Test status
Simulation time 31941832664 ps
CPU time 1169.93 seconds
Started Jul 02 07:49:54 AM PDT 24
Finished Jul 02 08:09:33 AM PDT 24
Peak memory 234516 kb
Host smart-71c287f5-290f-4910-a78a-a2d80eed3182
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617101972 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.617101972
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3245277977
Short name T342
Test name
Test status
Simulation time 174521264 ps
CPU time 8.1 seconds
Started Jul 02 07:49:41 AM PDT 24
Finished Jul 02 07:49:51 AM PDT 24
Peak memory 217096 kb
Host smart-6af7de9d-6fa0-4ec0-a048-62951a071eca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245277977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3245277977
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3561386184
Short name T140
Test name
Test status
Simulation time 43805152482 ps
CPU time 551.06 seconds
Started Jul 02 07:49:48 AM PDT 24
Finished Jul 02 07:59:10 AM PDT 24
Peak memory 217772 kb
Host smart-f15ea8e9-90cb-45de-ac4c-c83fa0563f97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561386184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3561386184
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1109679034
Short name T349
Test name
Test status
Simulation time 6353507811 ps
CPU time 39.53 seconds
Started Jul 02 07:49:51 AM PDT 24
Finished Jul 02 07:50:40 AM PDT 24
Peak memory 219264 kb
Host smart-6f5b578f-d19e-4bb8-84b2-a31f622b83c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109679034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1109679034
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.251837398
Short name T228
Test name
Test status
Simulation time 51879163986 ps
CPU time 29.02 seconds
Started Jul 02 07:49:44 AM PDT 24
Finished Jul 02 07:50:23 AM PDT 24
Peak memory 219252 kb
Host smart-32dedeb2-f92c-4927-affe-32a5944065b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=251837398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.251837398
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2770508619
Short name T205
Test name
Test status
Simulation time 7276068767 ps
CPU time 30.93 seconds
Started Jul 02 07:49:45 AM PDT 24
Finished Jul 02 07:50:27 AM PDT 24
Peak memory 217192 kb
Host smart-ac470b59-1f14-4f58-8308-3cbacbf74e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770508619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2770508619
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1124138520
Short name T104
Test name
Test status
Simulation time 62285595230 ps
CPU time 98.86 seconds
Started Jul 02 07:49:46 AM PDT 24
Finished Jul 02 07:51:35 AM PDT 24
Peak memory 219352 kb
Host smart-8d5ac630-edd8-46ab-a97a-ffc1290c76a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124138520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1124138520
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1966183980
Short name T301
Test name
Test status
Simulation time 15381014493 ps
CPU time 30.52 seconds
Started Jul 02 07:49:45 AM PDT 24
Finished Jul 02 07:50:26 AM PDT 24
Peak memory 217244 kb
Host smart-c23bc76c-a71b-4130-8052-21a8499b16c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966183980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1966183980
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2631957062
Short name T298
Test name
Test status
Simulation time 159235445459 ps
CPU time 902.35 seconds
Started Jul 02 07:49:46 AM PDT 24
Finished Jul 02 08:05:00 AM PDT 24
Peak memory 225680 kb
Host smart-7b0c8a40-9a35-4f7b-90a6-de7ee3fde394
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631957062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2631957062
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2788114656
Short name T330
Test name
Test status
Simulation time 18839264876 ps
CPU time 48.18 seconds
Started Jul 02 07:49:42 AM PDT 24
Finished Jul 02 07:50:35 AM PDT 24
Peak memory 219284 kb
Host smart-d74b906c-6a4d-4ff1-a4fa-aaffba29ed42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788114656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2788114656
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2237444534
Short name T193
Test name
Test status
Simulation time 2559975565 ps
CPU time 23.02 seconds
Started Jul 02 07:49:54 AM PDT 24
Finished Jul 02 07:50:26 AM PDT 24
Peak memory 211572 kb
Host smart-73b14ab5-be37-49bf-8677-202d77968166
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2237444534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2237444534
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3415798614
Short name T221
Test name
Test status
Simulation time 24060027918 ps
CPU time 39.51 seconds
Started Jul 02 07:49:46 AM PDT 24
Finished Jul 02 07:50:37 AM PDT 24
Peak memory 216908 kb
Host smart-d3f5a7b6-9c2c-4a7e-a8db-cedab60521ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415798614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3415798614
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2774814589
Short name T80
Test name
Test status
Simulation time 19233909081 ps
CPU time 66.74 seconds
Started Jul 02 07:49:42 AM PDT 24
Finished Jul 02 07:50:54 AM PDT 24
Peak memory 217592 kb
Host smart-b83a796b-2e90-49db-9b4e-952aa603e3bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774814589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2774814589
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2724407689
Short name T220
Test name
Test status
Simulation time 185719308 ps
CPU time 8.27 seconds
Started Jul 02 07:49:43 AM PDT 24
Finished Jul 02 07:49:59 AM PDT 24
Peak memory 217116 kb
Host smart-99f41d92-edf1-41b8-8e02-c5292df2f1ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724407689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2724407689
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1879694956
Short name T259
Test name
Test status
Simulation time 34719450159 ps
CPU time 270.94 seconds
Started Jul 02 07:49:43 AM PDT 24
Finished Jul 02 07:54:21 AM PDT 24
Peak memory 216744 kb
Host smart-5d6e1846-029a-4dad-ac4b-1b809355a219
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879694956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1879694956
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2392176819
Short name T299
Test name
Test status
Simulation time 25206020843 ps
CPU time 55.42 seconds
Started Jul 02 07:49:45 AM PDT 24
Finished Jul 02 07:50:51 AM PDT 24
Peak memory 219140 kb
Host smart-6b5cb088-f98d-4b26-991a-984e67bdfa02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392176819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2392176819
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3121193043
Short name T168
Test name
Test status
Simulation time 39389956349 ps
CPU time 29.06 seconds
Started Jul 02 07:49:46 AM PDT 24
Finished Jul 02 07:50:27 AM PDT 24
Peak memory 219292 kb
Host smart-afb46239-cf8f-43bc-91e1-92059cea5483
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3121193043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3121193043
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2125874980
Short name T273
Test name
Test status
Simulation time 1372437052 ps
CPU time 19.98 seconds
Started Jul 02 07:49:42 AM PDT 24
Finished Jul 02 07:50:06 AM PDT 24
Peak memory 216692 kb
Host smart-9214cfe3-60d4-4871-b62c-6895027c0ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125874980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2125874980
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2512908899
Short name T121
Test name
Test status
Simulation time 4575948168 ps
CPU time 69.34 seconds
Started Jul 02 07:49:39 AM PDT 24
Finished Jul 02 07:50:50 AM PDT 24
Peak memory 220164 kb
Host smart-0c69fe89-373a-44e4-85c6-e530e12bcfcf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512908899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2512908899
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2769618994
Short name T61
Test name
Test status
Simulation time 2895225818 ps
CPU time 24.74 seconds
Started Jul 02 07:49:47 AM PDT 24
Finished Jul 02 07:50:23 AM PDT 24
Peak memory 217232 kb
Host smart-c120eccc-a555-40e5-97b5-754ecd061d48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769618994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2769618994
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2335520896
Short name T237
Test name
Test status
Simulation time 30399052182 ps
CPU time 301.71 seconds
Started Jul 02 07:50:40 AM PDT 24
Finished Jul 02 07:55:45 AM PDT 24
Peak memory 234792 kb
Host smart-215bfaf1-6346-4d6d-9eb2-0999f32c8814
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335520896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2335520896
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1637239632
Short name T150
Test name
Test status
Simulation time 9243164079 ps
CPU time 33.98 seconds
Started Jul 02 07:49:43 AM PDT 24
Finished Jul 02 07:50:25 AM PDT 24
Peak memory 219264 kb
Host smart-5af697a4-479e-4a64-b7e2-ea895d82d715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637239632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1637239632
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3122688910
Short name T65
Test name
Test status
Simulation time 5709611286 ps
CPU time 17.78 seconds
Started Jul 02 07:49:41 AM PDT 24
Finished Jul 02 07:50:02 AM PDT 24
Peak memory 211920 kb
Host smart-c6407fca-15ec-4cf2-b729-04bf51d6f702
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3122688910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3122688910
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3607428982
Short name T131
Test name
Test status
Simulation time 1747333149 ps
CPU time 30.43 seconds
Started Jul 02 07:49:46 AM PDT 24
Finished Jul 02 07:50:26 AM PDT 24
Peak memory 216592 kb
Host smart-abeda94b-47e8-455d-9917-4f64497f5048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607428982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3607428982
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1272556623
Short name T192
Test name
Test status
Simulation time 1079911580 ps
CPU time 58.72 seconds
Started Jul 02 07:49:54 AM PDT 24
Finished Jul 02 07:51:02 AM PDT 24
Peak memory 219176 kb
Host smart-fd04a047-1553-4791-92d1-bf6f5f581627
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272556623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1272556623
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2578555827
Short name T285
Test name
Test status
Simulation time 1032921430 ps
CPU time 14.98 seconds
Started Jul 02 07:49:46 AM PDT 24
Finished Jul 02 07:50:13 AM PDT 24
Peak memory 217048 kb
Host smart-35220c20-6d06-4fb3-8006-445b7d2cc472
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578555827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2578555827
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1007396881
Short name T255
Test name
Test status
Simulation time 627128980465 ps
CPU time 623.85 seconds
Started Jul 02 07:49:44 AM PDT 24
Finished Jul 02 08:00:16 AM PDT 24
Peak memory 224384 kb
Host smart-eb130e4f-42bc-438b-aaa0-02a67409a504
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007396881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1007396881
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2038482186
Short name T178
Test name
Test status
Simulation time 16417745511 ps
CPU time 47.04 seconds
Started Jul 02 07:49:45 AM PDT 24
Finished Jul 02 07:50:42 AM PDT 24
Peak memory 219496 kb
Host smart-feebf28a-8cfc-4eff-8836-83eb33042abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038482186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2038482186
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.649488589
Short name T314
Test name
Test status
Simulation time 7559073898 ps
CPU time 30.67 seconds
Started Jul 02 07:49:46 AM PDT 24
Finished Jul 02 07:50:28 AM PDT 24
Peak memory 219292 kb
Host smart-d458333a-eef7-4477-b5f0-903d56afd2c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=649488589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.649488589
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3005389797
Short name T17
Test name
Test status
Simulation time 683959515 ps
CPU time 19.49 seconds
Started Jul 02 07:49:42 AM PDT 24
Finished Jul 02 07:50:08 AM PDT 24
Peak memory 217720 kb
Host smart-2a118e5c-5cde-4e0a-9568-2045a5c37aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005389797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3005389797
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2136769617
Short name T322
Test name
Test status
Simulation time 12802858461 ps
CPU time 123.75 seconds
Started Jul 02 07:49:41 AM PDT 24
Finished Jul 02 07:51:47 AM PDT 24
Peak memory 219264 kb
Host smart-c3a45814-391b-4686-96cd-ec63f2a2c663
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136769617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2136769617
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3860747935
Short name T49
Test name
Test status
Simulation time 89195985570 ps
CPU time 1600.72 seconds
Started Jul 02 07:49:45 AM PDT 24
Finished Jul 02 08:16:36 AM PDT 24
Peak memory 230876 kb
Host smart-9d65bce3-68b1-4d06-b0d0-205e6c9501e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860747935 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.3860747935
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1033102876
Short name T190
Test name
Test status
Simulation time 2475446593 ps
CPU time 23.37 seconds
Started Jul 02 07:49:50 AM PDT 24
Finished Jul 02 07:50:24 AM PDT 24
Peak memory 217212 kb
Host smart-6a34d605-96e6-4c3c-9430-7e91f29163db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033102876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1033102876
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2902098552
Short name T196
Test name
Test status
Simulation time 32982337621 ps
CPU time 355.64 seconds
Started Jul 02 07:49:54 AM PDT 24
Finished Jul 02 07:55:59 AM PDT 24
Peak memory 236508 kb
Host smart-e93ac3bb-7c14-4834-91a3-fb229ed2e39c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902098552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2902098552
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.4057566059
Short name T356
Test name
Test status
Simulation time 5805626132 ps
CPU time 37.86 seconds
Started Jul 02 07:49:53 AM PDT 24
Finished Jul 02 07:50:40 AM PDT 24
Peak memory 219196 kb
Host smart-dac3ef20-3525-4edf-9613-5cf9fae67573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057566059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.4057566059
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.4252488539
Short name T335
Test name
Test status
Simulation time 4108003152 ps
CPU time 32.67 seconds
Started Jul 02 07:49:43 AM PDT 24
Finished Jul 02 07:50:22 AM PDT 24
Peak memory 211512 kb
Host smart-e2025db2-9152-402b-8458-a970ed0ea3b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4252488539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.4252488539
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.1335145265
Short name T222
Test name
Test status
Simulation time 17069394596 ps
CPU time 50.41 seconds
Started Jul 02 07:49:44 AM PDT 24
Finished Jul 02 07:50:43 AM PDT 24
Peak memory 217360 kb
Host smart-c92d21c3-da2f-402e-835b-cba4c64cedd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335145265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1335145265
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.852348404
Short name T166
Test name
Test status
Simulation time 2235694599 ps
CPU time 30.47 seconds
Started Jul 02 07:49:53 AM PDT 24
Finished Jul 02 07:50:33 AM PDT 24
Peak memory 219276 kb
Host smart-1bfd49ea-8ee7-46ec-9428-0c94a5de2786
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852348404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.852348404
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3595243364
Short name T276
Test name
Test status
Simulation time 15355174886 ps
CPU time 30.63 seconds
Started Jul 02 07:49:50 AM PDT 24
Finished Jul 02 07:50:31 AM PDT 24
Peak memory 217404 kb
Host smart-85cb677a-c77b-4d7f-af8d-7d5c6762e37c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595243364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3595243364
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2748467137
Short name T19
Test name
Test status
Simulation time 594393322221 ps
CPU time 415.45 seconds
Started Jul 02 07:49:44 AM PDT 24
Finished Jul 02 07:56:49 AM PDT 24
Peak memory 235068 kb
Host smart-c39669a9-048f-436d-be16-7b7cedeb6745
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748467137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2748467137
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2962779248
Short name T5
Test name
Test status
Simulation time 18969415572 ps
CPU time 57.14 seconds
Started Jul 02 07:49:43 AM PDT 24
Finished Jul 02 07:50:47 AM PDT 24
Peak memory 219236 kb
Host smart-01a9e12d-a84b-47ce-a351-756965f61abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962779248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2962779248
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1511860639
Short name T337
Test name
Test status
Simulation time 186448709 ps
CPU time 10.42 seconds
Started Jul 02 07:49:39 AM PDT 24
Finished Jul 02 07:49:52 AM PDT 24
Peak memory 219188 kb
Host smart-aa152d91-4a05-4ccb-9d39-26fa5ff002c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1511860639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1511860639
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1030035736
Short name T334
Test name
Test status
Simulation time 5589479068 ps
CPU time 62.98 seconds
Started Jul 02 07:49:41 AM PDT 24
Finished Jul 02 07:50:46 AM PDT 24
Peak memory 219240 kb
Host smart-e78c7223-c279-4d51-94ef-efa45e5d355f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030035736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1030035736
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.988612879
Short name T53
Test name
Test status
Simulation time 5425427394 ps
CPU time 215.03 seconds
Started Jul 02 07:49:44 AM PDT 24
Finished Jul 02 07:53:29 AM PDT 24
Peak memory 226464 kb
Host smart-51a360e1-71a3-4f05-8d06-27c8f560c507
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988612879 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.988612879
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2418313293
Short name T309
Test name
Test status
Simulation time 174375983 ps
CPU time 8.48 seconds
Started Jul 02 07:49:23 AM PDT 24
Finished Jul 02 07:49:32 AM PDT 24
Peak memory 217436 kb
Host smart-56c052f8-ef33-4e3f-8ac8-3bbf13c5d126
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418313293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2418313293
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2080970350
Short name T329
Test name
Test status
Simulation time 225145696315 ps
CPU time 775.68 seconds
Started Jul 02 07:49:15 AM PDT 24
Finished Jul 02 08:02:16 AM PDT 24
Peak memory 218216 kb
Host smart-cbdb395c-1331-4fb7-8414-4adf53212da6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080970350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2080970350
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.4018777695
Short name T297
Test name
Test status
Simulation time 1320609951 ps
CPU time 18.79 seconds
Started Jul 02 07:49:33 AM PDT 24
Finished Jul 02 07:49:53 AM PDT 24
Peak memory 219204 kb
Host smart-47778b00-5720-473d-bce4-e348ab007461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018777695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.4018777695
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3924363934
Short name T117
Test name
Test status
Simulation time 4007107785 ps
CPU time 28.71 seconds
Started Jul 02 07:49:03 AM PDT 24
Finished Jul 02 07:49:34 AM PDT 24
Peak memory 219260 kb
Host smart-e5315cdf-9e50-4326-be64-2bdbbb5c6359
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3924363934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3924363934
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1737278607
Short name T24
Test name
Test status
Simulation time 1204849808 ps
CPU time 231.95 seconds
Started Jul 02 07:49:17 AM PDT 24
Finished Jul 02 07:53:10 AM PDT 24
Peak memory 235856 kb
Host smart-2b5682a0-59f5-4f67-9b2f-131772041402
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737278607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1737278607
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3137001483
Short name T331
Test name
Test status
Simulation time 10205093839 ps
CPU time 54.88 seconds
Started Jul 02 07:49:02 AM PDT 24
Finished Jul 02 07:49:59 AM PDT 24
Peak memory 216724 kb
Host smart-1d8e3df5-0def-42a5-806c-956120f2857b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137001483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3137001483
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2691946596
Short name T211
Test name
Test status
Simulation time 8093248475 ps
CPU time 86.3 seconds
Started Jul 02 07:49:04 AM PDT 24
Finished Jul 02 07:50:32 AM PDT 24
Peak memory 221600 kb
Host smart-ef8347bf-52a5-4be0-a96c-407b1c31d5e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691946596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2691946596
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3982592497
Short name T183
Test name
Test status
Simulation time 16363245137 ps
CPU time 31.89 seconds
Started Jul 02 07:49:42 AM PDT 24
Finished Jul 02 07:50:20 AM PDT 24
Peak memory 213180 kb
Host smart-25354856-173f-4cda-ba1c-29adff0d944a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982592497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3982592497
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4158198516
Short name T35
Test name
Test status
Simulation time 90956048161 ps
CPU time 320.48 seconds
Started Jul 02 07:49:37 AM PDT 24
Finished Jul 02 07:54:58 AM PDT 24
Peak memory 235304 kb
Host smart-458862dd-7e61-4034-bad8-cf27331af721
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158198516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.4158198516
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.4103799593
Short name T120
Test name
Test status
Simulation time 1566579602 ps
CPU time 28.41 seconds
Started Jul 02 07:49:47 AM PDT 24
Finished Jul 02 07:50:26 AM PDT 24
Peak memory 219204 kb
Host smart-66ed62eb-e846-407a-a79f-4d2a4cfe4cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103799593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.4103799593
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.98400104
Short name T11
Test name
Test status
Simulation time 696147685 ps
CPU time 10.13 seconds
Started Jul 02 07:49:44 AM PDT 24
Finished Jul 02 07:50:02 AM PDT 24
Peak memory 219316 kb
Host smart-74bd1e09-672b-471c-a26a-ddc9fc98c1f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=98400104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.98400104
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1699056886
Short name T304
Test name
Test status
Simulation time 6524590143 ps
CPU time 71.33 seconds
Started Jul 02 07:49:46 AM PDT 24
Finished Jul 02 07:51:09 AM PDT 24
Peak memory 217644 kb
Host smart-23b61171-14bf-4aa1-bd52-f48783bb1e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699056886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1699056886
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2030916195
Short name T199
Test name
Test status
Simulation time 38932243152 ps
CPU time 66.23 seconds
Started Jul 02 07:49:44 AM PDT 24
Finished Jul 02 07:50:59 AM PDT 24
Peak memory 219344 kb
Host smart-9b570979-f04e-41a0-9011-a995570f9edb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030916195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2030916195
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3325134855
Short name T145
Test name
Test status
Simulation time 3701113170 ps
CPU time 31.07 seconds
Started Jul 02 07:49:49 AM PDT 24
Finished Jul 02 07:50:30 AM PDT 24
Peak memory 217048 kb
Host smart-958bab36-2e20-4c3d-9424-81ef627a7afc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325134855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3325134855
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3784359352
Short name T213
Test name
Test status
Simulation time 7325119480 ps
CPU time 249.54 seconds
Started Jul 02 07:49:47 AM PDT 24
Finished Jul 02 07:54:07 AM PDT 24
Peak memory 237992 kb
Host smart-cd671796-721d-411e-b279-6c7e9354b7b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784359352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3784359352
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.486759147
Short name T146
Test name
Test status
Simulation time 25581702782 ps
CPU time 62.74 seconds
Started Jul 02 07:49:54 AM PDT 24
Finished Jul 02 07:51:06 AM PDT 24
Peak memory 219056 kb
Host smart-9936bcaa-0d75-4ac4-8970-19e5d7623250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486759147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.486759147
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3779059762
Short name T21
Test name
Test status
Simulation time 1294770844 ps
CPU time 17.83 seconds
Started Jul 02 07:49:49 AM PDT 24
Finished Jul 02 07:50:18 AM PDT 24
Peak memory 219224 kb
Host smart-0a56c39a-1a2d-40cb-88cc-b4a3c4e01ba3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3779059762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3779059762
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3107099656
Short name T280
Test name
Test status
Simulation time 4793067606 ps
CPU time 53.97 seconds
Started Jul 02 07:49:50 AM PDT 24
Finished Jul 02 07:50:54 AM PDT 24
Peak memory 217860 kb
Host smart-65674b2e-c384-4549-838d-ce3e59385bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107099656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3107099656
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.229394961
Short name T154
Test name
Test status
Simulation time 16589338219 ps
CPU time 31.51 seconds
Started Jul 02 07:49:44 AM PDT 24
Finished Jul 02 07:50:25 AM PDT 24
Peak memory 219232 kb
Host smart-f3ef64c8-bfb6-4ffe-b39e-0119d3bf2b9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229394961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.229394961
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.149879977
Short name T177
Test name
Test status
Simulation time 2674781088 ps
CPU time 16.35 seconds
Started Jul 02 07:49:47 AM PDT 24
Finished Jul 02 07:50:14 AM PDT 24
Peak memory 213216 kb
Host smart-ce4c361a-67a3-45c5-8170-ffff2d819794
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149879977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.149879977
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.4026201847
Short name T219
Test name
Test status
Simulation time 145507203052 ps
CPU time 424.02 seconds
Started Jul 02 07:49:52 AM PDT 24
Finished Jul 02 07:57:06 AM PDT 24
Peak memory 233528 kb
Host smart-48056a2b-3a94-4f14-bb0d-33779ede779b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026201847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.4026201847
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3815550272
Short name T253
Test name
Test status
Simulation time 6872274011 ps
CPU time 40.22 seconds
Started Jul 02 07:49:45 AM PDT 24
Finished Jul 02 07:50:35 AM PDT 24
Peak memory 218768 kb
Host smart-4aa31152-2128-4d20-ac7a-420205c6687f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815550272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3815550272
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.957523697
Short name T188
Test name
Test status
Simulation time 181159460 ps
CPU time 10.25 seconds
Started Jul 02 07:49:44 AM PDT 24
Finished Jul 02 07:50:02 AM PDT 24
Peak memory 219204 kb
Host smart-89eab047-cc7c-4f34-9b7c-e2fa92f10ad7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=957523697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.957523697
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1198523462
Short name T123
Test name
Test status
Simulation time 1490745624 ps
CPU time 19.47 seconds
Started Jul 02 07:49:46 AM PDT 24
Finished Jul 02 07:50:17 AM PDT 24
Peak memory 216740 kb
Host smart-b611000f-05b0-4fd9-9f8b-3b4912c7f54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198523462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1198523462
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1681772205
Short name T319
Test name
Test status
Simulation time 375046682 ps
CPU time 28.35 seconds
Started Jul 02 07:49:40 AM PDT 24
Finished Jul 02 07:50:11 AM PDT 24
Peak memory 217588 kb
Host smart-7b0fc1c6-7d1e-4b49-a549-b54baaa50560
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681772205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1681772205
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2560103650
Short name T216
Test name
Test status
Simulation time 2383015241 ps
CPU time 21.75 seconds
Started Jul 02 07:49:54 AM PDT 24
Finished Jul 02 07:50:25 AM PDT 24
Peak memory 216980 kb
Host smart-d5d4a796-62cb-4b06-b8a0-4d5c967196d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560103650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2560103650
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1905758014
Short name T147
Test name
Test status
Simulation time 369747209375 ps
CPU time 312.49 seconds
Started Jul 02 07:49:48 AM PDT 24
Finished Jul 02 07:55:11 AM PDT 24
Peak memory 233640 kb
Host smart-c82b85a9-4d6d-4e42-b59d-0e210d869627
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905758014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1905758014
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.23587906
Short name T125
Test name
Test status
Simulation time 1965994895 ps
CPU time 26.7 seconds
Started Jul 02 07:49:39 AM PDT 24
Finished Jul 02 07:50:08 AM PDT 24
Peak memory 219148 kb
Host smart-e9ba732a-b69a-4d1c-955e-581f904deb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23587906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.23587906
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2566659575
Short name T184
Test name
Test status
Simulation time 178476029 ps
CPU time 10.61 seconds
Started Jul 02 07:49:47 AM PDT 24
Finished Jul 02 07:50:08 AM PDT 24
Peak memory 219060 kb
Host smart-6f3ac860-c31c-42c3-a802-5935faaac75f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2566659575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2566659575
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.4237321968
Short name T187
Test name
Test status
Simulation time 6361501348 ps
CPU time 54.79 seconds
Started Jul 02 07:49:42 AM PDT 24
Finished Jul 02 07:50:42 AM PDT 24
Peak memory 218036 kb
Host smart-7d4a9329-0492-488e-a38d-033842e9be0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237321968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.4237321968
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1763623045
Short name T269
Test name
Test status
Simulation time 5242189691 ps
CPU time 16.83 seconds
Started Jul 02 07:49:50 AM PDT 24
Finished Jul 02 07:50:17 AM PDT 24
Peak memory 217376 kb
Host smart-307ce9d2-4002-46ad-b4da-a1ebae8af16f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763623045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1763623045
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3615571090
Short name T250
Test name
Test status
Simulation time 115819924213 ps
CPU time 325.86 seconds
Started Jul 02 07:49:50 AM PDT 24
Finished Jul 02 07:55:26 AM PDT 24
Peak memory 233720 kb
Host smart-139aec20-ebc1-47ff-8fdd-7cf4b5c2e29f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615571090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3615571090
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.517508977
Short name T251
Test name
Test status
Simulation time 5355358252 ps
CPU time 35.41 seconds
Started Jul 02 07:49:46 AM PDT 24
Finished Jul 02 07:50:33 AM PDT 24
Peak memory 219288 kb
Host smart-5e505228-b87f-49f0-8cb9-10f8df5a3d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517508977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.517508977
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2933108397
Short name T170
Test name
Test status
Simulation time 4354185926 ps
CPU time 28.33 seconds
Started Jul 02 07:49:46 AM PDT 24
Finished Jul 02 07:50:26 AM PDT 24
Peak memory 219364 kb
Host smart-19780de0-16db-40cf-9c94-06f9026c1c45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2933108397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2933108397
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.321881149
Short name T339
Test name
Test status
Simulation time 5611355546 ps
CPU time 40.32 seconds
Started Jul 02 07:49:43 AM PDT 24
Finished Jul 02 07:50:30 AM PDT 24
Peak memory 216660 kb
Host smart-69455267-c706-4606-881a-98417eacb0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321881149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.321881149
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2079807924
Short name T233
Test name
Test status
Simulation time 1492899054 ps
CPU time 28.61 seconds
Started Jul 02 07:49:46 AM PDT 24
Finished Jul 02 07:50:26 AM PDT 24
Peak memory 219256 kb
Host smart-00b7f8d0-0695-427d-89da-86dd4fcfa10b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079807924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2079807924
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.153210860
Short name T212
Test name
Test status
Simulation time 2285299512 ps
CPU time 16.31 seconds
Started Jul 02 07:49:50 AM PDT 24
Finished Jul 02 07:50:17 AM PDT 24
Peak memory 217540 kb
Host smart-93c99e8b-e8b1-497e-802d-daad8882efa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153210860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.153210860
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2715483138
Short name T290
Test name
Test status
Simulation time 35115272455 ps
CPU time 61.44 seconds
Started Jul 02 07:49:43 AM PDT 24
Finished Jul 02 07:50:53 AM PDT 24
Peak memory 218452 kb
Host smart-bc669fb3-6a52-4706-8f92-94d401bbca76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715483138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2715483138
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.42058761
Short name T227
Test name
Test status
Simulation time 28325511708 ps
CPU time 25.55 seconds
Started Jul 02 07:49:49 AM PDT 24
Finished Jul 02 07:50:26 AM PDT 24
Peak memory 211824 kb
Host smart-d2ed3821-4aa8-4146-a34e-b0b41b3afa49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=42058761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.42058761
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2147653325
Short name T207
Test name
Test status
Simulation time 5980469930 ps
CPU time 38.11 seconds
Started Jul 02 07:49:53 AM PDT 24
Finished Jul 02 07:50:41 AM PDT 24
Peak memory 218012 kb
Host smart-15eb10e8-2341-4620-b356-de39314ea610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147653325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2147653325
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2531698453
Short name T143
Test name
Test status
Simulation time 5387338475 ps
CPU time 20.35 seconds
Started Jul 02 07:49:48 AM PDT 24
Finished Jul 02 07:50:19 AM PDT 24
Peak memory 214564 kb
Host smart-a0dd4b65-780c-483a-bff1-933ed4ff9c06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531698453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2531698453
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2452632653
Short name T139
Test name
Test status
Simulation time 5130421836 ps
CPU time 31.88 seconds
Started Jul 02 07:49:47 AM PDT 24
Finished Jul 02 07:50:30 AM PDT 24
Peak memory 217516 kb
Host smart-af7bf2a6-499b-44a4-89c5-a3f832a68863
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452632653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2452632653
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1824608389
Short name T326
Test name
Test status
Simulation time 3740167901 ps
CPU time 214.62 seconds
Started Jul 02 07:49:43 AM PDT 24
Finished Jul 02 07:53:24 AM PDT 24
Peak memory 228256 kb
Host smart-97a45bac-3c15-4098-8989-fcd6a3c875eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824608389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1824608389
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3583354469
Short name T200
Test name
Test status
Simulation time 26018541955 ps
CPU time 54.05 seconds
Started Jul 02 07:49:51 AM PDT 24
Finished Jul 02 07:50:55 AM PDT 24
Peak memory 219272 kb
Host smart-6866675b-e640-4010-bc87-5ce10779a502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583354469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3583354469
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2413184270
Short name T198
Test name
Test status
Simulation time 11733704878 ps
CPU time 27.47 seconds
Started Jul 02 07:49:52 AM PDT 24
Finished Jul 02 07:50:29 AM PDT 24
Peak memory 211980 kb
Host smart-049cb489-608c-477c-94ee-9881f99b7bfe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2413184270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2413184270
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1257296843
Short name T79
Test name
Test status
Simulation time 68228049400 ps
CPU time 86.52 seconds
Started Jul 02 07:49:48 AM PDT 24
Finished Jul 02 07:51:25 AM PDT 24
Peak memory 216228 kb
Host smart-d975b402-eae1-4bd5-8741-70d28b93060b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257296843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1257296843
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.4233684071
Short name T214
Test name
Test status
Simulation time 22398271067 ps
CPU time 54.35 seconds
Started Jul 02 07:50:02 AM PDT 24
Finished Jul 02 07:51:01 AM PDT 24
Peak memory 218068 kb
Host smart-368ca7bb-eea1-404a-ae97-e10ee46eb8c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233684071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.4233684071
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3546172625
Short name T246
Test name
Test status
Simulation time 40077375613 ps
CPU time 28.93 seconds
Started Jul 02 07:49:46 AM PDT 24
Finished Jul 02 07:50:26 AM PDT 24
Peak memory 217392 kb
Host smart-62fea304-a46c-4eba-b76d-b7590d35021a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546172625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3546172625
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.704468676
Short name T39
Test name
Test status
Simulation time 12486273592 ps
CPU time 220.08 seconds
Started Jul 02 07:49:47 AM PDT 24
Finished Jul 02 07:53:38 AM PDT 24
Peak memory 218300 kb
Host smart-35820273-01a6-4d66-bfd7-9d81f830cd9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704468676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.704468676
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2229241214
Short name T115
Test name
Test status
Simulation time 2727185211 ps
CPU time 34 seconds
Started Jul 02 07:49:59 AM PDT 24
Finished Jul 02 07:50:39 AM PDT 24
Peak memory 219308 kb
Host smart-877de34b-60be-4368-bdc4-341c35730d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229241214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2229241214
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3816211736
Short name T243
Test name
Test status
Simulation time 3000384526 ps
CPU time 14.76 seconds
Started Jul 02 07:50:01 AM PDT 24
Finished Jul 02 07:50:21 AM PDT 24
Peak memory 219120 kb
Host smart-2a94cfa4-ae80-4ebe-b721-34c05209e9e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3816211736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3816211736
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3583315761
Short name T352
Test name
Test status
Simulation time 3620937033 ps
CPU time 48.64 seconds
Started Jul 02 07:50:02 AM PDT 24
Finished Jul 02 07:50:55 AM PDT 24
Peak memory 216340 kb
Host smart-fb5b4525-c42f-4865-bf33-8f226474ed50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583315761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3583315761
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2447546995
Short name T295
Test name
Test status
Simulation time 10590921801 ps
CPU time 104.11 seconds
Started Jul 02 07:49:47 AM PDT 24
Finished Jul 02 07:51:43 AM PDT 24
Peak memory 217616 kb
Host smart-2c4e5cc4-4fcf-4e05-9fe3-63d497e947f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447546995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2447546995
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2228972463
Short name T189
Test name
Test status
Simulation time 2737177666 ps
CPU time 13.13 seconds
Started Jul 02 07:49:48 AM PDT 24
Finished Jul 02 07:50:12 AM PDT 24
Peak memory 217060 kb
Host smart-63b2dd15-cd21-4414-98dc-562259bee651
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228972463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2228972463
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.786510544
Short name T48
Test name
Test status
Simulation time 68591058608 ps
CPU time 199.48 seconds
Started Jul 02 07:49:49 AM PDT 24
Finished Jul 02 07:53:20 AM PDT 24
Peak memory 219428 kb
Host smart-954fb290-937a-47d3-be9b-9448412014df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786510544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.786510544
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1648901330
Short name T274
Test name
Test status
Simulation time 4780087219 ps
CPU time 46.9 seconds
Started Jul 02 07:50:08 AM PDT 24
Finished Jul 02 07:50:57 AM PDT 24
Peak memory 219248 kb
Host smart-b06328fd-029d-4e3a-8447-b38bb722b3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648901330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1648901330
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3401742639
Short name T64
Test name
Test status
Simulation time 15172104360 ps
CPU time 31.8 seconds
Started Jul 02 07:50:04 AM PDT 24
Finished Jul 02 07:50:40 AM PDT 24
Peak memory 219224 kb
Host smart-12abccbc-296d-4a2c-988b-b0720871db00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3401742639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3401742639
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2222283233
Short name T191
Test name
Test status
Simulation time 1408603607 ps
CPU time 20.25 seconds
Started Jul 02 07:49:50 AM PDT 24
Finished Jul 02 07:50:21 AM PDT 24
Peak memory 217252 kb
Host smart-34b9ba20-4a1a-401e-b5ed-89e361903c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222283233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2222283233
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2289410611
Short name T180
Test name
Test status
Simulation time 133710499858 ps
CPU time 180.85 seconds
Started Jul 02 07:50:02 AM PDT 24
Finished Jul 02 07:53:07 AM PDT 24
Peak memory 220468 kb
Host smart-5d56027c-20e0-492c-84b4-1c2578a3f4c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289410611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2289410611
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2379024486
Short name T318
Test name
Test status
Simulation time 3285795639 ps
CPU time 28.25 seconds
Started Jul 02 07:49:56 AM PDT 24
Finished Jul 02 07:50:33 AM PDT 24
Peak memory 217092 kb
Host smart-42fbe3a5-008c-4533-9f3a-8ff3a2489c05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379024486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2379024486
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.4286057544
Short name T132
Test name
Test status
Simulation time 521057525396 ps
CPU time 647.09 seconds
Started Jul 02 07:50:09 AM PDT 24
Finished Jul 02 08:00:58 AM PDT 24
Peak memory 240588 kb
Host smart-fd2735e2-79f5-4561-bd2b-877bc8752f0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286057544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.4286057544
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.743310440
Short name T141
Test name
Test status
Simulation time 12367203486 ps
CPU time 56.39 seconds
Started Jul 02 07:49:48 AM PDT 24
Finished Jul 02 07:50:55 AM PDT 24
Peak memory 219084 kb
Host smart-05567db7-278c-46c1-ab7c-8ef5192bfc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743310440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.743310440
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2267231676
Short name T333
Test name
Test status
Simulation time 12939846519 ps
CPU time 31.07 seconds
Started Jul 02 07:49:49 AM PDT 24
Finished Jul 02 07:50:30 AM PDT 24
Peak memory 211944 kb
Host smart-8ce9f2c4-bac3-4adf-a064-96571f901ed7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2267231676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2267231676
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1384155006
Short name T282
Test name
Test status
Simulation time 42443546630 ps
CPU time 38.32 seconds
Started Jul 02 07:49:52 AM PDT 24
Finished Jul 02 07:50:40 AM PDT 24
Peak memory 216840 kb
Host smart-b951b1c8-59b3-4b16-9882-b1089d1126bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384155006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1384155006
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1090331101
Short name T286
Test name
Test status
Simulation time 7929185637 ps
CPU time 56.85 seconds
Started Jul 02 07:49:54 AM PDT 24
Finished Jul 02 07:51:00 AM PDT 24
Peak memory 219364 kb
Host smart-a104f944-571a-4c2c-afcb-c13724f239ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090331101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1090331101
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.45912462
Short name T306
Test name
Test status
Simulation time 6824835164 ps
CPU time 19.05 seconds
Started Jul 02 07:49:12 AM PDT 24
Finished Jul 02 07:49:32 AM PDT 24
Peak memory 217384 kb
Host smart-1e178287-3ce5-49fd-b043-e27f6172b0c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45912462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.45912462
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1106059367
Short name T332
Test name
Test status
Simulation time 189419421394 ps
CPU time 308.04 seconds
Started Jul 02 07:49:18 AM PDT 24
Finished Jul 02 07:54:27 AM PDT 24
Peak memory 233828 kb
Host smart-a2403fb9-ac3e-41a8-8913-6b320a96e9bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106059367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1106059367
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3177922395
Short name T262
Test name
Test status
Simulation time 21783856958 ps
CPU time 33.09 seconds
Started Jul 02 07:49:19 AM PDT 24
Finished Jul 02 07:49:53 AM PDT 24
Peak memory 219288 kb
Host smart-d69e680c-eb10-4eb0-ad41-e684f11da33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177922395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3177922395
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3889345154
Short name T126
Test name
Test status
Simulation time 16416259907 ps
CPU time 32.14 seconds
Started Jul 02 07:49:29 AM PDT 24
Finished Jul 02 07:50:03 AM PDT 24
Peak memory 211780 kb
Host smart-e81880a1-54d8-43dd-9b1b-04aef7754251
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3889345154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3889345154
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.376908449
Short name T324
Test name
Test status
Simulation time 2094916074 ps
CPU time 23.52 seconds
Started Jul 02 07:49:19 AM PDT 24
Finished Jul 02 07:49:43 AM PDT 24
Peak memory 215564 kb
Host smart-187f0610-9e82-4741-9b61-80c2cfbb9c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376908449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.376908449
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3935276093
Short name T153
Test name
Test status
Simulation time 45342571787 ps
CPU time 75.68 seconds
Started Jul 02 07:49:19 AM PDT 24
Finished Jul 02 07:50:36 AM PDT 24
Peak memory 219984 kb
Host smart-11e8259b-20ed-415a-a39b-8abbc6c3fed8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935276093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3935276093
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.926419582
Short name T14
Test name
Test status
Simulation time 73456286871 ps
CPU time 1927.39 seconds
Started Jul 02 07:49:19 AM PDT 24
Finished Jul 02 08:21:28 AM PDT 24
Peak memory 235704 kb
Host smart-ef8f6847-9298-4318-b633-f9533693e64d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926419582 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.926419582
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.311910351
Short name T128
Test name
Test status
Simulation time 9811603149 ps
CPU time 21.24 seconds
Started Jul 02 07:49:18 AM PDT 24
Finished Jul 02 07:49:40 AM PDT 24
Peak memory 217492 kb
Host smart-7c466178-295c-4e36-990f-4525116b73d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311910351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.311910351
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1124831252
Short name T20
Test name
Test status
Simulation time 181874685444 ps
CPU time 452.59 seconds
Started Jul 02 07:49:28 AM PDT 24
Finished Jul 02 07:57:02 AM PDT 24
Peak memory 241904 kb
Host smart-1732f0d3-59d6-499f-a52b-cbd5dd72fb34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124831252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1124831252
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2558879667
Short name T31
Test name
Test status
Simulation time 332208812 ps
CPU time 19.29 seconds
Started Jul 02 07:49:10 AM PDT 24
Finished Jul 02 07:49:30 AM PDT 24
Peak memory 219232 kb
Host smart-da23a156-c09a-4744-8eaf-8fe65fe97d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558879667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2558879667
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3794356995
Short name T240
Test name
Test status
Simulation time 9204168503 ps
CPU time 24.19 seconds
Started Jul 02 07:49:13 AM PDT 24
Finished Jul 02 07:49:38 AM PDT 24
Peak memory 219284 kb
Host smart-c84d054a-0097-405b-9e42-9f2421c93337
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3794356995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3794356995
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2613128804
Short name T78
Test name
Test status
Simulation time 23879111628 ps
CPU time 59.67 seconds
Started Jul 02 07:49:20 AM PDT 24
Finished Jul 02 07:50:21 AM PDT 24
Peak memory 216876 kb
Host smart-c61c7e16-b80b-4979-9f7c-450b26475dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613128804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2613128804
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.30228932
Short name T159
Test name
Test status
Simulation time 14649980927 ps
CPU time 130.49 seconds
Started Jul 02 07:49:40 AM PDT 24
Finished Jul 02 07:51:52 AM PDT 24
Peak memory 219256 kb
Host smart-9c52597d-4a65-4e4d-a722-783e20bf295b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30228932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 6.rom_ctrl_stress_all.30228932
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2485486169
Short name T307
Test name
Test status
Simulation time 169222950 ps
CPU time 8.64 seconds
Started Jul 02 07:49:08 AM PDT 24
Finished Jul 02 07:49:18 AM PDT 24
Peak memory 218192 kb
Host smart-52f30c1a-cc32-432b-ba1a-cd72f63f1bfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485486169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2485486169
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3330267745
Short name T293
Test name
Test status
Simulation time 66364451935 ps
CPU time 368.85 seconds
Started Jul 02 07:49:20 AM PDT 24
Finished Jul 02 07:55:30 AM PDT 24
Peak memory 237872 kb
Host smart-57e656d7-516d-4a05-b1be-ab9c6c8c0e17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330267745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3330267745
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3537825690
Short name T41
Test name
Test status
Simulation time 675691737 ps
CPU time 20.05 seconds
Started Jul 02 07:49:21 AM PDT 24
Finished Jul 02 07:49:42 AM PDT 24
Peak memory 219236 kb
Host smart-edf3deab-ab22-43c5-9254-94640c04ca8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537825690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3537825690
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3925876362
Short name T172
Test name
Test status
Simulation time 7312554426 ps
CPU time 30.52 seconds
Started Jul 02 07:49:15 AM PDT 24
Finished Jul 02 07:49:46 AM PDT 24
Peak memory 211816 kb
Host smart-455e2b51-9a55-4fce-bc16-192717c9bf38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3925876362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3925876362
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.4176634424
Short name T76
Test name
Test status
Simulation time 8578112952 ps
CPU time 36.91 seconds
Started Jul 02 07:49:11 AM PDT 24
Finished Jul 02 07:49:49 AM PDT 24
Peak memory 217420 kb
Host smart-c559bf73-480d-4742-b15c-9cdd15169bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176634424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.4176634424
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2879511752
Short name T157
Test name
Test status
Simulation time 54264152605 ps
CPU time 151.06 seconds
Started Jul 02 07:49:36 AM PDT 24
Finished Jul 02 07:52:09 AM PDT 24
Peak memory 227476 kb
Host smart-27bc4da5-5c4b-44ca-a664-ad54710b4da5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879511752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2879511752
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2486336215
Short name T315
Test name
Test status
Simulation time 46915285013 ps
CPU time 1829.71 seconds
Started Jul 02 07:49:11 AM PDT 24
Finished Jul 02 08:19:42 AM PDT 24
Peak memory 238208 kb
Host smart-31f5ae4a-fa91-48bf-8c39-25d486c9dfd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486336215 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.2486336215
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1071632247
Short name T238
Test name
Test status
Simulation time 5983731779 ps
CPU time 13.22 seconds
Started Jul 02 07:49:29 AM PDT 24
Finished Jul 02 07:49:44 AM PDT 24
Peak memory 217288 kb
Host smart-6c6bd6f3-5c73-4484-91f1-95ee8a7912a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071632247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1071632247
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1667941552
Short name T162
Test name
Test status
Simulation time 54014903663 ps
CPU time 560.64 seconds
Started Jul 02 07:49:12 AM PDT 24
Finished Jul 02 07:58:33 AM PDT 24
Peak memory 236664 kb
Host smart-f74eebcc-fbc8-4bc6-a94d-0e4936bdb60b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667941552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1667941552
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1617612903
Short name T204
Test name
Test status
Simulation time 5495739400 ps
CPU time 50.69 seconds
Started Jul 02 07:49:22 AM PDT 24
Finished Jul 02 07:50:14 AM PDT 24
Peak memory 219316 kb
Host smart-8d25048f-e668-4fc9-9b98-d98e8a19be93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617612903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1617612903
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3609207572
Short name T300
Test name
Test status
Simulation time 723213477 ps
CPU time 10.61 seconds
Started Jul 02 07:49:35 AM PDT 24
Finished Jul 02 07:49:47 AM PDT 24
Peak memory 219188 kb
Host smart-cbc7ea50-7f35-4ad2-ace0-cce4d6d4a886
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3609207572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3609207572
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1015569003
Short name T164
Test name
Test status
Simulation time 359676052 ps
CPU time 20.07 seconds
Started Jul 02 07:49:17 AM PDT 24
Finished Jul 02 07:49:38 AM PDT 24
Peak memory 216424 kb
Host smart-31c5372e-665c-474c-9955-3baec3c3f66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015569003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1015569003
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.305103622
Short name T308
Test name
Test status
Simulation time 71905338410 ps
CPU time 210.18 seconds
Started Jul 02 07:49:17 AM PDT 24
Finished Jul 02 07:52:48 AM PDT 24
Peak memory 220360 kb
Host smart-650719db-49a3-4174-939a-dbf6f3a39ffd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305103622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.305103622
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3222940317
Short name T266
Test name
Test status
Simulation time 14027194105 ps
CPU time 27.96 seconds
Started Jul 02 07:49:35 AM PDT 24
Finished Jul 02 07:50:04 AM PDT 24
Peak memory 217508 kb
Host smart-05945857-2157-4899-ab12-f644030a4709
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222940317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3222940317
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3822026224
Short name T47
Test name
Test status
Simulation time 18692563298 ps
CPU time 374.63 seconds
Started Jul 02 07:49:39 AM PDT 24
Finished Jul 02 07:55:55 AM PDT 24
Peak memory 234928 kb
Host smart-4818a22c-637c-4012-bce5-63870ddcc2c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822026224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3822026224
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1789637408
Short name T245
Test name
Test status
Simulation time 4090897447 ps
CPU time 45.19 seconds
Started Jul 02 07:49:25 AM PDT 24
Finished Jul 02 07:50:11 AM PDT 24
Peak memory 218956 kb
Host smart-471d5fb4-17ea-47ca-a69e-a5935c914c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789637408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1789637408
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1938438666
Short name T224
Test name
Test status
Simulation time 8283399149 ps
CPU time 33.69 seconds
Started Jul 02 07:49:19 AM PDT 24
Finished Jul 02 07:49:54 AM PDT 24
Peak memory 211612 kb
Host smart-f30012bd-85f7-4470-b1ee-81e3d8705cfc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1938438666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1938438666
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1608729060
Short name T303
Test name
Test status
Simulation time 429137714 ps
CPU time 17.92 seconds
Started Jul 02 07:49:25 AM PDT 24
Finished Jul 02 07:49:44 AM PDT 24
Peak memory 219296 kb
Host smart-c25b0a2b-4b7c-426c-a8cc-43b6cb1f97ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608729060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1608729060
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.793403201
Short name T2
Test name
Test status
Simulation time 93154811132 ps
CPU time 851.52 seconds
Started Jul 02 07:49:24 AM PDT 24
Finished Jul 02 08:03:37 AM PDT 24
Peak memory 235684 kb
Host smart-be7ecdbf-7007-4c09-b6a1-7aadd030ca55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793403201 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.793403201
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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