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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.24 96.89 91.99 97.68 100.00 98.28 97.45 98.37


Total test records in report: 461
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T300 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.300067413 Jul 03 04:23:31 PM PDT 24 Jul 03 04:23:48 PM PDT 24 4755573823 ps
T301 /workspace/coverage/default/17.rom_ctrl_alert_test.1639916318 Jul 03 04:21:56 PM PDT 24 Jul 03 04:22:07 PM PDT 24 658126350 ps
T302 /workspace/coverage/default/16.rom_ctrl_stress_all.190297180 Jul 03 04:23:08 PM PDT 24 Jul 03 04:24:34 PM PDT 24 6019314642 ps
T303 /workspace/coverage/default/5.rom_ctrl_stress_all.292687857 Jul 03 04:22:51 PM PDT 24 Jul 03 04:23:26 PM PDT 24 2207574236 ps
T304 /workspace/coverage/default/39.rom_ctrl_stress_all.23948642 Jul 03 04:22:22 PM PDT 24 Jul 03 04:22:37 PM PDT 24 348085008 ps
T305 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.148476685 Jul 03 04:22:49 PM PDT 24 Jul 03 04:23:44 PM PDT 24 5944402996 ps
T306 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.115333936 Jul 03 04:23:00 PM PDT 24 Jul 03 04:30:07 PM PDT 24 429427411549 ps
T307 /workspace/coverage/default/42.rom_ctrl_alert_test.4194293100 Jul 03 04:22:57 PM PDT 24 Jul 03 04:23:06 PM PDT 24 172634140 ps
T308 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4279093823 Jul 03 04:22:57 PM PDT 24 Jul 03 04:26:47 PM PDT 24 6783535736 ps
T309 /workspace/coverage/default/28.rom_ctrl_alert_test.988994265 Jul 03 04:21:56 PM PDT 24 Jul 03 04:22:21 PM PDT 24 10542619757 ps
T310 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.4019791199 Jul 03 04:22:14 PM PDT 24 Jul 03 04:23:19 PM PDT 24 15476680593 ps
T311 /workspace/coverage/default/36.rom_ctrl_alert_test.3627541026 Jul 03 04:22:09 PM PDT 24 Jul 03 04:22:29 PM PDT 24 2052756115 ps
T312 /workspace/coverage/default/47.rom_ctrl_smoke.2652791400 Jul 03 04:22:37 PM PDT 24 Jul 03 04:23:04 PM PDT 24 1000703914 ps
T313 /workspace/coverage/default/10.rom_ctrl_smoke.125866515 Jul 03 04:23:07 PM PDT 24 Jul 03 04:24:12 PM PDT 24 12824612569 ps
T314 /workspace/coverage/default/28.rom_ctrl_stress_all.300043519 Jul 03 04:22:01 PM PDT 24 Jul 03 04:23:32 PM PDT 24 9406764247 ps
T315 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2005770384 Jul 03 04:22:21 PM PDT 24 Jul 03 04:31:50 PM PDT 24 204867020514 ps
T316 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1308990130 Jul 03 04:22:23 PM PDT 24 Jul 03 04:22:56 PM PDT 24 9573664693 ps
T317 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2895993703 Jul 03 04:22:18 PM PDT 24 Jul 03 04:24:34 PM PDT 24 4222291192 ps
T318 /workspace/coverage/default/31.rom_ctrl_smoke.4160324446 Jul 03 04:22:03 PM PDT 24 Jul 03 04:22:51 PM PDT 24 8549570404 ps
T319 /workspace/coverage/default/5.rom_ctrl_alert_test.143748907 Jul 03 04:22:49 PM PDT 24 Jul 03 04:23:21 PM PDT 24 37484784214 ps
T320 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.461516689 Jul 03 04:22:02 PM PDT 24 Jul 03 04:22:34 PM PDT 24 36176410869 ps
T321 /workspace/coverage/default/33.rom_ctrl_smoke.3130138557 Jul 03 04:22:09 PM PDT 24 Jul 03 04:22:42 PM PDT 24 3359400436 ps
T322 /workspace/coverage/default/25.rom_ctrl_stress_all.1047771842 Jul 03 04:22:03 PM PDT 24 Jul 03 04:23:09 PM PDT 24 28796938339 ps
T323 /workspace/coverage/default/45.rom_ctrl_stress_all.3944594127 Jul 03 04:22:27 PM PDT 24 Jul 03 04:23:44 PM PDT 24 32253491786 ps
T324 /workspace/coverage/default/19.rom_ctrl_alert_test.1712289686 Jul 03 04:22:02 PM PDT 24 Jul 03 04:22:13 PM PDT 24 820945402 ps
T325 /workspace/coverage/default/21.rom_ctrl_alert_test.1623659999 Jul 03 04:22:01 PM PDT 24 Jul 03 04:22:10 PM PDT 24 660533905 ps
T32 /workspace/coverage/default/2.rom_ctrl_sec_cm.1625440025 Jul 03 04:22:59 PM PDT 24 Jul 03 04:27:01 PM PDT 24 14099754224 ps
T326 /workspace/coverage/default/35.rom_ctrl_smoke.3690748580 Jul 03 04:22:15 PM PDT 24 Jul 03 04:22:36 PM PDT 24 362453570 ps
T327 /workspace/coverage/default/8.rom_ctrl_stress_all.3034994668 Jul 03 04:23:06 PM PDT 24 Jul 03 04:24:32 PM PDT 24 41211191312 ps
T328 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.285863597 Jul 03 04:22:11 PM PDT 24 Jul 03 04:22:31 PM PDT 24 346274203 ps
T329 /workspace/coverage/default/5.rom_ctrl_smoke.2368693917 Jul 03 04:22:58 PM PDT 24 Jul 03 04:23:55 PM PDT 24 22413755381 ps
T330 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.4211813275 Jul 03 04:21:57 PM PDT 24 Jul 03 04:22:32 PM PDT 24 4115730745 ps
T331 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2935381680 Jul 03 04:22:07 PM PDT 24 Jul 03 04:25:29 PM PDT 24 6975872667 ps
T332 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1166058139 Jul 03 04:23:08 PM PDT 24 Jul 03 04:23:52 PM PDT 24 15716178906 ps
T333 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.851779805 Jul 03 04:21:56 PM PDT 24 Jul 03 04:22:28 PM PDT 24 15636824045 ps
T334 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2000013674 Jul 03 04:22:16 PM PDT 24 Jul 03 04:28:06 PM PDT 24 36282199941 ps
T335 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2657791228 Jul 03 04:22:12 PM PDT 24 Jul 03 04:29:49 PM PDT 24 34257131611 ps
T336 /workspace/coverage/default/6.rom_ctrl_stress_all.970571714 Jul 03 04:22:56 PM PDT 24 Jul 03 04:23:49 PM PDT 24 3443584138 ps
T337 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2122215969 Jul 03 04:22:04 PM PDT 24 Jul 03 04:22:15 PM PDT 24 692376528 ps
T338 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.725096795 Jul 03 04:22:58 PM PDT 24 Jul 03 04:23:40 PM PDT 24 14379388616 ps
T339 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1565698462 Jul 03 04:22:06 PM PDT 24 Jul 03 04:22:40 PM PDT 24 2297988297 ps
T340 /workspace/coverage/default/2.rom_ctrl_alert_test.625717652 Jul 03 04:22:42 PM PDT 24 Jul 03 04:23:04 PM PDT 24 7592255519 ps
T341 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.4126730459 Jul 03 04:21:59 PM PDT 24 Jul 03 04:29:59 PM PDT 24 37308254410 ps
T342 /workspace/coverage/default/3.rom_ctrl_smoke.1804764877 Jul 03 04:21:37 PM PDT 24 Jul 03 04:22:43 PM PDT 24 45751713528 ps
T343 /workspace/coverage/default/21.rom_ctrl_smoke.2115832463 Jul 03 04:22:02 PM PDT 24 Jul 03 04:22:31 PM PDT 24 1329570236 ps
T344 /workspace/coverage/default/30.rom_ctrl_stress_all.1223459046 Jul 03 04:22:05 PM PDT 24 Jul 03 04:23:01 PM PDT 24 861958115 ps
T345 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.4286295509 Jul 03 04:21:56 PM PDT 24 Jul 03 04:22:11 PM PDT 24 2771538981 ps
T346 /workspace/coverage/default/22.rom_ctrl_smoke.303817621 Jul 03 04:22:00 PM PDT 24 Jul 03 04:22:43 PM PDT 24 17103866483 ps
T347 /workspace/coverage/default/11.rom_ctrl_stress_all.1981081383 Jul 03 04:23:09 PM PDT 24 Jul 03 04:23:46 PM PDT 24 1162673946 ps
T348 /workspace/coverage/default/49.rom_ctrl_alert_test.1283741317 Jul 03 04:22:33 PM PDT 24 Jul 03 04:23:08 PM PDT 24 16959942630 ps
T349 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2634415089 Jul 03 04:22:06 PM PDT 24 Jul 03 04:23:17 PM PDT 24 74580623431 ps
T350 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3927624004 Jul 03 04:22:44 PM PDT 24 Jul 03 04:23:41 PM PDT 24 43687624377 ps
T351 /workspace/coverage/default/27.rom_ctrl_alert_test.3923355264 Jul 03 04:22:02 PM PDT 24 Jul 03 04:22:16 PM PDT 24 3080479075 ps
T352 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3360969615 Jul 03 04:22:30 PM PDT 24 Jul 03 04:23:03 PM PDT 24 16350373116 ps
T353 /workspace/coverage/default/31.rom_ctrl_alert_test.1775301950 Jul 03 04:22:12 PM PDT 24 Jul 03 04:22:39 PM PDT 24 6191125062 ps
T354 /workspace/coverage/default/44.rom_ctrl_stress_all.3142602251 Jul 03 04:22:38 PM PDT 24 Jul 03 04:24:47 PM PDT 24 60344569394 ps
T355 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3215993776 Jul 03 04:23:14 PM PDT 24 Jul 03 04:26:55 PM PDT 24 15052123787 ps
T356 /workspace/coverage/default/26.rom_ctrl_stress_all.3367367613 Jul 03 04:22:03 PM PDT 24 Jul 03 04:22:35 PM PDT 24 2399594054 ps
T357 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1208015585 Jul 03 04:22:31 PM PDT 24 Jul 03 04:22:50 PM PDT 24 2357106892 ps
T358 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1232897691 Jul 03 04:22:56 PM PDT 24 Jul 03 04:23:43 PM PDT 24 8848118923 ps
T359 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3754440809 Jul 03 04:22:33 PM PDT 24 Jul 03 04:22:53 PM PDT 24 674877049 ps
T360 /workspace/coverage/default/38.rom_ctrl_stress_all.1477923746 Jul 03 04:22:22 PM PDT 24 Jul 03 04:23:07 PM PDT 24 5954329387 ps
T361 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1435426598 Jul 03 04:21:57 PM PDT 24 Jul 03 04:34:00 PM PDT 24 283808878455 ps
T362 /workspace/coverage/default/12.rom_ctrl_smoke.892318799 Jul 03 04:22:59 PM PDT 24 Jul 03 04:23:39 PM PDT 24 5267809570 ps
T363 /workspace/coverage/default/37.rom_ctrl_smoke.2227184743 Jul 03 04:22:18 PM PDT 24 Jul 03 04:22:52 PM PDT 24 2215348849 ps
T364 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1621705306 Jul 03 04:23:02 PM PDT 24 Jul 03 04:31:24 PM PDT 24 29041166993 ps
T365 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1492077376 Jul 03 04:23:00 PM PDT 24 Jul 03 04:23:24 PM PDT 24 4771783319 ps
T65 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.156122752 Jul 03 04:21:12 PM PDT 24 Jul 03 04:21:38 PM PDT 24 2715182987 ps
T66 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1718174762 Jul 03 04:21:21 PM PDT 24 Jul 03 04:21:43 PM PDT 24 2046850681 ps
T67 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3175925265 Jul 03 04:21:37 PM PDT 24 Jul 03 04:21:59 PM PDT 24 4643550310 ps
T73 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.339901455 Jul 03 04:22:30 PM PDT 24 Jul 03 04:22:59 PM PDT 24 7012970192 ps
T104 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4135684306 Jul 03 04:21:46 PM PDT 24 Jul 03 04:22:20 PM PDT 24 4086368731 ps
T98 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.88659879 Jul 03 04:22:53 PM PDT 24 Jul 03 04:23:09 PM PDT 24 1237419933 ps
T366 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.198581303 Jul 03 04:23:02 PM PDT 24 Jul 03 04:23:20 PM PDT 24 17699484351 ps
T62 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.931358968 Jul 03 04:21:21 PM PDT 24 Jul 03 04:24:03 PM PDT 24 8509569448 ps
T105 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.4123577719 Jul 03 04:23:00 PM PDT 24 Jul 03 04:24:31 PM PDT 24 8518703646 ps
T367 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.859159039 Jul 03 04:22:23 PM PDT 24 Jul 03 04:22:34 PM PDT 24 189139069 ps
T368 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2336128583 Jul 03 04:21:14 PM PDT 24 Jul 03 04:21:43 PM PDT 24 3343542268 ps
T106 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2323398348 Jul 03 04:20:48 PM PDT 24 Jul 03 04:21:59 PM PDT 24 27638879330 ps
T74 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3741809456 Jul 03 04:23:01 PM PDT 24 Jul 03 04:24:53 PM PDT 24 9274114327 ps
T75 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.169234667 Jul 03 04:21:57 PM PDT 24 Jul 03 04:22:44 PM PDT 24 4823867526 ps
T369 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2262585160 Jul 03 04:23:09 PM PDT 24 Jul 03 04:23:19 PM PDT 24 1388677351 ps
T76 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2030872237 Jul 03 04:21:17 PM PDT 24 Jul 03 04:23:51 PM PDT 24 63127563575 ps
T77 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2523694422 Jul 03 04:21:30 PM PDT 24 Jul 03 04:21:43 PM PDT 24 2632776839 ps
T370 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2556688535 Jul 03 04:22:55 PM PDT 24 Jul 03 04:23:14 PM PDT 24 4279699297 ps
T371 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1089003583 Jul 03 04:21:14 PM PDT 24 Jul 03 04:21:37 PM PDT 24 2570829402 ps
T372 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3084083766 Jul 03 04:23:09 PM PDT 24 Jul 03 04:23:31 PM PDT 24 3122602301 ps
T373 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.430753602 Jul 03 04:20:17 PM PDT 24 Jul 03 04:20:49 PM PDT 24 3394243458 ps
T63 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2733474889 Jul 03 04:20:58 PM PDT 24 Jul 03 04:23:52 PM PDT 24 4255242600 ps
T374 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.186719814 Jul 03 04:21:36 PM PDT 24 Jul 03 04:21:46 PM PDT 24 180647884 ps
T64 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3497228190 Jul 03 04:21:07 PM PDT 24 Jul 03 04:22:49 PM PDT 24 38947805927 ps
T375 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.555320396 Jul 03 04:23:00 PM PDT 24 Jul 03 04:24:46 PM PDT 24 23846214407 ps
T109 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3865144291 Jul 03 04:22:55 PM PDT 24 Jul 03 04:25:24 PM PDT 24 2954101409 ps
T376 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.840374850 Jul 03 04:21:27 PM PDT 24 Jul 03 04:22:02 PM PDT 24 9468045664 ps
T377 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3094554343 Jul 03 04:23:09 PM PDT 24 Jul 03 04:26:32 PM PDT 24 25970779253 ps
T378 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.609585746 Jul 03 04:23:15 PM PDT 24 Jul 03 04:23:37 PM PDT 24 3446103560 ps
T379 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.4054328257 Jul 03 04:21:17 PM PDT 24 Jul 03 04:21:51 PM PDT 24 15035952765 ps
T78 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3855802718 Jul 03 04:23:01 PM PDT 24 Jul 03 04:23:40 PM PDT 24 2855305389 ps
T99 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.733882414 Jul 03 04:21:48 PM PDT 24 Jul 03 04:22:20 PM PDT 24 3796608994 ps
T79 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.300987227 Jul 03 04:22:55 PM PDT 24 Jul 03 04:25:25 PM PDT 24 65198457697 ps
T380 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1018864196 Jul 03 04:21:39 PM PDT 24 Jul 03 04:21:53 PM PDT 24 167472094 ps
T381 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2714458470 Jul 03 04:23:09 PM PDT 24 Jul 03 04:23:35 PM PDT 24 4891094715 ps
T382 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.136113874 Jul 03 04:21:05 PM PDT 24 Jul 03 04:21:16 PM PDT 24 751452649 ps
T110 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.417570201 Jul 03 04:21:57 PM PDT 24 Jul 03 04:24:39 PM PDT 24 1522573774 ps
T383 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2212277554 Jul 03 04:21:37 PM PDT 24 Jul 03 04:21:46 PM PDT 24 176346229 ps
T121 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1918576422 Jul 03 04:21:51 PM PDT 24 Jul 03 04:24:34 PM PDT 24 15024458509 ps
T384 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1833655245 Jul 03 04:22:53 PM PDT 24 Jul 03 04:23:11 PM PDT 24 1153116790 ps
T113 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.261835445 Jul 03 04:21:36 PM PDT 24 Jul 03 04:22:56 PM PDT 24 925955689 ps
T385 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1164670274 Jul 03 04:21:28 PM PDT 24 Jul 03 04:21:36 PM PDT 24 172605946 ps
T80 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1331946613 Jul 03 04:21:03 PM PDT 24 Jul 03 04:23:27 PM PDT 24 42066506076 ps
T386 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1438765728 Jul 03 04:21:12 PM PDT 24 Jul 03 04:21:30 PM PDT 24 3276721855 ps
T100 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3441865085 Jul 03 04:21:17 PM PDT 24 Jul 03 04:21:43 PM PDT 24 2946826577 ps
T81 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.484758529 Jul 03 04:21:03 PM PDT 24 Jul 03 04:21:21 PM PDT 24 4115793210 ps
T387 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2330113391 Jul 03 04:22:53 PM PDT 24 Jul 03 04:23:23 PM PDT 24 8234545771 ps
T88 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4191322600 Jul 03 04:19:39 PM PDT 24 Jul 03 04:20:13 PM PDT 24 32876657689 ps
T388 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4020690139 Jul 03 04:23:01 PM PDT 24 Jul 03 04:23:25 PM PDT 24 7164235645 ps
T389 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1486694967 Jul 03 04:21:36 PM PDT 24 Jul 03 04:21:49 PM PDT 24 2169295574 ps
T117 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1890051066 Jul 03 04:21:22 PM PDT 24 Jul 03 04:22:45 PM PDT 24 306706800 ps
T101 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3542614619 Jul 03 04:22:52 PM PDT 24 Jul 03 04:23:24 PM PDT 24 55902731740 ps
T390 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2804797891 Jul 03 04:21:21 PM PDT 24 Jul 03 04:21:46 PM PDT 24 2793953089 ps
T391 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1836541307 Jul 03 04:21:37 PM PDT 24 Jul 03 04:21:59 PM PDT 24 6136333413 ps
T102 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2645081221 Jul 03 04:21:03 PM PDT 24 Jul 03 04:21:16 PM PDT 24 2634583247 ps
T392 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2492089767 Jul 03 04:20:48 PM PDT 24 Jul 03 04:21:10 PM PDT 24 1679648894 ps
T393 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3189454753 Jul 03 04:21:19 PM PDT 24 Jul 03 04:21:44 PM PDT 24 44438185886 ps
T89 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1107470327 Jul 03 04:21:31 PM PDT 24 Jul 03 04:21:59 PM PDT 24 14019524651 ps
T394 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2606108357 Jul 03 04:21:35 PM PDT 24 Jul 03 04:22:05 PM PDT 24 14711227263 ps
T395 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.226995803 Jul 03 04:20:44 PM PDT 24 Jul 03 04:20:53 PM PDT 24 688462775 ps
T94 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4249306873 Jul 03 04:21:40 PM PDT 24 Jul 03 04:22:50 PM PDT 24 11024915547 ps
T396 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.559677100 Jul 03 04:21:37 PM PDT 24 Jul 03 04:22:11 PM PDT 24 7577011145 ps
T397 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2889133340 Jul 03 04:23:08 PM PDT 24 Jul 03 04:23:34 PM PDT 24 8245197030 ps
T103 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1255220867 Jul 03 04:21:44 PM PDT 24 Jul 03 04:22:13 PM PDT 24 2873635741 ps
T398 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.460044420 Jul 03 04:22:10 PM PDT 24 Jul 03 04:22:40 PM PDT 24 2243332144 ps
T399 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1028824440 Jul 03 04:21:14 PM PDT 24 Jul 03 04:21:23 PM PDT 24 689389371 ps
T400 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2259455579 Jul 03 04:22:55 PM PDT 24 Jul 03 04:23:29 PM PDT 24 70912701903 ps
T401 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1085706838 Jul 03 04:21:18 PM PDT 24 Jul 03 04:21:32 PM PDT 24 3211722196 ps
T402 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2016695772 Jul 03 04:21:13 PM PDT 24 Jul 03 04:21:22 PM PDT 24 688712572 ps
T95 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3828936711 Jul 03 04:21:38 PM PDT 24 Jul 03 04:23:11 PM PDT 24 8817801942 ps
T403 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.894270969 Jul 03 04:21:53 PM PDT 24 Jul 03 04:22:31 PM PDT 24 2387586978 ps
T404 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2420509167 Jul 03 04:21:05 PM PDT 24 Jul 03 04:21:13 PM PDT 24 170836358 ps
T90 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3971536420 Jul 03 04:21:57 PM PDT 24 Jul 03 04:22:21 PM PDT 24 18613788684 ps
T405 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3414617532 Jul 03 04:21:05 PM PDT 24 Jul 03 04:21:32 PM PDT 24 29219078749 ps
T406 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2706827000 Jul 03 04:21:39 PM PDT 24 Jul 03 04:22:05 PM PDT 24 2160513549 ps
T407 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3866618453 Jul 03 04:22:53 PM PDT 24 Jul 03 04:23:17 PM PDT 24 3602664923 ps
T408 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2542674201 Jul 03 04:21:15 PM PDT 24 Jul 03 04:21:49 PM PDT 24 14391124964 ps
T409 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1042151126 Jul 03 04:23:04 PM PDT 24 Jul 03 04:23:20 PM PDT 24 10722762012 ps
T410 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3582837053 Jul 03 04:23:09 PM PDT 24 Jul 03 04:23:23 PM PDT 24 896909543 ps
T107 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2991352241 Jul 03 04:21:14 PM PDT 24 Jul 03 04:22:20 PM PDT 24 3236683407 ps
T411 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1592866330 Jul 03 04:21:05 PM PDT 24 Jul 03 04:21:27 PM PDT 24 6119631283 ps
T412 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.47916902 Jul 03 04:21:52 PM PDT 24 Jul 03 04:22:05 PM PDT 24 2736481467 ps
T413 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3318762141 Jul 03 04:21:57 PM PDT 24 Jul 03 04:22:11 PM PDT 24 1321142516 ps
T414 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2365902032 Jul 03 04:21:56 PM PDT 24 Jul 03 04:22:04 PM PDT 24 718555905 ps
T415 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.4179199050 Jul 03 04:20:42 PM PDT 24 Jul 03 04:22:44 PM PDT 24 156688525071 ps
T416 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2208051395 Jul 03 04:21:22 PM PDT 24 Jul 03 04:21:40 PM PDT 24 3022818811 ps
T417 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4083846359 Jul 03 04:20:51 PM PDT 24 Jul 03 04:22:30 PM PDT 24 17019042424 ps
T418 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.570745448 Jul 03 04:21:17 PM PDT 24 Jul 03 04:21:49 PM PDT 24 3613854849 ps
T419 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3215522038 Jul 03 04:21:21 PM PDT 24 Jul 03 04:21:40 PM PDT 24 7846690513 ps
T119 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.228491816 Jul 03 04:23:00 PM PDT 24 Jul 03 04:25:51 PM PDT 24 3415541563 ps
T420 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.443768089 Jul 03 04:21:45 PM PDT 24 Jul 03 04:21:57 PM PDT 24 172508498 ps
T421 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.510568781 Jul 03 04:20:48 PM PDT 24 Jul 03 04:21:11 PM PDT 24 9563856063 ps
T91 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1092953625 Jul 03 04:23:01 PM PDT 24 Jul 03 04:23:29 PM PDT 24 12940932248 ps
T422 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.753546631 Jul 03 04:22:58 PM PDT 24 Jul 03 04:23:12 PM PDT 24 3080409619 ps
T423 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3179577225 Jul 03 04:21:28 PM PDT 24 Jul 03 04:21:37 PM PDT 24 167760451 ps
T424 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1580351041 Jul 03 04:20:51 PM PDT 24 Jul 03 04:21:03 PM PDT 24 438011088 ps
T425 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3534658658 Jul 03 04:21:15 PM PDT 24 Jul 03 04:21:41 PM PDT 24 10178264908 ps
T426 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.901579877 Jul 03 04:20:36 PM PDT 24 Jul 03 04:20:44 PM PDT 24 360405552 ps
T92 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2410798305 Jul 03 04:22:57 PM PDT 24 Jul 03 04:23:27 PM PDT 24 18581199954 ps
T120 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3269964602 Jul 03 04:22:52 PM PDT 24 Jul 03 04:25:34 PM PDT 24 5191050142 ps
T427 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3611227643 Jul 03 04:21:52 PM PDT 24 Jul 03 04:22:17 PM PDT 24 2708272573 ps
T428 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.501396141 Jul 03 04:21:32 PM PDT 24 Jul 03 04:22:07 PM PDT 24 39076822961 ps
T116 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2334569312 Jul 03 04:23:02 PM PDT 24 Jul 03 04:25:41 PM PDT 24 1392749140 ps
T429 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1152715488 Jul 03 04:22:05 PM PDT 24 Jul 03 04:22:37 PM PDT 24 6753088797 ps
T430 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1411548874 Jul 03 04:21:32 PM PDT 24 Jul 03 04:23:09 PM PDT 24 21875952088 ps
T431 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3357568263 Jul 03 04:21:18 PM PDT 24 Jul 03 04:21:33 PM PDT 24 1092647176 ps
T432 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2334683919 Jul 03 04:21:29 PM PDT 24 Jul 03 04:22:02 PM PDT 24 13201682516 ps
T433 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3355928398 Jul 03 04:21:21 PM PDT 24 Jul 03 04:21:53 PM PDT 24 8175860983 ps
T434 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3569492688 Jul 03 04:19:35 PM PDT 24 Jul 03 04:21:07 PM PDT 24 10391046657 ps
T435 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.183371899 Jul 03 04:21:31 PM PDT 24 Jul 03 04:22:02 PM PDT 24 15773479776 ps
T436 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3714202887 Jul 03 04:21:36 PM PDT 24 Jul 03 04:22:00 PM PDT 24 5922133199 ps
T437 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3042631240 Jul 03 04:20:03 PM PDT 24 Jul 03 04:20:31 PM PDT 24 2797948662 ps
T438 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2594968112 Jul 03 04:19:08 PM PDT 24 Jul 03 04:19:36 PM PDT 24 7200301711 ps
T111 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3495097737 Jul 03 04:21:08 PM PDT 24 Jul 03 04:23:55 PM PDT 24 1987113188 ps
T439 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.974921356 Jul 03 04:22:01 PM PDT 24 Jul 03 04:22:58 PM PDT 24 4144531465 ps
T440 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3246052632 Jul 03 04:21:00 PM PDT 24 Jul 03 04:21:21 PM PDT 24 7524073841 ps
T441 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1687024636 Jul 03 04:21:54 PM PDT 24 Jul 03 04:22:27 PM PDT 24 4290887998 ps
T442 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2214881034 Jul 03 04:22:55 PM PDT 24 Jul 03 04:23:18 PM PDT 24 2568162217 ps
T443 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1804723106 Jul 03 04:21:13 PM PDT 24 Jul 03 04:23:13 PM PDT 24 12052051569 ps
T444 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1432060766 Jul 03 04:20:46 PM PDT 24 Jul 03 04:21:02 PM PDT 24 4128311238 ps
T445 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1100887225 Jul 03 04:22:31 PM PDT 24 Jul 03 04:22:47 PM PDT 24 429255579 ps
T446 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.119326503 Jul 03 04:21:28 PM PDT 24 Jul 03 04:21:44 PM PDT 24 1155390497 ps
T447 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.129155027 Jul 03 04:21:13 PM PDT 24 Jul 03 04:21:21 PM PDT 24 338320522 ps
T448 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1529656232 Jul 03 04:23:09 PM PDT 24 Jul 03 04:23:19 PM PDT 24 766924121 ps
T96 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1351717470 Jul 03 04:21:22 PM PDT 24 Jul 03 04:22:43 PM PDT 24 13462331516 ps
T97 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1036202342 Jul 03 04:21:16 PM PDT 24 Jul 03 04:21:41 PM PDT 24 3042761118 ps
T449 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1537412556 Jul 03 04:20:34 PM PDT 24 Jul 03 04:20:55 PM PDT 24 2221837541 ps
T450 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2389196665 Jul 03 04:21:33 PM PDT 24 Jul 03 04:21:55 PM PDT 24 2225064032 ps
T451 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2416700700 Jul 03 04:21:15 PM PDT 24 Jul 03 04:22:45 PM PDT 24 5297350006 ps
T112 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3491799297 Jul 03 04:22:58 PM PDT 24 Jul 03 04:25:34 PM PDT 24 822558904 ps
T452 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.752393569 Jul 03 04:20:28 PM PDT 24 Jul 03 04:21:01 PM PDT 24 16637716135 ps
T453 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1783934132 Jul 03 04:21:56 PM PDT 24 Jul 03 04:23:04 PM PDT 24 8421431093 ps
T454 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.641345263 Jul 03 04:20:17 PM PDT 24 Jul 03 04:20:38 PM PDT 24 16406549447 ps
T455 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.430229443 Jul 03 04:20:57 PM PDT 24 Jul 03 04:21:24 PM PDT 24 14118524360 ps
T93 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.345095590 Jul 03 04:21:15 PM PDT 24 Jul 03 04:22:11 PM PDT 24 7938078302 ps
T456 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2628591226 Jul 03 04:23:09 PM PDT 24 Jul 03 04:23:34 PM PDT 24 2667007254 ps
T457 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2244321633 Jul 03 04:21:27 PM PDT 24 Jul 03 04:21:52 PM PDT 24 5493945769 ps
T458 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.765522368 Jul 03 04:22:06 PM PDT 24 Jul 03 04:22:32 PM PDT 24 9804218188 ps
T118 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3492873668 Jul 03 04:22:31 PM PDT 24 Jul 03 04:25:02 PM PDT 24 1445207265 ps
T459 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3340044797 Jul 03 04:20:50 PM PDT 24 Jul 03 04:21:19 PM PDT 24 10825119125 ps
T114 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.46758242 Jul 03 04:21:12 PM PDT 24 Jul 03 04:22:35 PM PDT 24 522668358 ps
T460 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4063587898 Jul 03 04:23:02 PM PDT 24 Jul 03 04:23:36 PM PDT 24 4371904307 ps
T115 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3418812198 Jul 03 04:23:02 PM PDT 24 Jul 03 04:25:39 PM PDT 24 470610912 ps
T461 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2955722085 Jul 03 04:21:00 PM PDT 24 Jul 03 04:21:28 PM PDT 24 8525873227 ps

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3448535664
Short name T2
Test name
Test status
Simulation time 9001034245 ps
CPU time 21.85 seconds
Started Jul 03 04:22:02 PM PDT 24
Finished Jul 03 04:22:24 PM PDT 24
Peak memory 219264 kb
Host smart-3fcaffdc-a363-499a-b15d-6084dfb73866
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3448535664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3448535664
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2668612849
Short name T16
Test name
Test status
Simulation time 74944823161 ps
CPU time 3092.8 seconds
Started Jul 03 04:22:58 PM PDT 24
Finished Jul 03 05:14:32 PM PDT 24
Peak memory 232604 kb
Host smart-ab50eb11-0480-4bcf-b900-b3581d8046b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668612849 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.2668612849
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3546929325
Short name T11
Test name
Test status
Simulation time 371574900643 ps
CPU time 761.54 seconds
Started Jul 03 04:22:00 PM PDT 24
Finished Jul 03 04:34:42 PM PDT 24
Peak memory 228232 kb
Host smart-ea87a006-e1e8-4016-ba64-f3d849e35008
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546929325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3546929325
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.471371339
Short name T7
Test name
Test status
Simulation time 517444031 ps
CPU time 21.32 seconds
Started Jul 03 04:22:15 PM PDT 24
Finished Jul 03 04:22:37 PM PDT 24
Peak memory 218960 kb
Host smart-d9a8b4f7-562a-466e-81af-f41c8166dad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471371339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.471371339
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3288099826
Short name T50
Test name
Test status
Simulation time 452760423315 ps
CPU time 449.2 seconds
Started Jul 03 04:22:18 PM PDT 24
Finished Jul 03 04:29:50 PM PDT 24
Peak memory 225812 kb
Host smart-04ac99ff-a89c-4ecb-83ed-c22ffa9e5c3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288099826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3288099826
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2733474889
Short name T63
Test name
Test status
Simulation time 4255242600 ps
CPU time 173.61 seconds
Started Jul 03 04:20:58 PM PDT 24
Finished Jul 03 04:23:52 PM PDT 24
Peak memory 214400 kb
Host smart-82685987-7959-435d-b565-52be68f78407
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733474889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2733474889
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3615490464
Short name T205
Test name
Test status
Simulation time 167420883043 ps
CPU time 635.5 seconds
Started Jul 03 04:22:12 PM PDT 24
Finished Jul 03 04:32:48 PM PDT 24
Peak memory 216768 kb
Host smart-a38f3c1c-cee2-49b6-95e6-fbb61bf00e88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615490464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3615490464
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3726301243
Short name T37
Test name
Test status
Simulation time 10004373137 ps
CPU time 44.07 seconds
Started Jul 03 04:23:00 PM PDT 24
Finished Jul 03 04:23:47 PM PDT 24
Peak memory 218908 kb
Host smart-67534f4d-d09d-494f-a55a-1d699c88164f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726301243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3726301243
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3741809456
Short name T74
Test name
Test status
Simulation time 9274114327 ps
CPU time 108.8 seconds
Started Jul 03 04:23:01 PM PDT 24
Finished Jul 03 04:24:53 PM PDT 24
Peak memory 215092 kb
Host smart-e6331372-4c2a-4598-acc3-4ffb80857123
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741809456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3741809456
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3457193662
Short name T26
Test name
Test status
Simulation time 3042428561 ps
CPU time 129.47 seconds
Started Jul 03 04:23:08 PM PDT 24
Finished Jul 03 04:25:19 PM PDT 24
Peak memory 237800 kb
Host smart-483d49bd-8704-41c3-b63b-83016d629fb9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457193662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3457193662
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2268909404
Short name T6
Test name
Test status
Simulation time 1044906892 ps
CPU time 14.62 seconds
Started Jul 03 04:22:13 PM PDT 24
Finished Jul 03 04:22:28 PM PDT 24
Peak memory 217120 kb
Host smart-536e9d94-4ea6-416c-89bd-4378146e2fa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268909404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2268909404
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2334569312
Short name T116
Test name
Test status
Simulation time 1392749140 ps
CPU time 156.1 seconds
Started Jul 03 04:23:02 PM PDT 24
Finished Jul 03 04:25:41 PM PDT 24
Peak memory 213408 kb
Host smart-4a67b13e-834f-4dbe-98b0-842c8125e48f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334569312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2334569312
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1266037285
Short name T126
Test name
Test status
Simulation time 1320130852 ps
CPU time 19.12 seconds
Started Jul 03 04:22:12 PM PDT 24
Finished Jul 03 04:22:32 PM PDT 24
Peak memory 219188 kb
Host smart-8b7bf280-e89b-4e5a-9149-4d063021360c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266037285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1266037285
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3492873668
Short name T118
Test name
Test status
Simulation time 1445207265 ps
CPU time 150.37 seconds
Started Jul 03 04:22:31 PM PDT 24
Finished Jul 03 04:25:02 PM PDT 24
Peak memory 213872 kb
Host smart-ea07ee24-bc76-4fb5-97ba-61d72399e81e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492873668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3492873668
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.46758242
Short name T114
Test name
Test status
Simulation time 522668358 ps
CPU time 81.79 seconds
Started Jul 03 04:21:12 PM PDT 24
Finished Jul 03 04:22:35 PM PDT 24
Peak memory 212160 kb
Host smart-7314d38d-9809-4886-87a1-114dde431c8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46758242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_intg
_err.46758242
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.169234667
Short name T75
Test name
Test status
Simulation time 4823867526 ps
CPU time 45.64 seconds
Started Jul 03 04:21:57 PM PDT 24
Finished Jul 03 04:22:44 PM PDT 24
Peak memory 213656 kb
Host smart-421bcd81-f38c-424f-aa41-57c3106d4edb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169234667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.169234667
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.881141624
Short name T82
Test name
Test status
Simulation time 11187979443 ps
CPU time 56.82 seconds
Started Jul 03 04:21:43 PM PDT 24
Finished Jul 03 04:22:41 PM PDT 24
Peak memory 217176 kb
Host smart-2b9c20f8-bfc3-4c50-b6fe-70b42bf5fb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881141624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.881141624
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3796603578
Short name T13
Test name
Test status
Simulation time 6615208922 ps
CPU time 19.85 seconds
Started Jul 03 04:22:13 PM PDT 24
Finished Jul 03 04:22:33 PM PDT 24
Peak memory 211676 kb
Host smart-70e459f7-a6bf-42ee-9c3e-9901775e7d58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3796603578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3796603578
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.156122752
Short name T65
Test name
Test status
Simulation time 2715182987 ps
CPU time 24.77 seconds
Started Jul 03 04:21:12 PM PDT 24
Finished Jul 03 04:21:38 PM PDT 24
Peak memory 210200 kb
Host smart-50ce8bbf-b612-4dd6-8cb0-32e6fc4b480b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156122752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.156122752
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.235642049
Short name T17
Test name
Test status
Simulation time 68972884119 ps
CPU time 4883.11 seconds
Started Jul 03 04:21:59 PM PDT 24
Finished Jul 03 05:43:23 PM PDT 24
Peak memory 232624 kb
Host smart-1ad0e94d-5302-4dc6-804d-233c995c0278
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235642049 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.235642049
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.3396666981
Short name T52
Test name
Test status
Simulation time 52126387311 ps
CPU time 1880.63 seconds
Started Jul 03 04:22:59 PM PDT 24
Finished Jul 03 04:54:22 PM PDT 24
Peak memory 229768 kb
Host smart-9ba1601f-b155-4ee1-a61f-40206a36b443
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396666981 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.3396666981
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2594968112
Short name T438
Test name
Test status
Simulation time 7200301711 ps
CPU time 28.09 seconds
Started Jul 03 04:19:08 PM PDT 24
Finished Jul 03 04:19:36 PM PDT 24
Peak memory 211492 kb
Host smart-a4155ea5-c9ff-4cad-a1e9-408cd0f2d193
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594968112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2594968112
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3179577225
Short name T423
Test name
Test status
Simulation time 167760451 ps
CPU time 8.13 seconds
Started Jul 03 04:21:28 PM PDT 24
Finished Jul 03 04:21:37 PM PDT 24
Peak memory 210604 kb
Host smart-1928c45a-b0d1-48cc-b4f8-c2f37d46499a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179577225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3179577225
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4191322600
Short name T88
Test name
Test status
Simulation time 32876657689 ps
CPU time 34.05 seconds
Started Jul 03 04:19:39 PM PDT 24
Finished Jul 03 04:20:13 PM PDT 24
Peak memory 212248 kb
Host smart-8bbd8dac-9211-4393-bd65-2c0ba5443a7d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191322600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.4191322600
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.641345263
Short name T454
Test name
Test status
Simulation time 16406549447 ps
CPU time 21.42 seconds
Started Jul 03 04:20:17 PM PDT 24
Finished Jul 03 04:20:38 PM PDT 24
Peak memory 218204 kb
Host smart-3870aca0-dd7e-4b54-ac03-75a65facab6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641345263 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.641345263
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.119326503
Short name T446
Test name
Test status
Simulation time 1155390497 ps
CPU time 15.16 seconds
Started Jul 03 04:21:28 PM PDT 24
Finished Jul 03 04:21:44 PM PDT 24
Peak memory 210604 kb
Host smart-37a14d07-61c7-4783-bb09-2e504065c5c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119326503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.119326503
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4063587898
Short name T460
Test name
Test status
Simulation time 4371904307 ps
CPU time 31.42 seconds
Started Jul 03 04:23:02 PM PDT 24
Finished Jul 03 04:23:36 PM PDT 24
Peak memory 210424 kb
Host smart-c5ffaf7f-a24e-44b3-9f9e-88a9b9e63dc0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063587898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.4063587898
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1164670274
Short name T385
Test name
Test status
Simulation time 172605946 ps
CPU time 7.96 seconds
Started Jul 03 04:21:28 PM PDT 24
Finished Jul 03 04:21:36 PM PDT 24
Peak memory 210452 kb
Host smart-125d0401-28d7-4a46-a227-49ebfc03698a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164670274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1164670274
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2244321633
Short name T457
Test name
Test status
Simulation time 5493945769 ps
CPU time 24.5 seconds
Started Jul 03 04:21:27 PM PDT 24
Finished Jul 03 04:21:52 PM PDT 24
Peak memory 212640 kb
Host smart-8ab7522c-7760-4414-9253-950153602bda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244321633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2244321633
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3042631240
Short name T437
Test name
Test status
Simulation time 2797948662 ps
CPU time 27.92 seconds
Started Jul 03 04:20:03 PM PDT 24
Finished Jul 03 04:20:31 PM PDT 24
Peak memory 218148 kb
Host smart-91f0ec56-3707-4140-bb63-8662d96e73b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042631240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3042631240
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3569492688
Short name T434
Test name
Test status
Simulation time 10391046657 ps
CPU time 91.89 seconds
Started Jul 03 04:19:35 PM PDT 24
Finished Jul 03 04:21:07 PM PDT 24
Peak memory 214056 kb
Host smart-32b3180e-a9b7-434c-8b63-1cf6f8e554f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569492688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3569492688
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3534658658
Short name T425
Test name
Test status
Simulation time 10178264908 ps
CPU time 25.43 seconds
Started Jul 03 04:21:15 PM PDT 24
Finished Jul 03 04:21:41 PM PDT 24
Peak memory 211648 kb
Host smart-da91acf3-df2e-48ff-8b4e-5ed7b189dbaa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534658658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3534658658
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2542674201
Short name T408
Test name
Test status
Simulation time 14391124964 ps
CPU time 33.09 seconds
Started Jul 03 04:21:15 PM PDT 24
Finished Jul 03 04:21:49 PM PDT 24
Peak memory 211976 kb
Host smart-be09e88d-f6ad-4bfb-bdf9-356cc10859c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542674201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2542674201
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1089003583
Short name T371
Test name
Test status
Simulation time 2570829402 ps
CPU time 22.18 seconds
Started Jul 03 04:21:14 PM PDT 24
Finished Jul 03 04:21:37 PM PDT 24
Peak memory 218896 kb
Host smart-1d6ec129-6357-4d2a-b698-1835c4633693
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089003583 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1089003583
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3246052632
Short name T440
Test name
Test status
Simulation time 7524073841 ps
CPU time 21.03 seconds
Started Jul 03 04:21:00 PM PDT 24
Finished Jul 03 04:21:21 PM PDT 24
Peak memory 212184 kb
Host smart-c81ef5f2-24f6-4271-b10c-c5890a66cd11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246052632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3246052632
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.901579877
Short name T426
Test name
Test status
Simulation time 360405552 ps
CPU time 8.36 seconds
Started Jul 03 04:20:36 PM PDT 24
Finished Jul 03 04:20:44 PM PDT 24
Peak memory 210452 kb
Host smart-3a6c459d-2fb1-4e71-8edc-c42eead97dca
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901579877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.901579877
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1537412556
Short name T449
Test name
Test status
Simulation time 2221837541 ps
CPU time 21.39 seconds
Started Jul 03 04:20:34 PM PDT 24
Finished Jul 03 04:20:55 PM PDT 24
Peak memory 210472 kb
Host smart-2fa00a96-075e-401f-8561-60442fe8c2f4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537412556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1537412556
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.4179199050
Short name T415
Test name
Test status
Simulation time 156688525071 ps
CPU time 121.16 seconds
Started Jul 03 04:20:42 PM PDT 24
Finished Jul 03 04:22:44 PM PDT 24
Peak memory 213812 kb
Host smart-fa8a527f-5402-4c84-9482-175ead938cad
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179199050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.4179199050
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1432060766
Short name T444
Test name
Test status
Simulation time 4128311238 ps
CPU time 16.2 seconds
Started Jul 03 04:20:46 PM PDT 24
Finished Jul 03 04:21:02 PM PDT 24
Peak memory 211124 kb
Host smart-56db603c-7040-4184-8443-422cf84ba897
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432060766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1432060766
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.430753602
Short name T373
Test name
Test status
Simulation time 3394243458 ps
CPU time 32.05 seconds
Started Jul 03 04:20:17 PM PDT 24
Finished Jul 03 04:20:49 PM PDT 24
Peak memory 218100 kb
Host smart-556c6cc6-bd53-4aed-a67e-cd1336e43880
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430753602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.430753602
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3497228190
Short name T64
Test name
Test status
Simulation time 38947805927 ps
CPU time 100.62 seconds
Started Jul 03 04:21:07 PM PDT 24
Finished Jul 03 04:22:49 PM PDT 24
Peak memory 213136 kb
Host smart-e2680c39-36c9-4404-9496-04389c89c439
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497228190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3497228190
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2365902032
Short name T414
Test name
Test status
Simulation time 718555905 ps
CPU time 8.39 seconds
Started Jul 03 04:21:56 PM PDT 24
Finished Jul 03 04:22:04 PM PDT 24
Peak memory 216416 kb
Host smart-49b9f418-6417-46ea-8ab8-713384dff266
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365902032 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2365902032
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1036202342
Short name T97
Test name
Test status
Simulation time 3042761118 ps
CPU time 24.48 seconds
Started Jul 03 04:21:16 PM PDT 24
Finished Jul 03 04:21:41 PM PDT 24
Peak memory 210908 kb
Host smart-302e78f3-4126-4f60-932f-da0fed630976
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036202342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1036202342
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.894270969
Short name T403
Test name
Test status
Simulation time 2387586978 ps
CPU time 36.86 seconds
Started Jul 03 04:21:53 PM PDT 24
Finished Jul 03 04:22:31 PM PDT 24
Peak memory 213732 kb
Host smart-fb4b90ac-77c7-4594-8438-504bb5970fd8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894270969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.894270969
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.129155027
Short name T447
Test name
Test status
Simulation time 338320522 ps
CPU time 8.01 seconds
Started Jul 03 04:21:13 PM PDT 24
Finished Jul 03 04:21:21 PM PDT 24
Peak memory 211268 kb
Host smart-37ef8149-8f4b-4903-9c19-62b9c23226de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129155027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.129155027
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2556688535
Short name T370
Test name
Test status
Simulation time 4279699297 ps
CPU time 18.15 seconds
Started Jul 03 04:22:55 PM PDT 24
Finished Jul 03 04:23:14 PM PDT 24
Peak memory 217064 kb
Host smart-5e7da8d5-b3ec-42b3-b0dd-759203c89751
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556688535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2556688535
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3269964602
Short name T120
Test name
Test status
Simulation time 5191050142 ps
CPU time 161.08 seconds
Started Jul 03 04:22:52 PM PDT 24
Finished Jul 03 04:25:34 PM PDT 24
Peak memory 213232 kb
Host smart-a115bb88-4bea-4f37-92cc-148983ceafdf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269964602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3269964602
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1687024636
Short name T441
Test name
Test status
Simulation time 4290887998 ps
CPU time 31.99 seconds
Started Jul 03 04:21:54 PM PDT 24
Finished Jul 03 04:22:27 PM PDT 24
Peak memory 217076 kb
Host smart-8cb66b18-4f22-4763-a9e7-7cbb541d2508
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687024636 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1687024636
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4135684306
Short name T104
Test name
Test status
Simulation time 4086368731 ps
CPU time 34.13 seconds
Started Jul 03 04:21:46 PM PDT 24
Finished Jul 03 04:22:20 PM PDT 24
Peak memory 211812 kb
Host smart-c3403f50-c738-4abb-9112-bd98dbecc036
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135684306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.4135684306
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.345095590
Short name T93
Test name
Test status
Simulation time 7938078302 ps
CPU time 56.43 seconds
Started Jul 03 04:21:15 PM PDT 24
Finished Jul 03 04:22:11 PM PDT 24
Peak memory 215216 kb
Host smart-73236478-7390-4f13-beb6-4e079a23d08f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345095590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.345095590
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.570745448
Short name T418
Test name
Test status
Simulation time 3613854849 ps
CPU time 31.24 seconds
Started Jul 03 04:21:17 PM PDT 24
Finished Jul 03 04:21:49 PM PDT 24
Peak memory 212172 kb
Host smart-f8ca3526-994b-4a82-a6f2-413d59123e17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570745448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.570745448
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1018864196
Short name T380
Test name
Test status
Simulation time 167472094 ps
CPU time 12.65 seconds
Started Jul 03 04:21:39 PM PDT 24
Finished Jul 03 04:21:53 PM PDT 24
Peak memory 217268 kb
Host smart-bd9cdd9a-b1f7-4d43-bb69-975ebb117474
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018864196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1018864196
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2262585160
Short name T369
Test name
Test status
Simulation time 1388677351 ps
CPU time 8.41 seconds
Started Jul 03 04:23:09 PM PDT 24
Finished Jul 03 04:23:19 PM PDT 24
Peak memory 216220 kb
Host smart-32afca97-26c6-47ec-9960-58ae5f904dd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262585160 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2262585160
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2212277554
Short name T383
Test name
Test status
Simulation time 176346229 ps
CPU time 8.29 seconds
Started Jul 03 04:21:37 PM PDT 24
Finished Jul 03 04:21:46 PM PDT 24
Peak memory 210528 kb
Host smart-90eae49e-d303-4ee1-8aa0-39c1d27e5d98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212277554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2212277554
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1783934132
Short name T453
Test name
Test status
Simulation time 8421431093 ps
CPU time 67.46 seconds
Started Jul 03 04:21:56 PM PDT 24
Finished Jul 03 04:23:04 PM PDT 24
Peak memory 214020 kb
Host smart-3674b7f6-1cb0-40b9-a553-e76a67848950
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783934132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1783934132
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2334683919
Short name T432
Test name
Test status
Simulation time 13201682516 ps
CPU time 32.56 seconds
Started Jul 03 04:21:29 PM PDT 24
Finished Jul 03 04:22:02 PM PDT 24
Peak memory 212660 kb
Host smart-acbfbc25-a166-4f8f-ba45-fa468e019922
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334683919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2334683919
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2706827000
Short name T406
Test name
Test status
Simulation time 2160513549 ps
CPU time 25.28 seconds
Started Jul 03 04:21:39 PM PDT 24
Finished Jul 03 04:22:05 PM PDT 24
Peak memory 218460 kb
Host smart-c0521995-d1f8-4628-9a22-1601f9c84c4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706827000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2706827000
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1918576422
Short name T121
Test name
Test status
Simulation time 15024458509 ps
CPU time 162.54 seconds
Started Jul 03 04:21:51 PM PDT 24
Finished Jul 03 04:24:34 PM PDT 24
Peak memory 214132 kb
Host smart-87e12324-56ca-42b0-aef4-5e78b6471a4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918576422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1918576422
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1486694967
Short name T389
Test name
Test status
Simulation time 2169295574 ps
CPU time 11.85 seconds
Started Jul 03 04:21:36 PM PDT 24
Finished Jul 03 04:21:49 PM PDT 24
Peak memory 213852 kb
Host smart-3e093073-0dc8-41c6-942e-27b1c4d5dd2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486694967 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1486694967
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3971536420
Short name T90
Test name
Test status
Simulation time 18613788684 ps
CPU time 22.88 seconds
Started Jul 03 04:21:57 PM PDT 24
Finished Jul 03 04:22:21 PM PDT 24
Peak memory 211596 kb
Host smart-d614c250-77ae-476d-864f-9b82ccaf47b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971536420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3971536420
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.974921356
Short name T439
Test name
Test status
Simulation time 4144531465 ps
CPU time 55.93 seconds
Started Jul 03 04:22:01 PM PDT 24
Finished Jul 03 04:22:58 PM PDT 24
Peak memory 214240 kb
Host smart-0e2eaf82-9ed3-4ad1-93d7-4107f8726ad5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974921356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.974921356
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3441865085
Short name T100
Test name
Test status
Simulation time 2946826577 ps
CPU time 25.63 seconds
Started Jul 03 04:21:17 PM PDT 24
Finished Jul 03 04:21:43 PM PDT 24
Peak memory 211868 kb
Host smart-c7fce387-8e10-4729-bf42-7f41e778206a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441865085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3441865085
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3318762141
Short name T413
Test name
Test status
Simulation time 1321142516 ps
CPU time 13.28 seconds
Started Jul 03 04:21:57 PM PDT 24
Finished Jul 03 04:22:11 PM PDT 24
Peak memory 218160 kb
Host smart-a55ee7d7-fcc5-434a-b83c-f4bdcf96e8c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318762141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3318762141
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2416700700
Short name T451
Test name
Test status
Simulation time 5297350006 ps
CPU time 89.6 seconds
Started Jul 03 04:21:15 PM PDT 24
Finished Jul 03 04:22:45 PM PDT 24
Peak memory 213624 kb
Host smart-f925fd36-2880-4f72-8fda-8456a455086a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416700700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2416700700
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3189454753
Short name T393
Test name
Test status
Simulation time 44438185886 ps
CPU time 24.25 seconds
Started Jul 03 04:21:19 PM PDT 24
Finished Jul 03 04:21:44 PM PDT 24
Peak memory 217764 kb
Host smart-e82de14b-9168-48ce-8d93-9e782e7a0302
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189454753 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3189454753
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2523694422
Short name T77
Test name
Test status
Simulation time 2632776839 ps
CPU time 12.5 seconds
Started Jul 03 04:21:30 PM PDT 24
Finished Jul 03 04:21:43 PM PDT 24
Peak memory 211708 kb
Host smart-8de26e0a-cc3c-49a4-965f-929b7777068a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523694422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2523694422
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2030872237
Short name T76
Test name
Test status
Simulation time 63127563575 ps
CPU time 153.52 seconds
Started Jul 03 04:21:17 PM PDT 24
Finished Jul 03 04:23:51 PM PDT 24
Peak memory 214740 kb
Host smart-28546f6b-2680-4428-8ff2-04be269cc984
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030872237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2030872237
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1042151126
Short name T409
Test name
Test status
Simulation time 10722762012 ps
CPU time 14.84 seconds
Started Jul 03 04:23:04 PM PDT 24
Finished Jul 03 04:23:20 PM PDT 24
Peak memory 212184 kb
Host smart-5b2c30b3-2970-47fd-8d00-d3622a34d7ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042151126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1042151126
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1836541307
Short name T391
Test name
Test status
Simulation time 6136333413 ps
CPU time 21.63 seconds
Started Jul 03 04:21:37 PM PDT 24
Finished Jul 03 04:21:59 PM PDT 24
Peak memory 218568 kb
Host smart-9068371e-7e3a-4e50-931e-5ecd62d7911e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836541307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1836541307
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1085706838
Short name T401
Test name
Test status
Simulation time 3211722196 ps
CPU time 12.94 seconds
Started Jul 03 04:21:18 PM PDT 24
Finished Jul 03 04:21:32 PM PDT 24
Peak memory 216300 kb
Host smart-3ba91109-be34-4b69-ba7d-304dd00f8913
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085706838 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1085706838
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2410798305
Short name T92
Test name
Test status
Simulation time 18581199954 ps
CPU time 30.02 seconds
Started Jul 03 04:22:57 PM PDT 24
Finished Jul 03 04:23:27 PM PDT 24
Peak memory 211668 kb
Host smart-c2f327fd-aa2e-483e-8c4f-00424b602dd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410798305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2410798305
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1351717470
Short name T96
Test name
Test status
Simulation time 13462331516 ps
CPU time 79.96 seconds
Started Jul 03 04:21:22 PM PDT 24
Finished Jul 03 04:22:43 PM PDT 24
Peak memory 214060 kb
Host smart-781939bd-0954-45d1-9164-4c9de4fbba02
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351717470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1351717470
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1718174762
Short name T66
Test name
Test status
Simulation time 2046850681 ps
CPU time 21.38 seconds
Started Jul 03 04:21:21 PM PDT 24
Finished Jul 03 04:21:43 PM PDT 24
Peak memory 212036 kb
Host smart-467aa51b-79b0-4ae7-a723-2afa2f3f34c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718174762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1718174762
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.609585746
Short name T378
Test name
Test status
Simulation time 3446103560 ps
CPU time 21.41 seconds
Started Jul 03 04:23:15 PM PDT 24
Finished Jul 03 04:23:37 PM PDT 24
Peak memory 217176 kb
Host smart-5bec1e4e-8d3b-4b72-b72a-ba8c43c08d8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609585746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.609585746
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3491799297
Short name T112
Test name
Test status
Simulation time 822558904 ps
CPU time 154.5 seconds
Started Jul 03 04:22:58 PM PDT 24
Finished Jul 03 04:25:34 PM PDT 24
Peak memory 212712 kb
Host smart-4659fc96-868c-47b5-ac32-56c237293262
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491799297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3491799297
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.501396141
Short name T428
Test name
Test status
Simulation time 39076822961 ps
CPU time 34.73 seconds
Started Jul 03 04:21:32 PM PDT 24
Finished Jul 03 04:22:07 PM PDT 24
Peak memory 218748 kb
Host smart-d844444f-20e7-4cd0-9334-7ffefe0d9a49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501396141 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.501396141
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.183371899
Short name T435
Test name
Test status
Simulation time 15773479776 ps
CPU time 31.59 seconds
Started Jul 03 04:21:31 PM PDT 24
Finished Jul 03 04:22:02 PM PDT 24
Peak memory 211736 kb
Host smart-9189b8f5-0f1a-442c-abbe-3b863d317a5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183371899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.183371899
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.4123577719
Short name T105
Test name
Test status
Simulation time 8518703646 ps
CPU time 87.42 seconds
Started Jul 03 04:23:00 PM PDT 24
Finished Jul 03 04:24:31 PM PDT 24
Peak memory 212208 kb
Host smart-f01c5634-7702-484f-8444-744aa8ed2045
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123577719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.4123577719
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2208051395
Short name T416
Test name
Test status
Simulation time 3022818811 ps
CPU time 17.9 seconds
Started Jul 03 04:21:22 PM PDT 24
Finished Jul 03 04:21:40 PM PDT 24
Peak memory 212260 kb
Host smart-688f8326-51f9-4ece-a22f-86f5d1e3986c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208051395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2208051395
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2889133340
Short name T397
Test name
Test status
Simulation time 8245197030 ps
CPU time 24.94 seconds
Started Jul 03 04:23:08 PM PDT 24
Finished Jul 03 04:23:34 PM PDT 24
Peak memory 217396 kb
Host smart-b0005bec-c678-4dc8-bc0e-d021f9f3898f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889133340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2889133340
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.931358968
Short name T62
Test name
Test status
Simulation time 8509569448 ps
CPU time 160.77 seconds
Started Jul 03 04:21:21 PM PDT 24
Finished Jul 03 04:24:03 PM PDT 24
Peak memory 214544 kb
Host smart-15561670-a547-4c4b-aa8c-936ba2929a95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931358968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.931358968
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.559677100
Short name T396
Test name
Test status
Simulation time 7577011145 ps
CPU time 33.33 seconds
Started Jul 03 04:21:37 PM PDT 24
Finished Jul 03 04:22:11 PM PDT 24
Peak memory 218528 kb
Host smart-ccb53d34-5e7f-42f0-b30b-12abebae9695
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559677100 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.559677100
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1107470327
Short name T89
Test name
Test status
Simulation time 14019524651 ps
CPU time 27.61 seconds
Started Jul 03 04:21:31 PM PDT 24
Finished Jul 03 04:21:59 PM PDT 24
Peak memory 211452 kb
Host smart-374cf70d-244c-48c0-8fc9-416caeab2741
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107470327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1107470327
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4249306873
Short name T94
Test name
Test status
Simulation time 11024915547 ps
CPU time 68.97 seconds
Started Jul 03 04:21:40 PM PDT 24
Finished Jul 03 04:22:50 PM PDT 24
Peak memory 214056 kb
Host smart-fe7bd55b-5272-4c0d-90d8-d0de9f9f738f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249306873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.4249306873
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3714202887
Short name T436
Test name
Test status
Simulation time 5922133199 ps
CPU time 17.72 seconds
Started Jul 03 04:21:36 PM PDT 24
Finished Jul 03 04:22:00 PM PDT 24
Peak memory 212672 kb
Host smart-c4b7e444-292c-414b-b781-9a1ce4faec0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714202887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3714202887
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3355928398
Short name T433
Test name
Test status
Simulation time 8175860983 ps
CPU time 31.43 seconds
Started Jul 03 04:21:21 PM PDT 24
Finished Jul 03 04:21:53 PM PDT 24
Peak memory 217620 kb
Host smart-23090c4a-c98f-4689-8d2d-abf3c1441bfc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355928398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3355928398
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1411548874
Short name T430
Test name
Test status
Simulation time 21875952088 ps
CPU time 96.9 seconds
Started Jul 03 04:21:32 PM PDT 24
Finished Jul 03 04:23:09 PM PDT 24
Peak memory 218848 kb
Host smart-47b13d0d-53d4-48c6-b18e-04d99bb5ec16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411548874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1411548874
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.186719814
Short name T374
Test name
Test status
Simulation time 180647884 ps
CPU time 9.09 seconds
Started Jul 03 04:21:36 PM PDT 24
Finished Jul 03 04:21:46 PM PDT 24
Peak memory 217408 kb
Host smart-05705c41-480e-4a57-9b98-ab8d5364596f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186719814 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.186719814
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3175925265
Short name T67
Test name
Test status
Simulation time 4643550310 ps
CPU time 21.5 seconds
Started Jul 03 04:21:37 PM PDT 24
Finished Jul 03 04:21:59 PM PDT 24
Peak memory 210580 kb
Host smart-7279c482-4708-4f09-91ae-2e618ef01cc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175925265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3175925265
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3828936711
Short name T95
Test name
Test status
Simulation time 8817801942 ps
CPU time 92.31 seconds
Started Jul 03 04:21:38 PM PDT 24
Finished Jul 03 04:23:11 PM PDT 24
Peak memory 214060 kb
Host smart-28fdeed0-5aed-4268-a5b1-257fafdfd877
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828936711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3828936711
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2214881034
Short name T442
Test name
Test status
Simulation time 2568162217 ps
CPU time 22.27 seconds
Started Jul 03 04:22:55 PM PDT 24
Finished Jul 03 04:23:18 PM PDT 24
Peak memory 211472 kb
Host smart-2a86d684-48dc-427a-8368-6864b6124881
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214881034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2214881034
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1492077376
Short name T365
Test name
Test status
Simulation time 4771783319 ps
CPU time 20.2 seconds
Started Jul 03 04:23:00 PM PDT 24
Finished Jul 03 04:23:24 PM PDT 24
Peak memory 217356 kb
Host smart-77967c63-440e-4a51-9928-2543d08895fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492077376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1492077376
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.228491816
Short name T119
Test name
Test status
Simulation time 3415541563 ps
CPU time 167.31 seconds
Started Jul 03 04:23:00 PM PDT 24
Finished Jul 03 04:25:51 PM PDT 24
Peak memory 213184 kb
Host smart-b7a08cd4-644e-4d38-8de1-f49a8bff118b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228491816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.228491816
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.765522368
Short name T458
Test name
Test status
Simulation time 9804218188 ps
CPU time 25.84 seconds
Started Jul 03 04:22:06 PM PDT 24
Finished Jul 03 04:22:32 PM PDT 24
Peak memory 216448 kb
Host smart-5cf1f6ef-042f-48e9-a261-6e9c7113fe3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765522368 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.765522368
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3582837053
Short name T410
Test name
Test status
Simulation time 896909543 ps
CPU time 13.28 seconds
Started Jul 03 04:23:09 PM PDT 24
Finished Jul 03 04:23:23 PM PDT 24
Peak memory 210236 kb
Host smart-5f6e5383-12be-42fb-bd84-7a364a38032a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582837053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3582837053
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.555320396
Short name T375
Test name
Test status
Simulation time 23846214407 ps
CPU time 102.83 seconds
Started Jul 03 04:23:00 PM PDT 24
Finished Jul 03 04:24:46 PM PDT 24
Peak memory 213060 kb
Host smart-5c5e8385-193a-45f5-aa38-233bbed34253
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555320396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.555320396
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1152715488
Short name T429
Test name
Test status
Simulation time 6753088797 ps
CPU time 31.94 seconds
Started Jul 03 04:22:05 PM PDT 24
Finished Jul 03 04:22:37 PM PDT 24
Peak memory 212376 kb
Host smart-28182a26-ea2b-4209-9d17-02c49200b4ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152715488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1152715488
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3084083766
Short name T372
Test name
Test status
Simulation time 3122602301 ps
CPU time 20.13 seconds
Started Jul 03 04:23:09 PM PDT 24
Finished Jul 03 04:23:31 PM PDT 24
Peak memory 218256 kb
Host smart-5ec48f56-101e-4a64-81a3-033fbbcf36f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084083766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3084083766
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.261835445
Short name T113
Test name
Test status
Simulation time 925955689 ps
CPU time 80.33 seconds
Started Jul 03 04:21:36 PM PDT 24
Finished Jul 03 04:22:56 PM PDT 24
Peak memory 213368 kb
Host smart-7fbca526-23d8-4d8c-940c-5aae61112c36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261835445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.261835445
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.510568781
Short name T421
Test name
Test status
Simulation time 9563856063 ps
CPU time 21.95 seconds
Started Jul 03 04:20:48 PM PDT 24
Finished Jul 03 04:21:11 PM PDT 24
Peak memory 209812 kb
Host smart-3e80faf4-62f1-4ef6-b46a-16996d664f04
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510568781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.510568781
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.752393569
Short name T452
Test name
Test status
Simulation time 16637716135 ps
CPU time 32.09 seconds
Started Jul 03 04:20:28 PM PDT 24
Finished Jul 03 04:21:01 PM PDT 24
Peak memory 211340 kb
Host smart-94ec3110-67df-41c9-9f3a-b472512d74f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752393569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.752393569
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1592866330
Short name T411
Test name
Test status
Simulation time 6119631283 ps
CPU time 21.75 seconds
Started Jul 03 04:21:05 PM PDT 24
Finished Jul 03 04:21:27 PM PDT 24
Peak memory 211744 kb
Host smart-834422c2-a2cf-4ea3-a7bf-80ab4444a8aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592866330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1592866330
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1580351041
Short name T424
Test name
Test status
Simulation time 438011088 ps
CPU time 11.03 seconds
Started Jul 03 04:20:51 PM PDT 24
Finished Jul 03 04:21:03 PM PDT 24
Peak memory 214504 kb
Host smart-db5a7195-7afd-4089-83a7-58f2d1323776
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580351041 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1580351041
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3340044797
Short name T459
Test name
Test status
Simulation time 10825119125 ps
CPU time 27.32 seconds
Started Jul 03 04:20:50 PM PDT 24
Finished Jul 03 04:21:19 PM PDT 24
Peak memory 211128 kb
Host smart-9b6269ca-56d8-486b-adb9-14b8391ec916
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340044797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3340044797
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2420509167
Short name T404
Test name
Test status
Simulation time 170836358 ps
CPU time 7.99 seconds
Started Jul 03 04:21:05 PM PDT 24
Finished Jul 03 04:21:13 PM PDT 24
Peak memory 210384 kb
Host smart-3ea2153b-1a9e-4403-9661-8c18549b19b2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420509167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2420509167
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.226995803
Short name T395
Test name
Test status
Simulation time 688462775 ps
CPU time 8.17 seconds
Started Jul 03 04:20:44 PM PDT 24
Finished Jul 03 04:20:53 PM PDT 24
Peak memory 210448 kb
Host smart-ff56d7a2-2874-4a07-9249-831b105c151d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226995803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
226995803
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2323398348
Short name T106
Test name
Test status
Simulation time 27638879330 ps
CPU time 70.59 seconds
Started Jul 03 04:20:48 PM PDT 24
Finished Jul 03 04:21:59 PM PDT 24
Peak memory 211812 kb
Host smart-9da49897-0d88-4afb-9a59-cfdb17440bf3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323398348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2323398348
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2645081221
Short name T102
Test name
Test status
Simulation time 2634583247 ps
CPU time 12.74 seconds
Started Jul 03 04:21:03 PM PDT 24
Finished Jul 03 04:21:16 PM PDT 24
Peak memory 211196 kb
Host smart-f3868d26-4240-4efc-8298-c98be06959d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645081221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2645081221
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.136113874
Short name T382
Test name
Test status
Simulation time 751452649 ps
CPU time 10.63 seconds
Started Jul 03 04:21:05 PM PDT 24
Finished Jul 03 04:21:16 PM PDT 24
Peak memory 216464 kb
Host smart-a4f848ca-beb3-44f2-808c-766f97a31ed8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136113874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.136113874
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4083846359
Short name T417
Test name
Test status
Simulation time 17019042424 ps
CPU time 98.82 seconds
Started Jul 03 04:20:51 PM PDT 24
Finished Jul 03 04:22:30 PM PDT 24
Peak memory 212892 kb
Host smart-8536ffb9-91b8-49ac-a0c2-27868dd9ea0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083846359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.4083846359
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.484758529
Short name T81
Test name
Test status
Simulation time 4115793210 ps
CPU time 17.15 seconds
Started Jul 03 04:21:03 PM PDT 24
Finished Jul 03 04:21:21 PM PDT 24
Peak memory 209912 kb
Host smart-454f8c15-6b74-4221-8721-6578fb3d6d12
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484758529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.484758529
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2606108357
Short name T394
Test name
Test status
Simulation time 14711227263 ps
CPU time 29.96 seconds
Started Jul 03 04:21:35 PM PDT 24
Finished Jul 03 04:22:05 PM PDT 24
Peak memory 211724 kb
Host smart-6a480ac5-32a8-4463-b804-ef94571a2943
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606108357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2606108357
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.840374850
Short name T376
Test name
Test status
Simulation time 9468045664 ps
CPU time 34.77 seconds
Started Jul 03 04:21:27 PM PDT 24
Finished Jul 03 04:22:02 PM PDT 24
Peak memory 211388 kb
Host smart-fc4ff981-4ef1-4534-ae2a-d11360ad7247
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840374850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.840374850
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3414617532
Short name T405
Test name
Test status
Simulation time 29219078749 ps
CPU time 26.9 seconds
Started Jul 03 04:21:05 PM PDT 24
Finished Jul 03 04:21:32 PM PDT 24
Peak memory 217456 kb
Host smart-5501ad26-1323-4650-90f1-822a9473ea56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414617532 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3414617532
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.339901455
Short name T73
Test name
Test status
Simulation time 7012970192 ps
CPU time 28.61 seconds
Started Jul 03 04:22:30 PM PDT 24
Finished Jul 03 04:22:59 PM PDT 24
Peak memory 212256 kb
Host smart-0e0460cf-6e5e-404f-b05b-d8799ce2bd30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339901455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.339901455
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1438765728
Short name T386
Test name
Test status
Simulation time 3276721855 ps
CPU time 17.99 seconds
Started Jul 03 04:21:12 PM PDT 24
Finished Jul 03 04:21:30 PM PDT 24
Peak memory 209780 kb
Host smart-7c10018c-9262-42e3-a0d9-a1fd0265cff9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438765728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1438765728
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.753546631
Short name T422
Test name
Test status
Simulation time 3080409619 ps
CPU time 13.08 seconds
Started Jul 03 04:22:58 PM PDT 24
Finished Jul 03 04:23:12 PM PDT 24
Peak memory 209236 kb
Host smart-c9556e25-da8d-4f1a-8af4-6924dc852f63
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753546631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
753546631
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1331946613
Short name T80
Test name
Test status
Simulation time 42066506076 ps
CPU time 142.93 seconds
Started Jul 03 04:21:03 PM PDT 24
Finished Jul 03 04:23:27 PM PDT 24
Peak memory 211668 kb
Host smart-e0016442-0016-48c4-bb97-52fff4c77b99
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331946613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1331946613
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.430229443
Short name T455
Test name
Test status
Simulation time 14118524360 ps
CPU time 26.44 seconds
Started Jul 03 04:20:57 PM PDT 24
Finished Jul 03 04:21:24 PM PDT 24
Peak memory 212708 kb
Host smart-95b35c0d-cb59-4520-be69-e578a84cc77a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430229443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.430229443
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2492089767
Short name T392
Test name
Test status
Simulation time 1679648894 ps
CPU time 21.26 seconds
Started Jul 03 04:20:48 PM PDT 24
Finished Jul 03 04:21:10 PM PDT 24
Peak memory 217320 kb
Host smart-ae60c5a8-f623-47f4-adcd-29a636dec40d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492089767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2492089767
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1092953625
Short name T91
Test name
Test status
Simulation time 12940932248 ps
CPU time 25.2 seconds
Started Jul 03 04:23:01 PM PDT 24
Finished Jul 03 04:23:29 PM PDT 24
Peak memory 211600 kb
Host smart-90ce197c-2caa-4997-84e8-9574e9d2fc62
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092953625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1092953625
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3357568263
Short name T431
Test name
Test status
Simulation time 1092647176 ps
CPU time 14.87 seconds
Started Jul 03 04:21:18 PM PDT 24
Finished Jul 03 04:21:33 PM PDT 24
Peak memory 210364 kb
Host smart-b27d45d9-b2d2-4b4c-b527-12fcdf7cb91b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357568263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3357568263
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.460044420
Short name T398
Test name
Test status
Simulation time 2243332144 ps
CPU time 29.44 seconds
Started Jul 03 04:22:10 PM PDT 24
Finished Jul 03 04:22:40 PM PDT 24
Peak memory 211556 kb
Host smart-09b87719-1a66-4bc7-8fed-541edf1e0f09
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460044420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.460044420
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4020690139
Short name T388
Test name
Test status
Simulation time 7164235645 ps
CPU time 21.19 seconds
Started Jul 03 04:23:01 PM PDT 24
Finished Jul 03 04:23:25 PM PDT 24
Peak memory 217468 kb
Host smart-905a5fff-4e90-49d5-97ed-1dfa83c686bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020690139 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.4020690139
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2259455579
Short name T400
Test name
Test status
Simulation time 70912701903 ps
CPU time 33.26 seconds
Started Jul 03 04:22:55 PM PDT 24
Finished Jul 03 04:23:29 PM PDT 24
Peak memory 211848 kb
Host smart-150bb117-a545-40ce-b792-4d080056a287
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259455579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2259455579
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2336128583
Short name T368
Test name
Test status
Simulation time 3343542268 ps
CPU time 27.99 seconds
Started Jul 03 04:21:14 PM PDT 24
Finished Jul 03 04:21:43 PM PDT 24
Peak memory 210528 kb
Host smart-da69efba-ab74-4999-8290-deea01e2ef45
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336128583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2336128583
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2016695772
Short name T402
Test name
Test status
Simulation time 688712572 ps
CPU time 8.17 seconds
Started Jul 03 04:21:13 PM PDT 24
Finished Jul 03 04:21:22 PM PDT 24
Peak memory 210148 kb
Host smart-05c2c583-5312-4d69-baa6-4def93c1119b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016695772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2016695772
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2991352241
Short name T107
Test name
Test status
Simulation time 3236683407 ps
CPU time 65.65 seconds
Started Jul 03 04:21:14 PM PDT 24
Finished Jul 03 04:22:20 PM PDT 24
Peak memory 215256 kb
Host smart-d8653ecb-db45-4171-be96-2edc08d6c229
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991352241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2991352241
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2389196665
Short name T450
Test name
Test status
Simulation time 2225064032 ps
CPU time 22.24 seconds
Started Jul 03 04:21:33 PM PDT 24
Finished Jul 03 04:21:55 PM PDT 24
Peak memory 211948 kb
Host smart-12a025ca-3cdf-4f5e-ad0c-d6e8d705893d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389196665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2389196665
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1100887225
Short name T445
Test name
Test status
Simulation time 429255579 ps
CPU time 15.72 seconds
Started Jul 03 04:22:31 PM PDT 24
Finished Jul 03 04:22:47 PM PDT 24
Peak memory 217332 kb
Host smart-195aba8f-c865-4570-8b55-bb677d0a25bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100887225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1100887225
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2330113391
Short name T387
Test name
Test status
Simulation time 8234545771 ps
CPU time 29.48 seconds
Started Jul 03 04:22:53 PM PDT 24
Finished Jul 03 04:23:23 PM PDT 24
Peak memory 215040 kb
Host smart-2eb85344-da02-4d8c-ab2c-01be12577163
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330113391 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2330113391
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.47916902
Short name T412
Test name
Test status
Simulation time 2736481467 ps
CPU time 12.57 seconds
Started Jul 03 04:21:52 PM PDT 24
Finished Jul 03 04:22:05 PM PDT 24
Peak memory 210556 kb
Host smart-e303e6f9-f0ad-41a0-8b37-ed01c549e694
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47916902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.47916902
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.300987227
Short name T79
Test name
Test status
Simulation time 65198457697 ps
CPU time 148.94 seconds
Started Jul 03 04:22:55 PM PDT 24
Finished Jul 03 04:25:25 PM PDT 24
Peak memory 213928 kb
Host smart-859395e3-493f-44d3-b2db-d7856bb5fb97
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300987227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.300987227
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3611227643
Short name T427
Test name
Test status
Simulation time 2708272573 ps
CPU time 23.9 seconds
Started Jul 03 04:21:52 PM PDT 24
Finished Jul 03 04:22:17 PM PDT 24
Peak memory 212256 kb
Host smart-47bedc10-eb87-492e-b9e0-3c4a97de4334
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611227643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3611227643
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3866618453
Short name T407
Test name
Test status
Simulation time 3602664923 ps
CPU time 23.21 seconds
Started Jul 03 04:22:53 PM PDT 24
Finished Jul 03 04:23:17 PM PDT 24
Peak memory 216960 kb
Host smart-51f8e527-7020-4df5-b825-0372b323a17f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866618453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3866618453
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3495097737
Short name T111
Test name
Test status
Simulation time 1987113188 ps
CPU time 166.11 seconds
Started Jul 03 04:21:08 PM PDT 24
Finished Jul 03 04:23:55 PM PDT 24
Peak memory 213824 kb
Host smart-ba2e6281-3be6-4628-a1f8-29705c2aeddb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495097737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3495097737
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1529656232
Short name T448
Test name
Test status
Simulation time 766924121 ps
CPU time 8.09 seconds
Started Jul 03 04:23:09 PM PDT 24
Finished Jul 03 04:23:19 PM PDT 24
Peak memory 213708 kb
Host smart-cbab2aff-b81e-407a-a8ae-3608205b45af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529656232 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1529656232
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.198581303
Short name T366
Test name
Test status
Simulation time 17699484351 ps
CPU time 14.91 seconds
Started Jul 03 04:23:02 PM PDT 24
Finished Jul 03 04:23:20 PM PDT 24
Peak memory 210720 kb
Host smart-8c39e0a5-053c-46ac-b307-470958fadc37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198581303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.198581303
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3855802718
Short name T78
Test name
Test status
Simulation time 2855305389 ps
CPU time 36.43 seconds
Started Jul 03 04:23:01 PM PDT 24
Finished Jul 03 04:23:40 PM PDT 24
Peak memory 214572 kb
Host smart-bd679606-7f6c-4079-879c-6a75ddb95fd8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855802718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3855802718
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1255220867
Short name T103
Test name
Test status
Simulation time 2873635741 ps
CPU time 27.95 seconds
Started Jul 03 04:21:44 PM PDT 24
Finished Jul 03 04:22:13 PM PDT 24
Peak memory 211524 kb
Host smart-9cf92b35-5b7e-46d3-a0ca-3bf98e7e85c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255220867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1255220867
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2955722085
Short name T461
Test name
Test status
Simulation time 8525873227 ps
CPU time 27.26 seconds
Started Jul 03 04:21:00 PM PDT 24
Finished Jul 03 04:21:28 PM PDT 24
Peak memory 218712 kb
Host smart-f34a091b-4604-480c-85b0-b9033e89922f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955722085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2955722085
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3865144291
Short name T109
Test name
Test status
Simulation time 2954101409 ps
CPU time 147.73 seconds
Started Jul 03 04:22:55 PM PDT 24
Finished Jul 03 04:25:24 PM PDT 24
Peak memory 218244 kb
Host smart-13f442f2-e7ef-40d3-8d74-8809c5ecb2f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865144291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3865144291
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.859159039
Short name T367
Test name
Test status
Simulation time 189139069 ps
CPU time 10.31 seconds
Started Jul 03 04:22:23 PM PDT 24
Finished Jul 03 04:22:34 PM PDT 24
Peak memory 217368 kb
Host smart-7114461f-920c-41fc-a6b1-86d8a644ad82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859159039 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.859159039
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.733882414
Short name T99
Test name
Test status
Simulation time 3796608994 ps
CPU time 30.96 seconds
Started Jul 03 04:21:48 PM PDT 24
Finished Jul 03 04:22:20 PM PDT 24
Peak memory 211620 kb
Host smart-9b6ef7d3-09f1-4a28-bade-960848417e5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733882414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.733882414
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3094554343
Short name T377
Test name
Test status
Simulation time 25970779253 ps
CPU time 202.47 seconds
Started Jul 03 04:23:09 PM PDT 24
Finished Jul 03 04:26:32 PM PDT 24
Peak memory 214780 kb
Host smart-2141fac2-b174-494a-9ae2-bc6a4cc6f08e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094554343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3094554343
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3542614619
Short name T101
Test name
Test status
Simulation time 55902731740 ps
CPU time 31.14 seconds
Started Jul 03 04:22:52 PM PDT 24
Finished Jul 03 04:23:24 PM PDT 24
Peak memory 211652 kb
Host smart-cc13afd9-a0ab-4820-8d19-9f8a0b97539e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542614619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3542614619
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.443768089
Short name T420
Test name
Test status
Simulation time 172508498 ps
CPU time 12.62 seconds
Started Jul 03 04:21:45 PM PDT 24
Finished Jul 03 04:21:57 PM PDT 24
Peak memory 217368 kb
Host smart-37f1ea1f-e591-40d2-a397-5bde9202b7ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443768089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.443768089
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1890051066
Short name T117
Test name
Test status
Simulation time 306706800 ps
CPU time 82.68 seconds
Started Jul 03 04:21:22 PM PDT 24
Finished Jul 03 04:22:45 PM PDT 24
Peak memory 213680 kb
Host smart-34dd0d3d-0d1a-4cbb-aa86-3cc453432ff3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890051066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1890051066
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2714458470
Short name T381
Test name
Test status
Simulation time 4891094715 ps
CPU time 24.31 seconds
Started Jul 03 04:23:09 PM PDT 24
Finished Jul 03 04:23:35 PM PDT 24
Peak memory 219052 kb
Host smart-6180acc0-9c4f-4872-8065-39fd08e47b90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714458470 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2714458470
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3215522038
Short name T419
Test name
Test status
Simulation time 7846690513 ps
CPU time 18.61 seconds
Started Jul 03 04:21:21 PM PDT 24
Finished Jul 03 04:21:40 PM PDT 24
Peak memory 210660 kb
Host smart-013e4d55-875e-4102-95d2-1d319dabc26a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215522038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3215522038
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.88659879
Short name T98
Test name
Test status
Simulation time 1237419933 ps
CPU time 15.37 seconds
Started Jul 03 04:22:53 PM PDT 24
Finished Jul 03 04:23:09 PM PDT 24
Peak memory 210748 kb
Host smart-f0a07a14-4c29-4a94-8a84-07613018ba57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88659879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctr
l_same_csr_outstanding.88659879
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.4054328257
Short name T379
Test name
Test status
Simulation time 15035952765 ps
CPU time 33.81 seconds
Started Jul 03 04:21:17 PM PDT 24
Finished Jul 03 04:21:51 PM PDT 24
Peak memory 218660 kb
Host smart-429575a9-ac69-4bce-9c6d-51c3f39440a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054328257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.4054328257
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3418812198
Short name T115
Test name
Test status
Simulation time 470610912 ps
CPU time 153.72 seconds
Started Jul 03 04:23:02 PM PDT 24
Finished Jul 03 04:25:39 PM PDT 24
Peak memory 213660 kb
Host smart-43d17eee-922e-4ff9-97a9-30fcfee7f6cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418812198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3418812198
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2804797891
Short name T390
Test name
Test status
Simulation time 2793953089 ps
CPU time 24.64 seconds
Started Jul 03 04:21:21 PM PDT 24
Finished Jul 03 04:21:46 PM PDT 24
Peak memory 216744 kb
Host smart-e735e8fc-1108-468b-a036-43c22d8bbeb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804797891 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2804797891
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1028824440
Short name T399
Test name
Test status
Simulation time 689389371 ps
CPU time 7.96 seconds
Started Jul 03 04:21:14 PM PDT 24
Finished Jul 03 04:21:23 PM PDT 24
Peak memory 210836 kb
Host smart-5a2d27ef-9b98-45ad-82ac-a0e69b8422e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028824440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1028824440
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1804723106
Short name T443
Test name
Test status
Simulation time 12052051569 ps
CPU time 119.54 seconds
Started Jul 03 04:21:13 PM PDT 24
Finished Jul 03 04:23:13 PM PDT 24
Peak memory 214900 kb
Host smart-65e27367-791b-4697-903f-1142fb02f373
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804723106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1804723106
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2628591226
Short name T456
Test name
Test status
Simulation time 2667007254 ps
CPU time 23.74 seconds
Started Jul 03 04:23:09 PM PDT 24
Finished Jul 03 04:23:34 PM PDT 24
Peak memory 211868 kb
Host smart-2932812c-5e02-45c9-b05a-e5c4536f5595
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628591226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2628591226
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1833655245
Short name T384
Test name
Test status
Simulation time 1153116790 ps
CPU time 17.93 seconds
Started Jul 03 04:22:53 PM PDT 24
Finished Jul 03 04:23:11 PM PDT 24
Peak memory 217928 kb
Host smart-35833347-bb70-4eaf-8ef5-5ab4887d6623
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833655245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1833655245
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.417570201
Short name T110
Test name
Test status
Simulation time 1522573774 ps
CPU time 161.01 seconds
Started Jul 03 04:21:57 PM PDT 24
Finished Jul 03 04:24:39 PM PDT 24
Peak memory 213836 kb
Host smart-57e60b7e-7aab-4e04-aff8-007ed2146311
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417570201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.417570201
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.129983712
Short name T245
Test name
Test status
Simulation time 16369421052 ps
CPU time 21.13 seconds
Started Jul 03 04:21:28 PM PDT 24
Finished Jul 03 04:21:50 PM PDT 24
Peak memory 217340 kb
Host smart-9f823d70-6369-4d87-8b85-45ee4c70ecff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129983712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.129983712
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3773878404
Short name T198
Test name
Test status
Simulation time 49447288917 ps
CPU time 303.65 seconds
Started Jul 03 04:23:00 PM PDT 24
Finished Jul 03 04:28:08 PM PDT 24
Peak memory 235268 kb
Host smart-96beab45-1c05-4268-9517-ac2e7437b9ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773878404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3773878404
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2860709781
Short name T227
Test name
Test status
Simulation time 9577357338 ps
CPU time 34.59 seconds
Started Jul 03 04:22:04 PM PDT 24
Finished Jul 03 04:22:39 PM PDT 24
Peak memory 219120 kb
Host smart-062ccd5d-c7b0-4988-9dad-995f4b873d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860709781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2860709781
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.4277159489
Short name T138
Test name
Test status
Simulation time 8578911637 ps
CPU time 32.72 seconds
Started Jul 03 04:23:00 PM PDT 24
Finished Jul 03 04:23:36 PM PDT 24
Peak memory 218008 kb
Host smart-439cdfea-6172-465b-8ad1-1cf66fee96a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4277159489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.4277159489
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1878420024
Short name T140
Test name
Test status
Simulation time 867235969 ps
CPU time 24.08 seconds
Started Jul 03 04:22:05 PM PDT 24
Finished Jul 03 04:22:29 PM PDT 24
Peak memory 216192 kb
Host smart-e99ff002-af75-43a5-81b2-8fab5f4f4aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878420024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1878420024
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1849944934
Short name T122
Test name
Test status
Simulation time 12604942252 ps
CPU time 105.44 seconds
Started Jul 03 04:22:04 PM PDT 24
Finished Jul 03 04:23:50 PM PDT 24
Peak memory 219420 kb
Host smart-1247dc68-03c7-4184-bae3-62c413ef8b53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849944934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1849944934
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.456323229
Short name T251
Test name
Test status
Simulation time 1100169278 ps
CPU time 8.46 seconds
Started Jul 03 04:21:41 PM PDT 24
Finished Jul 03 04:21:50 PM PDT 24
Peak memory 217028 kb
Host smart-0929f426-9304-4c38-9148-76ca96cde366
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456323229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.456323229
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.536125512
Short name T149
Test name
Test status
Simulation time 49549779825 ps
CPU time 595.17 seconds
Started Jul 03 04:21:39 PM PDT 24
Finished Jul 03 04:31:35 PM PDT 24
Peak memory 242688 kb
Host smart-b1079dc0-4b21-4743-b4f1-70e6f020a83b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536125512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.536125512
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2161758194
Short name T124
Test name
Test status
Simulation time 342834463 ps
CPU time 19.11 seconds
Started Jul 03 04:23:02 PM PDT 24
Finished Jul 03 04:23:24 PM PDT 24
Peak memory 219180 kb
Host smart-31164db8-8fed-40b9-ab99-b5d36c70e075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161758194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2161758194
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3026585627
Short name T136
Test name
Test status
Simulation time 5560324305 ps
CPU time 26.46 seconds
Started Jul 03 04:22:58 PM PDT 24
Finished Jul 03 04:23:26 PM PDT 24
Peak memory 211620 kb
Host smart-f8786b87-b6bd-4401-90c4-f8ed77444379
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3026585627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3026585627
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2699409365
Short name T27
Test name
Test status
Simulation time 3478128500 ps
CPU time 135.15 seconds
Started Jul 03 04:23:07 PM PDT 24
Finished Jul 03 04:25:23 PM PDT 24
Peak memory 237728 kb
Host smart-9158d5a8-f055-4d9e-9d74-63a08cd7d5ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699409365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2699409365
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2008161246
Short name T204
Test name
Test status
Simulation time 2869299078 ps
CPU time 44.37 seconds
Started Jul 03 04:21:48 PM PDT 24
Finished Jul 03 04:22:33 PM PDT 24
Peak memory 220164 kb
Host smart-9e0f5dbe-6ffe-4ef4-b149-f58fc2b80ff9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008161246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2008161246
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2189542116
Short name T258
Test name
Test status
Simulation time 2904443590 ps
CPU time 25.28 seconds
Started Jul 03 04:22:59 PM PDT 24
Finished Jul 03 04:23:26 PM PDT 24
Peak memory 216000 kb
Host smart-9e1688ab-bfba-4c26-a6bc-5c385696f459
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189542116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2189542116
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1621705306
Short name T364
Test name
Test status
Simulation time 29041166993 ps
CPU time 499.48 seconds
Started Jul 03 04:23:02 PM PDT 24
Finished Jul 03 04:31:24 PM PDT 24
Peak memory 217992 kb
Host smart-3fd8286a-88d9-4f30-bd88-0f2aa697c321
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621705306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1621705306
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1264238006
Short name T247
Test name
Test status
Simulation time 7144673131 ps
CPU time 62.41 seconds
Started Jul 03 04:21:46 PM PDT 24
Finished Jul 03 04:22:49 PM PDT 24
Peak memory 218964 kb
Host smart-9b44ff47-a047-443e-bc4a-a22bd798d31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264238006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1264238006
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3036604949
Short name T182
Test name
Test status
Simulation time 7918986699 ps
CPU time 22.15 seconds
Started Jul 03 04:22:31 PM PDT 24
Finished Jul 03 04:22:54 PM PDT 24
Peak memory 211904 kb
Host smart-c155da9b-bb6a-4fca-a198-f978ea2244d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3036604949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3036604949
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.125866515
Short name T313
Test name
Test status
Simulation time 12824612569 ps
CPU time 64.93 seconds
Started Jul 03 04:23:07 PM PDT 24
Finished Jul 03 04:24:12 PM PDT 24
Peak memory 217600 kb
Host smart-1080d139-4669-4344-a496-d1cb80137548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125866515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.125866515
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1116788088
Short name T177
Test name
Test status
Simulation time 3391488902 ps
CPU time 44.55 seconds
Started Jul 03 04:21:43 PM PDT 24
Finished Jul 03 04:22:28 PM PDT 24
Peak memory 218404 kb
Host smart-c0435bce-b94d-4c13-be55-b4c6d16486dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116788088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1116788088
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.859237339
Short name T56
Test name
Test status
Simulation time 53913305937 ps
CPU time 3771.15 seconds
Started Jul 03 04:22:51 PM PDT 24
Finished Jul 03 05:25:44 PM PDT 24
Peak memory 242684 kb
Host smart-6516f15a-b3fe-460d-b74c-ad0353f3c406
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859237339 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.859237339
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2215697424
Short name T209
Test name
Test status
Simulation time 10346146980 ps
CPU time 24.02 seconds
Started Jul 03 04:23:15 PM PDT 24
Finished Jul 03 04:23:39 PM PDT 24
Peak memory 217388 kb
Host smart-211a8299-79ca-4138-a898-9db42798dd2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215697424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2215697424
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1399245294
Short name T230
Test name
Test status
Simulation time 2981567201 ps
CPU time 229.87 seconds
Started Jul 03 04:22:57 PM PDT 24
Finished Jul 03 04:26:47 PM PDT 24
Peak memory 234840 kb
Host smart-659f764f-5b81-47dd-97ea-80b730f2a855
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399245294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1399245294
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2820638556
Short name T174
Test name
Test status
Simulation time 1373970648 ps
CPU time 18.53 seconds
Started Jul 03 04:21:58 PM PDT 24
Finished Jul 03 04:22:17 PM PDT 24
Peak memory 219100 kb
Host smart-ddc02aef-af34-4973-a922-55f4067df3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820638556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2820638556
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.4211813275
Short name T330
Test name
Test status
Simulation time 4115730745 ps
CPU time 34.17 seconds
Started Jul 03 04:21:57 PM PDT 24
Finished Jul 03 04:22:32 PM PDT 24
Peak memory 211172 kb
Host smart-0b3337ec-aa58-414d-8fe0-6ed780b64104
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4211813275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.4211813275
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2748254285
Short name T21
Test name
Test status
Simulation time 26718472691 ps
CPU time 56.75 seconds
Started Jul 03 04:23:14 PM PDT 24
Finished Jul 03 04:24:11 PM PDT 24
Peak memory 216900 kb
Host smart-952d0c17-d7e6-4fce-8000-0b914fe79d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748254285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2748254285
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1981081383
Short name T347
Test name
Test status
Simulation time 1162673946 ps
CPU time 35.62 seconds
Started Jul 03 04:23:09 PM PDT 24
Finished Jul 03 04:23:46 PM PDT 24
Peak memory 218928 kb
Host smart-f93a8932-7c50-4b5a-9879-9ba7f77b92e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981081383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1981081383
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2917475529
Short name T70
Test name
Test status
Simulation time 2062979459 ps
CPU time 7.73 seconds
Started Jul 03 04:23:09 PM PDT 24
Finished Jul 03 04:23:18 PM PDT 24
Peak memory 216756 kb
Host smart-9cb5f4b8-c21d-43b8-8492-6bdbdf720545
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917475529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2917475529
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3145677887
Short name T201
Test name
Test status
Simulation time 19415052249 ps
CPU time 258.8 seconds
Started Jul 03 04:22:58 PM PDT 24
Finished Jul 03 04:27:19 PM PDT 24
Peak memory 233224 kb
Host smart-a4af24d1-3950-4894-9ef5-8d8d490bacd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145677887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3145677887
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1232897691
Short name T358
Test name
Test status
Simulation time 8848118923 ps
CPU time 45.63 seconds
Started Jul 03 04:22:56 PM PDT 24
Finished Jul 03 04:23:43 PM PDT 24
Peak memory 218288 kb
Host smart-02d9fb3b-4fcd-40cb-a8ec-95c223918355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232897691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1232897691
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1240553032
Short name T162
Test name
Test status
Simulation time 2400829487 ps
CPU time 23.85 seconds
Started Jul 03 04:23:00 PM PDT 24
Finished Jul 03 04:23:27 PM PDT 24
Peak memory 217756 kb
Host smart-e3f9c6d5-81e1-44a7-af39-2d9c80cedd1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1240553032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1240553032
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.892318799
Short name T362
Test name
Test status
Simulation time 5267809570 ps
CPU time 37.66 seconds
Started Jul 03 04:22:59 PM PDT 24
Finished Jul 03 04:23:39 PM PDT 24
Peak memory 216384 kb
Host smart-de3c7a51-b52e-444a-bd1c-d68c024774bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892318799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.892318799
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.375464545
Short name T183
Test name
Test status
Simulation time 685821465 ps
CPU time 23.13 seconds
Started Jul 03 04:23:15 PM PDT 24
Finished Jul 03 04:23:39 PM PDT 24
Peak memory 218616 kb
Host smart-d80acc1d-ffd3-47c3-853f-06ed5763d945
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375464545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.375464545
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2614556155
Short name T168
Test name
Test status
Simulation time 11224926682 ps
CPU time 14.07 seconds
Started Jul 03 04:23:09 PM PDT 24
Finished Jul 03 04:23:25 PM PDT 24
Peak memory 217072 kb
Host smart-9aff4980-ee14-441b-9397-66ffd61d42e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614556155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2614556155
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.471273591
Short name T173
Test name
Test status
Simulation time 189030300926 ps
CPU time 591.6 seconds
Started Jul 03 04:23:09 PM PDT 24
Finished Jul 03 04:33:02 PM PDT 24
Peak memory 226568 kb
Host smart-0f691bf2-b402-4425-9cf4-e092c32cc241
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471273591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_c
orrupt_sig_fatal_chk.471273591
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2776421303
Short name T199
Test name
Test status
Simulation time 4301195475 ps
CPU time 25.06 seconds
Started Jul 03 04:22:59 PM PDT 24
Finished Jul 03 04:23:26 PM PDT 24
Peak memory 218784 kb
Host smart-bf00cc20-039d-4398-8e14-e986f68fe6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776421303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2776421303
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.582146546
Short name T4
Test name
Test status
Simulation time 2827860864 ps
CPU time 26.29 seconds
Started Jul 03 04:22:02 PM PDT 24
Finished Jul 03 04:22:29 PM PDT 24
Peak memory 219248 kb
Host smart-b537692f-6402-4d3c-814b-8d1eaec1e7b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=582146546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.582146546
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1329170686
Short name T33
Test name
Test status
Simulation time 353509350 ps
CPU time 19.26 seconds
Started Jul 03 04:23:10 PM PDT 24
Finished Jul 03 04:23:31 PM PDT 24
Peak memory 216400 kb
Host smart-daaf4cc9-2d96-4859-ab37-0131d6488dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329170686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1329170686
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2023317850
Short name T214
Test name
Test status
Simulation time 23700422506 ps
CPU time 67.88 seconds
Started Jul 03 04:23:09 PM PDT 24
Finished Jul 03 04:24:19 PM PDT 24
Peak memory 218580 kb
Host smart-c06a86fc-9fd6-4cef-8e5d-b31ccc338b1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023317850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2023317850
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1673156738
Short name T196
Test name
Test status
Simulation time 54959614105 ps
CPU time 26.1 seconds
Started Jul 03 04:23:14 PM PDT 24
Finished Jul 03 04:23:41 PM PDT 24
Peak memory 217336 kb
Host smart-658691bd-dca2-4227-a5f3-a38c4e45ce64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673156738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1673156738
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3215993776
Short name T355
Test name
Test status
Simulation time 15052123787 ps
CPU time 220.04 seconds
Started Jul 03 04:23:14 PM PDT 24
Finished Jul 03 04:26:55 PM PDT 24
Peak memory 239772 kb
Host smart-5ba20cd5-7fb5-492b-b4f4-46e9562194fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215993776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3215993776
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1951042443
Short name T215
Test name
Test status
Simulation time 18504064950 ps
CPU time 46.23 seconds
Started Jul 03 04:23:09 PM PDT 24
Finished Jul 03 04:23:56 PM PDT 24
Peak memory 218780 kb
Host smart-f1e1e4bc-df19-4912-bfe1-ff6e0aa2e030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951042443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1951042443
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.4286295509
Short name T345
Test name
Test status
Simulation time 2771538981 ps
CPU time 14.62 seconds
Started Jul 03 04:21:56 PM PDT 24
Finished Jul 03 04:22:11 PM PDT 24
Peak memory 218792 kb
Host smart-5fa661de-8616-425c-a612-ea17e2b0950a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4286295509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.4286295509
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2163288927
Short name T223
Test name
Test status
Simulation time 7069999708 ps
CPU time 65.15 seconds
Started Jul 03 04:22:56 PM PDT 24
Finished Jul 03 04:24:02 PM PDT 24
Peak memory 215764 kb
Host smart-830e5668-988a-4998-b3e3-68436e7223b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163288927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2163288927
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.4018972334
Short name T291
Test name
Test status
Simulation time 52260988230 ps
CPU time 122.84 seconds
Started Jul 03 04:23:10 PM PDT 24
Finished Jul 03 04:25:14 PM PDT 24
Peak memory 220100 kb
Host smart-14d99dc9-d50c-4862-bebb-c01b56323c85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018972334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.4018972334
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1344944448
Short name T298
Test name
Test status
Simulation time 2934815603 ps
CPU time 24.74 seconds
Started Jul 03 04:23:10 PM PDT 24
Finished Jul 03 04:23:36 PM PDT 24
Peak memory 216920 kb
Host smart-92991e61-a7ab-4249-a62a-52ba64d17622
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344944448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1344944448
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.4126730459
Short name T341
Test name
Test status
Simulation time 37308254410 ps
CPU time 479.32 seconds
Started Jul 03 04:21:59 PM PDT 24
Finished Jul 03 04:29:59 PM PDT 24
Peak memory 214656 kb
Host smart-606d227f-609c-49bb-bb3c-f24e01d87715
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126730459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.4126730459
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1313911526
Short name T139
Test name
Test status
Simulation time 1987143510 ps
CPU time 31.27 seconds
Started Jul 03 04:22:59 PM PDT 24
Finished Jul 03 04:23:32 PM PDT 24
Peak memory 218132 kb
Host smart-c0ece4d2-82c9-4c82-a909-89c256795688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313911526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1313911526
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3448988367
Short name T10
Test name
Test status
Simulation time 12270047968 ps
CPU time 24.08 seconds
Started Jul 03 04:23:10 PM PDT 24
Finished Jul 03 04:23:35 PM PDT 24
Peak memory 218972 kb
Host smart-cb44a07e-970d-489c-831b-cdc56d082ac5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3448988367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3448988367
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3364179142
Short name T276
Test name
Test status
Simulation time 20070185245 ps
CPU time 44.93 seconds
Started Jul 03 04:22:59 PM PDT 24
Finished Jul 03 04:23:47 PM PDT 24
Peak memory 216660 kb
Host smart-3c52ac12-4daa-4906-8041-8b00962fe310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364179142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3364179142
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3767958989
Short name T281
Test name
Test status
Simulation time 6595562798 ps
CPU time 51.32 seconds
Started Jul 03 04:21:56 PM PDT 24
Finished Jul 03 04:22:48 PM PDT 24
Peak memory 219192 kb
Host smart-1c5595e3-f2fa-492c-a4c7-1f9480983cfa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767958989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3767958989
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1536399746
Short name T18
Test name
Test status
Simulation time 53790524709 ps
CPU time 3786.59 seconds
Started Jul 03 04:22:59 PM PDT 24
Finished Jul 03 05:26:07 PM PDT 24
Peak memory 232016 kb
Host smart-ceddf398-87b8-40c1-b77f-5eda55dc99f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536399746 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.1536399746
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.26409624
Short name T160
Test name
Test status
Simulation time 167746014 ps
CPU time 8.24 seconds
Started Jul 03 04:22:01 PM PDT 24
Finished Jul 03 04:22:10 PM PDT 24
Peak memory 217092 kb
Host smart-733b50de-61bf-446c-97df-20c4ea7b2794
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26409624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.26409624
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1936569273
Short name T221
Test name
Test status
Simulation time 53002858306 ps
CPU time 540.22 seconds
Started Jul 03 04:23:09 PM PDT 24
Finished Jul 03 04:32:11 PM PDT 24
Peak memory 242304 kb
Host smart-e04fac38-da0b-4ddf-8d3a-28721a8f2374
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936569273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1936569273
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.725096795
Short name T338
Test name
Test status
Simulation time 14379388616 ps
CPU time 39.71 seconds
Started Jul 03 04:22:58 PM PDT 24
Finished Jul 03 04:23:40 PM PDT 24
Peak memory 217828 kb
Host smart-ce48b570-a32d-40bc-8b37-4ff96a2530b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725096795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.725096795
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.270253130
Short name T274
Test name
Test status
Simulation time 9262308528 ps
CPU time 25.02 seconds
Started Jul 03 04:22:59 PM PDT 24
Finished Jul 03 04:23:26 PM PDT 24
Peak memory 211068 kb
Host smart-9952c9b5-b6a7-411c-aee4-b82b8af3270a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=270253130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.270253130
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1465003551
Short name T264
Test name
Test status
Simulation time 4171842389 ps
CPU time 47.17 seconds
Started Jul 03 04:23:08 PM PDT 24
Finished Jul 03 04:23:56 PM PDT 24
Peak memory 215708 kb
Host smart-538ff5b9-61e6-42d2-9624-a15fd771c76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465003551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1465003551
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.190297180
Short name T302
Test name
Test status
Simulation time 6019314642 ps
CPU time 84.25 seconds
Started Jul 03 04:23:08 PM PDT 24
Finished Jul 03 04:24:34 PM PDT 24
Peak memory 218952 kb
Host smart-c2ad76b5-55ef-4b3f-a519-0202f66692d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190297180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.190297180
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1639916318
Short name T301
Test name
Test status
Simulation time 658126350 ps
CPU time 10.49 seconds
Started Jul 03 04:21:56 PM PDT 24
Finished Jul 03 04:22:07 PM PDT 24
Peak memory 217088 kb
Host smart-99b19b1f-ba00-4ff6-a59a-38fe6f96852e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639916318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1639916318
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1435426598
Short name T361
Test name
Test status
Simulation time 283808878455 ps
CPU time 721.88 seconds
Started Jul 03 04:21:57 PM PDT 24
Finished Jul 03 04:34:00 PM PDT 24
Peak memory 237404 kb
Host smart-2fce2f6b-249f-4a74-a4f3-d03527f003c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435426598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1435426598
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.909473406
Short name T125
Test name
Test status
Simulation time 7740429870 ps
CPU time 63.97 seconds
Started Jul 03 04:21:58 PM PDT 24
Finished Jul 03 04:23:03 PM PDT 24
Peak memory 219044 kb
Host smart-bd860902-0403-49a7-afa1-aadc589df2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909473406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.909473406
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.413822121
Short name T203
Test name
Test status
Simulation time 13178071277 ps
CPU time 29.08 seconds
Started Jul 03 04:22:01 PM PDT 24
Finished Jul 03 04:22:31 PM PDT 24
Peak memory 211888 kb
Host smart-1dba3266-882b-4151-a789-ef33ab323c4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=413822121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.413822121
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.819228461
Short name T180
Test name
Test status
Simulation time 20803621866 ps
CPU time 70.32 seconds
Started Jul 03 04:21:59 PM PDT 24
Finished Jul 03 04:23:09 PM PDT 24
Peak memory 216232 kb
Host smart-cdb52bd6-dcf4-4dcd-bedc-31b33f058368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819228461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.819228461
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2591730877
Short name T19
Test name
Test status
Simulation time 2188885826 ps
CPU time 34.31 seconds
Started Jul 03 04:22:00 PM PDT 24
Finished Jul 03 04:22:35 PM PDT 24
Peak memory 219244 kb
Host smart-a29fdde0-a219-40c2-957c-b6bc05cf8230
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591730877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2591730877
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.25293533
Short name T51
Test name
Test status
Simulation time 76868422495 ps
CPU time 647.32 seconds
Started Jul 03 04:22:02 PM PDT 24
Finished Jul 03 04:32:50 PM PDT 24
Peak memory 220228 kb
Host smart-32b9a8b3-f16e-461e-b0a3-33f297438aa8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25293533 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.25293533
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.4071155192
Short name T189
Test name
Test status
Simulation time 4769259655 ps
CPU time 31.05 seconds
Started Jul 03 04:23:01 PM PDT 24
Finished Jul 03 04:23:35 PM PDT 24
Peak memory 216952 kb
Host smart-f95bb7e0-bc11-4855-89fd-8f9f56505d6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071155192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.4071155192
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2935381680
Short name T331
Test name
Test status
Simulation time 6975872667 ps
CPU time 201.31 seconds
Started Jul 03 04:22:07 PM PDT 24
Finished Jul 03 04:25:29 PM PDT 24
Peak memory 224900 kb
Host smart-6f63dcaf-4d1d-42d6-836c-43cc4b55a891
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935381680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2935381680
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2783419935
Short name T5
Test name
Test status
Simulation time 352536432 ps
CPU time 18.46 seconds
Started Jul 03 04:21:59 PM PDT 24
Finished Jul 03 04:22:18 PM PDT 24
Peak memory 219144 kb
Host smart-96651ed7-81c6-4d67-abc9-89e46ffcd6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783419935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2783419935
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1131681368
Short name T127
Test name
Test status
Simulation time 4833207293 ps
CPU time 17.35 seconds
Started Jul 03 04:22:02 PM PDT 24
Finished Jul 03 04:22:20 PM PDT 24
Peak memory 211560 kb
Host smart-92cd0642-9740-4f9b-adac-6b55bff8f5fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1131681368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1131681368
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.3518491908
Short name T155
Test name
Test status
Simulation time 8551991547 ps
CPU time 46.84 seconds
Started Jul 03 04:21:55 PM PDT 24
Finished Jul 03 04:22:42 PM PDT 24
Peak memory 216936 kb
Host smart-20c11e72-5cd0-45f4-9709-56ea91012ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518491908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.3518491908
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2450811438
Short name T147
Test name
Test status
Simulation time 534348827 ps
CPU time 32.35 seconds
Started Jul 03 04:22:00 PM PDT 24
Finished Jul 03 04:22:33 PM PDT 24
Peak memory 218980 kb
Host smart-16ce1d8b-ed00-4362-ba03-f5c9baa7e912
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450811438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2450811438
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1712289686
Short name T324
Test name
Test status
Simulation time 820945402 ps
CPU time 10.96 seconds
Started Jul 03 04:22:02 PM PDT 24
Finished Jul 03 04:22:13 PM PDT 24
Peak memory 212900 kb
Host smart-84cf9a6c-21c2-42af-912b-02f2acd208ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712289686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1712289686
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1337355166
Short name T25
Test name
Test status
Simulation time 166692073898 ps
CPU time 231.42 seconds
Started Jul 03 04:22:01 PM PDT 24
Finished Jul 03 04:25:53 PM PDT 24
Peak memory 234692 kb
Host smart-e014b0c4-a37c-42e9-82c7-1d2b63876b0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337355166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1337355166
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3364627715
Short name T129
Test name
Test status
Simulation time 18388703169 ps
CPU time 48.29 seconds
Started Jul 03 04:21:59 PM PDT 24
Finished Jul 03 04:22:47 PM PDT 24
Peak memory 219216 kb
Host smart-3e6e150a-3938-4dc4-8b22-4e4cbdb61f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364627715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3364627715
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2325617985
Short name T257
Test name
Test status
Simulation time 17109995301 ps
CPU time 33.29 seconds
Started Jul 03 04:22:07 PM PDT 24
Finished Jul 03 04:22:40 PM PDT 24
Peak memory 211492 kb
Host smart-4b51f0a7-b6e0-415a-ae0d-c2360318adbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2325617985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2325617985
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1810454181
Short name T86
Test name
Test status
Simulation time 2684116669 ps
CPU time 38.79 seconds
Started Jul 03 04:22:01 PM PDT 24
Finished Jul 03 04:22:40 PM PDT 24
Peak memory 216408 kb
Host smart-936d04a9-aaac-48dd-85e7-52797dde17fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810454181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1810454181
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2069093898
Short name T154
Test name
Test status
Simulation time 4485045998 ps
CPU time 66.05 seconds
Started Jul 03 04:21:57 PM PDT 24
Finished Jul 03 04:23:04 PM PDT 24
Peak memory 219248 kb
Host smart-39a543c2-628c-451e-98a7-5dc0112cf1e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069093898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2069093898
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.625717652
Short name T340
Test name
Test status
Simulation time 7592255519 ps
CPU time 20.78 seconds
Started Jul 03 04:22:42 PM PDT 24
Finished Jul 03 04:23:04 PM PDT 24
Peak memory 212136 kb
Host smart-217f76fc-731c-4971-a470-d7316273e27b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625717652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.625717652
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2471316169
Short name T217
Test name
Test status
Simulation time 37299194946 ps
CPU time 143.53 seconds
Started Jul 03 04:23:01 PM PDT 24
Finished Jul 03 04:25:27 PM PDT 24
Peak memory 219188 kb
Host smart-a9724494-1411-4852-8b9b-167e5cf73cd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471316169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2471316169
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.554040826
Short name T3
Test name
Test status
Simulation time 19778345539 ps
CPU time 48.44 seconds
Started Jul 03 04:21:34 PM PDT 24
Finished Jul 03 04:22:23 PM PDT 24
Peak memory 219232 kb
Host smart-c2dd69b8-1b6a-4abc-ba6c-d7284a7111bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554040826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.554040826
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3392972682
Short name T206
Test name
Test status
Simulation time 14042167804 ps
CPU time 29.49 seconds
Started Jul 03 04:21:42 PM PDT 24
Finished Jul 03 04:22:12 PM PDT 24
Peak memory 217600 kb
Host smart-c4e46d82-9f59-4b16-8f3c-abb8a83142c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3392972682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3392972682
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1625440025
Short name T32
Test name
Test status
Simulation time 14099754224 ps
CPU time 239.5 seconds
Started Jul 03 04:22:59 PM PDT 24
Finished Jul 03 04:27:01 PM PDT 24
Peak memory 236028 kb
Host smart-ef8ce256-35fc-4eda-b611-562863e939a1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625440025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1625440025
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3072297681
Short name T211
Test name
Test status
Simulation time 6880327704 ps
CPU time 39.21 seconds
Started Jul 03 04:21:48 PM PDT 24
Finished Jul 03 04:22:28 PM PDT 24
Peak memory 216668 kb
Host smart-80d58c43-d9a9-4d7a-adb9-3c4f9449a00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072297681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3072297681
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.829126481
Short name T229
Test name
Test status
Simulation time 360359631 ps
CPU time 18.96 seconds
Started Jul 03 04:23:01 PM PDT 24
Finished Jul 03 04:23:23 PM PDT 24
Peak memory 217548 kb
Host smart-4138ad3b-b927-4be8-9abb-9f049b438c56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829126481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.829126481
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1232519180
Short name T266
Test name
Test status
Simulation time 4017687221 ps
CPU time 20.28 seconds
Started Jul 03 04:22:03 PM PDT 24
Finished Jul 03 04:22:23 PM PDT 24
Peak memory 216940 kb
Host smart-44e35bef-ac72-46f6-addc-cc960fd6d506
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232519180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1232519180
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1714839311
Short name T172
Test name
Test status
Simulation time 24900414809 ps
CPU time 299.67 seconds
Started Jul 03 04:22:02 PM PDT 24
Finished Jul 03 04:27:03 PM PDT 24
Peak memory 219104 kb
Host smart-6b9e6355-cdf1-441e-a631-93ac7df36dd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714839311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1714839311
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3360969615
Short name T352
Test name
Test status
Simulation time 16350373116 ps
CPU time 32.29 seconds
Started Jul 03 04:22:30 PM PDT 24
Finished Jul 03 04:23:03 PM PDT 24
Peak memory 218888 kb
Host smart-f2e22d5d-c2bb-4599-bf70-6a5eb99cf11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360969615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3360969615
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1450908605
Short name T228
Test name
Test status
Simulation time 346981006 ps
CPU time 10.07 seconds
Started Jul 03 04:22:03 PM PDT 24
Finished Jul 03 04:22:13 PM PDT 24
Peak memory 218960 kb
Host smart-a2de6561-4b86-4fa4-b6d0-bea3cb1cfbcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1450908605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1450908605
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2667819002
Short name T238
Test name
Test status
Simulation time 4939590735 ps
CPU time 46.83 seconds
Started Jul 03 04:21:57 PM PDT 24
Finished Jul 03 04:22:45 PM PDT 24
Peak memory 216052 kb
Host smart-4148c56f-4596-4bd8-8adf-509588bc406f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667819002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2667819002
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.1679384183
Short name T267
Test name
Test status
Simulation time 2165231806 ps
CPU time 41.24 seconds
Started Jul 03 04:21:57 PM PDT 24
Finished Jul 03 04:22:39 PM PDT 24
Peak memory 216028 kb
Host smart-5748bc6b-74ec-4d40-bb08-73f2ab5050f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679384183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.1679384183
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1623659999
Short name T325
Test name
Test status
Simulation time 660533905 ps
CPU time 7.89 seconds
Started Jul 03 04:22:01 PM PDT 24
Finished Jul 03 04:22:10 PM PDT 24
Peak memory 216692 kb
Host smart-109fca6f-3b7d-4015-ad41-ed04806795b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623659999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1623659999
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1683022267
Short name T34
Test name
Test status
Simulation time 1622139656 ps
CPU time 113.78 seconds
Started Jul 03 04:22:59 PM PDT 24
Finished Jul 03 04:24:57 PM PDT 24
Peak memory 226000 kb
Host smart-b3679136-b535-4ab0-8dab-e55425ad1093
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683022267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1683022267
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3573595262
Short name T48
Test name
Test status
Simulation time 4290015882 ps
CPU time 43.92 seconds
Started Jul 03 04:22:02 PM PDT 24
Finished Jul 03 04:22:47 PM PDT 24
Peak memory 219240 kb
Host smart-0d580615-ebcc-49fc-9180-0f11865f70e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573595262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3573595262
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3348706639
Short name T128
Test name
Test status
Simulation time 4112861456 ps
CPU time 32.86 seconds
Started Jul 03 04:21:58 PM PDT 24
Finished Jul 03 04:22:32 PM PDT 24
Peak memory 211224 kb
Host smart-d4292866-8391-4b07-8005-c4c96757a307
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3348706639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3348706639
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2115832463
Short name T343
Test name
Test status
Simulation time 1329570236 ps
CPU time 28.43 seconds
Started Jul 03 04:22:02 PM PDT 24
Finished Jul 03 04:22:31 PM PDT 24
Peak memory 215496 kb
Host smart-299863d3-75dd-4b57-bcc2-54384ab3d422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115832463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2115832463
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.757411852
Short name T236
Test name
Test status
Simulation time 30650342187 ps
CPU time 72.19 seconds
Started Jul 03 04:22:02 PM PDT 24
Finished Jul 03 04:23:15 PM PDT 24
Peak memory 217372 kb
Host smart-d183d072-4d83-4f52-8ff9-0cd6632e8522
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757411852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.757411852
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.115333936
Short name T306
Test name
Test status
Simulation time 429427411549 ps
CPU time 424.2 seconds
Started Jul 03 04:23:00 PM PDT 24
Finished Jul 03 04:30:07 PM PDT 24
Peak memory 228368 kb
Host smart-d483e66a-0eae-4002-a91e-347cde4fd55c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115333936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.115333936
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2246810838
Short name T47
Test name
Test status
Simulation time 53177638770 ps
CPU time 70.23 seconds
Started Jul 03 04:22:04 PM PDT 24
Finished Jul 03 04:23:15 PM PDT 24
Peak memory 219148 kb
Host smart-9d585a4d-0725-4ca4-afd7-27cfa684420b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246810838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2246810838
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1887197629
Short name T212
Test name
Test status
Simulation time 1824961152 ps
CPU time 19.71 seconds
Started Jul 03 04:22:00 PM PDT 24
Finished Jul 03 04:22:20 PM PDT 24
Peak memory 219232 kb
Host smart-7f804604-fda1-49e2-90ce-ff685ae49d1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1887197629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1887197629
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.303817621
Short name T346
Test name
Test status
Simulation time 17103866483 ps
CPU time 42.82 seconds
Started Jul 03 04:22:00 PM PDT 24
Finished Jul 03 04:22:43 PM PDT 24
Peak memory 216968 kb
Host smart-35b21f7f-2839-47d2-af62-0ba071fbba38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303817621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.303817621
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1110736945
Short name T171
Test name
Test status
Simulation time 6768097304 ps
CPU time 57.28 seconds
Started Jul 03 04:22:59 PM PDT 24
Finished Jul 03 04:24:00 PM PDT 24
Peak memory 219184 kb
Host smart-ab2916b0-5555-4860-9154-e5e6eecd5223
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110736945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1110736945
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1318754811
Short name T29
Test name
Test status
Simulation time 319045141 ps
CPU time 8.08 seconds
Started Jul 03 04:22:07 PM PDT 24
Finished Jul 03 04:22:15 PM PDT 24
Peak memory 217012 kb
Host smart-664af0e3-6fd5-46a4-804a-e5bec0f76672
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318754811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1318754811
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.285863597
Short name T328
Test name
Test status
Simulation time 346274203 ps
CPU time 19.24 seconds
Started Jul 03 04:22:11 PM PDT 24
Finished Jul 03 04:22:31 PM PDT 24
Peak memory 219156 kb
Host smart-6f97de41-ee26-403b-b51c-0a798eb368af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285863597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.285863597
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2122215969
Short name T337
Test name
Test status
Simulation time 692376528 ps
CPU time 9.95 seconds
Started Jul 03 04:22:04 PM PDT 24
Finished Jul 03 04:22:15 PM PDT 24
Peak memory 219132 kb
Host smart-7e7c06a8-1a21-4283-8fe8-4818404e607e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2122215969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2122215969
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.919422782
Short name T166
Test name
Test status
Simulation time 18617393074 ps
CPU time 58 seconds
Started Jul 03 04:21:57 PM PDT 24
Finished Jul 03 04:22:56 PM PDT 24
Peak memory 215800 kb
Host smart-aa9b6273-9ada-471e-b089-ea755466b7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919422782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.919422782
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2587989881
Short name T158
Test name
Test status
Simulation time 7156472030 ps
CPU time 16.28 seconds
Started Jul 03 04:22:01 PM PDT 24
Finished Jul 03 04:22:18 PM PDT 24
Peak memory 217512 kb
Host smart-b1e8c0fd-6180-4f88-8072-869a2496fdea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587989881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2587989881
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3949679271
Short name T284
Test name
Test status
Simulation time 12888943370 ps
CPU time 195.47 seconds
Started Jul 03 04:22:26 PM PDT 24
Finished Jul 03 04:25:42 PM PDT 24
Peak memory 242924 kb
Host smart-7d1e7176-7f85-4493-9b0a-4d0f714af383
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949679271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3949679271
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2634415089
Short name T349
Test name
Test status
Simulation time 74580623431 ps
CPU time 69.84 seconds
Started Jul 03 04:22:06 PM PDT 24
Finished Jul 03 04:23:17 PM PDT 24
Peak memory 219184 kb
Host smart-81cf0c1a-6fd2-49aa-ab9e-9e9381950b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634415089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2634415089
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2685772770
Short name T248
Test name
Test status
Simulation time 185859543 ps
CPU time 10.36 seconds
Started Jul 03 04:21:59 PM PDT 24
Finished Jul 03 04:22:10 PM PDT 24
Peak memory 219204 kb
Host smart-11e55b8c-742c-474b-98bd-bbc70309e2d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2685772770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2685772770
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.316785381
Short name T268
Test name
Test status
Simulation time 14321286496 ps
CPU time 64.52 seconds
Started Jul 03 04:22:02 PM PDT 24
Finished Jul 03 04:23:07 PM PDT 24
Peak memory 216928 kb
Host smart-44cc5db1-151a-4f90-9c72-af2366af8acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316785381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.316785381
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3385238115
Short name T296
Test name
Test status
Simulation time 562250528 ps
CPU time 29.05 seconds
Started Jul 03 04:21:57 PM PDT 24
Finished Jul 03 04:22:27 PM PDT 24
Peak memory 218960 kb
Host smart-86802a1a-3496-4b9b-a6c7-89ab48667e0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385238115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3385238115
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.217209718
Short name T280
Test name
Test status
Simulation time 7136613805 ps
CPU time 27.27 seconds
Started Jul 03 04:22:05 PM PDT 24
Finished Jul 03 04:22:33 PM PDT 24
Peak memory 217292 kb
Host smart-0ac57b58-90cf-4757-90af-e99c97bcaa01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217209718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.217209718
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2657791228
Short name T335
Test name
Test status
Simulation time 34257131611 ps
CPU time 455.78 seconds
Started Jul 03 04:22:12 PM PDT 24
Finished Jul 03 04:29:49 PM PDT 24
Peak memory 219368 kb
Host smart-045f2d55-d0be-453e-b2c8-b9b97366b23b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657791228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2657791228
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1233847038
Short name T58
Test name
Test status
Simulation time 35638369802 ps
CPU time 68.04 seconds
Started Jul 03 04:22:01 PM PDT 24
Finished Jul 03 04:23:09 PM PDT 24
Peak memory 219232 kb
Host smart-01f39f94-8cad-498c-b517-ade02a00a2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233847038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1233847038
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3332379870
Short name T187
Test name
Test status
Simulation time 2902799736 ps
CPU time 9.94 seconds
Started Jul 03 04:22:04 PM PDT 24
Finished Jul 03 04:22:15 PM PDT 24
Peak memory 218984 kb
Host smart-93786dd0-f4fb-4454-bd7e-597c915effc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3332379870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3332379870
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2417256944
Short name T85
Test name
Test status
Simulation time 19012935522 ps
CPU time 57.38 seconds
Started Jul 03 04:23:41 PM PDT 24
Finished Jul 03 04:24:39 PM PDT 24
Peak memory 215432 kb
Host smart-00f178a5-4af8-4943-b0ca-348fd405ca77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417256944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2417256944
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1047771842
Short name T322
Test name
Test status
Simulation time 28796938339 ps
CPU time 65.15 seconds
Started Jul 03 04:22:03 PM PDT 24
Finished Jul 03 04:23:09 PM PDT 24
Peak memory 217400 kb
Host smart-3451c2fb-3e80-4070-be55-50b66cc70787
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047771842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1047771842
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2140628864
Short name T53
Test name
Test status
Simulation time 25715689534 ps
CPU time 9716.28 seconds
Started Jul 03 04:21:56 PM PDT 24
Finished Jul 03 07:03:54 PM PDT 24
Peak memory 232280 kb
Host smart-14000b6a-b33d-4b05-a00a-284b7a0c6812
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140628864 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.2140628864
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2996354730
Short name T239
Test name
Test status
Simulation time 1564957389 ps
CPU time 10.61 seconds
Started Jul 03 04:21:57 PM PDT 24
Finished Jul 03 04:22:08 PM PDT 24
Peak memory 217040 kb
Host smart-e1516968-f0bb-4808-b793-f0ba1631a09d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996354730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2996354730
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2895993703
Short name T317
Test name
Test status
Simulation time 4222291192 ps
CPU time 134.82 seconds
Started Jul 03 04:22:18 PM PDT 24
Finished Jul 03 04:24:34 PM PDT 24
Peak memory 219456 kb
Host smart-ba49af7e-df20-4af7-b695-7d4078e20046
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895993703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2895993703
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3526422900
Short name T202
Test name
Test status
Simulation time 332388990 ps
CPU time 19.35 seconds
Started Jul 03 04:21:59 PM PDT 24
Finished Jul 03 04:22:19 PM PDT 24
Peak memory 219168 kb
Host smart-2e8e5e35-d2f0-43a1-b64a-6d2038459243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526422900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3526422900
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2728515599
Short name T262
Test name
Test status
Simulation time 23214772320 ps
CPU time 50.96 seconds
Started Jul 03 04:22:08 PM PDT 24
Finished Jul 03 04:22:59 PM PDT 24
Peak memory 216864 kb
Host smart-37d0cadf-dfce-4df1-bcd8-71a5f8896bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728515599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2728515599
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3367367613
Short name T356
Test name
Test status
Simulation time 2399594054 ps
CPU time 21.04 seconds
Started Jul 03 04:22:03 PM PDT 24
Finished Jul 03 04:22:35 PM PDT 24
Peak memory 217880 kb
Host smart-824026e8-ebf1-458c-ae95-87a37a8a0757
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367367613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3367367613
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3923355264
Short name T351
Test name
Test status
Simulation time 3080479075 ps
CPU time 12.99 seconds
Started Jul 03 04:22:02 PM PDT 24
Finished Jul 03 04:22:16 PM PDT 24
Peak memory 212884 kb
Host smart-0c9fe289-20bd-480f-85a9-1297fe90e1e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923355264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3923355264
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.31800493
Short name T60
Test name
Test status
Simulation time 8362109959 ps
CPU time 68.49 seconds
Started Jul 03 04:22:07 PM PDT 24
Finished Jul 03 04:23:16 PM PDT 24
Peak memory 219248 kb
Host smart-2e8349aa-c6a1-4d32-8bdf-9df0811ecaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31800493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.31800493
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.851779805
Short name T333
Test name
Test status
Simulation time 15636824045 ps
CPU time 31.09 seconds
Started Jul 03 04:21:56 PM PDT 24
Finished Jul 03 04:22:28 PM PDT 24
Peak memory 219264 kb
Host smart-1a923f79-0bae-4619-ba14-67d047b2d9fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=851779805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.851779805
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2977613183
Short name T167
Test name
Test status
Simulation time 1343529717 ps
CPU time 26.63 seconds
Started Jul 03 04:21:59 PM PDT 24
Finished Jul 03 04:22:26 PM PDT 24
Peak memory 215816 kb
Host smart-728b4c4e-8132-4502-992e-413a0fe88e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977613183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2977613183
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3866219341
Short name T265
Test name
Test status
Simulation time 15530376876 ps
CPU time 147.57 seconds
Started Jul 03 04:21:59 PM PDT 24
Finished Jul 03 04:24:27 PM PDT 24
Peak memory 219256 kb
Host smart-6e79f5ea-cc2f-460f-9ef2-904a73447d1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866219341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3866219341
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.988994265
Short name T309
Test name
Test status
Simulation time 10542619757 ps
CPU time 24.92 seconds
Started Jul 03 04:21:56 PM PDT 24
Finished Jul 03 04:22:21 PM PDT 24
Peak memory 217096 kb
Host smart-18cdf7be-2e16-49b2-93dd-de94eff8d492
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988994265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.988994265
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1268586464
Short name T161
Test name
Test status
Simulation time 9653118782 ps
CPU time 153.69 seconds
Started Jul 03 04:21:59 PM PDT 24
Finished Jul 03 04:24:34 PM PDT 24
Peak memory 219380 kb
Host smart-737a329e-6b6d-4ba9-88f2-fa32df8fef70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268586464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1268586464
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.461516689
Short name T320
Test name
Test status
Simulation time 36176410869 ps
CPU time 31.46 seconds
Started Jul 03 04:22:02 PM PDT 24
Finished Jul 03 04:22:34 PM PDT 24
Peak memory 219200 kb
Host smart-ebbf23b8-0e16-4632-bd19-0eab1a67daa3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=461516689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.461516689
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.452817864
Short name T194
Test name
Test status
Simulation time 11405832261 ps
CPU time 52.23 seconds
Started Jul 03 04:22:16 PM PDT 24
Finished Jul 03 04:23:09 PM PDT 24
Peak memory 215548 kb
Host smart-30253c7b-892e-484d-b673-0f7aab54917e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452817864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.452817864
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.300043519
Short name T314
Test name
Test status
Simulation time 9406764247 ps
CPU time 90.69 seconds
Started Jul 03 04:22:01 PM PDT 24
Finished Jul 03 04:23:32 PM PDT 24
Peak memory 218092 kb
Host smart-df6a1a1e-a009-40eb-8c55-9d27b2ebfdac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300043519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.rom_ctrl_stress_all.300043519
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.751383958
Short name T289
Test name
Test status
Simulation time 8504650587 ps
CPU time 26.78 seconds
Started Jul 03 04:22:06 PM PDT 24
Finished Jul 03 04:22:34 PM PDT 24
Peak memory 217244 kb
Host smart-0a780bd0-a37d-46b6-a5a9-220c82b9b0f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751383958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.751383958
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3381060426
Short name T259
Test name
Test status
Simulation time 2687163559 ps
CPU time 195.87 seconds
Started Jul 03 04:22:16 PM PDT 24
Finished Jul 03 04:25:32 PM PDT 24
Peak memory 239916 kb
Host smart-70ffc6f2-6f19-43a4-83d7-fbe54ce1ebfc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381060426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3381060426
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1565698462
Short name T339
Test name
Test status
Simulation time 2297988297 ps
CPU time 33.73 seconds
Started Jul 03 04:22:06 PM PDT 24
Finished Jul 03 04:22:40 PM PDT 24
Peak memory 219212 kb
Host smart-a92c96b5-7d79-45ff-abfe-a65cd5e8ca17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565698462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1565698462
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1947671178
Short name T153
Test name
Test status
Simulation time 9905941346 ps
CPU time 24.48 seconds
Started Jul 03 04:22:14 PM PDT 24
Finished Jul 03 04:22:39 PM PDT 24
Peak memory 211776 kb
Host smart-84ae3eb1-8e6c-4f4a-9fe5-4bb187195fff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1947671178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1947671178
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1245555327
Short name T261
Test name
Test status
Simulation time 1357029108 ps
CPU time 24.39 seconds
Started Jul 03 04:22:16 PM PDT 24
Finished Jul 03 04:22:41 PM PDT 24
Peak memory 215796 kb
Host smart-10cb86ea-3b62-4512-ae1d-e7dedce4d579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245555327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1245555327
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1287630656
Short name T241
Test name
Test status
Simulation time 2829330573 ps
CPU time 29.07 seconds
Started Jul 03 04:22:03 PM PDT 24
Finished Jul 03 04:22:32 PM PDT 24
Peak memory 219024 kb
Host smart-e55be927-6139-42ec-8d18-049b1e590b5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287630656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1287630656
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.4204548571
Short name T55
Test name
Test status
Simulation time 34038132335 ps
CPU time 2154.59 seconds
Started Jul 03 04:22:11 PM PDT 24
Finished Jul 03 04:58:06 PM PDT 24
Peak memory 229904 kb
Host smart-b21d6a2b-6b92-47bd-b02c-2b2e62d13ae6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204548571 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.4204548571
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2889660686
Short name T222
Test name
Test status
Simulation time 1793335220 ps
CPU time 14.4 seconds
Started Jul 03 04:22:49 PM PDT 24
Finished Jul 03 04:23:04 PM PDT 24
Peak memory 216156 kb
Host smart-e26d372c-1d75-4c4a-a3a8-b4a3eae7ef08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889660686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2889660686
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2858206222
Short name T249
Test name
Test status
Simulation time 22587964998 ps
CPU time 344.09 seconds
Started Jul 03 04:22:59 PM PDT 24
Finished Jul 03 04:28:45 PM PDT 24
Peak memory 234888 kb
Host smart-29b094bc-8728-42b6-b58e-ee8340c70696
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858206222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2858206222
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2749363123
Short name T1
Test name
Test status
Simulation time 8893206128 ps
CPU time 32.37 seconds
Started Jul 03 04:23:07 PM PDT 24
Finished Jul 03 04:23:40 PM PDT 24
Peak memory 218860 kb
Host smart-3d32100d-8d86-4002-9e5e-d051313a5d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749363123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2749363123
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.4099417987
Short name T210
Test name
Test status
Simulation time 206131778 ps
CPU time 10.15 seconds
Started Jul 03 04:22:59 PM PDT 24
Finished Jul 03 04:23:11 PM PDT 24
Peak memory 219188 kb
Host smart-d617c7ee-80aa-47e4-861d-c2ede7462162
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4099417987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.4099417987
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3043284867
Short name T28
Test name
Test status
Simulation time 3425747626 ps
CPU time 132.79 seconds
Started Jul 03 04:22:51 PM PDT 24
Finished Jul 03 04:25:06 PM PDT 24
Peak memory 236728 kb
Host smart-17662423-1a1e-498d-8004-6f07084f8d3b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043284867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3043284867
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1804764877
Short name T342
Test name
Test status
Simulation time 45751713528 ps
CPU time 65.46 seconds
Started Jul 03 04:21:37 PM PDT 24
Finished Jul 03 04:22:43 PM PDT 24
Peak memory 216968 kb
Host smart-6dbe675f-3d01-4d5b-af89-8028c03bebb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804764877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1804764877
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1576332412
Short name T123
Test name
Test status
Simulation time 16075325733 ps
CPU time 53.56 seconds
Started Jul 03 04:21:37 PM PDT 24
Finished Jul 03 04:22:31 PM PDT 24
Peak memory 217444 kb
Host smart-784bee22-fe57-4789-8759-520cad70cae7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576332412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1576332412
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.593372594
Short name T193
Test name
Test status
Simulation time 1777019046 ps
CPU time 19.75 seconds
Started Jul 03 04:22:09 PM PDT 24
Finished Jul 03 04:22:29 PM PDT 24
Peak memory 217124 kb
Host smart-0befb81a-b01c-4244-928b-19dd04507f1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593372594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.593372594
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3341098322
Short name T43
Test name
Test status
Simulation time 312603087129 ps
CPU time 817.36 seconds
Started Jul 03 04:22:07 PM PDT 24
Finished Jul 03 04:35:45 PM PDT 24
Peak memory 237820 kb
Host smart-90b835b3-8afe-4f8d-9431-9af2d9be8d10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341098322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3341098322
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1521853694
Short name T135
Test name
Test status
Simulation time 7674480214 ps
CPU time 64.82 seconds
Started Jul 03 04:23:40 PM PDT 24
Finished Jul 03 04:24:46 PM PDT 24
Peak memory 219024 kb
Host smart-6ca47d6b-b1dc-4cd2-97f9-a4e1f3d18ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521853694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1521853694
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1859230857
Short name T142
Test name
Test status
Simulation time 346514476 ps
CPU time 10.3 seconds
Started Jul 03 04:22:05 PM PDT 24
Finished Jul 03 04:22:16 PM PDT 24
Peak memory 219232 kb
Host smart-ab6252b2-7ae1-4b8f-9176-7253982f5bb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1859230857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1859230857
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3718923768
Short name T132
Test name
Test status
Simulation time 25196213748 ps
CPU time 43.19 seconds
Started Jul 03 04:22:08 PM PDT 24
Finished Jul 03 04:22:52 PM PDT 24
Peak memory 216680 kb
Host smart-069d2fe1-0441-4ce4-9365-105b6682d9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718923768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3718923768
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1223459046
Short name T344
Test name
Test status
Simulation time 861958115 ps
CPU time 55.28 seconds
Started Jul 03 04:22:05 PM PDT 24
Finished Jul 03 04:23:01 PM PDT 24
Peak memory 218992 kb
Host smart-c5a1ae74-928e-4fd3-a873-98b3d6acca20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223459046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1223459046
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1775301950
Short name T353
Test name
Test status
Simulation time 6191125062 ps
CPU time 26.04 seconds
Started Jul 03 04:22:12 PM PDT 24
Finished Jul 03 04:22:39 PM PDT 24
Peak memory 213148 kb
Host smart-5f0de936-cbbf-456a-b6ad-411db074bf2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775301950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1775301950
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.4017246499
Short name T23
Test name
Test status
Simulation time 521524739157 ps
CPU time 1134.32 seconds
Started Jul 03 04:22:04 PM PDT 24
Finished Jul 03 04:40:58 PM PDT 24
Peak memory 225576 kb
Host smart-27f56dd7-c0ba-413c-b80e-eec4b9a35c35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017246499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.4017246499
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.789551740
Short name T231
Test name
Test status
Simulation time 17805145281 ps
CPU time 66.03 seconds
Started Jul 03 04:22:25 PM PDT 24
Finished Jul 03 04:23:32 PM PDT 24
Peak memory 219232 kb
Host smart-227bedb9-afd9-4796-a1a2-7848adea55df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789551740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.789551740
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3020358863
Short name T130
Test name
Test status
Simulation time 13017005454 ps
CPU time 27.78 seconds
Started Jul 03 04:22:05 PM PDT 24
Finished Jul 03 04:22:34 PM PDT 24
Peak memory 219240 kb
Host smart-4ce48956-ad4f-46be-9403-cba215623d6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3020358863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3020358863
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.4160324446
Short name T318
Test name
Test status
Simulation time 8549570404 ps
CPU time 47.56 seconds
Started Jul 03 04:22:03 PM PDT 24
Finished Jul 03 04:22:51 PM PDT 24
Peak memory 217060 kb
Host smart-dd524bfc-3538-4f0b-b0ca-e4a15fb89fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160324446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.4160324446
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.4039499017
Short name T295
Test name
Test status
Simulation time 31237285622 ps
CPU time 156.37 seconds
Started Jul 03 04:22:06 PM PDT 24
Finished Jul 03 04:24:43 PM PDT 24
Peak memory 222776 kb
Host smart-5ea9e2c2-72ae-4c75-87d7-9916cbe613c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039499017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.4039499017
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.4125792192
Short name T294
Test name
Test status
Simulation time 3007052091 ps
CPU time 16.86 seconds
Started Jul 03 04:22:27 PM PDT 24
Finished Jul 03 04:22:44 PM PDT 24
Peak memory 217088 kb
Host smart-e41658db-9247-4a5b-8f65-a2d11b45939f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125792192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.4125792192
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1095345355
Short name T42
Test name
Test status
Simulation time 48841529967 ps
CPU time 560.11 seconds
Started Jul 03 04:22:12 PM PDT 24
Finished Jul 03 04:31:33 PM PDT 24
Peak memory 240936 kb
Host smart-f84fa9e5-8da6-463a-86b4-7b438a08086c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095345355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1095345355
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1729109761
Short name T254
Test name
Test status
Simulation time 2305832075 ps
CPU time 33.67 seconds
Started Jul 03 04:22:12 PM PDT 24
Finished Jul 03 04:22:47 PM PDT 24
Peak memory 218712 kb
Host smart-b9ff13c9-4fb2-497e-8953-c39c230ab692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729109761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1729109761
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.987626039
Short name T134
Test name
Test status
Simulation time 3595259788 ps
CPU time 29.91 seconds
Started Jul 03 04:22:05 PM PDT 24
Finished Jul 03 04:22:36 PM PDT 24
Peak memory 211624 kb
Host smart-e7931a10-dad7-4e57-a97e-a8f6571a0918
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=987626039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.987626039
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2816517653
Short name T148
Test name
Test status
Simulation time 7308875210 ps
CPU time 45.92 seconds
Started Jul 03 04:22:09 PM PDT 24
Finished Jul 03 04:22:55 PM PDT 24
Peak memory 216512 kb
Host smart-1b9aeb36-70cc-4e82-8370-6ebbae1575ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816517653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2816517653
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3455514490
Short name T20
Test name
Test status
Simulation time 58692130512 ps
CPU time 130.79 seconds
Started Jul 03 04:22:21 PM PDT 24
Finished Jul 03 04:24:33 PM PDT 24
Peak memory 219252 kb
Host smart-d6db2efa-70cd-4fc1-a68d-1b75636d0ae1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455514490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3455514490
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1333266574
Short name T30
Test name
Test status
Simulation time 1564749543 ps
CPU time 18.02 seconds
Started Jul 03 04:22:09 PM PDT 24
Finished Jul 03 04:22:27 PM PDT 24
Peak memory 217128 kb
Host smart-8e98a91d-07c7-4507-a139-e7d3708e9b23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333266574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1333266574
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3093287835
Short name T44
Test name
Test status
Simulation time 10878815706 ps
CPU time 372.6 seconds
Started Jul 03 04:22:13 PM PDT 24
Finished Jul 03 04:28:27 PM PDT 24
Peak memory 229724 kb
Host smart-3cb861fa-3622-40f2-980b-6c8d88c9f1d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093287835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3093287835
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.4019791199
Short name T310
Test name
Test status
Simulation time 15476680593 ps
CPU time 64.31 seconds
Started Jul 03 04:22:14 PM PDT 24
Finished Jul 03 04:23:19 PM PDT 24
Peak memory 218888 kb
Host smart-6d0652a9-3aa6-44f9-978c-1015f0a6d0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019791199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.4019791199
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3487394841
Short name T191
Test name
Test status
Simulation time 1490300828 ps
CPU time 19.5 seconds
Started Jul 03 04:22:10 PM PDT 24
Finished Jul 03 04:22:30 PM PDT 24
Peak memory 211096 kb
Host smart-cb5c3a41-70c9-4e3b-8b57-f0a1432456d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3487394841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3487394841
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3130138557
Short name T321
Test name
Test status
Simulation time 3359400436 ps
CPU time 33.09 seconds
Started Jul 03 04:22:09 PM PDT 24
Finished Jul 03 04:22:42 PM PDT 24
Peak memory 216220 kb
Host smart-a0777916-b2cb-459e-b885-39897414ed61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130138557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3130138557
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.4188778728
Short name T246
Test name
Test status
Simulation time 8307485466 ps
CPU time 26.42 seconds
Started Jul 03 04:22:12 PM PDT 24
Finished Jul 03 04:22:39 PM PDT 24
Peak memory 211728 kb
Host smart-815daa5c-d38f-4b95-a69b-3f62ceae5664
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188778728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.4188778728
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1915955356
Short name T144
Test name
Test status
Simulation time 1148300939 ps
CPU time 14.63 seconds
Started Jul 03 04:22:27 PM PDT 24
Finished Jul 03 04:22:42 PM PDT 24
Peak memory 216924 kb
Host smart-04d6c53f-b033-410e-a98c-9d996b6b0e48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915955356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1915955356
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1264810081
Short name T290
Test name
Test status
Simulation time 46214011889 ps
CPU time 489.21 seconds
Started Jul 03 04:22:16 PM PDT 24
Finished Jul 03 04:30:26 PM PDT 24
Peak memory 236240 kb
Host smart-580ddbb9-92d9-4ea4-a2bb-2c47beaa5fe9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264810081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1264810081
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2431798859
Short name T49
Test name
Test status
Simulation time 1321121628 ps
CPU time 18.35 seconds
Started Jul 03 04:22:18 PM PDT 24
Finished Jul 03 04:22:37 PM PDT 24
Peak memory 219164 kb
Host smart-48f68e81-fc79-4a5a-827a-c5afa7c38876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431798859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2431798859
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1952175313
Short name T22
Test name
Test status
Simulation time 5822967995 ps
CPU time 16.4 seconds
Started Jul 03 04:22:19 PM PDT 24
Finished Jul 03 04:22:36 PM PDT 24
Peak memory 219084 kb
Host smart-d20bfc95-7971-41f3-8a4a-33aba30b7367
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1952175313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1952175313
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1752745232
Short name T188
Test name
Test status
Simulation time 5087557171 ps
CPU time 47.44 seconds
Started Jul 03 04:22:14 PM PDT 24
Finished Jul 03 04:23:02 PM PDT 24
Peak memory 217100 kb
Host smart-50eb5525-3829-48b6-9b31-4f8d14375f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752745232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1752745232
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1585056123
Short name T235
Test name
Test status
Simulation time 20755276721 ps
CPU time 84.31 seconds
Started Jul 03 04:22:11 PM PDT 24
Finished Jul 03 04:23:36 PM PDT 24
Peak memory 221948 kb
Host smart-df2d1121-881b-4032-8ffc-b1270a11f2d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585056123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1585056123
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.4241643369
Short name T256
Test name
Test status
Simulation time 23074553159 ps
CPU time 28.98 seconds
Started Jul 03 04:22:15 PM PDT 24
Finished Jul 03 04:22:44 PM PDT 24
Peak memory 217460 kb
Host smart-f337bc04-09fa-4dbb-ab5b-050d0e0978fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241643369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.4241643369
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2079069092
Short name T207
Test name
Test status
Simulation time 26217331986 ps
CPU time 497.39 seconds
Started Jul 03 04:22:20 PM PDT 24
Finished Jul 03 04:30:39 PM PDT 24
Peak memory 234700 kb
Host smart-4ea7dc65-b9f8-473d-b27b-d85885eee195
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079069092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2079069092
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1308990130
Short name T316
Test name
Test status
Simulation time 9573664693 ps
CPU time 32.27 seconds
Started Jul 03 04:22:23 PM PDT 24
Finished Jul 03 04:22:56 PM PDT 24
Peak memory 215576 kb
Host smart-57ffb0ca-af8e-4d8a-8e49-443ec5c0c7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308990130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1308990130
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3690748580
Short name T326
Test name
Test status
Simulation time 362453570 ps
CPU time 20 seconds
Started Jul 03 04:22:15 PM PDT 24
Finished Jul 03 04:22:36 PM PDT 24
Peak memory 215508 kb
Host smart-b5545aa7-662d-4f16-acf3-bc2283922665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690748580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3690748580
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1270358652
Short name T233
Test name
Test status
Simulation time 2888750198 ps
CPU time 42.66 seconds
Started Jul 03 04:22:21 PM PDT 24
Finished Jul 03 04:23:04 PM PDT 24
Peak memory 219256 kb
Host smart-9ce2a88a-6c8d-438f-99ff-2194f1777736
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270358652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1270358652
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3627541026
Short name T311
Test name
Test status
Simulation time 2052756115 ps
CPU time 19.62 seconds
Started Jul 03 04:22:09 PM PDT 24
Finished Jul 03 04:22:29 PM PDT 24
Peak memory 217020 kb
Host smart-391aab95-fabc-4a7a-b661-8b2c3dea11ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627541026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3627541026
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.586524652
Short name T46
Test name
Test status
Simulation time 237676914912 ps
CPU time 652.62 seconds
Started Jul 03 04:22:07 PM PDT 24
Finished Jul 03 04:33:00 PM PDT 24
Peak memory 234548 kb
Host smart-b60e5014-4684-4e38-8b9d-517f3c6b0ab4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586524652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.586524652
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2973651357
Short name T271
Test name
Test status
Simulation time 14747215281 ps
CPU time 60.96 seconds
Started Jul 03 04:22:32 PM PDT 24
Finished Jul 03 04:23:33 PM PDT 24
Peak memory 219240 kb
Host smart-2acda4b5-b08e-4cf2-8740-0863efa67c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973651357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2973651357
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3438936751
Short name T163
Test name
Test status
Simulation time 3495130106 ps
CPU time 28.44 seconds
Started Jul 03 04:22:24 PM PDT 24
Finished Jul 03 04:22:53 PM PDT 24
Peak memory 211236 kb
Host smart-07364099-9783-46da-aad5-6c9d54e9991c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3438936751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3438936751
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2321481296
Short name T15
Test name
Test status
Simulation time 1790358059 ps
CPU time 19.6 seconds
Started Jul 03 04:22:19 PM PDT 24
Finished Jul 03 04:22:39 PM PDT 24
Peak memory 216240 kb
Host smart-6ec2d078-8bff-49ce-ac82-05e3681c2756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321481296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2321481296
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.600220527
Short name T159
Test name
Test status
Simulation time 17436568523 ps
CPU time 83.46 seconds
Started Jul 03 04:22:19 PM PDT 24
Finished Jul 03 04:23:43 PM PDT 24
Peak memory 220512 kb
Host smart-2a618d31-bfe2-41cb-9755-249d8c67e3c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600220527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.600220527
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2250926909
Short name T151
Test name
Test status
Simulation time 1365419884 ps
CPU time 16.13 seconds
Started Jul 03 04:22:10 PM PDT 24
Finished Jul 03 04:22:27 PM PDT 24
Peak memory 217136 kb
Host smart-d130c59d-f440-4592-8117-a44634f5b784
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250926909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2250926909
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3476878981
Short name T12
Test name
Test status
Simulation time 77563911274 ps
CPU time 302.4 seconds
Started Jul 03 04:22:09 PM PDT 24
Finished Jul 03 04:27:12 PM PDT 24
Peak memory 229376 kb
Host smart-2eab82d8-0994-4892-95e5-557371cf3d3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476878981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3476878981
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.299990623
Short name T40
Test name
Test status
Simulation time 59699979072 ps
CPU time 69.76 seconds
Started Jul 03 04:22:38 PM PDT 24
Finished Jul 03 04:23:48 PM PDT 24
Peak memory 219116 kb
Host smart-3fc963e8-454e-4cec-bad7-e880e1cdc1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299990623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.299990623
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2218177566
Short name T175
Test name
Test status
Simulation time 2707738652 ps
CPU time 18.23 seconds
Started Jul 03 04:22:07 PM PDT 24
Finished Jul 03 04:22:25 PM PDT 24
Peak memory 211560 kb
Host smart-0903df21-7cf5-4697-bf02-831edfa83a27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2218177566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2218177566
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2227184743
Short name T363
Test name
Test status
Simulation time 2215348849 ps
CPU time 33.42 seconds
Started Jul 03 04:22:18 PM PDT 24
Finished Jul 03 04:22:52 PM PDT 24
Peak memory 216232 kb
Host smart-7406f961-142e-48aa-ad54-097242e72ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227184743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2227184743
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1057373751
Short name T61
Test name
Test status
Simulation time 68598620193 ps
CPU time 146.26 seconds
Started Jul 03 04:22:06 PM PDT 24
Finished Jul 03 04:24:32 PM PDT 24
Peak memory 220508 kb
Host smart-354d79db-9a3b-4df9-8efe-eb96e4f631f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057373751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1057373751
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1723257202
Short name T57
Test name
Test status
Simulation time 139281912805 ps
CPU time 1605.05 seconds
Started Jul 03 04:22:13 PM PDT 24
Finished Jul 03 04:48:59 PM PDT 24
Peak memory 248624 kb
Host smart-c0822711-7878-4f58-a214-ee89f33bde44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723257202 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.1723257202
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.801849921
Short name T35
Test name
Test status
Simulation time 3446641089 ps
CPU time 28.79 seconds
Started Jul 03 04:22:23 PM PDT 24
Finished Jul 03 04:22:52 PM PDT 24
Peak memory 217096 kb
Host smart-25e94d6a-a399-42dd-8a31-90c64eb3d396
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801849921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.801849921
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1940067146
Short name T260
Test name
Test status
Simulation time 10603559156 ps
CPU time 115.01 seconds
Started Jul 03 04:22:08 PM PDT 24
Finished Jul 03 04:24:04 PM PDT 24
Peak memory 235884 kb
Host smart-78c3738b-3c34-4418-998d-4b872344ba03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940067146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1940067146
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1279280610
Short name T39
Test name
Test status
Simulation time 52590837316 ps
CPU time 50.63 seconds
Started Jul 03 04:22:12 PM PDT 24
Finished Jul 03 04:23:03 PM PDT 24
Peak memory 219168 kb
Host smart-d8d8d0cb-2a3e-41bd-9856-f2b7a95dd22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279280610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1279280610
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1968961235
Short name T225
Test name
Test status
Simulation time 1103068237 ps
CPU time 17.38 seconds
Started Jul 03 04:22:19 PM PDT 24
Finished Jul 03 04:22:36 PM PDT 24
Peak memory 211296 kb
Host smart-0afd6a76-d11f-493b-901e-6ecdb54321c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1968961235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1968961235
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.454119282
Short name T220
Test name
Test status
Simulation time 9783749322 ps
CPU time 39.78 seconds
Started Jul 03 04:22:09 PM PDT 24
Finished Jul 03 04:22:49 PM PDT 24
Peak memory 217364 kb
Host smart-df7d04ee-0ecb-47d7-9da8-322e6d91709f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454119282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.454119282
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1477923746
Short name T360
Test name
Test status
Simulation time 5954329387 ps
CPU time 44.66 seconds
Started Jul 03 04:22:22 PM PDT 24
Finished Jul 03 04:23:07 PM PDT 24
Peak memory 218972 kb
Host smart-84bcd1c3-fe04-4211-94d8-0cabd9f15a85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477923746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1477923746
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.54532291
Short name T68
Test name
Test status
Simulation time 995304975 ps
CPU time 10.65 seconds
Started Jul 03 04:22:16 PM PDT 24
Finished Jul 03 04:22:27 PM PDT 24
Peak memory 217112 kb
Host smart-d538b4f7-4ec6-443a-bc31-1589b3fc42d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54532291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.54532291
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2108620104
Short name T45
Test name
Test status
Simulation time 138299606618 ps
CPU time 412.39 seconds
Started Jul 03 04:22:07 PM PDT 24
Finished Jul 03 04:29:00 PM PDT 24
Peak memory 237700 kb
Host smart-0808d2a0-8e52-4aa4-9f4e-2dccb7c243db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108620104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2108620104
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3927624004
Short name T350
Test name
Test status
Simulation time 43687624377 ps
CPU time 56.33 seconds
Started Jul 03 04:22:44 PM PDT 24
Finished Jul 03 04:23:41 PM PDT 24
Peak memory 219256 kb
Host smart-b160405f-e11c-4ce6-a66a-82ffa4f2ba4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927624004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3927624004
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1658320153
Short name T250
Test name
Test status
Simulation time 11013669261 ps
CPU time 25.96 seconds
Started Jul 03 04:22:07 PM PDT 24
Finished Jul 03 04:22:33 PM PDT 24
Peak memory 217600 kb
Host smart-b00ad2a4-037e-406a-b964-4485ef93e47e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1658320153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1658320153
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.3092564091
Short name T226
Test name
Test status
Simulation time 24781123570 ps
CPU time 58.62 seconds
Started Jul 03 04:22:35 PM PDT 24
Finished Jul 03 04:23:34 PM PDT 24
Peak memory 214516 kb
Host smart-64e82b7e-0a59-477c-b58f-7c38d0c003da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092564091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.3092564091
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.23948642
Short name T304
Test name
Test status
Simulation time 348085008 ps
CPU time 14.08 seconds
Started Jul 03 04:22:22 PM PDT 24
Finished Jul 03 04:22:37 PM PDT 24
Peak memory 219160 kb
Host smart-48a538b8-2d23-4940-8d7d-8f24b4914d14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23948642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 39.rom_ctrl_stress_all.23948642
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3798031805
Short name T8
Test name
Test status
Simulation time 759548417 ps
CPU time 12.81 seconds
Started Jul 03 04:22:49 PM PDT 24
Finished Jul 03 04:23:03 PM PDT 24
Peak memory 215076 kb
Host smart-79ceb3df-ac33-43b4-8285-b87a77e2ea72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798031805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3798031805
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.700806670
Short name T197
Test name
Test status
Simulation time 10570573453 ps
CPU time 201.69 seconds
Started Jul 03 04:22:58 PM PDT 24
Finished Jul 03 04:26:21 PM PDT 24
Peak memory 218628 kb
Host smart-6b074a72-7843-41f3-a9a7-24a8e5cb6a1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700806670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.700806670
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.148476685
Short name T305
Test name
Test status
Simulation time 5944402996 ps
CPU time 53.39 seconds
Started Jul 03 04:22:49 PM PDT 24
Finished Jul 03 04:23:44 PM PDT 24
Peak memory 218756 kb
Host smart-4ec8e0e5-4aa7-4b96-bb7c-35c015f05b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148476685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.148476685
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2026461752
Short name T277
Test name
Test status
Simulation time 1928647999 ps
CPU time 10.12 seconds
Started Jul 03 04:22:59 PM PDT 24
Finished Jul 03 04:23:11 PM PDT 24
Peak memory 218936 kb
Host smart-a20f9e5c-f890-48cc-a9ad-6c867ac41a05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2026461752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2026461752
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.4219336350
Short name T31
Test name
Test status
Simulation time 13726953175 ps
CPU time 235.69 seconds
Started Jul 03 04:23:01 PM PDT 24
Finished Jul 03 04:27:00 PM PDT 24
Peak memory 235340 kb
Host smart-ffc503b8-7b5d-4e04-9c71-d08127c1861e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219336350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.4219336350
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.4091353163
Short name T131
Test name
Test status
Simulation time 1045616426 ps
CPU time 22.16 seconds
Started Jul 03 04:21:53 PM PDT 24
Finished Jul 03 04:22:16 PM PDT 24
Peak memory 216092 kb
Host smart-6535a359-b01a-4651-8734-013569181575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091353163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.4091353163
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2502330714
Short name T83
Test name
Test status
Simulation time 1213871972 ps
CPU time 73.24 seconds
Started Jul 03 04:23:01 PM PDT 24
Finished Jul 03 04:24:17 PM PDT 24
Peak memory 218976 kb
Host smart-4d24c411-11e5-448a-9f03-973b225b20f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502330714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2502330714
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.4142042045
Short name T141
Test name
Test status
Simulation time 167585324 ps
CPU time 8.29 seconds
Started Jul 03 04:23:35 PM PDT 24
Finished Jul 03 04:23:44 PM PDT 24
Peak memory 217036 kb
Host smart-d04ad566-fa56-47fc-a561-eb372ec59fdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142042045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.4142042045
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4279093823
Short name T308
Test name
Test status
Simulation time 6783535736 ps
CPU time 228.64 seconds
Started Jul 03 04:22:57 PM PDT 24
Finished Jul 03 04:26:47 PM PDT 24
Peak memory 236844 kb
Host smart-ce12b0a8-583b-40c0-b802-d3b79f649fa3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279093823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.4279093823
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.4004471132
Short name T292
Test name
Test status
Simulation time 1941574243 ps
CPU time 18.68 seconds
Started Jul 03 04:22:27 PM PDT 24
Finished Jul 03 04:22:46 PM PDT 24
Peak memory 219184 kb
Host smart-2ecfb5e2-e79a-4372-ab84-68bb48c4f1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004471132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.4004471132
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.10286803
Short name T24
Test name
Test status
Simulation time 14009874967 ps
CPU time 30.87 seconds
Started Jul 03 04:22:24 PM PDT 24
Finished Jul 03 04:22:56 PM PDT 24
Peak memory 211952 kb
Host smart-44bf86d9-5d5e-4bd4-a53e-63ad72eedd9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=10286803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.10286803
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.4051571749
Short name T84
Test name
Test status
Simulation time 14707277900 ps
CPU time 74.63 seconds
Started Jul 03 04:22:17 PM PDT 24
Finished Jul 03 04:23:32 PM PDT 24
Peak memory 217372 kb
Host smart-e577729a-4ed9-444e-aa4b-5ec258adf2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051571749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.4051571749
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1978973565
Short name T186
Test name
Test status
Simulation time 7462973480 ps
CPU time 64.31 seconds
Started Jul 03 04:22:14 PM PDT 24
Finished Jul 03 04:23:19 PM PDT 24
Peak memory 219004 kb
Host smart-a1ed4117-8e2b-448e-b40f-7693ba5f9bb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978973565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1978973565
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1805996143
Short name T288
Test name
Test status
Simulation time 2655880064 ps
CPU time 23.7 seconds
Started Jul 03 04:22:20 PM PDT 24
Finished Jul 03 04:22:45 PM PDT 24
Peak memory 217180 kb
Host smart-dd6fdf35-1b73-4d27-9c07-26380478bffe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805996143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1805996143
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2512896318
Short name T137
Test name
Test status
Simulation time 4271305332 ps
CPU time 46.48 seconds
Started Jul 03 04:22:53 PM PDT 24
Finished Jul 03 04:23:40 PM PDT 24
Peak memory 219280 kb
Host smart-b6889a73-74ef-48a2-9a10-dd34cb0d80fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512896318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2512896318
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2568170389
Short name T244
Test name
Test status
Simulation time 1645735537 ps
CPU time 20.16 seconds
Started Jul 03 04:22:57 PM PDT 24
Finished Jul 03 04:23:18 PM PDT 24
Peak memory 219204 kb
Host smart-fb5abecb-ff5f-47cc-8e13-98a76cb8b9b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2568170389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2568170389
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3784964389
Short name T282
Test name
Test status
Simulation time 41732314326 ps
CPU time 47.29 seconds
Started Jul 03 04:22:24 PM PDT 24
Finished Jul 03 04:23:12 PM PDT 24
Peak memory 215508 kb
Host smart-9e976c62-2685-4477-89d8-30f282cf8613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784964389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3784964389
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3917460396
Short name T278
Test name
Test status
Simulation time 7283782888 ps
CPU time 26.75 seconds
Started Jul 03 04:22:20 PM PDT 24
Finished Jul 03 04:22:48 PM PDT 24
Peak memory 216564 kb
Host smart-772ce2d5-e8a8-42a4-a74e-a3f62d8727d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917460396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3917460396
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.4194293100
Short name T307
Test name
Test status
Simulation time 172634140 ps
CPU time 8.43 seconds
Started Jul 03 04:22:57 PM PDT 24
Finished Jul 03 04:23:06 PM PDT 24
Peak memory 216920 kb
Host smart-c2664029-9b77-4dcf-9669-e1573d8372a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194293100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.4194293100
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.781459961
Short name T243
Test name
Test status
Simulation time 36451539563 ps
CPU time 435.61 seconds
Started Jul 03 04:22:20 PM PDT 24
Finished Jul 03 04:29:36 PM PDT 24
Peak memory 239868 kb
Host smart-3b134357-9eb6-44b2-b818-312956cc2aee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781459961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.781459961
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3039374418
Short name T150
Test name
Test status
Simulation time 25597762665 ps
CPU time 55.35 seconds
Started Jul 03 04:22:33 PM PDT 24
Finished Jul 03 04:23:29 PM PDT 24
Peak memory 219140 kb
Host smart-d004b7f5-93f8-492c-9dd1-52b1cf5c88c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039374418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3039374418
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1867739120
Short name T232
Test name
Test status
Simulation time 718367678 ps
CPU time 10.03 seconds
Started Jul 03 04:22:31 PM PDT 24
Finished Jul 03 04:22:41 PM PDT 24
Peak memory 219180 kb
Host smart-077abd4c-3776-40d3-983b-5da176be2b4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1867739120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1867739120
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2982073638
Short name T152
Test name
Test status
Simulation time 10618844797 ps
CPU time 46.62 seconds
Started Jul 03 04:22:32 PM PDT 24
Finished Jul 03 04:23:19 PM PDT 24
Peak memory 217144 kb
Host smart-af67da93-dca0-41a7-8456-3b49cba75d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982073638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2982073638
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.113131572
Short name T240
Test name
Test status
Simulation time 7862232031 ps
CPU time 80.34 seconds
Started Jul 03 04:22:22 PM PDT 24
Finished Jul 03 04:23:43 PM PDT 24
Peak memory 217260 kb
Host smart-650c12c0-3e82-4781-999e-3b5e150a224d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113131572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.113131572
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.381217957
Short name T179
Test name
Test status
Simulation time 15221674620 ps
CPU time 15.44 seconds
Started Jul 03 04:22:35 PM PDT 24
Finished Jul 03 04:22:51 PM PDT 24
Peak memory 212944 kb
Host smart-27ab825f-3c66-4458-8d64-fdf97e8b868f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381217957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.381217957
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3517257420
Short name T219
Test name
Test status
Simulation time 57806796794 ps
CPU time 551.61 seconds
Started Jul 03 04:22:14 PM PDT 24
Finished Jul 03 04:31:26 PM PDT 24
Peak memory 239404 kb
Host smart-cd5bae35-40c7-4cd8-98d1-c00faeef6adf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517257420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3517257420
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1208015585
Short name T357
Test name
Test status
Simulation time 2357106892 ps
CPU time 18.79 seconds
Started Jul 03 04:22:31 PM PDT 24
Finished Jul 03 04:22:50 PM PDT 24
Peak memory 219240 kb
Host smart-3eecddc9-44f6-477e-be42-4a386d4f9762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208015585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1208015585
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2887273858
Short name T234
Test name
Test status
Simulation time 3713449285 ps
CPU time 30.43 seconds
Started Jul 03 04:22:47 PM PDT 24
Finished Jul 03 04:23:18 PM PDT 24
Peak memory 211336 kb
Host smart-5a456a05-b9b1-4e65-a66c-2da224e78c84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2887273858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2887273858
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.697216524
Short name T59
Test name
Test status
Simulation time 7885589010 ps
CPU time 88.99 seconds
Started Jul 03 04:22:34 PM PDT 24
Finished Jul 03 04:24:03 PM PDT 24
Peak memory 217376 kb
Host smart-7534e1d3-1970-484b-a75f-9127049fd775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697216524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.697216524
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3665375142
Short name T216
Test name
Test status
Simulation time 3973139965 ps
CPU time 52.82 seconds
Started Jul 03 04:23:09 PM PDT 24
Finished Jul 03 04:24:02 PM PDT 24
Peak memory 219228 kb
Host smart-f0285698-1e04-498d-bbb2-84b2f086de62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665375142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3665375142
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.906118270
Short name T157
Test name
Test status
Simulation time 10532536012 ps
CPU time 23.48 seconds
Started Jul 03 04:22:20 PM PDT 24
Finished Jul 03 04:22:49 PM PDT 24
Peak memory 217332 kb
Host smart-fcc2b90b-ad9a-4591-8b55-7b6471f66c75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906118270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.906118270
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3547494899
Short name T272
Test name
Test status
Simulation time 29915725385 ps
CPU time 269.21 seconds
Started Jul 03 04:22:14 PM PDT 24
Finished Jul 03 04:26:44 PM PDT 24
Peak memory 230220 kb
Host smart-fee9ea72-9802-4dae-b85b-786492d79ca5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547494899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3547494899
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1166058139
Short name T332
Test name
Test status
Simulation time 15716178906 ps
CPU time 43.82 seconds
Started Jul 03 04:23:08 PM PDT 24
Finished Jul 03 04:23:52 PM PDT 24
Peak memory 219352 kb
Host smart-d4543d96-9c04-4bcb-a813-770f373c8a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166058139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1166058139
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.300067413
Short name T300
Test name
Test status
Simulation time 4755573823 ps
CPU time 16.56 seconds
Started Jul 03 04:23:31 PM PDT 24
Finished Jul 03 04:23:48 PM PDT 24
Peak memory 219352 kb
Host smart-7addfe50-6d14-4900-b7ad-1cc6302aef04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=300067413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.300067413
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3680296407
Short name T293
Test name
Test status
Simulation time 348466699 ps
CPU time 19.91 seconds
Started Jul 03 04:22:14 PM PDT 24
Finished Jul 03 04:22:35 PM PDT 24
Peak memory 216252 kb
Host smart-b4c90f10-e5c4-4133-868d-2d44d425759c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680296407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3680296407
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3142602251
Short name T354
Test name
Test status
Simulation time 60344569394 ps
CPU time 129.04 seconds
Started Jul 03 04:22:38 PM PDT 24
Finished Jul 03 04:24:47 PM PDT 24
Peak memory 220612 kb
Host smart-66c2a97c-1015-4476-a2d5-f3305e14084a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142602251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3142602251
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1351069182
Short name T287
Test name
Test status
Simulation time 4453081870 ps
CPU time 14.92 seconds
Started Jul 03 04:22:18 PM PDT 24
Finished Jul 03 04:22:33 PM PDT 24
Peak memory 217352 kb
Host smart-bdbc27f8-0b65-436f-ae61-ed3a141baca3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351069182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1351069182
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.795480382
Short name T237
Test name
Test status
Simulation time 30672101585 ps
CPU time 310.04 seconds
Started Jul 03 04:22:45 PM PDT 24
Finished Jul 03 04:27:55 PM PDT 24
Peak memory 244816 kb
Host smart-03a7759e-0088-4793-a411-2f96a3b3d5a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795480382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.795480382
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3861179280
Short name T275
Test name
Test status
Simulation time 6571394349 ps
CPU time 29.85 seconds
Started Jul 03 04:22:15 PM PDT 24
Finished Jul 03 04:22:45 PM PDT 24
Peak memory 219244 kb
Host smart-57371492-3b49-444c-962a-03dc9992cbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861179280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3861179280
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.4284717379
Short name T143
Test name
Test status
Simulation time 1603060995 ps
CPU time 10.13 seconds
Started Jul 03 04:22:29 PM PDT 24
Finished Jul 03 04:22:39 PM PDT 24
Peak memory 219172 kb
Host smart-01e5ccf4-35ee-4ae7-8ec9-2fe6a312408d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4284717379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.4284717379
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2872681251
Short name T156
Test name
Test status
Simulation time 3857493363 ps
CPU time 19.84 seconds
Started Jul 03 04:22:14 PM PDT 24
Finished Jul 03 04:22:34 PM PDT 24
Peak memory 216676 kb
Host smart-509bdd5f-b9e3-4fed-8ed1-f3f607f3bf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872681251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2872681251
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3944594127
Short name T323
Test name
Test status
Simulation time 32253491786 ps
CPU time 76.81 seconds
Started Jul 03 04:22:27 PM PDT 24
Finished Jul 03 04:23:44 PM PDT 24
Peak memory 217688 kb
Host smart-7a0d6da9-ec71-4724-8284-40a61f3dc7dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944594127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3944594127
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1919386834
Short name T224
Test name
Test status
Simulation time 688345496 ps
CPU time 8.73 seconds
Started Jul 03 04:22:14 PM PDT 24
Finished Jul 03 04:22:23 PM PDT 24
Peak memory 216940 kb
Host smart-96449bde-98e9-45cd-9e03-a8c1eeed696e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919386834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1919386834
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2000013674
Short name T334
Test name
Test status
Simulation time 36282199941 ps
CPU time 349.34 seconds
Started Jul 03 04:22:16 PM PDT 24
Finished Jul 03 04:28:06 PM PDT 24
Peak memory 234288 kb
Host smart-c6d6ed8c-f77c-48f4-8ec6-01db12c98fdd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000013674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2000013674
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.659130763
Short name T9
Test name
Test status
Simulation time 20466190935 ps
CPU time 47.3 seconds
Started Jul 03 04:22:32 PM PDT 24
Finished Jul 03 04:23:20 PM PDT 24
Peak memory 219204 kb
Host smart-58de7532-da20-49db-a2c4-8709bdae94fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659130763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.659130763
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.638396757
Short name T72
Test name
Test status
Simulation time 3739643782 ps
CPU time 30.3 seconds
Started Jul 03 04:22:33 PM PDT 24
Finished Jul 03 04:23:04 PM PDT 24
Peak memory 219288 kb
Host smart-ef31793a-6c2f-44b1-9115-103750593aa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=638396757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.638396757
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.433346447
Short name T252
Test name
Test status
Simulation time 3632547640 ps
CPU time 35.51 seconds
Started Jul 03 04:22:24 PM PDT 24
Finished Jul 03 04:23:00 PM PDT 24
Peak memory 214832 kb
Host smart-db2703ec-8803-4048-bf51-7c73ef66f680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433346447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.433346447
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.531887981
Short name T14
Test name
Test status
Simulation time 8751187605 ps
CPU time 76.88 seconds
Started Jul 03 04:22:32 PM PDT 24
Finished Jul 03 04:23:50 PM PDT 24
Peak memory 218512 kb
Host smart-067cf9cc-c7b7-4a17-95ec-909dfe711823
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531887981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.531887981
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2396952972
Short name T69
Test name
Test status
Simulation time 16819871108 ps
CPU time 32.31 seconds
Started Jul 03 04:22:22 PM PDT 24
Finished Jul 03 04:22:55 PM PDT 24
Peak memory 213204 kb
Host smart-290ef8a7-ab43-40ba-bb1b-37faa96e566d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396952972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2396952972
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2005770384
Short name T315
Test name
Test status
Simulation time 204867020514 ps
CPU time 567.63 seconds
Started Jul 03 04:22:21 PM PDT 24
Finished Jul 03 04:31:50 PM PDT 24
Peak memory 240768 kb
Host smart-6403e521-13fc-423a-87a6-4fc3d4ec76e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005770384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2005770384
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3365569954
Short name T38
Test name
Test status
Simulation time 4258528137 ps
CPU time 42.15 seconds
Started Jul 03 04:22:37 PM PDT 24
Finished Jul 03 04:23:19 PM PDT 24
Peak memory 219284 kb
Host smart-f8a2dc78-5c13-4d30-8bd1-a99c587ff9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365569954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3365569954
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.366212565
Short name T36
Test name
Test status
Simulation time 527936968 ps
CPU time 14.09 seconds
Started Jul 03 04:22:13 PM PDT 24
Finished Jul 03 04:22:28 PM PDT 24
Peak memory 219236 kb
Host smart-00e5f550-247d-4241-8e70-bb74144e9d42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=366212565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.366212565
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2652791400
Short name T312
Test name
Test status
Simulation time 1000703914 ps
CPU time 26.82 seconds
Started Jul 03 04:22:37 PM PDT 24
Finished Jul 03 04:23:04 PM PDT 24
Peak memory 216284 kb
Host smart-da7a8b46-191b-4407-9df6-2f0446034994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652791400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2652791400
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3777204033
Short name T87
Test name
Test status
Simulation time 1265869813 ps
CPU time 23.02 seconds
Started Jul 03 04:22:20 PM PDT 24
Finished Jul 03 04:22:44 PM PDT 24
Peak memory 217536 kb
Host smart-927ce6ca-5af2-4de2-b411-7cc4df58aca9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777204033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3777204033
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1806902612
Short name T54
Test name
Test status
Simulation time 74428725470 ps
CPU time 2705.96 seconds
Started Jul 03 04:22:30 PM PDT 24
Finished Jul 03 05:07:36 PM PDT 24
Peak memory 233668 kb
Host smart-e6100139-1898-4ddc-baa9-9d2aa85099e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806902612 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.1806902612
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3786611691
Short name T273
Test name
Test status
Simulation time 789006306 ps
CPU time 10.62 seconds
Started Jul 03 04:22:25 PM PDT 24
Finished Jul 03 04:22:36 PM PDT 24
Peak memory 217144 kb
Host smart-7bdc5b38-40ad-4ec6-ae25-1195c4af115b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786611691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3786611691
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2574933185
Short name T184
Test name
Test status
Simulation time 14272345057 ps
CPU time 174.4 seconds
Started Jul 03 04:22:30 PM PDT 24
Finished Jul 03 04:25:25 PM PDT 24
Peak memory 235984 kb
Host smart-0f402e7c-7d42-4870-905a-220078fabd54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574933185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2574933185
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3273760306
Short name T133
Test name
Test status
Simulation time 10422553639 ps
CPU time 46.85 seconds
Started Jul 03 04:22:37 PM PDT 24
Finished Jul 03 04:23:24 PM PDT 24
Peak memory 219240 kb
Host smart-e0b6fc15-4263-4893-abc2-4f004d5ebc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273760306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3273760306
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1221158259
Short name T190
Test name
Test status
Simulation time 3480393184 ps
CPU time 10.06 seconds
Started Jul 03 04:22:48 PM PDT 24
Finished Jul 03 04:22:58 PM PDT 24
Peak memory 219248 kb
Host smart-db09a8bd-32b8-480e-aa04-4887ee2adc1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1221158259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1221158259
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2137679570
Short name T178
Test name
Test status
Simulation time 9819073296 ps
CPU time 88.78 seconds
Started Jul 03 04:22:19 PM PDT 24
Finished Jul 03 04:23:50 PM PDT 24
Peak memory 216988 kb
Host smart-79a764bc-5972-421a-b43b-6ba5e8f6c57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137679570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2137679570
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3168205257
Short name T145
Test name
Test status
Simulation time 15129580018 ps
CPU time 63.45 seconds
Started Jul 03 04:22:26 PM PDT 24
Finished Jul 03 04:23:30 PM PDT 24
Peak memory 219284 kb
Host smart-2ce83dc4-2983-4434-ad94-e6e0a6b97c81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168205257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3168205257
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.153174066
Short name T108
Test name
Test status
Simulation time 69729779784 ps
CPU time 2665.13 seconds
Started Jul 03 04:22:42 PM PDT 24
Finished Jul 03 05:07:08 PM PDT 24
Peak memory 251856 kb
Host smart-6405c364-ff58-47e2-91c0-a6fb47023d3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153174066 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.153174066
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1283741317
Short name T348
Test name
Test status
Simulation time 16959942630 ps
CPU time 34.27 seconds
Started Jul 03 04:22:33 PM PDT 24
Finished Jul 03 04:23:08 PM PDT 24
Peak memory 217460 kb
Host smart-5e4f32e8-bb14-4e65-a46b-cc08dd03d11b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283741317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1283741317
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.335981613
Short name T176
Test name
Test status
Simulation time 32850891770 ps
CPU time 393.3 seconds
Started Jul 03 04:22:25 PM PDT 24
Finished Jul 03 04:28:59 PM PDT 24
Peak memory 219408 kb
Host smart-a3083c80-bad0-4619-ab7d-c9525aeee616
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335981613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.335981613
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3754440809
Short name T359
Test name
Test status
Simulation time 674877049 ps
CPU time 18.51 seconds
Started Jul 03 04:22:33 PM PDT 24
Finished Jul 03 04:22:53 PM PDT 24
Peak memory 219208 kb
Host smart-2d5c787b-292a-4779-af6e-6f03dd2f6bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754440809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3754440809
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.504944716
Short name T71
Test name
Test status
Simulation time 13566670819 ps
CPU time 19.18 seconds
Started Jul 03 04:22:34 PM PDT 24
Finished Jul 03 04:22:53 PM PDT 24
Peak memory 217992 kb
Host smart-ff15fe94-5a61-4597-b444-440d34f47a62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=504944716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.504944716
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.623748038
Short name T263
Test name
Test status
Simulation time 349973704 ps
CPU time 19.79 seconds
Started Jul 03 04:22:25 PM PDT 24
Finished Jul 03 04:22:45 PM PDT 24
Peak memory 215980 kb
Host smart-4e767616-071a-4f12-a762-2e440b6eabbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623748038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.623748038
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1565326969
Short name T286
Test name
Test status
Simulation time 26380189787 ps
CPU time 143.35 seconds
Started Jul 03 04:22:29 PM PDT 24
Finished Jul 03 04:24:53 PM PDT 24
Peak memory 220916 kb
Host smart-fb668028-85f0-4613-a6bd-84b05a5da799
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565326969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1565326969
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.143748907
Short name T319
Test name
Test status
Simulation time 37484784214 ps
CPU time 30.59 seconds
Started Jul 03 04:22:49 PM PDT 24
Finished Jul 03 04:23:21 PM PDT 24
Peak memory 215828 kb
Host smart-60fdde82-e66d-45c1-8f09-ec2351314498
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143748907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.143748907
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3761054339
Short name T41
Test name
Test status
Simulation time 308861981027 ps
CPU time 715.51 seconds
Started Jul 03 04:21:36 PM PDT 24
Finished Jul 03 04:33:32 PM PDT 24
Peak memory 237924 kb
Host smart-b1cc2362-dde9-4f41-b516-92bebf4ba5e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761054339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3761054339
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.922445423
Short name T279
Test name
Test status
Simulation time 1376508425 ps
CPU time 19.69 seconds
Started Jul 03 04:21:39 PM PDT 24
Finished Jul 03 04:21:59 PM PDT 24
Peak memory 219200 kb
Host smart-3c79a561-05a0-4345-b1cd-364744fe8389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922445423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.922445423
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3629474216
Short name T169
Test name
Test status
Simulation time 3412329154 ps
CPU time 12.24 seconds
Started Jul 03 04:23:01 PM PDT 24
Finished Jul 03 04:23:16 PM PDT 24
Peak memory 218356 kb
Host smart-df434365-f923-41ed-a6cd-1fb77112d20d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3629474216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3629474216
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2368693917
Short name T329
Test name
Test status
Simulation time 22413755381 ps
CPU time 55.92 seconds
Started Jul 03 04:22:58 PM PDT 24
Finished Jul 03 04:23:55 PM PDT 24
Peak memory 216484 kb
Host smart-6698d933-6d8b-4d20-a37a-ff7e908ad6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368693917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2368693917
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.292687857
Short name T303
Test name
Test status
Simulation time 2207574236 ps
CPU time 33.08 seconds
Started Jul 03 04:22:51 PM PDT 24
Finished Jul 03 04:23:26 PM PDT 24
Peak memory 218692 kb
Host smart-553d32cd-4a9a-47b6-8933-cccbd1c6d0a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292687857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.292687857
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1394839578
Short name T195
Test name
Test status
Simulation time 4240972235 ps
CPU time 32.89 seconds
Started Jul 03 04:23:01 PM PDT 24
Finished Jul 03 04:23:37 PM PDT 24
Peak memory 216808 kb
Host smart-34468f8b-2f19-4843-bda8-0520f46a414a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394839578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1394839578
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.395918254
Short name T285
Test name
Test status
Simulation time 12108272732 ps
CPU time 253.98 seconds
Started Jul 03 04:21:53 PM PDT 24
Finished Jul 03 04:26:08 PM PDT 24
Peak memory 237868 kb
Host smart-ae43005d-f27f-4d13-b787-72b8dcd6877b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395918254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.395918254
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1519760753
Short name T192
Test name
Test status
Simulation time 16006326709 ps
CPU time 63.39 seconds
Started Jul 03 04:21:41 PM PDT 24
Finished Jul 03 04:22:44 PM PDT 24
Peak memory 219288 kb
Host smart-f4e9bf10-7763-40f5-aac7-11642463fcaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519760753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1519760753
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3239215894
Short name T269
Test name
Test status
Simulation time 7002680941 ps
CPU time 29.33 seconds
Started Jul 03 04:22:59 PM PDT 24
Finished Jul 03 04:23:30 PM PDT 24
Peak memory 218996 kb
Host smart-21c39bec-2645-4ffd-a517-14191c607b7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3239215894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3239215894
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1295059493
Short name T170
Test name
Test status
Simulation time 46091847415 ps
CPU time 74.36 seconds
Started Jul 03 04:23:01 PM PDT 24
Finished Jul 03 04:24:18 PM PDT 24
Peak memory 216732 kb
Host smart-3f3b2154-d19c-49ef-8ade-13c2ad7f14bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295059493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1295059493
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.970571714
Short name T336
Test name
Test status
Simulation time 3443584138 ps
CPU time 51.9 seconds
Started Jul 03 04:22:56 PM PDT 24
Finished Jul 03 04:23:49 PM PDT 24
Peak memory 218948 kb
Host smart-b14fd826-08a3-4ff2-bff0-0ed178e69669
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970571714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.970571714
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2743182399
Short name T165
Test name
Test status
Simulation time 660825551 ps
CPU time 8.29 seconds
Started Jul 03 04:21:43 PM PDT 24
Finished Jul 03 04:21:52 PM PDT 24
Peak memory 213120 kb
Host smart-7f70f727-91bc-4713-9460-0510f6680ffc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743182399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2743182399
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3735043043
Short name T218
Test name
Test status
Simulation time 305050830080 ps
CPU time 718.98 seconds
Started Jul 03 04:23:02 PM PDT 24
Finished Jul 03 04:35:04 PM PDT 24
Peak memory 236788 kb
Host smart-577ad910-ec99-4bff-8af6-601f2eb6a587
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735043043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3735043043
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.519992420
Short name T164
Test name
Test status
Simulation time 355544268 ps
CPU time 10.13 seconds
Started Jul 03 04:22:49 PM PDT 24
Finished Jul 03 04:23:00 PM PDT 24
Peak memory 217300 kb
Host smart-d845c7c2-bf3f-4ae2-8631-0206586f052f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=519992420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.519992420
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3950186867
Short name T213
Test name
Test status
Simulation time 3540272966 ps
CPU time 23.35 seconds
Started Jul 03 04:23:01 PM PDT 24
Finished Jul 03 04:23:27 PM PDT 24
Peak memory 216616 kb
Host smart-d3df7660-fe9d-44c9-9388-9081d9777605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950186867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3950186867
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1420974063
Short name T270
Test name
Test status
Simulation time 8419331303 ps
CPU time 85.97 seconds
Started Jul 03 04:22:49 PM PDT 24
Finished Jul 03 04:24:16 PM PDT 24
Peak memory 217248 kb
Host smart-cace079c-2cbc-4d7b-bb93-43f4b80a942c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420974063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1420974063
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1451695672
Short name T242
Test name
Test status
Simulation time 4656811191 ps
CPU time 21.26 seconds
Started Jul 03 04:23:02 PM PDT 24
Finished Jul 03 04:23:26 PM PDT 24
Peak memory 217228 kb
Host smart-945db54a-3041-4466-be5d-9ba1bfcf04cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451695672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1451695672
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.4002658930
Short name T200
Test name
Test status
Simulation time 326283024784 ps
CPU time 494.29 seconds
Started Jul 03 04:23:07 PM PDT 24
Finished Jul 03 04:31:22 PM PDT 24
Peak memory 241592 kb
Host smart-dd3c2f47-1020-4ce2-9aae-50d0a656fcaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002658930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.4002658930
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.822755829
Short name T181
Test name
Test status
Simulation time 24325820327 ps
CPU time 58.43 seconds
Started Jul 03 04:21:41 PM PDT 24
Finished Jul 03 04:22:40 PM PDT 24
Peak memory 219228 kb
Host smart-e46c3c39-b4f1-416c-a17b-a96400dd840f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822755829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.822755829
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.430019862
Short name T255
Test name
Test status
Simulation time 3467443362 ps
CPU time 29.8 seconds
Started Jul 03 04:21:41 PM PDT 24
Finished Jul 03 04:22:11 PM PDT 24
Peak memory 219256 kb
Host smart-61490b98-b9b0-4ac3-a185-e31090d46c22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=430019862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.430019862
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3978790993
Short name T299
Test name
Test status
Simulation time 10987558755 ps
CPU time 50.49 seconds
Started Jul 03 04:21:52 PM PDT 24
Finished Jul 03 04:22:43 PM PDT 24
Peak memory 215324 kb
Host smart-b9c39034-fb42-4fd1-80a7-1a4bf7972e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978790993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3978790993
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3034994668
Short name T327
Test name
Test status
Simulation time 41211191312 ps
CPU time 85.05 seconds
Started Jul 03 04:23:06 PM PDT 24
Finished Jul 03 04:24:32 PM PDT 24
Peak memory 218580 kb
Host smart-3158b48a-30c2-4c37-bdf1-c3e8cfda2f90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034994668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3034994668
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.417633389
Short name T146
Test name
Test status
Simulation time 7761376059 ps
CPU time 25.18 seconds
Started Jul 03 04:21:47 PM PDT 24
Finished Jul 03 04:22:13 PM PDT 24
Peak memory 217440 kb
Host smart-c01828e2-6eda-4979-980a-fd69d45c4d42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417633389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.417633389
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2402891413
Short name T283
Test name
Test status
Simulation time 102133461234 ps
CPU time 515.35 seconds
Started Jul 03 04:21:52 PM PDT 24
Finished Jul 03 04:30:28 PM PDT 24
Peak memory 239096 kb
Host smart-64fb6b13-4fc3-48bc-ba0a-69a04cd9deb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402891413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2402891413
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.425387385
Short name T253
Test name
Test status
Simulation time 28374396450 ps
CPU time 59.83 seconds
Started Jul 03 04:21:48 PM PDT 24
Finished Jul 03 04:22:48 PM PDT 24
Peak memory 219224 kb
Host smart-ee434877-6dd0-41f7-9d25-8ad4c3acd19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425387385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.425387385
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.869566161
Short name T185
Test name
Test status
Simulation time 2103563217 ps
CPU time 13.67 seconds
Started Jul 03 04:23:06 PM PDT 24
Finished Jul 03 04:23:21 PM PDT 24
Peak memory 209992 kb
Host smart-e6173280-fb0a-4020-a9c0-4b45970ae776
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=869566161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.869566161
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3537829572
Short name T208
Test name
Test status
Simulation time 71029105896 ps
CPU time 57.55 seconds
Started Jul 03 04:23:02 PM PDT 24
Finished Jul 03 04:24:02 PM PDT 24
Peak memory 215924 kb
Host smart-9c22f2b7-7fa8-41f8-94f2-f9520c43ead4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537829572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3537829572
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3938751318
Short name T297
Test name
Test status
Simulation time 12594330112 ps
CPU time 99 seconds
Started Jul 03 04:23:07 PM PDT 24
Finished Jul 03 04:24:47 PM PDT 24
Peak memory 218876 kb
Host smart-f4eac67a-0a87-4a2b-a6ad-4581adb794a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938751318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3938751318
Directory /workspace/9.rom_ctrl_stress_all/latest
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