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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.28 96.89 92.13 97.68 100.00 98.62 97.30 98.37


Total test records in report: 456
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T300 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1681626251 Jul 04 05:05:10 PM PDT 24 Jul 04 05:10:21 PM PDT 24 120216210489 ps
T301 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1473375070 Jul 04 05:05:34 PM PDT 24 Jul 04 05:06:18 PM PDT 24 4284030506 ps
T302 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.700468732 Jul 04 05:03:57 PM PDT 24 Jul 04 05:04:16 PM PDT 24 663038942 ps
T303 /workspace/coverage/default/27.rom_ctrl_smoke.326318607 Jul 04 05:04:30 PM PDT 24 Jul 04 05:05:27 PM PDT 24 4964155532 ps
T304 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2293606920 Jul 04 05:03:46 PM PDT 24 Jul 04 05:04:09 PM PDT 24 15751172025 ps
T305 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2794346114 Jul 04 05:04:42 PM PDT 24 Jul 04 05:05:13 PM PDT 24 1644696213 ps
T306 /workspace/coverage/default/4.rom_ctrl_smoke.2655125194 Jul 04 05:03:41 PM PDT 24 Jul 04 05:04:43 PM PDT 24 63485652082 ps
T307 /workspace/coverage/default/39.rom_ctrl_smoke.700334058 Jul 04 05:05:13 PM PDT 24 Jul 04 05:06:26 PM PDT 24 15396108781 ps
T308 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2504378175 Jul 04 05:03:39 PM PDT 24 Jul 04 05:04:32 PM PDT 24 10736192882 ps
T309 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1303977455 Jul 04 05:05:11 PM PDT 24 Jul 04 05:05:52 PM PDT 24 14364137324 ps
T310 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2833356583 Jul 04 05:03:31 PM PDT 24 Jul 04 05:15:54 PM PDT 24 292295088509 ps
T311 /workspace/coverage/default/49.rom_ctrl_stress_all.2285264457 Jul 04 05:05:52 PM PDT 24 Jul 04 05:08:15 PM PDT 24 17163222754 ps
T55 /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2574178788 Jul 04 05:04:59 PM PDT 24 Jul 04 07:35:48 PM PDT 24 37501185344 ps
T26 /workspace/coverage/default/3.rom_ctrl_sec_cm.1790336485 Jul 04 05:03:40 PM PDT 24 Jul 04 05:07:50 PM PDT 24 18202923565 ps
T312 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3820670153 Jul 04 05:03:56 PM PDT 24 Jul 04 05:04:49 PM PDT 24 21843113984 ps
T313 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2051751772 Jul 04 05:05:32 PM PDT 24 Jul 04 05:05:59 PM PDT 24 2730899401 ps
T314 /workspace/coverage/default/2.rom_ctrl_alert_test.3961094130 Jul 04 05:03:41 PM PDT 24 Jul 04 05:03:53 PM PDT 24 413173164 ps
T315 /workspace/coverage/default/10.rom_ctrl_stress_all.1999492484 Jul 04 05:03:46 PM PDT 24 Jul 04 05:06:03 PM PDT 24 14040797275 ps
T316 /workspace/coverage/default/37.rom_ctrl_stress_all.2341283519 Jul 04 05:05:04 PM PDT 24 Jul 04 05:05:52 PM PDT 24 7752091546 ps
T317 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3069938457 Jul 04 05:03:46 PM PDT 24 Jul 04 05:04:22 PM PDT 24 5001888875 ps
T318 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1723008988 Jul 04 05:05:53 PM PDT 24 Jul 04 05:18:54 PM PDT 24 645682892047 ps
T319 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3965186113 Jul 04 05:03:55 PM PDT 24 Jul 04 05:13:25 PM PDT 24 217475718404 ps
T320 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.4089382416 Jul 04 05:05:10 PM PDT 24 Jul 04 05:06:03 PM PDT 24 11571577487 ps
T321 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1068882306 Jul 04 05:03:46 PM PDT 24 Jul 04 05:04:08 PM PDT 24 2169510542 ps
T322 /workspace/coverage/default/19.rom_ctrl_alert_test.2814174923 Jul 04 05:04:02 PM PDT 24 Jul 04 05:04:33 PM PDT 24 22839614489 ps
T323 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3075130830 Jul 04 05:03:31 PM PDT 24 Jul 04 05:04:35 PM PDT 24 26910690870 ps
T324 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.4036546819 Jul 04 05:03:46 PM PDT 24 Jul 04 05:17:23 PM PDT 24 344221904754 ps
T325 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.323407514 Jul 04 05:03:48 PM PDT 24 Jul 04 05:04:08 PM PDT 24 346232766 ps
T56 /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.954045222 Jul 04 05:05:31 PM PDT 24 Jul 04 06:09:33 PM PDT 24 99053952034 ps
T326 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3457113757 Jul 04 05:03:56 PM PDT 24 Jul 04 05:07:44 PM PDT 24 3669439427 ps
T327 /workspace/coverage/default/9.rom_ctrl_alert_test.719042258 Jul 04 05:03:47 PM PDT 24 Jul 04 05:04:01 PM PDT 24 1610923640 ps
T328 /workspace/coverage/default/34.rom_ctrl_alert_test.1013081984 Jul 04 05:04:59 PM PDT 24 Jul 04 05:05:18 PM PDT 24 1877851693 ps
T329 /workspace/coverage/default/5.rom_ctrl_stress_all.1914577523 Jul 04 05:03:39 PM PDT 24 Jul 04 05:04:46 PM PDT 24 7061991125 ps
T330 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3785943971 Jul 04 05:05:52 PM PDT 24 Jul 04 05:10:56 PM PDT 24 50634513739 ps
T331 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2701605573 Jul 04 05:03:39 PM PDT 24 Jul 04 05:17:02 PM PDT 24 205509902912 ps
T332 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1771174165 Jul 04 05:05:53 PM PDT 24 Jul 04 05:06:40 PM PDT 24 17064128633 ps
T333 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.306793725 Jul 04 05:03:50 PM PDT 24 Jul 04 05:15:17 PM PDT 24 68313086563 ps
T334 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1158846952 Jul 04 05:04:51 PM PDT 24 Jul 04 05:05:09 PM PDT 24 2251972893 ps
T335 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.4015066601 Jul 04 05:05:22 PM PDT 24 Jul 04 05:05:42 PM PDT 24 1912137977 ps
T336 /workspace/coverage/default/8.rom_ctrl_smoke.1067278416 Jul 04 05:03:49 PM PDT 24 Jul 04 05:04:48 PM PDT 24 7131971132 ps
T337 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.720179346 Jul 04 05:03:52 PM PDT 24 Jul 04 05:14:37 PM PDT 24 185959955802 ps
T338 /workspace/coverage/default/24.rom_ctrl_stress_all.1679417265 Jul 04 05:04:12 PM PDT 24 Jul 04 05:06:44 PM PDT 24 14546474436 ps
T339 /workspace/coverage/default/7.rom_ctrl_alert_test.4199762548 Jul 04 05:03:47 PM PDT 24 Jul 04 05:04:15 PM PDT 24 25138512569 ps
T340 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.262716908 Jul 04 05:03:40 PM PDT 24 Jul 04 05:07:16 PM PDT 24 39332592003 ps
T341 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3591541546 Jul 04 05:05:03 PM PDT 24 Jul 04 05:05:55 PM PDT 24 18741706193 ps
T342 /workspace/coverage/default/30.rom_ctrl_alert_test.2250737300 Jul 04 05:04:52 PM PDT 24 Jul 04 05:05:10 PM PDT 24 1606123054 ps
T343 /workspace/coverage/default/48.rom_ctrl_stress_all.1000176782 Jul 04 05:05:45 PM PDT 24 Jul 04 05:06:32 PM PDT 24 3970084515 ps
T344 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3938131427 Jul 04 05:04:23 PM PDT 24 Jul 04 05:12:24 PM PDT 24 52894957943 ps
T345 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.273041803 Jul 04 05:03:53 PM PDT 24 Jul 04 05:04:24 PM PDT 24 3374302296 ps
T346 /workspace/coverage/default/21.rom_ctrl_alert_test.1485338252 Jul 04 05:04:06 PM PDT 24 Jul 04 05:04:30 PM PDT 24 5205508118 ps
T347 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3806464770 Jul 04 05:05:56 PM PDT 24 Jul 04 05:06:12 PM PDT 24 1052965175 ps
T348 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1141627715 Jul 04 05:04:44 PM PDT 24 Jul 04 05:13:53 PM PDT 24 165840904957 ps
T349 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1013703239 Jul 04 05:03:39 PM PDT 24 Jul 04 05:04:07 PM PDT 24 11766265054 ps
T350 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3282020406 Jul 04 05:03:40 PM PDT 24 Jul 04 05:04:50 PM PDT 24 34837576429 ps
T351 /workspace/coverage/default/20.rom_ctrl_alert_test.3130959427 Jul 04 05:03:59 PM PDT 24 Jul 04 05:04:11 PM PDT 24 509880082 ps
T352 /workspace/coverage/default/33.rom_ctrl_smoke.3448402677 Jul 04 05:04:50 PM PDT 24 Jul 04 05:06:15 PM PDT 24 7893858069 ps
T353 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2810842702 Jul 04 05:05:18 PM PDT 24 Jul 04 05:09:41 PM PDT 24 12101776053 ps
T354 /workspace/coverage/default/14.rom_ctrl_stress_all.733745230 Jul 04 05:03:56 PM PDT 24 Jul 04 05:04:32 PM PDT 24 15932609541 ps
T355 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3147524927 Jul 04 05:03:30 PM PDT 24 Jul 04 05:03:57 PM PDT 24 12259009182 ps
T356 /workspace/coverage/default/31.rom_ctrl_alert_test.3448095455 Jul 04 05:04:52 PM PDT 24 Jul 04 05:05:07 PM PDT 24 4087603116 ps
T357 /workspace/coverage/default/49.rom_ctrl_alert_test.1300175810 Jul 04 05:05:52 PM PDT 24 Jul 04 05:06:00 PM PDT 24 689055659 ps
T57 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.569325904 Jul 04 05:05:40 PM PDT 24 Jul 04 05:05:52 PM PDT 24 176297929 ps
T62 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.694420704 Jul 04 05:05:45 PM PDT 24 Jul 04 05:06:02 PM PDT 24 1410166721 ps
T58 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.983751501 Jul 04 05:05:52 PM PDT 24 Jul 04 05:06:16 PM PDT 24 2485643586 ps
T358 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3704304389 Jul 04 05:05:34 PM PDT 24 Jul 04 05:05:57 PM PDT 24 29456986285 ps
T63 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1203701439 Jul 04 05:03:59 PM PDT 24 Jul 04 05:06:07 PM PDT 24 12832967330 ps
T359 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.371658652 Jul 04 05:04:16 PM PDT 24 Jul 04 05:04:30 PM PDT 24 3351678000 ps
T68 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1166165741 Jul 04 05:04:07 PM PDT 24 Jul 04 05:05:43 PM PDT 24 55954963640 ps
T59 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.738004421 Jul 04 05:04:58 PM PDT 24 Jul 04 05:07:39 PM PDT 24 1763612591 ps
T69 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2228164048 Jul 04 05:04:16 PM PDT 24 Jul 04 05:04:28 PM PDT 24 671161071 ps
T360 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3792598230 Jul 04 05:04:58 PM PDT 24 Jul 04 05:05:37 PM PDT 24 16282895953 ps
T361 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.364406410 Jul 04 05:04:00 PM PDT 24 Jul 04 05:04:09 PM PDT 24 339159396 ps
T94 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2706718183 Jul 04 05:05:06 PM PDT 24 Jul 04 05:05:25 PM PDT 24 3675948140 ps
T362 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1311721468 Jul 04 05:04:12 PM PDT 24 Jul 04 05:04:30 PM PDT 24 2798703859 ps
T97 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.90057905 Jul 04 05:05:17 PM PDT 24 Jul 04 05:05:37 PM PDT 24 4178551105 ps
T363 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.424816650 Jul 04 05:03:57 PM PDT 24 Jul 04 05:04:32 PM PDT 24 4426569423 ps
T364 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2139608375 Jul 04 05:04:00 PM PDT 24 Jul 04 05:04:25 PM PDT 24 5340950278 ps
T365 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3406459738 Jul 04 05:04:58 PM PDT 24 Jul 04 05:05:29 PM PDT 24 8050886991 ps
T70 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.774190211 Jul 04 05:04:06 PM PDT 24 Jul 04 05:04:29 PM PDT 24 9486535086 ps
T366 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3937994957 Jul 04 05:03:56 PM PDT 24 Jul 04 05:04:31 PM PDT 24 3978644585 ps
T367 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.408797684 Jul 04 05:05:04 PM PDT 24 Jul 04 05:05:16 PM PDT 24 174186733 ps
T71 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.766018898 Jul 04 05:04:43 PM PDT 24 Jul 04 05:05:14 PM PDT 24 3453246379 ps
T72 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.691603652 Jul 04 05:05:10 PM PDT 24 Jul 04 05:05:38 PM PDT 24 5130760277 ps
T73 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3161243045 Jul 04 05:05:11 PM PDT 24 Jul 04 05:05:40 PM PDT 24 6830692423 ps
T368 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2313347049 Jul 04 05:05:29 PM PDT 24 Jul 04 05:06:27 PM PDT 24 2060856115 ps
T95 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2849387673 Jul 04 05:04:01 PM PDT 24 Jul 04 05:04:10 PM PDT 24 1031374898 ps
T60 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.966918323 Jul 04 05:05:47 PM PDT 24 Jul 04 05:08:31 PM PDT 24 8461635604 ps
T74 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3424646538 Jul 04 05:04:58 PM PDT 24 Jul 04 05:05:13 PM PDT 24 4290036874 ps
T75 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1016612933 Jul 04 05:05:40 PM PDT 24 Jul 04 05:05:48 PM PDT 24 339227078 ps
T96 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3968031782 Jul 04 05:04:29 PM PDT 24 Jul 04 05:05:26 PM PDT 24 4256265586 ps
T369 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3910235263 Jul 04 05:03:56 PM PDT 24 Jul 04 05:04:28 PM PDT 24 3760036353 ps
T370 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3560446163 Jul 04 05:05:48 PM PDT 24 Jul 04 05:06:18 PM PDT 24 17815814171 ps
T371 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1325373132 Jul 04 05:05:40 PM PDT 24 Jul 04 05:06:17 PM PDT 24 701335324 ps
T76 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.63640827 Jul 04 05:05:07 PM PDT 24 Jul 04 05:06:05 PM PDT 24 4301716527 ps
T372 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2478134884 Jul 04 05:05:10 PM PDT 24 Jul 04 05:07:04 PM PDT 24 18783613382 ps
T81 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.4148787398 Jul 04 05:04:50 PM PDT 24 Jul 04 05:07:19 PM PDT 24 71789477336 ps
T373 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2671579770 Jul 04 05:04:53 PM PDT 24 Jul 04 05:05:01 PM PDT 24 688214263 ps
T61 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1782891281 Jul 04 05:05:13 PM PDT 24 Jul 04 05:07:54 PM PDT 24 5143271567 ps
T374 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1241540631 Jul 04 05:04:46 PM PDT 24 Jul 04 05:05:11 PM PDT 24 10594756114 ps
T375 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3189471953 Jul 04 05:04:23 PM PDT 24 Jul 04 05:04:31 PM PDT 24 319453419 ps
T376 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1451891019 Jul 04 05:05:16 PM PDT 24 Jul 04 05:05:36 PM PDT 24 2504207251 ps
T377 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1932261560 Jul 04 05:05:53 PM PDT 24 Jul 04 05:07:33 PM PDT 24 12493233972 ps
T378 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2028562881 Jul 04 05:05:11 PM PDT 24 Jul 04 05:05:51 PM PDT 24 17804353984 ps
T379 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2772940377 Jul 04 05:03:53 PM PDT 24 Jul 04 05:04:08 PM PDT 24 174228286 ps
T82 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.826283113 Jul 04 05:04:08 PM PDT 24 Jul 04 05:04:22 PM PDT 24 9079275328 ps
T380 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2045278303 Jul 04 05:05:17 PM PDT 24 Jul 04 05:05:49 PM PDT 24 3716248259 ps
T381 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1135331770 Jul 04 05:03:56 PM PDT 24 Jul 04 05:04:05 PM PDT 24 167584162 ps
T382 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2406560851 Jul 04 05:04:01 PM PDT 24 Jul 04 05:04:16 PM PDT 24 949638143 ps
T106 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2711839741 Jul 04 05:05:17 PM PDT 24 Jul 04 05:07:01 PM PDT 24 16374494854 ps
T383 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4127806103 Jul 04 05:04:06 PM PDT 24 Jul 04 05:04:38 PM PDT 24 3962780524 ps
T384 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3697087815 Jul 04 05:03:55 PM PDT 24 Jul 04 05:04:28 PM PDT 24 17522073966 ps
T385 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.999073177 Jul 04 05:04:03 PM PDT 24 Jul 04 05:04:29 PM PDT 24 8900010835 ps
T108 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1067300637 Jul 04 05:04:51 PM PDT 24 Jul 04 05:06:12 PM PDT 24 251306120 ps
T101 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1070985196 Jul 04 05:05:46 PM PDT 24 Jul 04 05:08:25 PM PDT 24 78215551358 ps
T83 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.492067679 Jul 04 05:04:08 PM PDT 24 Jul 04 05:04:50 PM PDT 24 4493916838 ps
T386 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4229594512 Jul 04 05:04:37 PM PDT 24 Jul 04 05:05:01 PM PDT 24 2779885062 ps
T387 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1970966550 Jul 04 05:05:17 PM PDT 24 Jul 04 05:05:40 PM PDT 24 11953123777 ps
T388 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4250885020 Jul 04 05:05:25 PM PDT 24 Jul 04 05:05:35 PM PDT 24 340028838 ps
T84 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3166004040 Jul 04 05:05:50 PM PDT 24 Jul 04 05:06:20 PM PDT 24 27051781314 ps
T112 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3143566042 Jul 04 05:04:59 PM PDT 24 Jul 04 05:06:28 PM PDT 24 1119068076 ps
T389 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3802644520 Jul 04 05:05:32 PM PDT 24 Jul 04 05:05:46 PM PDT 24 2954647671 ps
T390 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.967953468 Jul 04 05:04:37 PM PDT 24 Jul 04 05:06:11 PM PDT 24 2210951232 ps
T391 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.142310339 Jul 04 05:04:08 PM PDT 24 Jul 04 05:04:17 PM PDT 24 172820945 ps
T392 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1907226844 Jul 04 05:05:07 PM PDT 24 Jul 04 05:05:34 PM PDT 24 2259931879 ps
T393 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3265176688 Jul 04 05:04:18 PM PDT 24 Jul 04 05:04:26 PM PDT 24 171070542 ps
T394 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4125665689 Jul 04 05:04:04 PM PDT 24 Jul 04 05:04:33 PM PDT 24 2790039560 ps
T107 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2980500267 Jul 04 05:05:04 PM PDT 24 Jul 04 05:06:40 PM PDT 24 7394540655 ps
T395 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1817040290 Jul 04 05:04:12 PM PDT 24 Jul 04 05:04:42 PM PDT 24 5419210591 ps
T396 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1399758200 Jul 04 05:04:53 PM PDT 24 Jul 04 05:05:18 PM PDT 24 7200695291 ps
T85 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3530623986 Jul 04 05:03:56 PM PDT 24 Jul 04 05:06:33 PM PDT 24 17954117356 ps
T397 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3403059717 Jul 04 05:05:06 PM PDT 24 Jul 04 05:05:22 PM PDT 24 2857254155 ps
T398 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4183618360 Jul 04 05:04:50 PM PDT 24 Jul 04 05:04:59 PM PDT 24 174951562 ps
T399 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1202016218 Jul 04 05:05:32 PM PDT 24 Jul 04 05:05:54 PM PDT 24 2131183332 ps
T400 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.424548756 Jul 04 05:04:54 PM PDT 24 Jul 04 05:05:08 PM PDT 24 668334478 ps
T401 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.701490980 Jul 04 05:04:29 PM PDT 24 Jul 04 05:04:38 PM PDT 24 734399546 ps
T402 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3086097218 Jul 04 05:04:51 PM PDT 24 Jul 04 05:05:11 PM PDT 24 2017878516 ps
T403 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1560072937 Jul 04 05:03:56 PM PDT 24 Jul 04 05:04:29 PM PDT 24 5930589901 ps
T404 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3277694165 Jul 04 05:05:27 PM PDT 24 Jul 04 05:05:54 PM PDT 24 10947035122 ps
T405 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2100638329 Jul 04 05:04:58 PM PDT 24 Jul 04 05:05:28 PM PDT 24 2725626225 ps
T406 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3507239797 Jul 04 05:05:11 PM PDT 24 Jul 04 05:05:39 PM PDT 24 2627186871 ps
T407 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1253718223 Jul 04 05:04:36 PM PDT 24 Jul 04 05:04:48 PM PDT 24 648386843 ps
T408 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.667467086 Jul 04 05:05:48 PM PDT 24 Jul 04 05:05:57 PM PDT 24 184289673 ps
T86 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1959490520 Jul 04 05:05:42 PM PDT 24 Jul 04 05:07:00 PM PDT 24 7224712662 ps
T409 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1217356563 Jul 04 05:05:26 PM PDT 24 Jul 04 05:07:13 PM PDT 24 24533461801 ps
T93 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4275402315 Jul 04 05:04:38 PM PDT 24 Jul 04 05:05:09 PM PDT 24 12617240614 ps
T410 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.4091568323 Jul 04 05:05:05 PM PDT 24 Jul 04 05:05:32 PM PDT 24 6217799230 ps
T411 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3190255817 Jul 04 05:05:10 PM PDT 24 Jul 04 05:07:42 PM PDT 24 15935122480 ps
T412 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1872254522 Jul 04 05:04:12 PM PDT 24 Jul 04 05:04:48 PM PDT 24 8557813152 ps
T102 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2976936689 Jul 04 05:05:53 PM PDT 24 Jul 04 05:07:03 PM PDT 24 4104598599 ps
T413 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2334873072 Jul 04 05:05:45 PM PDT 24 Jul 04 05:06:05 PM PDT 24 1164806964 ps
T103 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2742044132 Jul 04 05:03:55 PM PDT 24 Jul 04 05:06:39 PM PDT 24 14849706436 ps
T414 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.627243393 Jul 04 05:05:34 PM PDT 24 Jul 04 05:05:45 PM PDT 24 1374762562 ps
T415 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1246391893 Jul 04 05:05:38 PM PDT 24 Jul 04 05:06:08 PM PDT 24 13768664792 ps
T416 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.338698940 Jul 04 05:04:45 PM PDT 24 Jul 04 05:05:49 PM PDT 24 4126822091 ps
T87 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.422174678 Jul 04 05:04:23 PM PDT 24 Jul 04 05:04:32 PM PDT 24 170901661 ps
T417 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1274633568 Jul 04 05:04:23 PM PDT 24 Jul 04 05:04:50 PM PDT 24 13501940875 ps
T418 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1695322713 Jul 04 05:05:37 PM PDT 24 Jul 04 05:05:46 PM PDT 24 487580831 ps
T88 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1776333825 Jul 04 05:04:52 PM PDT 24 Jul 04 05:08:07 PM PDT 24 90762358649 ps
T419 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3244298910 Jul 04 05:03:54 PM PDT 24 Jul 04 05:04:12 PM PDT 24 1402877080 ps
T420 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1471753196 Jul 04 05:05:30 PM PDT 24 Jul 04 05:06:04 PM PDT 24 8213196957 ps
T421 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3931067161 Jul 04 05:04:37 PM PDT 24 Jul 04 05:04:53 PM PDT 24 1264755885 ps
T422 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2363156410 Jul 04 05:04:02 PM PDT 24 Jul 04 05:04:17 PM PDT 24 1290092328 ps
T423 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.740758875 Jul 04 05:04:58 PM PDT 24 Jul 04 05:05:07 PM PDT 24 751817818 ps
T424 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.916269640 Jul 04 05:04:42 PM PDT 24 Jul 04 05:05:04 PM PDT 24 2111934280 ps
T425 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3717954315 Jul 04 05:05:47 PM PDT 24 Jul 04 05:06:01 PM PDT 24 1473308278 ps
T426 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1397586382 Jul 04 05:05:54 PM PDT 24 Jul 04 05:06:12 PM PDT 24 4451953758 ps
T104 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3307236846 Jul 04 05:05:34 PM PDT 24 Jul 04 05:08:22 PM PDT 24 2719818077 ps
T427 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2062428490 Jul 04 05:04:50 PM PDT 24 Jul 04 05:05:05 PM PDT 24 1650900168 ps
T428 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1562959513 Jul 04 05:05:08 PM PDT 24 Jul 04 05:05:20 PM PDT 24 590911056 ps
T92 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3606566105 Jul 04 05:05:00 PM PDT 24 Jul 04 05:06:41 PM PDT 24 43221153408 ps
T429 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.50168990 Jul 04 05:04:50 PM PDT 24 Jul 04 05:05:17 PM PDT 24 13670554601 ps
T430 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1923511744 Jul 04 05:05:12 PM PDT 24 Jul 04 05:05:33 PM PDT 24 7821576483 ps
T431 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2263271058 Jul 04 05:03:57 PM PDT 24 Jul 04 05:04:16 PM PDT 24 6300920382 ps
T432 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3493374192 Jul 04 05:05:49 PM PDT 24 Jul 04 05:06:00 PM PDT 24 423148766 ps
T433 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2047702794 Jul 04 05:05:25 PM PDT 24 Jul 04 05:05:51 PM PDT 24 2892552961 ps
T109 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3181546449 Jul 04 05:05:40 PM PDT 24 Jul 04 05:07:01 PM PDT 24 885151914 ps
T434 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1737360274 Jul 04 05:05:38 PM PDT 24 Jul 04 05:06:01 PM PDT 24 1490362801 ps
T435 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.729709991 Jul 04 05:04:43 PM PDT 24 Jul 04 05:05:20 PM PDT 24 15753673218 ps
T105 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1622698580 Jul 04 05:05:47 PM PDT 24 Jul 04 05:08:31 PM PDT 24 1343546575 ps
T436 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2784215234 Jul 04 05:05:19 PM PDT 24 Jul 04 05:07:25 PM PDT 24 64087235620 ps
T437 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1679327184 Jul 04 05:04:16 PM PDT 24 Jul 04 05:07:08 PM PDT 24 4281365998 ps
T438 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2153772609 Jul 04 05:05:05 PM PDT 24 Jul 04 05:06:45 PM PDT 24 3921430251 ps
T113 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3509795336 Jul 04 05:04:08 PM PDT 24 Jul 04 05:05:44 PM PDT 24 5612291510 ps
T439 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3010600923 Jul 04 05:05:26 PM PDT 24 Jul 04 05:05:40 PM PDT 24 3760437256 ps
T440 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.393822489 Jul 04 05:04:07 PM PDT 24 Jul 04 05:04:23 PM PDT 24 660315139 ps
T441 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1781686354 Jul 04 05:04:58 PM PDT 24 Jul 04 05:05:24 PM PDT 24 12801400689 ps
T442 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.394148118 Jul 04 05:05:05 PM PDT 24 Jul 04 05:05:34 PM PDT 24 6769432506 ps
T443 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.65279539 Jul 04 05:03:55 PM PDT 24 Jul 04 05:04:03 PM PDT 24 635799647 ps
T111 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3482590873 Jul 04 05:05:22 PM PDT 24 Jul 04 05:07:04 PM PDT 24 3904063992 ps
T444 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.428202618 Jul 04 05:04:43 PM PDT 24 Jul 04 05:05:02 PM PDT 24 1753373926 ps
T445 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.4038539324 Jul 04 05:05:25 PM PDT 24 Jul 04 05:05:49 PM PDT 24 10976988765 ps
T446 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.997346013 Jul 04 05:05:05 PM PDT 24 Jul 04 05:07:34 PM PDT 24 32799624003 ps
T447 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.109028567 Jul 04 05:04:30 PM PDT 24 Jul 04 05:04:44 PM PDT 24 174521878 ps
T448 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1595471256 Jul 04 05:05:42 PM PDT 24 Jul 04 05:06:04 PM PDT 24 4265414301 ps
T449 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1948117123 Jul 04 05:05:52 PM PDT 24 Jul 04 05:06:00 PM PDT 24 332415192 ps
T450 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.4145317736 Jul 04 05:03:54 PM PDT 24 Jul 04 05:04:32 PM PDT 24 697424323 ps
T451 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3912733029 Jul 04 05:04:07 PM PDT 24 Jul 04 05:04:15 PM PDT 24 435595823 ps
T452 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3355160933 Jul 04 05:04:45 PM PDT 24 Jul 04 05:06:05 PM PDT 24 263162848 ps
T453 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3588692373 Jul 04 05:05:04 PM PDT 24 Jul 04 05:05:33 PM PDT 24 13646256939 ps
T454 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3941632991 Jul 04 05:04:24 PM PDT 24 Jul 04 05:04:56 PM PDT 24 24413946644 ps
T455 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3174969682 Jul 04 05:05:25 PM PDT 24 Jul 04 05:08:13 PM PDT 24 12229134403 ps
T456 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.10798477 Jul 04 05:04:58 PM PDT 24 Jul 04 05:05:15 PM PDT 24 1237392617 ps
T89 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3589261149 Jul 04 05:04:43 PM PDT 24 Jul 04 05:05:15 PM PDT 24 15768209939 ps
T90 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2816152757 Jul 04 05:04:02 PM PDT 24 Jul 04 05:04:16 PM PDT 24 849602467 ps
T91 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1591564409 Jul 04 05:05:54 PM PDT 24 Jul 04 05:06:25 PM PDT 24 4562835245 ps
T110 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3442975665 Jul 04 05:03:55 PM PDT 24 Jul 04 05:06:47 PM PDT 24 3444804148 ps

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.1160708267
Short name T5
Test name
Test status
Simulation time 183110046838 ps
CPU time 832.69 seconds
Started Jul 04 05:04:52 PM PDT 24
Finished Jul 04 05:18:46 PM PDT 24
Peak memory 234592 kb
Host smart-6f1b5162-18ae-40d9-9dd7-673672682b79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160708267 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.1160708267
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.266819816
Short name T8
Test name
Test status
Simulation time 178697225460 ps
CPU time 979.92 seconds
Started Jul 04 05:03:45 PM PDT 24
Finished Jul 04 05:20:05 PM PDT 24
Peak memory 229540 kb
Host smart-a7fe3daa-9702-4619-9f4b-aafba031c8c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266819816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.266819816
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1782891281
Short name T61
Test name
Test status
Simulation time 5143271567 ps
CPU time 160.4 seconds
Started Jul 04 05:05:13 PM PDT 24
Finished Jul 04 05:07:54 PM PDT 24
Peak memory 214288 kb
Host smart-2312941d-a404-4dfd-8b67-aabdde4ecde8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782891281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1782891281
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1612008964
Short name T78
Test name
Test status
Simulation time 6543040352 ps
CPU time 73.34 seconds
Started Jul 04 05:03:55 PM PDT 24
Finished Jul 04 05:05:09 PM PDT 24
Peak memory 216804 kb
Host smart-58ad34ca-600e-42e2-9545-bbe06073dc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612008964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1612008964
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.167260369
Short name T17
Test name
Test status
Simulation time 1055049398 ps
CPU time 117.88 seconds
Started Jul 04 05:03:42 PM PDT 24
Finished Jul 04 05:05:40 PM PDT 24
Peak memory 237464 kb
Host smart-2c2cdbc2-21ba-4ce3-8886-5126bb0401bb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167260369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.167260369
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1166165741
Short name T68
Test name
Test status
Simulation time 55954963640 ps
CPU time 96.51 seconds
Started Jul 04 05:04:07 PM PDT 24
Finished Jul 04 05:05:43 PM PDT 24
Peak memory 213796 kb
Host smart-5b830e75-efd9-473d-a9b5-53de7c679925
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166165741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1166165741
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3131860142
Short name T42
Test name
Test status
Simulation time 22682395685 ps
CPU time 160.09 seconds
Started Jul 04 05:04:43 PM PDT 24
Finished Jul 04 05:07:24 PM PDT 24
Peak memory 219396 kb
Host smart-b3caae72-74f7-40ed-b455-9010182cd240
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131860142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3131860142
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3307236846
Short name T104
Test name
Test status
Simulation time 2719818077 ps
CPU time 167.78 seconds
Started Jul 04 05:05:34 PM PDT 24
Finished Jul 04 05:08:22 PM PDT 24
Peak memory 214008 kb
Host smart-6acbe1c2-2d81-48f1-af05-ca23842b324e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307236846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3307236846
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2424945227
Short name T138
Test name
Test status
Simulation time 3092762484 ps
CPU time 17.97 seconds
Started Jul 04 05:03:33 PM PDT 24
Finished Jul 04 05:03:52 PM PDT 24
Peak memory 217112 kb
Host smart-392f6c98-ae46-4c40-8e88-4661c8b3120a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424945227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2424945227
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3606566105
Short name T92
Test name
Test status
Simulation time 43221153408 ps
CPU time 101.56 seconds
Started Jul 04 05:05:00 PM PDT 24
Finished Jul 04 05:06:41 PM PDT 24
Peak memory 214016 kb
Host smart-b3705f62-e958-4e42-b274-b6033f9ce27c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606566105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3606566105
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2865312582
Short name T51
Test name
Test status
Simulation time 6324532202 ps
CPU time 132.41 seconds
Started Jul 04 05:03:53 PM PDT 24
Finished Jul 04 05:06:06 PM PDT 24
Peak memory 238312 kb
Host smart-c88ccf72-23a4-47b5-81da-63eac679ce1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865312582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2865312582
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1360611996
Short name T22
Test name
Test status
Simulation time 12622379113 ps
CPU time 60.98 seconds
Started Jul 04 05:03:45 PM PDT 24
Finished Jul 04 05:04:46 PM PDT 24
Peak memory 219184 kb
Host smart-6544fd34-e889-4ae7-913c-3c5597ea2421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360611996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1360611996
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2499533925
Short name T48
Test name
Test status
Simulation time 74809048698 ps
CPU time 61.57 seconds
Started Jul 04 05:03:49 PM PDT 24
Finished Jul 04 05:04:51 PM PDT 24
Peak memory 219080 kb
Host smart-bd00226a-396a-4852-9736-58e9100ff67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499533925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2499533925
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2758406127
Short name T199
Test name
Test status
Simulation time 1319657370 ps
CPU time 18.5 seconds
Started Jul 04 05:04:04 PM PDT 24
Finished Jul 04 05:04:23 PM PDT 24
Peak memory 219300 kb
Host smart-79cfdd60-d472-4fd8-b442-d8a8d7cc60ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758406127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2758406127
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2980500267
Short name T107
Test name
Test status
Simulation time 7394540655 ps
CPU time 95.56 seconds
Started Jul 04 05:05:04 PM PDT 24
Finished Jul 04 05:06:40 PM PDT 24
Peak memory 213928 kb
Host smart-a2c84d40-d63a-4302-8d9c-228cf38d7bcc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980500267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2980500267
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3442975665
Short name T110
Test name
Test status
Simulation time 3444804148 ps
CPU time 172.04 seconds
Started Jul 04 05:03:55 PM PDT 24
Finished Jul 04 05:06:47 PM PDT 24
Peak memory 213884 kb
Host smart-85374ce4-c79a-4505-b10b-60b17951d883
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442975665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3442975665
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2849387673
Short name T95
Test name
Test status
Simulation time 1031374898 ps
CPU time 8 seconds
Started Jul 04 05:04:01 PM PDT 24
Finished Jul 04 05:04:10 PM PDT 24
Peak memory 211216 kb
Host smart-4ec2bd91-d8c4-43ec-869a-a84294a02e98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849387673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2849387673
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2263271058
Short name T431
Test name
Test status
Simulation time 6300920382 ps
CPU time 18.65 seconds
Started Jul 04 05:03:57 PM PDT 24
Finished Jul 04 05:04:16 PM PDT 24
Peak memory 211612 kb
Host smart-8f5d8772-0a9d-4a90-98c9-f4dcc819fa2f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263271058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2263271058
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3244298910
Short name T419
Test name
Test status
Simulation time 1402877080 ps
CPU time 17.31 seconds
Started Jul 04 05:03:54 PM PDT 24
Finished Jul 04 05:04:12 PM PDT 24
Peak memory 211220 kb
Host smart-7d17e06e-b4a5-4c67-8864-d3e8170e36cc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244298910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3244298910
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.999073177
Short name T385
Test name
Test status
Simulation time 8900010835 ps
CPU time 26.46 seconds
Started Jul 04 05:04:03 PM PDT 24
Finished Jul 04 05:04:29 PM PDT 24
Peak memory 212328 kb
Host smart-b4fa8c8b-681e-4dd3-8a7c-b53bcc2f2524
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999073177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.999073177
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1560072937
Short name T403
Test name
Test status
Simulation time 5930589901 ps
CPU time 32.39 seconds
Started Jul 04 05:03:56 PM PDT 24
Finished Jul 04 05:04:29 PM PDT 24
Peak memory 218056 kb
Host smart-005ecd56-b503-4bed-b630-e5867f903685
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560072937 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1560072937
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3910235263
Short name T369
Test name
Test status
Simulation time 3760036353 ps
CPU time 31.12 seconds
Started Jul 04 05:03:56 PM PDT 24
Finished Jul 04 05:04:28 PM PDT 24
Peak memory 211308 kb
Host smart-251665bc-46b6-402a-8c2d-e2ad6ac44b23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910235263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3910235263
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.424816650
Short name T363
Test name
Test status
Simulation time 4426569423 ps
CPU time 34.49 seconds
Started Jul 04 05:03:57 PM PDT 24
Finished Jul 04 05:04:32 PM PDT 24
Peak memory 210628 kb
Host smart-18368013-1d88-4443-a3e7-c2492e31c175
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424816650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.424816650
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3697087815
Short name T384
Test name
Test status
Simulation time 17522073966 ps
CPU time 32.47 seconds
Started Jul 04 05:03:55 PM PDT 24
Finished Jul 04 05:04:28 PM PDT 24
Peak memory 210892 kb
Host smart-084ac912-0377-4041-a6c1-87d6caac48d6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697087815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3697087815
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3530623986
Short name T85
Test name
Test status
Simulation time 17954117356 ps
CPU time 156.54 seconds
Started Jul 04 05:03:56 PM PDT 24
Finished Jul 04 05:06:33 PM PDT 24
Peak memory 215284 kb
Host smart-e4e8a0f8-91e8-48c2-a018-89ec60f31046
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530623986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3530623986
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1135331770
Short name T381
Test name
Test status
Simulation time 167584162 ps
CPU time 8.49 seconds
Started Jul 04 05:03:56 PM PDT 24
Finished Jul 04 05:04:05 PM PDT 24
Peak memory 211108 kb
Host smart-887aad6b-f17e-4e46-98f4-9ec90d20699d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135331770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1135331770
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2772940377
Short name T379
Test name
Test status
Simulation time 174228286 ps
CPU time 13.92 seconds
Started Jul 04 05:03:53 PM PDT 24
Finished Jul 04 05:04:08 PM PDT 24
Peak memory 217292 kb
Host smart-b619ffa5-83af-4179-a346-b3c4bc8b3c8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772940377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2772940377
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2816152757
Short name T90
Test name
Test status
Simulation time 849602467 ps
CPU time 13.53 seconds
Started Jul 04 05:04:02 PM PDT 24
Finished Jul 04 05:04:16 PM PDT 24
Peak memory 210564 kb
Host smart-ff1b037f-2c68-4387-add0-ba9ffc06e5f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816152757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2816152757
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2406560851
Short name T382
Test name
Test status
Simulation time 949638143 ps
CPU time 14.39 seconds
Started Jul 04 05:04:01 PM PDT 24
Finished Jul 04 05:04:16 PM PDT 24
Peak memory 210608 kb
Host smart-643b6ba7-69b4-423d-b867-696c731b1a57
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406560851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2406560851
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4125665689
Short name T394
Test name
Test status
Simulation time 2790039560 ps
CPU time 29.3 seconds
Started Jul 04 05:04:04 PM PDT 24
Finished Jul 04 05:04:33 PM PDT 24
Peak memory 211252 kb
Host smart-844153e4-d292-486c-9786-13274d7eab46
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125665689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.4125665689
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2139608375
Short name T364
Test name
Test status
Simulation time 5340950278 ps
CPU time 24.47 seconds
Started Jul 04 05:04:00 PM PDT 24
Finished Jul 04 05:04:25 PM PDT 24
Peak memory 218920 kb
Host smart-ea9ca8f2-27cd-4d59-9864-4df9601c40b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139608375 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2139608375
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2363156410
Short name T422
Test name
Test status
Simulation time 1290092328 ps
CPU time 15.45 seconds
Started Jul 04 05:04:02 PM PDT 24
Finished Jul 04 05:04:17 PM PDT 24
Peak memory 210600 kb
Host smart-3244df04-57a2-4eec-a547-2da794fd726a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363156410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2363156410
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.364406410
Short name T361
Test name
Test status
Simulation time 339159396 ps
CPU time 8.25 seconds
Started Jul 04 05:04:00 PM PDT 24
Finished Jul 04 05:04:09 PM PDT 24
Peak memory 210472 kb
Host smart-7c86a174-c3ed-4d1f-9a72-32e860dea1f3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364406410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.364406410
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.65279539
Short name T443
Test name
Test status
Simulation time 635799647 ps
CPU time 7.88 seconds
Started Jul 04 05:03:55 PM PDT 24
Finished Jul 04 05:04:03 PM PDT 24
Peak memory 210456 kb
Host smart-faad1f7b-cb23-4baa-9192-6f2673012f13
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65279539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.65279539
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.4145317736
Short name T450
Test name
Test status
Simulation time 697424323 ps
CPU time 37.45 seconds
Started Jul 04 05:03:54 PM PDT 24
Finished Jul 04 05:04:32 PM PDT 24
Peak memory 214048 kb
Host smart-0c4741b6-6768-4ad7-ae48-dd9cde0c1021
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145317736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.4145317736
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3937994957
Short name T366
Test name
Test status
Simulation time 3978644585 ps
CPU time 34.94 seconds
Started Jul 04 05:03:56 PM PDT 24
Finished Jul 04 05:04:31 PM PDT 24
Peak memory 217108 kb
Host smart-1ff63514-53b0-450e-a2a5-2b6b595349cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937994957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3937994957
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2742044132
Short name T103
Test name
Test status
Simulation time 14849706436 ps
CPU time 164.01 seconds
Started Jul 04 05:03:55 PM PDT 24
Finished Jul 04 05:06:39 PM PDT 24
Peak memory 215484 kb
Host smart-fea469a7-6666-449c-b3fc-5bcf5eedc7ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742044132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2742044132
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.394148118
Short name T442
Test name
Test status
Simulation time 6769432506 ps
CPU time 28.52 seconds
Started Jul 04 05:05:05 PM PDT 24
Finished Jul 04 05:05:34 PM PDT 24
Peak memory 217096 kb
Host smart-a0c8ef63-fbd3-4758-b142-d0b9f4b62f65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394148118 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.394148118
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1562959513
Short name T428
Test name
Test status
Simulation time 590911056 ps
CPU time 12.33 seconds
Started Jul 04 05:05:08 PM PDT 24
Finished Jul 04 05:05:20 PM PDT 24
Peak memory 210488 kb
Host smart-27d7e342-5cad-4920-a33e-4f9ed2bf95e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562959513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1562959513
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.997346013
Short name T446
Test name
Test status
Simulation time 32799624003 ps
CPU time 148.93 seconds
Started Jul 04 05:05:05 PM PDT 24
Finished Jul 04 05:07:34 PM PDT 24
Peak memory 215036 kb
Host smart-ef3e7053-40a0-444b-89ec-18950d3b53d0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997346013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.997346013
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2706718183
Short name T94
Test name
Test status
Simulation time 3675948140 ps
CPU time 19.4 seconds
Started Jul 04 05:05:06 PM PDT 24
Finished Jul 04 05:05:25 PM PDT 24
Peak memory 212132 kb
Host smart-fbfb1177-4dd1-4c64-a711-892e7e1f162a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706718183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2706718183
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1907226844
Short name T392
Test name
Test status
Simulation time 2259931879 ps
CPU time 26.44 seconds
Started Jul 04 05:05:07 PM PDT 24
Finished Jul 04 05:05:34 PM PDT 24
Peak memory 218904 kb
Host smart-abb86360-316b-404b-9c25-1ed66291da65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907226844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1907226844
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1923511744
Short name T430
Test name
Test status
Simulation time 7821576483 ps
CPU time 20.81 seconds
Started Jul 04 05:05:12 PM PDT 24
Finished Jul 04 05:05:33 PM PDT 24
Peak memory 217016 kb
Host smart-3e5c2404-9721-42bb-b802-41a126ac01d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923511744 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1923511744
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3161243045
Short name T73
Test name
Test status
Simulation time 6830692423 ps
CPU time 27.93 seconds
Started Jul 04 05:05:11 PM PDT 24
Finished Jul 04 05:05:40 PM PDT 24
Peak memory 212180 kb
Host smart-95f75a6a-d707-437e-b18f-2cc4074a8744
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161243045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3161243045
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3190255817
Short name T411
Test name
Test status
Simulation time 15935122480 ps
CPU time 151.5 seconds
Started Jul 04 05:05:10 PM PDT 24
Finished Jul 04 05:07:42 PM PDT 24
Peak memory 215876 kb
Host smart-968ae937-694a-45ba-a4ab-3e79129e9650
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190255817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3190255817
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.691603652
Short name T72
Test name
Test status
Simulation time 5130760277 ps
CPU time 27.51 seconds
Started Jul 04 05:05:10 PM PDT 24
Finished Jul 04 05:05:38 PM PDT 24
Peak memory 212760 kb
Host smart-00638ff2-d07e-4188-b68e-c41a176ac62e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691603652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.691603652
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2028562881
Short name T378
Test name
Test status
Simulation time 17804353984 ps
CPU time 39.13 seconds
Started Jul 04 05:05:11 PM PDT 24
Finished Jul 04 05:05:51 PM PDT 24
Peak memory 217712 kb
Host smart-572ae6cf-fc1d-4c68-b5a7-d906beb91772
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028562881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2028562881
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1970966550
Short name T387
Test name
Test status
Simulation time 11953123777 ps
CPU time 21.98 seconds
Started Jul 04 05:05:17 PM PDT 24
Finished Jul 04 05:05:40 PM PDT 24
Peak memory 215932 kb
Host smart-18cb325a-5162-468e-abc1-a1349582baf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970966550 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1970966550
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.90057905
Short name T97
Test name
Test status
Simulation time 4178551105 ps
CPU time 19.68 seconds
Started Jul 04 05:05:17 PM PDT 24
Finished Jul 04 05:05:37 PM PDT 24
Peak memory 212144 kb
Host smart-f373e4f7-c10e-494d-8aa6-25c176c2536e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90057905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.90057905
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2478134884
Short name T372
Test name
Test status
Simulation time 18783613382 ps
CPU time 112.09 seconds
Started Jul 04 05:05:10 PM PDT 24
Finished Jul 04 05:07:04 PM PDT 24
Peak memory 215316 kb
Host smart-176d3eca-803a-4db9-b380-f704a716e7a5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478134884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2478134884
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2045278303
Short name T380
Test name
Test status
Simulation time 3716248259 ps
CPU time 31.66 seconds
Started Jul 04 05:05:17 PM PDT 24
Finished Jul 04 05:05:49 PM PDT 24
Peak memory 212512 kb
Host smart-0288a1fc-078c-4428-a0dc-548b68213ddf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045278303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2045278303
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3507239797
Short name T406
Test name
Test status
Simulation time 2627186871 ps
CPU time 26.91 seconds
Started Jul 04 05:05:11 PM PDT 24
Finished Jul 04 05:05:39 PM PDT 24
Peak memory 218236 kb
Host smart-a4822515-6d4a-42a8-bfb1-c3df45d67d49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507239797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3507239797
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3482590873
Short name T111
Test name
Test status
Simulation time 3904063992 ps
CPU time 102.08 seconds
Started Jul 04 05:05:22 PM PDT 24
Finished Jul 04 05:07:04 PM PDT 24
Peak memory 212532 kb
Host smart-382803df-00ed-4963-8c7a-b5cd664b4011
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482590873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3482590873
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.4038539324
Short name T445
Test name
Test status
Simulation time 10976988765 ps
CPU time 24.08 seconds
Started Jul 04 05:05:25 PM PDT 24
Finished Jul 04 05:05:49 PM PDT 24
Peak memory 217688 kb
Host smart-93ff407a-e425-4893-9676-293286ef5fee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038539324 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.4038539324
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3010600923
Short name T439
Test name
Test status
Simulation time 3760437256 ps
CPU time 13.97 seconds
Started Jul 04 05:05:26 PM PDT 24
Finished Jul 04 05:05:40 PM PDT 24
Peak memory 210720 kb
Host smart-81bc74f5-4b05-41dc-b809-1db0158de401
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010600923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3010600923
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2784215234
Short name T436
Test name
Test status
Simulation time 64087235620 ps
CPU time 125.97 seconds
Started Jul 04 05:05:19 PM PDT 24
Finished Jul 04 05:07:25 PM PDT 24
Peak memory 215272 kb
Host smart-975ffd6d-17d7-4ce5-a33d-160842ae3839
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784215234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2784215234
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4250885020
Short name T388
Test name
Test status
Simulation time 340028838 ps
CPU time 10.68 seconds
Started Jul 04 05:05:25 PM PDT 24
Finished Jul 04 05:05:35 PM PDT 24
Peak memory 211476 kb
Host smart-ec53a43b-ce26-4dba-96b6-9ef2a5e7724d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250885020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.4250885020
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1451891019
Short name T376
Test name
Test status
Simulation time 2504207251 ps
CPU time 19.59 seconds
Started Jul 04 05:05:16 PM PDT 24
Finished Jul 04 05:05:36 PM PDT 24
Peak memory 218328 kb
Host smart-1e0a1166-a3cb-4590-a998-81b587544537
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451891019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1451891019
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2711839741
Short name T106
Test name
Test status
Simulation time 16374494854 ps
CPU time 104.19 seconds
Started Jul 04 05:05:17 PM PDT 24
Finished Jul 04 05:07:01 PM PDT 24
Peak memory 213888 kb
Host smart-0b45dd5e-9d7c-4a23-8845-2e47f6c6848e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711839741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2711839741
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1471753196
Short name T420
Test name
Test status
Simulation time 8213196957 ps
CPU time 33.04 seconds
Started Jul 04 05:05:30 PM PDT 24
Finished Jul 04 05:06:04 PM PDT 24
Peak memory 219076 kb
Host smart-893ed9ef-d95f-486e-8649-7bede1548673
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471753196 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1471753196
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2047702794
Short name T433
Test name
Test status
Simulation time 2892552961 ps
CPU time 25.52 seconds
Started Jul 04 05:05:25 PM PDT 24
Finished Jul 04 05:05:51 PM PDT 24
Peak memory 211416 kb
Host smart-f8a7bab8-d4b7-4d70-8d97-c6318d321e79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047702794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2047702794
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1217356563
Short name T409
Test name
Test status
Simulation time 24533461801 ps
CPU time 106.07 seconds
Started Jul 04 05:05:26 PM PDT 24
Finished Jul 04 05:07:13 PM PDT 24
Peak memory 213704 kb
Host smart-65da23dd-8fad-4a83-b1a0-5cee29db0c56
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217356563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1217356563
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1202016218
Short name T399
Test name
Test status
Simulation time 2131183332 ps
CPU time 21.83 seconds
Started Jul 04 05:05:32 PM PDT 24
Finished Jul 04 05:05:54 PM PDT 24
Peak memory 212052 kb
Host smart-b8640d67-8b9b-4f40-aa9b-bfbc8a2eb3d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202016218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1202016218
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3277694165
Short name T404
Test name
Test status
Simulation time 10947035122 ps
CPU time 27.24 seconds
Started Jul 04 05:05:27 PM PDT 24
Finished Jul 04 05:05:54 PM PDT 24
Peak memory 217532 kb
Host smart-920bf837-bc8f-4347-bd78-60dec894cd72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277694165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3277694165
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3174969682
Short name T455
Test name
Test status
Simulation time 12229134403 ps
CPU time 168.3 seconds
Started Jul 04 05:05:25 PM PDT 24
Finished Jul 04 05:08:13 PM PDT 24
Peak memory 214220 kb
Host smart-b7244f90-7c62-4f02-9343-d6692013e712
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174969682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3174969682
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1595471256
Short name T448
Test name
Test status
Simulation time 4265414301 ps
CPU time 21.09 seconds
Started Jul 04 05:05:42 PM PDT 24
Finished Jul 04 05:06:04 PM PDT 24
Peak memory 215100 kb
Host smart-e7060360-89c0-43f6-9ce9-075e50419110
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595471256 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1595471256
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3802644520
Short name T389
Test name
Test status
Simulation time 2954647671 ps
CPU time 13.06 seconds
Started Jul 04 05:05:32 PM PDT 24
Finished Jul 04 05:05:46 PM PDT 24
Peak memory 211112 kb
Host smart-0f39eac2-eb00-4d98-b2b3-3bba52e31d54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802644520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3802644520
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2313347049
Short name T368
Test name
Test status
Simulation time 2060856115 ps
CPU time 57.95 seconds
Started Jul 04 05:05:29 PM PDT 24
Finished Jul 04 05:06:27 PM PDT 24
Peak memory 215068 kb
Host smart-a6e58bfb-2f46-4cea-967d-62c15288a84a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313347049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2313347049
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.627243393
Short name T414
Test name
Test status
Simulation time 1374762562 ps
CPU time 10.54 seconds
Started Jul 04 05:05:34 PM PDT 24
Finished Jul 04 05:05:45 PM PDT 24
Peak memory 211280 kb
Host smart-f35e28b8-44ab-4f64-86c5-8c477c5d5934
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627243393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.627243393
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3704304389
Short name T358
Test name
Test status
Simulation time 29456986285 ps
CPU time 22.46 seconds
Started Jul 04 05:05:34 PM PDT 24
Finished Jul 04 05:05:57 PM PDT 24
Peak memory 218756 kb
Host smart-1793545c-2ec0-42b9-90b7-926a41e3040e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704304389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3704304389
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1246391893
Short name T415
Test name
Test status
Simulation time 13768664792 ps
CPU time 29.37 seconds
Started Jul 04 05:05:38 PM PDT 24
Finished Jul 04 05:06:08 PM PDT 24
Peak memory 217880 kb
Host smart-db080ced-525e-4b00-a974-64f3681998a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246391893 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1246391893
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1016612933
Short name T75
Test name
Test status
Simulation time 339227078 ps
CPU time 8.01 seconds
Started Jul 04 05:05:40 PM PDT 24
Finished Jul 04 05:05:48 PM PDT 24
Peak memory 210916 kb
Host smart-6edf911e-594c-4c25-98c5-646571474b2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016612933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1016612933
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1325373132
Short name T371
Test name
Test status
Simulation time 701335324 ps
CPU time 37.49 seconds
Started Jul 04 05:05:40 PM PDT 24
Finished Jul 04 05:06:17 PM PDT 24
Peak memory 213672 kb
Host smart-8fbb0f71-34f5-45b4-8109-136fc3335f82
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325373132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1325373132
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1695322713
Short name T418
Test name
Test status
Simulation time 487580831 ps
CPU time 8.31 seconds
Started Jul 04 05:05:37 PM PDT 24
Finished Jul 04 05:05:46 PM PDT 24
Peak memory 211472 kb
Host smart-3384e870-58fb-43ed-a69c-f5b03b76a8d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695322713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1695322713
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.569325904
Short name T57
Test name
Test status
Simulation time 176297929 ps
CPU time 12.67 seconds
Started Jul 04 05:05:40 PM PDT 24
Finished Jul 04 05:05:52 PM PDT 24
Peak memory 217324 kb
Host smart-3ab592a3-812f-439d-b92f-6296b25a95b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569325904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.569325904
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3181546449
Short name T109
Test name
Test status
Simulation time 885151914 ps
CPU time 80.42 seconds
Started Jul 04 05:05:40 PM PDT 24
Finished Jul 04 05:07:01 PM PDT 24
Peak memory 213408 kb
Host smart-628a2481-0abf-4673-9142-c384cfd017f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181546449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3181546449
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3717954315
Short name T425
Test name
Test status
Simulation time 1473308278 ps
CPU time 13.07 seconds
Started Jul 04 05:05:47 PM PDT 24
Finished Jul 04 05:06:01 PM PDT 24
Peak memory 216332 kb
Host smart-9c0d2225-f500-4b1e-8168-8970487ab4e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717954315 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3717954315
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3166004040
Short name T84
Test name
Test status
Simulation time 27051781314 ps
CPU time 30.08 seconds
Started Jul 04 05:05:50 PM PDT 24
Finished Jul 04 05:06:20 PM PDT 24
Peak memory 212236 kb
Host smart-726bf1fa-942e-4c96-8a9e-e6cd22d5b5e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166004040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3166004040
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1959490520
Short name T86
Test name
Test status
Simulation time 7224712662 ps
CPU time 78.42 seconds
Started Jul 04 05:05:42 PM PDT 24
Finished Jul 04 05:07:00 PM PDT 24
Peak memory 214152 kb
Host smart-5bfb3879-699a-41d1-9fe3-0b9684011401
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959490520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1959490520
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2334873072
Short name T413
Test name
Test status
Simulation time 1164806964 ps
CPU time 19.45 seconds
Started Jul 04 05:05:45 PM PDT 24
Finished Jul 04 05:06:05 PM PDT 24
Peak memory 212240 kb
Host smart-d4737f47-f13c-4715-9d9c-e8bc6b679ca9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334873072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2334873072
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1737360274
Short name T434
Test name
Test status
Simulation time 1490362801 ps
CPU time 22.46 seconds
Started Jul 04 05:05:38 PM PDT 24
Finished Jul 04 05:06:01 PM PDT 24
Peak memory 218556 kb
Host smart-74d1a7a0-35fc-4a98-bf23-228befcb8043
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737360274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1737360274
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.966918323
Short name T60
Test name
Test status
Simulation time 8461635604 ps
CPU time 163.93 seconds
Started Jul 04 05:05:47 PM PDT 24
Finished Jul 04 05:08:31 PM PDT 24
Peak memory 214428 kb
Host smart-7b11b045-89cd-4103-a5c2-7f11202621b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966918323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.966918323
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.667467086
Short name T408
Test name
Test status
Simulation time 184289673 ps
CPU time 8.88 seconds
Started Jul 04 05:05:48 PM PDT 24
Finished Jul 04 05:05:57 PM PDT 24
Peak memory 216628 kb
Host smart-20c91fbe-7dc5-4d48-a532-d3156bc741b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667467086 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.667467086
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3493374192
Short name T432
Test name
Test status
Simulation time 423148766 ps
CPU time 11.01 seconds
Started Jul 04 05:05:49 PM PDT 24
Finished Jul 04 05:06:00 PM PDT 24
Peak memory 210652 kb
Host smart-fa9474fb-eda2-428a-9ffa-e5c8b244d895
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493374192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3493374192
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1070985196
Short name T101
Test name
Test status
Simulation time 78215551358 ps
CPU time 159.06 seconds
Started Jul 04 05:05:46 PM PDT 24
Finished Jul 04 05:08:25 PM PDT 24
Peak memory 214956 kb
Host smart-4d54a89a-6831-4c31-9857-4a436094ed1c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070985196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1070985196
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.694420704
Short name T62
Test name
Test status
Simulation time 1410166721 ps
CPU time 17.19 seconds
Started Jul 04 05:05:45 PM PDT 24
Finished Jul 04 05:06:02 PM PDT 24
Peak memory 211100 kb
Host smart-8c69909e-82b7-4759-abc8-c8958fb9639c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694420704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.694420704
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3560446163
Short name T370
Test name
Test status
Simulation time 17815814171 ps
CPU time 29.83 seconds
Started Jul 04 05:05:48 PM PDT 24
Finished Jul 04 05:06:18 PM PDT 24
Peak memory 217460 kb
Host smart-234b56e6-bc4a-49e2-b923-eddb7d80a773
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560446163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3560446163
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1622698580
Short name T105
Test name
Test status
Simulation time 1343546575 ps
CPU time 164.03 seconds
Started Jul 04 05:05:47 PM PDT 24
Finished Jul 04 05:08:31 PM PDT 24
Peak memory 213980 kb
Host smart-74ac842d-5997-45b6-a36d-f8b113a00913
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622698580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1622698580
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.983751501
Short name T58
Test name
Test status
Simulation time 2485643586 ps
CPU time 22.72 seconds
Started Jul 04 05:05:52 PM PDT 24
Finished Jul 04 05:06:16 PM PDT 24
Peak memory 216224 kb
Host smart-11db5ebb-c8d4-48e4-8c91-10dc25dac2ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983751501 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.983751501
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1591564409
Short name T91
Test name
Test status
Simulation time 4562835245 ps
CPU time 30.44 seconds
Started Jul 04 05:05:54 PM PDT 24
Finished Jul 04 05:06:25 PM PDT 24
Peak memory 212108 kb
Host smart-bfa8d021-e116-4dd3-ad36-5f62d94bc43b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591564409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1591564409
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2976936689
Short name T102
Test name
Test status
Simulation time 4104598599 ps
CPU time 69.77 seconds
Started Jul 04 05:05:53 PM PDT 24
Finished Jul 04 05:07:03 PM PDT 24
Peak memory 215252 kb
Host smart-6587a37e-b35b-42c2-b4d7-7db10b1a1839
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976936689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2976936689
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1948117123
Short name T449
Test name
Test status
Simulation time 332415192 ps
CPU time 8.15 seconds
Started Jul 04 05:05:52 PM PDT 24
Finished Jul 04 05:06:00 PM PDT 24
Peak memory 211116 kb
Host smart-058b2603-8cd3-425f-9c28-047f2ac1bb34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948117123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1948117123
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1397586382
Short name T426
Test name
Test status
Simulation time 4451953758 ps
CPU time 17.75 seconds
Started Jul 04 05:05:54 PM PDT 24
Finished Jul 04 05:06:12 PM PDT 24
Peak memory 218900 kb
Host smart-0bbc939e-3a76-48be-b7f3-8d730666c739
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397586382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1397586382
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1932261560
Short name T377
Test name
Test status
Simulation time 12493233972 ps
CPU time 99.53 seconds
Started Jul 04 05:05:53 PM PDT 24
Finished Jul 04 05:07:33 PM PDT 24
Peak memory 213672 kb
Host smart-5bb2de68-2704-41d1-b9db-9dc21b713cef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932261560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1932261560
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.826283113
Short name T82
Test name
Test status
Simulation time 9079275328 ps
CPU time 13.77 seconds
Started Jul 04 05:04:08 PM PDT 24
Finished Jul 04 05:04:22 PM PDT 24
Peak memory 211088 kb
Host smart-fffa04ed-85e8-4376-a42e-4a2d850eecc2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826283113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.826283113
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.142310339
Short name T391
Test name
Test status
Simulation time 172820945 ps
CPU time 8.42 seconds
Started Jul 04 05:04:08 PM PDT 24
Finished Jul 04 05:04:17 PM PDT 24
Peak memory 210588 kb
Host smart-ff00e1aa-cfbe-4d8d-8c2c-31b7b955acdc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142310339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.142310339
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.492067679
Short name T83
Test name
Test status
Simulation time 4493916838 ps
CPU time 41.37 seconds
Started Jul 04 05:04:08 PM PDT 24
Finished Jul 04 05:04:50 PM PDT 24
Peak memory 212076 kb
Host smart-33421d5a-da09-4034-88ca-dffc861e1288
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492067679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.492067679
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4127806103
Short name T383
Test name
Test status
Simulation time 3962780524 ps
CPU time 31.77 seconds
Started Jul 04 05:04:06 PM PDT 24
Finished Jul 04 05:04:38 PM PDT 24
Peak memory 215564 kb
Host smart-46ef9a35-eb3d-4c73-a176-bcbbb651f1fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127806103 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.4127806103
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.774190211
Short name T70
Test name
Test status
Simulation time 9486535086 ps
CPU time 22.83 seconds
Started Jul 04 05:04:06 PM PDT 24
Finished Jul 04 05:04:29 PM PDT 24
Peak memory 212400 kb
Host smart-5160ec09-0ae1-4fb3-baf7-33e448c17a10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774190211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.774190211
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1311721468
Short name T362
Test name
Test status
Simulation time 2798703859 ps
CPU time 17.65 seconds
Started Jul 04 05:04:12 PM PDT 24
Finished Jul 04 05:04:30 PM PDT 24
Peak memory 210676 kb
Host smart-b22c345d-0136-4951-bdcf-dde098f3bc99
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311721468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1311721468
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1817040290
Short name T395
Test name
Test status
Simulation time 5419210591 ps
CPU time 30.32 seconds
Started Jul 04 05:04:12 PM PDT 24
Finished Jul 04 05:04:42 PM PDT 24
Peak memory 210792 kb
Host smart-a76f1ed6-016c-448c-993e-b6e138306bd2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817040290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1817040290
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1203701439
Short name T63
Test name
Test status
Simulation time 12832967330 ps
CPU time 127.53 seconds
Started Jul 04 05:03:59 PM PDT 24
Finished Jul 04 05:06:07 PM PDT 24
Peak memory 214760 kb
Host smart-f9ec972d-2f6a-41b8-8c33-524ef9876343
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203701439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1203701439
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3912733029
Short name T451
Test name
Test status
Simulation time 435595823 ps
CPU time 8.27 seconds
Started Jul 04 05:04:07 PM PDT 24
Finished Jul 04 05:04:15 PM PDT 24
Peak memory 211360 kb
Host smart-c12f5628-1a31-49ed-b8db-0ef2bd10e42a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912733029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3912733029
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.393822489
Short name T440
Test name
Test status
Simulation time 660315139 ps
CPU time 15.86 seconds
Started Jul 04 05:04:07 PM PDT 24
Finished Jul 04 05:04:23 PM PDT 24
Peak memory 218212 kb
Host smart-3c2c2353-a122-4133-bd0f-06057fadb5b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393822489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.393822489
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3509795336
Short name T113
Test name
Test status
Simulation time 5612291510 ps
CPU time 95.82 seconds
Started Jul 04 05:04:08 PM PDT 24
Finished Jul 04 05:05:44 PM PDT 24
Peak memory 213936 kb
Host smart-640502e9-932b-4927-910f-25ca22b20b9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509795336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3509795336
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1274633568
Short name T417
Test name
Test status
Simulation time 13501940875 ps
CPU time 26.69 seconds
Started Jul 04 05:04:23 PM PDT 24
Finished Jul 04 05:04:50 PM PDT 24
Peak memory 211720 kb
Host smart-b56ad16f-9bdf-4f72-b5c6-6314b5122996
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274633568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1274633568
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.422174678
Short name T87
Test name
Test status
Simulation time 170901661 ps
CPU time 8.85 seconds
Started Jul 04 05:04:23 PM PDT 24
Finished Jul 04 05:04:32 PM PDT 24
Peak memory 210692 kb
Host smart-c77932a6-3174-4c14-87dc-c2b14a889306
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422174678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.422174678
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2228164048
Short name T69
Test name
Test status
Simulation time 671161071 ps
CPU time 11.78 seconds
Started Jul 04 05:04:16 PM PDT 24
Finished Jul 04 05:04:28 PM PDT 24
Peak memory 211896 kb
Host smart-b13077d8-0b46-4a06-be6f-cf43fbbf79dd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228164048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2228164048
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.701490980
Short name T401
Test name
Test status
Simulation time 734399546 ps
CPU time 8.98 seconds
Started Jul 04 05:04:29 PM PDT 24
Finished Jul 04 05:04:38 PM PDT 24
Peak memory 216000 kb
Host smart-7a1a89a2-4824-4bc4-b92d-fc17af5e2b4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701490980 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.701490980
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3941632991
Short name T454
Test name
Test status
Simulation time 24413946644 ps
CPU time 31.51 seconds
Started Jul 04 05:04:24 PM PDT 24
Finished Jul 04 05:04:56 PM PDT 24
Peak memory 211448 kb
Host smart-c67be812-2f26-49dd-baf2-b9f7b3ba2108
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941632991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3941632991
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3265176688
Short name T393
Test name
Test status
Simulation time 171070542 ps
CPU time 8.13 seconds
Started Jul 04 05:04:18 PM PDT 24
Finished Jul 04 05:04:26 PM PDT 24
Peak memory 210556 kb
Host smart-d9048ae0-a921-4f97-b6f8-b9bb456e9bed
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265176688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3265176688
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.371658652
Short name T359
Test name
Test status
Simulation time 3351678000 ps
CPU time 13.46 seconds
Started Jul 04 05:04:16 PM PDT 24
Finished Jul 04 05:04:30 PM PDT 24
Peak memory 210620 kb
Host smart-02bca2a8-114e-46c9-8cd8-6e7b33eda5a5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371658652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
371658652
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3189471953
Short name T375
Test name
Test status
Simulation time 319453419 ps
CPU time 8.18 seconds
Started Jul 04 05:04:23 PM PDT 24
Finished Jul 04 05:04:31 PM PDT 24
Peak memory 211288 kb
Host smart-0d96c1a6-b577-49bf-9a17-c64ca7592e14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189471953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3189471953
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1872254522
Short name T412
Test name
Test status
Simulation time 8557813152 ps
CPU time 35.07 seconds
Started Jul 04 05:04:12 PM PDT 24
Finished Jul 04 05:04:48 PM PDT 24
Peak memory 217476 kb
Host smart-0e90993e-d250-4545-a678-7bb8c47afafd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872254522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1872254522
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1679327184
Short name T437
Test name
Test status
Simulation time 4281365998 ps
CPU time 172.45 seconds
Started Jul 04 05:04:16 PM PDT 24
Finished Jul 04 05:07:08 PM PDT 24
Peak memory 213852 kb
Host smart-3218f65f-e230-4443-84cf-f92644334800
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679327184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1679327184
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3589261149
Short name T89
Test name
Test status
Simulation time 15768209939 ps
CPU time 31.68 seconds
Started Jul 04 05:04:43 PM PDT 24
Finished Jul 04 05:05:15 PM PDT 24
Peak memory 211668 kb
Host smart-989471ce-c6e1-4c41-8178-c0357762b159
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589261149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3589261149
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.916269640
Short name T424
Test name
Test status
Simulation time 2111934280 ps
CPU time 21.3 seconds
Started Jul 04 05:04:42 PM PDT 24
Finished Jul 04 05:05:04 PM PDT 24
Peak memory 211448 kb
Host smart-81b7d3ee-dba8-4b1d-a9e4-1aecb12f4ab9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916269640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.916269640
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4275402315
Short name T93
Test name
Test status
Simulation time 12617240614 ps
CPU time 30.85 seconds
Started Jul 04 05:04:38 PM PDT 24
Finished Jul 04 05:05:09 PM PDT 24
Peak memory 211964 kb
Host smart-2fb66c10-7845-4ba6-a9c3-1664e6096748
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275402315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.4275402315
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1241540631
Short name T374
Test name
Test status
Simulation time 10594756114 ps
CPU time 24.15 seconds
Started Jul 04 05:04:46 PM PDT 24
Finished Jul 04 05:05:11 PM PDT 24
Peak memory 215408 kb
Host smart-2e160673-187d-4f42-96f1-2c0f66a96b56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241540631 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1241540631
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3931067161
Short name T421
Test name
Test status
Simulation time 1264755885 ps
CPU time 16.08 seconds
Started Jul 04 05:04:37 PM PDT 24
Finished Jul 04 05:04:53 PM PDT 24
Peak memory 210512 kb
Host smart-9dbb76a2-40b2-44fa-a3d8-fd77406a7aed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931067161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3931067161
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1253718223
Short name T407
Test name
Test status
Simulation time 648386843 ps
CPU time 10.99 seconds
Started Jul 04 05:04:36 PM PDT 24
Finished Jul 04 05:04:48 PM PDT 24
Peak memory 210568 kb
Host smart-992fa079-509f-4d16-827d-979d97687d08
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253718223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1253718223
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4229594512
Short name T386
Test name
Test status
Simulation time 2779885062 ps
CPU time 24.04 seconds
Started Jul 04 05:04:37 PM PDT 24
Finished Jul 04 05:05:01 PM PDT 24
Peak memory 210508 kb
Host smart-65ee93fd-224e-41a1-9d84-943280624c85
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229594512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.4229594512
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3968031782
Short name T96
Test name
Test status
Simulation time 4256265586 ps
CPU time 56.77 seconds
Started Jul 04 05:04:29 PM PDT 24
Finished Jul 04 05:05:26 PM PDT 24
Peak memory 215288 kb
Host smart-ad333e85-d467-40b1-b0c4-0b2cfb9b84e9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968031782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3968031782
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.766018898
Short name T71
Test name
Test status
Simulation time 3453246379 ps
CPU time 30.52 seconds
Started Jul 04 05:04:43 PM PDT 24
Finished Jul 04 05:05:14 PM PDT 24
Peak memory 212352 kb
Host smart-4896dd2e-1ead-439b-8abc-044e2813c7bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766018898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.766018898
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.109028567
Short name T447
Test name
Test status
Simulation time 174521878 ps
CPU time 13.94 seconds
Started Jul 04 05:04:30 PM PDT 24
Finished Jul 04 05:04:44 PM PDT 24
Peak memory 218540 kb
Host smart-d30e11d5-516c-44ec-95ed-3529f6ae95f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109028567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.109028567
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.967953468
Short name T390
Test name
Test status
Simulation time 2210951232 ps
CPU time 93.43 seconds
Started Jul 04 05:04:37 PM PDT 24
Finished Jul 04 05:06:11 PM PDT 24
Peak memory 213424 kb
Host smart-7bc4246c-95a1-46d3-9522-6e5b80b35a17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967953468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.967953468
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4183618360
Short name T398
Test name
Test status
Simulation time 174951562 ps
CPU time 8.78 seconds
Started Jul 04 05:04:50 PM PDT 24
Finished Jul 04 05:04:59 PM PDT 24
Peak memory 214668 kb
Host smart-8a2c79c0-25b7-4d44-a838-c9dfd1a187b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183618360 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.4183618360
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2671579770
Short name T373
Test name
Test status
Simulation time 688214263 ps
CPU time 8.15 seconds
Started Jul 04 05:04:53 PM PDT 24
Finished Jul 04 05:05:01 PM PDT 24
Peak memory 210684 kb
Host smart-f49e251f-318d-4ee7-be6b-106373db4223
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671579770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2671579770
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.338698940
Short name T416
Test name
Test status
Simulation time 4126822091 ps
CPU time 63.31 seconds
Started Jul 04 05:04:45 PM PDT 24
Finished Jul 04 05:05:49 PM PDT 24
Peak memory 214244 kb
Host smart-8a7ea65c-62be-40ed-a256-19a83cfa4064
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338698940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.338698940
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.428202618
Short name T444
Test name
Test status
Simulation time 1753373926 ps
CPU time 18.93 seconds
Started Jul 04 05:04:43 PM PDT 24
Finished Jul 04 05:05:02 PM PDT 24
Peak memory 212424 kb
Host smart-a0a3df23-e05d-494f-9c41-3a62d8545d81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428202618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.428202618
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.729709991
Short name T435
Test name
Test status
Simulation time 15753673218 ps
CPU time 36.31 seconds
Started Jul 04 05:04:43 PM PDT 24
Finished Jul 04 05:05:20 PM PDT 24
Peak memory 217872 kb
Host smart-425db701-f9ee-45f4-a461-4f4922147660
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729709991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.729709991
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3355160933
Short name T452
Test name
Test status
Simulation time 263162848 ps
CPU time 80.25 seconds
Started Jul 04 05:04:45 PM PDT 24
Finished Jul 04 05:06:05 PM PDT 24
Peak memory 218924 kb
Host smart-df2869fd-93c6-417d-88db-4c61d8b83711
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355160933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3355160933
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.50168990
Short name T429
Test name
Test status
Simulation time 13670554601 ps
CPU time 27.25 seconds
Started Jul 04 05:04:50 PM PDT 24
Finished Jul 04 05:05:17 PM PDT 24
Peak memory 217876 kb
Host smart-473a9f10-2332-4bfa-8fe6-9ae8f63e671b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50168990 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.50168990
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3086097218
Short name T402
Test name
Test status
Simulation time 2017878516 ps
CPU time 20.17 seconds
Started Jul 04 05:04:51 PM PDT 24
Finished Jul 04 05:05:11 PM PDT 24
Peak memory 210576 kb
Host smart-7977f627-0a7b-40ef-976a-f3731b90c394
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086097218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3086097218
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.4148787398
Short name T81
Test name
Test status
Simulation time 71789477336 ps
CPU time 149.04 seconds
Started Jul 04 05:04:50 PM PDT 24
Finished Jul 04 05:07:19 PM PDT 24
Peak memory 214824 kb
Host smart-bd6a96cd-d25f-45d8-afec-c5f59c458660
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148787398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.4148787398
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.424548756
Short name T400
Test name
Test status
Simulation time 668334478 ps
CPU time 14.38 seconds
Started Jul 04 05:04:54 PM PDT 24
Finished Jul 04 05:05:08 PM PDT 24
Peak memory 212432 kb
Host smart-d68c0d7a-7e7d-4ca2-9479-6678c57686f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424548756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.424548756
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2062428490
Short name T427
Test name
Test status
Simulation time 1650900168 ps
CPU time 14.7 seconds
Started Jul 04 05:04:50 PM PDT 24
Finished Jul 04 05:05:05 PM PDT 24
Peak memory 218848 kb
Host smart-eecca912-f4a3-45b3-acc7-c5025646ce05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062428490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2062428490
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1067300637
Short name T108
Test name
Test status
Simulation time 251306120 ps
CPU time 81.66 seconds
Started Jul 04 05:04:51 PM PDT 24
Finished Jul 04 05:06:12 PM PDT 24
Peak memory 213724 kb
Host smart-ff0f2b7c-83ce-4a32-83fd-92d9e3a7d1f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067300637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1067300637
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1781686354
Short name T441
Test name
Test status
Simulation time 12801400689 ps
CPU time 25.5 seconds
Started Jul 04 05:04:58 PM PDT 24
Finished Jul 04 05:05:24 PM PDT 24
Peak memory 218636 kb
Host smart-dfff230b-dd5b-4371-af0f-60fc698ae4e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781686354 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1781686354
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.10798477
Short name T456
Test name
Test status
Simulation time 1237392617 ps
CPU time 16.54 seconds
Started Jul 04 05:04:58 PM PDT 24
Finished Jul 04 05:05:15 PM PDT 24
Peak memory 211652 kb
Host smart-0a9239c2-0225-47f6-8933-260a9287fc8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10798477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.10798477
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1776333825
Short name T88
Test name
Test status
Simulation time 90762358649 ps
CPU time 194.96 seconds
Started Jul 04 05:04:52 PM PDT 24
Finished Jul 04 05:08:07 PM PDT 24
Peak memory 215044 kb
Host smart-80f27d71-0b43-4fd2-94cb-6d3456658c85
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776333825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1776333825
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3424646538
Short name T74
Test name
Test status
Simulation time 4290036874 ps
CPU time 14.89 seconds
Started Jul 04 05:04:58 PM PDT 24
Finished Jul 04 05:05:13 PM PDT 24
Peak memory 211336 kb
Host smart-26b45803-107e-44ed-80de-d6e3260321e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424646538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3424646538
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1399758200
Short name T396
Test name
Test status
Simulation time 7200695291 ps
CPU time 25.31 seconds
Started Jul 04 05:04:53 PM PDT 24
Finished Jul 04 05:05:18 PM PDT 24
Peak memory 218920 kb
Host smart-0c6aead7-8fbc-46e7-92f0-7e5fa6420b92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399758200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1399758200
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3143566042
Short name T112
Test name
Test status
Simulation time 1119068076 ps
CPU time 88.12 seconds
Started Jul 04 05:04:59 PM PDT 24
Finished Jul 04 05:06:28 PM PDT 24
Peak memory 214752 kb
Host smart-e818f772-b70d-4525-9cc5-2ccd2de30899
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143566042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3143566042
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3406459738
Short name T365
Test name
Test status
Simulation time 8050886991 ps
CPU time 30.74 seconds
Started Jul 04 05:04:58 PM PDT 24
Finished Jul 04 05:05:29 PM PDT 24
Peak memory 217356 kb
Host smart-a2117234-d3c2-46d2-857c-951a9f135f6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406459738 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3406459738
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.740758875
Short name T423
Test name
Test status
Simulation time 751817818 ps
CPU time 8.57 seconds
Started Jul 04 05:04:58 PM PDT 24
Finished Jul 04 05:05:07 PM PDT 24
Peak memory 210756 kb
Host smart-674efe5e-5ee7-43a2-8deb-6a4977511ad8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740758875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.740758875
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2100638329
Short name T405
Test name
Test status
Simulation time 2725626225 ps
CPU time 29.54 seconds
Started Jul 04 05:04:58 PM PDT 24
Finished Jul 04 05:05:28 PM PDT 24
Peak memory 212476 kb
Host smart-7531776e-ae3a-4ffc-abfb-d87a0cd8ef7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100638329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2100638329
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3792598230
Short name T360
Test name
Test status
Simulation time 16282895953 ps
CPU time 38.47 seconds
Started Jul 04 05:04:58 PM PDT 24
Finished Jul 04 05:05:37 PM PDT 24
Peak memory 217740 kb
Host smart-f32c3297-7e22-43b0-a5a6-5dbebb3fcc92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792598230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3792598230
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.738004421
Short name T59
Test name
Test status
Simulation time 1763612591 ps
CPU time 160.45 seconds
Started Jul 04 05:04:58 PM PDT 24
Finished Jul 04 05:07:39 PM PDT 24
Peak memory 212772 kb
Host smart-40f27a61-c2b8-467f-bbc7-bf5feb8c72f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738004421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.738004421
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.4091568323
Short name T410
Test name
Test status
Simulation time 6217799230 ps
CPU time 26.97 seconds
Started Jul 04 05:05:05 PM PDT 24
Finished Jul 04 05:05:32 PM PDT 24
Peak memory 216824 kb
Host smart-cb8441d5-c6a0-49d3-a470-1d07cbd1be8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091568323 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.4091568323
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3403059717
Short name T397
Test name
Test status
Simulation time 2857254155 ps
CPU time 16.7 seconds
Started Jul 04 05:05:06 PM PDT 24
Finished Jul 04 05:05:22 PM PDT 24
Peak memory 210564 kb
Host smart-90083397-d759-4472-aa1f-2314d188c7bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403059717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3403059717
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.63640827
Short name T76
Test name
Test status
Simulation time 4301716527 ps
CPU time 57.28 seconds
Started Jul 04 05:05:07 PM PDT 24
Finished Jul 04 05:06:05 PM PDT 24
Peak memory 214504 kb
Host smart-d48db403-70f8-45fb-9c34-b40f65b86de8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63640827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pass
thru_mem_tl_intg_err.63640827
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3588692373
Short name T453
Test name
Test status
Simulation time 13646256939 ps
CPU time 27.36 seconds
Started Jul 04 05:05:04 PM PDT 24
Finished Jul 04 05:05:33 PM PDT 24
Peak memory 212340 kb
Host smart-c08dc055-271b-42be-97fb-f540a84e6c86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588692373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3588692373
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.408797684
Short name T367
Test name
Test status
Simulation time 174186733 ps
CPU time 11.27 seconds
Started Jul 04 05:05:04 PM PDT 24
Finished Jul 04 05:05:16 PM PDT 24
Peak memory 216888 kb
Host smart-c45a9636-dc9a-4467-97e2-a8ec0c92c53d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408797684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.408797684
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2153772609
Short name T438
Test name
Test status
Simulation time 3921430251 ps
CPU time 99.84 seconds
Started Jul 04 05:05:05 PM PDT 24
Finished Jul 04 05:06:45 PM PDT 24
Peak memory 218892 kb
Host smart-41427c18-b48c-4620-b6ac-410b7ca927c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153772609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2153772609
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.973087354
Short name T122
Test name
Test status
Simulation time 181871220 ps
CPU time 8.38 seconds
Started Jul 04 05:03:36 PM PDT 24
Finished Jul 04 05:03:45 PM PDT 24
Peak memory 217108 kb
Host smart-c08262fc-4001-4c8d-8eeb-bf651e277223
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973087354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.973087354
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2833356583
Short name T310
Test name
Test status
Simulation time 292295088509 ps
CPU time 742.74 seconds
Started Jul 04 05:03:31 PM PDT 24
Finished Jul 04 05:15:54 PM PDT 24
Peak memory 239680 kb
Host smart-98b7b44f-6dc3-481d-8d78-e3b064a83581
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833356583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2833356583
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2203036169
Short name T278
Test name
Test status
Simulation time 16109825192 ps
CPU time 66.37 seconds
Started Jul 04 05:03:31 PM PDT 24
Finished Jul 04 05:04:38 PM PDT 24
Peak memory 219116 kb
Host smart-06064ada-9cf3-43b6-941a-99fce1437f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203036169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2203036169
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1729763414
Short name T129
Test name
Test status
Simulation time 741869141 ps
CPU time 10.51 seconds
Started Jul 04 05:03:37 PM PDT 24
Finished Jul 04 05:03:48 PM PDT 24
Peak memory 219216 kb
Host smart-898cdb18-6f45-46e0-811f-e7493790dce9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1729763414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1729763414
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.919491591
Short name T19
Test name
Test status
Simulation time 885161067 ps
CPU time 115.49 seconds
Started Jul 04 05:03:37 PM PDT 24
Finished Jul 04 05:05:33 PM PDT 24
Peak memory 237392 kb
Host smart-7ada5132-7b2e-4130-8637-8956269303b4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919491591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.919491591
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2343410257
Short name T79
Test name
Test status
Simulation time 5356083963 ps
CPU time 56.25 seconds
Started Jul 04 05:03:32 PM PDT 24
Finished Jul 04 05:04:29 PM PDT 24
Peak memory 216288 kb
Host smart-72675244-d5fd-41d1-9b63-05543ddc4450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343410257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2343410257
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.895873689
Short name T243
Test name
Test status
Simulation time 16751266190 ps
CPU time 135.36 seconds
Started Jul 04 05:03:35 PM PDT 24
Finished Jul 04 05:05:51 PM PDT 24
Peak memory 220304 kb
Host smart-11441a11-db11-4eea-afd8-b1a129b12808
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895873689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.895873689
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.2644899982
Short name T9
Test name
Test status
Simulation time 264574456430 ps
CPU time 2603.32 seconds
Started Jul 04 05:03:29 PM PDT 24
Finished Jul 04 05:46:53 PM PDT 24
Peak memory 248872 kb
Host smart-1c1a13d8-cffd-4051-b2ae-d1b5fd9894de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644899982 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.2644899982
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1669416868
Short name T206
Test name
Test status
Simulation time 552826343622 ps
CPU time 835.49 seconds
Started Jul 04 05:03:30 PM PDT 24
Finished Jul 04 05:17:26 PM PDT 24
Peak memory 237164 kb
Host smart-7d392a19-dcd3-45c8-a546-b5954af141bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669416868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1669416868
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3075130830
Short name T323
Test name
Test status
Simulation time 26910690870 ps
CPU time 63.58 seconds
Started Jul 04 05:03:31 PM PDT 24
Finished Jul 04 05:04:35 PM PDT 24
Peak memory 219236 kb
Host smart-7a61720b-8d19-48a0-9c20-0aa3795a95c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075130830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3075130830
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3147524927
Short name T355
Test name
Test status
Simulation time 12259009182 ps
CPU time 26.09 seconds
Started Jul 04 05:03:30 PM PDT 24
Finished Jul 04 05:03:57 PM PDT 24
Peak memory 211948 kb
Host smart-60daccd6-fc32-41a5-932b-c10baf63ab89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3147524927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3147524927
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2335758684
Short name T18
Test name
Test status
Simulation time 1218341106 ps
CPU time 116.38 seconds
Started Jul 04 05:03:35 PM PDT 24
Finished Jul 04 05:05:32 PM PDT 24
Peak memory 236748 kb
Host smart-730d9f74-b2b3-48e5-90bb-c8b6934907d6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335758684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2335758684
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1108994046
Short name T292
Test name
Test status
Simulation time 2868859374 ps
CPU time 37 seconds
Started Jul 04 05:03:34 PM PDT 24
Finished Jul 04 05:04:11 PM PDT 24
Peak memory 216308 kb
Host smart-c33ab122-2391-4be9-b74e-609a5ed060ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108994046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1108994046
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3672610007
Short name T213
Test name
Test status
Simulation time 19328205084 ps
CPU time 159.02 seconds
Started Jul 04 05:03:30 PM PDT 24
Finished Jul 04 05:06:09 PM PDT 24
Peak memory 221788 kb
Host smart-3ca73e1b-9b18-48b9-b5ca-768f7ecf9964
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672610007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3672610007
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.249942420
Short name T54
Test name
Test status
Simulation time 43217054528 ps
CPU time 2014.23 seconds
Started Jul 04 05:03:32 PM PDT 24
Finished Jul 04 05:37:07 PM PDT 24
Peak memory 234644 kb
Host smart-69c34fe3-2572-4094-bef1-f3140495d04d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249942420 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.249942420
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1514006902
Short name T152
Test name
Test status
Simulation time 7561722639 ps
CPU time 19.92 seconds
Started Jul 04 05:03:49 PM PDT 24
Finished Jul 04 05:04:09 PM PDT 24
Peak memory 213248 kb
Host smart-05b8563f-982e-4eb8-95f9-11b1bae48840
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514006902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1514006902
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.4036546819
Short name T324
Test name
Test status
Simulation time 344221904754 ps
CPU time 816.86 seconds
Started Jul 04 05:03:46 PM PDT 24
Finished Jul 04 05:17:23 PM PDT 24
Peak memory 233628 kb
Host smart-e304de10-4a17-4493-b344-bbcb924611d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036546819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.4036546819
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.42778994
Short name T189
Test name
Test status
Simulation time 2154630294 ps
CPU time 22.5 seconds
Started Jul 04 05:03:50 PM PDT 24
Finished Jul 04 05:04:13 PM PDT 24
Peak memory 219228 kb
Host smart-3c070550-fa1f-495f-aaa5-fd07b5ae9024
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=42778994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.42778994
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.614137280
Short name T30
Test name
Test status
Simulation time 24071492935 ps
CPU time 58.35 seconds
Started Jul 04 05:03:45 PM PDT 24
Finished Jul 04 05:04:44 PM PDT 24
Peak memory 217028 kb
Host smart-a2bccd8c-2f58-4efc-a83d-3e20a44049f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614137280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.614137280
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1999492484
Short name T315
Test name
Test status
Simulation time 14040797275 ps
CPU time 136.29 seconds
Started Jul 04 05:03:46 PM PDT 24
Finished Jul 04 05:06:03 PM PDT 24
Peak memory 219600 kb
Host smart-ba96b167-b9b2-4a0c-9dfc-a878fde06a3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999492484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1999492484
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1858212396
Short name T144
Test name
Test status
Simulation time 6657187530 ps
CPU time 19.57 seconds
Started Jul 04 05:03:47 PM PDT 24
Finished Jul 04 05:04:06 PM PDT 24
Peak memory 213284 kb
Host smart-09b7f695-1f0f-487a-bc4a-0210f78f0420
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858212396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1858212396
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1076733290
Short name T194
Test name
Test status
Simulation time 33484905285 ps
CPU time 326.72 seconds
Started Jul 04 05:03:46 PM PDT 24
Finished Jul 04 05:09:13 PM PDT 24
Peak memory 236776 kb
Host smart-dd598bfd-b786-4625-afd9-03c7ef0fb5a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076733290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1076733290
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3069938457
Short name T317
Test name
Test status
Simulation time 5001888875 ps
CPU time 35.17 seconds
Started Jul 04 05:03:46 PM PDT 24
Finished Jul 04 05:04:22 PM PDT 24
Peak memory 219096 kb
Host smart-3d0d699e-c365-47fe-8be4-18b0e144f0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069938457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3069938457
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1068882306
Short name T321
Test name
Test status
Simulation time 2169510542 ps
CPU time 21.52 seconds
Started Jul 04 05:03:46 PM PDT 24
Finished Jul 04 05:04:08 PM PDT 24
Peak memory 219344 kb
Host smart-8ff5861f-9bb9-4eb8-95b0-7943c48ff46a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1068882306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1068882306
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.984893975
Short name T134
Test name
Test status
Simulation time 50908829794 ps
CPU time 57.34 seconds
Started Jul 04 05:03:48 PM PDT 24
Finished Jul 04 05:04:45 PM PDT 24
Peak memory 218336 kb
Host smart-82295f5d-2f73-47c6-bf58-3d3624bf15ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984893975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.984893975
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.4140116498
Short name T159
Test name
Test status
Simulation time 548788463 ps
CPU time 30.94 seconds
Started Jul 04 05:03:47 PM PDT 24
Finished Jul 04 05:04:19 PM PDT 24
Peak memory 220272 kb
Host smart-8a25b2fc-e268-4ff4-badb-903813fa6c18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140116498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.4140116498
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.641658536
Short name T29
Test name
Test status
Simulation time 687947998 ps
CPU time 8.48 seconds
Started Jul 04 05:03:45 PM PDT 24
Finished Jul 04 05:03:54 PM PDT 24
Peak memory 213220 kb
Host smart-2efca155-5618-4774-981f-8db98bb35fa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641658536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.641658536
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3361902275
Short name T277
Test name
Test status
Simulation time 1750670665 ps
CPU time 13.37 seconds
Started Jul 04 05:03:45 PM PDT 24
Finished Jul 04 05:03:59 PM PDT 24
Peak memory 218716 kb
Host smart-40396473-059f-4591-90da-919aaded58fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3361902275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3361902275
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.377271156
Short name T158
Test name
Test status
Simulation time 6505432049 ps
CPU time 69.35 seconds
Started Jul 04 05:03:49 PM PDT 24
Finished Jul 04 05:04:59 PM PDT 24
Peak memory 216180 kb
Host smart-1f297165-9f7d-4033-b1e8-c4799c7ac874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377271156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.377271156
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2649139145
Short name T121
Test name
Test status
Simulation time 24792958525 ps
CPU time 32.01 seconds
Started Jul 04 05:03:47 PM PDT 24
Finished Jul 04 05:04:19 PM PDT 24
Peak memory 219316 kb
Host smart-d059cecd-5d1c-4968-b7f0-4bc9ea395663
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649139145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2649139145
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3913662804
Short name T250
Test name
Test status
Simulation time 9884184369 ps
CPU time 23.23 seconds
Started Jul 04 05:03:52 PM PDT 24
Finished Jul 04 05:04:17 PM PDT 24
Peak memory 217464 kb
Host smart-f0205112-8f29-4394-9b11-64d748a634ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913662804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3913662804
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3933166089
Short name T208
Test name
Test status
Simulation time 5933159552 ps
CPU time 29.95 seconds
Started Jul 04 05:03:53 PM PDT 24
Finished Jul 04 05:04:24 PM PDT 24
Peak memory 219316 kb
Host smart-58a5a649-48e1-4597-a459-c27849ea6f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933166089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3933166089
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.273041803
Short name T345
Test name
Test status
Simulation time 3374302296 ps
CPU time 30.22 seconds
Started Jul 04 05:03:53 PM PDT 24
Finished Jul 04 05:04:24 PM PDT 24
Peak memory 211320 kb
Host smart-da17c690-491f-408f-a63b-a5329da752b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=273041803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.273041803
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.834901900
Short name T283
Test name
Test status
Simulation time 1634508854 ps
CPU time 19.55 seconds
Started Jul 04 05:03:53 PM PDT 24
Finished Jul 04 05:04:13 PM PDT 24
Peak memory 215792 kb
Host smart-eae18968-5d74-42bb-aa37-e215652c5682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834901900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.834901900
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.59433561
Short name T296
Test name
Test status
Simulation time 4404519669 ps
CPU time 36.69 seconds
Started Jul 04 05:03:57 PM PDT 24
Finished Jul 04 05:04:34 PM PDT 24
Peak memory 217344 kb
Host smart-05924db2-9ad4-42b9-b477-2da0d11a7877
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59433561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 13.rom_ctrl_stress_all.59433561
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.1677067156
Short name T52
Test name
Test status
Simulation time 19711935900 ps
CPU time 186.95 seconds
Started Jul 04 05:03:56 PM PDT 24
Finished Jul 04 05:07:04 PM PDT 24
Peak memory 220640 kb
Host smart-de6dc58c-e1c1-46b4-8026-0aa33af11fd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677067156 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.1677067156
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1584123995
Short name T274
Test name
Test status
Simulation time 2195906413 ps
CPU time 21.52 seconds
Started Jul 04 05:03:54 PM PDT 24
Finished Jul 04 05:04:16 PM PDT 24
Peak memory 217112 kb
Host smart-dd091e01-e243-4b66-9043-b7f72b1235d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584123995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1584123995
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.720179346
Short name T337
Test name
Test status
Simulation time 185959955802 ps
CPU time 643.16 seconds
Started Jul 04 05:03:52 PM PDT 24
Finished Jul 04 05:14:37 PM PDT 24
Peak memory 233876 kb
Host smart-f16a9638-50b3-43ec-8230-a06899dca967
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720179346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.720179346
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1513273937
Short name T23
Test name
Test status
Simulation time 29400556512 ps
CPU time 57.56 seconds
Started Jul 04 05:04:01 PM PDT 24
Finished Jul 04 05:04:59 PM PDT 24
Peak memory 219336 kb
Host smart-7420b8d2-9afe-4b50-9060-38bc9884efc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513273937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1513273937
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.706284317
Short name T244
Test name
Test status
Simulation time 2118935151 ps
CPU time 17.17 seconds
Started Jul 04 05:03:56 PM PDT 24
Finished Jul 04 05:04:14 PM PDT 24
Peak memory 218576 kb
Host smart-532ffe86-dd53-46e3-8629-b172ec7ec76c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=706284317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.706284317
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.733745230
Short name T354
Test name
Test status
Simulation time 15932609541 ps
CPU time 35.3 seconds
Started Jul 04 05:03:56 PM PDT 24
Finished Jul 04 05:04:32 PM PDT 24
Peak memory 214576 kb
Host smart-683bd771-425c-4617-84fd-0c2168d41401
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733745230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.733745230
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1541366718
Short name T164
Test name
Test status
Simulation time 12946625110 ps
CPU time 26.73 seconds
Started Jul 04 05:03:53 PM PDT 24
Finished Jul 04 05:04:20 PM PDT 24
Peak memory 217532 kb
Host smart-c2e1bb32-af3c-433d-a8ff-2f88e6612025
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541366718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1541366718
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1092660893
Short name T231
Test name
Test status
Simulation time 131404875427 ps
CPU time 640.67 seconds
Started Jul 04 05:03:56 PM PDT 24
Finished Jul 04 05:14:37 PM PDT 24
Peak memory 233592 kb
Host smart-0ec53cdc-d205-4592-8646-518f9cdbdfad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092660893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1092660893
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.360396204
Short name T148
Test name
Test status
Simulation time 27840130492 ps
CPU time 65.88 seconds
Started Jul 04 05:03:55 PM PDT 24
Finished Jul 04 05:05:01 PM PDT 24
Peak memory 219272 kb
Host smart-cc0d5639-e71f-4dfc-8cf7-adc6632aa7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360396204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.360396204
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2694310614
Short name T147
Test name
Test status
Simulation time 3609516809 ps
CPU time 29.56 seconds
Started Jul 04 05:03:54 PM PDT 24
Finished Jul 04 05:04:24 PM PDT 24
Peak memory 219616 kb
Host smart-865fd35c-3964-46e3-9217-636b52af3e9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2694310614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2694310614
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.2854053286
Short name T80
Test name
Test status
Simulation time 1432947540 ps
CPU time 20.83 seconds
Started Jul 04 05:03:55 PM PDT 24
Finished Jul 04 05:04:17 PM PDT 24
Peak memory 217092 kb
Host smart-2458651b-fe57-450e-a8f3-4ffd3b627cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854053286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2854053286
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3048841265
Short name T258
Test name
Test status
Simulation time 26729042692 ps
CPU time 76.35 seconds
Started Jul 04 05:03:56 PM PDT 24
Finished Jul 04 05:05:13 PM PDT 24
Peak memory 217196 kb
Host smart-b10dc23c-b4f5-4947-b15f-f9cf82afc5d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048841265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3048841265
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1869547442
Short name T166
Test name
Test status
Simulation time 19997378349 ps
CPU time 22.76 seconds
Started Jul 04 05:03:55 PM PDT 24
Finished Jul 04 05:04:18 PM PDT 24
Peak memory 217432 kb
Host smart-6ece8b18-f23a-46b1-a790-694314b31201
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869547442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1869547442
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3965186113
Short name T319
Test name
Test status
Simulation time 217475718404 ps
CPU time 569.39 seconds
Started Jul 04 05:03:55 PM PDT 24
Finished Jul 04 05:13:25 PM PDT 24
Peak memory 237036 kb
Host smart-1128dc78-fba5-4352-a754-d4bef9664118
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965186113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3965186113
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3820670153
Short name T312
Test name
Test status
Simulation time 21843113984 ps
CPU time 52.84 seconds
Started Jul 04 05:03:56 PM PDT 24
Finished Jul 04 05:04:49 PM PDT 24
Peak memory 219228 kb
Host smart-dfaff5b5-669f-4035-830a-d04c47c69e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820670153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3820670153
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.293927498
Short name T135
Test name
Test status
Simulation time 2408665565 ps
CPU time 23.59 seconds
Started Jul 04 05:04:00 PM PDT 24
Finished Jul 04 05:04:24 PM PDT 24
Peak memory 211660 kb
Host smart-90c63ba4-239c-4c42-85a6-de19967bade0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=293927498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.293927498
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.430763238
Short name T271
Test name
Test status
Simulation time 11993727368 ps
CPU time 62.02 seconds
Started Jul 04 05:03:53 PM PDT 24
Finished Jul 04 05:04:55 PM PDT 24
Peak memory 216716 kb
Host smart-f5bf2960-7b1e-43c9-929a-3d78d655197c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430763238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.430763238
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3590745120
Short name T203
Test name
Test status
Simulation time 13331058220 ps
CPU time 161.25 seconds
Started Jul 04 05:04:04 PM PDT 24
Finished Jul 04 05:06:45 PM PDT 24
Peak memory 219444 kb
Host smart-e0c273c7-eda0-4805-8d5b-6df47337cec5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590745120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3590745120
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2527336660
Short name T232
Test name
Test status
Simulation time 32133064390 ps
CPU time 26.16 seconds
Started Jul 04 05:03:54 PM PDT 24
Finished Jul 04 05:04:20 PM PDT 24
Peak memory 217352 kb
Host smart-98bee772-525d-4721-8150-3276c0e81015
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527336660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2527336660
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3457113757
Short name T326
Test name
Test status
Simulation time 3669439427 ps
CPU time 227.94 seconds
Started Jul 04 05:03:56 PM PDT 24
Finished Jul 04 05:07:44 PM PDT 24
Peak memory 219472 kb
Host smart-33c4bf6a-c371-4f88-aa4c-cc111545cfd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457113757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3457113757
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.792846365
Short name T236
Test name
Test status
Simulation time 19309567476 ps
CPU time 44.43 seconds
Started Jul 04 05:03:55 PM PDT 24
Finished Jul 04 05:04:40 PM PDT 24
Peak memory 219260 kb
Host smart-f3652c63-a92e-442a-bfdf-cc096776f991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792846365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.792846365
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.4221461086
Short name T2
Test name
Test status
Simulation time 15908249802 ps
CPU time 32.63 seconds
Started Jul 04 05:03:56 PM PDT 24
Finished Jul 04 05:04:29 PM PDT 24
Peak memory 211764 kb
Host smart-eb7df289-a7a7-4cb1-8ee8-8b814fc0b4e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4221461086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.4221461086
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.468023498
Short name T146
Test name
Test status
Simulation time 533092925 ps
CPU time 24.3 seconds
Started Jul 04 05:03:53 PM PDT 24
Finished Jul 04 05:04:18 PM PDT 24
Peak memory 216324 kb
Host smart-fa87b7cd-757f-4b15-8352-bb0f048eded8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468023498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.468023498
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.471499417
Short name T255
Test name
Test status
Simulation time 34904261455 ps
CPU time 65.43 seconds
Started Jul 04 05:03:54 PM PDT 24
Finished Jul 04 05:05:00 PM PDT 24
Peak memory 216956 kb
Host smart-8432a058-5941-4e44-984f-7ab77bfca338
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471499417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.471499417
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1436316600
Short name T21
Test name
Test status
Simulation time 15101734929 ps
CPU time 29.5 seconds
Started Jul 04 05:03:53 PM PDT 24
Finished Jul 04 05:04:23 PM PDT 24
Peak memory 217352 kb
Host smart-841ad18d-18d7-4941-bc36-7730eba74e7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436316600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1436316600
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1375281303
Short name T201
Test name
Test status
Simulation time 209088704589 ps
CPU time 516.54 seconds
Started Jul 04 05:03:54 PM PDT 24
Finished Jul 04 05:12:31 PM PDT 24
Peak memory 225936 kb
Host smart-9771e3f9-524b-47e5-ae8c-88c7573c2cdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375281303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1375281303
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.700468732
Short name T302
Test name
Test status
Simulation time 663038942 ps
CPU time 19.35 seconds
Started Jul 04 05:03:57 PM PDT 24
Finished Jul 04 05:04:16 PM PDT 24
Peak memory 219184 kb
Host smart-e54d3ed8-f8bd-445a-9dd4-a2523b048cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700468732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.700468732
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2360326639
Short name T154
Test name
Test status
Simulation time 12820123959 ps
CPU time 29.05 seconds
Started Jul 04 05:03:54 PM PDT 24
Finished Jul 04 05:04:23 PM PDT 24
Peak memory 211796 kb
Host smart-f793a0ca-d057-4b66-a7dc-21a90360e8bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2360326639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2360326639
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.864687463
Short name T262
Test name
Test status
Simulation time 18489766460 ps
CPU time 69.35 seconds
Started Jul 04 05:03:56 PM PDT 24
Finished Jul 04 05:05:05 PM PDT 24
Peak memory 216432 kb
Host smart-ab99b320-6d07-45cd-8936-4091bf6dd297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864687463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.864687463
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3249506387
Short name T281
Test name
Test status
Simulation time 49517309781 ps
CPU time 100.83 seconds
Started Jul 04 05:03:57 PM PDT 24
Finished Jul 04 05:05:38 PM PDT 24
Peak memory 219272 kb
Host smart-41cbe1e7-9d29-4019-ad00-e1946a106d42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249506387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3249506387
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2814174923
Short name T322
Test name
Test status
Simulation time 22839614489 ps
CPU time 31.17 seconds
Started Jul 04 05:04:02 PM PDT 24
Finished Jul 04 05:04:33 PM PDT 24
Peak memory 217380 kb
Host smart-4be717e7-346a-476e-b2fa-e17599e7fab9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814174923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2814174923
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2526950696
Short name T273
Test name
Test status
Simulation time 25355037234 ps
CPU time 226.01 seconds
Started Jul 04 05:04:00 PM PDT 24
Finished Jul 04 05:07:47 PM PDT 24
Peak memory 228996 kb
Host smart-787985a7-2a98-4cf9-90ed-019e903455ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526950696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2526950696
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1711430662
Short name T265
Test name
Test status
Simulation time 79870585473 ps
CPU time 32.73 seconds
Started Jul 04 05:04:02 PM PDT 24
Finished Jul 04 05:04:35 PM PDT 24
Peak memory 219308 kb
Host smart-918bbe54-f4e8-409d-8c93-9092191616e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1711430662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1711430662
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.2700379473
Short name T223
Test name
Test status
Simulation time 1273643725 ps
CPU time 19.78 seconds
Started Jul 04 05:04:03 PM PDT 24
Finished Jul 04 05:04:22 PM PDT 24
Peak memory 215816 kb
Host smart-2fa70eb9-ff2c-49dc-b643-de6b4299ddb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700379473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.2700379473
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2009637850
Short name T247
Test name
Test status
Simulation time 27488464494 ps
CPU time 82.18 seconds
Started Jul 04 05:03:56 PM PDT 24
Finished Jul 04 05:05:19 PM PDT 24
Peak memory 219300 kb
Host smart-79616ed3-47d8-45ef-9851-d8ca33a8100c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009637850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2009637850
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3961094130
Short name T314
Test name
Test status
Simulation time 413173164 ps
CPU time 11.25 seconds
Started Jul 04 05:03:41 PM PDT 24
Finished Jul 04 05:03:53 PM PDT 24
Peak memory 217040 kb
Host smart-a5ac1d3e-b38b-4b37-85e5-e3250de89fb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961094130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3961094130
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1507028920
Short name T35
Test name
Test status
Simulation time 87783141817 ps
CPU time 325.37 seconds
Started Jul 04 05:03:37 PM PDT 24
Finished Jul 04 05:09:03 PM PDT 24
Peak memory 236172 kb
Host smart-c62568ff-20a0-4ec6-aebb-1bc180e611d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507028920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1507028920
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1535508621
Short name T214
Test name
Test status
Simulation time 16689907436 ps
CPU time 69.33 seconds
Started Jul 04 05:03:37 PM PDT 24
Finished Jul 04 05:04:47 PM PDT 24
Peak memory 219300 kb
Host smart-5ab9a667-878c-4901-b2f2-8e1919a0384d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535508621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1535508621
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1781477067
Short name T168
Test name
Test status
Simulation time 10800933756 ps
CPU time 26.09 seconds
Started Jul 04 05:03:37 PM PDT 24
Finished Jul 04 05:04:03 PM PDT 24
Peak memory 219288 kb
Host smart-f3b54b3c-f86b-4667-b35f-c069b3bdb8f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1781477067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1781477067
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3554645326
Short name T25
Test name
Test status
Simulation time 2907051938 ps
CPU time 137.76 seconds
Started Jul 04 05:03:39 PM PDT 24
Finished Jul 04 05:05:57 PM PDT 24
Peak memory 237620 kb
Host smart-51be52be-1388-4453-b479-dfd07f9a78e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554645326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3554645326
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1674309534
Short name T228
Test name
Test status
Simulation time 6994759327 ps
CPU time 50.72 seconds
Started Jul 04 05:03:37 PM PDT 24
Finished Jul 04 05:04:28 PM PDT 24
Peak memory 219324 kb
Host smart-ca65c534-d3e5-47cf-af88-39bf0dda1c69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674309534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1674309534
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3130959427
Short name T351
Test name
Test status
Simulation time 509880082 ps
CPU time 11.92 seconds
Started Jul 04 05:03:59 PM PDT 24
Finished Jul 04 05:04:11 PM PDT 24
Peak memory 218104 kb
Host smart-216ffac6-35e1-4386-b9a4-dcfbb8177f6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130959427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3130959427
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.377944857
Short name T39
Test name
Test status
Simulation time 54334637894 ps
CPU time 536.83 seconds
Started Jul 04 05:04:00 PM PDT 24
Finished Jul 04 05:12:57 PM PDT 24
Peak memory 233728 kb
Host smart-26270bf9-4f89-4cc5-bfd1-7c07b10b51f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377944857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.377944857
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.957520290
Short name T252
Test name
Test status
Simulation time 6287700696 ps
CPU time 58.13 seconds
Started Jul 04 05:04:00 PM PDT 24
Finished Jul 04 05:04:58 PM PDT 24
Peak memory 219272 kb
Host smart-a1eafe84-c991-420a-8cbf-efa0aa8d17cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957520290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.957520290
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.32352558
Short name T4
Test name
Test status
Simulation time 175298972 ps
CPU time 10.11 seconds
Started Jul 04 05:03:59 PM PDT 24
Finished Jul 04 05:04:10 PM PDT 24
Peak memory 219292 kb
Host smart-66caac69-1fc2-48d5-9da2-015194be2a77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=32352558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.32352558
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3142671090
Short name T221
Test name
Test status
Simulation time 7562549594 ps
CPU time 49.06 seconds
Started Jul 04 05:04:02 PM PDT 24
Finished Jul 04 05:04:51 PM PDT 24
Peak memory 217264 kb
Host smart-8e162ead-d25a-42d5-9d8a-2e5b6be0a323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142671090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3142671090
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3017507474
Short name T286
Test name
Test status
Simulation time 19291586772 ps
CPU time 102.45 seconds
Started Jul 04 05:04:03 PM PDT 24
Finished Jul 04 05:05:46 PM PDT 24
Peak memory 219352 kb
Host smart-abf77558-1a87-4d1c-8278-33bcd2c129d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017507474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3017507474
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1485338252
Short name T346
Test name
Test status
Simulation time 5205508118 ps
CPU time 23.47 seconds
Started Jul 04 05:04:06 PM PDT 24
Finished Jul 04 05:04:30 PM PDT 24
Peak memory 217452 kb
Host smart-e13c57ec-3545-4c59-afea-50ecf9fcf477
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485338252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1485338252
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1025174760
Short name T40
Test name
Test status
Simulation time 63530113179 ps
CPU time 689.95 seconds
Started Jul 04 05:04:12 PM PDT 24
Finished Jul 04 05:15:42 PM PDT 24
Peak memory 229416 kb
Host smart-8bee6f91-10ef-4745-afee-d7832cfa144b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025174760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1025174760
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2904890302
Short name T197
Test name
Test status
Simulation time 22897163477 ps
CPU time 53.52 seconds
Started Jul 04 05:04:09 PM PDT 24
Finished Jul 04 05:05:03 PM PDT 24
Peak memory 219280 kb
Host smart-39a22384-f8b2-49e3-8531-abed1424e1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904890302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2904890302
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2972527795
Short name T276
Test name
Test status
Simulation time 2181584700 ps
CPU time 10.67 seconds
Started Jul 04 05:04:07 PM PDT 24
Finished Jul 04 05:04:18 PM PDT 24
Peak memory 219316 kb
Host smart-39519552-f8a3-4df1-98f5-d58201d4f317
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2972527795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2972527795
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2467601020
Short name T298
Test name
Test status
Simulation time 52273488586 ps
CPU time 62.97 seconds
Started Jul 04 05:04:04 PM PDT 24
Finished Jul 04 05:05:07 PM PDT 24
Peak memory 219328 kb
Host smart-193eb022-c49c-4cad-aa7f-e14673497436
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467601020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2467601020
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.3866931755
Short name T11
Test name
Test status
Simulation time 211040345277 ps
CPU time 1985.33 seconds
Started Jul 04 05:04:08 PM PDT 24
Finished Jul 04 05:37:13 PM PDT 24
Peak memory 240644 kb
Host smart-afbea1ce-1328-4cb0-a77a-c78ca025e8b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866931755 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.3866931755
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1996954587
Short name T143
Test name
Test status
Simulation time 584290605 ps
CPU time 12.41 seconds
Started Jul 04 05:04:08 PM PDT 24
Finished Jul 04 05:04:21 PM PDT 24
Peak memory 216984 kb
Host smart-7a2dab36-d6ca-4558-893d-a840ced22e47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996954587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1996954587
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3523084093
Short name T33
Test name
Test status
Simulation time 65770168360 ps
CPU time 623.72 seconds
Started Jul 04 05:04:12 PM PDT 24
Finished Jul 04 05:14:36 PM PDT 24
Peak memory 226768 kb
Host smart-9f1e3f44-d20b-4246-8f15-8e7776955a1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523084093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3523084093
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.14976253
Short name T191
Test name
Test status
Simulation time 8085259521 ps
CPU time 53.91 seconds
Started Jul 04 05:04:09 PM PDT 24
Finished Jul 04 05:05:03 PM PDT 24
Peak memory 219288 kb
Host smart-a761c3e8-ba55-47fe-8535-41c1f616b13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14976253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.14976253
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1112952789
Short name T45
Test name
Test status
Simulation time 9226023370 ps
CPU time 22.54 seconds
Started Jul 04 05:04:12 PM PDT 24
Finished Jul 04 05:04:34 PM PDT 24
Peak memory 211940 kb
Host smart-78a8c733-e596-433a-b041-fbaaf86dd3c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1112952789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1112952789
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2537384503
Short name T234
Test name
Test status
Simulation time 1542865183 ps
CPU time 30.03 seconds
Started Jul 04 05:04:08 PM PDT 24
Finished Jul 04 05:04:38 PM PDT 24
Peak memory 215652 kb
Host smart-c3eb1319-c87d-417f-9a68-a725b50ac13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537384503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2537384503
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1452564434
Short name T200
Test name
Test status
Simulation time 65152983642 ps
CPU time 155.2 seconds
Started Jul 04 05:04:13 PM PDT 24
Finished Jul 04 05:06:48 PM PDT 24
Peak memory 219752 kb
Host smart-0aee6f0b-0943-4cae-8a5b-fe0f5d90605b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452564434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1452564434
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.850098621
Short name T260
Test name
Test status
Simulation time 3076077007 ps
CPU time 17.75 seconds
Started Jul 04 05:04:12 PM PDT 24
Finished Jul 04 05:04:30 PM PDT 24
Peak memory 217120 kb
Host smart-82baf1ce-d9b1-4d68-b73e-f29cdfab9d6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850098621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.850098621
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2548004448
Short name T41
Test name
Test status
Simulation time 10658086600 ps
CPU time 177.43 seconds
Started Jul 04 05:04:11 PM PDT 24
Finished Jul 04 05:07:09 PM PDT 24
Peak memory 236144 kb
Host smart-04da7e09-6c22-4709-a84e-b965a9ccb3b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548004448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2548004448
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1392639191
Short name T153
Test name
Test status
Simulation time 6363029241 ps
CPU time 54.19 seconds
Started Jul 04 05:04:07 PM PDT 24
Finished Jul 04 05:05:01 PM PDT 24
Peak memory 219316 kb
Host smart-d1bd1db6-2cb7-4297-8b36-c93130e6031f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392639191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1392639191
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1039723713
Short name T124
Test name
Test status
Simulation time 297937674 ps
CPU time 12.08 seconds
Started Jul 04 05:04:12 PM PDT 24
Finished Jul 04 05:04:24 PM PDT 24
Peak memory 219212 kb
Host smart-11c50ea9-e82d-4990-bb40-459fb599a3ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1039723713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1039723713
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1317893178
Short name T167
Test name
Test status
Simulation time 22573530157 ps
CPU time 35.92 seconds
Started Jul 04 05:04:08 PM PDT 24
Finished Jul 04 05:04:44 PM PDT 24
Peak memory 217076 kb
Host smart-82aa41f9-db0e-413b-bed2-ee71504d7406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317893178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1317893178
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1743466963
Short name T177
Test name
Test status
Simulation time 2346686440 ps
CPU time 27.61 seconds
Started Jul 04 05:04:12 PM PDT 24
Finished Jul 04 05:04:40 PM PDT 24
Peak memory 219296 kb
Host smart-f3dc8ce2-ed6f-47d7-88fd-f6a78241b965
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743466963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1743466963
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.152165601
Short name T66
Test name
Test status
Simulation time 167309084 ps
CPU time 8.43 seconds
Started Jul 04 05:04:16 PM PDT 24
Finished Jul 04 05:04:25 PM PDT 24
Peak memory 217084 kb
Host smart-fc795f75-5bd1-4603-a25a-76f130611a5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152165601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.152165601
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.970414479
Short name T162
Test name
Test status
Simulation time 174537559517 ps
CPU time 483.79 seconds
Started Jul 04 05:04:12 PM PDT 24
Finished Jul 04 05:12:16 PM PDT 24
Peak memory 233464 kb
Host smart-83b0a775-e719-4ae0-8e56-8f06a77986c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970414479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.970414479
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1692821949
Short name T47
Test name
Test status
Simulation time 1377888898 ps
CPU time 18.99 seconds
Started Jul 04 05:04:17 PM PDT 24
Finished Jul 04 05:04:36 PM PDT 24
Peak memory 219268 kb
Host smart-7c4694c4-67aa-4108-b425-beed4b457abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692821949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1692821949
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3195233583
Short name T184
Test name
Test status
Simulation time 4115780457 ps
CPU time 31.77 seconds
Started Jul 04 05:04:12 PM PDT 24
Finished Jul 04 05:04:44 PM PDT 24
Peak memory 211364 kb
Host smart-c6664ac1-c2f0-44df-bc89-2bbcd3822968
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3195233583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3195233583
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3271200014
Short name T128
Test name
Test status
Simulation time 1377732428 ps
CPU time 20.14 seconds
Started Jul 04 05:04:09 PM PDT 24
Finished Jul 04 05:04:29 PM PDT 24
Peak memory 216380 kb
Host smart-abe51f2e-1a92-4ab2-bfe5-aea762c49d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271200014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3271200014
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1679417265
Short name T338
Test name
Test status
Simulation time 14546474436 ps
CPU time 151.84 seconds
Started Jul 04 05:04:12 PM PDT 24
Finished Jul 04 05:06:44 PM PDT 24
Peak memory 227496 kb
Host smart-2e0d1911-fae0-4f4a-a9f1-f94d93489dad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679417265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1679417265
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3229189458
Short name T173
Test name
Test status
Simulation time 1349218315 ps
CPU time 16.9 seconds
Started Jul 04 05:04:23 PM PDT 24
Finished Jul 04 05:04:40 PM PDT 24
Peak memory 217228 kb
Host smart-23d30766-4ed0-459b-9ca2-dd64ff3516e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229189458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3229189458
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3938131427
Short name T344
Test name
Test status
Simulation time 52894957943 ps
CPU time 481.32 seconds
Started Jul 04 05:04:23 PM PDT 24
Finished Jul 04 05:12:24 PM PDT 24
Peak memory 217792 kb
Host smart-15ae69b9-7774-4f33-a361-ed0dc4f91e34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938131427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3938131427
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.910925992
Short name T50
Test name
Test status
Simulation time 3766067677 ps
CPU time 42.9 seconds
Started Jul 04 05:04:24 PM PDT 24
Finished Jul 04 05:05:07 PM PDT 24
Peak memory 219232 kb
Host smart-e1cc050d-2cb1-40b8-90b8-9d0aa43bb59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910925992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.910925992
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3365505306
Short name T259
Test name
Test status
Simulation time 437867686 ps
CPU time 10.62 seconds
Started Jul 04 05:04:16 PM PDT 24
Finished Jul 04 05:04:27 PM PDT 24
Peak memory 219152 kb
Host smart-6da8e26b-73a7-413c-b534-da5fef175fa2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3365505306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3365505306
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1735401120
Short name T187
Test name
Test status
Simulation time 1341141123 ps
CPU time 23.43 seconds
Started Jul 04 05:04:15 PM PDT 24
Finished Jul 04 05:04:39 PM PDT 24
Peak memory 215644 kb
Host smart-b1e75616-dad4-4a13-a5a4-7d39c37d7ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735401120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1735401120
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2825445215
Short name T210
Test name
Test status
Simulation time 47696106564 ps
CPU time 126.19 seconds
Started Jul 04 05:04:16 PM PDT 24
Finished Jul 04 05:06:23 PM PDT 24
Peak memory 219276 kb
Host smart-94d37121-c398-4f81-a8b2-182c7ca6a9d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825445215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2825445215
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.3800092072
Short name T53
Test name
Test status
Simulation time 91540659793 ps
CPU time 7507.89 seconds
Started Jul 04 05:04:24 PM PDT 24
Finished Jul 04 07:09:33 PM PDT 24
Peak memory 233824 kb
Host smart-4ff7dd69-378f-4b12-a2cb-92e8a6b5e952
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800092072 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.3800092072
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3869759979
Short name T219
Test name
Test status
Simulation time 10181539252 ps
CPU time 23.89 seconds
Started Jul 04 05:04:32 PM PDT 24
Finished Jul 04 05:04:56 PM PDT 24
Peak memory 217376 kb
Host smart-2fc5c406-c5d0-4ebe-9096-c6ef150473a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869759979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3869759979
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3678449795
Short name T174
Test name
Test status
Simulation time 170909707849 ps
CPU time 469.82 seconds
Started Jul 04 05:04:22 PM PDT 24
Finished Jul 04 05:12:12 PM PDT 24
Peak memory 216952 kb
Host smart-72ee997c-3f15-4cca-9fb4-5d21c9dba0a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678449795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3678449795
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1648228907
Short name T161
Test name
Test status
Simulation time 21598436588 ps
CPU time 51.92 seconds
Started Jul 04 05:04:23 PM PDT 24
Finished Jul 04 05:05:15 PM PDT 24
Peak memory 218816 kb
Host smart-eb26dd81-3bb8-4d1b-b54c-2a1af5fa2658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648228907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1648228907
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2453368572
Short name T100
Test name
Test status
Simulation time 13798504309 ps
CPU time 29.43 seconds
Started Jul 04 05:04:24 PM PDT 24
Finished Jul 04 05:04:54 PM PDT 24
Peak memory 211840 kb
Host smart-300d79c6-d7bc-4f4d-bb68-6f46e8b15e06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2453368572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2453368572
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.454092200
Short name T32
Test name
Test status
Simulation time 65544055436 ps
CPU time 75.01 seconds
Started Jul 04 05:04:23 PM PDT 24
Finished Jul 04 05:05:38 PM PDT 24
Peak memory 215928 kb
Host smart-28037284-34c2-4457-89ab-898ba5bd2c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454092200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.454092200
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1886162435
Short name T77
Test name
Test status
Simulation time 7073682386 ps
CPU time 49.63 seconds
Started Jul 04 05:04:23 PM PDT 24
Finished Jul 04 05:05:13 PM PDT 24
Peak memory 219828 kb
Host smart-4c5b379a-57db-4c04-aba8-2173710960e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886162435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1886162435
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3187842069
Short name T176
Test name
Test status
Simulation time 661583834 ps
CPU time 12.84 seconds
Started Jul 04 05:04:38 PM PDT 24
Finished Jul 04 05:04:51 PM PDT 24
Peak memory 216968 kb
Host smart-8611d8e9-3128-4326-b8da-7e7444bdc7c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187842069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3187842069
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2286602989
Short name T16
Test name
Test status
Simulation time 58529942103 ps
CPU time 675.76 seconds
Started Jul 04 05:04:37 PM PDT 24
Finished Jul 04 05:15:53 PM PDT 24
Peak memory 216700 kb
Host smart-dc6b6642-c6a8-4c3c-a331-82516fb18d1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286602989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2286602989
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3528229382
Short name T24
Test name
Test status
Simulation time 7720433927 ps
CPU time 65.15 seconds
Started Jul 04 05:04:37 PM PDT 24
Finished Jul 04 05:05:42 PM PDT 24
Peak memory 219332 kb
Host smart-10cc23d7-ad2b-49b8-9efb-eddcba2d4826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528229382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3528229382
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.136211579
Short name T279
Test name
Test status
Simulation time 3769404053 ps
CPU time 31.32 seconds
Started Jul 04 05:04:36 PM PDT 24
Finished Jul 04 05:05:08 PM PDT 24
Peak memory 211340 kb
Host smart-5b65b345-2d62-46ce-89a9-5b088fe89807
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=136211579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.136211579
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.326318607
Short name T303
Test name
Test status
Simulation time 4964155532 ps
CPU time 56.9 seconds
Started Jul 04 05:04:30 PM PDT 24
Finished Jul 04 05:05:27 PM PDT 24
Peak memory 216868 kb
Host smart-9757a77f-7b46-4326-afb1-50251772c28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326318607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.326318607
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3626802078
Short name T139
Test name
Test status
Simulation time 4063509270 ps
CPU time 52.5 seconds
Started Jul 04 05:04:29 PM PDT 24
Finished Jul 04 05:05:22 PM PDT 24
Peak memory 217536 kb
Host smart-1ac2a64e-592e-4db7-927a-e704f8b49e74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626802078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3626802078
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.4209495276
Short name T253
Test name
Test status
Simulation time 662016001 ps
CPU time 8.46 seconds
Started Jul 04 05:04:46 PM PDT 24
Finished Jul 04 05:04:55 PM PDT 24
Peak memory 213140 kb
Host smart-dcdff038-ea51-476f-9a76-0b78df52009f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209495276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.4209495276
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1856135805
Short name T36
Test name
Test status
Simulation time 133828518479 ps
CPU time 841.03 seconds
Started Jul 04 05:04:38 PM PDT 24
Finished Jul 04 05:18:39 PM PDT 24
Peak memory 236064 kb
Host smart-090fc99c-9d83-4ee7-a314-2703c8c0ac03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856135805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1856135805
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1598921458
Short name T156
Test name
Test status
Simulation time 42944938285 ps
CPU time 55.06 seconds
Started Jul 04 05:04:44 PM PDT 24
Finished Jul 04 05:05:39 PM PDT 24
Peak memory 219228 kb
Host smart-ff48bcbd-5df3-4178-a16e-cbe5480be36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598921458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1598921458
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.959541584
Short name T127
Test name
Test status
Simulation time 2725768669 ps
CPU time 26.45 seconds
Started Jul 04 05:04:36 PM PDT 24
Finished Jul 04 05:05:03 PM PDT 24
Peak memory 217604 kb
Host smart-0cf8335d-32e2-4bf7-9fb2-ae1244c84023
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=959541584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.959541584
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3921307329
Short name T132
Test name
Test status
Simulation time 6743646445 ps
CPU time 66.36 seconds
Started Jul 04 05:04:38 PM PDT 24
Finished Jul 04 05:05:45 PM PDT 24
Peak memory 216576 kb
Host smart-a7243e3e-fc34-4571-b72f-5436d2efa078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921307329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3921307329
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2516236207
Short name T137
Test name
Test status
Simulation time 5240871317 ps
CPU time 24.69 seconds
Started Jul 04 05:04:38 PM PDT 24
Finished Jul 04 05:05:03 PM PDT 24
Peak memory 211984 kb
Host smart-ee4c930c-4176-48e3-8192-ed84fa89a5fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516236207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2516236207
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2919701035
Short name T175
Test name
Test status
Simulation time 661387677 ps
CPU time 8.11 seconds
Started Jul 04 05:04:43 PM PDT 24
Finished Jul 04 05:04:51 PM PDT 24
Peak memory 217100 kb
Host smart-e0d7a837-019c-43b9-836e-e7a0a9b9466a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919701035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2919701035
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2708210934
Short name T204
Test name
Test status
Simulation time 25753312142 ps
CPU time 330.2 seconds
Started Jul 04 05:04:43 PM PDT 24
Finished Jul 04 05:10:14 PM PDT 24
Peak memory 233968 kb
Host smart-e4d550e7-f08b-42eb-8fdd-25bf2d70f71f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708210934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2708210934
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2794346114
Short name T305
Test name
Test status
Simulation time 1644696213 ps
CPU time 29.99 seconds
Started Jul 04 05:04:42 PM PDT 24
Finished Jul 04 05:05:13 PM PDT 24
Peak memory 219200 kb
Host smart-4737d13c-b8f4-4a60-b4e4-25341b3b0ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794346114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2794346114
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1241130381
Short name T125
Test name
Test status
Simulation time 2190843456 ps
CPU time 17.41 seconds
Started Jul 04 05:04:44 PM PDT 24
Finished Jul 04 05:05:02 PM PDT 24
Peak memory 219264 kb
Host smart-03a824fc-7e81-4902-b13c-ec9f67bac929
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1241130381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1241130381
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3209480483
Short name T10
Test name
Test status
Simulation time 355134765 ps
CPU time 19.4 seconds
Started Jul 04 05:04:43 PM PDT 24
Finished Jul 04 05:05:03 PM PDT 24
Peak memory 216056 kb
Host smart-ae22da90-4a90-4495-98de-20331e26ed3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209480483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3209480483
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.4001386051
Short name T140
Test name
Test status
Simulation time 5720556488 ps
CPU time 25.06 seconds
Started Jul 04 05:03:39 PM PDT 24
Finished Jul 04 05:04:05 PM PDT 24
Peak memory 217380 kb
Host smart-2c64e46f-4dde-4a10-9dc6-84311c07b9a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001386051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.4001386051
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.262716908
Short name T340
Test name
Test status
Simulation time 39332592003 ps
CPU time 215.97 seconds
Started Jul 04 05:03:40 PM PDT 24
Finished Jul 04 05:07:16 PM PDT 24
Peak memory 229660 kb
Host smart-4ef4f70c-517b-4a72-9108-a7bf955699b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262716908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.262716908
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3282020406
Short name T350
Test name
Test status
Simulation time 34837576429 ps
CPU time 70.3 seconds
Started Jul 04 05:03:40 PM PDT 24
Finished Jul 04 05:04:50 PM PDT 24
Peak memory 219296 kb
Host smart-475cbcb4-902c-477c-a07c-b283dbee90b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282020406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3282020406
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.814850362
Short name T131
Test name
Test status
Simulation time 1164913452 ps
CPU time 14.5 seconds
Started Jul 04 05:03:41 PM PDT 24
Finished Jul 04 05:03:56 PM PDT 24
Peak memory 219032 kb
Host smart-58832617-fa3a-48a6-bc3e-003318142969
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=814850362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.814850362
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1790336485
Short name T26
Test name
Test status
Simulation time 18202923565 ps
CPU time 249.16 seconds
Started Jul 04 05:03:40 PM PDT 24
Finished Jul 04 05:07:50 PM PDT 24
Peak memory 238280 kb
Host smart-ee35289c-7995-4d79-80e5-0561ce0be6f2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790336485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1790336485
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1324980575
Short name T190
Test name
Test status
Simulation time 4163109336 ps
CPU time 27.05 seconds
Started Jul 04 05:03:40 PM PDT 24
Finished Jul 04 05:04:07 PM PDT 24
Peak memory 216936 kb
Host smart-f90f9817-a83d-4d3b-849e-5bec8073e3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324980575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1324980575
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2132163239
Short name T218
Test name
Test status
Simulation time 10499021017 ps
CPU time 91.62 seconds
Started Jul 04 05:03:40 PM PDT 24
Finished Jul 04 05:05:12 PM PDT 24
Peak memory 219236 kb
Host smart-ed6a824f-ef71-48e1-afcf-e975d5d9c65c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132163239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2132163239
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2250737300
Short name T342
Test name
Test status
Simulation time 1606123054 ps
CPU time 18.52 seconds
Started Jul 04 05:04:52 PM PDT 24
Finished Jul 04 05:05:10 PM PDT 24
Peak memory 217052 kb
Host smart-4d07d30a-58e5-4486-b2d5-96ce524ecbe4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250737300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2250737300
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1141627715
Short name T348
Test name
Test status
Simulation time 165840904957 ps
CPU time 548.43 seconds
Started Jul 04 05:04:44 PM PDT 24
Finished Jul 04 05:13:53 PM PDT 24
Peak memory 237852 kb
Host smart-f7401560-e871-4f43-9935-016ed39f72aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141627715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1141627715
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.747743113
Short name T27
Test name
Test status
Simulation time 675283550 ps
CPU time 19.56 seconds
Started Jul 04 05:04:44 PM PDT 24
Finished Jul 04 05:05:04 PM PDT 24
Peak memory 219256 kb
Host smart-ba3c4a72-81a4-428a-a980-fc574a77f50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747743113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.747743113
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1623955597
Short name T249
Test name
Test status
Simulation time 12519822683 ps
CPU time 29.26 seconds
Started Jul 04 05:04:44 PM PDT 24
Finished Jul 04 05:05:14 PM PDT 24
Peak memory 211652 kb
Host smart-807d8aef-f91f-4edc-a5e2-4049e2015d98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1623955597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1623955597
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1528303951
Short name T211
Test name
Test status
Simulation time 21701355473 ps
CPU time 58.23 seconds
Started Jul 04 05:04:46 PM PDT 24
Finished Jul 04 05:05:44 PM PDT 24
Peak memory 216940 kb
Host smart-361c87c5-d64c-41a8-af61-6feea3c354c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528303951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1528303951
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.493744654
Short name T123
Test name
Test status
Simulation time 1088550949 ps
CPU time 40.06 seconds
Started Jul 04 05:04:46 PM PDT 24
Finished Jul 04 05:05:26 PM PDT 24
Peak memory 219244 kb
Host smart-3ee45d81-9953-4207-b83c-6a8214217418
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493744654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.493744654
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3448095455
Short name T356
Test name
Test status
Simulation time 4087603116 ps
CPU time 15.19 seconds
Started Jul 04 05:04:52 PM PDT 24
Finished Jul 04 05:05:07 PM PDT 24
Peak memory 217112 kb
Host smart-adae40d8-fb80-48f3-b461-6862541fa519
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448095455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3448095455
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3817536586
Short name T230
Test name
Test status
Simulation time 73198499821 ps
CPU time 379.65 seconds
Started Jul 04 05:04:51 PM PDT 24
Finished Jul 04 05:11:11 PM PDT 24
Peak memory 234428 kb
Host smart-79684d4f-73bc-4cec-bc2d-b59ad0489d42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817536586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3817536586
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.227149790
Short name T288
Test name
Test status
Simulation time 5684087398 ps
CPU time 54.38 seconds
Started Jul 04 05:04:54 PM PDT 24
Finished Jul 04 05:05:49 PM PDT 24
Peak memory 219296 kb
Host smart-8a632d20-3041-4019-8c67-d41ff13466c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227149790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.227149790
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3522002404
Short name T248
Test name
Test status
Simulation time 2504611123 ps
CPU time 23.2 seconds
Started Jul 04 05:04:54 PM PDT 24
Finished Jul 04 05:05:17 PM PDT 24
Peak memory 219348 kb
Host smart-e5cd95fc-4332-4861-a120-382070f41d0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3522002404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3522002404
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2571163247
Short name T293
Test name
Test status
Simulation time 6472924517 ps
CPU time 56.17 seconds
Started Jul 04 05:04:49 PM PDT 24
Finished Jul 04 05:05:46 PM PDT 24
Peak memory 216500 kb
Host smart-9d2fd46e-8eab-4037-bd28-966f60c6a318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571163247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2571163247
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.342004714
Short name T285
Test name
Test status
Simulation time 55883534837 ps
CPU time 144.65 seconds
Started Jul 04 05:04:50 PM PDT 24
Finished Jul 04 05:07:15 PM PDT 24
Peak memory 219836 kb
Host smart-2de4f6d9-3b52-4f1e-9686-728e36d4093d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342004714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.342004714
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2627398845
Short name T3
Test name
Test status
Simulation time 11600143194 ps
CPU time 24.26 seconds
Started Jul 04 05:04:52 PM PDT 24
Finished Jul 04 05:05:16 PM PDT 24
Peak memory 217508 kb
Host smart-fa203ba1-9c40-4309-8b85-119f697f1ced
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627398845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2627398845
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.297112618
Short name T34
Test name
Test status
Simulation time 187117958542 ps
CPU time 376.04 seconds
Started Jul 04 05:04:51 PM PDT 24
Finished Jul 04 05:11:07 PM PDT 24
Peak memory 228584 kb
Host smart-d2ed1784-aa4b-4f8a-9575-a255ebb728da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297112618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.297112618
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2317765711
Short name T149
Test name
Test status
Simulation time 6680655495 ps
CPU time 41.24 seconds
Started Jul 04 05:04:50 PM PDT 24
Finished Jul 04 05:05:31 PM PDT 24
Peak memory 219232 kb
Host smart-32664731-7a40-4ca9-9950-ca4908f7a97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317765711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2317765711
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1158846952
Short name T334
Test name
Test status
Simulation time 2251972893 ps
CPU time 16.91 seconds
Started Jul 04 05:04:51 PM PDT 24
Finished Jul 04 05:05:09 PM PDT 24
Peak memory 219316 kb
Host smart-bca076c1-666c-4946-8530-a5eb02346871
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1158846952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1158846952
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1624690619
Short name T12
Test name
Test status
Simulation time 15217789580 ps
CPU time 49.66 seconds
Started Jul 04 05:04:52 PM PDT 24
Finished Jul 04 05:05:43 PM PDT 24
Peak memory 216632 kb
Host smart-503c692d-dbfd-4cb3-aa10-6cb90705e752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624690619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1624690619
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.613156332
Short name T44
Test name
Test status
Simulation time 53558942023 ps
CPU time 121.23 seconds
Started Jul 04 05:04:51 PM PDT 24
Finished Jul 04 05:06:53 PM PDT 24
Peak memory 219400 kb
Host smart-d0e613a5-6aa8-4cdb-ba85-38529e09ffd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613156332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.613156332
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3933826413
Short name T67
Test name
Test status
Simulation time 174386056 ps
CPU time 8.53 seconds
Started Jul 04 05:04:58 PM PDT 24
Finished Jul 04 05:05:07 PM PDT 24
Peak memory 216984 kb
Host smart-3da4f71d-f2f3-4753-9134-e0f9947d12e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933826413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3933826413
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.411735433
Short name T220
Test name
Test status
Simulation time 106222103906 ps
CPU time 406.72 seconds
Started Jul 04 05:04:58 PM PDT 24
Finished Jul 04 05:11:45 PM PDT 24
Peak memory 236596 kb
Host smart-de270731-595e-406e-95c9-e30318c574e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411735433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.411735433
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.672556432
Short name T193
Test name
Test status
Simulation time 7346923794 ps
CPU time 58.21 seconds
Started Jul 04 05:04:58 PM PDT 24
Finished Jul 04 05:05:56 PM PDT 24
Peak memory 219296 kb
Host smart-c4c73aa1-00fe-4cc0-a18f-dd80aee9b54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672556432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.672556432
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2174708429
Short name T224
Test name
Test status
Simulation time 10184930809 ps
CPU time 25.19 seconds
Started Jul 04 05:04:59 PM PDT 24
Finished Jul 04 05:05:24 PM PDT 24
Peak memory 217704 kb
Host smart-6aec85c9-9df7-497a-88fa-240f6d8b512a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2174708429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2174708429
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3448402677
Short name T352
Test name
Test status
Simulation time 7893858069 ps
CPU time 84.14 seconds
Started Jul 04 05:04:50 PM PDT 24
Finished Jul 04 05:06:15 PM PDT 24
Peak memory 216624 kb
Host smart-b4503946-cc91-4e6e-94f0-a9ae409b3e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448402677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3448402677
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2437727512
Short name T207
Test name
Test status
Simulation time 80703017741 ps
CPU time 156.93 seconds
Started Jul 04 05:04:58 PM PDT 24
Finished Jul 04 05:07:35 PM PDT 24
Peak memory 220700 kb
Host smart-eecdefd3-9a5f-43f4-88fb-10872759083b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437727512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2437727512
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2574178788
Short name T55
Test name
Test status
Simulation time 37501185344 ps
CPU time 9048.04 seconds
Started Jul 04 05:04:59 PM PDT 24
Finished Jul 04 07:35:48 PM PDT 24
Peak memory 237288 kb
Host smart-eefecb75-1f69-44ed-a8aa-3dfe3786f414
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574178788 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.2574178788
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1013081984
Short name T328
Test name
Test status
Simulation time 1877851693 ps
CPU time 19.13 seconds
Started Jul 04 05:04:59 PM PDT 24
Finished Jul 04 05:05:18 PM PDT 24
Peak memory 217016 kb
Host smart-86e0c828-fd9e-4978-942e-73f5dc4a9d4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013081984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1013081984
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1520265899
Short name T216
Test name
Test status
Simulation time 385169687425 ps
CPU time 954.49 seconds
Started Jul 04 05:04:58 PM PDT 24
Finished Jul 04 05:20:53 PM PDT 24
Peak memory 224588 kb
Host smart-43c78f99-e931-4059-be26-7976b7153699
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520265899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1520265899
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1727878993
Short name T186
Test name
Test status
Simulation time 5082431328 ps
CPU time 49.72 seconds
Started Jul 04 05:04:59 PM PDT 24
Finished Jul 04 05:05:49 PM PDT 24
Peak memory 219172 kb
Host smart-c3f44afc-98a3-4805-9575-dd473fcdc433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727878993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1727878993
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2994003416
Short name T151
Test name
Test status
Simulation time 4415213734 ps
CPU time 33.67 seconds
Started Jul 04 05:04:58 PM PDT 24
Finished Jul 04 05:05:32 PM PDT 24
Peak memory 219344 kb
Host smart-2ed3ca22-5e29-40b5-816c-b9043393d182
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2994003416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2994003416
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1272856592
Short name T282
Test name
Test status
Simulation time 8370826871 ps
CPU time 65.83 seconds
Started Jul 04 05:05:01 PM PDT 24
Finished Jul 04 05:06:07 PM PDT 24
Peak memory 216904 kb
Host smart-faa9d9f7-e289-4991-b85f-4f742e7879fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272856592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1272856592
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3382734529
Short name T294
Test name
Test status
Simulation time 11324425690 ps
CPU time 87.18 seconds
Started Jul 04 05:04:58 PM PDT 24
Finished Jul 04 05:06:25 PM PDT 24
Peak memory 219300 kb
Host smart-5f6a1208-d06c-4cd4-a7fa-ff59dcc82637
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382734529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3382734529
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2378664210
Short name T270
Test name
Test status
Simulation time 26961422517 ps
CPU time 28.36 seconds
Started Jul 04 05:05:05 PM PDT 24
Finished Jul 04 05:05:34 PM PDT 24
Peak memory 217428 kb
Host smart-89447bc5-790a-4f63-8e40-951529dcd364
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378664210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2378664210
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2958580182
Short name T172
Test name
Test status
Simulation time 401227524090 ps
CPU time 934.63 seconds
Started Jul 04 05:05:04 PM PDT 24
Finished Jul 04 05:20:39 PM PDT 24
Peak memory 234908 kb
Host smart-60fa394b-d246-4dc0-9a3c-02851f1a34d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958580182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2958580182
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3568192472
Short name T183
Test name
Test status
Simulation time 2730678229 ps
CPU time 35.96 seconds
Started Jul 04 05:05:07 PM PDT 24
Finished Jul 04 05:05:43 PM PDT 24
Peak memory 219236 kb
Host smart-15a5a92b-cc3b-4fcb-99e5-3d7002577859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568192472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3568192472
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2357484216
Short name T196
Test name
Test status
Simulation time 15891791242 ps
CPU time 22.72 seconds
Started Jul 04 05:04:59 PM PDT 24
Finished Jul 04 05:05:22 PM PDT 24
Peak memory 211892 kb
Host smart-003318a6-23ca-4ea6-abee-3ea1fe93dfa3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2357484216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2357484216
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1392820534
Short name T150
Test name
Test status
Simulation time 18515737438 ps
CPU time 55.22 seconds
Started Jul 04 05:04:58 PM PDT 24
Finished Jul 04 05:05:53 PM PDT 24
Peak memory 217220 kb
Host smart-d900c301-bb14-4056-b21a-9f0eb75fbb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392820534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1392820534
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.283243273
Short name T98
Test name
Test status
Simulation time 35202800594 ps
CPU time 119.86 seconds
Started Jul 04 05:04:58 PM PDT 24
Finished Jul 04 05:06:59 PM PDT 24
Peak memory 222084 kb
Host smart-a2febaf6-ed67-4d60-b61c-648a1321b1c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283243273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.283243273
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.4286751405
Short name T257
Test name
Test status
Simulation time 176193025 ps
CPU time 8.3 seconds
Started Jul 04 05:05:04 PM PDT 24
Finished Jul 04 05:05:12 PM PDT 24
Peak memory 216544 kb
Host smart-13342142-6935-40cf-9437-0e6c11d2f74c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286751405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.4286751405
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2961121096
Short name T266
Test name
Test status
Simulation time 351303302863 ps
CPU time 748.44 seconds
Started Jul 04 05:05:06 PM PDT 24
Finished Jul 04 05:17:35 PM PDT 24
Peak memory 235144 kb
Host smart-c65219b3-e8b6-4086-bbc7-7c6bb49d545a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961121096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2961121096
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.4024250235
Short name T181
Test name
Test status
Simulation time 6592139400 ps
CPU time 23.66 seconds
Started Jul 04 05:05:07 PM PDT 24
Finished Jul 04 05:05:31 PM PDT 24
Peak memory 215716 kb
Host smart-58b32f55-f7cd-4259-bc68-5428661cd3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024250235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.4024250235
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.4005743094
Short name T226
Test name
Test status
Simulation time 8222223289 ps
CPU time 33.62 seconds
Started Jul 04 05:05:03 PM PDT 24
Finished Jul 04 05:05:37 PM PDT 24
Peak memory 219264 kb
Host smart-15f259a2-2fdb-4784-977e-34b5c4719540
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4005743094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.4005743094
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1460063086
Short name T225
Test name
Test status
Simulation time 32123385997 ps
CPU time 73.39 seconds
Started Jul 04 05:05:06 PM PDT 24
Finished Jul 04 05:06:19 PM PDT 24
Peak memory 216072 kb
Host smart-248591d1-a812-451f-8018-17716cd8d026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460063086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1460063086
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.27941592
Short name T268
Test name
Test status
Simulation time 8255918411 ps
CPU time 98.6 seconds
Started Jul 04 05:05:03 PM PDT 24
Finished Jul 04 05:06:42 PM PDT 24
Peak memory 219540 kb
Host smart-7d145536-e2db-4ac3-a0de-893372f859e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27941592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 36.rom_ctrl_stress_all.27941592
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3709759240
Short name T237
Test name
Test status
Simulation time 169238235 ps
CPU time 8.35 seconds
Started Jul 04 05:05:05 PM PDT 24
Finished Jul 04 05:05:14 PM PDT 24
Peak memory 217948 kb
Host smart-11b7d63d-5da1-4d12-a501-418b1455cd2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709759240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3709759240
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3445526175
Short name T15
Test name
Test status
Simulation time 158696437617 ps
CPU time 325.72 seconds
Started Jul 04 05:05:04 PM PDT 24
Finished Jul 04 05:10:30 PM PDT 24
Peak memory 226720 kb
Host smart-96c24cd8-859f-4ee8-b9ff-b41eb082e139
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445526175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3445526175
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3591541546
Short name T341
Test name
Test status
Simulation time 18741706193 ps
CPU time 51.54 seconds
Started Jul 04 05:05:03 PM PDT 24
Finished Jul 04 05:05:55 PM PDT 24
Peak memory 219072 kb
Host smart-3118e35d-1a48-4923-94dc-dcef8936dd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591541546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3591541546
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.4146127432
Short name T267
Test name
Test status
Simulation time 2442135145 ps
CPU time 14.56 seconds
Started Jul 04 05:05:07 PM PDT 24
Finished Jul 04 05:05:22 PM PDT 24
Peak memory 217608 kb
Host smart-983281dc-f4d1-4b6d-b116-97e6a0828ba4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4146127432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.4146127432
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.420795695
Short name T272
Test name
Test status
Simulation time 1535940092 ps
CPU time 19.91 seconds
Started Jul 04 05:05:07 PM PDT 24
Finished Jul 04 05:05:27 PM PDT 24
Peak memory 215796 kb
Host smart-f27392ad-0f4d-4a6b-9c58-38cd31e9567b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420795695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.420795695
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2341283519
Short name T316
Test name
Test status
Simulation time 7752091546 ps
CPU time 47.84 seconds
Started Jul 04 05:05:04 PM PDT 24
Finished Jul 04 05:05:52 PM PDT 24
Peak memory 219288 kb
Host smart-a8a7cb26-e18e-4b3c-9a0b-c8804a70f911
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341283519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2341283519
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2762606539
Short name T209
Test name
Test status
Simulation time 3855476780 ps
CPU time 31.14 seconds
Started Jul 04 05:05:10 PM PDT 24
Finished Jul 04 05:05:42 PM PDT 24
Peak memory 217260 kb
Host smart-f0a1daa0-8c4f-4d84-b50b-4f02fa3315fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762606539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2762606539
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3851153943
Short name T163
Test name
Test status
Simulation time 49601137864 ps
CPU time 475.74 seconds
Started Jul 04 05:05:10 PM PDT 24
Finished Jul 04 05:13:05 PM PDT 24
Peak memory 226856 kb
Host smart-2ff91fbd-4ffc-40bd-9a9b-768c9d8f599d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851153943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3851153943
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.4089382416
Short name T320
Test name
Test status
Simulation time 11571577487 ps
CPU time 52.32 seconds
Started Jul 04 05:05:10 PM PDT 24
Finished Jul 04 05:06:03 PM PDT 24
Peak memory 219304 kb
Host smart-2d6b82ce-47d8-4cec-b4d6-4a646fb2bc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089382416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.4089382416
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.4186955400
Short name T169
Test name
Test status
Simulation time 8198255591 ps
CPU time 22.65 seconds
Started Jul 04 05:05:07 PM PDT 24
Finished Jul 04 05:05:30 PM PDT 24
Peak memory 211900 kb
Host smart-ad996e4d-d89c-4866-b195-a52b7eacb00f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4186955400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.4186955400
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3142982862
Short name T118
Test name
Test status
Simulation time 7906865291 ps
CPU time 64.14 seconds
Started Jul 04 05:05:07 PM PDT 24
Finished Jul 04 05:06:11 PM PDT 24
Peak memory 216848 kb
Host smart-787779a4-23b4-4647-94b4-87ea28044ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142982862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3142982862
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2596097949
Short name T160
Test name
Test status
Simulation time 2099680821 ps
CPU time 10.58 seconds
Started Jul 04 05:05:05 PM PDT 24
Finished Jul 04 05:05:16 PM PDT 24
Peak memory 214564 kb
Host smart-5f49c1ec-1eaa-437b-9b4d-4c7dcb100fe2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596097949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2596097949
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2932317873
Short name T192
Test name
Test status
Simulation time 10277860001 ps
CPU time 24.21 seconds
Started Jul 04 05:05:10 PM PDT 24
Finished Jul 04 05:05:35 PM PDT 24
Peak memory 217544 kb
Host smart-e60d1682-50f5-4304-8321-40b16e1d1229
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932317873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2932317873
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1681626251
Short name T300
Test name
Test status
Simulation time 120216210489 ps
CPU time 309.99 seconds
Started Jul 04 05:05:10 PM PDT 24
Finished Jul 04 05:10:21 PM PDT 24
Peak memory 224592 kb
Host smart-4531c6b0-c6fc-49c4-bd6a-5a2d8adf8e4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681626251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1681626251
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1303977455
Short name T309
Test name
Test status
Simulation time 14364137324 ps
CPU time 40.61 seconds
Started Jul 04 05:05:11 PM PDT 24
Finished Jul 04 05:05:52 PM PDT 24
Peak memory 219248 kb
Host smart-65d279e4-b98b-45c1-9732-fd58168b02b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303977455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1303977455
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1546541297
Short name T202
Test name
Test status
Simulation time 736029088 ps
CPU time 10.46 seconds
Started Jul 04 05:05:10 PM PDT 24
Finished Jul 04 05:05:22 PM PDT 24
Peak memory 219184 kb
Host smart-71b171a5-4b5e-4679-ae7d-18e75ec4ea28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1546541297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1546541297
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.700334058
Short name T307
Test name
Test status
Simulation time 15396108781 ps
CPU time 73.22 seconds
Started Jul 04 05:05:13 PM PDT 24
Finished Jul 04 05:06:26 PM PDT 24
Peak memory 216968 kb
Host smart-419235c2-e89e-4c8d-9493-9c43a302e959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700334058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.700334058
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2663652036
Short name T170
Test name
Test status
Simulation time 35952254014 ps
CPU time 123.68 seconds
Started Jul 04 05:05:11 PM PDT 24
Finished Jul 04 05:07:15 PM PDT 24
Peak memory 219304 kb
Host smart-566c73f1-a965-42a7-8f31-643e40f52eab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663652036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2663652036
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1500577311
Short name T65
Test name
Test status
Simulation time 25235115651 ps
CPU time 26.32 seconds
Started Jul 04 05:03:42 PM PDT 24
Finished Jul 04 05:04:08 PM PDT 24
Peak memory 217352 kb
Host smart-4e76c126-1eac-4dcb-9bb7-2418b7cfee53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500577311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1500577311
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2701605573
Short name T331
Test name
Test status
Simulation time 205509902912 ps
CPU time 802.25 seconds
Started Jul 04 05:03:39 PM PDT 24
Finished Jul 04 05:17:02 PM PDT 24
Peak memory 217812 kb
Host smart-f4bdc45e-8036-4c3f-a17f-7adc4e3c5b8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701605573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2701605573
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2504378175
Short name T308
Test name
Test status
Simulation time 10736192882 ps
CPU time 52.05 seconds
Started Jul 04 05:03:39 PM PDT 24
Finished Jul 04 05:04:32 PM PDT 24
Peak memory 219296 kb
Host smart-c961d210-f6a7-4bf5-a602-b2046f09d625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504378175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2504378175
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3018212156
Short name T99
Test name
Test status
Simulation time 4108722651 ps
CPU time 34.45 seconds
Started Jul 04 05:03:40 PM PDT 24
Finished Jul 04 05:04:15 PM PDT 24
Peak memory 219248 kb
Host smart-31d960da-e402-499f-8fa7-810eee2c82f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3018212156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3018212156
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2655125194
Short name T306
Test name
Test status
Simulation time 63485652082 ps
CPU time 61.02 seconds
Started Jul 04 05:03:41 PM PDT 24
Finished Jul 04 05:04:43 PM PDT 24
Peak memory 216472 kb
Host smart-9547a428-018a-4764-87b8-068ec7c1a801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655125194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2655125194
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.4145070159
Short name T13
Test name
Test status
Simulation time 2520879620 ps
CPU time 31.96 seconds
Started Jul 04 05:03:39 PM PDT 24
Finished Jul 04 05:04:11 PM PDT 24
Peak memory 219372 kb
Host smart-18016521-f2bb-4dde-82ec-b7e996e3ef19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145070159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.4145070159
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3555297318
Short name T212
Test name
Test status
Simulation time 1355699741 ps
CPU time 14.81 seconds
Started Jul 04 05:05:17 PM PDT 24
Finished Jul 04 05:05:32 PM PDT 24
Peak memory 217004 kb
Host smart-0d196412-4a3d-42c2-9fc7-c0ab379c25e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555297318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3555297318
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2810842702
Short name T353
Test name
Test status
Simulation time 12101776053 ps
CPU time 262.83 seconds
Started Jul 04 05:05:18 PM PDT 24
Finished Jul 04 05:09:41 PM PDT 24
Peak memory 241984 kb
Host smart-39b24ad6-6743-412b-90c0-683118889693
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810842702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2810842702
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2238948248
Short name T269
Test name
Test status
Simulation time 720263146 ps
CPU time 18.82 seconds
Started Jul 04 05:05:17 PM PDT 24
Finished Jul 04 05:05:36 PM PDT 24
Peak memory 219180 kb
Host smart-189e2843-28ba-4e3e-989b-3f885ad1b0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238948248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2238948248
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.4015066601
Short name T335
Test name
Test status
Simulation time 1912137977 ps
CPU time 19.62 seconds
Started Jul 04 05:05:22 PM PDT 24
Finished Jul 04 05:05:42 PM PDT 24
Peak memory 211272 kb
Host smart-d2b28214-83cf-4c52-99b4-429ec8660f57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4015066601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.4015066601
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3894835816
Short name T284
Test name
Test status
Simulation time 19173090010 ps
CPU time 48.03 seconds
Started Jul 04 05:05:11 PM PDT 24
Finished Jul 04 05:06:00 PM PDT 24
Peak memory 216512 kb
Host smart-d7ce5341-57e9-4980-a5b6-5c823154903e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894835816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3894835816
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1286744618
Short name T120
Test name
Test status
Simulation time 4786410418 ps
CPU time 63.19 seconds
Started Jul 04 05:05:17 PM PDT 24
Finished Jul 04 05:06:20 PM PDT 24
Peak memory 220256 kb
Host smart-e12e728f-e255-4d7f-934c-c1bfa8f82082
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286744618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1286744618
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3313457684
Short name T145
Test name
Test status
Simulation time 1868826919 ps
CPU time 20.36 seconds
Started Jul 04 05:05:25 PM PDT 24
Finished Jul 04 05:05:46 PM PDT 24
Peak memory 217148 kb
Host smart-89daf3b0-eed7-45b3-bfb8-2908b19e8baa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313457684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3313457684
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3276735006
Short name T171
Test name
Test status
Simulation time 211997061750 ps
CPU time 573.05 seconds
Started Jul 04 05:05:24 PM PDT 24
Finished Jul 04 05:14:58 PM PDT 24
Peak memory 242860 kb
Host smart-7fd17b3b-ecdb-4984-8111-7331b409a26a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276735006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3276735006
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.267521437
Short name T46
Test name
Test status
Simulation time 689675113 ps
CPU time 19.15 seconds
Started Jul 04 05:05:25 PM PDT 24
Finished Jul 04 05:05:44 PM PDT 24
Peak memory 219284 kb
Host smart-30e368e3-3ac0-4f65-802f-3b9fa98e87b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267521437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.267521437
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3564328943
Short name T245
Test name
Test status
Simulation time 4412984370 ps
CPU time 34.08 seconds
Started Jul 04 05:05:17 PM PDT 24
Finished Jul 04 05:05:51 PM PDT 24
Peak memory 211620 kb
Host smart-41a40aed-70d1-433b-a16e-ea70d4ab1ee3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3564328943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3564328943
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3055895230
Short name T130
Test name
Test status
Simulation time 2527655694 ps
CPU time 39.41 seconds
Started Jul 04 05:05:17 PM PDT 24
Finished Jul 04 05:05:57 PM PDT 24
Peak memory 218072 kb
Host smart-94cc92f8-18d5-4644-96fe-d8cad80ff117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055895230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3055895230
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2640349935
Short name T43
Test name
Test status
Simulation time 1197923368 ps
CPU time 32.41 seconds
Started Jul 04 05:05:17 PM PDT 24
Finished Jul 04 05:05:50 PM PDT 24
Peak memory 219184 kb
Host smart-b392d38a-1c65-424c-81c2-f559146978f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640349935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2640349935
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2688943302
Short name T261
Test name
Test status
Simulation time 3678881368 ps
CPU time 29.71 seconds
Started Jul 04 05:05:24 PM PDT 24
Finished Jul 04 05:05:53 PM PDT 24
Peak memory 217220 kb
Host smart-63a565f8-ee07-4a8c-9d3c-fcc836216089
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688943302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2688943302
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.385961058
Short name T179
Test name
Test status
Simulation time 347535166187 ps
CPU time 862.36 seconds
Started Jul 04 05:05:25 PM PDT 24
Finished Jul 04 05:19:48 PM PDT 24
Peak memory 238936 kb
Host smart-d73df3e9-9529-4202-8601-c1b9af15ee27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385961058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.385961058
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.966804485
Short name T264
Test name
Test status
Simulation time 346331341 ps
CPU time 19.47 seconds
Started Jul 04 05:05:25 PM PDT 24
Finished Jul 04 05:05:45 PM PDT 24
Peak memory 219296 kb
Host smart-fb6a77e6-9d4f-49ae-b579-c2ec8057338d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966804485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.966804485
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3464599950
Short name T178
Test name
Test status
Simulation time 2912211167 ps
CPU time 26.66 seconds
Started Jul 04 05:05:25 PM PDT 24
Finished Jul 04 05:05:52 PM PDT 24
Peak memory 211228 kb
Host smart-bcdd063d-7759-4e37-9cba-284b9cbe9476
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3464599950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3464599950
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1263067427
Short name T291
Test name
Test status
Simulation time 18360415702 ps
CPU time 50.72 seconds
Started Jul 04 05:05:24 PM PDT 24
Finished Jul 04 05:06:15 PM PDT 24
Peak memory 217152 kb
Host smart-174577b5-4743-417b-a3f9-ff287eefa2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263067427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1263067427
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3795246301
Short name T242
Test name
Test status
Simulation time 6177142655 ps
CPU time 62.15 seconds
Started Jul 04 05:05:25 PM PDT 24
Finished Jul 04 05:06:28 PM PDT 24
Peak memory 219368 kb
Host smart-fc0d9998-9611-49ff-a44b-33338013dff1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795246301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3795246301
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2304286715
Short name T198
Test name
Test status
Simulation time 9961308278 ps
CPU time 22.89 seconds
Started Jul 04 05:05:31 PM PDT 24
Finished Jul 04 05:05:55 PM PDT 24
Peak memory 217448 kb
Host smart-e34a3f0a-6f3a-4e04-87e7-e41141b6f376
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304286715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2304286715
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2290971230
Short name T185
Test name
Test status
Simulation time 3007466394 ps
CPU time 214.32 seconds
Started Jul 04 05:05:34 PM PDT 24
Finished Jul 04 05:09:09 PM PDT 24
Peak memory 239468 kb
Host smart-0f861c72-5e2e-4881-acd0-003e55fb477d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290971230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2290971230
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1473375070
Short name T301
Test name
Test status
Simulation time 4284030506 ps
CPU time 43.92 seconds
Started Jul 04 05:05:34 PM PDT 24
Finished Jul 04 05:06:18 PM PDT 24
Peak memory 219304 kb
Host smart-83e530f9-f0bb-4983-ad6f-f02430728803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473375070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1473375070
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.335883693
Short name T290
Test name
Test status
Simulation time 3676730371 ps
CPU time 16.66 seconds
Started Jul 04 05:05:25 PM PDT 24
Finished Jul 04 05:05:42 PM PDT 24
Peak memory 218844 kb
Host smart-4d4448d0-170b-47e3-b1a8-5e568fbe9c06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=335883693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.335883693
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2516831250
Short name T238
Test name
Test status
Simulation time 54299203168 ps
CPU time 66.39 seconds
Started Jul 04 05:05:26 PM PDT 24
Finished Jul 04 05:06:32 PM PDT 24
Peak memory 216092 kb
Host smart-8a0f2b0f-8f84-40d0-8002-ae27c32b2eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516831250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2516831250
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2277327053
Short name T165
Test name
Test status
Simulation time 3145723720 ps
CPU time 19.2 seconds
Started Jul 04 05:05:24 PM PDT 24
Finished Jul 04 05:05:44 PM PDT 24
Peak memory 219160 kb
Host smart-55c725f0-3545-4d99-a5ad-d9506aab6842
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277327053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2277327053
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.798537936
Short name T20
Test name
Test status
Simulation time 771151703 ps
CPU time 13.49 seconds
Started Jul 04 05:05:33 PM PDT 24
Finished Jul 04 05:05:47 PM PDT 24
Peak memory 216984 kb
Host smart-c2ae583d-c94a-4115-a1e8-bc6dece2dbec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798537936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.798537936
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.33509911
Short name T114
Test name
Test status
Simulation time 165229149737 ps
CPU time 691.07 seconds
Started Jul 04 05:05:31 PM PDT 24
Finished Jul 04 05:17:02 PM PDT 24
Peak memory 234856 kb
Host smart-9d72b84a-aeb7-4890-9349-a001586a7ff3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33509911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_co
rrupt_sig_fatal_chk.33509911
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.4247990087
Short name T229
Test name
Test status
Simulation time 689105118 ps
CPU time 19.36 seconds
Started Jul 04 05:05:35 PM PDT 24
Finished Jul 04 05:05:55 PM PDT 24
Peak memory 219184 kb
Host smart-d04b628a-745e-4b7d-a284-36315024037c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247990087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.4247990087
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2051751772
Short name T313
Test name
Test status
Simulation time 2730899401 ps
CPU time 27.03 seconds
Started Jul 04 05:05:32 PM PDT 24
Finished Jul 04 05:05:59 PM PDT 24
Peak memory 219304 kb
Host smart-146b95bd-eebe-4b0e-92a6-c205955c7edb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2051751772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2051751772
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2451799014
Short name T14
Test name
Test status
Simulation time 7722985911 ps
CPU time 72.8 seconds
Started Jul 04 05:05:32 PM PDT 24
Finished Jul 04 05:06:45 PM PDT 24
Peak memory 216828 kb
Host smart-fbc404b3-22d8-424f-9ba9-a17862fcdacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451799014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2451799014
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2150878554
Short name T136
Test name
Test status
Simulation time 2004069624 ps
CPU time 25.32 seconds
Started Jul 04 05:05:31 PM PDT 24
Finished Jul 04 05:05:57 PM PDT 24
Peak memory 219324 kb
Host smart-8c3e09ae-28f6-490e-81ce-bac3e2bb400f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150878554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2150878554
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.954045222
Short name T56
Test name
Test status
Simulation time 99053952034 ps
CPU time 3840.46 seconds
Started Jul 04 05:05:31 PM PDT 24
Finished Jul 04 06:09:33 PM PDT 24
Peak memory 252088 kb
Host smart-e3a7e73d-83bf-4768-95df-040fb400c22e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954045222 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.954045222
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3386688711
Short name T275
Test name
Test status
Simulation time 12119773552 ps
CPU time 26.32 seconds
Started Jul 04 05:05:38 PM PDT 24
Finished Jul 04 05:06:04 PM PDT 24
Peak memory 217100 kb
Host smart-ed8ee4e9-96a8-4300-87ae-54fe488d857d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386688711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3386688711
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1923556643
Short name T239
Test name
Test status
Simulation time 284815613016 ps
CPU time 641.88 seconds
Started Jul 04 05:05:40 PM PDT 24
Finished Jul 04 05:16:23 PM PDT 24
Peak memory 229496 kb
Host smart-e59d7ece-9049-4f6b-aaed-27723a56512f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923556643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1923556643
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2487050508
Short name T49
Test name
Test status
Simulation time 14060612314 ps
CPU time 58.44 seconds
Started Jul 04 05:05:41 PM PDT 24
Finished Jul 04 05:06:40 PM PDT 24
Peak memory 219068 kb
Host smart-c8240601-65f0-4db3-9f09-13e3e5afeb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487050508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2487050508
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2957246597
Short name T142
Test name
Test status
Simulation time 8385180403 ps
CPU time 33.01 seconds
Started Jul 04 05:05:41 PM PDT 24
Finished Jul 04 05:06:14 PM PDT 24
Peak memory 219348 kb
Host smart-d96dfd52-af08-4030-a8ff-b08320c93fe7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2957246597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2957246597
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.3296851019
Short name T295
Test name
Test status
Simulation time 704138827 ps
CPU time 20.28 seconds
Started Jul 04 05:05:41 PM PDT 24
Finished Jul 04 05:06:02 PM PDT 24
Peak memory 215980 kb
Host smart-ba90fc6b-0c66-4b6a-85c0-02f5acb8f04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296851019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.3296851019
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.4039456547
Short name T205
Test name
Test status
Simulation time 16643486581 ps
CPU time 157.42 seconds
Started Jul 04 05:05:36 PM PDT 24
Finished Jul 04 05:08:14 PM PDT 24
Peak memory 220600 kb
Host smart-d3d81800-7f7c-4864-862c-333502532f7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039456547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.4039456547
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1155354751
Short name T280
Test name
Test status
Simulation time 9842349179 ps
CPU time 24.17 seconds
Started Jul 04 05:05:49 PM PDT 24
Finished Jul 04 05:06:14 PM PDT 24
Peak memory 217376 kb
Host smart-41fad625-3145-4ef8-af2e-5c1b4c8ce8c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155354751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1155354751
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1965684339
Short name T37
Test name
Test status
Simulation time 54860560541 ps
CPU time 271.63 seconds
Started Jul 04 05:05:41 PM PDT 24
Finished Jul 04 05:10:13 PM PDT 24
Peak memory 228152 kb
Host smart-e3cf3f40-d995-4120-bdde-a07897ec0b47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965684339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1965684339
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.223694133
Short name T254
Test name
Test status
Simulation time 32170489662 ps
CPU time 66.41 seconds
Started Jul 04 05:05:40 PM PDT 24
Finished Jul 04 05:06:47 PM PDT 24
Peak memory 219220 kb
Host smart-59b88a22-decc-481c-9198-5d34a1f42c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223694133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.223694133
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1104908519
Short name T116
Test name
Test status
Simulation time 1120079221 ps
CPU time 16.32 seconds
Started Jul 04 05:05:40 PM PDT 24
Finished Jul 04 05:05:56 PM PDT 24
Peak memory 219164 kb
Host smart-1b6714b7-6ab8-4dda-bc87-81d2ed060ff4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1104908519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1104908519
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.169347167
Short name T195
Test name
Test status
Simulation time 361072196 ps
CPU time 20.02 seconds
Started Jul 04 05:05:40 PM PDT 24
Finished Jul 04 05:06:01 PM PDT 24
Peak memory 216560 kb
Host smart-d8ea5247-40e4-437b-b1be-c8d0895445e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169347167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.169347167
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3934337050
Short name T240
Test name
Test status
Simulation time 43637312891 ps
CPU time 174.4 seconds
Started Jul 04 05:05:42 PM PDT 24
Finished Jul 04 05:08:37 PM PDT 24
Peak memory 227504 kb
Host smart-5eceb473-746d-4b5c-9e77-8ae91ba128a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934337050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3934337050
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2332225817
Short name T299
Test name
Test status
Simulation time 3497979194 ps
CPU time 18.71 seconds
Started Jul 04 05:05:47 PM PDT 24
Finished Jul 04 05:06:06 PM PDT 24
Peak memory 216888 kb
Host smart-de698a09-3424-423e-bac2-eb0f239228bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332225817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2332225817
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2372042613
Short name T188
Test name
Test status
Simulation time 163602454125 ps
CPU time 466.6 seconds
Started Jul 04 05:05:50 PM PDT 24
Finished Jul 04 05:13:37 PM PDT 24
Peak memory 238356 kb
Host smart-de08c776-ff69-4040-8681-2e54d7ab8d65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372042613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2372042613
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1672042820
Short name T155
Test name
Test status
Simulation time 39594182096 ps
CPU time 55.29 seconds
Started Jul 04 05:05:50 PM PDT 24
Finished Jul 04 05:06:45 PM PDT 24
Peak memory 219256 kb
Host smart-081586fd-9242-4fba-87fb-89ae239ada2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672042820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1672042820
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3885436878
Short name T141
Test name
Test status
Simulation time 3490334899 ps
CPU time 20.58 seconds
Started Jul 04 05:05:47 PM PDT 24
Finished Jul 04 05:06:08 PM PDT 24
Peak memory 219328 kb
Host smart-7267d315-95b2-4e24-b361-5a600ba45888
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3885436878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3885436878
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1069332036
Short name T7
Test name
Test status
Simulation time 26627283204 ps
CPU time 70.36 seconds
Started Jul 04 05:05:51 PM PDT 24
Finished Jul 04 05:07:02 PM PDT 24
Peak memory 217076 kb
Host smart-3dbdb360-f1d7-4c87-be99-c56b3a26b759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069332036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1069332036
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3971653891
Short name T182
Test name
Test status
Simulation time 16044611708 ps
CPU time 193.32 seconds
Started Jul 04 05:05:48 PM PDT 24
Finished Jul 04 05:09:02 PM PDT 24
Peak memory 220976 kb
Host smart-d4062b9a-1c34-4b9a-bf88-55d398b0980f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971653891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3971653891
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1647543776
Short name T227
Test name
Test status
Simulation time 167366998 ps
CPU time 8.35 seconds
Started Jul 04 05:05:56 PM PDT 24
Finished Jul 04 05:06:05 PM PDT 24
Peak memory 216976 kb
Host smart-4764853c-3073-4e44-9a74-09836be8d271
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647543776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1647543776
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3785943971
Short name T330
Test name
Test status
Simulation time 50634513739 ps
CPU time 303.61 seconds
Started Jul 04 05:05:52 PM PDT 24
Finished Jul 04 05:10:56 PM PDT 24
Peak memory 235024 kb
Host smart-741aeb53-d29c-421d-a1f7-4d46cd276318
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785943971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3785943971
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1951449389
Short name T297
Test name
Test status
Simulation time 19970187775 ps
CPU time 47.67 seconds
Started Jul 04 05:05:52 PM PDT 24
Finished Jul 04 05:06:40 PM PDT 24
Peak memory 215220 kb
Host smart-56c88f03-51bb-4319-bde4-bd083836a486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951449389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1951449389
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3773919003
Short name T126
Test name
Test status
Simulation time 1806117860 ps
CPU time 21.28 seconds
Started Jul 04 05:05:47 PM PDT 24
Finished Jul 04 05:06:08 PM PDT 24
Peak memory 211408 kb
Host smart-6d9635c9-d888-4ca0-be2f-f3de760df61f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3773919003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3773919003
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3433504722
Short name T1
Test name
Test status
Simulation time 14759511216 ps
CPU time 29.34 seconds
Started Jul 04 05:05:47 PM PDT 24
Finished Jul 04 05:06:16 PM PDT 24
Peak memory 216580 kb
Host smart-2f6f7f02-53c1-46e8-95c8-a1c5029e734c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433504722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3433504722
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1000176782
Short name T343
Test name
Test status
Simulation time 3970084515 ps
CPU time 46.78 seconds
Started Jul 04 05:05:45 PM PDT 24
Finished Jul 04 05:06:32 PM PDT 24
Peak memory 219364 kb
Host smart-a282390e-6500-423d-b408-f13fd255b9bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000176782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1000176782
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1300175810
Short name T357
Test name
Test status
Simulation time 689055659 ps
CPU time 8.19 seconds
Started Jul 04 05:05:52 PM PDT 24
Finished Jul 04 05:06:00 PM PDT 24
Peak memory 217088 kb
Host smart-73db61da-ebb7-4362-8cf3-e6b04f41b008
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300175810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1300175810
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1723008988
Short name T318
Test name
Test status
Simulation time 645682892047 ps
CPU time 781.46 seconds
Started Jul 04 05:05:53 PM PDT 24
Finished Jul 04 05:18:54 PM PDT 24
Peak memory 225324 kb
Host smart-0c7af1b3-705f-407f-949c-7ac7ac03007d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723008988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1723008988
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1771174165
Short name T332
Test name
Test status
Simulation time 17064128633 ps
CPU time 46.58 seconds
Started Jul 04 05:05:53 PM PDT 24
Finished Jul 04 05:06:40 PM PDT 24
Peak memory 219244 kb
Host smart-4b410d5f-7602-4c18-bee4-877a52f991b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771174165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1771174165
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3806464770
Short name T347
Test name
Test status
Simulation time 1052965175 ps
CPU time 15.41 seconds
Started Jul 04 05:05:56 PM PDT 24
Finished Jul 04 05:06:12 PM PDT 24
Peak memory 219184 kb
Host smart-f09ea5ef-d8f4-4c79-8f3f-9b5dc68b7999
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3806464770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3806464770
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.4129999956
Short name T289
Test name
Test status
Simulation time 706017923 ps
CPU time 19.81 seconds
Started Jul 04 05:05:53 PM PDT 24
Finished Jul 04 05:06:13 PM PDT 24
Peak memory 216820 kb
Host smart-63956f5c-09ed-4db1-a38b-378d6ee7a807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129999956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.4129999956
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2285264457
Short name T311
Test name
Test status
Simulation time 17163222754 ps
CPU time 143.37 seconds
Started Jul 04 05:05:52 PM PDT 24
Finished Jul 04 05:08:15 PM PDT 24
Peak memory 219456 kb
Host smart-bcf583e6-0608-4668-8d4d-0823c740b294
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285264457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2285264457
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2313366576
Short name T157
Test name
Test status
Simulation time 3694941279 ps
CPU time 31.55 seconds
Started Jul 04 05:03:38 PM PDT 24
Finished Jul 04 05:04:10 PM PDT 24
Peak memory 217204 kb
Host smart-846cae7b-fc7c-48d7-9e0b-3a5283a9917c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313366576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2313366576
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.4037382421
Short name T115
Test name
Test status
Simulation time 56907426282 ps
CPU time 324.22 seconds
Started Jul 04 05:03:37 PM PDT 24
Finished Jul 04 05:09:02 PM PDT 24
Peak memory 224556 kb
Host smart-e0b0c0ba-3cfb-4e99-8c6e-895859afd037
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037382421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.4037382421
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1877253253
Short name T256
Test name
Test status
Simulation time 6757811624 ps
CPU time 54.29 seconds
Started Jul 04 05:03:41 PM PDT 24
Finished Jul 04 05:04:35 PM PDT 24
Peak memory 219340 kb
Host smart-2538ecda-0318-435f-998f-4630e9e43d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877253253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1877253253
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1013703239
Short name T349
Test name
Test status
Simulation time 11766265054 ps
CPU time 28.44 seconds
Started Jul 04 05:03:39 PM PDT 24
Finished Jul 04 05:04:07 PM PDT 24
Peak memory 211876 kb
Host smart-931839e8-756e-4a20-9d6d-67ff5b1e6e10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1013703239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1013703239
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1996759175
Short name T233
Test name
Test status
Simulation time 15098220380 ps
CPU time 40.41 seconds
Started Jul 04 05:03:37 PM PDT 24
Finished Jul 04 05:04:18 PM PDT 24
Peak memory 216296 kb
Host smart-ab7d3274-1976-4244-a219-bfbe72c5aeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996759175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1996759175
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1914577523
Short name T329
Test name
Test status
Simulation time 7061991125 ps
CPU time 66.55 seconds
Started Jul 04 05:03:39 PM PDT 24
Finished Jul 04 05:04:46 PM PDT 24
Peak memory 219344 kb
Host smart-2daa30d0-46db-4d55-802b-faa5eba24c21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914577523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1914577523
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.477938090
Short name T64
Test name
Test status
Simulation time 16445113889 ps
CPU time 16.62 seconds
Started Jul 04 05:03:39 PM PDT 24
Finished Jul 04 05:03:56 PM PDT 24
Peak memory 212620 kb
Host smart-8e68b332-d809-446d-82e2-a56f32bcae92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477938090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.477938090
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3862298732
Short name T251
Test name
Test status
Simulation time 1678475908 ps
CPU time 145.96 seconds
Started Jul 04 05:03:39 PM PDT 24
Finished Jul 04 05:06:06 PM PDT 24
Peak memory 243152 kb
Host smart-d80e3fc4-dde4-4439-b32c-7f80eddb7aeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862298732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3862298732
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1196327995
Short name T287
Test name
Test status
Simulation time 4921055082 ps
CPU time 35.39 seconds
Started Jul 04 05:03:40 PM PDT 24
Finished Jul 04 05:04:16 PM PDT 24
Peak memory 219228 kb
Host smart-492e84b2-0b71-448c-967d-d1a647e898c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196327995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1196327995
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1178532984
Short name T241
Test name
Test status
Simulation time 640053308 ps
CPU time 10.56 seconds
Started Jul 04 05:03:42 PM PDT 24
Finished Jul 04 05:03:53 PM PDT 24
Peak memory 219220 kb
Host smart-4884c9a4-e14c-49c8-8551-614a1fa57396
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1178532984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1178532984
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.880342389
Short name T246
Test name
Test status
Simulation time 3558252860 ps
CPU time 42.1 seconds
Started Jul 04 05:03:40 PM PDT 24
Finished Jul 04 05:04:22 PM PDT 24
Peak memory 215680 kb
Host smart-4864780b-280e-4f9d-b5fa-0287711229fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880342389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.880342389
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2520443046
Short name T119
Test name
Test status
Simulation time 18661009277 ps
CPU time 60.75 seconds
Started Jul 04 05:03:42 PM PDT 24
Finished Jul 04 05:04:43 PM PDT 24
Peak memory 219352 kb
Host smart-32c244ac-afb9-47fc-a71e-30abf41d8675
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520443046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2520443046
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.4199762548
Short name T339
Test name
Test status
Simulation time 25138512569 ps
CPU time 27.21 seconds
Started Jul 04 05:03:47 PM PDT 24
Finished Jul 04 05:04:15 PM PDT 24
Peak memory 213252 kb
Host smart-b466ea23-a006-4af8-8c43-ec90cb5e027c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199762548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.4199762548
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2585961310
Short name T222
Test name
Test status
Simulation time 141100344262 ps
CPU time 724.63 seconds
Started Jul 04 05:03:38 PM PDT 24
Finished Jul 04 05:15:43 PM PDT 24
Peak memory 236928 kb
Host smart-da95bcb4-b76e-4009-ae58-78c23a2efa1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585961310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2585961310
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3479954719
Short name T31
Test name
Test status
Simulation time 8136598432 ps
CPU time 64.97 seconds
Started Jul 04 05:03:39 PM PDT 24
Finished Jul 04 05:04:44 PM PDT 24
Peak memory 219352 kb
Host smart-b2ec9c52-863c-4df1-bff4-a5a2a710abc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479954719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3479954719
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2661024150
Short name T217
Test name
Test status
Simulation time 13811098501 ps
CPU time 30.04 seconds
Started Jul 04 05:03:37 PM PDT 24
Finished Jul 04 05:04:08 PM PDT 24
Peak memory 217660 kb
Host smart-8c73ecf9-0e77-4a2f-9375-193731fc0ae8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2661024150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2661024150
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2295930187
Short name T263
Test name
Test status
Simulation time 9876660625 ps
CPU time 35.88 seconds
Started Jul 04 05:03:37 PM PDT 24
Finished Jul 04 05:04:13 PM PDT 24
Peak memory 216796 kb
Host smart-b168854e-3848-4efb-9c73-f1ba3a821c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295930187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2295930187
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.70246177
Short name T28
Test name
Test status
Simulation time 2986495740 ps
CPU time 44.8 seconds
Started Jul 04 05:03:39 PM PDT 24
Finished Jul 04 05:04:24 PM PDT 24
Peak memory 219252 kb
Host smart-591c6900-43c0-489f-8ac0-547e54dcd7cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70246177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 7.rom_ctrl_stress_all.70246177
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.4066226887
Short name T6
Test name
Test status
Simulation time 1065126981 ps
CPU time 15.33 seconds
Started Jul 04 05:03:47 PM PDT 24
Finished Jul 04 05:04:03 PM PDT 24
Peak memory 217160 kb
Host smart-da3efe8a-e652-42f7-864b-79e42632f870
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066226887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.4066226887
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.360602444
Short name T38
Test name
Test status
Simulation time 458617131405 ps
CPU time 712.62 seconds
Started Jul 04 05:03:46 PM PDT 24
Finished Jul 04 05:15:40 PM PDT 24
Peak memory 234184 kb
Host smart-02074068-8a45-4534-8415-beacb8ebb1f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360602444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.360602444
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1537373766
Short name T180
Test name
Test status
Simulation time 1375278701 ps
CPU time 19.61 seconds
Started Jul 04 05:03:47 PM PDT 24
Finished Jul 04 05:04:07 PM PDT 24
Peak memory 219176 kb
Host smart-e6704f3e-7f6e-466e-af02-9ce45db6a959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537373766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1537373766
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.630471216
Short name T133
Test name
Test status
Simulation time 755851728 ps
CPU time 10.25 seconds
Started Jul 04 05:03:46 PM PDT 24
Finished Jul 04 05:03:57 PM PDT 24
Peak memory 219208 kb
Host smart-dc756727-5758-4022-aeb5-891ac9d12f49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=630471216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.630471216
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1067278416
Short name T336
Test name
Test status
Simulation time 7131971132 ps
CPU time 57.94 seconds
Started Jul 04 05:03:49 PM PDT 24
Finished Jul 04 05:04:48 PM PDT 24
Peak memory 217416 kb
Host smart-1af7ec4d-320f-42f2-bcff-add64399815f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067278416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1067278416
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2767870967
Short name T235
Test name
Test status
Simulation time 9099793122 ps
CPU time 32.88 seconds
Started Jul 04 05:03:49 PM PDT 24
Finished Jul 04 05:04:22 PM PDT 24
Peak memory 219156 kb
Host smart-2c0dff62-47b3-4ebc-9b50-2e64e78e5423
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767870967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2767870967
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.719042258
Short name T327
Test name
Test status
Simulation time 1610923640 ps
CPU time 13.45 seconds
Started Jul 04 05:03:47 PM PDT 24
Finished Jul 04 05:04:01 PM PDT 24
Peak memory 216980 kb
Host smart-d3e8629c-8960-4385-aba4-305bc2828314
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719042258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.719042258
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.306793725
Short name T333
Test name
Test status
Simulation time 68313086563 ps
CPU time 687.12 seconds
Started Jul 04 05:03:50 PM PDT 24
Finished Jul 04 05:15:17 PM PDT 24
Peak memory 234560 kb
Host smart-db08276b-90c5-4e14-8bef-301623c977ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306793725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.306793725
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.323407514
Short name T325
Test name
Test status
Simulation time 346232766 ps
CPU time 19.32 seconds
Started Jul 04 05:03:48 PM PDT 24
Finished Jul 04 05:04:08 PM PDT 24
Peak memory 219284 kb
Host smart-7dd10ec9-2724-4f59-9148-e9450d96c984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323407514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.323407514
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2293606920
Short name T304
Test name
Test status
Simulation time 15751172025 ps
CPU time 22.16 seconds
Started Jul 04 05:03:46 PM PDT 24
Finished Jul 04 05:04:09 PM PDT 24
Peak memory 219344 kb
Host smart-43356f07-01c1-4756-b7cf-79aeeb35dc49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2293606920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2293606920
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1487888896
Short name T215
Test name
Test status
Simulation time 2709146701 ps
CPU time 30.4 seconds
Started Jul 04 05:03:49 PM PDT 24
Finished Jul 04 05:04:20 PM PDT 24
Peak memory 215900 kb
Host smart-e5d18486-219f-4a5e-b9da-2ea4d9c63048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487888896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1487888896
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2385465957
Short name T117
Test name
Test status
Simulation time 9784474551 ps
CPU time 101.43 seconds
Started Jul 04 05:03:46 PM PDT 24
Finished Jul 04 05:05:28 PM PDT 24
Peak memory 219576 kb
Host smart-5fc03703-c455-4ab6-8d99-2b5f57687e31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385465957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2385465957
Directory /workspace/9.rom_ctrl_stress_all/latest
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