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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.22 96.89 91.85 97.68 100.00 98.28 97.45 98.37


Total test records in report: 459
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T307 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3707952179 Jul 05 04:29:53 PM PDT 24 Jul 05 04:30:14 PM PDT 24 5268382111 ps
T308 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.53607306 Jul 05 04:29:55 PM PDT 24 Jul 05 04:31:00 PM PDT 24 32710355649 ps
T309 /workspace/coverage/default/23.rom_ctrl_stress_all.1304395577 Jul 05 04:30:01 PM PDT 24 Jul 05 04:31:45 PM PDT 24 20870699383 ps
T310 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.980829772 Jul 05 04:29:23 PM PDT 24 Jul 05 04:36:39 PM PDT 24 29574849196 ps
T311 /workspace/coverage/default/48.rom_ctrl_stress_all.435441927 Jul 05 04:30:13 PM PDT 24 Jul 05 04:30:49 PM PDT 24 7370308027 ps
T312 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.837310850 Jul 05 04:29:46 PM PDT 24 Jul 05 04:30:02 PM PDT 24 345382281 ps
T313 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2208321172 Jul 05 04:29:39 PM PDT 24 Jul 05 04:39:23 PM PDT 24 640438248688 ps
T314 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.4111690386 Jul 05 04:29:21 PM PDT 24 Jul 05 04:38:39 PM PDT 24 104438003097 ps
T315 /workspace/coverage/default/23.rom_ctrl_alert_test.3103941482 Jul 05 04:29:50 PM PDT 24 Jul 05 04:30:08 PM PDT 24 1302602623 ps
T316 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2490068740 Jul 05 04:30:07 PM PDT 24 Jul 05 04:33:34 PM PDT 24 15976077526 ps
T317 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3876292637 Jul 05 04:30:17 PM PDT 24 Jul 05 04:31:28 PM PDT 24 43818639345 ps
T318 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2385605882 Jul 05 04:30:25 PM PDT 24 Jul 05 04:34:51 PM PDT 24 33673385039 ps
T46 /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.3215081755 Jul 05 04:30:23 PM PDT 24 Jul 05 05:29:34 PM PDT 24 180075191849 ps
T319 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1514986595 Jul 05 04:29:55 PM PDT 24 Jul 05 04:31:05 PM PDT 24 117113522353 ps
T320 /workspace/coverage/default/31.rom_ctrl_stress_all.2143401870 Jul 05 04:29:55 PM PDT 24 Jul 05 04:31:37 PM PDT 24 71355262668 ps
T321 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2409980859 Jul 05 04:29:35 PM PDT 24 Jul 05 04:29:59 PM PDT 24 332438571 ps
T322 /workspace/coverage/default/45.rom_ctrl_stress_all.1867872177 Jul 05 04:30:26 PM PDT 24 Jul 05 04:31:07 PM PDT 24 2382337639 ps
T323 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.4121697412 Jul 05 04:29:51 PM PDT 24 Jul 05 04:30:20 PM PDT 24 6867708351 ps
T324 /workspace/coverage/default/17.rom_ctrl_alert_test.4026317799 Jul 05 04:29:34 PM PDT 24 Jul 05 04:30:06 PM PDT 24 42748157989 ps
T325 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.911436559 Jul 05 04:30:01 PM PDT 24 Jul 05 04:31:02 PM PDT 24 28073590022 ps
T326 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3852559658 Jul 05 04:29:55 PM PDT 24 Jul 05 04:30:25 PM PDT 24 36080614481 ps
T327 /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.2077064693 Jul 05 04:29:34 PM PDT 24 Jul 05 06:31:26 PM PDT 24 25235157680 ps
T328 /workspace/coverage/default/10.rom_ctrl_stress_all.3689155492 Jul 05 04:29:48 PM PDT 24 Jul 05 04:30:24 PM PDT 24 2170904202 ps
T329 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1217705633 Jul 05 04:29:41 PM PDT 24 Jul 05 04:30:12 PM PDT 24 1164629440 ps
T330 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1663291564 Jul 05 04:30:17 PM PDT 24 Jul 05 04:30:43 PM PDT 24 4859099155 ps
T331 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.922132829 Jul 05 04:30:05 PM PDT 24 Jul 05 04:30:42 PM PDT 24 17183842086 ps
T332 /workspace/coverage/default/41.rom_ctrl_smoke.921420459 Jul 05 04:30:10 PM PDT 24 Jul 05 04:30:32 PM PDT 24 1417538615 ps
T333 /workspace/coverage/default/44.rom_ctrl_alert_test.818893621 Jul 05 04:30:15 PM PDT 24 Jul 05 04:30:35 PM PDT 24 1388156313 ps
T334 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1457278201 Jul 05 04:29:28 PM PDT 24 Jul 05 04:29:46 PM PDT 24 966782241 ps
T335 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.4137974543 Jul 05 04:29:28 PM PDT 24 Jul 05 04:30:09 PM PDT 24 9370567096 ps
T336 /workspace/coverage/default/17.rom_ctrl_stress_all.1514815721 Jul 05 04:29:49 PM PDT 24 Jul 05 04:31:20 PM PDT 24 9505368431 ps
T337 /workspace/coverage/default/24.rom_ctrl_stress_all.1943248464 Jul 05 04:29:51 PM PDT 24 Jul 05 04:32:19 PM PDT 24 16382072956 ps
T338 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2532068467 Jul 05 04:30:36 PM PDT 24 Jul 05 04:31:14 PM PDT 24 28007736817 ps
T339 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1530669283 Jul 05 04:30:13 PM PDT 24 Jul 05 04:31:14 PM PDT 24 9283402158 ps
T340 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3484149148 Jul 05 04:29:59 PM PDT 24 Jul 05 04:30:15 PM PDT 24 698960002 ps
T341 /workspace/coverage/default/11.rom_ctrl_alert_test.3255154276 Jul 05 04:30:02 PM PDT 24 Jul 05 04:30:30 PM PDT 24 16231651587 ps
T342 /workspace/coverage/default/20.rom_ctrl_alert_test.441513858 Jul 05 04:30:01 PM PDT 24 Jul 05 04:30:37 PM PDT 24 8007740892 ps
T343 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.433614407 Jul 05 04:29:42 PM PDT 24 Jul 05 04:30:16 PM PDT 24 13165646511 ps
T344 /workspace/coverage/default/41.rom_ctrl_stress_all.2041186405 Jul 05 04:30:15 PM PDT 24 Jul 05 04:31:27 PM PDT 24 14491307668 ps
T345 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.323586202 Jul 05 04:29:54 PM PDT 24 Jul 05 04:40:19 PM PDT 24 855601857922 ps
T346 /workspace/coverage/default/15.rom_ctrl_stress_all.4102816174 Jul 05 04:29:43 PM PDT 24 Jul 05 04:30:15 PM PDT 24 5102111763 ps
T347 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1248297922 Jul 05 04:30:08 PM PDT 24 Jul 05 04:31:04 PM PDT 24 6003311128 ps
T348 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2077892174 Jul 05 04:30:08 PM PDT 24 Jul 05 04:30:22 PM PDT 24 727561527 ps
T349 /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.2912635727 Jul 05 04:29:59 PM PDT 24 Jul 05 06:40:48 PM PDT 24 314131702823 ps
T350 /workspace/coverage/default/2.rom_ctrl_stress_all.4131923038 Jul 05 04:29:24 PM PDT 24 Jul 05 04:30:09 PM PDT 24 17658297452 ps
T351 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.344218795 Jul 05 04:29:43 PM PDT 24 Jul 05 04:30:15 PM PDT 24 3468166471 ps
T352 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1121751260 Jul 05 04:29:46 PM PDT 24 Jul 05 04:30:01 PM PDT 24 955395562 ps
T353 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.487355689 Jul 05 04:30:22 PM PDT 24 Jul 05 04:30:45 PM PDT 24 1319827701 ps
T86 /workspace/coverage/default/44.rom_ctrl_stress_all.2296822086 Jul 05 04:30:51 PM PDT 24 Jul 05 04:32:36 PM PDT 24 48947911961 ps
T87 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1817278665 Jul 05 04:29:49 PM PDT 24 Jul 05 04:30:18 PM PDT 24 5393006882 ps
T88 /workspace/coverage/default/34.rom_ctrl_smoke.3581685257 Jul 05 04:30:01 PM PDT 24 Jul 05 04:31:15 PM PDT 24 9851130295 ps
T89 /workspace/coverage/default/16.rom_ctrl_stress_all.2288969814 Jul 05 04:29:41 PM PDT 24 Jul 05 04:30:40 PM PDT 24 3491793639 ps
T90 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.190934352 Jul 05 04:29:33 PM PDT 24 Jul 05 04:30:47 PM PDT 24 8467918049 ps
T91 /workspace/coverage/default/32.rom_ctrl_smoke.2137909570 Jul 05 04:29:54 PM PDT 24 Jul 05 04:30:15 PM PDT 24 683894862 ps
T92 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3334353890 Jul 05 04:30:16 PM PDT 24 Jul 05 04:34:48 PM PDT 24 4140869991 ps
T93 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3238641428 Jul 05 04:29:41 PM PDT 24 Jul 05 04:33:04 PM PDT 24 3109090509 ps
T94 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2340636449 Jul 05 04:29:45 PM PDT 24 Jul 05 04:30:38 PM PDT 24 5692582365 ps
T95 /workspace/coverage/default/42.rom_ctrl_stress_all.4138228141 Jul 05 04:30:25 PM PDT 24 Jul 05 04:32:36 PM PDT 24 27771818522 ps
T354 /workspace/coverage/default/21.rom_ctrl_alert_test.2855752229 Jul 05 04:29:43 PM PDT 24 Jul 05 04:30:06 PM PDT 24 3525181203 ps
T355 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.4131072091 Jul 05 04:29:52 PM PDT 24 Jul 05 04:30:07 PM PDT 24 1361675586 ps
T108 /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.1459600295 Jul 05 04:30:06 PM PDT 24 Jul 05 05:01:06 PM PDT 24 49106350343 ps
T356 /workspace/coverage/default/0.rom_ctrl_stress_all.2367092471 Jul 05 04:29:34 PM PDT 24 Jul 05 04:30:28 PM PDT 24 2627869048 ps
T357 /workspace/coverage/default/40.rom_ctrl_stress_all.3004818801 Jul 05 04:30:05 PM PDT 24 Jul 05 04:31:23 PM PDT 24 7071456779 ps
T358 /workspace/coverage/default/33.rom_ctrl_stress_all.3265567438 Jul 05 04:29:53 PM PDT 24 Jul 05 04:30:29 PM PDT 24 39970063553 ps
T47 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1857192971 Jul 05 04:47:25 PM PDT 24 Jul 05 04:49:03 PM PDT 24 3035905326 ps
T50 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2705824967 Jul 05 04:47:12 PM PDT 24 Jul 05 04:47:36 PM PDT 24 4513984503 ps
T51 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.782599232 Jul 05 04:46:49 PM PDT 24 Jul 05 04:47:17 PM PDT 24 3358730604 ps
T96 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1054540787 Jul 05 04:47:19 PM PDT 24 Jul 05 04:47:44 PM PDT 24 12516154630 ps
T97 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3129801539 Jul 05 04:47:44 PM PDT 24 Jul 05 04:48:09 PM PDT 24 8244061684 ps
T98 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2922154052 Jul 05 04:47:12 PM PDT 24 Jul 05 04:47:30 PM PDT 24 8401256807 ps
T59 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3423222757 Jul 05 04:47:11 PM PDT 24 Jul 05 04:49:36 PM PDT 24 59105461977 ps
T99 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3700296026 Jul 05 04:47:12 PM PDT 24 Jul 05 04:47:32 PM PDT 24 1130106473 ps
T104 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1700825139 Jul 05 04:47:10 PM PDT 24 Jul 05 04:47:29 PM PDT 24 1634589326 ps
T359 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2357711264 Jul 05 04:46:47 PM PDT 24 Jul 05 04:46:56 PM PDT 24 167729668 ps
T60 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.964261599 Jul 05 04:46:46 PM PDT 24 Jul 05 04:47:02 PM PDT 24 880468633 ps
T61 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1365006328 Jul 05 04:46:43 PM PDT 24 Jul 05 04:46:52 PM PDT 24 688140881 ps
T62 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2705683822 Jul 05 04:47:42 PM PDT 24 Jul 05 04:50:44 PM PDT 24 51495901292 ps
T63 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1305049448 Jul 05 04:46:36 PM PDT 24 Jul 05 04:48:02 PM PDT 24 25866342619 ps
T48 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2108658749 Jul 05 04:47:10 PM PDT 24 Jul 05 04:50:00 PM PDT 24 6433165970 ps
T49 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.733398136 Jul 05 04:46:55 PM PDT 24 Jul 05 04:48:23 PM PDT 24 5095518045 ps
T100 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.802698772 Jul 05 04:47:44 PM PDT 24 Jul 05 04:49:44 PM PDT 24 10875590492 ps
T101 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.631314933 Jul 05 04:47:42 PM PDT 24 Jul 05 04:48:14 PM PDT 24 4640573656 ps
T109 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1140269447 Jul 05 04:47:34 PM PDT 24 Jul 05 04:50:09 PM PDT 24 2871559713 ps
T64 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3828660345 Jul 05 04:47:19 PM PDT 24 Jul 05 04:50:48 PM PDT 24 28136292035 ps
T360 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.110267761 Jul 05 04:47:25 PM PDT 24 Jul 05 04:48:53 PM PDT 24 16416139485 ps
T65 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.4073453754 Jul 05 04:47:41 PM PDT 24 Jul 05 04:47:50 PM PDT 24 176253699 ps
T66 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.4242609488 Jul 05 04:47:13 PM PDT 24 Jul 05 04:47:39 PM PDT 24 5297399809 ps
T361 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2760555257 Jul 05 04:47:13 PM PDT 24 Jul 05 04:47:43 PM PDT 24 3631418647 ps
T102 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1360838214 Jul 05 04:47:47 PM PDT 24 Jul 05 04:48:08 PM PDT 24 1959679880 ps
T362 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1398220379 Jul 05 04:47:40 PM PDT 24 Jul 05 04:47:53 PM PDT 24 611939147 ps
T363 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3351076393 Jul 05 04:47:17 PM PDT 24 Jul 05 04:47:44 PM PDT 24 30928238199 ps
T364 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3607662672 Jul 05 04:47:34 PM PDT 24 Jul 05 04:48:45 PM PDT 24 2101206185 ps
T365 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1467728483 Jul 05 04:46:55 PM PDT 24 Jul 05 04:47:23 PM PDT 24 3198046104 ps
T366 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2338975106 Jul 05 04:47:15 PM PDT 24 Jul 05 04:47:38 PM PDT 24 2730955207 ps
T367 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4263043604 Jul 05 04:46:55 PM PDT 24 Jul 05 04:47:25 PM PDT 24 3635286919 ps
T368 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2323020002 Jul 05 04:47:42 PM PDT 24 Jul 05 04:47:59 PM PDT 24 5793951986 ps
T369 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3699060482 Jul 05 04:47:04 PM PDT 24 Jul 05 04:47:14 PM PDT 24 177783553 ps
T112 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2788172584 Jul 05 04:47:34 PM PDT 24 Jul 05 04:50:33 PM PDT 24 15979147770 ps
T370 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1135252625 Jul 05 04:47:19 PM PDT 24 Jul 05 04:47:28 PM PDT 24 716626546 ps
T371 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4119134520 Jul 05 04:47:10 PM PDT 24 Jul 05 04:48:48 PM PDT 24 3892596847 ps
T103 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.410491301 Jul 05 04:47:41 PM PDT 24 Jul 05 04:49:27 PM PDT 24 11536889411 ps
T372 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.651390710 Jul 05 04:47:26 PM PDT 24 Jul 05 04:47:43 PM PDT 24 689557486 ps
T373 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.840830263 Jul 05 04:47:25 PM PDT 24 Jul 05 04:47:40 PM PDT 24 826695001 ps
T374 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3778073585 Jul 05 04:47:34 PM PDT 24 Jul 05 04:47:58 PM PDT 24 2274776695 ps
T114 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.901035891 Jul 05 04:47:12 PM PDT 24 Jul 05 04:49:58 PM PDT 24 5165619076 ps
T375 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1519483494 Jul 05 04:46:41 PM PDT 24 Jul 05 04:49:46 PM PDT 24 86618994572 ps
T376 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1396604835 Jul 05 04:46:48 PM PDT 24 Jul 05 04:47:10 PM PDT 24 10801552982 ps
T67 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1139128865 Jul 05 04:47:43 PM PDT 24 Jul 05 04:48:07 PM PDT 24 9287549642 ps
T377 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3292305095 Jul 05 04:47:34 PM PDT 24 Jul 05 04:48:00 PM PDT 24 5608631387 ps
T378 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.4270909889 Jul 05 04:46:48 PM PDT 24 Jul 05 04:47:17 PM PDT 24 9913501254 ps
T379 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2399548978 Jul 05 04:47:42 PM PDT 24 Jul 05 04:47:52 PM PDT 24 186227648 ps
T380 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.496555170 Jul 05 04:46:44 PM PDT 24 Jul 05 04:47:03 PM PDT 24 2975368582 ps
T75 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1599818347 Jul 05 04:47:13 PM PDT 24 Jul 05 04:49:31 PM PDT 24 47562163328 ps
T381 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2355170785 Jul 05 04:47:41 PM PDT 24 Jul 05 04:47:57 PM PDT 24 1335979962 ps
T76 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2855248194 Jul 05 04:46:39 PM PDT 24 Jul 05 04:46:48 PM PDT 24 338739227 ps
T115 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2345284655 Jul 05 04:47:11 PM PDT 24 Jul 05 04:49:48 PM PDT 24 349771003 ps
T382 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1471974182 Jul 05 04:46:48 PM PDT 24 Jul 05 04:47:14 PM PDT 24 5376721710 ps
T77 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2238603996 Jul 05 04:46:55 PM PDT 24 Jul 05 04:47:20 PM PDT 24 11434551580 ps
T78 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.4245586107 Jul 05 04:47:34 PM PDT 24 Jul 05 04:47:49 PM PDT 24 767114605 ps
T383 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.4233233048 Jul 05 04:46:55 PM PDT 24 Jul 05 04:49:59 PM PDT 24 92334531340 ps
T79 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1856870453 Jul 05 04:47:02 PM PDT 24 Jul 05 04:47:28 PM PDT 24 3461187940 ps
T384 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1923054180 Jul 05 04:47:03 PM PDT 24 Jul 05 04:47:19 PM PDT 24 11805231912 ps
T385 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1644336357 Jul 05 04:47:04 PM PDT 24 Jul 05 04:47:23 PM PDT 24 7415255874 ps
T386 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2456351101 Jul 05 04:47:12 PM PDT 24 Jul 05 04:47:29 PM PDT 24 4160597715 ps
T387 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2750870730 Jul 05 04:47:34 PM PDT 24 Jul 05 04:48:06 PM PDT 24 8658600133 ps
T110 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2861121495 Jul 05 04:46:46 PM PDT 24 Jul 05 04:48:27 PM PDT 24 3665069459 ps
T388 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2184682871 Jul 05 04:46:57 PM PDT 24 Jul 05 04:47:28 PM PDT 24 10978499741 ps
T389 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3533217973 Jul 05 04:46:41 PM PDT 24 Jul 05 04:46:54 PM PDT 24 338471621 ps
T390 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1014173579 Jul 05 04:47:03 PM PDT 24 Jul 05 04:47:16 PM PDT 24 661854379 ps
T391 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3402505569 Jul 05 04:47:24 PM PDT 24 Jul 05 04:47:44 PM PDT 24 1820935070 ps
T392 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1933293730 Jul 05 04:47:42 PM PDT 24 Jul 05 04:49:02 PM PDT 24 262850805 ps
T393 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.43061459 Jul 05 04:47:03 PM PDT 24 Jul 05 04:47:29 PM PDT 24 14712090321 ps
T394 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1630442303 Jul 05 04:46:52 PM PDT 24 Jul 05 04:47:27 PM PDT 24 3553370884 ps
T395 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2891467056 Jul 05 04:46:55 PM PDT 24 Jul 05 04:48:41 PM PDT 24 46024475971 ps
T396 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3203943818 Jul 05 04:47:48 PM PDT 24 Jul 05 04:48:06 PM PDT 24 4448345014 ps
T397 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1514595941 Jul 05 04:47:36 PM PDT 24 Jul 05 04:48:04 PM PDT 24 12484081564 ps
T398 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2679111456 Jul 05 04:46:41 PM PDT 24 Jul 05 04:47:13 PM PDT 24 17086991212 ps
T399 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2962545846 Jul 05 04:47:19 PM PDT 24 Jul 05 04:48:05 PM PDT 24 6742483697 ps
T400 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2496203754 Jul 05 04:47:14 PM PDT 24 Jul 05 04:47:42 PM PDT 24 12040932976 ps
T401 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4154460505 Jul 05 04:47:05 PM PDT 24 Jul 05 04:47:22 PM PDT 24 3341230502 ps
T402 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1875831615 Jul 05 04:46:55 PM PDT 24 Jul 05 04:47:18 PM PDT 24 8239347690 ps
T403 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.611039243 Jul 05 04:47:26 PM PDT 24 Jul 05 04:47:52 PM PDT 24 2689992237 ps
T404 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2253469383 Jul 05 04:46:54 PM PDT 24 Jul 05 04:47:15 PM PDT 24 2017098483 ps
T405 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3312530088 Jul 05 04:47:44 PM PDT 24 Jul 05 04:47:52 PM PDT 24 346318043 ps
T406 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1933545581 Jul 05 04:47:36 PM PDT 24 Jul 05 04:47:46 PM PDT 24 1002671433 ps
T407 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.917968546 Jul 05 04:47:20 PM PDT 24 Jul 05 04:47:52 PM PDT 24 3367565409 ps
T111 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3072042740 Jul 05 04:47:40 PM PDT 24 Jul 05 04:49:23 PM PDT 24 7994030204 ps
T408 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2653600245 Jul 05 04:46:54 PM PDT 24 Jul 05 04:47:13 PM PDT 24 1558662075 ps
T409 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2903845549 Jul 05 04:47:04 PM PDT 24 Jul 05 04:47:33 PM PDT 24 29107922908 ps
T410 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.223964909 Jul 05 04:47:14 PM PDT 24 Jul 05 04:48:37 PM PDT 24 4069396168 ps
T116 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.161061003 Jul 05 04:47:03 PM PDT 24 Jul 05 04:49:38 PM PDT 24 597243611 ps
T411 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3870553835 Jul 05 04:46:47 PM PDT 24 Jul 05 04:46:56 PM PDT 24 174313825 ps
T412 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1484004627 Jul 05 04:47:51 PM PDT 24 Jul 05 04:48:03 PM PDT 24 1325147783 ps
T413 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.856763598 Jul 05 04:47:09 PM PDT 24 Jul 05 04:47:35 PM PDT 24 12118945400 ps
T414 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1510513499 Jul 05 04:47:40 PM PDT 24 Jul 05 04:48:03 PM PDT 24 2122042455 ps
T415 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.902368443 Jul 05 04:47:26 PM PDT 24 Jul 05 04:47:35 PM PDT 24 276963958 ps
T80 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.624946505 Jul 05 04:47:49 PM PDT 24 Jul 05 04:50:49 PM PDT 24 21346575217 ps
T416 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4033733248 Jul 05 04:47:18 PM PDT 24 Jul 05 04:47:52 PM PDT 24 4148385858 ps
T417 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3087876940 Jul 05 04:46:48 PM PDT 24 Jul 05 04:47:04 PM PDT 24 937204146 ps
T418 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.775035853 Jul 05 04:47:40 PM PDT 24 Jul 05 04:48:05 PM PDT 24 2622696585 ps
T84 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1818028312 Jul 05 04:47:03 PM PDT 24 Jul 05 04:47:12 PM PDT 24 182009628 ps
T419 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1642783664 Jul 05 04:47:44 PM PDT 24 Jul 05 04:47:56 PM PDT 24 174382329 ps
T113 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.4176921850 Jul 05 04:47:26 PM PDT 24 Jul 05 04:50:15 PM PDT 24 2512336286 ps
T420 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4165616697 Jul 05 04:46:50 PM PDT 24 Jul 05 04:47:24 PM PDT 24 14383497054 ps
T421 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2409901803 Jul 05 04:47:34 PM PDT 24 Jul 05 04:48:53 PM PDT 24 17381260310 ps
T422 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.155008663 Jul 05 04:47:12 PM PDT 24 Jul 05 04:47:40 PM PDT 24 12467818357 ps
T423 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1733635488 Jul 05 04:46:56 PM PDT 24 Jul 05 04:47:26 PM PDT 24 73879842525 ps
T424 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3519760839 Jul 05 04:47:12 PM PDT 24 Jul 05 04:47:43 PM PDT 24 15088529716 ps
T81 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3216369228 Jul 05 04:46:47 PM PDT 24 Jul 05 04:46:56 PM PDT 24 719360525 ps
T82 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3166693510 Jul 05 04:46:47 PM PDT 24 Jul 05 04:48:37 PM PDT 24 51835598688 ps
T425 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1996930537 Jul 05 04:47:34 PM PDT 24 Jul 05 04:47:59 PM PDT 24 2688059453 ps
T426 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2466797412 Jul 05 04:47:11 PM PDT 24 Jul 05 04:47:42 PM PDT 24 5478122161 ps
T427 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2838227106 Jul 05 04:46:54 PM PDT 24 Jul 05 04:47:16 PM PDT 24 4452145974 ps
T428 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3773269219 Jul 05 04:46:56 PM PDT 24 Jul 05 04:47:27 PM PDT 24 13245423158 ps
T429 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2840878364 Jul 05 04:47:17 PM PDT 24 Jul 05 04:47:48 PM PDT 24 6834951268 ps
T430 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3308520226 Jul 05 04:46:48 PM PDT 24 Jul 05 04:47:07 PM PDT 24 1783849280 ps
T431 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4053151965 Jul 05 04:47:44 PM PDT 24 Jul 05 04:48:11 PM PDT 24 3137446469 ps
T432 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1928167210 Jul 05 04:47:18 PM PDT 24 Jul 05 04:47:42 PM PDT 24 2621975150 ps
T433 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1768478885 Jul 05 04:46:44 PM PDT 24 Jul 05 04:46:56 PM PDT 24 2082786860 ps
T434 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3281072941 Jul 05 04:47:42 PM PDT 24 Jul 05 04:49:07 PM PDT 24 668416274 ps
T435 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.438718654 Jul 05 04:46:41 PM PDT 24 Jul 05 04:47:15 PM PDT 24 14380146572 ps
T436 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3597142159 Jul 05 04:47:11 PM PDT 24 Jul 05 04:47:50 PM PDT 24 2884317958 ps
T437 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.439798406 Jul 05 04:46:52 PM PDT 24 Jul 05 04:47:00 PM PDT 24 533758223 ps
T118 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3730469431 Jul 05 04:47:16 PM PDT 24 Jul 05 04:49:49 PM PDT 24 535176926 ps
T438 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2248029665 Jul 05 04:47:03 PM PDT 24 Jul 05 04:47:53 PM PDT 24 6954274492 ps
T117 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.754460123 Jul 05 04:47:17 PM PDT 24 Jul 05 04:50:05 PM PDT 24 8802036807 ps
T439 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1044385368 Jul 05 04:47:12 PM PDT 24 Jul 05 04:47:44 PM PDT 24 14186259194 ps
T440 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.645752213 Jul 05 04:47:47 PM PDT 24 Jul 05 04:48:02 PM PDT 24 4461335594 ps
T441 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.77650170 Jul 05 04:47:19 PM PDT 24 Jul 05 04:47:33 PM PDT 24 2341261709 ps
T442 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.142328581 Jul 05 04:47:49 PM PDT 24 Jul 05 04:49:32 PM PDT 24 7699019896 ps
T443 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4052221698 Jul 05 04:46:55 PM PDT 24 Jul 05 04:48:38 PM PDT 24 66488255369 ps
T444 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.136675028 Jul 05 04:47:12 PM PDT 24 Jul 05 04:47:37 PM PDT 24 1538266637 ps
T445 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.674201091 Jul 05 04:46:53 PM PDT 24 Jul 05 04:47:12 PM PDT 24 27398073808 ps
T446 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3031151471 Jul 05 04:46:48 PM PDT 24 Jul 05 04:47:03 PM PDT 24 927430487 ps
T447 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3598710207 Jul 05 04:47:19 PM PDT 24 Jul 05 04:47:46 PM PDT 24 9196664947 ps
T448 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.170432442 Jul 05 04:47:03 PM PDT 24 Jul 05 04:47:21 PM PDT 24 1328129070 ps
T449 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.553994208 Jul 05 04:46:56 PM PDT 24 Jul 05 04:47:04 PM PDT 24 636682442 ps
T450 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2334222975 Jul 05 04:46:50 PM PDT 24 Jul 05 04:46:59 PM PDT 24 170731282 ps
T451 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.4223586748 Jul 05 04:46:56 PM PDT 24 Jul 05 04:47:29 PM PDT 24 17455029809 ps
T85 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1698490549 Jul 05 04:47:36 PM PDT 24 Jul 05 04:48:06 PM PDT 24 13195205939 ps
T452 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3926235674 Jul 05 04:47:41 PM PDT 24 Jul 05 04:48:14 PM PDT 24 3550490533 ps
T453 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1265229479 Jul 05 04:47:14 PM PDT 24 Jul 05 04:47:31 PM PDT 24 2126151141 ps
T454 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.672698891 Jul 05 04:46:48 PM PDT 24 Jul 05 04:46:57 PM PDT 24 345315051 ps
T455 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3408805414 Jul 05 04:47:01 PM PDT 24 Jul 05 04:47:31 PM PDT 24 14756368742 ps
T456 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2724756015 Jul 05 04:46:57 PM PDT 24 Jul 05 04:47:30 PM PDT 24 10525309576 ps
T83 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.347240838 Jul 05 04:47:04 PM PDT 24 Jul 05 04:48:02 PM PDT 24 1080598834 ps
T457 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1615281962 Jul 05 04:46:48 PM PDT 24 Jul 05 04:48:27 PM PDT 24 3351868709 ps
T458 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2175721329 Jul 05 04:46:47 PM PDT 24 Jul 05 04:48:22 PM PDT 24 2685729676 ps
T459 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3456595052 Jul 05 04:46:40 PM PDT 24 Jul 05 04:47:04 PM PDT 24 10983717962 ps

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.997864510
Short name T5
Test name
Test status
Simulation time 80171445765 ps
CPU time 1534.65 seconds
Started Jul 05 04:30:36 PM PDT 24
Finished Jul 05 04:56:16 PM PDT 24
Peak memory 237992 kb
Host smart-c8547cbe-64e7-4b1d-963d-dd3c95e77477
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997864510 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.997864510
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.123488285
Short name T28
Test name
Test status
Simulation time 40796578097 ps
CPU time 456.49 seconds
Started Jul 05 04:29:50 PM PDT 24
Finished Jul 05 04:37:29 PM PDT 24
Peak memory 225964 kb
Host smart-10ee09f2-33a4-494e-8bf7-3b8ad972f6d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123488285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.123488285
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1869240480
Short name T15
Test name
Test status
Simulation time 26394125403 ps
CPU time 173.51 seconds
Started Jul 05 04:30:03 PM PDT 24
Finished Jul 05 04:33:02 PM PDT 24
Peak memory 235764 kb
Host smart-2943b67b-d396-4f22-bf7a-ca41b3666d8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869240480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1869240480
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2788172584
Short name T112
Test name
Test status
Simulation time 15979147770 ps
CPU time 178.54 seconds
Started Jul 05 04:47:34 PM PDT 24
Finished Jul 05 04:50:33 PM PDT 24
Peak memory 214408 kb
Host smart-ca5b3d90-ea86-4824-a94a-138568ff2fb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788172584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2788172584
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3270687947
Short name T32
Test name
Test status
Simulation time 3258983029 ps
CPU time 250.59 seconds
Started Jul 05 04:29:39 PM PDT 24
Finished Jul 05 04:33:53 PM PDT 24
Peak memory 240680 kb
Host smart-9112af74-ebca-4a34-a4dc-9158f9aa9b6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270687947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3270687947
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.4181644204
Short name T12
Test name
Test status
Simulation time 3058204398 ps
CPU time 59.13 seconds
Started Jul 05 04:29:56 PM PDT 24
Finished Jul 05 04:30:58 PM PDT 24
Peak memory 217244 kb
Host smart-e17032b7-b272-4333-ba4d-6d95e98a6a17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181644204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.4181644204
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1118175677
Short name T1
Test name
Test status
Simulation time 3700124650 ps
CPU time 244.05 seconds
Started Jul 05 04:29:24 PM PDT 24
Finished Jul 05 04:33:37 PM PDT 24
Peak memory 238004 kb
Host smart-32dd331d-ca94-4b04-8a06-90472d8cb130
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118175677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1118175677
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3423222757
Short name T59
Test name
Test status
Simulation time 59105461977 ps
CPU time 144.97 seconds
Started Jul 05 04:47:11 PM PDT 24
Finished Jul 05 04:49:36 PM PDT 24
Peak memory 214964 kb
Host smart-17244540-d73a-4cf3-8177-e37e64de46a3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423222757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3423222757
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.161061003
Short name T116
Test name
Test status
Simulation time 597243611 ps
CPU time 153.84 seconds
Started Jul 05 04:47:03 PM PDT 24
Finished Jul 05 04:49:38 PM PDT 24
Peak memory 214160 kb
Host smart-c9d4d8f2-f63c-4d39-9532-48aa396511bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161061003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.161061003
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.831958868
Short name T52
Test name
Test status
Simulation time 7015766530 ps
CPU time 28.23 seconds
Started Jul 05 04:29:30 PM PDT 24
Finished Jul 05 04:30:05 PM PDT 24
Peak memory 217488 kb
Host smart-7d05c394-ea68-4016-b920-0790e02f46b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831958868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.831958868
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2109548747
Short name T24
Test name
Test status
Simulation time 47337915676 ps
CPU time 62.58 seconds
Started Jul 05 04:29:50 PM PDT 24
Finished Jul 05 04:30:54 PM PDT 24
Peak memory 219296 kb
Host smart-17ba0bb2-9508-4a13-b2cb-d3cc0c57cf84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109548747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2109548747
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3197657264
Short name T36
Test name
Test status
Simulation time 1378170930 ps
CPU time 19.17 seconds
Started Jul 05 04:30:03 PM PDT 24
Finished Jul 05 04:30:27 PM PDT 24
Peak memory 219200 kb
Host smart-c85d183f-9a4f-41ed-ab12-068f0bb590dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197657264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3197657264
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.4176921850
Short name T113
Test name
Test status
Simulation time 2512336286 ps
CPU time 167.86 seconds
Started Jul 05 04:47:26 PM PDT 24
Finished Jul 05 04:50:15 PM PDT 24
Peak memory 214192 kb
Host smart-92659eec-4e36-491f-9ca2-450934ef6c6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176921850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.4176921850
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.802698772
Short name T100
Test name
Test status
Simulation time 10875590492 ps
CPU time 119.97 seconds
Started Jul 05 04:47:44 PM PDT 24
Finished Jul 05 04:49:44 PM PDT 24
Peak memory 215504 kb
Host smart-ae5bdc47-7bbd-48d4-a91b-34b99261fb00
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802698772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.802698772
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3162347570
Short name T9
Test name
Test status
Simulation time 170412446221 ps
CPU time 217.97 seconds
Started Jul 05 04:30:06 PM PDT 24
Finished Jul 05 04:33:49 PM PDT 24
Peak memory 221344 kb
Host smart-33084eda-8efb-43e9-8389-1fd514a1adb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162347570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3162347570
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2861121495
Short name T110
Test name
Test status
Simulation time 3665069459 ps
CPU time 101.39 seconds
Started Jul 05 04:46:46 PM PDT 24
Finished Jul 05 04:48:27 PM PDT 24
Peak memory 213380 kb
Host smart-38592065-5adf-4016-916e-6afb4abeceb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861121495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2861121495
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2296822086
Short name T86
Test name
Test status
Simulation time 48947911961 ps
CPU time 103.71 seconds
Started Jul 05 04:30:51 PM PDT 24
Finished Jul 05 04:32:36 PM PDT 24
Peak memory 220440 kb
Host smart-2ddefffa-e3ca-47ec-bbd7-af7963bf58b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296822086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2296822086
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3441035994
Short name T13
Test name
Test status
Simulation time 1824950068 ps
CPU time 51.14 seconds
Started Jul 05 04:29:44 PM PDT 24
Finished Jul 05 04:30:38 PM PDT 24
Peak memory 219240 kb
Host smart-f15d8970-5b2b-40ba-8696-31be12987262
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441035994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3441035994
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2855248194
Short name T76
Test name
Test status
Simulation time 338739227 ps
CPU time 8.31 seconds
Started Jul 05 04:46:39 PM PDT 24
Finished Jul 05 04:46:48 PM PDT 24
Peak memory 210736 kb
Host smart-81dd68e2-505c-445e-82e3-a4e3433d2839
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855248194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2855248194
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3456595052
Short name T459
Test name
Test status
Simulation time 10983717962 ps
CPU time 23.38 seconds
Started Jul 05 04:46:40 PM PDT 24
Finished Jul 05 04:47:04 PM PDT 24
Peak memory 211840 kb
Host smart-24e13f2d-efba-4abf-ac63-450b5bfc1a42
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456595052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3456595052
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1768478885
Short name T433
Test name
Test status
Simulation time 2082786860 ps
CPU time 11.7 seconds
Started Jul 05 04:46:44 PM PDT 24
Finished Jul 05 04:46:56 PM PDT 24
Peak memory 211728 kb
Host smart-10a94708-14d5-40b5-928c-e6e6a1c16c69
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768478885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1768478885
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.496555170
Short name T380
Test name
Test status
Simulation time 2975368582 ps
CPU time 19.02 seconds
Started Jul 05 04:46:44 PM PDT 24
Finished Jul 05 04:47:03 PM PDT 24
Peak memory 216264 kb
Host smart-490e4154-3be0-407e-ba7e-6baf69b415c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496555170 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.496555170
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1365006328
Short name T61
Test name
Test status
Simulation time 688140881 ps
CPU time 8.2 seconds
Started Jul 05 04:46:43 PM PDT 24
Finished Jul 05 04:46:52 PM PDT 24
Peak memory 210612 kb
Host smart-2bfd5a5d-206c-4eca-81e6-20b558fc370d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365006328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1365006328
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.674201091
Short name T445
Test name
Test status
Simulation time 27398073808 ps
CPU time 18.72 seconds
Started Jul 05 04:46:53 PM PDT 24
Finished Jul 05 04:47:12 PM PDT 24
Peak memory 210948 kb
Host smart-d1d947dd-cc40-4027-9b96-56fdd394b12c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674201091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.674201091
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2679111456
Short name T398
Test name
Test status
Simulation time 17086991212 ps
CPU time 31.26 seconds
Started Jul 05 04:46:41 PM PDT 24
Finished Jul 05 04:47:13 PM PDT 24
Peak memory 210932 kb
Host smart-92d767fe-8fe4-4c0d-9acf-3905e6261312
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679111456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2679111456
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1305049448
Short name T63
Test name
Test status
Simulation time 25866342619 ps
CPU time 84.06 seconds
Started Jul 05 04:46:36 PM PDT 24
Finished Jul 05 04:48:02 PM PDT 24
Peak memory 213836 kb
Host smart-3b75f05d-0e97-4442-90cc-2364c06895bf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305049448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1305049448
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.438718654
Short name T435
Test name
Test status
Simulation time 14380146572 ps
CPU time 32.23 seconds
Started Jul 05 04:46:41 PM PDT 24
Finished Jul 05 04:47:15 PM PDT 24
Peak memory 212784 kb
Host smart-e36f8490-ae4f-45e9-8282-78dfe1d2c7f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438718654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.438718654
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3533217973
Short name T389
Test name
Test status
Simulation time 338471621 ps
CPU time 11.87 seconds
Started Jul 05 04:46:41 PM PDT 24
Finished Jul 05 04:46:54 PM PDT 24
Peak memory 217100 kb
Host smart-c32d132c-3844-409b-9160-df2a8f7e1c4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533217973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3533217973
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3216369228
Short name T81
Test name
Test status
Simulation time 719360525 ps
CPU time 8.36 seconds
Started Jul 05 04:46:47 PM PDT 24
Finished Jul 05 04:46:56 PM PDT 24
Peak memory 210876 kb
Host smart-618c6adc-2df9-4e41-a638-b7be960998ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216369228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3216369228
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3087876940
Short name T417
Test name
Test status
Simulation time 937204146 ps
CPU time 15.3 seconds
Started Jul 05 04:46:48 PM PDT 24
Finished Jul 05 04:47:04 PM PDT 24
Peak memory 210784 kb
Host smart-212994cf-e66d-4573-becc-a9501f290299
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087876940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3087876940
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.964261599
Short name T60
Test name
Test status
Simulation time 880468633 ps
CPU time 15.44 seconds
Started Jul 05 04:46:46 PM PDT 24
Finished Jul 05 04:47:02 PM PDT 24
Peak memory 212180 kb
Host smart-dd424e31-e2bf-4b89-9d7e-6fa05a9e97a6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964261599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.964261599
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2253469383
Short name T404
Test name
Test status
Simulation time 2017098483 ps
CPU time 20.57 seconds
Started Jul 05 04:46:54 PM PDT 24
Finished Jul 05 04:47:15 PM PDT 24
Peak memory 216548 kb
Host smart-3c9b2663-b7b8-4778-ae06-1b571927422f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253469383 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2253469383
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.782599232
Short name T51
Test name
Test status
Simulation time 3358730604 ps
CPU time 28.11 seconds
Started Jul 05 04:46:49 PM PDT 24
Finished Jul 05 04:47:17 PM PDT 24
Peak memory 211660 kb
Host smart-c3364a61-afcf-48a8-9d33-ac3b2bc22dbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782599232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.782599232
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3031151471
Short name T446
Test name
Test status
Simulation time 927430487 ps
CPU time 14.51 seconds
Started Jul 05 04:46:48 PM PDT 24
Finished Jul 05 04:47:03 PM PDT 24
Peak memory 210648 kb
Host smart-94a6f711-7b4c-40c0-9832-627563fa7e1b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031151471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3031151471
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.439798406
Short name T437
Test name
Test status
Simulation time 533758223 ps
CPU time 8.18 seconds
Started Jul 05 04:46:52 PM PDT 24
Finished Jul 05 04:47:00 PM PDT 24
Peak memory 210572 kb
Host smart-34a1b067-b196-40e0-897c-abea0d63e284
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439798406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
439798406
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1519483494
Short name T375
Test name
Test status
Simulation time 86618994572 ps
CPU time 183.16 seconds
Started Jul 05 04:46:41 PM PDT 24
Finished Jul 05 04:49:46 PM PDT 24
Peak memory 215152 kb
Host smart-7c65748a-4f47-4cb5-8ed7-a4e9cfc1a657
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519483494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1519483494
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2334222975
Short name T450
Test name
Test status
Simulation time 170731282 ps
CPU time 8.42 seconds
Started Jul 05 04:46:50 PM PDT 24
Finished Jul 05 04:46:59 PM PDT 24
Peak memory 211504 kb
Host smart-dbc9da6a-8329-4ae1-888a-b0d84b8cd24e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334222975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2334222975
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1630442303
Short name T394
Test name
Test status
Simulation time 3553370884 ps
CPU time 33.76 seconds
Started Jul 05 04:46:52 PM PDT 24
Finished Jul 05 04:47:27 PM PDT 24
Peak memory 218532 kb
Host smart-7dc68e94-0469-40c7-8c4e-63c50a492437
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630442303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1630442303
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2175721329
Short name T458
Test name
Test status
Simulation time 2685729676 ps
CPU time 94.9 seconds
Started Jul 05 04:46:47 PM PDT 24
Finished Jul 05 04:48:22 PM PDT 24
Peak memory 213664 kb
Host smart-5a171b05-797c-4df4-bb92-6ebdc97ead40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175721329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2175721329
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1135252625
Short name T370
Test name
Test status
Simulation time 716626546 ps
CPU time 8.32 seconds
Started Jul 05 04:47:19 PM PDT 24
Finished Jul 05 04:47:28 PM PDT 24
Peak memory 213812 kb
Host smart-e3d6de80-4b04-441d-b763-7ebc7ea52118
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135252625 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1135252625
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4033733248
Short name T416
Test name
Test status
Simulation time 4148385858 ps
CPU time 33.21 seconds
Started Jul 05 04:47:18 PM PDT 24
Finished Jul 05 04:47:52 PM PDT 24
Peak memory 211848 kb
Host smart-19149391-9646-4d6e-b4a8-73ff6e2696eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033733248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.4033733248
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.223964909
Short name T410
Test name
Test status
Simulation time 4069396168 ps
CPU time 82.65 seconds
Started Jul 05 04:47:14 PM PDT 24
Finished Jul 05 04:48:37 PM PDT 24
Peak memory 215984 kb
Host smart-fca6e8db-f6ad-48db-8fec-4b21b4b13ea0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223964909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.223964909
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.917968546
Short name T407
Test name
Test status
Simulation time 3367565409 ps
CPU time 30.72 seconds
Started Jul 05 04:47:20 PM PDT 24
Finished Jul 05 04:47:52 PM PDT 24
Peak memory 212512 kb
Host smart-847fd03c-6fa8-4365-8e8c-6735d95dbc29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917968546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.917968546
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2840878364
Short name T429
Test name
Test status
Simulation time 6834951268 ps
CPU time 30.48 seconds
Started Jul 05 04:47:17 PM PDT 24
Finished Jul 05 04:47:48 PM PDT 24
Peak memory 218492 kb
Host smart-95c63a11-ec5b-43ee-84f7-84a1626b98e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840878364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2840878364
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3730469431
Short name T118
Test name
Test status
Simulation time 535176926 ps
CPU time 152.96 seconds
Started Jul 05 04:47:16 PM PDT 24
Finished Jul 05 04:49:49 PM PDT 24
Peak memory 214020 kb
Host smart-d3d5f5c9-be45-4847-a0b9-4091a3601dd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730469431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3730469431
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1928167210
Short name T432
Test name
Test status
Simulation time 2621975150 ps
CPU time 23.85 seconds
Started Jul 05 04:47:18 PM PDT 24
Finished Jul 05 04:47:42 PM PDT 24
Peak memory 217548 kb
Host smart-e2484dcc-2351-4976-a8e7-f494e2cab8ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928167210 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1928167210
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.77650170
Short name T441
Test name
Test status
Simulation time 2341261709 ps
CPU time 12.58 seconds
Started Jul 05 04:47:19 PM PDT 24
Finished Jul 05 04:47:33 PM PDT 24
Peak memory 211124 kb
Host smart-722028a0-0d1e-4bee-b423-6345cf24435d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77650170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.77650170
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2962545846
Short name T399
Test name
Test status
Simulation time 6742483697 ps
CPU time 44.19 seconds
Started Jul 05 04:47:19 PM PDT 24
Finished Jul 05 04:48:05 PM PDT 24
Peak memory 214856 kb
Host smart-f6a295d5-5710-44e6-8818-4bd62a94ec57
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962545846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2962545846
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1054540787
Short name T96
Test name
Test status
Simulation time 12516154630 ps
CPU time 24.1 seconds
Started Jul 05 04:47:19 PM PDT 24
Finished Jul 05 04:47:44 PM PDT 24
Peak memory 212608 kb
Host smart-3043e033-d971-4994-80dd-6a6ad6e93fd5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054540787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1054540787
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3351076393
Short name T363
Test name
Test status
Simulation time 30928238199 ps
CPU time 27.15 seconds
Started Jul 05 04:47:17 PM PDT 24
Finished Jul 05 04:47:44 PM PDT 24
Peak memory 218912 kb
Host smart-d6dd0313-71b8-48fb-ad92-761b8ff29672
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351076393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3351076393
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.754460123
Short name T117
Test name
Test status
Simulation time 8802036807 ps
CPU time 166.91 seconds
Started Jul 05 04:47:17 PM PDT 24
Finished Jul 05 04:50:05 PM PDT 24
Peak memory 214372 kb
Host smart-33751426-4d38-4ec7-8fbb-0c8ec345e543
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754460123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.754460123
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.840830263
Short name T373
Test name
Test status
Simulation time 826695001 ps
CPU time 14.01 seconds
Started Jul 05 04:47:25 PM PDT 24
Finished Jul 05 04:47:40 PM PDT 24
Peak memory 213656 kb
Host smart-2b368403-4e2f-40b8-9064-f8b7de0939d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840830263 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.840830263
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.902368443
Short name T415
Test name
Test status
Simulation time 276963958 ps
CPU time 8.32 seconds
Started Jul 05 04:47:26 PM PDT 24
Finished Jul 05 04:47:35 PM PDT 24
Peak memory 210720 kb
Host smart-c3eb441f-0832-4c59-a2a7-aa274062786b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902368443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.902368443
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3828660345
Short name T64
Test name
Test status
Simulation time 28136292035 ps
CPU time 208.1 seconds
Started Jul 05 04:47:19 PM PDT 24
Finished Jul 05 04:50:48 PM PDT 24
Peak memory 215004 kb
Host smart-10457cc8-22e1-4355-af63-621c3f78f96c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828660345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3828660345
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3402505569
Short name T391
Test name
Test status
Simulation time 1820935070 ps
CPU time 18.81 seconds
Started Jul 05 04:47:24 PM PDT 24
Finished Jul 05 04:47:44 PM PDT 24
Peak memory 212388 kb
Host smart-2d7d3698-0a15-4018-a16a-59235091f4be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402505569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3402505569
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3598710207
Short name T447
Test name
Test status
Simulation time 9196664947 ps
CPU time 26.49 seconds
Started Jul 05 04:47:19 PM PDT 24
Finished Jul 05 04:47:46 PM PDT 24
Peak memory 218784 kb
Host smart-07634fdf-052c-44c8-81fc-f26d0401dcc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598710207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3598710207
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1933545581
Short name T406
Test name
Test status
Simulation time 1002671433 ps
CPU time 10.19 seconds
Started Jul 05 04:47:36 PM PDT 24
Finished Jul 05 04:47:46 PM PDT 24
Peak memory 214424 kb
Host smart-12e7e1a5-578e-42f4-bbf6-dc13a3a7b204
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933545581 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1933545581
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.611039243
Short name T403
Test name
Test status
Simulation time 2689992237 ps
CPU time 25.03 seconds
Started Jul 05 04:47:26 PM PDT 24
Finished Jul 05 04:47:52 PM PDT 24
Peak memory 211784 kb
Host smart-a12b9b1d-04f7-4bee-9209-8a93a86f9704
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611039243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.611039243
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.110267761
Short name T360
Test name
Test status
Simulation time 16416139485 ps
CPU time 87.69 seconds
Started Jul 05 04:47:25 PM PDT 24
Finished Jul 05 04:48:53 PM PDT 24
Peak memory 213880 kb
Host smart-10d533fd-f275-4207-8752-a7188cb2bb80
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110267761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.110267761
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1514595941
Short name T397
Test name
Test status
Simulation time 12484081564 ps
CPU time 27.38 seconds
Started Jul 05 04:47:36 PM PDT 24
Finished Jul 05 04:48:04 PM PDT 24
Peak memory 212532 kb
Host smart-8f5612d5-e140-4f82-be5a-31acfe823b27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514595941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1514595941
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.651390710
Short name T372
Test name
Test status
Simulation time 689557486 ps
CPU time 16.37 seconds
Started Jul 05 04:47:26 PM PDT 24
Finished Jul 05 04:47:43 PM PDT 24
Peak memory 217248 kb
Host smart-2097d7a7-95f2-4c74-acb3-32c3a861110d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651390710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.651390710
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1857192971
Short name T47
Test name
Test status
Simulation time 3035905326 ps
CPU time 97.44 seconds
Started Jul 05 04:47:25 PM PDT 24
Finished Jul 05 04:49:03 PM PDT 24
Peak memory 213888 kb
Host smart-cef8964f-c9dc-4b9a-8f33-64573d30e6d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857192971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1857192971
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3292305095
Short name T377
Test name
Test status
Simulation time 5608631387 ps
CPU time 25.03 seconds
Started Jul 05 04:47:34 PM PDT 24
Finished Jul 05 04:48:00 PM PDT 24
Peak memory 217888 kb
Host smart-21b871ec-21a3-4723-8569-d8d280ca59cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292305095 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3292305095
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1698490549
Short name T85
Test name
Test status
Simulation time 13195205939 ps
CPU time 28.87 seconds
Started Jul 05 04:47:36 PM PDT 24
Finished Jul 05 04:48:06 PM PDT 24
Peak memory 212196 kb
Host smart-4bb8d728-6fef-4145-82fa-bf467892cada
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698490549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1698490549
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3607662672
Short name T364
Test name
Test status
Simulation time 2101206185 ps
CPU time 69.53 seconds
Started Jul 05 04:47:34 PM PDT 24
Finished Jul 05 04:48:45 PM PDT 24
Peak memory 213784 kb
Host smart-e3542919-7276-4b4d-816c-35e2bcb274b0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607662672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3607662672
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1996930537
Short name T425
Test name
Test status
Simulation time 2688059453 ps
CPU time 23.71 seconds
Started Jul 05 04:47:34 PM PDT 24
Finished Jul 05 04:47:59 PM PDT 24
Peak memory 212180 kb
Host smart-eb96d16a-4cb1-4e08-992d-f732c715e250
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996930537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1996930537
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2750870730
Short name T387
Test name
Test status
Simulation time 8658600133 ps
CPU time 31 seconds
Started Jul 05 04:47:34 PM PDT 24
Finished Jul 05 04:48:06 PM PDT 24
Peak memory 217412 kb
Host smart-5189d1f7-0c56-438f-bfcf-1123b5a4d084
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750870730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2750870730
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1140269447
Short name T109
Test name
Test status
Simulation time 2871559713 ps
CPU time 153.51 seconds
Started Jul 05 04:47:34 PM PDT 24
Finished Jul 05 04:50:09 PM PDT 24
Peak memory 219044 kb
Host smart-499f9eef-ad48-4af6-8155-dd43a1a83a0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140269447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1140269447
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1510513499
Short name T414
Test name
Test status
Simulation time 2122042455 ps
CPU time 21.71 seconds
Started Jul 05 04:47:40 PM PDT 24
Finished Jul 05 04:48:03 PM PDT 24
Peak memory 214684 kb
Host smart-0e202661-36f5-4588-bbf6-a9e060f83b78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510513499 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1510513499
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.4245586107
Short name T78
Test name
Test status
Simulation time 767114605 ps
CPU time 13.27 seconds
Started Jul 05 04:47:34 PM PDT 24
Finished Jul 05 04:47:49 PM PDT 24
Peak memory 210892 kb
Host smart-ba308bf5-c148-4e69-ab8d-9a6298d8994a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245586107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.4245586107
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2409901803
Short name T421
Test name
Test status
Simulation time 17381260310 ps
CPU time 78.42 seconds
Started Jul 05 04:47:34 PM PDT 24
Finished Jul 05 04:48:53 PM PDT 24
Peak memory 213908 kb
Host smart-1acd0929-b655-4087-b655-8ac07b34a6bf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409901803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2409901803
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.4073453754
Short name T65
Test name
Test status
Simulation time 176253699 ps
CPU time 8.31 seconds
Started Jul 05 04:47:41 PM PDT 24
Finished Jul 05 04:47:50 PM PDT 24
Peak memory 211316 kb
Host smart-4fc4b1bf-ea68-411e-a4bc-ab85e943cf81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073453754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.4073453754
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3778073585
Short name T374
Test name
Test status
Simulation time 2274776695 ps
CPU time 23.92 seconds
Started Jul 05 04:47:34 PM PDT 24
Finished Jul 05 04:47:58 PM PDT 24
Peak memory 217364 kb
Host smart-54c68023-fb78-477c-939c-ff4f8b473437
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778073585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3778073585
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2323020002
Short name T368
Test name
Test status
Simulation time 5793951986 ps
CPU time 16.76 seconds
Started Jul 05 04:47:42 PM PDT 24
Finished Jul 05 04:47:59 PM PDT 24
Peak memory 217300 kb
Host smart-5d7ec0f9-e501-459d-8861-a59c356da9ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323020002 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2323020002
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3312530088
Short name T405
Test name
Test status
Simulation time 346318043 ps
CPU time 8.16 seconds
Started Jul 05 04:47:44 PM PDT 24
Finished Jul 05 04:47:52 PM PDT 24
Peak memory 210672 kb
Host smart-bc62139c-360b-4a3c-8c68-cc9898a4198a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312530088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3312530088
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2705683822
Short name T62
Test name
Test status
Simulation time 51495901292 ps
CPU time 180.89 seconds
Started Jul 05 04:47:42 PM PDT 24
Finished Jul 05 04:50:44 PM PDT 24
Peak memory 215084 kb
Host smart-eb3e45e2-7866-479d-bb26-e8ea759a143d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705683822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2705683822
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.631314933
Short name T101
Test name
Test status
Simulation time 4640573656 ps
CPU time 30.76 seconds
Started Jul 05 04:47:42 PM PDT 24
Finished Jul 05 04:48:14 PM PDT 24
Peak memory 212448 kb
Host smart-e4362809-85fc-4e58-8ac4-2f3fb87dace6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631314933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.631314933
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3926235674
Short name T452
Test name
Test status
Simulation time 3550490533 ps
CPU time 32.11 seconds
Started Jul 05 04:47:41 PM PDT 24
Finished Jul 05 04:48:14 PM PDT 24
Peak memory 218528 kb
Host smart-d19adb0d-7ef2-494f-829c-833ac6dbd873
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926235674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3926235674
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3072042740
Short name T111
Test name
Test status
Simulation time 7994030204 ps
CPU time 101.82 seconds
Started Jul 05 04:47:40 PM PDT 24
Finished Jul 05 04:49:23 PM PDT 24
Peak memory 214016 kb
Host smart-3abf8040-ff90-438a-a026-22a0a649b063
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072042740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3072042740
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4053151965
Short name T431
Test name
Test status
Simulation time 3137446469 ps
CPU time 26.99 seconds
Started Jul 05 04:47:44 PM PDT 24
Finished Jul 05 04:48:11 PM PDT 24
Peak memory 217456 kb
Host smart-eb12bf36-f15d-4da7-a5cd-b409e48f8c0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053151965 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.4053151965
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2355170785
Short name T381
Test name
Test status
Simulation time 1335979962 ps
CPU time 16.07 seconds
Started Jul 05 04:47:41 PM PDT 24
Finished Jul 05 04:47:57 PM PDT 24
Peak memory 210896 kb
Host smart-b1ff3e6c-a673-4564-a715-cc69765d25ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355170785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2355170785
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1139128865
Short name T67
Test name
Test status
Simulation time 9287549642 ps
CPU time 23.14 seconds
Started Jul 05 04:47:43 PM PDT 24
Finished Jul 05 04:48:07 PM PDT 24
Peak memory 212772 kb
Host smart-897fe977-e04b-4b02-9ad6-ffa62055e212
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139128865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1139128865
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1398220379
Short name T362
Test name
Test status
Simulation time 611939147 ps
CPU time 12.27 seconds
Started Jul 05 04:47:40 PM PDT 24
Finished Jul 05 04:47:53 PM PDT 24
Peak memory 217508 kb
Host smart-6a484769-f5ba-48ff-bea5-2ba9479ea458
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398220379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1398220379
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3281072941
Short name T434
Test name
Test status
Simulation time 668416274 ps
CPU time 83.78 seconds
Started Jul 05 04:47:42 PM PDT 24
Finished Jul 05 04:49:07 PM PDT 24
Peak memory 213204 kb
Host smart-fcbce7fd-b846-4ef3-bf18-7173b1b93c12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281072941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3281072941
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2399548978
Short name T379
Test name
Test status
Simulation time 186227648 ps
CPU time 8.99 seconds
Started Jul 05 04:47:42 PM PDT 24
Finished Jul 05 04:47:52 PM PDT 24
Peak memory 217468 kb
Host smart-75102a96-6904-44bf-9ecf-8af5ff9342d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399548978 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2399548978
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.775035853
Short name T418
Test name
Test status
Simulation time 2622696585 ps
CPU time 23.83 seconds
Started Jul 05 04:47:40 PM PDT 24
Finished Jul 05 04:48:05 PM PDT 24
Peak memory 210848 kb
Host smart-773ae6a2-3358-40db-b890-8a16e3923279
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775035853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.775035853
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.410491301
Short name T103
Test name
Test status
Simulation time 11536889411 ps
CPU time 105.16 seconds
Started Jul 05 04:47:41 PM PDT 24
Finished Jul 05 04:49:27 PM PDT 24
Peak memory 214000 kb
Host smart-ea33e6d8-ed42-4e3d-b70c-c22c3302fcb4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410491301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pa
ssthru_mem_tl_intg_err.410491301
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3129801539
Short name T97
Test name
Test status
Simulation time 8244061684 ps
CPU time 24.71 seconds
Started Jul 05 04:47:44 PM PDT 24
Finished Jul 05 04:48:09 PM PDT 24
Peak memory 212740 kb
Host smart-d5a85974-9036-43ed-8bae-735e6dced8ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129801539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3129801539
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1642783664
Short name T419
Test name
Test status
Simulation time 174382329 ps
CPU time 11.51 seconds
Started Jul 05 04:47:44 PM PDT 24
Finished Jul 05 04:47:56 PM PDT 24
Peak memory 216956 kb
Host smart-ef405476-976d-48c7-941a-24992cf98bb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642783664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1642783664
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1933293730
Short name T392
Test name
Test status
Simulation time 262850805 ps
CPU time 80.19 seconds
Started Jul 05 04:47:42 PM PDT 24
Finished Jul 05 04:49:02 PM PDT 24
Peak memory 214748 kb
Host smart-ebca15b8-9f70-4e80-95e6-129323bb9764
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933293730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1933293730
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1484004627
Short name T412
Test name
Test status
Simulation time 1325147783 ps
CPU time 12.01 seconds
Started Jul 05 04:47:51 PM PDT 24
Finished Jul 05 04:48:03 PM PDT 24
Peak memory 215388 kb
Host smart-d4d254c6-824c-4c09-adb8-860ceb6fbb6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484004627 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1484004627
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.645752213
Short name T440
Test name
Test status
Simulation time 4461335594 ps
CPU time 15.15 seconds
Started Jul 05 04:47:47 PM PDT 24
Finished Jul 05 04:48:02 PM PDT 24
Peak memory 211424 kb
Host smart-fa137fe3-718a-44b5-81ef-bae953fdddb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645752213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.645752213
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.624946505
Short name T80
Test name
Test status
Simulation time 21346575217 ps
CPU time 180.22 seconds
Started Jul 05 04:47:49 PM PDT 24
Finished Jul 05 04:50:49 PM PDT 24
Peak memory 215028 kb
Host smart-e30f06c3-2329-4c04-9408-ecce123b2667
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624946505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.624946505
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1360838214
Short name T102
Test name
Test status
Simulation time 1959679880 ps
CPU time 20.18 seconds
Started Jul 05 04:47:47 PM PDT 24
Finished Jul 05 04:48:08 PM PDT 24
Peak memory 212428 kb
Host smart-14f06858-67dd-4bdc-bf5b-d4a7810b9b31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360838214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1360838214
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3203943818
Short name T396
Test name
Test status
Simulation time 4448345014 ps
CPU time 17.91 seconds
Started Jul 05 04:47:48 PM PDT 24
Finished Jul 05 04:48:06 PM PDT 24
Peak memory 217572 kb
Host smart-7d0342c1-78d4-4dc6-8387-3c57f7ab68ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203943818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3203943818
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.142328581
Short name T442
Test name
Test status
Simulation time 7699019896 ps
CPU time 102.28 seconds
Started Jul 05 04:47:49 PM PDT 24
Finished Jul 05 04:49:32 PM PDT 24
Peak memory 214056 kb
Host smart-7907c0e7-06d9-4835-af48-13806d468a20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142328581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.142328581
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.672698891
Short name T454
Test name
Test status
Simulation time 345315051 ps
CPU time 8.11 seconds
Started Jul 05 04:46:48 PM PDT 24
Finished Jul 05 04:46:57 PM PDT 24
Peak memory 210628 kb
Host smart-14a52046-8886-4df7-a29d-22bc49be1f32
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672698891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.672698891
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2357711264
Short name T359
Test name
Test status
Simulation time 167729668 ps
CPU time 8.63 seconds
Started Jul 05 04:46:47 PM PDT 24
Finished Jul 05 04:46:56 PM PDT 24
Peak memory 210704 kb
Host smart-59a74203-69e8-412e-bfb0-0b038558ce43
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357711264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2357711264
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4165616697
Short name T420
Test name
Test status
Simulation time 14383497054 ps
CPU time 33.88 seconds
Started Jul 05 04:46:50 PM PDT 24
Finished Jul 05 04:47:24 PM PDT 24
Peak memory 211824 kb
Host smart-1a2dbee9-9547-40cc-b526-034d29ba6277
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165616697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.4165616697
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2838227106
Short name T427
Test name
Test status
Simulation time 4452145974 ps
CPU time 21.33 seconds
Started Jul 05 04:46:54 PM PDT 24
Finished Jul 05 04:47:16 PM PDT 24
Peak memory 215884 kb
Host smart-e1efcb7c-5ead-401b-9efb-1f6cefc66140
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838227106 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2838227106
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3308520226
Short name T430
Test name
Test status
Simulation time 1783849280 ps
CPU time 18.65 seconds
Started Jul 05 04:46:48 PM PDT 24
Finished Jul 05 04:47:07 PM PDT 24
Peak memory 212104 kb
Host smart-69b187fe-0294-4281-9d9e-55eabf1715b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308520226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3308520226
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3870553835
Short name T411
Test name
Test status
Simulation time 174313825 ps
CPU time 8.32 seconds
Started Jul 05 04:46:47 PM PDT 24
Finished Jul 05 04:46:56 PM PDT 24
Peak memory 210552 kb
Host smart-0627917b-3960-4735-8bc2-be7c77e769e0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870553835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3870553835
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1396604835
Short name T376
Test name
Test status
Simulation time 10801552982 ps
CPU time 21.09 seconds
Started Jul 05 04:46:48 PM PDT 24
Finished Jul 05 04:47:10 PM PDT 24
Peak memory 210992 kb
Host smart-3fca53ad-7a10-455c-9fe8-2a16c5f762d0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396604835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1396604835
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3166693510
Short name T82
Test name
Test status
Simulation time 51835598688 ps
CPU time 109.69 seconds
Started Jul 05 04:46:47 PM PDT 24
Finished Jul 05 04:48:37 PM PDT 24
Peak memory 213880 kb
Host smart-9f024538-5a84-4b86-aeee-c619905233cc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166693510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3166693510
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.4270909889
Short name T378
Test name
Test status
Simulation time 9913501254 ps
CPU time 27.89 seconds
Started Jul 05 04:46:48 PM PDT 24
Finished Jul 05 04:47:17 PM PDT 24
Peak memory 212764 kb
Host smart-bc04dc7f-fbb2-428c-8290-9853f2ac8984
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270909889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.4270909889
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1471974182
Short name T382
Test name
Test status
Simulation time 5376721710 ps
CPU time 25.91 seconds
Started Jul 05 04:46:48 PM PDT 24
Finished Jul 05 04:47:14 PM PDT 24
Peak memory 218576 kb
Host smart-3624e964-f010-409e-a505-d40437fa43e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471974182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1471974182
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1615281962
Short name T457
Test name
Test status
Simulation time 3351868709 ps
CPU time 99.2 seconds
Started Jul 05 04:46:48 PM PDT 24
Finished Jul 05 04:48:27 PM PDT 24
Peak memory 213628 kb
Host smart-a5fc036e-caf7-4510-9754-a213b4bfa8ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615281962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1615281962
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2184682871
Short name T388
Test name
Test status
Simulation time 10978499741 ps
CPU time 30.59 seconds
Started Jul 05 04:46:57 PM PDT 24
Finished Jul 05 04:47:28 PM PDT 24
Peak memory 212424 kb
Host smart-af8ead9d-4a9a-4645-8673-23cbf161a5a9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184682871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2184682871
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2653600245
Short name T408
Test name
Test status
Simulation time 1558662075 ps
CPU time 18.61 seconds
Started Jul 05 04:46:54 PM PDT 24
Finished Jul 05 04:47:13 PM PDT 24
Peak memory 211368 kb
Host smart-92f653d4-03c0-4d01-93c5-7788c6cfdefb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653600245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2653600245
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2724756015
Short name T456
Test name
Test status
Simulation time 10525309576 ps
CPU time 32.38 seconds
Started Jul 05 04:46:57 PM PDT 24
Finished Jul 05 04:47:30 PM PDT 24
Peak memory 212368 kb
Host smart-417ed573-f4e4-482c-99bf-4df093bbecf7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724756015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2724756015
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4263043604
Short name T367
Test name
Test status
Simulation time 3635286919 ps
CPU time 29.67 seconds
Started Jul 05 04:46:55 PM PDT 24
Finished Jul 05 04:47:25 PM PDT 24
Peak memory 217708 kb
Host smart-9ec7e60f-666d-4f9c-81f6-1e0dcad2529c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263043604 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.4263043604
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2238603996
Short name T77
Test name
Test status
Simulation time 11434551580 ps
CPU time 24.57 seconds
Started Jul 05 04:46:55 PM PDT 24
Finished Jul 05 04:47:20 PM PDT 24
Peak memory 212360 kb
Host smart-4e6cd378-9fd5-44ab-903c-598c7c22d69c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238603996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2238603996
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1733635488
Short name T423
Test name
Test status
Simulation time 73879842525 ps
CPU time 29.79 seconds
Started Jul 05 04:46:56 PM PDT 24
Finished Jul 05 04:47:26 PM PDT 24
Peak memory 210892 kb
Host smart-f92ccf01-ca81-4e0b-9a1e-abe61e0e7784
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733635488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1733635488
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.553994208
Short name T449
Test name
Test status
Simulation time 636682442 ps
CPU time 7.95 seconds
Started Jul 05 04:46:56 PM PDT 24
Finished Jul 05 04:47:04 PM PDT 24
Peak memory 210628 kb
Host smart-4554120e-abfc-468b-8646-af7e316aff56
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553994208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
553994208
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2891467056
Short name T395
Test name
Test status
Simulation time 46024475971 ps
CPU time 105.11 seconds
Started Jul 05 04:46:55 PM PDT 24
Finished Jul 05 04:48:41 PM PDT 24
Peak memory 214100 kb
Host smart-3b129be9-140c-4b24-9fc5-22c53abebaf2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891467056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2891467056
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.4223586748
Short name T451
Test name
Test status
Simulation time 17455029809 ps
CPU time 32.18 seconds
Started Jul 05 04:46:56 PM PDT 24
Finished Jul 05 04:47:29 PM PDT 24
Peak memory 212400 kb
Host smart-16857969-4833-42a6-8281-607c88be9161
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223586748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.4223586748
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3773269219
Short name T428
Test name
Test status
Simulation time 13245423158 ps
CPU time 30.27 seconds
Started Jul 05 04:46:56 PM PDT 24
Finished Jul 05 04:47:27 PM PDT 24
Peak memory 219060 kb
Host smart-1f418097-09e0-4fef-a5a8-a126663d7862
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773269219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3773269219
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4052221698
Short name T443
Test name
Test status
Simulation time 66488255369 ps
CPU time 102.46 seconds
Started Jul 05 04:46:55 PM PDT 24
Finished Jul 05 04:48:38 PM PDT 24
Peak memory 213620 kb
Host smart-b04401d0-0335-469c-bde7-fb31c4e13503
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052221698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.4052221698
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1856870453
Short name T79
Test name
Test status
Simulation time 3461187940 ps
CPU time 25.57 seconds
Started Jul 05 04:47:02 PM PDT 24
Finished Jul 05 04:47:28 PM PDT 24
Peak memory 211516 kb
Host smart-61c28eae-6ed1-4156-8dc1-77216f89d562
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856870453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1856870453
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1644336357
Short name T385
Test name
Test status
Simulation time 7415255874 ps
CPU time 18.56 seconds
Started Jul 05 04:47:04 PM PDT 24
Finished Jul 05 04:47:23 PM PDT 24
Peak memory 211960 kb
Host smart-7ade1ee7-bd92-4654-a71f-36c31533afe3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644336357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1644336357
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2903845549
Short name T409
Test name
Test status
Simulation time 29107922908 ps
CPU time 28.16 seconds
Started Jul 05 04:47:04 PM PDT 24
Finished Jul 05 04:47:33 PM PDT 24
Peak memory 212048 kb
Host smart-78a461c8-1561-43dc-bf2b-342d32fc1433
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903845549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2903845549
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3408805414
Short name T455
Test name
Test status
Simulation time 14756368742 ps
CPU time 28.95 seconds
Started Jul 05 04:47:01 PM PDT 24
Finished Jul 05 04:47:31 PM PDT 24
Peak memory 216000 kb
Host smart-cb846f34-65f2-41b3-8298-069dc5585c49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408805414 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3408805414
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1818028312
Short name T84
Test name
Test status
Simulation time 182009628 ps
CPU time 8.14 seconds
Started Jul 05 04:47:03 PM PDT 24
Finished Jul 05 04:47:12 PM PDT 24
Peak memory 210668 kb
Host smart-f4ab2bdf-341e-4811-91b6-39074fa7e9c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818028312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1818028312
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1923054180
Short name T384
Test name
Test status
Simulation time 11805231912 ps
CPU time 15.54 seconds
Started Jul 05 04:47:03 PM PDT 24
Finished Jul 05 04:47:19 PM PDT 24
Peak memory 210824 kb
Host smart-54b2b9ad-6ef4-4bf4-a26b-6548243fbc18
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923054180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1923054180
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1467728483
Short name T365
Test name
Test status
Simulation time 3198046104 ps
CPU time 28.13 seconds
Started Jul 05 04:46:55 PM PDT 24
Finished Jul 05 04:47:23 PM PDT 24
Peak memory 210636 kb
Host smart-a5a94ac7-fb94-4531-a448-77648e3754d1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467728483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1467728483
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.4233233048
Short name T383
Test name
Test status
Simulation time 92334531340 ps
CPU time 182.65 seconds
Started Jul 05 04:46:55 PM PDT 24
Finished Jul 05 04:49:59 PM PDT 24
Peak memory 214992 kb
Host smart-01dfb7ac-1fb5-439c-97c4-172550827017
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233233048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.4233233048
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.43061459
Short name T393
Test name
Test status
Simulation time 14712090321 ps
CPU time 25.34 seconds
Started Jul 05 04:47:03 PM PDT 24
Finished Jul 05 04:47:29 PM PDT 24
Peak memory 212784 kb
Host smart-0f4a7903-a5e7-4d50-8d39-a7a7df7fa260
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43061459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_same_csr_outstanding.43061459
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1875831615
Short name T402
Test name
Test status
Simulation time 8239347690 ps
CPU time 22.92 seconds
Started Jul 05 04:46:55 PM PDT 24
Finished Jul 05 04:47:18 PM PDT 24
Peak memory 218984 kb
Host smart-b7157588-e872-43f8-ba39-a9147167bbb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875831615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1875831615
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.733398136
Short name T49
Test name
Test status
Simulation time 5095518045 ps
CPU time 86.88 seconds
Started Jul 05 04:46:55 PM PDT 24
Finished Jul 05 04:48:23 PM PDT 24
Peak memory 212868 kb
Host smart-7f3a2331-7cd6-410f-8b08-edfa67fb5e77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733398136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.733398136
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3699060482
Short name T369
Test name
Test status
Simulation time 177783553 ps
CPU time 9.28 seconds
Started Jul 05 04:47:04 PM PDT 24
Finished Jul 05 04:47:14 PM PDT 24
Peak memory 217220 kb
Host smart-17507ba0-b087-4e31-803f-6640174c23c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699060482 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3699060482
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.170432442
Short name T448
Test name
Test status
Simulation time 1328129070 ps
CPU time 16.75 seconds
Started Jul 05 04:47:03 PM PDT 24
Finished Jul 05 04:47:21 PM PDT 24
Peak memory 211864 kb
Host smart-ac6c38e3-3a88-43af-98e5-7e9128abcbb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170432442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.170432442
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2248029665
Short name T438
Test name
Test status
Simulation time 6954274492 ps
CPU time 49.41 seconds
Started Jul 05 04:47:03 PM PDT 24
Finished Jul 05 04:47:53 PM PDT 24
Peak memory 214836 kb
Host smart-70b98886-8820-4de4-84d1-8ac107659623
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248029665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2248029665
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1014173579
Short name T390
Test name
Test status
Simulation time 661854379 ps
CPU time 12.1 seconds
Started Jul 05 04:47:03 PM PDT 24
Finished Jul 05 04:47:16 PM PDT 24
Peak memory 212364 kb
Host smart-b7e234ef-3c4f-4f94-ad00-c2c4c370187c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014173579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1014173579
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4154460505
Short name T401
Test name
Test status
Simulation time 3341230502 ps
CPU time 16.59 seconds
Started Jul 05 04:47:05 PM PDT 24
Finished Jul 05 04:47:22 PM PDT 24
Peak memory 218316 kb
Host smart-936979da-d572-466b-91f5-2eef12bf276f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154460505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.4154460505
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.155008663
Short name T422
Test name
Test status
Simulation time 12467818357 ps
CPU time 27.74 seconds
Started Jul 05 04:47:12 PM PDT 24
Finished Jul 05 04:47:40 PM PDT 24
Peak memory 217956 kb
Host smart-7ec4da44-0d3b-46d2-812d-bf75344079fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155008663 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.155008663
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.4242609488
Short name T66
Test name
Test status
Simulation time 5297399809 ps
CPU time 24.43 seconds
Started Jul 05 04:47:13 PM PDT 24
Finished Jul 05 04:47:39 PM PDT 24
Peak memory 211888 kb
Host smart-83e3861a-5472-43ca-b6a3-afd244f149eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242609488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.4242609488
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.347240838
Short name T83
Test name
Test status
Simulation time 1080598834 ps
CPU time 56.82 seconds
Started Jul 05 04:47:04 PM PDT 24
Finished Jul 05 04:48:02 PM PDT 24
Peak memory 215292 kb
Host smart-9b10f8ac-6375-406d-bfff-2b19cd02b15d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347240838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.347240838
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2922154052
Short name T98
Test name
Test status
Simulation time 8401256807 ps
CPU time 16.81 seconds
Started Jul 05 04:47:12 PM PDT 24
Finished Jul 05 04:47:30 PM PDT 24
Peak memory 212636 kb
Host smart-9482e769-7427-41cf-be2b-f825e26182a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922154052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2922154052
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.136675028
Short name T444
Test name
Test status
Simulation time 1538266637 ps
CPU time 23.77 seconds
Started Jul 05 04:47:12 PM PDT 24
Finished Jul 05 04:47:37 PM PDT 24
Peak memory 219012 kb
Host smart-7d3e00a8-5b24-4060-82ac-d32092adfe40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136675028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.136675028
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.901035891
Short name T114
Test name
Test status
Simulation time 5165619076 ps
CPU time 163.85 seconds
Started Jul 05 04:47:12 PM PDT 24
Finished Jul 05 04:49:58 PM PDT 24
Peak memory 219080 kb
Host smart-f54555b4-0807-4a8c-b147-0ea46d49a07a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901035891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.901035891
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.856763598
Short name T413
Test name
Test status
Simulation time 12118945400 ps
CPU time 25.6 seconds
Started Jul 05 04:47:09 PM PDT 24
Finished Jul 05 04:47:35 PM PDT 24
Peak memory 215912 kb
Host smart-6edf01db-9c82-4881-bc5b-ee40830a73b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856763598 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.856763598
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2705824967
Short name T50
Test name
Test status
Simulation time 4513984503 ps
CPU time 22.25 seconds
Started Jul 05 04:47:12 PM PDT 24
Finished Jul 05 04:47:36 PM PDT 24
Peak memory 212012 kb
Host smart-2d1e02c3-69e8-4f4a-8df6-b3bb0bb7c0e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705824967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2705824967
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3597142159
Short name T436
Test name
Test status
Simulation time 2884317958 ps
CPU time 38.02 seconds
Started Jul 05 04:47:11 PM PDT 24
Finished Jul 05 04:47:50 PM PDT 24
Peak memory 213920 kb
Host smart-0f424374-04a9-450b-8072-48880b128426
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597142159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3597142159
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1044385368
Short name T439
Test name
Test status
Simulation time 14186259194 ps
CPU time 30.46 seconds
Started Jul 05 04:47:12 PM PDT 24
Finished Jul 05 04:47:44 PM PDT 24
Peak memory 212356 kb
Host smart-0679f2c6-fe28-4a96-8038-99c84a9819e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044385368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1044385368
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2466797412
Short name T426
Test name
Test status
Simulation time 5478122161 ps
CPU time 30.58 seconds
Started Jul 05 04:47:11 PM PDT 24
Finished Jul 05 04:47:42 PM PDT 24
Peak memory 217848 kb
Host smart-69898b71-bea0-434c-a697-bee58eee59d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466797412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2466797412
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2108658749
Short name T48
Test name
Test status
Simulation time 6433165970 ps
CPU time 170.23 seconds
Started Jul 05 04:47:10 PM PDT 24
Finished Jul 05 04:50:00 PM PDT 24
Peak memory 214080 kb
Host smart-17f22dca-b2e8-467b-9a1c-e99ee0b21592
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108658749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2108658749
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2760555257
Short name T361
Test name
Test status
Simulation time 3631418647 ps
CPU time 29 seconds
Started Jul 05 04:47:13 PM PDT 24
Finished Jul 05 04:47:43 PM PDT 24
Peak memory 216776 kb
Host smart-ee85aa87-6b06-43b6-9635-f7ae020718e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760555257 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2760555257
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1700825139
Short name T104
Test name
Test status
Simulation time 1634589326 ps
CPU time 18.55 seconds
Started Jul 05 04:47:10 PM PDT 24
Finished Jul 05 04:47:29 PM PDT 24
Peak memory 211784 kb
Host smart-0edda878-827f-4bed-bb31-17395ab1af9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700825139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1700825139
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1599818347
Short name T75
Test name
Test status
Simulation time 47562163328 ps
CPU time 137.48 seconds
Started Jul 05 04:47:13 PM PDT 24
Finished Jul 05 04:49:31 PM PDT 24
Peak memory 215048 kb
Host smart-8d1156d1-e524-423f-82d2-bcbe1953172c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599818347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1599818347
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3519760839
Short name T424
Test name
Test status
Simulation time 15088529716 ps
CPU time 29.78 seconds
Started Jul 05 04:47:12 PM PDT 24
Finished Jul 05 04:47:43 PM PDT 24
Peak memory 212428 kb
Host smart-7566828e-9f48-46b5-8bd8-c24b94771285
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519760839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3519760839
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1265229479
Short name T453
Test name
Test status
Simulation time 2126151141 ps
CPU time 16.69 seconds
Started Jul 05 04:47:14 PM PDT 24
Finished Jul 05 04:47:31 PM PDT 24
Peak memory 218976 kb
Host smart-c94d880d-4f42-4a83-991a-dc4782e527bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265229479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1265229479
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4119134520
Short name T371
Test name
Test status
Simulation time 3892596847 ps
CPU time 97.13 seconds
Started Jul 05 04:47:10 PM PDT 24
Finished Jul 05 04:48:48 PM PDT 24
Peak memory 213800 kb
Host smart-2edb9a49-bb3e-4b6a-a404-170162c571c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119134520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.4119134520
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2456351101
Short name T386
Test name
Test status
Simulation time 4160597715 ps
CPU time 16.24 seconds
Started Jul 05 04:47:12 PM PDT 24
Finished Jul 05 04:47:29 PM PDT 24
Peak memory 217472 kb
Host smart-38cc54d3-b250-4674-be17-4d40fb84121b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456351101 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2456351101
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2338975106
Short name T366
Test name
Test status
Simulation time 2730955207 ps
CPU time 23.09 seconds
Started Jul 05 04:47:15 PM PDT 24
Finished Jul 05 04:47:38 PM PDT 24
Peak memory 211944 kb
Host smart-01472c7d-129d-4a7e-b395-299a95d1d5d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338975106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2338975106
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3700296026
Short name T99
Test name
Test status
Simulation time 1130106473 ps
CPU time 18.89 seconds
Started Jul 05 04:47:12 PM PDT 24
Finished Jul 05 04:47:32 PM PDT 24
Peak memory 211548 kb
Host smart-521ecca7-cd76-4fe4-910e-85051c6df2ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700296026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3700296026
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2496203754
Short name T400
Test name
Test status
Simulation time 12040932976 ps
CPU time 27.44 seconds
Started Jul 05 04:47:14 PM PDT 24
Finished Jul 05 04:47:42 PM PDT 24
Peak memory 217300 kb
Host smart-17ba6741-3fc3-40fb-b467-acab830a3bef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496203754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2496203754
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2345284655
Short name T115
Test name
Test status
Simulation time 349771003 ps
CPU time 156.07 seconds
Started Jul 05 04:47:11 PM PDT 24
Finished Jul 05 04:49:48 PM PDT 24
Peak memory 214172 kb
Host smart-f3541b09-32a6-41dc-aa55-4981d5e53d03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345284655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2345284655
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2849538096
Short name T37
Test name
Test status
Simulation time 18505160977 ps
CPU time 416.3 seconds
Started Jul 05 04:29:44 PM PDT 24
Finished Jul 05 04:36:43 PM PDT 24
Peak memory 233568 kb
Host smart-bddba2a6-8f9d-4817-ab80-d18af41ef27b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849538096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2849538096
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2433059371
Short name T183
Test name
Test status
Simulation time 561404604 ps
CPU time 19 seconds
Started Jul 05 04:29:18 PM PDT 24
Finished Jul 05 04:29:46 PM PDT 24
Peak memory 219212 kb
Host smart-20ed8f2c-f81f-4562-acb4-ac1e70d03084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433059371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2433059371
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.279080850
Short name T164
Test name
Test status
Simulation time 491913465 ps
CPU time 13.64 seconds
Started Jul 05 04:29:31 PM PDT 24
Finished Jul 05 04:29:51 PM PDT 24
Peak memory 218460 kb
Host smart-bd635baf-b57c-49d8-a8fe-5f0dc6f5fc8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=279080850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.279080850
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.4063250395
Short name T25
Test name
Test status
Simulation time 3686017764 ps
CPU time 244.22 seconds
Started Jul 05 04:29:29 PM PDT 24
Finished Jul 05 04:33:41 PM PDT 24
Peak memory 237820 kb
Host smart-4594a11d-a469-450d-8cab-bbafcab062de
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063250395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.4063250395
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.279489725
Short name T265
Test name
Test status
Simulation time 11669270777 ps
CPU time 42.2 seconds
Started Jul 05 04:29:23 PM PDT 24
Finished Jul 05 04:30:14 PM PDT 24
Peak memory 217088 kb
Host smart-5cb3db19-f4e0-4aa4-9d0b-9eb61baa8abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279489725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.279489725
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2367092471
Short name T356
Test name
Test status
Simulation time 2627869048 ps
CPU time 48.65 seconds
Started Jul 05 04:29:34 PM PDT 24
Finished Jul 05 04:30:28 PM PDT 24
Peak memory 217372 kb
Host smart-df9095dd-810f-4844-a093-864bbfeb7de6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367092471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2367092471
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.2721182748
Short name T42
Test name
Test status
Simulation time 37246285805 ps
CPU time 1528.32 seconds
Started Jul 05 04:29:24 PM PDT 24
Finished Jul 05 04:55:02 PM PDT 24
Peak memory 239020 kb
Host smart-830879f5-758b-4670-a029-a74acfd22ecd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721182748 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.2721182748
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3963624772
Short name T259
Test name
Test status
Simulation time 1105225126 ps
CPU time 14.95 seconds
Started Jul 05 04:29:37 PM PDT 24
Finished Jul 05 04:29:56 PM PDT 24
Peak memory 216944 kb
Host smart-ad8be08b-e5a6-48c0-9b93-5be75c6be615
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963624772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3963624772
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.980829772
Short name T310
Test name
Test status
Simulation time 29574849196 ps
CPU time 426.74 seconds
Started Jul 05 04:29:23 PM PDT 24
Finished Jul 05 04:36:39 PM PDT 24
Peak memory 235736 kb
Host smart-d2ac6955-6cab-41b1-b5af-7bdd16be864d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980829772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.980829772
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.631948728
Short name T133
Test name
Test status
Simulation time 21069000643 ps
CPU time 37.53 seconds
Started Jul 05 04:29:14 PM PDT 24
Finished Jul 05 04:30:00 PM PDT 24
Peak memory 219292 kb
Host smart-8b973425-32ec-4573-948e-16b3b5fb0817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631948728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.631948728
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1457278201
Short name T334
Test name
Test status
Simulation time 966782241 ps
CPU time 10.38 seconds
Started Jul 05 04:29:28 PM PDT 24
Finished Jul 05 04:29:46 PM PDT 24
Peak memory 219156 kb
Host smart-2d34135e-0361-45dc-b4fc-857736215ec6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1457278201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1457278201
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1644646848
Short name T157
Test name
Test status
Simulation time 11469219692 ps
CPU time 31.63 seconds
Started Jul 05 04:29:12 PM PDT 24
Finished Jul 05 04:29:53 PM PDT 24
Peak memory 217152 kb
Host smart-365e70ed-dc2c-4062-97ce-8c388191fafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644646848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1644646848
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.99724038
Short name T150
Test name
Test status
Simulation time 16181598585 ps
CPU time 210.22 seconds
Started Jul 05 04:29:40 PM PDT 24
Finished Jul 05 04:33:14 PM PDT 24
Peak memory 227500 kb
Host smart-96985e01-a3be-45c2-8036-6ec1ca615b1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99724038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.rom_ctrl_stress_all.99724038
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.930742978
Short name T255
Test name
Test status
Simulation time 688137370 ps
CPU time 8.21 seconds
Started Jul 05 04:29:44 PM PDT 24
Finished Jul 05 04:29:55 PM PDT 24
Peak memory 216952 kb
Host smart-d645b769-958a-4b86-a84e-dae80b920489
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930742978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.930742978
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2577008865
Short name T203
Test name
Test status
Simulation time 92534571248 ps
CPU time 513 seconds
Started Jul 05 04:30:02 PM PDT 24
Finished Jul 05 04:38:40 PM PDT 24
Peak memory 226740 kb
Host smart-10cbd7ef-4679-4ba5-93cd-afa7cb1b53c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577008865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2577008865
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.4137974543
Short name T335
Test name
Test status
Simulation time 9370567096 ps
CPU time 32.86 seconds
Started Jul 05 04:29:28 PM PDT 24
Finished Jul 05 04:30:09 PM PDT 24
Peak memory 219264 kb
Host smart-9f093386-9823-48cf-ae0d-08f91b188689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137974543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.4137974543
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3707952179
Short name T307
Test name
Test status
Simulation time 5268382111 ps
CPU time 18.46 seconds
Started Jul 05 04:29:53 PM PDT 24
Finished Jul 05 04:30:14 PM PDT 24
Peak memory 219268 kb
Host smart-c77f69e7-4804-4539-9a28-6d4d6d577bdd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3707952179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3707952179
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3686173439
Short name T177
Test name
Test status
Simulation time 6415303293 ps
CPU time 52.9 seconds
Started Jul 05 04:29:47 PM PDT 24
Finished Jul 05 04:30:43 PM PDT 24
Peak memory 216748 kb
Host smart-fc8735d9-c00f-4364-b577-3f26a7332a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686173439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3686173439
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3689155492
Short name T328
Test name
Test status
Simulation time 2170904202 ps
CPU time 33.57 seconds
Started Jul 05 04:29:48 PM PDT 24
Finished Jul 05 04:30:24 PM PDT 24
Peak memory 219096 kb
Host smart-a7110414-7fa4-483e-a04e-3b2c85753783
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689155492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3689155492
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.2077064693
Short name T327
Test name
Test status
Simulation time 25235157680 ps
CPU time 7305.66 seconds
Started Jul 05 04:29:34 PM PDT 24
Finished Jul 05 06:31:26 PM PDT 24
Peak memory 233036 kb
Host smart-d3001b3a-52cd-4106-b5cf-527728e3b157
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077064693 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.2077064693
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3255154276
Short name T341
Test name
Test status
Simulation time 16231651587 ps
CPU time 23.13 seconds
Started Jul 05 04:30:02 PM PDT 24
Finished Jul 05 04:30:30 PM PDT 24
Peak memory 217388 kb
Host smart-ec30e99e-e03b-492d-a43a-37501ac8f485
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255154276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3255154276
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2208321172
Short name T313
Test name
Test status
Simulation time 640438248688 ps
CPU time 580.52 seconds
Started Jul 05 04:29:39 PM PDT 24
Finished Jul 05 04:39:23 PM PDT 24
Peak memory 219496 kb
Host smart-4557eab0-c051-461e-999c-23d4b31835ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208321172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2208321172
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3857275337
Short name T298
Test name
Test status
Simulation time 1377319304 ps
CPU time 28.41 seconds
Started Jul 05 04:29:52 PM PDT 24
Finished Jul 05 04:30:22 PM PDT 24
Peak memory 219172 kb
Host smart-eafd0c1b-a1cb-43ff-811f-e9dac94acf91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857275337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3857275337
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1700116248
Short name T147
Test name
Test status
Simulation time 9955501203 ps
CPU time 31.17 seconds
Started Jul 05 04:29:27 PM PDT 24
Finished Jul 05 04:30:06 PM PDT 24
Peak memory 219264 kb
Host smart-3cc12f53-3943-4248-a672-117ba33635a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1700116248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1700116248
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.573946871
Short name T231
Test name
Test status
Simulation time 7485159315 ps
CPU time 40.6 seconds
Started Jul 05 04:29:37 PM PDT 24
Finished Jul 05 04:30:21 PM PDT 24
Peak memory 217996 kb
Host smart-6d8c9dae-5cfd-4fd8-ae71-0e0d0f7093c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573946871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.573946871
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1431855132
Short name T178
Test name
Test status
Simulation time 15768731989 ps
CPU time 149.44 seconds
Started Jul 05 04:29:42 PM PDT 24
Finished Jul 05 04:32:14 PM PDT 24
Peak memory 219240 kb
Host smart-4bd3876c-f56e-4a0d-b311-3940d09d1b60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431855132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1431855132
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3310666152
Short name T239
Test name
Test status
Simulation time 719105957 ps
CPU time 8.34 seconds
Started Jul 05 04:30:01 PM PDT 24
Finished Jul 05 04:30:13 PM PDT 24
Peak memory 217160 kb
Host smart-d4470e8e-558b-4c31-9140-515472f8f8a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310666152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3310666152
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.4097815208
Short name T199
Test name
Test status
Simulation time 4418657392 ps
CPU time 135.8 seconds
Started Jul 05 04:29:43 PM PDT 24
Finished Jul 05 04:32:02 PM PDT 24
Peak memory 240152 kb
Host smart-c754ba20-aafc-4ee2-9248-c21d82b940e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097815208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.4097815208
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1217705633
Short name T329
Test name
Test status
Simulation time 1164629440 ps
CPU time 26.96 seconds
Started Jul 05 04:29:41 PM PDT 24
Finished Jul 05 04:30:12 PM PDT 24
Peak memory 219200 kb
Host smart-e75b91fe-011f-43fd-adfa-b69245703e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217705633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1217705633
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2669189380
Short name T127
Test name
Test status
Simulation time 1749994107 ps
CPU time 13.26 seconds
Started Jul 05 04:29:30 PM PDT 24
Finished Jul 05 04:29:50 PM PDT 24
Peak memory 218480 kb
Host smart-4e8f0143-04a4-420d-b965-4f67c3bd1ee9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2669189380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2669189380
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3233274627
Short name T172
Test name
Test status
Simulation time 16744571529 ps
CPU time 80.09 seconds
Started Jul 05 04:29:51 PM PDT 24
Finished Jul 05 04:31:12 PM PDT 24
Peak memory 216156 kb
Host smart-a58f4159-ca20-4e68-8fb1-576e10da60e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233274627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3233274627
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2091147950
Short name T143
Test name
Test status
Simulation time 102109021431 ps
CPU time 179.1 seconds
Started Jul 05 04:29:55 PM PDT 24
Finished Jul 05 04:32:57 PM PDT 24
Peak memory 220200 kb
Host smart-527eb178-fae0-4be3-a314-746b748cbd31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091147950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2091147950
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.51569394
Short name T174
Test name
Test status
Simulation time 8900032550 ps
CPU time 34.25 seconds
Started Jul 05 04:29:51 PM PDT 24
Finished Jul 05 04:30:26 PM PDT 24
Peak memory 217268 kb
Host smart-51ab8bf8-0e8d-4a58-9560-62fb3211ef16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51569394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.51569394
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1918311760
Short name T38
Test name
Test status
Simulation time 41999363784 ps
CPU time 385.9 seconds
Started Jul 05 04:29:39 PM PDT 24
Finished Jul 05 04:36:08 PM PDT 24
Peak memory 236888 kb
Host smart-62cfc559-88d3-4bcd-9822-a5c1371f7532
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918311760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1918311760
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1232113999
Short name T153
Test name
Test status
Simulation time 2292246516 ps
CPU time 23.15 seconds
Started Jul 05 04:30:02 PM PDT 24
Finished Jul 05 04:30:30 PM PDT 24
Peak memory 211200 kb
Host smart-8989dd33-322d-4a23-a9f2-28e7e902e160
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1232113999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1232113999
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.932643747
Short name T179
Test name
Test status
Simulation time 702761271 ps
CPU time 24.24 seconds
Started Jul 05 04:29:41 PM PDT 24
Finished Jul 05 04:30:08 PM PDT 24
Peak memory 216176 kb
Host smart-9e06c537-137b-4cfb-bbe7-995300f643ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932643747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.932643747
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2458913832
Short name T205
Test name
Test status
Simulation time 8057524284 ps
CPU time 66.96 seconds
Started Jul 05 04:29:53 PM PDT 24
Finished Jul 05 04:31:02 PM PDT 24
Peak memory 217144 kb
Host smart-98b0bc5f-554e-4274-bf8f-3c745585c91f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458913832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2458913832
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2082069692
Short name T151
Test name
Test status
Simulation time 991243309 ps
CPU time 10 seconds
Started Jul 05 04:29:39 PM PDT 24
Finished Jul 05 04:29:52 PM PDT 24
Peak memory 217064 kb
Host smart-89b9f59c-e939-4a51-81fd-f7cb0899d9e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082069692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2082069692
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3174062462
Short name T245
Test name
Test status
Simulation time 35440937311 ps
CPU time 427.22 seconds
Started Jul 05 04:29:44 PM PDT 24
Finished Jul 05 04:36:54 PM PDT 24
Peak memory 217788 kb
Host smart-a074385c-d968-419b-9943-ac07537a2565
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174062462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3174062462
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.522506477
Short name T23
Test name
Test status
Simulation time 26575266695 ps
CPU time 50.95 seconds
Started Jul 05 04:29:38 PM PDT 24
Finished Jul 05 04:30:32 PM PDT 24
Peak memory 219180 kb
Host smart-20b87cbe-0dfa-476b-bb48-8a0fe142fc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522506477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.522506477
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1121751260
Short name T352
Test name
Test status
Simulation time 955395562 ps
CPU time 12.01 seconds
Started Jul 05 04:29:46 PM PDT 24
Finished Jul 05 04:30:01 PM PDT 24
Peak memory 219196 kb
Host smart-12d93b13-0986-4893-bf7f-27768b95ff6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1121751260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1121751260
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.675127663
Short name T247
Test name
Test status
Simulation time 5741758026 ps
CPU time 21.12 seconds
Started Jul 05 04:29:50 PM PDT 24
Finished Jul 05 04:30:13 PM PDT 24
Peak memory 216968 kb
Host smart-971a7145-591b-4b4f-8d96-820fc03b6f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675127663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.675127663
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.821672192
Short name T161
Test name
Test status
Simulation time 2164846376 ps
CPU time 31.71 seconds
Started Jul 05 04:29:33 PM PDT 24
Finished Jul 05 04:30:10 PM PDT 24
Peak memory 218408 kb
Host smart-3fb25c9c-054e-4a5e-b3e9-bd1abd9bd8f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821672192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.821672192
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3107024100
Short name T7
Test name
Test status
Simulation time 29752691476 ps
CPU time 32.91 seconds
Started Jul 05 04:29:41 PM PDT 24
Finished Jul 05 04:30:17 PM PDT 24
Peak memory 217484 kb
Host smart-a02bd8b3-feb2-45e5-b1b8-0e0d999999fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107024100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3107024100
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1810917582
Short name T39
Test name
Test status
Simulation time 234259499568 ps
CPU time 546.95 seconds
Started Jul 05 04:29:44 PM PDT 24
Finished Jul 05 04:38:53 PM PDT 24
Peak memory 239716 kb
Host smart-c073764f-81de-425a-bdf4-ecdc6316deb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810917582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1810917582
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.871471682
Short name T21
Test name
Test status
Simulation time 6650390339 ps
CPU time 57.15 seconds
Started Jul 05 04:29:45 PM PDT 24
Finished Jul 05 04:30:44 PM PDT 24
Peak memory 219224 kb
Host smart-05ca52d3-a29f-4adb-916e-30a3a3cad821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871471682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.871471682
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.433614407
Short name T343
Test name
Test status
Simulation time 13165646511 ps
CPU time 30.21 seconds
Started Jul 05 04:29:42 PM PDT 24
Finished Jul 05 04:30:16 PM PDT 24
Peak memory 211768 kb
Host smart-21f66db8-1291-4e42-a181-19e74f7a9e17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=433614407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.433614407
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3818600669
Short name T70
Test name
Test status
Simulation time 16507458724 ps
CPU time 51.25 seconds
Started Jul 05 04:29:46 PM PDT 24
Finished Jul 05 04:30:40 PM PDT 24
Peak memory 216988 kb
Host smart-5b781bb4-cb96-4d46-b2bd-8cfeae2d0950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818600669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3818600669
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.4102816174
Short name T346
Test name
Test status
Simulation time 5102111763 ps
CPU time 28.29 seconds
Started Jul 05 04:29:43 PM PDT 24
Finished Jul 05 04:30:15 PM PDT 24
Peak memory 215648 kb
Host smart-d4b95aac-5bae-41c6-a85b-837efb6c866c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102816174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.4102816174
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1336498405
Short name T281
Test name
Test status
Simulation time 1711368516 ps
CPU time 18.79 seconds
Started Jul 05 04:29:46 PM PDT 24
Finished Jul 05 04:30:08 PM PDT 24
Peak memory 213184 kb
Host smart-bd0f50fb-fcb6-482c-a2a8-a17faf54e4ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336498405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1336498405
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2364766079
Short name T287
Test name
Test status
Simulation time 39623066546 ps
CPU time 209.13 seconds
Started Jul 05 04:29:43 PM PDT 24
Finished Jul 05 04:33:15 PM PDT 24
Peak memory 240092 kb
Host smart-46efaff3-57eb-4bf5-87bf-c7627987f8d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364766079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2364766079
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.122862168
Short name T258
Test name
Test status
Simulation time 8822321476 ps
CPU time 46.4 seconds
Started Jul 05 04:29:43 PM PDT 24
Finished Jul 05 04:30:32 PM PDT 24
Peak memory 219588 kb
Host smart-347c5078-35d0-4259-b7da-a6d34ea2ea62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122862168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.122862168
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2665989897
Short name T211
Test name
Test status
Simulation time 1555322910 ps
CPU time 18.77 seconds
Started Jul 05 04:29:31 PM PDT 24
Finished Jul 05 04:29:57 PM PDT 24
Peak memory 211136 kb
Host smart-b2ba1c42-307a-4cbe-9bba-6c91666e8a8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2665989897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2665989897
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2009814789
Short name T284
Test name
Test status
Simulation time 1372934018 ps
CPU time 20.66 seconds
Started Jul 05 04:29:43 PM PDT 24
Finished Jul 05 04:30:07 PM PDT 24
Peak memory 216840 kb
Host smart-3195aa9a-833a-4d3c-ae99-37e6922bcbd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009814789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2009814789
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2288969814
Short name T89
Test name
Test status
Simulation time 3491793639 ps
CPU time 56 seconds
Started Jul 05 04:29:41 PM PDT 24
Finished Jul 05 04:30:40 PM PDT 24
Peak memory 219320 kb
Host smart-88f2197a-618d-4f5d-8d9d-0a6a400b91d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288969814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2288969814
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.4026317799
Short name T324
Test name
Test status
Simulation time 42748157989 ps
CPU time 21.3 seconds
Started Jul 05 04:29:34 PM PDT 24
Finished Jul 05 04:30:06 PM PDT 24
Peak memory 217324 kb
Host smart-3c0a9abc-675b-4f9d-8556-2bc30642ce2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026317799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.4026317799
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2418634511
Short name T296
Test name
Test status
Simulation time 187859816773 ps
CPU time 840.45 seconds
Started Jul 05 04:29:48 PM PDT 24
Finished Jul 05 04:43:51 PM PDT 24
Peak memory 219452 kb
Host smart-3c7fd825-adc3-497d-9061-5eb42519bc0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418634511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2418634511
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2340636449
Short name T94
Test name
Test status
Simulation time 5692582365 ps
CPU time 50.29 seconds
Started Jul 05 04:29:45 PM PDT 24
Finished Jul 05 04:30:38 PM PDT 24
Peak memory 219184 kb
Host smart-193403d7-7aea-4fe4-9575-0eedb0ad1de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340636449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2340636449
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.4131072091
Short name T355
Test name
Test status
Simulation time 1361675586 ps
CPU time 13.17 seconds
Started Jul 05 04:29:52 PM PDT 24
Finished Jul 05 04:30:07 PM PDT 24
Peak memory 211572 kb
Host smart-81e28ae0-a0b2-400f-b5e6-8dc8864840f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4131072091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.4131072091
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.406614658
Short name T226
Test name
Test status
Simulation time 10365300374 ps
CPU time 58.79 seconds
Started Jul 05 04:30:05 PM PDT 24
Finished Jul 05 04:31:09 PM PDT 24
Peak memory 216292 kb
Host smart-86b816b4-fd38-4672-9fa7-e11f8d495fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406614658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.406614658
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1514815721
Short name T336
Test name
Test status
Simulation time 9505368431 ps
CPU time 89.38 seconds
Started Jul 05 04:29:49 PM PDT 24
Finished Jul 05 04:31:20 PM PDT 24
Peak memory 218560 kb
Host smart-9ba0bd27-b73e-4d83-8967-2bf50e65c303
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514815721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1514815721
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.184746301
Short name T129
Test name
Test status
Simulation time 4343911266 ps
CPU time 32.19 seconds
Started Jul 05 04:30:09 PM PDT 24
Finished Jul 05 04:30:45 PM PDT 24
Peak memory 213260 kb
Host smart-3a568243-fc90-4cbd-9b6d-b362c2c87385
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184746301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.184746301
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1553017529
Short name T301
Test name
Test status
Simulation time 205561262270 ps
CPU time 456.22 seconds
Started Jul 05 04:30:08 PM PDT 24
Finished Jul 05 04:37:48 PM PDT 24
Peak memory 240812 kb
Host smart-2ff0fef3-aa4f-4478-854a-5e4de02e1d87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553017529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1553017529
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.691691221
Short name T302
Test name
Test status
Simulation time 24791998979 ps
CPU time 58.52 seconds
Started Jul 05 04:29:44 PM PDT 24
Finished Jul 05 04:30:46 PM PDT 24
Peak memory 219092 kb
Host smart-51c4f849-65bb-4fc9-bf85-fbb8a0624fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691691221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.691691221
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1240857420
Short name T159
Test name
Test status
Simulation time 727987739 ps
CPU time 10.09 seconds
Started Jul 05 04:29:45 PM PDT 24
Finished Jul 05 04:29:58 PM PDT 24
Peak memory 219192 kb
Host smart-0effb2bc-9ea8-4c63-b9ea-a973553ca67b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1240857420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1240857420
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2030575831
Short name T146
Test name
Test status
Simulation time 13101693947 ps
CPU time 45.93 seconds
Started Jul 05 04:30:00 PM PDT 24
Finished Jul 05 04:30:50 PM PDT 24
Peak memory 216064 kb
Host smart-42e23301-1667-4a3d-bd9f-23e0a7a1e4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030575831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2030575831
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.168285389
Short name T244
Test name
Test status
Simulation time 379945513 ps
CPU time 21.3 seconds
Started Jul 05 04:29:55 PM PDT 24
Finished Jul 05 04:30:18 PM PDT 24
Peak memory 218512 kb
Host smart-96890a31-14cd-4137-94a7-f74eac610720
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168285389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.168285389
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1190867484
Short name T291
Test name
Test status
Simulation time 3956192627 ps
CPU time 14.81 seconds
Started Jul 05 04:29:52 PM PDT 24
Finished Jul 05 04:30:08 PM PDT 24
Peak memory 216968 kb
Host smart-c47b9ec1-2085-4e4a-9ac0-33d3daed11f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190867484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1190867484
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.4041132014
Short name T225
Test name
Test status
Simulation time 170145571442 ps
CPU time 604.64 seconds
Started Jul 05 04:30:06 PM PDT 24
Finished Jul 05 04:40:15 PM PDT 24
Peak memory 234872 kb
Host smart-913148d0-9539-4aff-938c-f75eb8e0fdc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041132014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.4041132014
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3778122427
Short name T273
Test name
Test status
Simulation time 4648076889 ps
CPU time 46.67 seconds
Started Jul 05 04:30:04 PM PDT 24
Finished Jul 05 04:30:56 PM PDT 24
Peak memory 219056 kb
Host smart-ec8c1b64-2ddc-4ed6-b35d-568dfe3f750d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778122427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3778122427
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.4116984122
Short name T149
Test name
Test status
Simulation time 13839563523 ps
CPU time 22.33 seconds
Started Jul 05 04:29:52 PM PDT 24
Finished Jul 05 04:30:16 PM PDT 24
Peak memory 219368 kb
Host smart-dc10584c-56b5-40f4-b483-7201fc7a6818
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4116984122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.4116984122
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.2900153229
Short name T271
Test name
Test status
Simulation time 16939331404 ps
CPU time 45.79 seconds
Started Jul 05 04:29:49 PM PDT 24
Finished Jul 05 04:30:37 PM PDT 24
Peak memory 216736 kb
Host smart-8613d6c0-63d8-4dc6-9caa-f3d8cc14cb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900153229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.2900153229
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2921651128
Short name T251
Test name
Test status
Simulation time 68473795155 ps
CPU time 150.52 seconds
Started Jul 05 04:30:05 PM PDT 24
Finished Jul 05 04:32:40 PM PDT 24
Peak memory 219280 kb
Host smart-750a7eef-b308-49b9-bbf4-9233d5fd24d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921651128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2921651128
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3864803739
Short name T162
Test name
Test status
Simulation time 11547230510 ps
CPU time 25.78 seconds
Started Jul 05 04:29:29 PM PDT 24
Finished Jul 05 04:30:02 PM PDT 24
Peak memory 217432 kb
Host smart-e41ed3d2-7d73-4a09-bb70-8065a0c74116
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864803739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3864803739
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2233296356
Short name T27
Test name
Test status
Simulation time 101404975539 ps
CPU time 390.27 seconds
Started Jul 05 04:29:32 PM PDT 24
Finished Jul 05 04:36:09 PM PDT 24
Peak memory 224796 kb
Host smart-d3cef121-717c-4ed2-a348-4a843da8adea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233296356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2233296356
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3323324639
Short name T35
Test name
Test status
Simulation time 332261182 ps
CPU time 18.68 seconds
Started Jul 05 04:29:10 PM PDT 24
Finished Jul 05 04:29:38 PM PDT 24
Peak memory 219168 kb
Host smart-11effa2e-04c9-4788-a887-0497dcce6471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323324639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3323324639
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3349225646
Short name T210
Test name
Test status
Simulation time 4591952380 ps
CPU time 23.22 seconds
Started Jul 05 04:30:32 PM PDT 24
Finished Jul 05 04:31:01 PM PDT 24
Peak memory 219212 kb
Host smart-ca096569-6b8d-4d12-a75f-8c6b0b7c4d49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3349225646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3349225646
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1722499358
Short name T20
Test name
Test status
Simulation time 4361327764 ps
CPU time 126.43 seconds
Started Jul 05 04:29:38 PM PDT 24
Finished Jul 05 04:31:48 PM PDT 24
Peak memory 238528 kb
Host smart-659e4467-3081-4e7d-b8a3-72925afee967
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722499358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1722499358
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2492369581
Short name T136
Test name
Test status
Simulation time 17756559898 ps
CPU time 42.96 seconds
Started Jul 05 04:30:36 PM PDT 24
Finished Jul 05 04:31:23 PM PDT 24
Peak memory 216400 kb
Host smart-e40cd0de-2496-46da-a4af-5870e999deb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492369581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2492369581
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.4131923038
Short name T350
Test name
Test status
Simulation time 17658297452 ps
CPU time 36.03 seconds
Started Jul 05 04:29:24 PM PDT 24
Finished Jul 05 04:30:09 PM PDT 24
Peak memory 214596 kb
Host smart-33499173-3ccf-48d2-9a36-353e21c111b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131923038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.4131923038
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.441513858
Short name T342
Test name
Test status
Simulation time 8007740892 ps
CPU time 31.87 seconds
Started Jul 05 04:30:01 PM PDT 24
Finished Jul 05 04:30:37 PM PDT 24
Peak memory 213228 kb
Host smart-029a2992-028f-4dba-a4cf-8426b881b4fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441513858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.441513858
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2648757119
Short name T154
Test name
Test status
Simulation time 2624984259 ps
CPU time 194.19 seconds
Started Jul 05 04:29:54 PM PDT 24
Finished Jul 05 04:33:10 PM PDT 24
Peak memory 241632 kb
Host smart-6ba7ec15-2033-445f-bd01-2610cc0093c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648757119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2648757119
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1604574306
Short name T141
Test name
Test status
Simulation time 24785763885 ps
CPU time 56.53 seconds
Started Jul 05 04:30:01 PM PDT 24
Finished Jul 05 04:31:02 PM PDT 24
Peak memory 219196 kb
Host smart-a0dc1a13-ef74-4531-8529-fdbba56bbd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604574306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1604574306
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2431619099
Short name T242
Test name
Test status
Simulation time 4305166661 ps
CPU time 16.58 seconds
Started Jul 05 04:29:47 PM PDT 24
Finished Jul 05 04:30:06 PM PDT 24
Peak memory 219252 kb
Host smart-19df71d3-f170-4d2b-af26-011eb4275776
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2431619099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2431619099
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.1232986779
Short name T68
Test name
Test status
Simulation time 8526359552 ps
CPU time 84.88 seconds
Started Jul 05 04:29:59 PM PDT 24
Finished Jul 05 04:31:27 PM PDT 24
Peak memory 217072 kb
Host smart-af42689c-ae0f-4923-a9df-b666bd5478bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232986779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.1232986779
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.1594515000
Short name T264
Test name
Test status
Simulation time 21493147362 ps
CPU time 117.58 seconds
Started Jul 05 04:30:07 PM PDT 24
Finished Jul 05 04:32:11 PM PDT 24
Peak memory 221636 kb
Host smart-e4873751-6e35-4d8d-b328-5cc577e4e913
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594515000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.1594515000
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2855752229
Short name T354
Test name
Test status
Simulation time 3525181203 ps
CPU time 20.05 seconds
Started Jul 05 04:29:43 PM PDT 24
Finished Jul 05 04:30:06 PM PDT 24
Peak memory 213212 kb
Host smart-4a820dae-8beb-4697-a2f4-a1cbb48302d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855752229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2855752229
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1775742703
Short name T274
Test name
Test status
Simulation time 5413234877 ps
CPU time 50.5 seconds
Started Jul 05 04:29:57 PM PDT 24
Finished Jul 05 04:30:50 PM PDT 24
Peak memory 219256 kb
Host smart-5c2c361f-91a1-4512-9660-3088646addc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775742703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1775742703
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.922132829
Short name T331
Test name
Test status
Simulation time 17183842086 ps
CPU time 32.39 seconds
Started Jul 05 04:30:05 PM PDT 24
Finished Jul 05 04:30:42 PM PDT 24
Peak memory 211720 kb
Host smart-2cb9afd5-b71c-4a86-a389-f55d242ebdee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=922132829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.922132829
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.1704703872
Short name T224
Test name
Test status
Simulation time 2699156790 ps
CPU time 27.87 seconds
Started Jul 05 04:29:49 PM PDT 24
Finished Jul 05 04:30:19 PM PDT 24
Peak memory 215904 kb
Host smart-328a8e2e-b229-4c35-95cc-f4ce317b0822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704703872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.1704703872
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3617162856
Short name T107
Test name
Test status
Simulation time 65703622176 ps
CPU time 149.19 seconds
Started Jul 05 04:29:57 PM PDT 24
Finished Jul 05 04:32:29 PM PDT 24
Peak memory 220760 kb
Host smart-f3688175-a2f2-4888-8ce1-e8c914795c10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617162856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3617162856
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1131157370
Short name T222
Test name
Test status
Simulation time 169020183 ps
CPU time 8.07 seconds
Started Jul 05 04:30:04 PM PDT 24
Finished Jul 05 04:30:17 PM PDT 24
Peak memory 216980 kb
Host smart-bd3cac06-3093-49ec-980c-bf9fb0dada4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131157370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1131157370
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1852818636
Short name T17
Test name
Test status
Simulation time 80464453392 ps
CPU time 782.8 seconds
Started Jul 05 04:29:55 PM PDT 24
Finished Jul 05 04:43:00 PM PDT 24
Peak memory 225600 kb
Host smart-42af336e-b280-459b-bcc9-c44087260ea2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852818636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1852818636
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.679424579
Short name T197
Test name
Test status
Simulation time 1375281698 ps
CPU time 19.05 seconds
Started Jul 05 04:29:54 PM PDT 24
Finished Jul 05 04:30:15 PM PDT 24
Peak memory 219160 kb
Host smart-2ae73ea1-3231-4237-9424-9209293e542e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679424579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.679424579
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2399209210
Short name T196
Test name
Test status
Simulation time 5286751570 ps
CPU time 18.81 seconds
Started Jul 05 04:29:47 PM PDT 24
Finished Jul 05 04:30:08 PM PDT 24
Peak memory 219228 kb
Host smart-25f5a318-ab0f-4415-af28-eb78afa094e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2399209210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2399209210
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1694117538
Short name T171
Test name
Test status
Simulation time 4843013248 ps
CPU time 48.08 seconds
Started Jul 05 04:30:02 PM PDT 24
Finished Jul 05 04:30:55 PM PDT 24
Peak memory 216416 kb
Host smart-b2aa5702-2e7c-4a48-9cf3-789aa9d4f668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694117538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1694117538
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3312129502
Short name T235
Test name
Test status
Simulation time 11657246308 ps
CPU time 65.06 seconds
Started Jul 05 04:29:54 PM PDT 24
Finished Jul 05 04:31:01 PM PDT 24
Peak memory 220652 kb
Host smart-ed2bebaa-4d22-4270-8c17-5d271414f069
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312129502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3312129502
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3103941482
Short name T315
Test name
Test status
Simulation time 1302602623 ps
CPU time 16.59 seconds
Started Jul 05 04:29:50 PM PDT 24
Finished Jul 05 04:30:08 PM PDT 24
Peak memory 217140 kb
Host smart-be094f12-deac-44c3-b3a6-76e74af80e6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103941482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3103941482
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.483761725
Short name T234
Test name
Test status
Simulation time 58919023713 ps
CPU time 516.5 seconds
Started Jul 05 04:29:50 PM PDT 24
Finished Jul 05 04:38:28 PM PDT 24
Peak memory 239888 kb
Host smart-5ecfe2a0-9e3b-4889-a293-f464a14ecf6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483761725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.483761725
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2182128529
Short name T124
Test name
Test status
Simulation time 3117003153 ps
CPU time 39.27 seconds
Started Jul 05 04:29:57 PM PDT 24
Finished Jul 05 04:30:38 PM PDT 24
Peak memory 219224 kb
Host smart-07d83cea-b5fa-4ca9-b365-ae5b55c9652a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182128529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2182128529
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3751708250
Short name T204
Test name
Test status
Simulation time 16425653300 ps
CPU time 31.95 seconds
Started Jul 05 04:29:44 PM PDT 24
Finished Jul 05 04:30:19 PM PDT 24
Peak memory 217592 kb
Host smart-436b9b85-9ccd-4992-9057-66630b53fe60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3751708250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3751708250
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.259765367
Short name T260
Test name
Test status
Simulation time 16484669885 ps
CPU time 65.08 seconds
Started Jul 05 04:29:51 PM PDT 24
Finished Jul 05 04:30:58 PM PDT 24
Peak memory 216628 kb
Host smart-d48ff8a5-028f-4d26-9c62-77354a53e793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259765367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.259765367
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1304395577
Short name T309
Test name
Test status
Simulation time 20870699383 ps
CPU time 100.34 seconds
Started Jul 05 04:30:01 PM PDT 24
Finished Jul 05 04:31:45 PM PDT 24
Peak memory 219332 kb
Host smart-3fb867ca-5e5e-4b65-b5b3-e2751f81c964
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304395577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1304395577
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3342615772
Short name T138
Test name
Test status
Simulation time 4503807208 ps
CPU time 22.38 seconds
Started Jul 05 04:29:55 PM PDT 24
Finished Jul 05 04:30:19 PM PDT 24
Peak memory 217372 kb
Host smart-16c58ed2-87c7-42fd-a273-ff0a2a5b8463
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342615772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3342615772
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.387212368
Short name T18
Test name
Test status
Simulation time 302156583170 ps
CPU time 502.39 seconds
Started Jul 05 04:29:53 PM PDT 24
Finished Jul 05 04:38:17 PM PDT 24
Peak memory 216980 kb
Host smart-0864e9fa-5ef3-4ea6-b3cb-1961975a671f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387212368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.387212368
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1426923266
Short name T142
Test name
Test status
Simulation time 4734106127 ps
CPU time 33.13 seconds
Started Jul 05 04:30:05 PM PDT 24
Finished Jul 05 04:30:42 PM PDT 24
Peak memory 219268 kb
Host smart-ebec01d4-7f31-4ae3-9a61-73233aabd09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426923266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1426923266
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1389259141
Short name T152
Test name
Test status
Simulation time 2583879756 ps
CPU time 25.04 seconds
Started Jul 05 04:29:45 PM PDT 24
Finished Jul 05 04:30:13 PM PDT 24
Peak memory 219268 kb
Host smart-05ee27a6-6bfd-42ca-9d87-f0f59b503d25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1389259141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1389259141
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.2865549906
Short name T158
Test name
Test status
Simulation time 13866565953 ps
CPU time 63.3 seconds
Started Jul 05 04:29:47 PM PDT 24
Finished Jul 05 04:30:53 PM PDT 24
Peak memory 216980 kb
Host smart-850d6ef2-f0c8-429b-a4a4-1f76f25a96d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865549906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.2865549906
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1943248464
Short name T337
Test name
Test status
Simulation time 16382072956 ps
CPU time 146.35 seconds
Started Jul 05 04:29:51 PM PDT 24
Finished Jul 05 04:32:19 PM PDT 24
Peak memory 219664 kb
Host smart-1bd2ab9d-42f5-4dc8-bff1-a247545833ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943248464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1943248464
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3463180119
Short name T175
Test name
Test status
Simulation time 8179426522 ps
CPU time 20.8 seconds
Started Jul 05 04:29:48 PM PDT 24
Finished Jul 05 04:30:11 PM PDT 24
Peak memory 217496 kb
Host smart-9f517e94-4ced-4a2e-b83c-54c47e32c2b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463180119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3463180119
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1011978013
Short name T283
Test name
Test status
Simulation time 51760437923 ps
CPU time 527.59 seconds
Started Jul 05 04:29:51 PM PDT 24
Finished Jul 05 04:38:40 PM PDT 24
Peak memory 233680 kb
Host smart-bbca04c1-ba63-4c29-b0a7-5d82005a5c9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011978013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1011978013
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2057539972
Short name T300
Test name
Test status
Simulation time 37420543259 ps
CPU time 35.77 seconds
Started Jul 05 04:29:41 PM PDT 24
Finished Jul 05 04:30:20 PM PDT 24
Peak memory 218640 kb
Host smart-7ded1aac-e506-4788-a80f-c97552618a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057539972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2057539972
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.4121697412
Short name T323
Test name
Test status
Simulation time 6867708351 ps
CPU time 28.34 seconds
Started Jul 05 04:29:51 PM PDT 24
Finished Jul 05 04:30:20 PM PDT 24
Peak memory 211556 kb
Host smart-82eda5d2-8e7d-42fe-aa63-a7918d458b60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4121697412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.4121697412
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.423065745
Short name T10
Test name
Test status
Simulation time 7035667068 ps
CPU time 41.58 seconds
Started Jul 05 04:29:41 PM PDT 24
Finished Jul 05 04:30:26 PM PDT 24
Peak memory 217248 kb
Host smart-ae933336-0a6f-4931-bcd0-65ff6aa0c2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423065745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.423065745
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2190727537
Short name T173
Test name
Test status
Simulation time 6709649966 ps
CPU time 106.62 seconds
Started Jul 05 04:29:44 PM PDT 24
Finished Jul 05 04:31:33 PM PDT 24
Peak memory 221436 kb
Host smart-fde6d296-9e9a-49e1-84e2-d15fc9f2e4db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190727537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2190727537
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.3588488351
Short name T44
Test name
Test status
Simulation time 95589641655 ps
CPU time 3745.57 seconds
Started Jul 05 04:31:48 PM PDT 24
Finished Jul 05 05:34:14 PM PDT 24
Peak memory 252136 kb
Host smart-bcf45889-9e04-41c3-8bcc-83ddd51b4e05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588488351 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.3588488351
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.44133222
Short name T126
Test name
Test status
Simulation time 970317782 ps
CPU time 8.12 seconds
Started Jul 05 04:29:59 PM PDT 24
Finished Jul 05 04:30:10 PM PDT 24
Peak memory 216908 kb
Host smart-a768ca4b-823c-4b3c-92e0-6a20402b8678
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44133222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.44133222
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3826089729
Short name T163
Test name
Test status
Simulation time 11720699491 ps
CPU time 245.51 seconds
Started Jul 05 04:30:01 PM PDT 24
Finished Jul 05 04:34:11 PM PDT 24
Peak memory 217800 kb
Host smart-75c8c30d-6641-4d14-9f7b-c89d6b804794
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826089729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3826089729
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1979370358
Short name T148
Test name
Test status
Simulation time 7856204417 ps
CPU time 54.7 seconds
Started Jul 05 04:30:01 PM PDT 24
Finished Jul 05 04:31:01 PM PDT 24
Peak memory 219240 kb
Host smart-101b5d2a-5e6a-447f-878f-bb6ac29b7a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979370358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1979370358
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3484149148
Short name T340
Test name
Test status
Simulation time 698960002 ps
CPU time 12.33 seconds
Started Jul 05 04:29:59 PM PDT 24
Finished Jul 05 04:30:15 PM PDT 24
Peak memory 211036 kb
Host smart-b863cc87-50c0-45c0-8904-17c95f0d4df7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3484149148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3484149148
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3252667847
Short name T188
Test name
Test status
Simulation time 695593744 ps
CPU time 20.59 seconds
Started Jul 05 04:29:47 PM PDT 24
Finished Jul 05 04:30:10 PM PDT 24
Peak memory 216576 kb
Host smart-6d1fac15-f1b0-4606-9eb8-2d4cb9545ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252667847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3252667847
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2630856837
Short name T248
Test name
Test status
Simulation time 2911956409 ps
CPU time 78.82 seconds
Started Jul 05 04:29:45 PM PDT 24
Finished Jul 05 04:31:06 PM PDT 24
Peak memory 220192 kb
Host smart-45327e5b-ab18-4c1d-aa21-07acf6f0be3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630856837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2630856837
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.594288735
Short name T192
Test name
Test status
Simulation time 10032570021 ps
CPU time 25.07 seconds
Started Jul 05 04:29:57 PM PDT 24
Finished Jul 05 04:30:24 PM PDT 24
Peak memory 217484 kb
Host smart-e47fa8b0-1a12-43a9-a55b-985730ca3ef7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594288735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.594288735
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.622933164
Short name T241
Test name
Test status
Simulation time 58688743913 ps
CPU time 701.87 seconds
Started Jul 05 04:29:49 PM PDT 24
Finished Jul 05 04:41:33 PM PDT 24
Peak memory 225536 kb
Host smart-8c7a8cfe-871b-4b3c-9290-f23de7645b8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622933164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.622933164
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1514986595
Short name T319
Test name
Test status
Simulation time 117113522353 ps
CPU time 67.3 seconds
Started Jul 05 04:29:55 PM PDT 24
Finished Jul 05 04:31:05 PM PDT 24
Peak memory 219136 kb
Host smart-314436ee-b789-4ea8-8edf-e37b2ce95fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514986595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1514986595
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1301007877
Short name T106
Test name
Test status
Simulation time 949525136 ps
CPU time 16.39 seconds
Started Jul 05 04:30:00 PM PDT 24
Finished Jul 05 04:30:21 PM PDT 24
Peak memory 218484 kb
Host smart-dc5892bc-5e32-463f-9c29-0b2c826a1cf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1301007877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1301007877
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2015957125
Short name T238
Test name
Test status
Simulation time 13794227127 ps
CPU time 74.68 seconds
Started Jul 05 04:29:58 PM PDT 24
Finished Jul 05 04:31:15 PM PDT 24
Peak memory 216620 kb
Host smart-f96a9d2c-56a1-4765-99fc-d6a2c821d2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015957125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2015957125
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1417929583
Short name T2
Test name
Test status
Simulation time 2053013202 ps
CPU time 35.93 seconds
Started Jul 05 04:30:02 PM PDT 24
Finished Jul 05 04:30:43 PM PDT 24
Peak memory 219764 kb
Host smart-1d40f6b2-8af4-4bfd-8321-05dc3f715bc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417929583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1417929583
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2254666316
Short name T134
Test name
Test status
Simulation time 4082675226 ps
CPU time 26.39 seconds
Started Jul 05 04:31:08 PM PDT 24
Finished Jul 05 04:31:36 PM PDT 24
Peak memory 217092 kb
Host smart-c41845be-02c3-48a1-8510-e7de64c39a37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254666316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2254666316
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1292980223
Short name T254
Test name
Test status
Simulation time 16240241157 ps
CPU time 505.83 seconds
Started Jul 05 04:30:06 PM PDT 24
Finished Jul 05 04:38:36 PM PDT 24
Peak memory 234796 kb
Host smart-d44543f4-77e6-4104-9ea7-1dfb2cd23fb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292980223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1292980223
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.911436559
Short name T325
Test name
Test status
Simulation time 28073590022 ps
CPU time 57.24 seconds
Started Jul 05 04:30:01 PM PDT 24
Finished Jul 05 04:31:02 PM PDT 24
Peak memory 219208 kb
Host smart-184e4f3c-a1d9-47f5-b6d9-965d9a8fb7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911436559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.911436559
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2793615774
Short name T297
Test name
Test status
Simulation time 3261954696 ps
CPU time 27.4 seconds
Started Jul 05 04:30:09 PM PDT 24
Finished Jul 05 04:30:40 PM PDT 24
Peak memory 219256 kb
Host smart-a023d838-b976-4284-aefc-e95d5ed54ded
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2793615774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2793615774
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.897515899
Short name T236
Test name
Test status
Simulation time 633197454 ps
CPU time 21.89 seconds
Started Jul 05 04:29:55 PM PDT 24
Finished Jul 05 04:30:19 PM PDT 24
Peak memory 219176 kb
Host smart-adaba59b-9a8e-4e32-9dd1-8514888eb1f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897515899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.rom_ctrl_stress_all.897515899
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2857820589
Short name T190
Test name
Test status
Simulation time 13625104620 ps
CPU time 27.58 seconds
Started Jul 05 04:29:47 PM PDT 24
Finished Jul 05 04:30:17 PM PDT 24
Peak memory 217380 kb
Host smart-00d4adbd-2ab2-4961-8c98-e9f9f3599e22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857820589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2857820589
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2777403612
Short name T29
Test name
Test status
Simulation time 103101227400 ps
CPU time 473.39 seconds
Started Jul 05 04:30:02 PM PDT 24
Finished Jul 05 04:38:00 PM PDT 24
Peak memory 236136 kb
Host smart-20705004-d577-4c71-9efd-a0cac2ccce8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777403612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2777403612
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1248297922
Short name T347
Test name
Test status
Simulation time 6003311128 ps
CPU time 52.3 seconds
Started Jul 05 04:30:08 PM PDT 24
Finished Jul 05 04:31:04 PM PDT 24
Peak memory 219240 kb
Host smart-cd0611c9-1ae2-4bf4-8e0a-788bc373751c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248297922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1248297922
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3205656287
Short name T213
Test name
Test status
Simulation time 3208949680 ps
CPU time 28.23 seconds
Started Jul 05 04:29:50 PM PDT 24
Finished Jul 05 04:30:25 PM PDT 24
Peak memory 217620 kb
Host smart-49605918-2d51-47c3-a622-afc2081365be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3205656287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3205656287
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.715485468
Short name T201
Test name
Test status
Simulation time 32890528358 ps
CPU time 66.76 seconds
Started Jul 05 04:29:59 PM PDT 24
Finished Jul 05 04:31:09 PM PDT 24
Peak memory 216332 kb
Host smart-57afde84-1630-4036-9c9f-2285bd137a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715485468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.715485468
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.708826236
Short name T73
Test name
Test status
Simulation time 73566200134 ps
CPU time 207.64 seconds
Started Jul 05 04:30:24 PM PDT 24
Finished Jul 05 04:33:57 PM PDT 24
Peak memory 220080 kb
Host smart-7cfc7c8c-de82-4fa7-a3a9-ddbc051c9025
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708826236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.708826236
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1490491234
Short name T45
Test name
Test status
Simulation time 19958349992 ps
CPU time 796.36 seconds
Started Jul 05 04:29:56 PM PDT 24
Finished Jul 05 04:43:15 PM PDT 24
Peak memory 229768 kb
Host smart-c9b19b89-427d-42ff-b590-3eb00744878c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490491234 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.1490491234
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.122124785
Short name T250
Test name
Test status
Simulation time 1069910513 ps
CPU time 15.5 seconds
Started Jul 05 04:29:39 PM PDT 24
Finished Jul 05 04:29:58 PM PDT 24
Peak memory 216984 kb
Host smart-9d77dca6-4f6c-4274-9e41-cdd59e213fa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122124785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.122124785
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3238641428
Short name T93
Test name
Test status
Simulation time 3109090509 ps
CPU time 200.56 seconds
Started Jul 05 04:29:41 PM PDT 24
Finished Jul 05 04:33:04 PM PDT 24
Peak memory 225608 kb
Host smart-7c94329e-d0ac-4d2d-92f6-ac1102c5a56c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238641428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3238641428
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2905036268
Short name T137
Test name
Test status
Simulation time 34703743174 ps
CPU time 67.37 seconds
Started Jul 05 04:29:41 PM PDT 24
Finished Jul 05 04:30:52 PM PDT 24
Peak memory 218492 kb
Host smart-dc8f94b5-dd24-4a71-88dc-5cefbdaaef90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905036268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2905036268
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1817278665
Short name T87
Test name
Test status
Simulation time 5393006882 ps
CPU time 26.3 seconds
Started Jul 05 04:29:49 PM PDT 24
Finished Jul 05 04:30:18 PM PDT 24
Peak memory 217624 kb
Host smart-dc4057a4-adc0-4529-aed5-948dbddc9fdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1817278665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1817278665
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2928877474
Short name T19
Test name
Test status
Simulation time 537900751 ps
CPU time 225.38 seconds
Started Jul 05 04:29:18 PM PDT 24
Finished Jul 05 04:33:13 PM PDT 24
Peak memory 238040 kb
Host smart-2c6a7ce9-53fd-40de-8b7a-de9b3e3bddc2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928877474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2928877474
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3916005244
Short name T120
Test name
Test status
Simulation time 3759136837 ps
CPU time 41.55 seconds
Started Jul 05 04:29:33 PM PDT 24
Finished Jul 05 04:30:20 PM PDT 24
Peak memory 216688 kb
Host smart-54becf97-5cc4-4d72-9e8b-215befb86683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916005244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3916005244
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1919959996
Short name T54
Test name
Test status
Simulation time 4789376488 ps
CPU time 16.08 seconds
Started Jul 05 04:29:55 PM PDT 24
Finished Jul 05 04:30:14 PM PDT 24
Peak memory 217484 kb
Host smart-37115c3e-ac09-4570-bac3-3f80b19bb24b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919959996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1919959996
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1869977164
Short name T229
Test name
Test status
Simulation time 105893326957 ps
CPU time 373.59 seconds
Started Jul 05 04:29:51 PM PDT 24
Finished Jul 05 04:36:06 PM PDT 24
Peak memory 216768 kb
Host smart-8a1e5663-f6aa-4a5e-aa82-d2705fa53ceb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869977164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1869977164
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1330595535
Short name T121
Test name
Test status
Simulation time 7539481767 ps
CPU time 63.74 seconds
Started Jul 05 04:30:09 PM PDT 24
Finished Jul 05 04:31:16 PM PDT 24
Peak memory 219128 kb
Host smart-1b9e8667-a780-4137-ae61-cdc826cef05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330595535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1330595535
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3852559658
Short name T326
Test name
Test status
Simulation time 36080614481 ps
CPU time 27.11 seconds
Started Jul 05 04:29:55 PM PDT 24
Finished Jul 05 04:30:25 PM PDT 24
Peak memory 219240 kb
Host smart-03977a77-6182-44fb-8ee1-b5eb6f585705
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3852559658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3852559658
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.342505070
Short name T249
Test name
Test status
Simulation time 7087701810 ps
CPU time 40.44 seconds
Started Jul 05 04:30:06 PM PDT 24
Finished Jul 05 04:30:51 PM PDT 24
Peak memory 217580 kb
Host smart-2e970764-c1b3-4fb9-aafe-b633a454033a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342505070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.342505070
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.179610421
Short name T299
Test name
Test status
Simulation time 4109327354 ps
CPU time 63.01 seconds
Started Jul 05 04:30:03 PM PDT 24
Finished Jul 05 04:31:15 PM PDT 24
Peak memory 216728 kb
Host smart-9570739c-e066-4fdc-a770-ea0abe156888
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179610421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.179610421
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3840169074
Short name T294
Test name
Test status
Simulation time 18579764045 ps
CPU time 24.94 seconds
Started Jul 05 04:30:02 PM PDT 24
Finished Jul 05 04:30:32 PM PDT 24
Peak memory 217392 kb
Host smart-0dc9a93f-da12-4d08-b2f7-4fc9ed97880e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840169074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3840169074
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3385690190
Short name T280
Test name
Test status
Simulation time 40963937593 ps
CPU time 53.57 seconds
Started Jul 05 04:30:17 PM PDT 24
Finished Jul 05 04:31:13 PM PDT 24
Peak memory 219184 kb
Host smart-cc41224c-faf9-468a-927f-967766aafea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385690190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3385690190
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2045735013
Short name T278
Test name
Test status
Simulation time 520735393 ps
CPU time 12.44 seconds
Started Jul 05 04:30:09 PM PDT 24
Finished Jul 05 04:30:30 PM PDT 24
Peak memory 218592 kb
Host smart-8f799a5d-af5f-48d7-8f06-c1d100f81d67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2045735013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2045735013
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3579061342
Short name T282
Test name
Test status
Simulation time 11189106666 ps
CPU time 51.04 seconds
Started Jul 05 04:29:52 PM PDT 24
Finished Jul 05 04:30:45 PM PDT 24
Peak memory 217308 kb
Host smart-8a8e517e-581e-41fa-899e-1a36f43421c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579061342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3579061342
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2143401870
Short name T320
Test name
Test status
Simulation time 71355262668 ps
CPU time 99.46 seconds
Started Jul 05 04:29:55 PM PDT 24
Finished Jul 05 04:31:37 PM PDT 24
Peak memory 219964 kb
Host smart-225c0ed9-b84f-404c-b0e4-4add148a7b64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143401870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2143401870
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.1459600295
Short name T108
Test name
Test status
Simulation time 49106350343 ps
CPU time 1855.4 seconds
Started Jul 05 04:30:06 PM PDT 24
Finished Jul 05 05:01:06 PM PDT 24
Peak memory 245608 kb
Host smart-527222a8-cd57-4444-ac50-97e219917314
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459600295 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.1459600295
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.685614114
Short name T219
Test name
Test status
Simulation time 11882271506 ps
CPU time 25.33 seconds
Started Jul 05 04:30:01 PM PDT 24
Finished Jul 05 04:30:30 PM PDT 24
Peak memory 217108 kb
Host smart-6122b376-e394-4d1f-b7a4-8bdc3cf8c4ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685614114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.685614114
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2008256865
Short name T31
Test name
Test status
Simulation time 4940732485 ps
CPU time 209.37 seconds
Started Jul 05 04:30:02 PM PDT 24
Finished Jul 05 04:33:36 PM PDT 24
Peak memory 236400 kb
Host smart-8d604135-23a7-48ee-b8a0-0c5859c65303
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008256865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2008256865
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.796956253
Short name T195
Test name
Test status
Simulation time 1376532308 ps
CPU time 19.08 seconds
Started Jul 05 04:29:46 PM PDT 24
Finished Jul 05 04:30:08 PM PDT 24
Peak memory 219228 kb
Host smart-7947ce4f-b14e-4ac5-abdb-4e2798edf332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796956253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.796956253
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.412023761
Short name T155
Test name
Test status
Simulation time 688551122 ps
CPU time 9.98 seconds
Started Jul 05 04:30:02 PM PDT 24
Finished Jul 05 04:30:17 PM PDT 24
Peak memory 219168 kb
Host smart-9447d375-6aa4-4745-b7cb-1f03440a9034
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=412023761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.412023761
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2137909570
Short name T91
Test name
Test status
Simulation time 683894862 ps
CPU time 19.32 seconds
Started Jul 05 04:29:54 PM PDT 24
Finished Jul 05 04:30:15 PM PDT 24
Peak memory 216160 kb
Host smart-ab2ae504-4523-4aea-b7ef-4052f2d07757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137909570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2137909570
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3599720061
Short name T3
Test name
Test status
Simulation time 3303559417 ps
CPU time 42 seconds
Started Jul 05 04:29:57 PM PDT 24
Finished Jul 05 04:30:42 PM PDT 24
Peak memory 216976 kb
Host smart-4a15372f-5cd8-48c4-a5f3-f32a5a616f32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599720061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3599720061
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.4167393002
Short name T6
Test name
Test status
Simulation time 72679506241 ps
CPU time 734.43 seconds
Started Jul 05 04:30:08 PM PDT 24
Finished Jul 05 04:42:26 PM PDT 24
Peak memory 234648 kb
Host smart-ded51854-bb31-4fa1-9d5e-e224108ee4d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167393002 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.4167393002
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3248937298
Short name T306
Test name
Test status
Simulation time 689689555 ps
CPU time 8.3 seconds
Started Jul 05 04:30:06 PM PDT 24
Finished Jul 05 04:30:19 PM PDT 24
Peak memory 216912 kb
Host smart-a7af41eb-ad7d-4bef-9a3c-cdf6e847fb48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248937298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3248937298
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1781327324
Short name T33
Test name
Test status
Simulation time 65603477713 ps
CPU time 595.71 seconds
Started Jul 05 04:36:48 PM PDT 24
Finished Jul 05 04:46:46 PM PDT 24
Peak memory 227344 kb
Host smart-c398b388-5ce4-44a7-8db7-6a8d772b00e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781327324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1781327324
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.296128517
Short name T57
Test name
Test status
Simulation time 6780770778 ps
CPU time 28.1 seconds
Started Jul 05 04:29:57 PM PDT 24
Finished Jul 05 04:30:28 PM PDT 24
Peak memory 211928 kb
Host smart-5328347c-830c-4952-94a0-6a5981d9f5fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=296128517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.296128517
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.4073928214
Short name T270
Test name
Test status
Simulation time 349987263 ps
CPU time 20.67 seconds
Started Jul 05 04:36:51 PM PDT 24
Finished Jul 05 04:37:15 PM PDT 24
Peak memory 216628 kb
Host smart-5059ee27-d03b-4621-938f-747785dd7764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073928214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.4073928214
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3265567438
Short name T358
Test name
Test status
Simulation time 39970063553 ps
CPU time 34.12 seconds
Started Jul 05 04:29:53 PM PDT 24
Finished Jul 05 04:30:29 PM PDT 24
Peak memory 219148 kb
Host smart-b8f91d70-3480-434a-b559-71e039f6bf3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265567438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3265567438
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1365081448
Short name T139
Test name
Test status
Simulation time 689180051 ps
CPU time 7.95 seconds
Started Jul 05 04:30:02 PM PDT 24
Finished Jul 05 04:30:20 PM PDT 24
Peak memory 217124 kb
Host smart-d76586bb-2bc2-4be4-8ef4-889b424ab51a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365081448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1365081448
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3334353890
Short name T92
Test name
Test status
Simulation time 4140869991 ps
CPU time 269.49 seconds
Started Jul 05 04:30:16 PM PDT 24
Finished Jul 05 04:34:48 PM PDT 24
Peak memory 235092 kb
Host smart-765fbaec-b9d3-4087-954e-e5ddbef4769f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334353890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3334353890
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2904006395
Short name T220
Test name
Test status
Simulation time 6024851429 ps
CPU time 55.25 seconds
Started Jul 05 04:30:21 PM PDT 24
Finished Jul 05 04:31:18 PM PDT 24
Peak memory 219228 kb
Host smart-f8a02805-15f9-4932-aba2-5cea534acc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904006395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2904006395
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3115040179
Short name T200
Test name
Test status
Simulation time 3874704936 ps
CPU time 31.51 seconds
Started Jul 05 04:30:03 PM PDT 24
Finished Jul 05 04:30:39 PM PDT 24
Peak memory 219232 kb
Host smart-3eff20d6-7ba7-4883-a05d-fe87ce66bbcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3115040179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3115040179
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3581685257
Short name T88
Test name
Test status
Simulation time 9851130295 ps
CPU time 70.12 seconds
Started Jul 05 04:30:01 PM PDT 24
Finished Jul 05 04:31:15 PM PDT 24
Peak memory 215920 kb
Host smart-ae710106-fd6e-4867-b63d-3c59a28c24da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581685257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3581685257
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1804080364
Short name T4
Test name
Test status
Simulation time 1114069567 ps
CPU time 14.82 seconds
Started Jul 05 04:29:59 PM PDT 24
Finished Jul 05 04:30:17 PM PDT 24
Peak memory 216984 kb
Host smart-fc76b7e6-2c26-4f2e-b27c-64901b87bff2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804080364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1804080364
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2896128107
Short name T269
Test name
Test status
Simulation time 79498667335 ps
CPU time 666.04 seconds
Started Jul 05 04:30:01 PM PDT 24
Finished Jul 05 04:41:12 PM PDT 24
Peak memory 234868 kb
Host smart-d0e9a8db-3511-46cd-a840-ae764fe0f78e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896128107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2896128107
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2098275024
Short name T286
Test name
Test status
Simulation time 15705158474 ps
CPU time 41.71 seconds
Started Jul 05 04:30:04 PM PDT 24
Finished Jul 05 04:30:50 PM PDT 24
Peak memory 219308 kb
Host smart-656f277b-376a-4a43-9443-d3d90d5339dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098275024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2098275024
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1156102442
Short name T56
Test name
Test status
Simulation time 3055792804 ps
CPU time 26.29 seconds
Started Jul 05 04:30:00 PM PDT 24
Finished Jul 05 04:30:30 PM PDT 24
Peak memory 219360 kb
Host smart-1b6190ee-65f9-43c5-8b11-b6e5121846b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1156102442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1156102442
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3193970766
Short name T304
Test name
Test status
Simulation time 25224124971 ps
CPU time 56.01 seconds
Started Jul 05 04:30:00 PM PDT 24
Finished Jul 05 04:31:00 PM PDT 24
Peak memory 216192 kb
Host smart-ac64fc40-3f71-4ba4-9e9d-45df4f3e92b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193970766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3193970766
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.949974385
Short name T240
Test name
Test status
Simulation time 20363549298 ps
CPU time 172.59 seconds
Started Jul 05 04:30:15 PM PDT 24
Finished Jul 05 04:33:10 PM PDT 24
Peak memory 220840 kb
Host smart-23f1d4c6-9c6a-45dc-8b99-c2c801deab8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949974385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.949974385
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1114821625
Short name T167
Test name
Test status
Simulation time 2947995226 ps
CPU time 13.34 seconds
Started Jul 05 04:30:07 PM PDT 24
Finished Jul 05 04:30:24 PM PDT 24
Peak memory 217008 kb
Host smart-9ab72b14-407c-46a4-86bd-d0f21277d351
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114821625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1114821625
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1118035572
Short name T232
Test name
Test status
Simulation time 81180394947 ps
CPU time 697.46 seconds
Started Jul 05 04:30:02 PM PDT 24
Finished Jul 05 04:41:44 PM PDT 24
Peak memory 219396 kb
Host smart-d81354c1-cc50-4654-94e3-ef87572435c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118035572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1118035572
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2021232882
Short name T145
Test name
Test status
Simulation time 9412340538 ps
CPU time 43.95 seconds
Started Jul 05 04:30:29 PM PDT 24
Finished Jul 05 04:31:19 PM PDT 24
Peak memory 219304 kb
Host smart-2cee7236-14cf-4c26-904a-d5c8980efb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021232882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2021232882
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.733094244
Short name T305
Test name
Test status
Simulation time 844523658 ps
CPU time 10.44 seconds
Started Jul 05 04:30:00 PM PDT 24
Finished Jul 05 04:30:14 PM PDT 24
Peak memory 219252 kb
Host smart-8d76f8c9-babc-4687-b027-054786495e7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=733094244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.733094244
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.141099587
Short name T303
Test name
Test status
Simulation time 60023582995 ps
CPU time 67.16 seconds
Started Jul 05 04:29:55 PM PDT 24
Finished Jul 05 04:31:05 PM PDT 24
Peak memory 215888 kb
Host smart-06b30893-5d2b-4552-af4a-603a6df43ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141099587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.141099587
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.647570600
Short name T257
Test name
Test status
Simulation time 23144211398 ps
CPU time 77.04 seconds
Started Jul 05 04:29:57 PM PDT 24
Finished Jul 05 04:31:17 PM PDT 24
Peak memory 217332 kb
Host smart-1b30c097-038a-48fe-897e-1c9e7bbcfe48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647570600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.647570600
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1613582848
Short name T165
Test name
Test status
Simulation time 167509526 ps
CPU time 8.38 seconds
Started Jul 05 04:30:01 PM PDT 24
Finished Jul 05 04:30:14 PM PDT 24
Peak memory 217288 kb
Host smart-b3dca3a4-4d2d-4102-9345-6a179cfeaf6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613582848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1613582848
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3248031774
Short name T30
Test name
Test status
Simulation time 38242970735 ps
CPU time 430.06 seconds
Started Jul 05 04:30:09 PM PDT 24
Finished Jul 05 04:37:22 PM PDT 24
Peak memory 229620 kb
Host smart-c89d62f1-bf33-41f5-a5d3-765628e6c832
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248031774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3248031774
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2077892174
Short name T348
Test name
Test status
Simulation time 727561527 ps
CPU time 10.3 seconds
Started Jul 05 04:30:08 PM PDT 24
Finished Jul 05 04:30:22 PM PDT 24
Peak memory 219248 kb
Host smart-3e0d8ee1-30cd-4ec4-a5db-8c15624e2bf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2077892174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2077892174
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3165560303
Short name T285
Test name
Test status
Simulation time 5124718110 ps
CPU time 53.34 seconds
Started Jul 05 04:30:08 PM PDT 24
Finished Jul 05 04:31:05 PM PDT 24
Peak memory 216792 kb
Host smart-fbd454b5-8c61-4538-8342-75fac7bb34dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165560303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3165560303
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3871579865
Short name T41
Test name
Test status
Simulation time 5355526760 ps
CPU time 200.73 seconds
Started Jul 05 04:30:12 PM PDT 24
Finished Jul 05 04:33:36 PM PDT 24
Peak memory 227612 kb
Host smart-8d3bedfc-a181-4209-abd1-c2fc8c29d860
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871579865 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.3871579865
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1553599145
Short name T230
Test name
Test status
Simulation time 1832914234 ps
CPU time 8.49 seconds
Started Jul 05 04:29:59 PM PDT 24
Finished Jul 05 04:30:10 PM PDT 24
Peak memory 217052 kb
Host smart-2e192dde-8288-46cc-a38b-9da31c2eb2ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553599145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1553599145
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.832745012
Short name T288
Test name
Test status
Simulation time 30201652840 ps
CPU time 62.43 seconds
Started Jul 05 04:30:01 PM PDT 24
Finished Jul 05 04:31:07 PM PDT 24
Peak memory 219204 kb
Host smart-e1750748-1334-4ecc-8c8e-efe332e7f1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832745012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.832745012
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2919985167
Short name T140
Test name
Test status
Simulation time 5813866103 ps
CPU time 19.9 seconds
Started Jul 05 04:30:08 PM PDT 24
Finished Jul 05 04:30:32 PM PDT 24
Peak memory 219248 kb
Host smart-83b6ed51-34ea-4e03-be55-15909efafc47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2919985167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2919985167
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3519618709
Short name T279
Test name
Test status
Simulation time 4315937079 ps
CPU time 54.64 seconds
Started Jul 05 04:29:55 PM PDT 24
Finished Jul 05 04:30:52 PM PDT 24
Peak memory 216992 kb
Host smart-d99b2327-86a7-496e-8010-8b24ecbb07cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519618709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3519618709
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1681940781
Short name T233
Test name
Test status
Simulation time 385626370 ps
CPU time 31.3 seconds
Started Jul 05 04:29:56 PM PDT 24
Finished Jul 05 04:30:30 PM PDT 24
Peak memory 219228 kb
Host smart-8786914b-ce61-41ea-a900-35de40cce1e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681940781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1681940781
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.2912635727
Short name T349
Test name
Test status
Simulation time 314131702823 ps
CPU time 7845.07 seconds
Started Jul 05 04:29:59 PM PDT 24
Finished Jul 05 06:40:48 PM PDT 24
Peak memory 237028 kb
Host smart-00309467-c107-4870-bfcd-d058701a20d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912635727 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.2912635727
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2743396359
Short name T268
Test name
Test status
Simulation time 10184680190 ps
CPU time 22.36 seconds
Started Jul 05 04:30:10 PM PDT 24
Finished Jul 05 04:30:35 PM PDT 24
Peak memory 217468 kb
Host smart-cbbe62e4-49a9-4ad6-b4ba-03081a7f83f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743396359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2743396359
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2974113733
Short name T266
Test name
Test status
Simulation time 4118457397 ps
CPU time 275.76 seconds
Started Jul 05 04:29:58 PM PDT 24
Finished Jul 05 04:34:36 PM PDT 24
Peak memory 225896 kb
Host smart-2469be57-a00f-47d6-aac2-41fe971219e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974113733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2974113733
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1584089375
Short name T295
Test name
Test status
Simulation time 10528443999 ps
CPU time 29.87 seconds
Started Jul 05 04:30:13 PM PDT 24
Finished Jul 05 04:30:46 PM PDT 24
Peak memory 219268 kb
Host smart-f68b9011-f420-466b-9933-313a66f30b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584089375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1584089375
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.538498700
Short name T156
Test name
Test status
Simulation time 7847629634 ps
CPU time 29.03 seconds
Started Jul 05 04:29:58 PM PDT 24
Finished Jul 05 04:30:29 PM PDT 24
Peak memory 212008 kb
Host smart-2b321bcc-ca65-498f-82a5-940889667266
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=538498700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.538498700
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.3293300820
Short name T206
Test name
Test status
Simulation time 3523501976 ps
CPU time 24.16 seconds
Started Jul 05 04:30:01 PM PDT 24
Finished Jul 05 04:30:30 PM PDT 24
Peak memory 216556 kb
Host smart-9c042cfa-3e79-4a68-b24e-788b6fed2f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293300820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.3293300820
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2732135250
Short name T292
Test name
Test status
Simulation time 10831640892 ps
CPU time 91.47 seconds
Started Jul 05 04:30:08 PM PDT 24
Finished Jul 05 04:31:43 PM PDT 24
Peak memory 218452 kb
Host smart-3186d0df-f884-447b-af2c-7687b167efb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732135250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2732135250
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3247205355
Short name T53
Test name
Test status
Simulation time 419612429 ps
CPU time 11.01 seconds
Started Jul 05 04:29:46 PM PDT 24
Finished Jul 05 04:30:00 PM PDT 24
Peak memory 217152 kb
Host smart-c66676ee-504d-4278-96e2-7ee9085ebced
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247205355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3247205355
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.886658676
Short name T193
Test name
Test status
Simulation time 156764274323 ps
CPU time 975.94 seconds
Started Jul 05 04:29:35 PM PDT 24
Finished Jul 05 04:45:56 PM PDT 24
Peak memory 233640 kb
Host smart-681bfa80-7108-40a0-beb7-1b7ed31fb526
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886658676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.886658676
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2409980859
Short name T321
Test name
Test status
Simulation time 332438571 ps
CPU time 19.03 seconds
Started Jul 05 04:29:35 PM PDT 24
Finished Jul 05 04:29:59 PM PDT 24
Peak memory 219200 kb
Host smart-49c71dc0-a843-439a-b3dc-24d68c22440b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409980859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2409980859
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.344218795
Short name T351
Test name
Test status
Simulation time 3468166471 ps
CPU time 28.12 seconds
Started Jul 05 04:29:43 PM PDT 24
Finished Jul 05 04:30:15 PM PDT 24
Peak memory 219260 kb
Host smart-cfd19bb7-0feb-4934-9093-988531abd293
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=344218795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.344218795
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3428574480
Short name T26
Test name
Test status
Simulation time 7302065756 ps
CPU time 236.86 seconds
Started Jul 05 04:30:13 PM PDT 24
Finished Jul 05 04:34:14 PM PDT 24
Peak memory 236620 kb
Host smart-82d886cf-8223-4ca5-a376-cfe21f914fb0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428574480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3428574480
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.4270949033
Short name T261
Test name
Test status
Simulation time 352113073 ps
CPU time 19.68 seconds
Started Jul 05 04:29:52 PM PDT 24
Finished Jul 05 04:30:13 PM PDT 24
Peak memory 216472 kb
Host smart-48f989e9-5f70-4944-b408-c94adbf67be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270949033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.4270949033
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.4104301811
Short name T189
Test name
Test status
Simulation time 34647268301 ps
CPU time 97.28 seconds
Started Jul 05 04:29:55 PM PDT 24
Finished Jul 05 04:31:34 PM PDT 24
Peak memory 220164 kb
Host smart-d51b21f3-66c5-469c-b549-d2789d20d1a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104301811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.4104301811
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2352956538
Short name T22
Test name
Test status
Simulation time 6717677751 ps
CPU time 22.06 seconds
Started Jul 05 04:30:09 PM PDT 24
Finished Jul 05 04:30:34 PM PDT 24
Peak memory 217364 kb
Host smart-6e8772ff-86ba-4f6d-8f0c-aac717c77acf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352956538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2352956538
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.323586202
Short name T345
Test name
Test status
Simulation time 855601857922 ps
CPU time 622.96 seconds
Started Jul 05 04:29:54 PM PDT 24
Finished Jul 05 04:40:19 PM PDT 24
Peak memory 239604 kb
Host smart-ed7042a9-1729-4cdb-a6f0-4e4de4268f68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323586202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.323586202
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2805345894
Short name T267
Test name
Test status
Simulation time 4226389883 ps
CPU time 28.65 seconds
Started Jul 05 04:29:57 PM PDT 24
Finished Jul 05 04:30:28 PM PDT 24
Peak memory 218644 kb
Host smart-4713bb29-d8df-4e97-b979-ce3c8919c4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805345894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2805345894
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3959187486
Short name T198
Test name
Test status
Simulation time 1346115722 ps
CPU time 18.7 seconds
Started Jul 05 04:30:01 PM PDT 24
Finished Jul 05 04:30:25 PM PDT 24
Peak memory 219248 kb
Host smart-c7afac93-d220-449f-b557-6e26e382b26f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3959187486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3959187486
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3367641187
Short name T14
Test name
Test status
Simulation time 9699565968 ps
CPU time 53.07 seconds
Started Jul 05 04:30:22 PM PDT 24
Finished Jul 05 04:31:26 PM PDT 24
Peak memory 216844 kb
Host smart-5c5efcc0-6d90-4868-84b1-e7d9a81e2936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367641187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3367641187
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3004818801
Short name T357
Test name
Test status
Simulation time 7071456779 ps
CPU time 73.92 seconds
Started Jul 05 04:30:05 PM PDT 24
Finished Jul 05 04:31:23 PM PDT 24
Peak memory 220052 kb
Host smart-f19bbf81-879c-40dd-9f6e-7b1eae3f529e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004818801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3004818801
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2740858763
Short name T181
Test name
Test status
Simulation time 4022783928 ps
CPU time 31.45 seconds
Started Jul 05 04:30:08 PM PDT 24
Finished Jul 05 04:30:43 PM PDT 24
Peak memory 217208 kb
Host smart-2c6890e4-a371-4ade-83df-1117b43536c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740858763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2740858763
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.694949546
Short name T212
Test name
Test status
Simulation time 115637533199 ps
CPU time 1065.37 seconds
Started Jul 05 04:29:57 PM PDT 24
Finished Jul 05 04:47:52 PM PDT 24
Peak memory 230768 kb
Host smart-63ae7461-ab25-41db-b22b-95fd84eae9b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694949546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.694949546
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.4234809316
Short name T275
Test name
Test status
Simulation time 30661138327 ps
CPU time 63.55 seconds
Started Jul 05 04:30:00 PM PDT 24
Finished Jul 05 04:31:07 PM PDT 24
Peak memory 219140 kb
Host smart-db6f3ea7-158d-4bfd-b143-a3263f16d9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234809316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.4234809316
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2915298011
Short name T202
Test name
Test status
Simulation time 187907035 ps
CPU time 10.49 seconds
Started Jul 05 04:30:02 PM PDT 24
Finished Jul 05 04:30:17 PM PDT 24
Peak memory 219180 kb
Host smart-26d9e7d4-732e-4492-b78b-ac2b5eb27613
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2915298011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2915298011
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.921420459
Short name T332
Test name
Test status
Simulation time 1417538615 ps
CPU time 19.29 seconds
Started Jul 05 04:30:10 PM PDT 24
Finished Jul 05 04:30:32 PM PDT 24
Peak memory 216084 kb
Host smart-c4bc5011-9408-42a9-af16-23e91eade1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921420459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.921420459
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2041186405
Short name T344
Test name
Test status
Simulation time 14491307668 ps
CPU time 68.51 seconds
Started Jul 05 04:30:15 PM PDT 24
Finished Jul 05 04:31:27 PM PDT 24
Peak memory 217916 kb
Host smart-77724336-9d2d-4b0f-b222-125f79ef3ea4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041186405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2041186405
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1546104352
Short name T243
Test name
Test status
Simulation time 4069962339 ps
CPU time 19.94 seconds
Started Jul 05 04:30:21 PM PDT 24
Finished Jul 05 04:30:43 PM PDT 24
Peak memory 217092 kb
Host smart-9179e1dd-386b-4460-b7bf-f9588958245e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546104352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1546104352
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.599072629
Short name T208
Test name
Test status
Simulation time 173811592438 ps
CPU time 455.91 seconds
Started Jul 05 04:30:06 PM PDT 24
Finished Jul 05 04:37:47 PM PDT 24
Peak memory 236144 kb
Host smart-bcbb9069-6249-4e75-8ae9-0bb768d4fc1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599072629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.599072629
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3876292637
Short name T317
Test name
Test status
Simulation time 43818639345 ps
CPU time 67.83 seconds
Started Jul 05 04:30:17 PM PDT 24
Finished Jul 05 04:31:28 PM PDT 24
Peak memory 219112 kb
Host smart-1a09bfd2-5fca-44c9-ade1-080f8720341d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876292637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3876292637
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.701387343
Short name T215
Test name
Test status
Simulation time 3410275787 ps
CPU time 29.9 seconds
Started Jul 05 04:30:14 PM PDT 24
Finished Jul 05 04:30:47 PM PDT 24
Peak memory 219340 kb
Host smart-259ae12d-3273-491c-9261-a49d27b9bb6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=701387343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.701387343
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3051534566
Short name T130
Test name
Test status
Simulation time 30013746929 ps
CPU time 58.07 seconds
Started Jul 05 04:30:19 PM PDT 24
Finished Jul 05 04:31:19 PM PDT 24
Peak memory 217332 kb
Host smart-3829a6a2-53b5-4fb8-808b-a1c5f5f69fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051534566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3051534566
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.4138228141
Short name T95
Test name
Test status
Simulation time 27771818522 ps
CPU time 125.74 seconds
Started Jul 05 04:30:25 PM PDT 24
Finished Jul 05 04:32:36 PM PDT 24
Peak memory 220676 kb
Host smart-2c998e1b-883a-4f91-bb08-fc50ce5aa7ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138228141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.4138228141
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.545555728
Short name T180
Test name
Test status
Simulation time 332192503 ps
CPU time 8.33 seconds
Started Jul 05 04:30:10 PM PDT 24
Finished Jul 05 04:30:21 PM PDT 24
Peak memory 217060 kb
Host smart-da585cda-cb81-464b-9634-d57a5961dcc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545555728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.545555728
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1489992378
Short name T166
Test name
Test status
Simulation time 158537159427 ps
CPU time 402.39 seconds
Started Jul 05 04:30:24 PM PDT 24
Finished Jul 05 04:37:12 PM PDT 24
Peak memory 219468 kb
Host smart-f4526c19-53bb-48e0-9f75-a5fe36be95ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489992378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1489992378
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2532068467
Short name T338
Test name
Test status
Simulation time 28007736817 ps
CPU time 32.69 seconds
Started Jul 05 04:30:36 PM PDT 24
Finished Jul 05 04:31:14 PM PDT 24
Peak memory 215564 kb
Host smart-10de3921-ed31-444f-a9b3-ee629fc24667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532068467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2532068467
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1814216554
Short name T246
Test name
Test status
Simulation time 4816160760 ps
CPU time 17.94 seconds
Started Jul 05 04:30:25 PM PDT 24
Finished Jul 05 04:30:49 PM PDT 24
Peak memory 211824 kb
Host smart-f8e14515-937f-4130-b1f5-3bdb650a2431
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1814216554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1814216554
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.1470999828
Short name T123
Test name
Test status
Simulation time 8152453222 ps
CPU time 55.41 seconds
Started Jul 05 04:30:13 PM PDT 24
Finished Jul 05 04:31:12 PM PDT 24
Peak memory 217088 kb
Host smart-112d8eb7-09bf-4316-b9c5-68940d385d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470999828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1470999828
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2685608633
Short name T194
Test name
Test status
Simulation time 386463794 ps
CPU time 31.29 seconds
Started Jul 05 04:30:15 PM PDT 24
Finished Jul 05 04:30:49 PM PDT 24
Peak memory 219252 kb
Host smart-d16ee406-a689-4e0b-a81c-3bc7c30b5b0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685608633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2685608633
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3509539985
Short name T43
Test name
Test status
Simulation time 69064166392 ps
CPU time 734.02 seconds
Started Jul 05 04:30:19 PM PDT 24
Finished Jul 05 04:42:35 PM PDT 24
Peak memory 235688 kb
Host smart-fc19cdba-8688-47ce-977a-54c1492bf8a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509539985 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.3509539985
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.818893621
Short name T333
Test name
Test status
Simulation time 1388156313 ps
CPU time 16.6 seconds
Started Jul 05 04:30:15 PM PDT 24
Finished Jul 05 04:30:35 PM PDT 24
Peak memory 217160 kb
Host smart-565a848a-b3b3-4298-b115-d64c39783eea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818893621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.818893621
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2385605882
Short name T318
Test name
Test status
Simulation time 33673385039 ps
CPU time 260.53 seconds
Started Jul 05 04:30:25 PM PDT 24
Finished Jul 05 04:34:51 PM PDT 24
Peak memory 232852 kb
Host smart-37d13f53-ce40-467a-86d7-c41079f33b7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385605882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2385605882
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1911952459
Short name T209
Test name
Test status
Simulation time 3431323439 ps
CPU time 38.56 seconds
Started Jul 05 04:30:24 PM PDT 24
Finished Jul 05 04:31:08 PM PDT 24
Peak memory 219332 kb
Host smart-0df77a6f-a638-4ab0-8fe6-2d24ababcc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911952459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1911952459
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1663291564
Short name T330
Test name
Test status
Simulation time 4859099155 ps
CPU time 23.75 seconds
Started Jul 05 04:30:17 PM PDT 24
Finished Jul 05 04:30:43 PM PDT 24
Peak memory 219288 kb
Host smart-00a43a1f-42c1-4d31-b42c-18346cafa0fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1663291564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1663291564
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3963348438
Short name T71
Test name
Test status
Simulation time 4159185315 ps
CPU time 27.84 seconds
Started Jul 05 04:30:39 PM PDT 24
Finished Jul 05 04:31:11 PM PDT 24
Peak memory 215788 kb
Host smart-fd0dccdc-5528-46c5-926a-9240718667c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963348438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3963348438
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1113166601
Short name T55
Test name
Test status
Simulation time 2822128186 ps
CPU time 24.01 seconds
Started Jul 05 04:30:06 PM PDT 24
Finished Jul 05 04:30:35 PM PDT 24
Peak memory 217076 kb
Host smart-2b5f561a-6619-4e83-9018-4a1ff444445c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113166601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1113166601
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2490068740
Short name T316
Test name
Test status
Simulation time 15976077526 ps
CPU time 202.14 seconds
Started Jul 05 04:30:07 PM PDT 24
Finished Jul 05 04:33:34 PM PDT 24
Peak memory 216740 kb
Host smart-55d01e46-b79d-4d15-9377-8a263053a174
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490068740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2490068740
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.53607306
Short name T308
Test name
Test status
Simulation time 32710355649 ps
CPU time 62.4 seconds
Started Jul 05 04:29:55 PM PDT 24
Finished Jul 05 04:31:00 PM PDT 24
Peak memory 219268 kb
Host smart-916cd927-bc87-4f36-8de6-e6b9bb78850f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53607306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.53607306
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.690771285
Short name T105
Test name
Test status
Simulation time 178284505 ps
CPU time 10.57 seconds
Started Jul 05 04:30:20 PM PDT 24
Finished Jul 05 04:30:33 PM PDT 24
Peak memory 219212 kb
Host smart-24121d99-ff40-440b-82ef-4e9ece5a7397
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=690771285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.690771285
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.199862233
Short name T237
Test name
Test status
Simulation time 14166101439 ps
CPU time 38.39 seconds
Started Jul 05 04:30:02 PM PDT 24
Finished Jul 05 04:30:46 PM PDT 24
Peak memory 216192 kb
Host smart-e01f5407-566a-4068-8790-7a7b41980031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199862233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.199862233
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1867872177
Short name T322
Test name
Test status
Simulation time 2382337639 ps
CPU time 34.9 seconds
Started Jul 05 04:30:26 PM PDT 24
Finished Jul 05 04:31:07 PM PDT 24
Peak memory 216636 kb
Host smart-c4700504-aff5-4387-9f11-c0ae0a95fdd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867872177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1867872177
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1071310597
Short name T184
Test name
Test status
Simulation time 4214815986 ps
CPU time 32.56 seconds
Started Jul 05 04:30:18 PM PDT 24
Finished Jul 05 04:30:53 PM PDT 24
Peak memory 217096 kb
Host smart-e8460472-42b1-4987-9f22-2e9ee01c7879
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071310597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1071310597
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1184695468
Short name T289
Test name
Test status
Simulation time 83460193064 ps
CPU time 359.7 seconds
Started Jul 05 04:30:25 PM PDT 24
Finished Jul 05 04:36:31 PM PDT 24
Peak memory 219472 kb
Host smart-910b6c84-195a-4a9a-a2f4-22e977a99cc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184695468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1184695468
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1530669283
Short name T339
Test name
Test status
Simulation time 9283402158 ps
CPU time 58.49 seconds
Started Jul 05 04:30:13 PM PDT 24
Finished Jul 05 04:31:14 PM PDT 24
Peak memory 219240 kb
Host smart-e9b2a046-2fcf-41ca-b3ff-86c1aadfd06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530669283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1530669283
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2456315049
Short name T16
Test name
Test status
Simulation time 4955221811 ps
CPU time 25 seconds
Started Jul 05 04:30:20 PM PDT 24
Finished Jul 05 04:30:47 PM PDT 24
Peak memory 217620 kb
Host smart-0f1fd9e4-7b30-4cab-9b02-be4b57345c07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2456315049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2456315049
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3758346627
Short name T8
Test name
Test status
Simulation time 6857862742 ps
CPU time 29.77 seconds
Started Jul 05 04:30:05 PM PDT 24
Finished Jul 05 04:30:39 PM PDT 24
Peak memory 216992 kb
Host smart-11450974-2d96-403d-adff-8b76b685f227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758346627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3758346627
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3577020773
Short name T185
Test name
Test status
Simulation time 366648686 ps
CPU time 15.91 seconds
Started Jul 05 04:30:03 PM PDT 24
Finished Jul 05 04:30:24 PM PDT 24
Peak memory 219196 kb
Host smart-a4c20585-6d82-48db-a071-0222ed935b81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577020773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3577020773
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.3215081755
Short name T46
Test name
Test status
Simulation time 180075191849 ps
CPU time 3545.17 seconds
Started Jul 05 04:30:23 PM PDT 24
Finished Jul 05 05:29:34 PM PDT 24
Peak memory 232832 kb
Host smart-32108e85-8ca7-4ff6-a9e8-20de860bfb05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215081755 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.3215081755
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.911166064
Short name T290
Test name
Test status
Simulation time 4998952244 ps
CPU time 23.74 seconds
Started Jul 05 04:30:23 PM PDT 24
Finished Jul 05 04:30:51 PM PDT 24
Peak memory 217412 kb
Host smart-8362b0d6-44d1-4382-873d-c8910d783ff9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911166064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.911166064
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3448053583
Short name T119
Test name
Test status
Simulation time 16440752860 ps
CPU time 182.58 seconds
Started Jul 05 04:30:11 PM PDT 24
Finished Jul 05 04:33:22 PM PDT 24
Peak memory 228108 kb
Host smart-09b48f9c-951d-493b-930c-df6e5b7dea12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448053583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3448053583
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.4143392130
Short name T168
Test name
Test status
Simulation time 14939000040 ps
CPU time 40.69 seconds
Started Jul 05 04:30:11 PM PDT 24
Finished Jul 05 04:30:55 PM PDT 24
Peak memory 219256 kb
Host smart-f08c049e-6a9e-4513-8473-d30e389d58a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143392130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.4143392130
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.487355689
Short name T353
Test name
Test status
Simulation time 1319827701 ps
CPU time 17.82 seconds
Started Jul 05 04:30:22 PM PDT 24
Finished Jul 05 04:30:45 PM PDT 24
Peak memory 211248 kb
Host smart-34cdf626-4519-462d-a06a-757d2bd87603
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=487355689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.487355689
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.544854845
Short name T74
Test name
Test status
Simulation time 35736119109 ps
CPU time 75.91 seconds
Started Jul 05 04:30:06 PM PDT 24
Finished Jul 05 04:31:26 PM PDT 24
Peak memory 217016 kb
Host smart-963d2c43-7d67-4de1-9856-01521576ac12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544854845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.544854845
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2959684006
Short name T253
Test name
Test status
Simulation time 8059049132 ps
CPU time 85.73 seconds
Started Jul 05 04:30:02 PM PDT 24
Finished Jul 05 04:31:33 PM PDT 24
Peak memory 219296 kb
Host smart-8127fe22-53d0-43df-8684-5c3524f828ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959684006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2959684006
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.530456139
Short name T11
Test name
Test status
Simulation time 100862833627 ps
CPU time 1927.26 seconds
Started Jul 05 04:30:24 PM PDT 24
Finished Jul 05 05:02:37 PM PDT 24
Peak memory 243972 kb
Host smart-05208c3a-6ee7-415e-922e-b974ba870a45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530456139 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.530456139
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1169762712
Short name T169
Test name
Test status
Simulation time 174213332 ps
CPU time 8.62 seconds
Started Jul 05 04:30:21 PM PDT 24
Finished Jul 05 04:30:31 PM PDT 24
Peak memory 217116 kb
Host smart-74d8086a-ccbd-460f-8f0a-26d8b45be5cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169762712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1169762712
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.229047026
Short name T277
Test name
Test status
Simulation time 32144518807 ps
CPU time 235.03 seconds
Started Jul 05 04:30:27 PM PDT 24
Finished Jul 05 04:34:28 PM PDT 24
Peak memory 241768 kb
Host smart-b65300f7-52cf-41e4-ba13-b75d54e9aaed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229047026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.229047026
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.4284425155
Short name T122
Test name
Test status
Simulation time 7006321986 ps
CPU time 57.24 seconds
Started Jul 05 04:30:31 PM PDT 24
Finished Jul 05 04:31:33 PM PDT 24
Peak memory 219268 kb
Host smart-5df04c77-5359-4f11-8fbb-f90bdee3938f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284425155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.4284425155
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1719327386
Short name T125
Test name
Test status
Simulation time 357130276 ps
CPU time 9.9 seconds
Started Jul 05 04:30:56 PM PDT 24
Finished Jul 05 04:31:08 PM PDT 24
Peak memory 219180 kb
Host smart-8f130495-5ab7-4665-8ec9-f122e740ae1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1719327386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1719327386
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3243153340
Short name T69
Test name
Test status
Simulation time 6504284636 ps
CPU time 61.27 seconds
Started Jul 05 04:30:22 PM PDT 24
Finished Jul 05 04:31:26 PM PDT 24
Peak memory 216884 kb
Host smart-85a995ab-b013-4268-b899-4c7fe59870fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243153340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3243153340
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.435441927
Short name T311
Test name
Test status
Simulation time 7370308027 ps
CPU time 33.08 seconds
Started Jul 05 04:30:13 PM PDT 24
Finished Jul 05 04:30:49 PM PDT 24
Peak memory 214720 kb
Host smart-66b20008-cb75-4cb6-a684-a08e315a10a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435441927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.435441927
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2168905036
Short name T276
Test name
Test status
Simulation time 1027261801 ps
CPU time 14.76 seconds
Started Jul 05 04:30:36 PM PDT 24
Finished Jul 05 04:30:56 PM PDT 24
Peak memory 217004 kb
Host smart-a88f9b67-86d1-4093-b0b2-54c5589024b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168905036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2168905036
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2052135148
Short name T217
Test name
Test status
Simulation time 14372058951 ps
CPU time 271.54 seconds
Started Jul 05 04:30:12 PM PDT 24
Finished Jul 05 04:34:47 PM PDT 24
Peak memory 229724 kb
Host smart-94f7f5d1-48f4-4d16-9f71-c364a3282f35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052135148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2052135148
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.75476004
Short name T135
Test name
Test status
Simulation time 4647385479 ps
CPU time 46.13 seconds
Started Jul 05 04:30:20 PM PDT 24
Finished Jul 05 04:31:08 PM PDT 24
Peak memory 219236 kb
Host smart-0c2813ec-bca2-435a-923d-8da6736ebc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75476004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.75476004
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1674079390
Short name T144
Test name
Test status
Simulation time 45264729518 ps
CPU time 32.38 seconds
Started Jul 05 04:30:22 PM PDT 24
Finished Jul 05 04:30:58 PM PDT 24
Peak memory 211840 kb
Host smart-238936ce-0e47-43b3-bd10-31b39ae64e7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1674079390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1674079390
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.73671319
Short name T256
Test name
Test status
Simulation time 704071933 ps
CPU time 19.65 seconds
Started Jul 05 04:30:15 PM PDT 24
Finished Jul 05 04:30:37 PM PDT 24
Peak memory 216084 kb
Host smart-06f83aff-86bb-4812-b715-c5b968b71f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73671319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.73671319
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3491289291
Short name T176
Test name
Test status
Simulation time 22233760336 ps
CPU time 93.8 seconds
Started Jul 05 04:30:38 PM PDT 24
Finished Jul 05 04:32:16 PM PDT 24
Peak memory 219876 kb
Host smart-f8bf63f6-f601-4c06-b8ef-85ba11b59bff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491289291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3491289291
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1206829462
Short name T170
Test name
Test status
Simulation time 2640087717 ps
CPU time 22.99 seconds
Started Jul 05 04:29:46 PM PDT 24
Finished Jul 05 04:30:12 PM PDT 24
Peak memory 217228 kb
Host smart-af18fae1-1805-4c15-b7df-f880ad5b8696
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206829462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1206829462
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.304421767
Short name T218
Test name
Test status
Simulation time 14103020393 ps
CPU time 317.43 seconds
Started Jul 05 04:29:39 PM PDT 24
Finished Jul 05 04:35:00 PM PDT 24
Peak memory 240320 kb
Host smart-e1b0c50a-92de-4b4b-8af5-67a214d4a9c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304421767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.304421767
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1939389951
Short name T191
Test name
Test status
Simulation time 7477575425 ps
CPU time 60.33 seconds
Started Jul 05 04:29:49 PM PDT 24
Finished Jul 05 04:30:51 PM PDT 24
Peak memory 219244 kb
Host smart-f6bd58dc-2640-4a02-b27d-25903bba2d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939389951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1939389951
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3408675618
Short name T263
Test name
Test status
Simulation time 6603568142 ps
CPU time 29.17 seconds
Started Jul 05 04:29:39 PM PDT 24
Finished Jul 05 04:30:12 PM PDT 24
Peak memory 211592 kb
Host smart-88626920-91fd-4fae-b0a6-1616c306f2af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3408675618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3408675618
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2002550331
Short name T228
Test name
Test status
Simulation time 50672481787 ps
CPU time 60.14 seconds
Started Jul 05 04:29:36 PM PDT 24
Finished Jul 05 04:30:41 PM PDT 24
Peak memory 216504 kb
Host smart-9c7a7161-04a2-4714-bb13-e187b30edf54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002550331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2002550331
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.995797127
Short name T223
Test name
Test status
Simulation time 205872208 ps
CPU time 14.66 seconds
Started Jul 05 04:29:51 PM PDT 24
Finished Jul 05 04:30:13 PM PDT 24
Peak memory 219208 kb
Host smart-b7294de0-59b4-4c8b-a6a7-9324440739fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995797127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.995797127
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2952246254
Short name T186
Test name
Test status
Simulation time 3972318996 ps
CPU time 30.06 seconds
Started Jul 05 04:29:28 PM PDT 24
Finished Jul 05 04:30:05 PM PDT 24
Peak memory 217060 kb
Host smart-61d2270d-52a1-4f5e-80bf-93b21a066031
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952246254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2952246254
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.4111690386
Short name T314
Test name
Test status
Simulation time 104438003097 ps
CPU time 549 seconds
Started Jul 05 04:29:21 PM PDT 24
Finished Jul 05 04:38:39 PM PDT 24
Peak memory 225992 kb
Host smart-912886ae-5857-448e-8b56-b105f80c39ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111690386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.4111690386
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2704184440
Short name T252
Test name
Test status
Simulation time 59124648011 ps
CPU time 55.08 seconds
Started Jul 05 04:29:31 PM PDT 24
Finished Jul 05 04:30:33 PM PDT 24
Peak memory 219252 kb
Host smart-0401e82d-f2e4-4e57-9191-6ba2d6caf56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704184440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2704184440
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.4066744336
Short name T221
Test name
Test status
Simulation time 4016641600 ps
CPU time 31.99 seconds
Started Jul 05 04:29:46 PM PDT 24
Finished Jul 05 04:30:21 PM PDT 24
Peak memory 211604 kb
Host smart-2051603d-68be-4c7b-adb5-fec083b3235f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4066744336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.4066744336
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.81217086
Short name T214
Test name
Test status
Simulation time 6718133009 ps
CPU time 19.68 seconds
Started Jul 05 04:29:33 PM PDT 24
Finished Jul 05 04:29:58 PM PDT 24
Peak memory 217108 kb
Host smart-6e6966ae-8197-446d-ae8f-355df657fac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81217086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.81217086
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1453497551
Short name T128
Test name
Test status
Simulation time 13977128795 ps
CPU time 85.39 seconds
Started Jul 05 04:29:36 PM PDT 24
Finished Jul 05 04:31:06 PM PDT 24
Peak memory 227436 kb
Host smart-240e7fe6-bdc6-4c41-86bf-0126c702157f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453497551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1453497551
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3155247031
Short name T160
Test name
Test status
Simulation time 286523174 ps
CPU time 8.19 seconds
Started Jul 05 04:29:42 PM PDT 24
Finished Jul 05 04:29:54 PM PDT 24
Peak memory 217076 kb
Host smart-de833140-5ec0-46a8-b816-20b3e9b9636a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155247031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3155247031
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1223439933
Short name T293
Test name
Test status
Simulation time 125509600335 ps
CPU time 571.32 seconds
Started Jul 05 04:29:46 PM PDT 24
Finished Jul 05 04:39:20 PM PDT 24
Peak memory 216792 kb
Host smart-4255da84-bebc-4507-9247-5599d425f864
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223439933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1223439933
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.190934352
Short name T90
Test name
Test status
Simulation time 8467918049 ps
CPU time 67.94 seconds
Started Jul 05 04:29:33 PM PDT 24
Finished Jul 05 04:30:47 PM PDT 24
Peak memory 219028 kb
Host smart-e890b209-946a-4621-8c07-4c6877702872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190934352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.190934352
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3919520808
Short name T187
Test name
Test status
Simulation time 977400286 ps
CPU time 10.47 seconds
Started Jul 05 04:30:13 PM PDT 24
Finished Jul 05 04:30:28 PM PDT 24
Peak memory 217936 kb
Host smart-cc1cc08d-02bb-402a-a8bf-24ef25685c6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3919520808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3919520808
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1236789059
Short name T207
Test name
Test status
Simulation time 4678528210 ps
CPU time 46.05 seconds
Started Jul 05 04:29:52 PM PDT 24
Finished Jul 05 04:30:40 PM PDT 24
Peak memory 216448 kb
Host smart-319f74a8-9309-4748-bf4c-f0f571656b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236789059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1236789059
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.431169066
Short name T262
Test name
Test status
Simulation time 8497205574 ps
CPU time 19.83 seconds
Started Jul 05 04:29:34 PM PDT 24
Finished Jul 05 04:29:59 PM PDT 24
Peak memory 213168 kb
Host smart-f31f920b-2519-4d1f-b947-b08463b2c97d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431169066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.431169066
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.933658732
Short name T132
Test name
Test status
Simulation time 17660297247 ps
CPU time 43.57 seconds
Started Jul 05 04:30:34 PM PDT 24
Finished Jul 05 04:31:22 PM PDT 24
Peak memory 219240 kb
Host smart-1982c546-317e-4785-9581-d71faf0a16ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933658732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.933658732
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3926581048
Short name T131
Test name
Test status
Simulation time 769957666 ps
CPU time 10.61 seconds
Started Jul 05 04:29:27 PM PDT 24
Finished Jul 05 04:29:46 PM PDT 24
Peak memory 219180 kb
Host smart-552e32af-1422-4ba6-a690-2aefa7b87b0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3926581048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3926581048
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2420762011
Short name T272
Test name
Test status
Simulation time 1524872934 ps
CPU time 32.94 seconds
Started Jul 05 04:29:40 PM PDT 24
Finished Jul 05 04:30:16 PM PDT 24
Peak memory 216252 kb
Host smart-75f9d587-8ce1-4ac9-8777-da0df1e3fa2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420762011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2420762011
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.4100926895
Short name T72
Test name
Test status
Simulation time 22691170297 ps
CPU time 40.06 seconds
Started Jul 05 04:30:44 PM PDT 24
Finished Jul 05 04:31:25 PM PDT 24
Peak memory 214484 kb
Host smart-99e3d330-e1b2-4ff3-8956-7eeb8cc64ce5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100926895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.4100926895
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3442590263
Short name T182
Test name
Test status
Simulation time 6701338921 ps
CPU time 20.32 seconds
Started Jul 05 04:29:50 PM PDT 24
Finished Jul 05 04:30:12 PM PDT 24
Peak memory 217348 kb
Host smart-f4f88694-fec3-4127-8471-bce019bb1f4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442590263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3442590263
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3352981522
Short name T216
Test name
Test status
Simulation time 17482444565 ps
CPU time 237.75 seconds
Started Jul 05 04:29:40 PM PDT 24
Finished Jul 05 04:33:40 PM PDT 24
Peak memory 234804 kb
Host smart-a4c54b83-6072-4c9e-a1b2-49d1fc697c08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352981522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3352981522
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3017406527
Short name T34
Test name
Test status
Simulation time 342749702 ps
CPU time 18.78 seconds
Started Jul 05 04:29:46 PM PDT 24
Finished Jul 05 04:30:08 PM PDT 24
Peak memory 219200 kb
Host smart-2ee2430d-58eb-4e82-8e18-146211e075d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017406527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3017406527
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.837310850
Short name T312
Test name
Test status
Simulation time 345382281 ps
CPU time 12.59 seconds
Started Jul 05 04:29:46 PM PDT 24
Finished Jul 05 04:30:02 PM PDT 24
Peak memory 211004 kb
Host smart-8cc1713f-0a03-44dd-9ece-48cd6ba4c44c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=837310850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.837310850
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1524244964
Short name T227
Test name
Test status
Simulation time 2068360716 ps
CPU time 32.34 seconds
Started Jul 05 04:29:41 PM PDT 24
Finished Jul 05 04:30:16 PM PDT 24
Peak memory 217980 kb
Host smart-2047f558-aab5-4caa-93af-1cf324ca9774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524244964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1524244964
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3707868196
Short name T58
Test name
Test status
Simulation time 16110193127 ps
CPU time 87.63 seconds
Started Jul 05 04:29:46 PM PDT 24
Finished Jul 05 04:31:17 PM PDT 24
Peak memory 219244 kb
Host smart-3843c362-ba1a-4649-8b7c-64047e1d0d64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707868196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3707868196
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.813230234
Short name T40
Test name
Test status
Simulation time 17593744228 ps
CPU time 628.86 seconds
Started Jul 05 04:29:37 PM PDT 24
Finished Jul 05 04:40:10 PM PDT 24
Peak memory 228476 kb
Host smart-5e9f0054-8505-4dd4-99cb-9536b9a47637
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813230234 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.813230234
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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