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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.21 96.89 91.99 97.68 100.00 98.28 97.30 98.37


Total test records in report: 452
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T306 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2869054397 Jul 06 05:35:59 PM PDT 24 Jul 06 05:39:05 PM PDT 24 11124018988 ps
T307 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2195133171 Jul 06 05:34:21 PM PDT 24 Jul 06 05:34:54 PM PDT 24 24376566974 ps
T308 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3331448131 Jul 06 05:33:41 PM PDT 24 Jul 06 05:36:09 PM PDT 24 29413692465 ps
T309 /workspace/coverage/default/43.rom_ctrl_stress_all.111138870 Jul 06 05:35:42 PM PDT 24 Jul 06 05:40:03 PM PDT 24 32777996839 ps
T310 /workspace/coverage/default/28.rom_ctrl_smoke.189683500 Jul 06 05:34:54 PM PDT 24 Jul 06 05:35:28 PM PDT 24 8920251877 ps
T311 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1951115149 Jul 06 05:34:05 PM PDT 24 Jul 06 05:35:00 PM PDT 24 24028738650 ps
T312 /workspace/coverage/default/49.rom_ctrl_alert_test.3994668983 Jul 06 05:36:11 PM PDT 24 Jul 06 05:36:19 PM PDT 24 661454392 ps
T313 /workspace/coverage/default/48.rom_ctrl_alert_test.455833362 Jul 06 05:36:05 PM PDT 24 Jul 06 05:36:21 PM PDT 24 2374371159 ps
T314 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3436029461 Jul 06 05:34:42 PM PDT 24 Jul 06 05:35:45 PM PDT 24 26796081716 ps
T315 /workspace/coverage/default/34.rom_ctrl_smoke.796075348 Jul 06 05:35:10 PM PDT 24 Jul 06 05:36:18 PM PDT 24 29578006235 ps
T316 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3231503798 Jul 06 05:33:27 PM PDT 24 Jul 06 05:33:38 PM PDT 24 1100744964 ps
T317 /workspace/coverage/default/18.rom_ctrl_alert_test.1484615979 Jul 06 05:34:17 PM PDT 24 Jul 06 05:34:25 PM PDT 24 174492309 ps
T318 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2772584128 Jul 06 05:35:39 PM PDT 24 Jul 06 05:36:12 PM PDT 24 14494003043 ps
T319 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3971973268 Jul 06 05:34:11 PM PDT 24 Jul 06 05:34:31 PM PDT 24 448108270 ps
T320 /workspace/coverage/default/29.rom_ctrl_smoke.3298646236 Jul 06 05:34:54 PM PDT 24 Jul 06 05:36:30 PM PDT 24 8847460640 ps
T321 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2258393953 Jul 06 05:35:30 PM PDT 24 Jul 06 05:36:22 PM PDT 24 11415056791 ps
T48 /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.689028034 Jul 06 05:33:59 PM PDT 24 Jul 06 06:10:12 PM PDT 24 226310403254 ps
T322 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3541191965 Jul 06 05:33:10 PM PDT 24 Jul 06 05:33:49 PM PDT 24 12121205165 ps
T323 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2299054222 Jul 06 05:34:54 PM PDT 24 Jul 06 05:41:02 PM PDT 24 181830061251 ps
T324 /workspace/coverage/default/36.rom_ctrl_alert_test.2563789284 Jul 06 05:35:22 PM PDT 24 Jul 06 05:35:38 PM PDT 24 1236861007 ps
T325 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1925239361 Jul 06 05:33:25 PM PDT 24 Jul 06 05:44:16 PM PDT 24 69639353893 ps
T326 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.891821846 Jul 06 05:33:52 PM PDT 24 Jul 06 05:34:16 PM PDT 24 2401615250 ps
T327 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.854692022 Jul 06 05:33:16 PM PDT 24 Jul 06 05:39:51 PM PDT 24 408520033624 ps
T328 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.929619453 Jul 06 05:36:01 PM PDT 24 Jul 06 05:36:39 PM PDT 24 3038891240 ps
T329 /workspace/coverage/default/46.rom_ctrl_stress_all.4116360758 Jul 06 05:36:00 PM PDT 24 Jul 06 05:36:57 PM PDT 24 4613446512 ps
T13 /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.3996575308 Jul 06 05:34:21 PM PDT 24 Jul 06 06:01:10 PM PDT 24 26686136438 ps
T330 /workspace/coverage/default/40.rom_ctrl_smoke.2826097598 Jul 06 05:35:32 PM PDT 24 Jul 06 05:37:09 PM PDT 24 8621526975 ps
T331 /workspace/coverage/default/12.rom_ctrl_stress_all.1183958274 Jul 06 05:33:54 PM PDT 24 Jul 06 05:35:30 PM PDT 24 10580307718 ps
T332 /workspace/coverage/default/23.rom_ctrl_stress_all.1805690954 Jul 06 05:34:32 PM PDT 24 Jul 06 05:35:35 PM PDT 24 4149594508 ps
T333 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.673263367 Jul 06 05:34:12 PM PDT 24 Jul 06 05:34:36 PM PDT 24 2428237233 ps
T334 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1090875711 Jul 06 05:35:25 PM PDT 24 Jul 06 05:36:15 PM PDT 24 5473845940 ps
T335 /workspace/coverage/default/39.rom_ctrl_alert_test.2362744343 Jul 06 05:35:31 PM PDT 24 Jul 06 05:35:57 PM PDT 24 6395793816 ps
T336 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.4176652093 Jul 06 05:34:47 PM PDT 24 Jul 06 05:34:59 PM PDT 24 1405093545 ps
T337 /workspace/coverage/default/14.rom_ctrl_stress_all.3905893144 Jul 06 05:34:04 PM PDT 24 Jul 06 05:37:38 PM PDT 24 22465924742 ps
T338 /workspace/coverage/default/25.rom_ctrl_stress_all.1879473545 Jul 06 05:34:38 PM PDT 24 Jul 06 05:35:20 PM PDT 24 1260030907 ps
T339 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.4141614266 Jul 06 05:34:53 PM PDT 24 Jul 06 05:35:39 PM PDT 24 5359846399 ps
T340 /workspace/coverage/default/35.rom_ctrl_stress_all.1451808091 Jul 06 05:35:16 PM PDT 24 Jul 06 05:36:01 PM PDT 24 2884658277 ps
T341 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1343619811 Jul 06 05:35:29 PM PDT 24 Jul 06 05:35:58 PM PDT 24 21855771568 ps
T342 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.140732672 Jul 06 05:34:04 PM PDT 24 Jul 06 05:34:24 PM PDT 24 332764077 ps
T343 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2461745309 Jul 06 05:35:49 PM PDT 24 Jul 06 05:36:13 PM PDT 24 14803445590 ps
T344 /workspace/coverage/default/32.rom_ctrl_smoke.634152838 Jul 06 05:35:06 PM PDT 24 Jul 06 05:35:27 PM PDT 24 1430535665 ps
T345 /workspace/coverage/default/7.rom_ctrl_stress_all.3288630193 Jul 06 05:33:39 PM PDT 24 Jul 06 05:34:29 PM PDT 24 2381279195 ps
T346 /workspace/coverage/default/38.rom_ctrl_smoke.2368369734 Jul 06 05:35:27 PM PDT 24 Jul 06 05:36:30 PM PDT 24 21644553961 ps
T347 /workspace/coverage/default/30.rom_ctrl_alert_test.3297966087 Jul 06 05:35:00 PM PDT 24 Jul 06 05:35:21 PM PDT 24 2131566189 ps
T348 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3894523772 Jul 06 05:35:07 PM PDT 24 Jul 06 05:35:27 PM PDT 24 335794814 ps
T349 /workspace/coverage/default/47.rom_ctrl_smoke.2292368881 Jul 06 05:35:58 PM PDT 24 Jul 06 05:36:37 PM PDT 24 2840953766 ps
T350 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2043675033 Jul 06 05:34:27 PM PDT 24 Jul 06 05:34:54 PM PDT 24 5041167057 ps
T351 /workspace/coverage/default/30.rom_ctrl_stress_all.1437788203 Jul 06 05:34:59 PM PDT 24 Jul 06 05:36:17 PM PDT 24 53598432231 ps
T352 /workspace/coverage/default/10.rom_ctrl_smoke.2739472806 Jul 06 05:33:46 PM PDT 24 Jul 06 05:34:13 PM PDT 24 3800791365 ps
T353 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2735104261 Jul 06 05:33:47 PM PDT 24 Jul 06 05:34:17 PM PDT 24 5457212469 ps
T354 /workspace/coverage/default/21.rom_ctrl_stress_all.468310374 Jul 06 05:34:21 PM PDT 24 Jul 06 05:36:53 PM PDT 24 25169172448 ps
T355 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.755564501 Jul 06 05:33:46 PM PDT 24 Jul 06 05:34:08 PM PDT 24 3650869994 ps
T356 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.697007820 Jul 06 05:33:47 PM PDT 24 Jul 06 05:34:42 PM PDT 24 24438986538 ps
T27 /workspace/coverage/default/2.rom_ctrl_sec_cm.834358405 Jul 06 05:33:17 PM PDT 24 Jul 06 05:35:16 PM PDT 24 303401374 ps
T357 /workspace/coverage/default/35.rom_ctrl_smoke.2502248095 Jul 06 05:35:16 PM PDT 24 Jul 06 05:35:38 PM PDT 24 1436996121 ps
T358 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2515997385 Jul 06 05:35:10 PM PDT 24 Jul 06 05:40:53 PM PDT 24 29074027309 ps
T359 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3378432890 Jul 06 05:34:15 PM PDT 24 Jul 06 05:35:20 PM PDT 24 119957992981 ps
T360 /workspace/coverage/default/13.rom_ctrl_alert_test.1005391949 Jul 06 05:34:05 PM PDT 24 Jul 06 05:34:13 PM PDT 24 174678327 ps
T49 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2669609215 Jul 06 04:41:55 PM PDT 24 Jul 06 04:42:16 PM PDT 24 2089118636 ps
T50 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2644495296 Jul 06 04:42:01 PM PDT 24 Jul 06 04:44:55 PM PDT 24 7701635224 ps
T55 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1333830384 Jul 06 04:41:42 PM PDT 24 Jul 06 04:41:51 PM PDT 24 174272509 ps
T51 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1161865611 Jul 06 04:41:39 PM PDT 24 Jul 06 04:42:05 PM PDT 24 9838617146 ps
T52 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1420504725 Jul 06 04:41:54 PM PDT 24 Jul 06 04:42:21 PM PDT 24 14638474921 ps
T62 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.569064201 Jul 06 04:42:29 PM PDT 24 Jul 06 04:44:43 PM PDT 24 13241497580 ps
T361 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1541874657 Jul 06 04:41:39 PM PDT 24 Jul 06 04:41:58 PM PDT 24 7437102883 ps
T61 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2844895372 Jul 06 04:41:52 PM PDT 24 Jul 06 04:42:20 PM PDT 24 10617643241 ps
T98 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1099920086 Jul 06 04:41:40 PM PDT 24 Jul 06 04:42:09 PM PDT 24 3365888982 ps
T53 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2472709550 Jul 06 04:41:53 PM PDT 24 Jul 06 04:43:26 PM PDT 24 7770909952 ps
T362 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1991299971 Jul 06 04:41:47 PM PDT 24 Jul 06 04:42:16 PM PDT 24 3671719813 ps
T363 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.191705010 Jul 06 04:41:46 PM PDT 24 Jul 06 04:41:59 PM PDT 24 174434685 ps
T364 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3922293129 Jul 06 04:42:03 PM PDT 24 Jul 06 04:42:20 PM PDT 24 6010683663 ps
T63 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3548141734 Jul 06 04:41:41 PM PDT 24 Jul 06 04:42:38 PM PDT 24 1067707254 ps
T365 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1065574659 Jul 06 04:41:54 PM PDT 24 Jul 06 04:42:08 PM PDT 24 4100254097 ps
T64 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1536635673 Jul 06 04:41:54 PM PDT 24 Jul 06 04:42:24 PM PDT 24 3681124129 ps
T366 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.522729325 Jul 06 04:41:51 PM PDT 24 Jul 06 04:42:00 PM PDT 24 174239816 ps
T367 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1772444926 Jul 06 04:41:44 PM PDT 24 Jul 06 04:41:54 PM PDT 24 768635329 ps
T99 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2251443952 Jul 06 04:41:44 PM PDT 24 Jul 06 04:41:53 PM PDT 24 174381176 ps
T65 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2807617342 Jul 06 04:41:47 PM PDT 24 Jul 06 04:41:56 PM PDT 24 174373613 ps
T368 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3343354220 Jul 06 04:41:39 PM PDT 24 Jul 06 04:42:06 PM PDT 24 3250260655 ps
T66 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2981018899 Jul 06 04:41:39 PM PDT 24 Jul 06 04:41:48 PM PDT 24 167597106 ps
T67 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.848587314 Jul 06 04:41:54 PM PDT 24 Jul 06 04:43:14 PM PDT 24 66023445458 ps
T369 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2272178972 Jul 06 04:41:40 PM PDT 24 Jul 06 04:42:04 PM PDT 24 9252229327 ps
T92 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.720692408 Jul 06 04:41:47 PM PDT 24 Jul 06 04:42:01 PM PDT 24 2935920419 ps
T68 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.376729980 Jul 06 04:41:54 PM PDT 24 Jul 06 04:42:02 PM PDT 24 377035698 ps
T69 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.803441730 Jul 06 04:41:40 PM PDT 24 Jul 06 04:44:56 PM PDT 24 26105754188 ps
T370 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2448616906 Jul 06 04:41:41 PM PDT 24 Jul 06 04:42:13 PM PDT 24 16256476477 ps
T54 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3779784783 Jul 06 04:41:54 PM PDT 24 Jul 06 04:44:42 PM PDT 24 5848173167 ps
T70 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2235377982 Jul 06 04:41:53 PM PDT 24 Jul 06 04:42:02 PM PDT 24 167319501 ps
T371 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2294353655 Jul 06 04:41:54 PM PDT 24 Jul 06 04:42:17 PM PDT 24 3258546190 ps
T71 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3615786770 Jul 06 04:41:47 PM PDT 24 Jul 06 04:44:36 PM PDT 24 127249449622 ps
T372 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3461283997 Jul 06 04:41:44 PM PDT 24 Jul 06 04:41:57 PM PDT 24 2300185082 ps
T83 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.4055885541 Jul 06 04:41:43 PM PDT 24 Jul 06 04:42:09 PM PDT 24 7055185904 ps
T373 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2062259428 Jul 06 04:41:44 PM PDT 24 Jul 06 04:42:11 PM PDT 24 12748772961 ps
T374 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.44409383 Jul 06 04:41:57 PM PDT 24 Jul 06 04:42:20 PM PDT 24 10348384480 ps
T375 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2007988805 Jul 06 04:42:01 PM PDT 24 Jul 06 04:42:10 PM PDT 24 758410389 ps
T93 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3121718129 Jul 06 04:41:58 PM PDT 24 Jul 06 04:42:26 PM PDT 24 13382429058 ps
T76 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.998304983 Jul 06 04:41:54 PM PDT 24 Jul 06 04:42:10 PM PDT 24 346736287 ps
T376 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.472329074 Jul 06 04:41:54 PM PDT 24 Jul 06 04:42:18 PM PDT 24 2086878453 ps
T77 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3054267628 Jul 06 04:41:45 PM PDT 24 Jul 06 04:43:05 PM PDT 24 6587641032 ps
T78 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2524602164 Jul 06 04:41:43 PM PDT 24 Jul 06 04:44:01 PM PDT 24 73555596507 ps
T377 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.284378203 Jul 06 04:41:44 PM PDT 24 Jul 06 04:41:59 PM PDT 24 1025927054 ps
T378 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1375879332 Jul 06 04:41:43 PM PDT 24 Jul 06 04:41:56 PM PDT 24 684096130 ps
T379 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2180090499 Jul 06 04:41:57 PM PDT 24 Jul 06 04:42:24 PM PDT 24 12721110900 ps
T106 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2948939362 Jul 06 04:42:10 PM PDT 24 Jul 06 04:43:41 PM PDT 24 8090818281 ps
T94 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1379284428 Jul 06 04:41:55 PM PDT 24 Jul 06 04:42:25 PM PDT 24 33571561690 ps
T380 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1179386623 Jul 06 04:41:54 PM PDT 24 Jul 06 04:42:15 PM PDT 24 2136575396 ps
T381 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.873295717 Jul 06 04:41:41 PM PDT 24 Jul 06 04:42:13 PM PDT 24 3766156821 ps
T382 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2911765177 Jul 06 04:41:38 PM PDT 24 Jul 06 04:41:56 PM PDT 24 1481180424 ps
T383 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1401628118 Jul 06 04:41:46 PM PDT 24 Jul 06 04:42:12 PM PDT 24 9203401800 ps
T95 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1398735844 Jul 06 04:41:51 PM PDT 24 Jul 06 04:42:22 PM PDT 24 3875821643 ps
T111 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2054310246 Jul 06 04:41:50 PM PDT 24 Jul 06 04:43:11 PM PDT 24 898946133 ps
T96 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1031320607 Jul 06 04:41:44 PM PDT 24 Jul 06 04:42:11 PM PDT 24 16931009997 ps
T107 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1810502869 Jul 06 04:41:56 PM PDT 24 Jul 06 04:44:48 PM PDT 24 12820496131 ps
T384 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2888762975 Jul 06 04:41:39 PM PDT 24 Jul 06 04:41:48 PM PDT 24 169291280 ps
T385 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4208455210 Jul 06 04:41:41 PM PDT 24 Jul 06 04:41:58 PM PDT 24 1397231409 ps
T386 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3591833258 Jul 06 04:41:39 PM PDT 24 Jul 06 04:42:06 PM PDT 24 12964072221 ps
T387 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.4294366465 Jul 06 04:42:03 PM PDT 24 Jul 06 04:42:11 PM PDT 24 196746720 ps
T388 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3374047743 Jul 06 04:41:47 PM PDT 24 Jul 06 04:42:23 PM PDT 24 7381578109 ps
T97 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2949348492 Jul 06 04:41:47 PM PDT 24 Jul 06 04:41:56 PM PDT 24 167324692 ps
T389 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2815935512 Jul 06 04:41:50 PM PDT 24 Jul 06 04:43:24 PM PDT 24 9292495282 ps
T390 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2996663465 Jul 06 04:41:45 PM PDT 24 Jul 06 04:43:56 PM PDT 24 15118457102 ps
T391 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3557064020 Jul 06 04:41:41 PM PDT 24 Jul 06 04:42:10 PM PDT 24 3747442126 ps
T392 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1258632506 Jul 06 04:41:47 PM PDT 24 Jul 06 04:42:04 PM PDT 24 5500771244 ps
T393 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1273225598 Jul 06 04:41:42 PM PDT 24 Jul 06 04:42:16 PM PDT 24 3957672790 ps
T394 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4243644941 Jul 06 04:41:54 PM PDT 24 Jul 06 04:42:05 PM PDT 24 294995378 ps
T79 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1726551754 Jul 06 04:41:51 PM PDT 24 Jul 06 04:44:05 PM PDT 24 69579358797 ps
T395 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1252507015 Jul 06 04:41:45 PM PDT 24 Jul 06 04:42:08 PM PDT 24 19579901791 ps
T396 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.504927596 Jul 06 04:41:54 PM PDT 24 Jul 06 04:42:17 PM PDT 24 1948792765 ps
T109 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2266423013 Jul 06 04:41:45 PM PDT 24 Jul 06 04:43:14 PM PDT 24 1439264202 ps
T80 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1290584796 Jul 06 04:41:52 PM PDT 24 Jul 06 04:42:00 PM PDT 24 345601653 ps
T110 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3195896468 Jul 06 04:41:46 PM PDT 24 Jul 06 04:44:34 PM PDT 24 2617211073 ps
T397 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2576294450 Jul 06 04:41:53 PM PDT 24 Jul 06 04:42:20 PM PDT 24 3341193707 ps
T398 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3515533076 Jul 06 04:41:54 PM PDT 24 Jul 06 04:42:27 PM PDT 24 4031527843 ps
T399 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2477555597 Jul 06 04:41:39 PM PDT 24 Jul 06 04:42:05 PM PDT 24 8984798230 ps
T400 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1298045518 Jul 06 04:41:48 PM PDT 24 Jul 06 04:42:23 PM PDT 24 35603040506 ps
T401 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.426619467 Jul 06 04:41:45 PM PDT 24 Jul 06 04:42:12 PM PDT 24 19714778903 ps
T402 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1933018712 Jul 06 04:41:54 PM PDT 24 Jul 06 04:42:06 PM PDT 24 868451683 ps
T403 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.22600893 Jul 06 04:41:46 PM PDT 24 Jul 06 04:42:07 PM PDT 24 8161189606 ps
T404 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.4049014751 Jul 06 04:41:40 PM PDT 24 Jul 06 04:41:50 PM PDT 24 1180321606 ps
T108 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.407552036 Jul 06 04:41:39 PM PDT 24 Jul 06 04:43:04 PM PDT 24 4281055900 ps
T81 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.4133126384 Jul 06 04:41:50 PM PDT 24 Jul 06 04:44:41 PM PDT 24 22909507985 ps
T405 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3261713736 Jul 06 04:41:49 PM PDT 24 Jul 06 04:42:21 PM PDT 24 3920161065 ps
T84 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3456021040 Jul 06 04:41:44 PM PDT 24 Jul 06 04:42:23 PM PDT 24 2757122711 ps
T406 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2095929487 Jul 06 04:41:53 PM PDT 24 Jul 06 04:42:02 PM PDT 24 174499226 ps
T85 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3872021910 Jul 06 04:41:51 PM PDT 24 Jul 06 04:43:30 PM PDT 24 53591017850 ps
T407 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.64070712 Jul 06 04:41:50 PM PDT 24 Jul 06 04:42:16 PM PDT 24 3170926538 ps
T86 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.13455084 Jul 06 04:41:47 PM PDT 24 Jul 06 04:43:51 PM PDT 24 55998279269 ps
T408 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3460752552 Jul 06 04:41:40 PM PDT 24 Jul 06 04:41:49 PM PDT 24 570026289 ps
T409 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.61492056 Jul 06 04:41:59 PM PDT 24 Jul 06 04:42:15 PM PDT 24 1147091390 ps
T115 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2519170203 Jul 06 04:41:38 PM PDT 24 Jul 06 04:44:19 PM PDT 24 3767135846 ps
T410 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1269343061 Jul 06 04:41:40 PM PDT 24 Jul 06 04:42:05 PM PDT 24 6114044085 ps
T411 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1736836110 Jul 06 04:41:45 PM PDT 24 Jul 06 04:42:23 PM PDT 24 8509542807 ps
T87 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3997833000 Jul 06 04:41:44 PM PDT 24 Jul 06 04:42:14 PM PDT 24 16496228301 ps
T412 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2251952751 Jul 06 04:41:40 PM PDT 24 Jul 06 04:42:02 PM PDT 24 826882477 ps
T413 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3509784290 Jul 06 04:41:40 PM PDT 24 Jul 06 04:41:55 PM PDT 24 347893677 ps
T414 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2422491226 Jul 06 04:41:43 PM PDT 24 Jul 06 04:42:09 PM PDT 24 2396221494 ps
T415 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2045658735 Jul 06 04:41:43 PM PDT 24 Jul 06 04:43:05 PM PDT 24 942398017 ps
T88 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.4199297072 Jul 06 04:41:41 PM PDT 24 Jul 06 04:42:12 PM PDT 24 3507695352 ps
T82 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2991810606 Jul 06 04:41:58 PM PDT 24 Jul 06 04:42:07 PM PDT 24 167765864 ps
T416 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2779102923 Jul 06 04:41:43 PM PDT 24 Jul 06 04:42:02 PM PDT 24 4442284371 ps
T417 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.75957119 Jul 06 04:41:54 PM PDT 24 Jul 06 04:42:29 PM PDT 24 3589338839 ps
T418 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2197292818 Jul 06 04:41:43 PM PDT 24 Jul 06 04:42:13 PM PDT 24 2957713470 ps
T419 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.315975327 Jul 06 04:41:43 PM PDT 24 Jul 06 04:42:14 PM PDT 24 3825273494 ps
T420 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.102315196 Jul 06 04:41:43 PM PDT 24 Jul 06 04:43:58 PM PDT 24 17639840457 ps
T421 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1059722826 Jul 06 04:41:40 PM PDT 24 Jul 06 04:42:09 PM PDT 24 3580403080 ps
T422 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.616061054 Jul 06 04:41:39 PM PDT 24 Jul 06 04:42:03 PM PDT 24 3989353852 ps
T423 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2646607182 Jul 06 04:41:42 PM PDT 24 Jul 06 04:44:18 PM PDT 24 342103310 ps
T424 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3921246721 Jul 06 04:41:59 PM PDT 24 Jul 06 04:42:10 PM PDT 24 1292076589 ps
T91 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2961827464 Jul 06 04:41:44 PM PDT 24 Jul 06 04:43:18 PM PDT 24 36908053993 ps
T425 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.654832810 Jul 06 04:41:40 PM PDT 24 Jul 06 04:41:58 PM PDT 24 11247333960 ps
T426 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3595636531 Jul 06 04:41:47 PM PDT 24 Jul 06 04:44:30 PM PDT 24 8428159633 ps
T427 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3155612478 Jul 06 04:41:45 PM PDT 24 Jul 06 04:42:09 PM PDT 24 8587761734 ps
T428 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3107770811 Jul 06 04:41:41 PM PDT 24 Jul 06 04:42:04 PM PDT 24 14380016094 ps
T429 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2993557927 Jul 06 04:41:57 PM PDT 24 Jul 06 04:42:25 PM PDT 24 11516421812 ps
T430 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4014403296 Jul 06 04:41:46 PM PDT 24 Jul 06 04:43:23 PM PDT 24 2823418511 ps
T89 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2005361451 Jul 06 04:41:57 PM PDT 24 Jul 06 04:44:46 PM PDT 24 40338009301 ps
T431 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3201054656 Jul 06 04:41:58 PM PDT 24 Jul 06 04:42:28 PM PDT 24 3428716109 ps
T112 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.484664426 Jul 06 04:41:42 PM PDT 24 Jul 06 04:43:16 PM PDT 24 22115455978 ps
T432 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3323868206 Jul 06 04:41:56 PM PDT 24 Jul 06 04:42:25 PM PDT 24 12847161445 ps
T433 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3868241408 Jul 06 04:41:39 PM PDT 24 Jul 06 04:41:51 PM PDT 24 399908557 ps
T434 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2649356046 Jul 06 04:41:43 PM PDT 24 Jul 06 04:42:03 PM PDT 24 1718067313 ps
T435 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2730026796 Jul 06 04:41:49 PM PDT 24 Jul 06 04:43:42 PM PDT 24 25375666347 ps
T90 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1685387954 Jul 06 04:41:56 PM PDT 24 Jul 06 04:42:04 PM PDT 24 167698383 ps
T436 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.595686037 Jul 06 04:41:43 PM PDT 24 Jul 06 04:42:07 PM PDT 24 2740467905 ps
T437 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.284299320 Jul 06 04:41:40 PM PDT 24 Jul 06 04:42:14 PM PDT 24 8916253973 ps
T438 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2374153489 Jul 06 04:41:45 PM PDT 24 Jul 06 04:42:14 PM PDT 24 2860104195 ps
T439 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3847972539 Jul 06 04:41:42 PM PDT 24 Jul 06 04:42:03 PM PDT 24 9425383195 ps
T440 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2502759014 Jul 06 04:41:48 PM PDT 24 Jul 06 04:42:09 PM PDT 24 2133402762 ps
T441 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3555329942 Jul 06 04:41:51 PM PDT 24 Jul 06 04:42:05 PM PDT 24 761683304 ps
T442 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1749603855 Jul 06 04:41:42 PM PDT 24 Jul 06 04:41:50 PM PDT 24 661820707 ps
T443 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.854628982 Jul 06 04:41:45 PM PDT 24 Jul 06 04:42:17 PM PDT 24 8191927964 ps
T444 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2252305109 Jul 06 04:41:51 PM PDT 24 Jul 06 04:42:26 PM PDT 24 5598131439 ps
T445 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3998834348 Jul 06 04:41:59 PM PDT 24 Jul 06 04:42:24 PM PDT 24 2738617774 ps
T446 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3530472723 Jul 06 04:41:52 PM PDT 24 Jul 06 04:43:29 PM PDT 24 22656791123 ps
T113 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4260420242 Jul 06 04:41:46 PM PDT 24 Jul 06 04:44:39 PM PDT 24 60218640527 ps
T447 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3504070586 Jul 06 04:41:54 PM PDT 24 Jul 06 04:44:20 PM PDT 24 84553293011 ps
T448 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1133229739 Jul 06 04:41:47 PM PDT 24 Jul 06 04:42:05 PM PDT 24 1567132773 ps
T449 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2691398976 Jul 06 04:42:02 PM PDT 24 Jul 06 04:43:47 PM PDT 24 106220097393 ps
T114 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2746422235 Jul 06 04:41:45 PM PDT 24 Jul 06 04:44:44 PM PDT 24 16864178698 ps
T450 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3366364092 Jul 06 04:41:43 PM PDT 24 Jul 06 04:41:55 PM PDT 24 1469996044 ps
T451 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.311972485 Jul 06 04:42:08 PM PDT 24 Jul 06 04:42:39 PM PDT 24 3004537101 ps
T452 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3731992279 Jul 06 04:41:41 PM PDT 24 Jul 06 04:43:09 PM PDT 24 2059666565 ps

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.685671501
Short name T3
Test name
Test status
Simulation time 85236878632 ps
CPU time 1766.02 seconds
Started Jul 06 05:33:11 PM PDT 24
Finished Jul 06 06:02:38 PM PDT 24
Peak memory 246068 kb
Host smart-44547f20-580d-44ae-ac97-c59dc1807a00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685671501 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.685671501
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.4265196288
Short name T4
Test name
Test status
Simulation time 409069269854 ps
CPU time 1068.93 seconds
Started Jul 06 05:33:52 PM PDT 24
Finished Jul 06 05:51:41 PM PDT 24
Peak memory 215812 kb
Host smart-f07fdf23-824b-419c-ad6b-709063c0d855
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265196288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.4265196288
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3900933663
Short name T40
Test name
Test status
Simulation time 467161464989 ps
CPU time 750.01 seconds
Started Jul 06 05:34:54 PM PDT 24
Finished Jul 06 05:47:24 PM PDT 24
Peak memory 234896 kb
Host smart-63fb5e82-6ef2-4f0c-9611-86178417748a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900933663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3900933663
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2644495296
Short name T50
Test name
Test status
Simulation time 7701635224 ps
CPU time 173.09 seconds
Started Jul 06 04:42:01 PM PDT 24
Finished Jul 06 04:44:55 PM PDT 24
Peak memory 214100 kb
Host smart-de97a02e-064c-4f48-b236-a745bf4002a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644495296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2644495296
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3773675398
Short name T11
Test name
Test status
Simulation time 16541729147 ps
CPU time 299.54 seconds
Started Jul 06 05:34:54 PM PDT 24
Finished Jul 06 05:39:54 PM PDT 24
Peak memory 220996 kb
Host smart-ec45074e-295d-47b6-97a6-71e4bb313bae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773675398 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3773675398
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.187564853
Short name T21
Test name
Test status
Simulation time 2645477923 ps
CPU time 227.43 seconds
Started Jul 06 05:33:27 PM PDT 24
Finished Jul 06 05:37:14 PM PDT 24
Peak memory 238064 kb
Host smart-11d47c13-e126-4641-81b9-596e9665fcfe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187564853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.187564853
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.803441730
Short name T69
Test name
Test status
Simulation time 26105754188 ps
CPU time 195.6 seconds
Started Jul 06 04:41:40 PM PDT 24
Finished Jul 06 04:44:56 PM PDT 24
Peak memory 214892 kb
Host smart-c624adf1-0750-4430-a325-3340eafbcc86
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803441730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.803441730
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.195219022
Short name T14
Test name
Test status
Simulation time 743886069 ps
CPU time 45.42 seconds
Started Jul 06 05:33:10 PM PDT 24
Finished Jul 06 05:33:55 PM PDT 24
Peak memory 219328 kb
Host smart-91d7b54d-a03b-4c24-85d0-46628812cb31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195219022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.195219022
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3779784783
Short name T54
Test name
Test status
Simulation time 5848173167 ps
CPU time 167.04 seconds
Started Jul 06 04:41:54 PM PDT 24
Finished Jul 06 04:44:42 PM PDT 24
Peak memory 214076 kb
Host smart-adc6c8d4-b641-4cde-a8c7-78ae7b3ce959
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779784783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3779784783
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1247785881
Short name T56
Test name
Test status
Simulation time 2733845932 ps
CPU time 12.96 seconds
Started Jul 06 05:34:10 PM PDT 24
Finished Jul 06 05:34:23 PM PDT 24
Peak memory 217200 kb
Host smart-6f29874a-cce9-44d8-ac96-dfa254f9231a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247785881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1247785881
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.804648061
Short name T45
Test name
Test status
Simulation time 6555719631 ps
CPU time 40.47 seconds
Started Jul 06 05:34:20 PM PDT 24
Finished Jul 06 05:35:01 PM PDT 24
Peak memory 219340 kb
Host smart-870af5f4-b30b-4db5-8418-eba43ed282c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804648061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.804648061
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.92390898
Short name T140
Test name
Test status
Simulation time 339152374 ps
CPU time 19.16 seconds
Started Jul 06 05:34:20 PM PDT 24
Finished Jul 06 05:34:40 PM PDT 24
Peak memory 219328 kb
Host smart-896a7e49-0f16-4ae7-b3c6-7aaae2473f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92390898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.92390898
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2005361451
Short name T89
Test name
Test status
Simulation time 40338009301 ps
CPU time 168.02 seconds
Started Jul 06 04:41:57 PM PDT 24
Finished Jul 06 04:44:46 PM PDT 24
Peak memory 214764 kb
Host smart-7071a1cf-6f09-4f7c-baf6-c9ef27f2f768
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005361451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2005361451
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4260420242
Short name T113
Test name
Test status
Simulation time 60218640527 ps
CPU time 172.87 seconds
Started Jul 06 04:41:46 PM PDT 24
Finished Jul 06 04:44:39 PM PDT 24
Peak memory 213108 kb
Host smart-529a38e2-5d07-4e58-bb9a-89577446a66a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260420242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.4260420242
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2746422235
Short name T114
Test name
Test status
Simulation time 16864178698 ps
CPU time 174.24 seconds
Started Jul 06 04:41:45 PM PDT 24
Finished Jul 06 04:44:44 PM PDT 24
Peak memory 214028 kb
Host smart-ccba005b-35e0-45fa-84c1-d49956b66376
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746422235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2746422235
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3548141734
Short name T63
Test name
Test status
Simulation time 1067707254 ps
CPU time 56.08 seconds
Started Jul 06 04:41:41 PM PDT 24
Finished Jul 06 04:42:38 PM PDT 24
Peak memory 213764 kb
Host smart-40290c91-1fc0-4473-8a87-4ff1611d1fc2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548141734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3548141734
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.3996575308
Short name T13
Test name
Test status
Simulation time 26686136438 ps
CPU time 1608.51 seconds
Started Jul 06 05:34:21 PM PDT 24
Finished Jul 06 06:01:10 PM PDT 24
Peak memory 228232 kb
Host smart-b0aff73b-4579-493e-8e3f-bf625a51bb4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996575308 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.3996575308
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1685387954
Short name T90
Test name
Test status
Simulation time 167698383 ps
CPU time 8.29 seconds
Started Jul 06 04:41:56 PM PDT 24
Finished Jul 06 04:42:04 PM PDT 24
Peak memory 210588 kb
Host smart-696133f5-d602-4e67-aa15-7b741d76b751
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685387954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1685387954
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2272178972
Short name T369
Test name
Test status
Simulation time 9252229327 ps
CPU time 22.8 seconds
Started Jul 06 04:41:40 PM PDT 24
Finished Jul 06 04:42:04 PM PDT 24
Peak memory 211068 kb
Host smart-a0dce64d-867c-4b64-8e48-4e9df17985ad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272178972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2272178972
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2251952751
Short name T412
Test name
Test status
Simulation time 826882477 ps
CPU time 21.11 seconds
Started Jul 06 04:41:40 PM PDT 24
Finished Jul 06 04:42:02 PM PDT 24
Peak memory 210928 kb
Host smart-17457771-bf6e-4d92-aeae-d2fab06e7aca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251952751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2251952751
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1161865611
Short name T51
Test name
Test status
Simulation time 9838617146 ps
CPU time 25.64 seconds
Started Jul 06 04:41:39 PM PDT 24
Finished Jul 06 04:42:05 PM PDT 24
Peak memory 217500 kb
Host smart-db1957cf-1066-4ab1-b8d4-dbee7eb2ff28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161865611 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1161865611
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1375879332
Short name T378
Test name
Test status
Simulation time 684096130 ps
CPU time 12.73 seconds
Started Jul 06 04:41:43 PM PDT 24
Finished Jul 06 04:41:56 PM PDT 24
Peak memory 210536 kb
Host smart-87da3523-ebc9-4e61-94ad-e87a046397e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375879332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1375879332
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4208455210
Short name T385
Test name
Test status
Simulation time 1397231409 ps
CPU time 16.85 seconds
Started Jul 06 04:41:41 PM PDT 24
Finished Jul 06 04:41:58 PM PDT 24
Peak memory 210428 kb
Host smart-75606fc4-db42-4648-8679-ad7ec6c73176
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208455210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.4208455210
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3343354220
Short name T368
Test name
Test status
Simulation time 3250260655 ps
CPU time 26.9 seconds
Started Jul 06 04:41:39 PM PDT 24
Finished Jul 06 04:42:06 PM PDT 24
Peak memory 210520 kb
Host smart-f21c327e-6d3c-4839-b697-4dec94aa71ef
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343354220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3343354220
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.315975327
Short name T419
Test name
Test status
Simulation time 3825273494 ps
CPU time 30.35 seconds
Started Jul 06 04:41:43 PM PDT 24
Finished Jul 06 04:42:14 PM PDT 24
Peak memory 211976 kb
Host smart-db3dac55-5140-4007-b3ce-851935e78afa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315975327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.315975327
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2294353655
Short name T371
Test name
Test status
Simulation time 3258546190 ps
CPU time 22.98 seconds
Started Jul 06 04:41:54 PM PDT 24
Finished Jul 06 04:42:17 PM PDT 24
Peak memory 218212 kb
Host smart-3a9269be-a14f-4d25-a629-d2833a4c5df2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294353655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2294353655
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.407552036
Short name T108
Test name
Test status
Simulation time 4281055900 ps
CPU time 84.66 seconds
Started Jul 06 04:41:39 PM PDT 24
Finished Jul 06 04:43:04 PM PDT 24
Peak memory 213480 kb
Host smart-400528b5-3370-4a10-a75a-fd561ff9a427
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407552036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.407552036
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1333830384
Short name T55
Test name
Test status
Simulation time 174272509 ps
CPU time 8.18 seconds
Started Jul 06 04:41:42 PM PDT 24
Finished Jul 06 04:41:51 PM PDT 24
Peak memory 210540 kb
Host smart-748b3725-43e2-45d8-9dd0-9b23ea022f15
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333830384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1333830384
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1059722826
Short name T421
Test name
Test status
Simulation time 3580403080 ps
CPU time 28.63 seconds
Started Jul 06 04:41:40 PM PDT 24
Finished Jul 06 04:42:09 PM PDT 24
Peak memory 211160 kb
Host smart-33be85fe-1bf7-4101-abdd-c3fe31cfc70c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059722826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1059722826
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.75957119
Short name T417
Test name
Test status
Simulation time 3589338839 ps
CPU time 34.26 seconds
Started Jul 06 04:41:54 PM PDT 24
Finished Jul 06 04:42:29 PM PDT 24
Peak memory 211592 kb
Host smart-5b0ca556-16bd-410f-9bef-3d767c3ce813
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75957119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_res
et.75957119
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3847972539
Short name T439
Test name
Test status
Simulation time 9425383195 ps
CPU time 20.65 seconds
Started Jul 06 04:41:42 PM PDT 24
Finished Jul 06 04:42:03 PM PDT 24
Peak memory 217636 kb
Host smart-6a8d8333-56ff-4fe8-8ee4-4d9cc4619b4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847972539 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3847972539
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3107770811
Short name T428
Test name
Test status
Simulation time 14380016094 ps
CPU time 23 seconds
Started Jul 06 04:41:41 PM PDT 24
Finished Jul 06 04:42:04 PM PDT 24
Peak memory 211888 kb
Host smart-d1c50865-e5ff-4146-90fe-a9a6c1409a50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107770811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3107770811
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1749603855
Short name T442
Test name
Test status
Simulation time 661820707 ps
CPU time 8.23 seconds
Started Jul 06 04:41:42 PM PDT 24
Finished Jul 06 04:41:50 PM PDT 24
Peak memory 210400 kb
Host smart-30d343ee-3a1b-4dde-bbc1-de8917f03bed
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749603855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1749603855
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3591833258
Short name T386
Test name
Test status
Simulation time 12964072221 ps
CPU time 26.54 seconds
Started Jul 06 04:41:39 PM PDT 24
Finished Jul 06 04:42:06 PM PDT 24
Peak memory 210460 kb
Host smart-3265825a-0296-452b-80e2-e6add64a1cbb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591833258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3591833258
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2779102923
Short name T416
Test name
Test status
Simulation time 4442284371 ps
CPU time 19.01 seconds
Started Jul 06 04:41:43 PM PDT 24
Finished Jul 06 04:42:02 PM PDT 24
Peak memory 212532 kb
Host smart-7599cc20-5ecb-48e7-b592-e2e20b8de0b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779102923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2779102923
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.472329074
Short name T376
Test name
Test status
Simulation time 2086878453 ps
CPU time 23.64 seconds
Started Jul 06 04:41:54 PM PDT 24
Finished Jul 06 04:42:18 PM PDT 24
Peak memory 218184 kb
Host smart-bb7dca1a-961b-47b8-9e78-980b77c97146
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472329074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.472329074
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.484664426
Short name T112
Test name
Test status
Simulation time 22115455978 ps
CPU time 93.42 seconds
Started Jul 06 04:41:42 PM PDT 24
Finished Jul 06 04:43:16 PM PDT 24
Peak memory 213804 kb
Host smart-e5fa5b3f-b309-41c4-8a93-a68fd57f5bc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484664426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.484664426
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3555329942
Short name T441
Test name
Test status
Simulation time 761683304 ps
CPU time 13.48 seconds
Started Jul 06 04:41:51 PM PDT 24
Finished Jul 06 04:42:05 PM PDT 24
Peak memory 213456 kb
Host smart-8d33fd06-e54c-4d71-bb27-294b1f6462bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555329942 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3555329942
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3461283997
Short name T372
Test name
Test status
Simulation time 2300185082 ps
CPU time 12.38 seconds
Started Jul 06 04:41:44 PM PDT 24
Finished Jul 06 04:41:57 PM PDT 24
Peak memory 210572 kb
Host smart-4fb47c3d-0b9e-455d-9ab5-85862bf6c7a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461283997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3461283997
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.64070712
Short name T407
Test name
Test status
Simulation time 3170926538 ps
CPU time 25.97 seconds
Started Jul 06 04:41:50 PM PDT 24
Finished Jul 06 04:42:16 PM PDT 24
Peak memory 211960 kb
Host smart-53c00d35-2ab7-48e3-a7e8-dd145f77d721
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64070712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ct
rl_same_csr_outstanding.64070712
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2993557927
Short name T429
Test name
Test status
Simulation time 11516421812 ps
CPU time 27.65 seconds
Started Jul 06 04:41:57 PM PDT 24
Finished Jul 06 04:42:25 PM PDT 24
Peak memory 217532 kb
Host smart-dd2da18b-b1cf-487b-97be-ad45d916d341
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993557927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2993557927
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3195896468
Short name T110
Test name
Test status
Simulation time 2617211073 ps
CPU time 168.1 seconds
Started Jul 06 04:41:46 PM PDT 24
Finished Jul 06 04:44:34 PM PDT 24
Peak memory 213696 kb
Host smart-a2f96fe8-33be-491a-bd19-59ab474da035
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195896468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3195896468
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1420504725
Short name T52
Test name
Test status
Simulation time 14638474921 ps
CPU time 26.82 seconds
Started Jul 06 04:41:54 PM PDT 24
Finished Jul 06 04:42:21 PM PDT 24
Peak memory 218092 kb
Host smart-a7d34e7c-2064-4fef-ab86-654babb99f3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420504725 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1420504725
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2251443952
Short name T99
Test name
Test status
Simulation time 174381176 ps
CPU time 7.97 seconds
Started Jul 06 04:41:44 PM PDT 24
Finished Jul 06 04:41:53 PM PDT 24
Peak memory 210540 kb
Host smart-01e08185-4cce-48e1-83c0-81631418c2f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251443952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2251443952
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3054267628
Short name T77
Test name
Test status
Simulation time 6587641032 ps
CPU time 80.15 seconds
Started Jul 06 04:41:45 PM PDT 24
Finished Jul 06 04:43:05 PM PDT 24
Peak memory 213960 kb
Host smart-988b8b79-f25f-4826-9f74-fff8e0a77621
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054267628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3054267628
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3366364092
Short name T450
Test name
Test status
Simulation time 1469996044 ps
CPU time 11.36 seconds
Started Jul 06 04:41:43 PM PDT 24
Finished Jul 06 04:41:55 PM PDT 24
Peak memory 211208 kb
Host smart-5be5eefa-22f0-4591-b144-6d0e8dcdfecf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366364092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3366364092
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.191705010
Short name T363
Test name
Test status
Simulation time 174434685 ps
CPU time 12.11 seconds
Started Jul 06 04:41:46 PM PDT 24
Finished Jul 06 04:41:59 PM PDT 24
Peak memory 217088 kb
Host smart-b7379df4-0128-4ad3-88ed-25900706d38d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191705010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.191705010
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3921246721
Short name T424
Test name
Test status
Simulation time 1292076589 ps
CPU time 10.96 seconds
Started Jul 06 04:41:59 PM PDT 24
Finished Jul 06 04:42:10 PM PDT 24
Peak memory 215580 kb
Host smart-077c7e4e-d456-4c32-98b5-ab8ea63f0b70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921246721 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3921246721
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2807617342
Short name T65
Test name
Test status
Simulation time 174373613 ps
CPU time 8.31 seconds
Started Jul 06 04:41:47 PM PDT 24
Finished Jul 06 04:41:56 PM PDT 24
Peak memory 210332 kb
Host smart-29bc1831-8068-4cab-8961-95f9389d098f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807617342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2807617342
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1726551754
Short name T79
Test name
Test status
Simulation time 69579358797 ps
CPU time 133.86 seconds
Started Jul 06 04:41:51 PM PDT 24
Finished Jul 06 04:44:05 PM PDT 24
Peak memory 213716 kb
Host smart-c3c89c5c-d7f1-42c6-acf6-f3635d9a86ac
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726551754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1726551754
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1536635673
Short name T64
Test name
Test status
Simulation time 3681124129 ps
CPU time 28.86 seconds
Started Jul 06 04:41:54 PM PDT 24
Finished Jul 06 04:42:24 PM PDT 24
Peak memory 212176 kb
Host smart-1a7f8024-887b-498f-8b1f-d7b3e5d8d03f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536635673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1536635673
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2252305109
Short name T444
Test name
Test status
Simulation time 5598131439 ps
CPU time 34.82 seconds
Started Jul 06 04:41:51 PM PDT 24
Finished Jul 06 04:42:26 PM PDT 24
Peak memory 217556 kb
Host smart-6385e51d-8fb8-4dc3-9583-00a55583dfe1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252305109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2252305109
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3530472723
Short name T446
Test name
Test status
Simulation time 22656791123 ps
CPU time 97.67 seconds
Started Jul 06 04:41:52 PM PDT 24
Finished Jul 06 04:43:29 PM PDT 24
Peak memory 212492 kb
Host smart-af74357d-24ae-423f-ad72-4fb2e797a239
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530472723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3530472723
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3922293129
Short name T364
Test name
Test status
Simulation time 6010683663 ps
CPU time 16.52 seconds
Started Jul 06 04:42:03 PM PDT 24
Finished Jul 06 04:42:20 PM PDT 24
Peak memory 218864 kb
Host smart-30000894-b6ae-40a4-8809-c29ba2857e67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922293129 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3922293129
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2991810606
Short name T82
Test name
Test status
Simulation time 167765864 ps
CPU time 8.22 seconds
Started Jul 06 04:41:58 PM PDT 24
Finished Jul 06 04:42:07 PM PDT 24
Peak memory 210520 kb
Host smart-1b8690d5-1c77-45b2-b0d7-6dceaa652caa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991810606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2991810606
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2996663465
Short name T390
Test name
Test status
Simulation time 15118457102 ps
CPU time 131.14 seconds
Started Jul 06 04:41:45 PM PDT 24
Finished Jul 06 04:43:56 PM PDT 24
Peak memory 214016 kb
Host smart-441d7d2b-12c0-4036-a0e6-3448f5fe3b0d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996663465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2996663465
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2576294450
Short name T397
Test name
Test status
Simulation time 3341193707 ps
CPU time 26.62 seconds
Started Jul 06 04:41:53 PM PDT 24
Finished Jul 06 04:42:20 PM PDT 24
Peak memory 211836 kb
Host smart-e66c75b2-9a33-406c-adb6-b1deb43d2479
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576294450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2576294450
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1401628118
Short name T383
Test name
Test status
Simulation time 9203401800 ps
CPU time 25.2 seconds
Started Jul 06 04:41:46 PM PDT 24
Finished Jul 06 04:42:12 PM PDT 24
Peak memory 216972 kb
Host smart-bf9425c5-c99d-47d3-b72f-1e1c04792ca9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401628118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1401628118
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1810502869
Short name T107
Test name
Test status
Simulation time 12820496131 ps
CPU time 171.61 seconds
Started Jul 06 04:41:56 PM PDT 24
Finished Jul 06 04:44:48 PM PDT 24
Peak memory 214256 kb
Host smart-c5c8cd73-6aa8-46bb-9d97-78e26da35bbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810502869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1810502869
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2180090499
Short name T379
Test name
Test status
Simulation time 12721110900 ps
CPU time 26.73 seconds
Started Jul 06 04:41:57 PM PDT 24
Finished Jul 06 04:42:24 PM PDT 24
Peak memory 217192 kb
Host smart-60f7e145-7255-4983-b063-00944eb938f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180090499 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2180090499
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.4294366465
Short name T387
Test name
Test status
Simulation time 196746720 ps
CPU time 8.2 seconds
Started Jul 06 04:42:03 PM PDT 24
Finished Jul 06 04:42:11 PM PDT 24
Peak memory 210872 kb
Host smart-b3696330-0ae1-4695-84a5-8be3b65af1bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294366465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.4294366465
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.569064201
Short name T62
Test name
Test status
Simulation time 13241497580 ps
CPU time 133.75 seconds
Started Jul 06 04:42:29 PM PDT 24
Finished Jul 06 04:44:43 PM PDT 24
Peak memory 214084 kb
Host smart-be69e2ee-5369-4fa3-9029-40d796818c58
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569064201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa
ssthru_mem_tl_intg_err.569064201
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1133229739
Short name T448
Test name
Test status
Simulation time 1567132773 ps
CPU time 17.84 seconds
Started Jul 06 04:41:47 PM PDT 24
Finished Jul 06 04:42:05 PM PDT 24
Peak memory 212204 kb
Host smart-0e16bda6-e8ea-4b9e-a14a-79cf3746999f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133229739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1133229739
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2197292818
Short name T418
Test name
Test status
Simulation time 2957713470 ps
CPU time 29.75 seconds
Started Jul 06 04:41:43 PM PDT 24
Finished Jul 06 04:42:13 PM PDT 24
Peak memory 217160 kb
Host smart-dfb35362-2f0c-476f-a178-f4854a890f4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197292818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2197292818
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2948939362
Short name T106
Test name
Test status
Simulation time 8090818281 ps
CPU time 90.94 seconds
Started Jul 06 04:42:10 PM PDT 24
Finished Jul 06 04:43:41 PM PDT 24
Peak memory 213880 kb
Host smart-361cd9fe-6729-4a0f-bc34-95f9e55091ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948939362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2948939362
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2007988805
Short name T375
Test name
Test status
Simulation time 758410389 ps
CPU time 9.15 seconds
Started Jul 06 04:42:01 PM PDT 24
Finished Jul 06 04:42:10 PM PDT 24
Peak memory 217280 kb
Host smart-f6219896-3045-4c39-a26a-b727f72365eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007988805 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2007988805
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.284378203
Short name T377
Test name
Test status
Simulation time 1025927054 ps
CPU time 14.42 seconds
Started Jul 06 04:41:44 PM PDT 24
Finished Jul 06 04:41:59 PM PDT 24
Peak memory 211744 kb
Host smart-6effbf75-a92c-432f-9c16-4d766ad2bc62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284378203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.284378203
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3615786770
Short name T71
Test name
Test status
Simulation time 127249449622 ps
CPU time 168.7 seconds
Started Jul 06 04:41:47 PM PDT 24
Finished Jul 06 04:44:36 PM PDT 24
Peak memory 215228 kb
Host smart-92df2f3e-645b-4cdb-9a8b-7e558a0969ce
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615786770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3615786770
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.720692408
Short name T92
Test name
Test status
Simulation time 2935920419 ps
CPU time 13.44 seconds
Started Jul 06 04:41:47 PM PDT 24
Finished Jul 06 04:42:01 PM PDT 24
Peak memory 210700 kb
Host smart-2dbf007f-1d2b-4c40-ab84-586df057207c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720692408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.720692408
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2844895372
Short name T61
Test name
Test status
Simulation time 10617643241 ps
CPU time 27.7 seconds
Started Jul 06 04:41:52 PM PDT 24
Finished Jul 06 04:42:20 PM PDT 24
Peak memory 218896 kb
Host smart-e765df21-63c4-4134-bda6-5846209094a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844895372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2844895372
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4243644941
Short name T394
Test name
Test status
Simulation time 294995378 ps
CPU time 9.93 seconds
Started Jul 06 04:41:54 PM PDT 24
Finished Jul 06 04:42:05 PM PDT 24
Peak memory 213516 kb
Host smart-f94547ca-bb86-4ca8-b432-7c52aec9d31b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243644941 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.4243644941
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2235377982
Short name T70
Test name
Test status
Simulation time 167319501 ps
CPU time 8.15 seconds
Started Jul 06 04:41:53 PM PDT 24
Finished Jul 06 04:42:02 PM PDT 24
Peak memory 210168 kb
Host smart-7beabd53-2e74-4bb3-a47e-aae265f45d73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235377982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2235377982
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2691398976
Short name T449
Test name
Test status
Simulation time 106220097393 ps
CPU time 103.96 seconds
Started Jul 06 04:42:02 PM PDT 24
Finished Jul 06 04:43:47 PM PDT 24
Peak memory 214772 kb
Host smart-d784c640-1b0d-4b1c-b12b-e245a5d6eab7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691398976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2691398976
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1379284428
Short name T94
Test name
Test status
Simulation time 33571561690 ps
CPU time 29.33 seconds
Started Jul 06 04:41:55 PM PDT 24
Finished Jul 06 04:42:25 PM PDT 24
Peak memory 212608 kb
Host smart-4eb98288-5a35-44fb-be0a-ff1f1eda0b86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379284428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1379284428
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2422491226
Short name T414
Test name
Test status
Simulation time 2396221494 ps
CPU time 24.71 seconds
Started Jul 06 04:41:43 PM PDT 24
Finished Jul 06 04:42:09 PM PDT 24
Peak memory 217208 kb
Host smart-401e8944-bcfb-4676-b10e-0ed779dd5300
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422491226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2422491226
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3595636531
Short name T426
Test name
Test status
Simulation time 8428159633 ps
CPU time 162.49 seconds
Started Jul 06 04:41:47 PM PDT 24
Finished Jul 06 04:44:30 PM PDT 24
Peak memory 214232 kb
Host smart-dac8c197-6c64-40fd-bc57-a830a7bcf0f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595636531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3595636531
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1298045518
Short name T400
Test name
Test status
Simulation time 35603040506 ps
CPU time 34.78 seconds
Started Jul 06 04:41:48 PM PDT 24
Finished Jul 06 04:42:23 PM PDT 24
Peak memory 217920 kb
Host smart-1de0b762-350f-4e52-97f7-5c03e7ffeefb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298045518 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1298045518
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.61492056
Short name T409
Test name
Test status
Simulation time 1147091390 ps
CPU time 15.7 seconds
Started Jul 06 04:41:59 PM PDT 24
Finished Jul 06 04:42:15 PM PDT 24
Peak memory 210676 kb
Host smart-51726afc-7dc5-432c-8e63-6eb20b8b6b7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61492056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.61492056
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.13455084
Short name T86
Test name
Test status
Simulation time 55998279269 ps
CPU time 123.03 seconds
Started Jul 06 04:41:47 PM PDT 24
Finished Jul 06 04:43:51 PM PDT 24
Peak memory 213760 kb
Host smart-c2acd40c-e12e-467d-b683-151b2f709dd1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13455084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pas
sthru_mem_tl_intg_err.13455084
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3201054656
Short name T431
Test name
Test status
Simulation time 3428716109 ps
CPU time 29.44 seconds
Started Jul 06 04:41:58 PM PDT 24
Finished Jul 06 04:42:28 PM PDT 24
Peak memory 212216 kb
Host smart-42cea884-1f9f-46e3-bec4-e4b891513a23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201054656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3201054656
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.504927596
Short name T396
Test name
Test status
Simulation time 1948792765 ps
CPU time 22.37 seconds
Started Jul 06 04:41:54 PM PDT 24
Finished Jul 06 04:42:17 PM PDT 24
Peak memory 217132 kb
Host smart-d240dec8-4f76-40e7-bf57-3c8953905327
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504927596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.504927596
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2472709550
Short name T53
Test name
Test status
Simulation time 7770909952 ps
CPU time 93.02 seconds
Started Jul 06 04:41:53 PM PDT 24
Finished Jul 06 04:43:26 PM PDT 24
Peak memory 213224 kb
Host smart-a34c8616-cf74-40a0-a9e9-67beb41ca24c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472709550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2472709550
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3515533076
Short name T398
Test name
Test status
Simulation time 4031527843 ps
CPU time 31.66 seconds
Started Jul 06 04:41:54 PM PDT 24
Finished Jul 06 04:42:27 PM PDT 24
Peak memory 214736 kb
Host smart-3ea58cca-1218-4c2a-8976-9890a619b6c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515533076 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3515533076
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2502759014
Short name T440
Test name
Test status
Simulation time 2133402762 ps
CPU time 21.29 seconds
Started Jul 06 04:41:48 PM PDT 24
Finished Jul 06 04:42:09 PM PDT 24
Peak memory 210520 kb
Host smart-5f0eee09-8c56-4ec6-bd04-5bd968207d09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502759014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2502759014
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.4133126384
Short name T81
Test name
Test status
Simulation time 22909507985 ps
CPU time 170.96 seconds
Started Jul 06 04:41:50 PM PDT 24
Finished Jul 06 04:44:41 PM PDT 24
Peak memory 215080 kb
Host smart-e0be3b4c-2978-4434-b35d-831e6cfe6635
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133126384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.4133126384
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1398735844
Short name T95
Test name
Test status
Simulation time 3875821643 ps
CPU time 30.86 seconds
Started Jul 06 04:41:51 PM PDT 24
Finished Jul 06 04:42:22 PM PDT 24
Peak memory 212184 kb
Host smart-edbbc9d4-8149-44ad-8e10-d7051483eb25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398735844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1398735844
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.311972485
Short name T451
Test name
Test status
Simulation time 3004537101 ps
CPU time 30.4 seconds
Started Jul 06 04:42:08 PM PDT 24
Finished Jul 06 04:42:39 PM PDT 24
Peak memory 218432 kb
Host smart-72d21067-369f-4881-b6b4-6b6fb01799e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311972485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.311972485
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3323868206
Short name T432
Test name
Test status
Simulation time 12847161445 ps
CPU time 28.11 seconds
Started Jul 06 04:41:56 PM PDT 24
Finished Jul 06 04:42:25 PM PDT 24
Peak memory 216292 kb
Host smart-4723ab99-40a9-41ef-9796-a44ef23c69e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323868206 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3323868206
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3261713736
Short name T405
Test name
Test status
Simulation time 3920161065 ps
CPU time 32.59 seconds
Started Jul 06 04:41:49 PM PDT 24
Finished Jul 06 04:42:21 PM PDT 24
Peak memory 211536 kb
Host smart-de653f4f-73c0-48f4-8bfe-188c89f519d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261713736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3261713736
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3121718129
Short name T93
Test name
Test status
Simulation time 13382429058 ps
CPU time 27.7 seconds
Started Jul 06 04:41:58 PM PDT 24
Finished Jul 06 04:42:26 PM PDT 24
Peak memory 211580 kb
Host smart-3c6d9a99-f424-4b03-97da-1da5f26a2f71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121718129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3121718129
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1933018712
Short name T402
Test name
Test status
Simulation time 868451683 ps
CPU time 11.4 seconds
Started Jul 06 04:41:54 PM PDT 24
Finished Jul 06 04:42:06 PM PDT 24
Peak memory 217220 kb
Host smart-6d0fd818-0950-4c29-8f31-161e13196f50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933018712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1933018712
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2054310246
Short name T111
Test name
Test status
Simulation time 898946133 ps
CPU time 80.89 seconds
Started Jul 06 04:41:50 PM PDT 24
Finished Jul 06 04:43:11 PM PDT 24
Peak memory 212596 kb
Host smart-f691eb54-eb82-4a6d-9cd0-b2b1a8028e99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054310246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2054310246
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.376729980
Short name T68
Test name
Test status
Simulation time 377035698 ps
CPU time 8.05 seconds
Started Jul 06 04:41:54 PM PDT 24
Finished Jul 06 04:42:02 PM PDT 24
Peak memory 210232 kb
Host smart-bbfc2738-3d69-4e12-a0ea-40cbc18016e3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376729980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.376729980
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3460752552
Short name T408
Test name
Test status
Simulation time 570026289 ps
CPU time 8.51 seconds
Started Jul 06 04:41:40 PM PDT 24
Finished Jul 06 04:41:49 PM PDT 24
Peak memory 210584 kb
Host smart-3d0bcda4-9b5c-4878-8701-8032483edf4e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460752552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3460752552
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.998304983
Short name T76
Test name
Test status
Simulation time 346736287 ps
CPU time 14.84 seconds
Started Jul 06 04:41:54 PM PDT 24
Finished Jul 06 04:42:10 PM PDT 24
Peak memory 211616 kb
Host smart-a6a47db0-2e3f-47ed-933b-4faa2dc73ed7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998304983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.998304983
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1179386623
Short name T380
Test name
Test status
Simulation time 2136575396 ps
CPU time 21.05 seconds
Started Jul 06 04:41:54 PM PDT 24
Finished Jul 06 04:42:15 PM PDT 24
Peak memory 218740 kb
Host smart-6078126a-774d-4cd6-93fe-ee69eb36d38d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179386623 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1179386623
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1269343061
Short name T410
Test name
Test status
Simulation time 6114044085 ps
CPU time 24.92 seconds
Started Jul 06 04:41:40 PM PDT 24
Finished Jul 06 04:42:05 PM PDT 24
Peak memory 211812 kb
Host smart-5a56f286-a16a-4604-8cd4-efc069581bf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269343061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1269343061
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1541874657
Short name T361
Test name
Test status
Simulation time 7437102883 ps
CPU time 18.4 seconds
Started Jul 06 04:41:39 PM PDT 24
Finished Jul 06 04:41:58 PM PDT 24
Peak memory 210748 kb
Host smart-114ea5b2-c202-45e0-82d4-3aa68160763a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541874657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1541874657
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2888762975
Short name T384
Test name
Test status
Simulation time 169291280 ps
CPU time 8.43 seconds
Started Jul 06 04:41:39 PM PDT 24
Finished Jul 06 04:41:48 PM PDT 24
Peak memory 210448 kb
Host smart-6b08def0-7d2d-4211-bb47-3599f5d1cba1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888762975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2888762975
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3504070586
Short name T447
Test name
Test status
Simulation time 84553293011 ps
CPU time 145.81 seconds
Started Jul 06 04:41:54 PM PDT 24
Finished Jul 06 04:44:20 PM PDT 24
Peak memory 214332 kb
Host smart-72952c27-175d-4ade-81ea-a07b5cf9f5a5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504070586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3504070586
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2981018899
Short name T66
Test name
Test status
Simulation time 167597106 ps
CPU time 8.22 seconds
Started Jul 06 04:41:39 PM PDT 24
Finished Jul 06 04:41:48 PM PDT 24
Peak memory 211044 kb
Host smart-5c63a1be-ff9b-4c34-9bcc-a055338a3188
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981018899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2981018899
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1065574659
Short name T365
Test name
Test status
Simulation time 4100254097 ps
CPU time 13.83 seconds
Started Jul 06 04:41:54 PM PDT 24
Finished Jul 06 04:42:08 PM PDT 24
Peak memory 217016 kb
Host smart-907a19e4-b309-4003-93d2-bf0b342db51d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065574659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1065574659
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3731992279
Short name T452
Test name
Test status
Simulation time 2059666565 ps
CPU time 87.64 seconds
Started Jul 06 04:41:41 PM PDT 24
Finished Jul 06 04:43:09 PM PDT 24
Peak memory 213496 kb
Host smart-ba9d0f83-ad3a-4dae-8930-950fb8c2d14e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731992279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3731992279
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.4199297072
Short name T88
Test name
Test status
Simulation time 3507695352 ps
CPU time 29.87 seconds
Started Jul 06 04:41:41 PM PDT 24
Finished Jul 06 04:42:12 PM PDT 24
Peak memory 211428 kb
Host smart-0b018d9b-265d-43eb-af58-8af5656ae40e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199297072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.4199297072
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.4055885541
Short name T83
Test name
Test status
Simulation time 7055185904 ps
CPU time 26.23 seconds
Started Jul 06 04:41:43 PM PDT 24
Finished Jul 06 04:42:09 PM PDT 24
Peak memory 211660 kb
Host smart-f5e98319-a84e-47f7-91da-2158967ba034
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055885541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.4055885541
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.654832810
Short name T425
Test name
Test status
Simulation time 11247333960 ps
CPU time 17.79 seconds
Started Jul 06 04:41:40 PM PDT 24
Finished Jul 06 04:41:58 PM PDT 24
Peak memory 212028 kb
Host smart-4d27442a-9dd4-42c4-b60e-0e326d7b9666
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654832810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.654832810
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2911765177
Short name T382
Test name
Test status
Simulation time 1481180424 ps
CPU time 17.59 seconds
Started Jul 06 04:41:38 PM PDT 24
Finished Jul 06 04:41:56 PM PDT 24
Peak memory 216664 kb
Host smart-04c6d202-ff74-44a7-a6e9-b60369b4e536
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911765177 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2911765177
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.284299320
Short name T437
Test name
Test status
Simulation time 8916253973 ps
CPU time 33.84 seconds
Started Jul 06 04:41:40 PM PDT 24
Finished Jul 06 04:42:14 PM PDT 24
Peak memory 212072 kb
Host smart-9fed7925-f13d-4c1b-a9c2-b27a278a37de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284299320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.284299320
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.873295717
Short name T381
Test name
Test status
Simulation time 3766156821 ps
CPU time 31.11 seconds
Started Jul 06 04:41:41 PM PDT 24
Finished Jul 06 04:42:13 PM PDT 24
Peak memory 210452 kb
Host smart-5da7c8b7-dcd7-4513-94f1-e41feeceafc5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873295717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.873295717
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3557064020
Short name T391
Test name
Test status
Simulation time 3747442126 ps
CPU time 28.87 seconds
Started Jul 06 04:41:41 PM PDT 24
Finished Jul 06 04:42:10 PM PDT 24
Peak memory 210504 kb
Host smart-f13f5a18-492a-461d-b2e8-5b331c8e1bf8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557064020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3557064020
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.848587314
Short name T67
Test name
Test status
Simulation time 66023445458 ps
CPU time 79.77 seconds
Started Jul 06 04:41:54 PM PDT 24
Finished Jul 06 04:43:14 PM PDT 24
Peak memory 213760 kb
Host smart-3ceb0c07-69c8-4aeb-8030-c091b8623927
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848587314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.848587314
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.4049014751
Short name T404
Test name
Test status
Simulation time 1180321606 ps
CPU time 10.36 seconds
Started Jul 06 04:41:40 PM PDT 24
Finished Jul 06 04:41:50 PM PDT 24
Peak memory 211180 kb
Host smart-ca342254-c455-4165-80f8-c1e8f0ed921e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049014751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.4049014751
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3509784290
Short name T413
Test name
Test status
Simulation time 347893677 ps
CPU time 14.07 seconds
Started Jul 06 04:41:40 PM PDT 24
Finished Jul 06 04:41:55 PM PDT 24
Peak memory 217372 kb
Host smart-45333431-3d80-4d39-be39-f4be6f936946
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509784290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3509784290
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2519170203
Short name T115
Test name
Test status
Simulation time 3767135846 ps
CPU time 160.89 seconds
Started Jul 06 04:41:38 PM PDT 24
Finished Jul 06 04:44:19 PM PDT 24
Peak memory 213744 kb
Host smart-c9254907-4eb7-4cf5-b44b-c5db43434c5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519170203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2519170203
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.44409383
Short name T374
Test name
Test status
Simulation time 10348384480 ps
CPU time 22.8 seconds
Started Jul 06 04:41:57 PM PDT 24
Finished Jul 06 04:42:20 PM PDT 24
Peak memory 211932 kb
Host smart-dab00d1b-a91e-4665-8f5d-bbd5b53d49c9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44409383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_aliasi
ng.44409383
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2062259428
Short name T373
Test name
Test status
Simulation time 12748772961 ps
CPU time 26.94 seconds
Started Jul 06 04:41:44 PM PDT 24
Finished Jul 06 04:42:11 PM PDT 24
Peak memory 211716 kb
Host smart-9382836f-6603-48b6-970c-d379e99d8d3e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062259428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2062259428
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3868241408
Short name T433
Test name
Test status
Simulation time 399908557 ps
CPU time 11.95 seconds
Started Jul 06 04:41:39 PM PDT 24
Finished Jul 06 04:41:51 PM PDT 24
Peak memory 210552 kb
Host smart-531f5f1c-705f-4da3-a88c-c7854160b9d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868241408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3868241408
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1772444926
Short name T367
Test name
Test status
Simulation time 768635329 ps
CPU time 9.36 seconds
Started Jul 06 04:41:44 PM PDT 24
Finished Jul 06 04:41:54 PM PDT 24
Peak memory 216964 kb
Host smart-7574cac9-e601-4579-bf5e-19e898200310
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772444926 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1772444926
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1099920086
Short name T98
Test name
Test status
Simulation time 3365888982 ps
CPU time 28.16 seconds
Started Jul 06 04:41:40 PM PDT 24
Finished Jul 06 04:42:09 PM PDT 24
Peak memory 211104 kb
Host smart-d13d5a89-4044-42ab-9858-f19e1cec4072
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099920086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1099920086
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2477555597
Short name T399
Test name
Test status
Simulation time 8984798230 ps
CPU time 25.31 seconds
Started Jul 06 04:41:39 PM PDT 24
Finished Jul 06 04:42:05 PM PDT 24
Peak memory 210024 kb
Host smart-90c5f015-44fb-4353-ad82-ff2cab074ccb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477555597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2477555597
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2448616906
Short name T370
Test name
Test status
Simulation time 16256476477 ps
CPU time 32.04 seconds
Started Jul 06 04:41:41 PM PDT 24
Finished Jul 06 04:42:13 PM PDT 24
Peak memory 210724 kb
Host smart-866d71f0-c3b8-4c8a-9442-0562e9b8a693
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448616906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2448616906
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2524602164
Short name T78
Test name
Test status
Simulation time 73555596507 ps
CPU time 137.42 seconds
Started Jul 06 04:41:43 PM PDT 24
Finished Jul 06 04:44:01 PM PDT 24
Peak memory 213808 kb
Host smart-be8918b0-a6c9-4b2b-8456-1ff1c6014a99
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524602164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2524602164
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.22600893
Short name T403
Test name
Test status
Simulation time 8161189606 ps
CPU time 21.23 seconds
Started Jul 06 04:41:46 PM PDT 24
Finished Jul 06 04:42:07 PM PDT 24
Peak memory 212344 kb
Host smart-b12e2c0c-a671-44c6-968d-bfb284f30c8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22600893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_same_csr_outstanding.22600893
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.616061054
Short name T422
Test name
Test status
Simulation time 3989353852 ps
CPU time 23.81 seconds
Started Jul 06 04:41:39 PM PDT 24
Finished Jul 06 04:42:03 PM PDT 24
Peak memory 217032 kb
Host smart-081c878c-6c72-4a87-a6e8-dded306843ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616061054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.616061054
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2646607182
Short name T423
Test name
Test status
Simulation time 342103310 ps
CPU time 156.08 seconds
Started Jul 06 04:41:42 PM PDT 24
Finished Jul 06 04:44:18 PM PDT 24
Peak memory 214028 kb
Host smart-2d0898de-6998-43e3-9aca-aa1b8bee05e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646607182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2646607182
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2669609215
Short name T49
Test name
Test status
Simulation time 2089118636 ps
CPU time 20.85 seconds
Started Jul 06 04:41:55 PM PDT 24
Finished Jul 06 04:42:16 PM PDT 24
Peak memory 215760 kb
Host smart-e637b14c-90c1-449a-82b0-a8ae544cc81c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669609215 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2669609215
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3997833000
Short name T87
Test name
Test status
Simulation time 16496228301 ps
CPU time 29.87 seconds
Started Jul 06 04:41:44 PM PDT 24
Finished Jul 06 04:42:14 PM PDT 24
Peak memory 212000 kb
Host smart-7b567881-3d6b-4752-8e34-2e9fa3872e9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997833000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3997833000
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2730026796
Short name T435
Test name
Test status
Simulation time 25375666347 ps
CPU time 112.75 seconds
Started Jul 06 04:41:49 PM PDT 24
Finished Jul 06 04:43:42 PM PDT 24
Peak memory 213752 kb
Host smart-47af4702-72a4-4cb1-9b5e-97d9fe89212e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730026796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2730026796
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1252507015
Short name T395
Test name
Test status
Simulation time 19579901791 ps
CPU time 21.86 seconds
Started Jul 06 04:41:45 PM PDT 24
Finished Jul 06 04:42:08 PM PDT 24
Peak memory 212696 kb
Host smart-cfc16957-696a-470e-b2df-7f31a3393f1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252507015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1252507015
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1273225598
Short name T393
Test name
Test status
Simulation time 3957672790 ps
CPU time 33.96 seconds
Started Jul 06 04:41:42 PM PDT 24
Finished Jul 06 04:42:16 PM PDT 24
Peak memory 218048 kb
Host smart-d4bb0521-701a-488b-91ad-fac0339998f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273225598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1273225598
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2045658735
Short name T415
Test name
Test status
Simulation time 942398017 ps
CPU time 82.01 seconds
Started Jul 06 04:41:43 PM PDT 24
Finished Jul 06 04:43:05 PM PDT 24
Peak memory 213636 kb
Host smart-660d718d-8c25-4c27-a472-823a734b1e49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045658735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2045658735
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1258632506
Short name T392
Test name
Test status
Simulation time 5500771244 ps
CPU time 16.92 seconds
Started Jul 06 04:41:47 PM PDT 24
Finished Jul 06 04:42:04 PM PDT 24
Peak memory 215556 kb
Host smart-f966e96f-63ee-4390-857a-4c21ebecb818
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258632506 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1258632506
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2649356046
Short name T434
Test name
Test status
Simulation time 1718067313 ps
CPU time 19.2 seconds
Started Jul 06 04:41:43 PM PDT 24
Finished Jul 06 04:42:03 PM PDT 24
Peak memory 211424 kb
Host smart-2863aef2-46be-49b7-ac31-5eadc946fa88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649356046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2649356046
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3456021040
Short name T84
Test name
Test status
Simulation time 2757122711 ps
CPU time 38.37 seconds
Started Jul 06 04:41:44 PM PDT 24
Finished Jul 06 04:42:23 PM PDT 24
Peak memory 213748 kb
Host smart-38d8f0fe-d0bd-405e-bf27-6c75a45aa88b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456021040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3456021040
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2949348492
Short name T97
Test name
Test status
Simulation time 167324692 ps
CPU time 8.1 seconds
Started Jul 06 04:41:47 PM PDT 24
Finished Jul 06 04:41:56 PM PDT 24
Peak memory 211024 kb
Host smart-51d00d33-dffe-46b8-b26f-3e49c9ffc331
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949348492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2949348492
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.426619467
Short name T401
Test name
Test status
Simulation time 19714778903 ps
CPU time 26.19 seconds
Started Jul 06 04:41:45 PM PDT 24
Finished Jul 06 04:42:12 PM PDT 24
Peak memory 217488 kb
Host smart-f122e92e-9280-4357-bb1a-5c0c193e89c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426619467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.426619467
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2266423013
Short name T109
Test name
Test status
Simulation time 1439264202 ps
CPU time 88.49 seconds
Started Jul 06 04:41:45 PM PDT 24
Finished Jul 06 04:43:14 PM PDT 24
Peak memory 213544 kb
Host smart-e1d1c469-724b-4209-a91d-ece9dfbd2506
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266423013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2266423013
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.595686037
Short name T436
Test name
Test status
Simulation time 2740467905 ps
CPU time 23.68 seconds
Started Jul 06 04:41:43 PM PDT 24
Finished Jul 06 04:42:07 PM PDT 24
Peak memory 216736 kb
Host smart-aa6bb820-d423-45d7-b85d-cb56f0088254
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595686037 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.595686037
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3998834348
Short name T445
Test name
Test status
Simulation time 2738617774 ps
CPU time 24.46 seconds
Started Jul 06 04:41:59 PM PDT 24
Finished Jul 06 04:42:24 PM PDT 24
Peak memory 211612 kb
Host smart-80a59396-e17b-4412-a8fb-14c458ab057d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998834348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3998834348
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.102315196
Short name T420
Test name
Test status
Simulation time 17639840457 ps
CPU time 134.06 seconds
Started Jul 06 04:41:43 PM PDT 24
Finished Jul 06 04:43:58 PM PDT 24
Peak memory 210784 kb
Host smart-2b655d3f-fc3a-4460-9c00-93a595d18004
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102315196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.102315196
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.854628982
Short name T443
Test name
Test status
Simulation time 8191927964 ps
CPU time 31.21 seconds
Started Jul 06 04:41:45 PM PDT 24
Finished Jul 06 04:42:17 PM PDT 24
Peak memory 212340 kb
Host smart-0d60e4ae-a46f-49d8-be07-ea8c3a6b436c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854628982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.854628982
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2374153489
Short name T438
Test name
Test status
Simulation time 2860104195 ps
CPU time 29.53 seconds
Started Jul 06 04:41:45 PM PDT 24
Finished Jul 06 04:42:14 PM PDT 24
Peak memory 218132 kb
Host smart-af2eb2e8-c8a8-44a8-bc94-09bedb502c9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374153489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2374153489
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4014403296
Short name T430
Test name
Test status
Simulation time 2823418511 ps
CPU time 97.39 seconds
Started Jul 06 04:41:46 PM PDT 24
Finished Jul 06 04:43:23 PM PDT 24
Peak memory 213540 kb
Host smart-e392a272-74c6-477b-b863-b271834a2c3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014403296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.4014403296
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1991299971
Short name T362
Test name
Test status
Simulation time 3671719813 ps
CPU time 29.12 seconds
Started Jul 06 04:41:47 PM PDT 24
Finished Jul 06 04:42:16 PM PDT 24
Peak memory 216988 kb
Host smart-ef3f078d-b66f-4b9f-841e-835d682324a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991299971 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1991299971
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2095929487
Short name T406
Test name
Test status
Simulation time 174499226 ps
CPU time 8.21 seconds
Started Jul 06 04:41:53 PM PDT 24
Finished Jul 06 04:42:02 PM PDT 24
Peak memory 210256 kb
Host smart-b6f6097f-b10c-44ee-8614-6d390bedd3f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095929487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2095929487
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3872021910
Short name T85
Test name
Test status
Simulation time 53591017850 ps
CPU time 99.47 seconds
Started Jul 06 04:41:51 PM PDT 24
Finished Jul 06 04:43:30 PM PDT 24
Peak memory 213828 kb
Host smart-ec47a021-0c46-48cc-a286-e2e3f3892926
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872021910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3872021910
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1736836110
Short name T411
Test name
Test status
Simulation time 8509542807 ps
CPU time 32.55 seconds
Started Jul 06 04:41:45 PM PDT 24
Finished Jul 06 04:42:23 PM PDT 24
Peak memory 212240 kb
Host smart-fb2a07fb-87b1-4f74-a214-ad2a2d228c7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736836110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1736836110
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3374047743
Short name T388
Test name
Test status
Simulation time 7381578109 ps
CPU time 35.79 seconds
Started Jul 06 04:41:47 PM PDT 24
Finished Jul 06 04:42:23 PM PDT 24
Peak memory 217664 kb
Host smart-51cc7283-4a08-40b0-9a65-8057877bec16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374047743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3374047743
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.522729325
Short name T366
Test name
Test status
Simulation time 174239816 ps
CPU time 8.63 seconds
Started Jul 06 04:41:51 PM PDT 24
Finished Jul 06 04:42:00 PM PDT 24
Peak memory 214608 kb
Host smart-d5d742ff-76f9-4cd5-b199-76eaf2779992
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522729325 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.522729325
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1290584796
Short name T80
Test name
Test status
Simulation time 345601653 ps
CPU time 8.14 seconds
Started Jul 06 04:41:52 PM PDT 24
Finished Jul 06 04:42:00 PM PDT 24
Peak memory 210576 kb
Host smart-c422ea40-e12e-450e-8510-13848c994b7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290584796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1290584796
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2961827464
Short name T91
Test name
Test status
Simulation time 36908053993 ps
CPU time 93.78 seconds
Started Jul 06 04:41:44 PM PDT 24
Finished Jul 06 04:43:18 PM PDT 24
Peak memory 213792 kb
Host smart-6d415c6a-b5cb-440f-ae9a-2fbc9cd0b00b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961827464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2961827464
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1031320607
Short name T96
Test name
Test status
Simulation time 16931009997 ps
CPU time 27.17 seconds
Started Jul 06 04:41:44 PM PDT 24
Finished Jul 06 04:42:11 PM PDT 24
Peak memory 211980 kb
Host smart-551ad9c3-04f1-499b-8193-57d5c9931023
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031320607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1031320607
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3155612478
Short name T427
Test name
Test status
Simulation time 8587761734 ps
CPU time 24.44 seconds
Started Jul 06 04:41:45 PM PDT 24
Finished Jul 06 04:42:09 PM PDT 24
Peak memory 218656 kb
Host smart-cafdfc23-9fc3-417a-8508-494e65a6d463
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155612478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3155612478
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2815935512
Short name T389
Test name
Test status
Simulation time 9292495282 ps
CPU time 93.81 seconds
Started Jul 06 04:41:50 PM PDT 24
Finished Jul 06 04:43:24 PM PDT 24
Peak memory 213704 kb
Host smart-b236813a-775f-442e-ace9-17e01c4e5fc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815935512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2815935512
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2225352485
Short name T283
Test name
Test status
Simulation time 5472299555 ps
CPU time 17.23 seconds
Started Jul 06 05:33:09 PM PDT 24
Finished Jul 06 05:33:27 PM PDT 24
Peak memory 217616 kb
Host smart-347ffae9-eafb-4f49-b798-80ac55dc96de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225352485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2225352485
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2427081072
Short name T34
Test name
Test status
Simulation time 29409741894 ps
CPU time 415.11 seconds
Started Jul 06 05:33:09 PM PDT 24
Finished Jul 06 05:40:05 PM PDT 24
Peak memory 234264 kb
Host smart-d997d434-5417-4969-8321-d58ea3ed8c1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427081072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2427081072
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2655876583
Short name T138
Test name
Test status
Simulation time 5668228125 ps
CPU time 37.88 seconds
Started Jul 06 05:33:11 PM PDT 24
Finished Jul 06 05:33:49 PM PDT 24
Peak memory 219256 kb
Host smart-111c3ff6-f3c4-4eca-b6e4-9f66be894195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655876583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2655876583
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2835163907
Short name T187
Test name
Test status
Simulation time 4049242950 ps
CPU time 24.38 seconds
Started Jul 06 05:33:05 PM PDT 24
Finished Jul 06 05:33:29 PM PDT 24
Peak memory 219424 kb
Host smart-92ae6976-fd38-49b1-8fdb-9956ee9fd1c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2835163907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2835163907
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1045329447
Short name T23
Test name
Test status
Simulation time 4127484543 ps
CPU time 243.33 seconds
Started Jul 06 05:33:10 PM PDT 24
Finished Jul 06 05:37:14 PM PDT 24
Peak memory 237828 kb
Host smart-26d13313-d0ef-47c6-8e10-1daa7a95ffb9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045329447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1045329447
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1481344557
Short name T167
Test name
Test status
Simulation time 15790003724 ps
CPU time 51.17 seconds
Started Jul 06 05:33:06 PM PDT 24
Finished Jul 06 05:33:58 PM PDT 24
Peak memory 216148 kb
Host smart-49eb10dc-2b99-49cb-b9ad-d3dac708e49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481344557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1481344557
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.4236747688
Short name T182
Test name
Test status
Simulation time 740213289 ps
CPU time 45.43 seconds
Started Jul 06 05:33:05 PM PDT 24
Finished Jul 06 05:33:50 PM PDT 24
Peak memory 219348 kb
Host smart-6977662e-6131-4424-806e-14f9c35b8a17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236747688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.4236747688
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.4240793581
Short name T185
Test name
Test status
Simulation time 4288296101 ps
CPU time 31.87 seconds
Started Jul 06 05:33:09 PM PDT 24
Finished Jul 06 05:33:41 PM PDT 24
Peak memory 217312 kb
Host smart-d9f4f1dc-67af-4304-b2d8-443499df9a10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240793581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.4240793581
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2985954432
Short name T288
Test name
Test status
Simulation time 14213108421 ps
CPU time 268.22 seconds
Started Jul 06 05:33:09 PM PDT 24
Finished Jul 06 05:37:38 PM PDT 24
Peak memory 240000 kb
Host smart-782e8038-4df0-4cd5-ab87-7f6022e9ca3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985954432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2985954432
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3541191965
Short name T322
Test name
Test status
Simulation time 12121205165 ps
CPU time 38.24 seconds
Started Jul 06 05:33:10 PM PDT 24
Finished Jul 06 05:33:49 PM PDT 24
Peak memory 219324 kb
Host smart-69c14784-edb7-49bf-8f21-4d35d07f1207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541191965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3541191965
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1468459141
Short name T269
Test name
Test status
Simulation time 10432790836 ps
CPU time 22.26 seconds
Started Jul 06 05:33:11 PM PDT 24
Finished Jul 06 05:33:34 PM PDT 24
Peak memory 219348 kb
Host smart-35ac9e5d-bbe0-4e45-b6d1-55e9f2fc780e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1468459141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1468459141
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2199106130
Short name T26
Test name
Test status
Simulation time 14841913505 ps
CPU time 252.09 seconds
Started Jul 06 05:33:08 PM PDT 24
Finished Jul 06 05:37:21 PM PDT 24
Peak memory 238100 kb
Host smart-85aedff2-d61f-47dd-a23e-8153d581b9cc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199106130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2199106130
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.307663177
Short name T184
Test name
Test status
Simulation time 1380546267 ps
CPU time 20.28 seconds
Started Jul 06 05:33:09 PM PDT 24
Finished Jul 06 05:33:29 PM PDT 24
Peak memory 216436 kb
Host smart-15428a8f-83fe-4eb6-b93f-232f4f4586ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307663177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.307663177
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1410615422
Short name T267
Test name
Test status
Simulation time 17699294084 ps
CPU time 30.08 seconds
Started Jul 06 05:33:54 PM PDT 24
Finished Jul 06 05:34:24 PM PDT 24
Peak memory 217512 kb
Host smart-932f7bb7-a85a-4b17-8adb-73fdd70b776a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410615422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1410615422
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3506538536
Short name T134
Test name
Test status
Simulation time 4218229236 ps
CPU time 135.38 seconds
Started Jul 06 05:33:50 PM PDT 24
Finished Jul 06 05:36:06 PM PDT 24
Peak memory 228536 kb
Host smart-abd18fb5-3269-4764-896b-ad52515ec468
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506538536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3506538536
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2735104261
Short name T353
Test name
Test status
Simulation time 5457212469 ps
CPU time 29.38 seconds
Started Jul 06 05:33:47 PM PDT 24
Finished Jul 06 05:34:17 PM PDT 24
Peak memory 219380 kb
Host smart-6a1d8c1c-9945-481a-92ad-ccadcbc3620e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735104261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2735104261
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1018630236
Short name T160
Test name
Test status
Simulation time 20466219897 ps
CPU time 30.37 seconds
Started Jul 06 05:33:47 PM PDT 24
Finished Jul 06 05:34:18 PM PDT 24
Peak memory 219372 kb
Host smart-b51a1893-0424-40c5-947b-0b1060d81454
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1018630236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1018630236
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2739472806
Short name T352
Test name
Test status
Simulation time 3800791365 ps
CPU time 27.23 seconds
Started Jul 06 05:33:46 PM PDT 24
Finished Jul 06 05:34:13 PM PDT 24
Peak memory 216660 kb
Host smart-7ed51c17-7b8b-4c17-9b9f-fb2030354eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739472806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2739472806
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2818759120
Short name T15
Test name
Test status
Simulation time 7577206021 ps
CPU time 32.53 seconds
Started Jul 06 05:33:48 PM PDT 24
Finished Jul 06 05:34:21 PM PDT 24
Peak memory 214620 kb
Host smart-f70b93b0-f084-49af-8140-9a3cf2d33b53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818759120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2818759120
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3375520287
Short name T256
Test name
Test status
Simulation time 1372934548 ps
CPU time 8.35 seconds
Started Jul 06 05:33:52 PM PDT 24
Finished Jul 06 05:34:01 PM PDT 24
Peak memory 217156 kb
Host smart-1169bf6a-b6bf-47c8-accb-adc24c01db31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375520287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3375520287
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3902851778
Short name T228
Test name
Test status
Simulation time 6556809120 ps
CPU time 38.89 seconds
Started Jul 06 05:33:51 PM PDT 24
Finished Jul 06 05:34:31 PM PDT 24
Peak memory 215276 kb
Host smart-141e20f1-a7e7-4bc3-8e59-c4eea6bbdfea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902851778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3902851778
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1931174571
Short name T255
Test name
Test status
Simulation time 199102402 ps
CPU time 10.52 seconds
Started Jul 06 05:33:52 PM PDT 24
Finished Jul 06 05:34:03 PM PDT 24
Peak memory 219296 kb
Host smart-ead9ee9d-d22d-4406-97df-aca0a3f7575e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1931174571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1931174571
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3200060889
Short name T168
Test name
Test status
Simulation time 3820014554 ps
CPU time 20.86 seconds
Started Jul 06 05:33:51 PM PDT 24
Finished Jul 06 05:34:12 PM PDT 24
Peak memory 216472 kb
Host smart-325794f0-ecf6-4e6e-96c9-d819c946ad47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200060889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3200060889
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.550624882
Short name T251
Test name
Test status
Simulation time 16942566368 ps
CPU time 90.53 seconds
Started Jul 06 05:33:53 PM PDT 24
Finished Jul 06 05:35:23 PM PDT 24
Peak memory 220432 kb
Host smart-d351f36e-ce7f-4435-9d13-e99ac24fe911
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550624882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.550624882
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1323337693
Short name T158
Test name
Test status
Simulation time 1832263206 ps
CPU time 8.32 seconds
Started Jul 06 05:34:01 PM PDT 24
Finished Jul 06 05:34:10 PM PDT 24
Peak memory 217208 kb
Host smart-277c1271-b8f1-4e8f-84ef-bc2e01b58929
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323337693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1323337693
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.554923286
Short name T279
Test name
Test status
Simulation time 45491504011 ps
CPU time 426.56 seconds
Started Jul 06 05:33:58 PM PDT 24
Finished Jul 06 05:41:05 PM PDT 24
Peak memory 233816 kb
Host smart-6d456414-f30e-423f-a1d7-67e590499115
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554923286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.554923286
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1612297020
Short name T161
Test name
Test status
Simulation time 7670672301 ps
CPU time 60.71 seconds
Started Jul 06 05:33:58 PM PDT 24
Finished Jul 06 05:34:59 PM PDT 24
Peak memory 219364 kb
Host smart-c7ea958b-58d4-4e80-a39e-1250d6908d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612297020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1612297020
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.891821846
Short name T326
Test name
Test status
Simulation time 2401615250 ps
CPU time 23.75 seconds
Started Jul 06 05:33:52 PM PDT 24
Finished Jul 06 05:34:16 PM PDT 24
Peak memory 219388 kb
Host smart-a436b8bd-42b3-4f33-a3ac-f29dc114f479
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=891821846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.891821846
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.931970405
Short name T31
Test name
Test status
Simulation time 9622568894 ps
CPU time 52.44 seconds
Started Jul 06 05:33:53 PM PDT 24
Finished Jul 06 05:34:45 PM PDT 24
Peak memory 216480 kb
Host smart-493ee5d0-5e91-497d-a1c3-a38e47619a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931970405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.931970405
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1183958274
Short name T331
Test name
Test status
Simulation time 10580307718 ps
CPU time 96.38 seconds
Started Jul 06 05:33:54 PM PDT 24
Finished Jul 06 05:35:30 PM PDT 24
Peak memory 219376 kb
Host smart-b5cd4be2-735a-4699-bfec-83927f95b73a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183958274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1183958274
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.689028034
Short name T48
Test name
Test status
Simulation time 226310403254 ps
CPU time 2173.22 seconds
Started Jul 06 05:33:59 PM PDT 24
Finished Jul 06 06:10:12 PM PDT 24
Peak memory 247156 kb
Host smart-88e80267-645f-489d-8a51-cfd5caf57af1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689028034 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.689028034
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1005391949
Short name T360
Test name
Test status
Simulation time 174678327 ps
CPU time 8.61 seconds
Started Jul 06 05:34:05 PM PDT 24
Finished Jul 06 05:34:13 PM PDT 24
Peak memory 217188 kb
Host smart-56c98f3a-bf87-4f5c-b285-204fb4b259d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005391949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1005391949
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3180486903
Short name T240
Test name
Test status
Simulation time 5198440504 ps
CPU time 337.62 seconds
Started Jul 06 05:34:03 PM PDT 24
Finished Jul 06 05:39:41 PM PDT 24
Peak memory 218196 kb
Host smart-bc8f6fda-176a-45a7-a3ee-ba1a73c8bccc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180486903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3180486903
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3921276710
Short name T211
Test name
Test status
Simulation time 19509268672 ps
CPU time 40.1 seconds
Started Jul 06 05:34:01 PM PDT 24
Finished Jul 06 05:34:42 PM PDT 24
Peak memory 219308 kb
Host smart-40c127e9-5550-4545-ab1a-540184f02919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921276710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3921276710
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.939216376
Short name T301
Test name
Test status
Simulation time 2978512888 ps
CPU time 28.55 seconds
Started Jul 06 05:34:01 PM PDT 24
Finished Jul 06 05:34:30 PM PDT 24
Peak memory 219412 kb
Host smart-932e6caf-df87-4bbe-88a0-b579d0b3a86d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=939216376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.939216376
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3107139763
Short name T162
Test name
Test status
Simulation time 1252909123 ps
CPU time 19.77 seconds
Started Jul 06 05:34:00 PM PDT 24
Finished Jul 06 05:34:20 PM PDT 24
Peak memory 218116 kb
Host smart-eb2223a0-114c-4a18-aab0-b831744d0c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107139763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3107139763
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1440413082
Short name T223
Test name
Test status
Simulation time 51325451530 ps
CPU time 212.91 seconds
Started Jul 06 05:34:00 PM PDT 24
Finished Jul 06 05:37:33 PM PDT 24
Peak memory 227636 kb
Host smart-d16f8d09-3cd0-47f2-ac74-4bc597e402ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440413082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1440413082
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.533428566
Short name T153
Test name
Test status
Simulation time 3462950308 ps
CPU time 15.22 seconds
Started Jul 06 05:34:07 PM PDT 24
Finished Jul 06 05:34:23 PM PDT 24
Peak memory 217156 kb
Host smart-d684d24b-ef9a-4760-89ac-ea6f0b9392bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533428566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.533428566
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3990224508
Short name T126
Test name
Test status
Simulation time 130407723508 ps
CPU time 699.27 seconds
Started Jul 06 05:34:04 PM PDT 24
Finished Jul 06 05:45:44 PM PDT 24
Peak memory 214976 kb
Host smart-fc77203c-e701-43b2-a25a-b9d94014c506
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990224508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3990224508
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1951115149
Short name T311
Test name
Test status
Simulation time 24028738650 ps
CPU time 54.55 seconds
Started Jul 06 05:34:05 PM PDT 24
Finished Jul 06 05:35:00 PM PDT 24
Peak memory 219416 kb
Host smart-68ebe454-f530-4fa2-a269-ab6e475a19e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951115149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1951115149
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.4155066003
Short name T304
Test name
Test status
Simulation time 19444588346 ps
CPU time 31.61 seconds
Started Jul 06 05:34:07 PM PDT 24
Finished Jul 06 05:34:39 PM PDT 24
Peak memory 219392 kb
Host smart-2abe5325-6371-495f-b28f-4dc101d80dfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4155066003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.4155066003
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1359801173
Short name T191
Test name
Test status
Simulation time 6512053350 ps
CPU time 69.14 seconds
Started Jul 06 05:34:09 PM PDT 24
Finished Jul 06 05:35:18 PM PDT 24
Peak memory 217636 kb
Host smart-575f46dc-4e11-4043-95d0-6341531c5fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359801173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1359801173
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3905893144
Short name T337
Test name
Test status
Simulation time 22465924742 ps
CPU time 213.81 seconds
Started Jul 06 05:34:04 PM PDT 24
Finished Jul 06 05:37:38 PM PDT 24
Peak memory 235716 kb
Host smart-e88adb9a-d7e1-4d38-8875-915e1ce82bb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905893144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3905893144
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1557399634
Short name T174
Test name
Test status
Simulation time 15527675050 ps
CPU time 26.82 seconds
Started Jul 06 05:34:05 PM PDT 24
Finished Jul 06 05:34:33 PM PDT 24
Peak memory 217452 kb
Host smart-8deb4335-2c34-4e0c-b468-d08c77b67550
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557399634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1557399634
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1994004830
Short name T220
Test name
Test status
Simulation time 93627585980 ps
CPU time 474.89 seconds
Started Jul 06 05:34:04 PM PDT 24
Finished Jul 06 05:41:59 PM PDT 24
Peak memory 236256 kb
Host smart-d45a3983-a5a6-4112-92d0-25a3100c6581
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994004830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1994004830
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.140732672
Short name T342
Test name
Test status
Simulation time 332764077 ps
CPU time 19.09 seconds
Started Jul 06 05:34:04 PM PDT 24
Finished Jul 06 05:34:24 PM PDT 24
Peak memory 219328 kb
Host smart-7fb5e373-1e6c-4ce7-baca-a01d9a9c224a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140732672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.140732672
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3981976363
Short name T101
Test name
Test status
Simulation time 354478756 ps
CPU time 10.22 seconds
Started Jul 06 05:34:08 PM PDT 24
Finished Jul 06 05:34:19 PM PDT 24
Peak memory 219348 kb
Host smart-1ebb9f18-c8e7-4f63-94da-2dd3870d719d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3981976363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3981976363
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.115089196
Short name T124
Test name
Test status
Simulation time 3379920443 ps
CPU time 43.88 seconds
Started Jul 06 05:34:05 PM PDT 24
Finished Jul 06 05:34:50 PM PDT 24
Peak memory 216372 kb
Host smart-e59b791d-1130-4393-aa7f-043acfe31af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115089196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.115089196
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3864579179
Short name T133
Test name
Test status
Simulation time 66080672707 ps
CPU time 72.48 seconds
Started Jul 06 05:34:03 PM PDT 24
Finished Jul 06 05:35:16 PM PDT 24
Peak memory 219816 kb
Host smart-e1ee1933-a962-409b-89cc-4db912792131
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864579179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3864579179
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3323798377
Short name T292
Test name
Test status
Simulation time 159664475749 ps
CPU time 450.36 seconds
Started Jul 06 05:34:09 PM PDT 24
Finished Jul 06 05:41:39 PM PDT 24
Peak memory 237516 kb
Host smart-26b5b06d-8334-4950-ba02-2521d0b36e3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323798377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3323798377
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3432805283
Short name T194
Test name
Test status
Simulation time 12313439231 ps
CPU time 38.52 seconds
Started Jul 06 05:34:12 PM PDT 24
Finished Jul 06 05:34:51 PM PDT 24
Peak memory 219268 kb
Host smart-6a92304e-b694-4542-a7bf-6f6136e8b923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432805283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3432805283
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3581353189
Short name T231
Test name
Test status
Simulation time 26792973251 ps
CPU time 22.39 seconds
Started Jul 06 05:34:12 PM PDT 24
Finished Jul 06 05:34:35 PM PDT 24
Peak memory 217776 kb
Host smart-3c3b0e88-65e2-4401-a55f-34a0917f7677
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3581353189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3581353189
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2326395237
Short name T274
Test name
Test status
Simulation time 350622346 ps
CPU time 20.42 seconds
Started Jul 06 05:34:07 PM PDT 24
Finished Jul 06 05:34:28 PM PDT 24
Peak memory 216188 kb
Host smart-e7c03f55-2e2d-4d94-ab53-d0c21010c00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326395237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2326395237
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3962141773
Short name T18
Test name
Test status
Simulation time 2573831494 ps
CPU time 33.39 seconds
Started Jul 06 05:34:10 PM PDT 24
Finished Jul 06 05:34:44 PM PDT 24
Peak memory 214912 kb
Host smart-bef2dc01-3cf1-4b0e-9c1f-d0e41b520f49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962141773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3962141773
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2827219051
Short name T58
Test name
Test status
Simulation time 6893639408 ps
CPU time 28.69 seconds
Started Jul 06 05:34:17 PM PDT 24
Finished Jul 06 05:34:46 PM PDT 24
Peak memory 217652 kb
Host smart-91f5283e-a326-4682-b59c-27bba1ec0d93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827219051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2827219051
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1053735719
Short name T216
Test name
Test status
Simulation time 88041550733 ps
CPU time 894.55 seconds
Started Jul 06 05:34:11 PM PDT 24
Finished Jul 06 05:49:05 PM PDT 24
Peak memory 240048 kb
Host smart-8a861a63-3bcb-4390-9844-a9d2623e474a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053735719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1053735719
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3971973268
Short name T319
Test name
Test status
Simulation time 448108270 ps
CPU time 19.56 seconds
Started Jul 06 05:34:11 PM PDT 24
Finished Jul 06 05:34:31 PM PDT 24
Peak memory 219260 kb
Host smart-73fe9cec-6961-42d2-a886-771aa6b53402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971973268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3971973268
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.673263367
Short name T333
Test name
Test status
Simulation time 2428237233 ps
CPU time 23.51 seconds
Started Jul 06 05:34:12 PM PDT 24
Finished Jul 06 05:34:36 PM PDT 24
Peak memory 219448 kb
Host smart-a316e790-64a2-4bfc-9015-d05e4080487b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=673263367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.673263367
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1870358147
Short name T257
Test name
Test status
Simulation time 1381490313 ps
CPU time 20.3 seconds
Started Jul 06 05:34:09 PM PDT 24
Finished Jul 06 05:34:30 PM PDT 24
Peak memory 216588 kb
Host smart-2910be75-783a-4910-976a-a7cf992aa93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870358147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1870358147
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.589428350
Short name T118
Test name
Test status
Simulation time 49581140940 ps
CPU time 110.37 seconds
Started Jul 06 05:34:12 PM PDT 24
Finished Jul 06 05:36:02 PM PDT 24
Peak memory 219344 kb
Host smart-562d9484-01bb-4be0-a42d-2fc135bf30cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589428350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.589428350
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1484615979
Short name T317
Test name
Test status
Simulation time 174492309 ps
CPU time 8.28 seconds
Started Jul 06 05:34:17 PM PDT 24
Finished Jul 06 05:34:25 PM PDT 24
Peak memory 217244 kb
Host smart-89a71312-7c5f-4c17-b3a0-2955040f9522
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484615979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1484615979
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1747983418
Short name T43
Test name
Test status
Simulation time 381595257464 ps
CPU time 672.56 seconds
Started Jul 06 05:34:16 PM PDT 24
Finished Jul 06 05:45:29 PM PDT 24
Peak memory 225372 kb
Host smart-d2f62083-715c-489d-88c1-61b8636e70f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747983418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1747983418
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3378432890
Short name T359
Test name
Test status
Simulation time 119957992981 ps
CPU time 64.38 seconds
Started Jul 06 05:34:15 PM PDT 24
Finished Jul 06 05:35:20 PM PDT 24
Peak memory 219384 kb
Host smart-d42ef589-e04e-4ec4-94da-465944465909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378432890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3378432890
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.4123734952
Short name T175
Test name
Test status
Simulation time 1378701004 ps
CPU time 19.38 seconds
Started Jul 06 05:34:17 PM PDT 24
Finished Jul 06 05:34:36 PM PDT 24
Peak memory 219284 kb
Host smart-427b468b-6552-450a-a228-2203e287eb4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4123734952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.4123734952
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.832858158
Short name T210
Test name
Test status
Simulation time 8757175952 ps
CPU time 78.87 seconds
Started Jul 06 05:34:15 PM PDT 24
Finished Jul 06 05:35:35 PM PDT 24
Peak memory 216744 kb
Host smart-9e6a99c5-8ee9-4ceb-b98f-b6a9d0497f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832858158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.832858158
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.4098999152
Short name T236
Test name
Test status
Simulation time 7427058983 ps
CPU time 39.63 seconds
Started Jul 06 05:34:16 PM PDT 24
Finished Jul 06 05:34:56 PM PDT 24
Peak memory 219264 kb
Host smart-4d3b1dcf-e9f4-48d9-8f33-1ad6541b4026
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098999152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.4098999152
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2786346624
Short name T47
Test name
Test status
Simulation time 28874564419 ps
CPU time 1242.02 seconds
Started Jul 06 05:34:16 PM PDT 24
Finished Jul 06 05:54:59 PM PDT 24
Peak memory 235896 kb
Host smart-15a0b83f-1197-4024-88bd-443829be831a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786346624 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.2786346624
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.422970895
Short name T291
Test name
Test status
Simulation time 4299403838 ps
CPU time 32.62 seconds
Started Jul 06 05:34:21 PM PDT 24
Finished Jul 06 05:34:53 PM PDT 24
Peak memory 217468 kb
Host smart-eb53c454-9fd2-433e-a437-c6905e813218
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422970895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.422970895
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2495086449
Short name T285
Test name
Test status
Simulation time 70310418274 ps
CPU time 712.77 seconds
Started Jul 06 05:34:17 PM PDT 24
Finished Jul 06 05:46:10 PM PDT 24
Peak memory 248376 kb
Host smart-0ac7bf47-3a5d-44c1-a8e5-180341538f66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495086449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2495086449
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3855878025
Short name T100
Test name
Test status
Simulation time 42025223230 ps
CPU time 34.66 seconds
Started Jul 06 05:34:17 PM PDT 24
Finished Jul 06 05:34:52 PM PDT 24
Peak memory 211948 kb
Host smart-798aa4b7-6f1d-455b-8510-f47250a85a0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3855878025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3855878025
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3245970193
Short name T19
Test name
Test status
Simulation time 15520102072 ps
CPU time 41.9 seconds
Started Jul 06 05:34:15 PM PDT 24
Finished Jul 06 05:34:57 PM PDT 24
Peak memory 215980 kb
Host smart-69170078-e524-4f02-ad55-63c4eddda621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245970193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3245970193
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1591413608
Short name T169
Test name
Test status
Simulation time 824685687 ps
CPU time 22.17 seconds
Started Jul 06 05:34:14 PM PDT 24
Finished Jul 06 05:34:37 PM PDT 24
Peak memory 219048 kb
Host smart-20c1b776-f46b-40c6-a8d4-e214a3ca25af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591413608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1591413608
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.111068168
Short name T149
Test name
Test status
Simulation time 767267192 ps
CPU time 13.91 seconds
Started Jul 06 05:33:15 PM PDT 24
Finished Jul 06 05:33:30 PM PDT 24
Peak memory 217140 kb
Host smart-4625ac09-6e7c-4fdf-b360-181ad8c2e814
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111068168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.111068168
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.854692022
Short name T327
Test name
Test status
Simulation time 408520033624 ps
CPU time 393.81 seconds
Started Jul 06 05:33:16 PM PDT 24
Finished Jul 06 05:39:51 PM PDT 24
Peak memory 236396 kb
Host smart-847c359c-9fa9-48d9-ab6b-5882642d167e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854692022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.854692022
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1147457430
Short name T260
Test name
Test status
Simulation time 5802438885 ps
CPU time 37.79 seconds
Started Jul 06 05:33:15 PM PDT 24
Finished Jul 06 05:33:53 PM PDT 24
Peak memory 215664 kb
Host smart-9242b49c-ef6e-45c5-8a1c-7c29ee076fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147457430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1147457430
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1445381521
Short name T192
Test name
Test status
Simulation time 5034046483 ps
CPU time 25.29 seconds
Started Jul 06 05:33:18 PM PDT 24
Finished Jul 06 05:33:43 PM PDT 24
Peak memory 212024 kb
Host smart-7387e8c4-9857-4e6d-8d81-3f44cf2b629c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1445381521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1445381521
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.834358405
Short name T27
Test name
Test status
Simulation time 303401374 ps
CPU time 119.05 seconds
Started Jul 06 05:33:17 PM PDT 24
Finished Jul 06 05:35:16 PM PDT 24
Peak memory 236448 kb
Host smart-6adfbcae-9ef4-47af-b667-e67e0326ef3f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834358405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.834358405
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1033343954
Short name T120
Test name
Test status
Simulation time 11936810740 ps
CPU time 63.3 seconds
Started Jul 06 05:33:16 PM PDT 24
Finished Jul 06 05:34:20 PM PDT 24
Peak memory 219388 kb
Host smart-d90469d8-f5c8-427d-a4ae-99be1f59a9ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033343954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1033343954
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3462396728
Short name T222
Test name
Test status
Simulation time 8369941656 ps
CPU time 33.07 seconds
Started Jul 06 05:34:21 PM PDT 24
Finished Jul 06 05:34:54 PM PDT 24
Peak memory 217600 kb
Host smart-f695ba7c-0a31-4b5d-a10b-9e5107df3077
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462396728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3462396728
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1543996420
Short name T247
Test name
Test status
Simulation time 78200983301 ps
CPU time 507.72 seconds
Started Jul 06 05:34:21 PM PDT 24
Finished Jul 06 05:42:49 PM PDT 24
Peak memory 233884 kb
Host smart-13a231db-fb3c-4ec6-ad4d-19454907dbda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543996420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1543996420
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2195133171
Short name T307
Test name
Test status
Simulation time 24376566974 ps
CPU time 32.9 seconds
Started Jul 06 05:34:21 PM PDT 24
Finished Jul 06 05:34:54 PM PDT 24
Peak memory 219372 kb
Host smart-006283f9-d2a2-4ce4-8ca5-7f145a9dd5f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2195133171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2195133171
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.1321790768
Short name T254
Test name
Test status
Simulation time 3979474009 ps
CPU time 36.22 seconds
Started Jul 06 05:34:20 PM PDT 24
Finished Jul 06 05:34:56 PM PDT 24
Peak memory 215512 kb
Host smart-316baf8e-0434-4072-972c-76d172309250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321790768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.1321790768
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.1585946061
Short name T44
Test name
Test status
Simulation time 10300261708 ps
CPU time 127.44 seconds
Started Jul 06 05:34:21 PM PDT 24
Finished Jul 06 05:36:29 PM PDT 24
Peak memory 219428 kb
Host smart-91b45e0f-5e82-45fb-b15f-c3b0cc7223ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585946061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.1585946061
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.473018987
Short name T5
Test name
Test status
Simulation time 3619041948 ps
CPU time 19.39 seconds
Started Jul 06 05:34:26 PM PDT 24
Finished Jul 06 05:34:46 PM PDT 24
Peak memory 217352 kb
Host smart-dadc77ec-8c85-4ceb-9de7-72b93dbeaedc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473018987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.473018987
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.4085765892
Short name T17
Test name
Test status
Simulation time 21287181772 ps
CPU time 198.6 seconds
Started Jul 06 05:34:27 PM PDT 24
Finished Jul 06 05:37:46 PM PDT 24
Peak memory 216904 kb
Host smart-fa23a861-a80a-4717-a311-0f1e78e26626
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085765892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.4085765892
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.983806999
Short name T305
Test name
Test status
Simulation time 7362191481 ps
CPU time 60.76 seconds
Started Jul 06 05:34:24 PM PDT 24
Finished Jul 06 05:35:25 PM PDT 24
Peak memory 219380 kb
Host smart-477f8426-4751-4114-927a-4be14946807d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983806999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.983806999
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2043675033
Short name T350
Test name
Test status
Simulation time 5041167057 ps
CPU time 26.04 seconds
Started Jul 06 05:34:27 PM PDT 24
Finished Jul 06 05:34:54 PM PDT 24
Peak memory 217708 kb
Host smart-94e4fd0b-fa60-4a1d-9314-594e3ac79022
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2043675033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2043675033
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2892159350
Short name T183
Test name
Test status
Simulation time 12484639866 ps
CPU time 43.92 seconds
Started Jul 06 05:34:20 PM PDT 24
Finished Jul 06 05:35:04 PM PDT 24
Peak memory 216656 kb
Host smart-ee396e9e-951c-46c6-be5f-a45550ca0a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892159350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2892159350
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.468310374
Short name T354
Test name
Test status
Simulation time 25169172448 ps
CPU time 151.46 seconds
Started Jul 06 05:34:21 PM PDT 24
Finished Jul 06 05:36:53 PM PDT 24
Peak memory 219448 kb
Host smart-20e0af0a-c155-4ccd-8eb7-f17c5c68851a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468310374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.468310374
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3515083582
Short name T193
Test name
Test status
Simulation time 3316276439 ps
CPU time 19.58 seconds
Started Jul 06 05:34:30 PM PDT 24
Finished Jul 06 05:34:50 PM PDT 24
Peak memory 217160 kb
Host smart-7df34ffc-a361-4a3c-8a35-55fffc6bdbe8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515083582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3515083582
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.4146436868
Short name T252
Test name
Test status
Simulation time 52772361415 ps
CPU time 550.16 seconds
Started Jul 06 05:34:27 PM PDT 24
Finished Jul 06 05:43:37 PM PDT 24
Peak memory 225660 kb
Host smart-024869ac-aadf-4000-8940-761f8c534e1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146436868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.4146436868
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.865170910
Short name T36
Test name
Test status
Simulation time 688325170 ps
CPU time 19.84 seconds
Started Jul 06 05:34:29 PM PDT 24
Finished Jul 06 05:34:49 PM PDT 24
Peak memory 219272 kb
Host smart-10cbc5b2-2d3e-4712-8f6b-987eb51f0f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865170910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.865170910
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.59567392
Short name T119
Test name
Test status
Simulation time 16443381908 ps
CPU time 26.58 seconds
Started Jul 06 05:34:31 PM PDT 24
Finished Jul 06 05:34:58 PM PDT 24
Peak memory 212052 kb
Host smart-27daabd3-fcad-4701-874b-a38926da4b32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=59567392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.59567392
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2415568899
Short name T197
Test name
Test status
Simulation time 360831804 ps
CPU time 20.82 seconds
Started Jul 06 05:34:25 PM PDT 24
Finished Jul 06 05:34:46 PM PDT 24
Peak memory 216348 kb
Host smart-d9b4fcfa-c07c-41c5-adb8-adde3eddbefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415568899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2415568899
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.4244405151
Short name T218
Test name
Test status
Simulation time 19162853182 ps
CPU time 124.07 seconds
Started Jul 06 05:34:27 PM PDT 24
Finished Jul 06 05:36:31 PM PDT 24
Peak memory 219384 kb
Host smart-c98fdccf-7ad9-4691-88ac-8d259f33af6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244405151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.4244405151
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1430455459
Short name T57
Test name
Test status
Simulation time 3354676501 ps
CPU time 28.18 seconds
Started Jul 06 05:34:31 PM PDT 24
Finished Jul 06 05:35:00 PM PDT 24
Peak memory 217312 kb
Host smart-05149c09-a137-4ef2-8678-143e5662af1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430455459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1430455459
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.146999263
Short name T8
Test name
Test status
Simulation time 127446696368 ps
CPU time 690.16 seconds
Started Jul 06 05:34:33 PM PDT 24
Finished Jul 06 05:46:03 PM PDT 24
Peak memory 225008 kb
Host smart-101fc5d1-1ed8-4991-ac78-dc393d0af2a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146999263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.146999263
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2023237147
Short name T2
Test name
Test status
Simulation time 347733278 ps
CPU time 19.42 seconds
Started Jul 06 05:34:33 PM PDT 24
Finished Jul 06 05:34:53 PM PDT 24
Peak memory 219352 kb
Host smart-1d3bf62b-bb5b-4eda-93dc-5e6285b82d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023237147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2023237147
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1816189342
Short name T33
Test name
Test status
Simulation time 2215416224 ps
CPU time 22.77 seconds
Started Jul 06 05:34:29 PM PDT 24
Finished Jul 06 05:34:52 PM PDT 24
Peak memory 219384 kb
Host smart-e549e210-ad32-48f5-a588-e70722c5e9a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1816189342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1816189342
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1805690954
Short name T332
Test name
Test status
Simulation time 4149594508 ps
CPU time 62.07 seconds
Started Jul 06 05:34:32 PM PDT 24
Finished Jul 06 05:35:35 PM PDT 24
Peak memory 219556 kb
Host smart-ddec9247-0c1d-4041-91eb-686eb417f5f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805690954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1805690954
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.4029831707
Short name T198
Test name
Test status
Simulation time 10602853336 ps
CPU time 24.1 seconds
Started Jul 06 05:34:38 PM PDT 24
Finished Jul 06 05:35:03 PM PDT 24
Peak memory 217604 kb
Host smart-51f61bcc-c408-4a0d-b430-09c165fec7ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029831707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.4029831707
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.376601250
Short name T224
Test name
Test status
Simulation time 24908359323 ps
CPU time 239.72 seconds
Started Jul 06 05:34:37 PM PDT 24
Finished Jul 06 05:38:37 PM PDT 24
Peak memory 224848 kb
Host smart-221f73b3-9b12-43df-8736-bf1a8151dd5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376601250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.376601250
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.434569680
Short name T135
Test name
Test status
Simulation time 8771870909 ps
CPU time 71.63 seconds
Started Jul 06 05:34:36 PM PDT 24
Finished Jul 06 05:35:48 PM PDT 24
Peak memory 219316 kb
Host smart-e7dd08ed-c72a-4fd8-8e56-0e8783e16488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434569680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.434569680
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.671518328
Short name T258
Test name
Test status
Simulation time 2012604946 ps
CPU time 21.15 seconds
Started Jul 06 05:34:30 PM PDT 24
Finished Jul 06 05:34:51 PM PDT 24
Peak memory 211384 kb
Host smart-98c0c84a-4c56-4fa8-93a7-826a6f47da1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=671518328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.671518328
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.2009774712
Short name T203
Test name
Test status
Simulation time 7132339486 ps
CPU time 68.27 seconds
Started Jul 06 05:34:31 PM PDT 24
Finished Jul 06 05:35:40 PM PDT 24
Peak memory 217008 kb
Host smart-ee5a3592-cabc-45ca-b900-6cd878a6076c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009774712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.2009774712
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.4239979607
Short name T195
Test name
Test status
Simulation time 29484190503 ps
CPU time 102.85 seconds
Started Jul 06 05:34:30 PM PDT 24
Finished Jul 06 05:36:14 PM PDT 24
Peak memory 219388 kb
Host smart-906591ec-6347-438b-a49a-4bd1ccecc775
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239979607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.4239979607
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3836071299
Short name T271
Test name
Test status
Simulation time 15552039314 ps
CPU time 18.72 seconds
Started Jul 06 05:34:42 PM PDT 24
Finished Jul 06 05:35:01 PM PDT 24
Peak memory 217476 kb
Host smart-432bbf74-aa05-448a-aa1e-6d14f827f6dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836071299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3836071299
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.479817111
Short name T172
Test name
Test status
Simulation time 182347730952 ps
CPU time 436.56 seconds
Started Jul 06 05:34:40 PM PDT 24
Finished Jul 06 05:41:57 PM PDT 24
Peak memory 227748 kb
Host smart-a4f0e145-5f02-48d9-990b-8aadd889dc4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479817111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.479817111
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1693198214
Short name T202
Test name
Test status
Simulation time 689519961 ps
CPU time 19.87 seconds
Started Jul 06 05:34:40 PM PDT 24
Finished Jul 06 05:35:01 PM PDT 24
Peak memory 219264 kb
Host smart-7c100c86-4c2b-4559-abb5-d522fed8d3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693198214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1693198214
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1866815608
Short name T229
Test name
Test status
Simulation time 951644465 ps
CPU time 16.52 seconds
Started Jul 06 05:34:42 PM PDT 24
Finished Jul 06 05:34:59 PM PDT 24
Peak memory 219280 kb
Host smart-750df664-17d6-44d7-93f3-d6ff097122da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1866815608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1866815608
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.82292653
Short name T275
Test name
Test status
Simulation time 348445430 ps
CPU time 20.65 seconds
Started Jul 06 05:34:36 PM PDT 24
Finished Jul 06 05:34:57 PM PDT 24
Peak memory 216480 kb
Host smart-e22f7a37-d5fc-4edf-900f-1134f7dc0096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82292653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.82292653
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1879473545
Short name T338
Test name
Test status
Simulation time 1260030907 ps
CPU time 41.23 seconds
Started Jul 06 05:34:38 PM PDT 24
Finished Jul 06 05:35:20 PM PDT 24
Peak memory 219048 kb
Host smart-69f0be65-24b6-4e9d-8a4e-658669951275
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879473545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1879473545
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2321283449
Short name T12
Test name
Test status
Simulation time 67539674216 ps
CPU time 538.64 seconds
Started Jul 06 05:34:46 PM PDT 24
Finished Jul 06 05:43:45 PM PDT 24
Peak memory 232364 kb
Host smart-cb999674-4ce8-4a72-9044-95803e10847a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321283449 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.2321283449
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.4205120687
Short name T156
Test name
Test status
Simulation time 2502699050 ps
CPU time 22.11 seconds
Started Jul 06 05:34:46 PM PDT 24
Finished Jul 06 05:35:09 PM PDT 24
Peak memory 217356 kb
Host smart-0da99abc-e9bd-46b1-a934-4380e718ac32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205120687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.4205120687
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2881388898
Short name T234
Test name
Test status
Simulation time 79717130057 ps
CPU time 377.6 seconds
Started Jul 06 05:34:48 PM PDT 24
Finished Jul 06 05:41:06 PM PDT 24
Peak memory 224776 kb
Host smart-e2855a43-f23e-41cb-9a12-6549eaec3e8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881388898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2881388898
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3436029461
Short name T314
Test name
Test status
Simulation time 26796081716 ps
CPU time 62.59 seconds
Started Jul 06 05:34:42 PM PDT 24
Finished Jul 06 05:35:45 PM PDT 24
Peak memory 219380 kb
Host smart-e29fbadf-f8a8-439c-9a54-a17d012f8f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436029461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3436029461
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.4176652093
Short name T336
Test name
Test status
Simulation time 1405093545 ps
CPU time 12.38 seconds
Started Jul 06 05:34:47 PM PDT 24
Finished Jul 06 05:34:59 PM PDT 24
Peak memory 218772 kb
Host smart-1adebc9a-ca8a-4261-85bf-72bc31ba5e9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4176652093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.4176652093
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.637826676
Short name T150
Test name
Test status
Simulation time 689358953 ps
CPU time 20.33 seconds
Started Jul 06 05:34:42 PM PDT 24
Finished Jul 06 05:35:03 PM PDT 24
Peak memory 216464 kb
Host smart-c13f941d-7eec-4a3a-bf54-a62ed41e4436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637826676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.637826676
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.574790766
Short name T16
Test name
Test status
Simulation time 48116995688 ps
CPU time 104.98 seconds
Started Jul 06 05:34:47 PM PDT 24
Finished Jul 06 05:36:32 PM PDT 24
Peak memory 217008 kb
Host smart-37361beb-5e08-44ed-816f-41a9a5ad2ef3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574790766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.574790766
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.575608863
Short name T173
Test name
Test status
Simulation time 4570203847 ps
CPU time 20.68 seconds
Started Jul 06 05:34:54 PM PDT 24
Finished Jul 06 05:35:15 PM PDT 24
Peak memory 217584 kb
Host smart-03c707d3-2399-436a-9704-c40cce10ac76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575608863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.575608863
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3683215665
Short name T46
Test name
Test status
Simulation time 194767733114 ps
CPU time 502.22 seconds
Started Jul 06 05:34:47 PM PDT 24
Finished Jul 06 05:43:09 PM PDT 24
Peak memory 237944 kb
Host smart-3c498840-c279-4472-98d5-d8654949413d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683215665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3683215665
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.4141614266
Short name T339
Test name
Test status
Simulation time 5359846399 ps
CPU time 45.57 seconds
Started Jul 06 05:34:53 PM PDT 24
Finished Jul 06 05:35:39 PM PDT 24
Peak memory 219384 kb
Host smart-8b4485a5-2a72-4e23-856b-94a2421f791c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141614266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.4141614266
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3864734559
Short name T219
Test name
Test status
Simulation time 1641415494 ps
CPU time 19.8 seconds
Started Jul 06 05:34:47 PM PDT 24
Finished Jul 06 05:35:07 PM PDT 24
Peak memory 219324 kb
Host smart-03ce4cb0-808b-438b-9fad-a0c38a7b027e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3864734559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3864734559
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3312281596
Short name T105
Test name
Test status
Simulation time 3941147100 ps
CPU time 45.21 seconds
Started Jul 06 05:34:41 PM PDT 24
Finished Jul 06 05:35:27 PM PDT 24
Peak memory 216632 kb
Host smart-c53f86df-795c-44e5-af5a-74ddd2b6cd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312281596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3312281596
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1612920366
Short name T207
Test name
Test status
Simulation time 563728212 ps
CPU time 34.25 seconds
Started Jul 06 05:34:46 PM PDT 24
Finished Jul 06 05:35:21 PM PDT 24
Peak memory 219300 kb
Host smart-28bf38c5-b426-42f6-9bb3-f6b45658de2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612920366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1612920366
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.51142347
Short name T59
Test name
Test status
Simulation time 3163150335 ps
CPU time 25.06 seconds
Started Jul 06 05:34:55 PM PDT 24
Finished Jul 06 05:35:20 PM PDT 24
Peak memory 217104 kb
Host smart-0d28ee3b-05de-477f-afb4-1615f62bffb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51142347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.51142347
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2299054222
Short name T323
Test name
Test status
Simulation time 181830061251 ps
CPU time 367.47 seconds
Started Jul 06 05:34:54 PM PDT 24
Finished Jul 06 05:41:02 PM PDT 24
Peak memory 238360 kb
Host smart-97b4df83-62aa-4dbd-bae7-1e0d119e6050
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299054222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2299054222
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3250926087
Short name T7
Test name
Test status
Simulation time 5736082308 ps
CPU time 52.44 seconds
Started Jul 06 05:34:53 PM PDT 24
Finished Jul 06 05:35:46 PM PDT 24
Peak memory 219408 kb
Host smart-586208fb-f098-4548-a5ba-50fa7316cf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250926087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3250926087
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3461152173
Short name T104
Test name
Test status
Simulation time 184884254 ps
CPU time 10.63 seconds
Started Jul 06 05:34:54 PM PDT 24
Finished Jul 06 05:35:05 PM PDT 24
Peak memory 219312 kb
Host smart-b8b5159f-1127-48d7-9c20-470ad1a3f5f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3461152173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3461152173
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.189683500
Short name T310
Test name
Test status
Simulation time 8920251877 ps
CPU time 33.89 seconds
Started Jul 06 05:34:54 PM PDT 24
Finished Jul 06 05:35:28 PM PDT 24
Peak memory 216804 kb
Host smart-cb0cfe68-f4de-489c-8a8b-5f9204e66434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189683500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.189683500
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1441865522
Short name T128
Test name
Test status
Simulation time 15899566619 ps
CPU time 48.84 seconds
Started Jul 06 05:34:52 PM PDT 24
Finished Jul 06 05:35:41 PM PDT 24
Peak memory 217620 kb
Host smart-4c5f6352-5206-42e0-b75d-a6dcd1bc05b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441865522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1441865522
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2581456571
Short name T177
Test name
Test status
Simulation time 15022467344 ps
CPU time 28.59 seconds
Started Jul 06 05:34:55 PM PDT 24
Finished Jul 06 05:35:23 PM PDT 24
Peak memory 217584 kb
Host smart-f02f4d99-9914-414b-9732-f1f2a800f0a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581456571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2581456571
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1994861596
Short name T42
Test name
Test status
Simulation time 1376854902 ps
CPU time 19.39 seconds
Started Jul 06 05:34:53 PM PDT 24
Finished Jul 06 05:35:13 PM PDT 24
Peak memory 219296 kb
Host smart-717a03c5-4657-4088-8634-37d27c5b0277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994861596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1994861596
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.612436143
Short name T154
Test name
Test status
Simulation time 14512400015 ps
CPU time 28.35 seconds
Started Jul 06 05:34:54 PM PDT 24
Finished Jul 06 05:35:23 PM PDT 24
Peak memory 211812 kb
Host smart-803be6d8-ad23-40fc-981a-3172c630990a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=612436143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.612436143
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3298646236
Short name T320
Test name
Test status
Simulation time 8847460640 ps
CPU time 95.7 seconds
Started Jul 06 05:34:54 PM PDT 24
Finished Jul 06 05:36:30 PM PDT 24
Peak memory 216360 kb
Host smart-6b8ea6ea-b3ae-41e7-b843-ee4a8994e1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298646236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3298646236
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2746008656
Short name T127
Test name
Test status
Simulation time 764027385 ps
CPU time 26.06 seconds
Started Jul 06 05:34:55 PM PDT 24
Finished Jul 06 05:35:21 PM PDT 24
Peak memory 219336 kb
Host smart-b9eaabd6-b27f-4082-a79a-0d33f068031f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746008656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2746008656
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2075958561
Short name T152
Test name
Test status
Simulation time 174159918 ps
CPU time 8.45 seconds
Started Jul 06 05:33:22 PM PDT 24
Finished Jul 06 05:33:30 PM PDT 24
Peak memory 217220 kb
Host smart-05f111f4-e446-4565-8374-53c4a7dd778c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075958561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2075958561
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1099016638
Short name T37
Test name
Test status
Simulation time 15147412354 ps
CPU time 282.1 seconds
Started Jul 06 05:33:26 PM PDT 24
Finished Jul 06 05:38:08 PM PDT 24
Peak memory 238752 kb
Host smart-5ce49142-4c13-4585-ba00-3c0b963c7521
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099016638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1099016638
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1492079584
Short name T29
Test name
Test status
Simulation time 53742568703 ps
CPU time 56.83 seconds
Started Jul 06 05:33:26 PM PDT 24
Finished Jul 06 05:34:23 PM PDT 24
Peak memory 219400 kb
Host smart-5ab7bd8a-2bf0-4887-be98-152cce5b01df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492079584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1492079584
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.4073603977
Short name T28
Test name
Test status
Simulation time 1219749236 ps
CPU time 12.34 seconds
Started Jul 06 05:33:21 PM PDT 24
Finished Jul 06 05:33:33 PM PDT 24
Peak memory 219248 kb
Host smart-55a0dda8-8cc5-4c26-9104-f8790326e515
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4073603977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.4073603977
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3236088301
Short name T22
Test name
Test status
Simulation time 1338435524 ps
CPU time 228.77 seconds
Started Jul 06 05:33:21 PM PDT 24
Finished Jul 06 05:37:10 PM PDT 24
Peak memory 238320 kb
Host smart-023e50b7-2289-451a-abac-774456280e0f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236088301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3236088301
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.49125543
Short name T226
Test name
Test status
Simulation time 36969048411 ps
CPU time 77.05 seconds
Started Jul 06 05:33:16 PM PDT 24
Finished Jul 06 05:34:33 PM PDT 24
Peak memory 217364 kb
Host smart-337de3e0-548d-43b4-b7b1-8dcf96860ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49125543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.49125543
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1434929267
Short name T73
Test name
Test status
Simulation time 1417109578 ps
CPU time 43.68 seconds
Started Jul 06 05:33:22 PM PDT 24
Finished Jul 06 05:34:06 PM PDT 24
Peak memory 219344 kb
Host smart-351b5a04-fcdd-4f38-be06-a4bdd6dcee91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434929267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1434929267
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3297966087
Short name T347
Test name
Test status
Simulation time 2131566189 ps
CPU time 20.82 seconds
Started Jul 06 05:35:00 PM PDT 24
Finished Jul 06 05:35:21 PM PDT 24
Peak memory 217152 kb
Host smart-dbb3ad68-21ce-4f9e-9cc8-c02e0d934502
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297966087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3297966087
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2532934690
Short name T295
Test name
Test status
Simulation time 70427364985 ps
CPU time 388.47 seconds
Started Jul 06 05:35:00 PM PDT 24
Finished Jul 06 05:41:29 PM PDT 24
Peak memory 225844 kb
Host smart-634a19c1-f46b-49e9-8fe5-a22f76f30818
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532934690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2532934690
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.685196885
Short name T201
Test name
Test status
Simulation time 13553077478 ps
CPU time 39.16 seconds
Started Jul 06 05:35:02 PM PDT 24
Finished Jul 06 05:35:41 PM PDT 24
Peak memory 219388 kb
Host smart-80c09472-69b5-469c-ab6d-4dac36f53083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685196885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.685196885
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2849742081
Short name T199
Test name
Test status
Simulation time 3628716240 ps
CPU time 30.74 seconds
Started Jul 06 05:35:01 PM PDT 24
Finished Jul 06 05:35:32 PM PDT 24
Peak memory 211432 kb
Host smart-0ac27dbe-62ed-4d65-8e0f-a363093ad716
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2849742081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2849742081
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3324124369
Short name T270
Test name
Test status
Simulation time 2035551420 ps
CPU time 20.44 seconds
Started Jul 06 05:34:59 PM PDT 24
Finished Jul 06 05:35:20 PM PDT 24
Peak memory 216420 kb
Host smart-113c580c-4e78-4170-856d-a5f70b3ac44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324124369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3324124369
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1437788203
Short name T351
Test name
Test status
Simulation time 53598432231 ps
CPU time 77.65 seconds
Started Jul 06 05:34:59 PM PDT 24
Finished Jul 06 05:36:17 PM PDT 24
Peak memory 218052 kb
Host smart-065ae202-3a9e-4361-aca2-df2c8847c63a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437788203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1437788203
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.4127867717
Short name T209
Test name
Test status
Simulation time 4459837578 ps
CPU time 15.47 seconds
Started Jul 06 05:35:06 PM PDT 24
Finished Jul 06 05:35:21 PM PDT 24
Peak memory 217404 kb
Host smart-516e4551-eeac-457a-b229-1cd1b452ca1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127867717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.4127867717
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2515997385
Short name T358
Test name
Test status
Simulation time 29074027309 ps
CPU time 342.14 seconds
Started Jul 06 05:35:10 PM PDT 24
Finished Jul 06 05:40:53 PM PDT 24
Peak memory 238508 kb
Host smart-6efc4919-d667-4dc7-961b-103055699edd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515997385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2515997385
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1888787714
Short name T281
Test name
Test status
Simulation time 4707949689 ps
CPU time 19.55 seconds
Started Jul 06 05:35:06 PM PDT 24
Finished Jul 06 05:35:26 PM PDT 24
Peak memory 219332 kb
Host smart-e74bd27a-443b-4c11-ab1c-a7b0dfd93199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888787714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1888787714
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.4142691018
Short name T136
Test name
Test status
Simulation time 2317725598 ps
CPU time 17.84 seconds
Started Jul 06 05:35:01 PM PDT 24
Finished Jul 06 05:35:19 PM PDT 24
Peak memory 211420 kb
Host smart-d5f4897a-e4b1-4699-bf97-abdedad6504b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4142691018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.4142691018
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2592495820
Short name T217
Test name
Test status
Simulation time 16408645513 ps
CPU time 78.16 seconds
Started Jul 06 05:34:59 PM PDT 24
Finished Jul 06 05:36:17 PM PDT 24
Peak memory 217228 kb
Host smart-84564413-1e39-411a-b9da-bbb8783214fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592495820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2592495820
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1862427831
Short name T249
Test name
Test status
Simulation time 24184684472 ps
CPU time 100.6 seconds
Started Jul 06 05:35:00 PM PDT 24
Finished Jul 06 05:36:41 PM PDT 24
Peak memory 219340 kb
Host smart-c8ee61f5-9306-4a29-8ea9-d532fd371c0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862427831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1862427831
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1887927144
Short name T243
Test name
Test status
Simulation time 177915934 ps
CPU time 8.66 seconds
Started Jul 06 05:35:06 PM PDT 24
Finished Jul 06 05:35:15 PM PDT 24
Peak memory 217188 kb
Host smart-0b0cd97b-461e-48b2-831b-05f847279ca6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887927144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1887927144
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2034827542
Short name T276
Test name
Test status
Simulation time 184444251415 ps
CPU time 568.51 seconds
Started Jul 06 05:35:06 PM PDT 24
Finished Jul 06 05:44:35 PM PDT 24
Peak memory 216816 kb
Host smart-606c1f94-eb08-49d9-b03d-df5904f46e5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034827542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2034827542
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3894523772
Short name T348
Test name
Test status
Simulation time 335794814 ps
CPU time 19.36 seconds
Started Jul 06 05:35:07 PM PDT 24
Finished Jul 06 05:35:27 PM PDT 24
Peak memory 219240 kb
Host smart-a9664ac3-725a-4d8e-b78f-2b9f45b242f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894523772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3894523772
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.806131717
Short name T145
Test name
Test status
Simulation time 688967295 ps
CPU time 10.37 seconds
Started Jul 06 05:35:08 PM PDT 24
Finished Jul 06 05:35:18 PM PDT 24
Peak memory 219324 kb
Host smart-27856d51-be06-4eed-851a-f12e9a785cae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=806131717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.806131717
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.634152838
Short name T344
Test name
Test status
Simulation time 1430535665 ps
CPU time 20.8 seconds
Started Jul 06 05:35:06 PM PDT 24
Finished Jul 06 05:35:27 PM PDT 24
Peak memory 216228 kb
Host smart-0a97485a-bbc4-4973-8e39-fff641ffb890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634152838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.634152838
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1548605826
Short name T214
Test name
Test status
Simulation time 91659498556 ps
CPU time 71.26 seconds
Started Jul 06 05:35:07 PM PDT 24
Finished Jul 06 05:36:19 PM PDT 24
Peak memory 220528 kb
Host smart-461f38dd-c14f-4c6a-9113-aed50960dfcb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548605826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1548605826
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3312537618
Short name T298
Test name
Test status
Simulation time 3783506690 ps
CPU time 31.39 seconds
Started Jul 06 05:35:14 PM PDT 24
Finished Jul 06 05:35:46 PM PDT 24
Peak memory 217308 kb
Host smart-5b154868-2507-4557-8828-f80699cc653e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312537618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3312537618
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2315110965
Short name T245
Test name
Test status
Simulation time 375084112486 ps
CPU time 529.17 seconds
Started Jul 06 05:35:11 PM PDT 24
Finished Jul 06 05:44:01 PM PDT 24
Peak memory 224684 kb
Host smart-0a1121c8-6036-4c2e-b105-ec82e93f11ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315110965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2315110965
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1800452655
Short name T284
Test name
Test status
Simulation time 5047469877 ps
CPU time 32.53 seconds
Started Jul 06 05:35:12 PM PDT 24
Finished Jul 06 05:35:45 PM PDT 24
Peak memory 219384 kb
Host smart-38dfea3a-9de4-4c16-bc40-7206f6797a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800452655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1800452655
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2765126391
Short name T253
Test name
Test status
Simulation time 2383897435 ps
CPU time 19.25 seconds
Started Jul 06 05:35:09 PM PDT 24
Finished Jul 06 05:35:28 PM PDT 24
Peak memory 211544 kb
Host smart-f3b4ee5b-aeae-4cbd-b9a0-0e3de29953e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2765126391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2765126391
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2556427841
Short name T233
Test name
Test status
Simulation time 349437689 ps
CPU time 19.8 seconds
Started Jul 06 05:35:07 PM PDT 24
Finished Jul 06 05:35:27 PM PDT 24
Peak memory 216980 kb
Host smart-cf96c0b2-67b6-4a81-bbe4-897580b29acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556427841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2556427841
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1236520133
Short name T268
Test name
Test status
Simulation time 10546838485 ps
CPU time 117.99 seconds
Started Jul 06 05:35:08 PM PDT 24
Finished Jul 06 05:37:07 PM PDT 24
Peak memory 219348 kb
Host smart-8c425a76-d9dd-498c-9ed1-9b7bd7986b3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236520133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1236520133
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3774889775
Short name T157
Test name
Test status
Simulation time 1215946904 ps
CPU time 16.04 seconds
Started Jul 06 05:35:14 PM PDT 24
Finished Jul 06 05:35:31 PM PDT 24
Peak memory 217216 kb
Host smart-00875607-22c4-41ce-8bc8-63d16150c75e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774889775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3774889775
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2148956039
Short name T296
Test name
Test status
Simulation time 81906359540 ps
CPU time 282.7 seconds
Started Jul 06 05:35:11 PM PDT 24
Finished Jul 06 05:39:54 PM PDT 24
Peak memory 238160 kb
Host smart-42e62fc6-79a1-4e6f-b641-409e095b88f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148956039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2148956039
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.734746868
Short name T190
Test name
Test status
Simulation time 637288616 ps
CPU time 19.6 seconds
Started Jul 06 05:35:13 PM PDT 24
Finished Jul 06 05:35:32 PM PDT 24
Peak memory 219356 kb
Host smart-fa34bfad-ee60-4402-a702-c19d6fa56e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734746868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.734746868
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1761820162
Short name T294
Test name
Test status
Simulation time 3155917707 ps
CPU time 26.54 seconds
Started Jul 06 05:35:11 PM PDT 24
Finished Jul 06 05:35:37 PM PDT 24
Peak memory 219404 kb
Host smart-b95b2ad2-2d3d-4775-ad12-e0d16ec92d77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1761820162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1761820162
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.796075348
Short name T315
Test name
Test status
Simulation time 29578006235 ps
CPU time 67.89 seconds
Started Jul 06 05:35:10 PM PDT 24
Finished Jul 06 05:36:18 PM PDT 24
Peak memory 216924 kb
Host smart-fe9218ea-bced-4715-b9ce-2babb8b50ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796075348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.796075348
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.645669508
Short name T189
Test name
Test status
Simulation time 17117573439 ps
CPU time 140.93 seconds
Started Jul 06 05:35:13 PM PDT 24
Finished Jul 06 05:37:34 PM PDT 24
Peak memory 219244 kb
Host smart-bf530fd0-6173-4f93-93a9-92f857eeac2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645669508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.645669508
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.4087829932
Short name T35
Test name
Test status
Simulation time 1191211259 ps
CPU time 15.66 seconds
Started Jul 06 05:35:22 PM PDT 24
Finished Jul 06 05:35:38 PM PDT 24
Peak memory 217192 kb
Host smart-274c4386-bdc1-43a0-a23c-bcd6830196c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087829932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.4087829932
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3371062507
Short name T286
Test name
Test status
Simulation time 36226287303 ps
CPU time 232.66 seconds
Started Jul 06 05:35:16 PM PDT 24
Finished Jul 06 05:39:08 PM PDT 24
Peak memory 238708 kb
Host smart-a12390ef-329f-4351-af32-47d8d3f52d94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371062507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3371062507
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1197717697
Short name T206
Test name
Test status
Simulation time 15776898171 ps
CPU time 62.82 seconds
Started Jul 06 05:35:16 PM PDT 24
Finished Jul 06 05:36:19 PM PDT 24
Peak memory 219408 kb
Host smart-7f97d3a1-1e88-4e50-8fe5-c11296f2bb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197717697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1197717697
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3603170227
Short name T302
Test name
Test status
Simulation time 1402622366 ps
CPU time 12.67 seconds
Started Jul 06 05:35:17 PM PDT 24
Finished Jul 06 05:35:30 PM PDT 24
Peak memory 218624 kb
Host smart-7d80741d-94eb-4505-903a-7e0cc70ab360
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3603170227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3603170227
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2502248095
Short name T357
Test name
Test status
Simulation time 1436996121 ps
CPU time 21.47 seconds
Started Jul 06 05:35:16 PM PDT 24
Finished Jul 06 05:35:38 PM PDT 24
Peak memory 216920 kb
Host smart-48b8f86b-4897-446d-861d-35374daa8ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502248095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2502248095
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1451808091
Short name T340
Test name
Test status
Simulation time 2884658277 ps
CPU time 45.02 seconds
Started Jul 06 05:35:16 PM PDT 24
Finished Jul 06 05:36:01 PM PDT 24
Peak memory 219444 kb
Host smart-52165d4f-5925-4d4d-909d-4da2daf899c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451808091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1451808091
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2563789284
Short name T324
Test name
Test status
Simulation time 1236861007 ps
CPU time 15.41 seconds
Started Jul 06 05:35:22 PM PDT 24
Finished Jul 06 05:35:38 PM PDT 24
Peak memory 217180 kb
Host smart-fe4a52f9-5729-46ab-a7ca-4690ebad2d76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563789284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2563789284
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.473765733
Short name T262
Test name
Test status
Simulation time 46642486742 ps
CPU time 256.52 seconds
Started Jul 06 05:35:24 PM PDT 24
Finished Jul 06 05:39:41 PM PDT 24
Peak memory 227616 kb
Host smart-2722ec46-bc17-45f6-9099-afb93b384c74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473765733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.473765733
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1090875711
Short name T334
Test name
Test status
Simulation time 5473845940 ps
CPU time 50.28 seconds
Started Jul 06 05:35:25 PM PDT 24
Finished Jul 06 05:36:15 PM PDT 24
Peak memory 219420 kb
Host smart-cf829f15-709d-46f8-82dd-d73b86556ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090875711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1090875711
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.97891085
Short name T259
Test name
Test status
Simulation time 4818032692 ps
CPU time 18.18 seconds
Started Jul 06 05:35:23 PM PDT 24
Finished Jul 06 05:35:42 PM PDT 24
Peak memory 217792 kb
Host smart-549b8480-a1c8-4d5c-91f3-59604d4c7b4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=97891085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.97891085
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1140461131
Short name T125
Test name
Test status
Simulation time 26260568258 ps
CPU time 57.51 seconds
Started Jul 06 05:35:23 PM PDT 24
Finished Jul 06 05:36:21 PM PDT 24
Peak memory 216520 kb
Host smart-02ad1afb-bded-4e16-a945-553521dc9ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140461131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1140461131
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2106139970
Short name T6
Test name
Test status
Simulation time 26952558365 ps
CPU time 61.74 seconds
Started Jul 06 05:35:22 PM PDT 24
Finished Jul 06 05:36:24 PM PDT 24
Peak memory 219356 kb
Host smart-363146c7-3066-4b95-b81b-585a651dde2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106139970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2106139970
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1830647592
Short name T179
Test name
Test status
Simulation time 2359045935 ps
CPU time 20.97 seconds
Started Jul 06 05:35:28 PM PDT 24
Finished Jul 06 05:35:49 PM PDT 24
Peak memory 217212 kb
Host smart-d0411c0c-84f1-4aaf-a9d5-8eea8ba1faac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830647592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1830647592
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1088958146
Short name T290
Test name
Test status
Simulation time 138108653071 ps
CPU time 462.09 seconds
Started Jul 06 05:35:27 PM PDT 24
Finished Jul 06 05:43:10 PM PDT 24
Peak memory 219612 kb
Host smart-4017b5ef-6085-470c-9eeb-951223d58776
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088958146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1088958146
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1343619811
Short name T341
Test name
Test status
Simulation time 21855771568 ps
CPU time 28.22 seconds
Started Jul 06 05:35:29 PM PDT 24
Finished Jul 06 05:35:58 PM PDT 24
Peak memory 219120 kb
Host smart-507f44a3-14c5-49b1-b3a3-7e831419a572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343619811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1343619811
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1572794620
Short name T147
Test name
Test status
Simulation time 20362213814 ps
CPU time 28.02 seconds
Started Jul 06 05:35:28 PM PDT 24
Finished Jul 06 05:35:56 PM PDT 24
Peak memory 212048 kb
Host smart-fb5dbb85-e26c-46e5-8ccc-7242240ee24e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1572794620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1572794620
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2552221965
Short name T165
Test name
Test status
Simulation time 705370305 ps
CPU time 24.29 seconds
Started Jul 06 05:35:25 PM PDT 24
Finished Jul 06 05:35:49 PM PDT 24
Peak memory 216284 kb
Host smart-3ee5ee1c-df46-46f6-bf2a-1ac618555220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552221965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2552221965
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.99484281
Short name T102
Test name
Test status
Simulation time 10585745441 ps
CPU time 72.09 seconds
Started Jul 06 05:35:23 PM PDT 24
Finished Jul 06 05:36:36 PM PDT 24
Peak memory 219400 kb
Host smart-9d75ddc0-4b25-4b80-b42b-62089f436192
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99484281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 37.rom_ctrl_stress_all.99484281
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1875392520
Short name T164
Test name
Test status
Simulation time 15490645679 ps
CPU time 26.93 seconds
Started Jul 06 05:35:29 PM PDT 24
Finished Jul 06 05:35:56 PM PDT 24
Peak memory 213308 kb
Host smart-398ca01a-615d-4720-a3fb-1b9af4b1b59c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875392520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1875392520
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2941903732
Short name T280
Test name
Test status
Simulation time 8039540277 ps
CPU time 285.71 seconds
Started Jul 06 05:35:29 PM PDT 24
Finished Jul 06 05:40:15 PM PDT 24
Peak memory 236240 kb
Host smart-745aca0c-71e5-4101-85af-d9d01954fc34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941903732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2941903732
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.884102018
Short name T32
Test name
Test status
Simulation time 5570393356 ps
CPU time 40.56 seconds
Started Jul 06 05:35:29 PM PDT 24
Finished Jul 06 05:36:10 PM PDT 24
Peak memory 219376 kb
Host smart-8fe64f55-49e5-4dda-a595-ea4d1ea14fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884102018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.884102018
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.831763243
Short name T272
Test name
Test status
Simulation time 16727547537 ps
CPU time 34.33 seconds
Started Jul 06 05:35:29 PM PDT 24
Finished Jul 06 05:36:03 PM PDT 24
Peak memory 217704 kb
Host smart-994332fe-96cd-4a30-957a-38937535276e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=831763243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.831763243
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2368369734
Short name T346
Test name
Test status
Simulation time 21644553961 ps
CPU time 62.41 seconds
Started Jul 06 05:35:27 PM PDT 24
Finished Jul 06 05:36:30 PM PDT 24
Peak memory 217476 kb
Host smart-52afbd1c-6deb-4fd7-85d6-7c901df9c84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368369734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2368369734
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3247484804
Short name T230
Test name
Test status
Simulation time 3187695681 ps
CPU time 43.98 seconds
Started Jul 06 05:35:27 PM PDT 24
Finished Jul 06 05:36:11 PM PDT 24
Peak memory 217712 kb
Host smart-a1c1ba73-25fd-487a-93ab-0172f1408f7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247484804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3247484804
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2362744343
Short name T335
Test name
Test status
Simulation time 6395793816 ps
CPU time 25.74 seconds
Started Jul 06 05:35:31 PM PDT 24
Finished Jul 06 05:35:57 PM PDT 24
Peak memory 213360 kb
Host smart-173eb735-0a08-4081-9c18-591de3249780
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362744343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2362744343
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1398820646
Short name T232
Test name
Test status
Simulation time 30998694114 ps
CPU time 480.66 seconds
Started Jul 06 05:35:29 PM PDT 24
Finished Jul 06 05:43:30 PM PDT 24
Peak memory 234252 kb
Host smart-ff938f75-d041-4d3c-9923-adba8fae981a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398820646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1398820646
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2258393953
Short name T321
Test name
Test status
Simulation time 11415056791 ps
CPU time 52.4 seconds
Started Jul 06 05:35:30 PM PDT 24
Finished Jul 06 05:36:22 PM PDT 24
Peak memory 218908 kb
Host smart-f38d7dfe-ec96-40c2-a60d-47b228bb6331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258393953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2258393953
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.130812744
Short name T300
Test name
Test status
Simulation time 11383459058 ps
CPU time 25.71 seconds
Started Jul 06 05:35:29 PM PDT 24
Finished Jul 06 05:35:55 PM PDT 24
Peak memory 219380 kb
Host smart-9b454965-64c7-4262-8356-8a31854e539b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=130812744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.130812744
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.161391244
Short name T250
Test name
Test status
Simulation time 31309946498 ps
CPU time 67.5 seconds
Started Jul 06 05:35:29 PM PDT 24
Finished Jul 06 05:36:36 PM PDT 24
Peak memory 217300 kb
Host smart-0d1dfa29-e9df-49e7-bc15-2e3fcf896a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161391244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.161391244
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.4185366764
Short name T208
Test name
Test status
Simulation time 14226339228 ps
CPU time 112.23 seconds
Started Jul 06 05:35:27 PM PDT 24
Finished Jul 06 05:37:19 PM PDT 24
Peak memory 221136 kb
Host smart-8cad92c4-d4a3-4043-8a78-30eca2ddc1c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185366764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.4185366764
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1966197935
Short name T242
Test name
Test status
Simulation time 688198632 ps
CPU time 8.54 seconds
Started Jul 06 05:33:27 PM PDT 24
Finished Jul 06 05:33:36 PM PDT 24
Peak memory 217092 kb
Host smart-a80a408b-cbef-45e6-b362-8357431efa01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966197935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1966197935
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3128655505
Short name T303
Test name
Test status
Simulation time 34805206011 ps
CPU time 408.41 seconds
Started Jul 06 05:33:28 PM PDT 24
Finished Jul 06 05:40:17 PM PDT 24
Peak memory 233908 kb
Host smart-d900d0ff-dd86-4577-98c1-a032d66085de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128655505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3128655505
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.473201084
Short name T41
Test name
Test status
Simulation time 30103926313 ps
CPU time 62.65 seconds
Started Jul 06 05:33:28 PM PDT 24
Finished Jul 06 05:34:31 PM PDT 24
Peak memory 218960 kb
Host smart-41d0bfb0-ae60-418f-a66f-9f5282328791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473201084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.473201084
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2511562388
Short name T144
Test name
Test status
Simulation time 182022700 ps
CPU time 10.15 seconds
Started Jul 06 05:33:27 PM PDT 24
Finished Jul 06 05:33:38 PM PDT 24
Peak memory 219388 kb
Host smart-9a02054e-428b-4b74-a267-a1bacf8f5d5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2511562388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2511562388
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2312797575
Short name T263
Test name
Test status
Simulation time 695340958 ps
CPU time 19.41 seconds
Started Jul 06 05:33:25 PM PDT 24
Finished Jul 06 05:33:45 PM PDT 24
Peak memory 216516 kb
Host smart-b70d5a02-429d-4aa4-a3bf-b01e4bb49960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312797575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2312797575
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.4222227696
Short name T74
Test name
Test status
Simulation time 18307963168 ps
CPU time 60.51 seconds
Started Jul 06 05:33:28 PM PDT 24
Finished Jul 06 05:34:29 PM PDT 24
Peak memory 217768 kb
Host smart-ae29b0f4-591f-4387-8455-a4af8a70caad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222227696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.4222227696
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3605125654
Short name T9
Test name
Test status
Simulation time 6893145527 ps
CPU time 30.18 seconds
Started Jul 06 05:35:33 PM PDT 24
Finished Jul 06 05:36:03 PM PDT 24
Peak memory 217548 kb
Host smart-e6728b1d-c502-4ea9-b070-ed0973db94bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605125654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3605125654
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1704141966
Short name T273
Test name
Test status
Simulation time 17341077859 ps
CPU time 367.9 seconds
Started Jul 06 05:35:32 PM PDT 24
Finished Jul 06 05:41:40 PM PDT 24
Peak memory 234676 kb
Host smart-716dfdd5-6bd7-4e56-96bb-76e329eb0911
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704141966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1704141966
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3383174976
Short name T282
Test name
Test status
Simulation time 3684916034 ps
CPU time 30.99 seconds
Started Jul 06 05:35:32 PM PDT 24
Finished Jul 06 05:36:03 PM PDT 24
Peak memory 218908 kb
Host smart-c998e18b-3173-4e7e-b093-7f0be63d3cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383174976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3383174976
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3645112642
Short name T299
Test name
Test status
Simulation time 2332488792 ps
CPU time 23.37 seconds
Started Jul 06 05:35:34 PM PDT 24
Finished Jul 06 05:35:58 PM PDT 24
Peak memory 219416 kb
Host smart-0742e0ac-9fd2-49f1-9354-967e7e6c619d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3645112642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3645112642
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2826097598
Short name T330
Test name
Test status
Simulation time 8621526975 ps
CPU time 96.63 seconds
Started Jul 06 05:35:32 PM PDT 24
Finished Jul 06 05:37:09 PM PDT 24
Peak memory 217236 kb
Host smart-616153c8-b411-4da7-bb94-70dd3ab42d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826097598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2826097598
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3095087724
Short name T121
Test name
Test status
Simulation time 496846793 ps
CPU time 14.4 seconds
Started Jul 06 05:35:35 PM PDT 24
Finished Jul 06 05:35:49 PM PDT 24
Peak memory 214796 kb
Host smart-90b4ce8e-0c0f-4505-ad20-4c1544eacfac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095087724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3095087724
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1883521198
Short name T146
Test name
Test status
Simulation time 169418667 ps
CPU time 8.47 seconds
Started Jul 06 05:35:39 PM PDT 24
Finished Jul 06 05:35:48 PM PDT 24
Peak memory 217184 kb
Host smart-18193a2d-d21a-42ed-857f-78b726fdb01f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883521198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1883521198
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.689626562
Short name T131
Test name
Test status
Simulation time 197336945582 ps
CPU time 630 seconds
Started Jul 06 05:35:42 PM PDT 24
Finished Jul 06 05:46:12 PM PDT 24
Peak memory 216880 kb
Host smart-f238365f-2b62-4e2c-841d-8113058edb29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689626562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.689626562
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.157959655
Short name T170
Test name
Test status
Simulation time 8900201885 ps
CPU time 46.12 seconds
Started Jul 06 05:35:38 PM PDT 24
Finished Jul 06 05:36:24 PM PDT 24
Peak memory 219332 kb
Host smart-de759091-3294-4eb7-b511-f279d3bf9958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157959655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.157959655
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2772584128
Short name T318
Test name
Test status
Simulation time 14494003043 ps
CPU time 32.64 seconds
Started Jul 06 05:35:39 PM PDT 24
Finished Jul 06 05:36:12 PM PDT 24
Peak memory 219380 kb
Host smart-e886e628-689c-485c-b834-098a134cd33b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2772584128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2772584128
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.4056145303
Short name T248
Test name
Test status
Simulation time 2599267499 ps
CPU time 20.52 seconds
Started Jul 06 05:35:38 PM PDT 24
Finished Jul 06 05:35:58 PM PDT 24
Peak memory 217504 kb
Host smart-edd7fb6e-e65f-422d-854c-7b7710888b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056145303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.4056145303
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1201338354
Short name T129
Test name
Test status
Simulation time 14831762531 ps
CPU time 87.34 seconds
Started Jul 06 05:35:39 PM PDT 24
Finished Jul 06 05:37:07 PM PDT 24
Peak memory 219412 kb
Host smart-f2049595-61fb-484f-ae04-e5d7d2c78a16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201338354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1201338354
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.332796366
Short name T239
Test name
Test status
Simulation time 611844697 ps
CPU time 8.19 seconds
Started Jul 06 05:35:44 PM PDT 24
Finished Jul 06 05:35:52 PM PDT 24
Peak memory 217228 kb
Host smart-94a01a2d-c28f-4eee-a255-3132d33e169c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332796366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.332796366
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.231913489
Short name T117
Test name
Test status
Simulation time 78685062062 ps
CPU time 369.51 seconds
Started Jul 06 05:35:43 PM PDT 24
Finished Jul 06 05:41:52 PM PDT 24
Peak memory 247636 kb
Host smart-6be351b6-86d5-436b-a67c-fc0b44e81d3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231913489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.231913489
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3916296366
Short name T141
Test name
Test status
Simulation time 1321210511 ps
CPU time 19.24 seconds
Started Jul 06 05:35:44 PM PDT 24
Finished Jul 06 05:36:03 PM PDT 24
Peak memory 219336 kb
Host smart-d91233aa-1ca8-40fa-92c0-a756860208a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916296366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3916296366
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1979994662
Short name T142
Test name
Test status
Simulation time 2586459196 ps
CPU time 18.62 seconds
Started Jul 06 05:35:40 PM PDT 24
Finished Jul 06 05:35:59 PM PDT 24
Peak memory 219352 kb
Host smart-d41fbaf6-5b77-42b6-9fa1-9b8e59a0f197
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1979994662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1979994662
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1026988100
Short name T1
Test name
Test status
Simulation time 5511163918 ps
CPU time 32.56 seconds
Started Jul 06 05:35:42 PM PDT 24
Finished Jul 06 05:36:14 PM PDT 24
Peak memory 216240 kb
Host smart-20e44515-9a54-4338-a401-167872afc582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026988100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1026988100
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3783011361
Short name T10
Test name
Test status
Simulation time 6656955535 ps
CPU time 65.97 seconds
Started Jul 06 05:35:43 PM PDT 24
Finished Jul 06 05:36:49 PM PDT 24
Peak memory 220764 kb
Host smart-3b54ce9b-b1ea-465e-bed9-c4e1f110264e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783011361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3783011361
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.892406287
Short name T287
Test name
Test status
Simulation time 2230741098 ps
CPU time 20.94 seconds
Started Jul 06 05:35:43 PM PDT 24
Finished Jul 06 05:36:04 PM PDT 24
Peak memory 217224 kb
Host smart-89d95f9b-501c-4971-b4c9-100473ba51d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892406287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.892406287
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3156031845
Short name T103
Test name
Test status
Simulation time 127442761149 ps
CPU time 293.97 seconds
Started Jul 06 05:35:46 PM PDT 24
Finished Jul 06 05:40:40 PM PDT 24
Peak memory 233892 kb
Host smart-cd6043aa-0bb9-40c8-8901-77de5b3e33f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156031845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3156031845
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1973306776
Short name T212
Test name
Test status
Simulation time 3586277487 ps
CPU time 38.8 seconds
Started Jul 06 05:35:44 PM PDT 24
Finished Jul 06 05:36:23 PM PDT 24
Peak memory 219420 kb
Host smart-9e256183-ec9b-426f-ba5a-58fd4693d959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973306776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1973306776
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2566214808
Short name T213
Test name
Test status
Simulation time 5593746858 ps
CPU time 26.84 seconds
Started Jul 06 05:35:43 PM PDT 24
Finished Jul 06 05:36:10 PM PDT 24
Peak memory 217700 kb
Host smart-016ff83a-d10f-4fb8-802d-efde17edab75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2566214808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2566214808
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.1834840065
Short name T148
Test name
Test status
Simulation time 2909914665 ps
CPU time 31.35 seconds
Started Jul 06 05:35:43 PM PDT 24
Finished Jul 06 05:36:15 PM PDT 24
Peak memory 216172 kb
Host smart-8ca770c8-2553-4ccd-8c15-607a4d3a847d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834840065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1834840065
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.111138870
Short name T309
Test name
Test status
Simulation time 32777996839 ps
CPU time 260.6 seconds
Started Jul 06 05:35:42 PM PDT 24
Finished Jul 06 05:40:03 PM PDT 24
Peak memory 222172 kb
Host smart-2f1503b9-1f41-4bbf-b4f0-b389916c537e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111138870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.111138870
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3711356649
Short name T123
Test name
Test status
Simulation time 174603711 ps
CPU time 8.1 seconds
Started Jul 06 05:35:53 PM PDT 24
Finished Jul 06 05:36:01 PM PDT 24
Peak memory 217056 kb
Host smart-b03d25a4-02ef-4d28-ba2b-7ef39deac3fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711356649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3711356649
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1702417377
Short name T38
Test name
Test status
Simulation time 163468686842 ps
CPU time 475.48 seconds
Started Jul 06 05:35:55 PM PDT 24
Finished Jul 06 05:43:51 PM PDT 24
Peak memory 234256 kb
Host smart-08111dc4-195a-4d3e-b235-1353703e9f29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702417377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1702417377
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.4068797013
Short name T181
Test name
Test status
Simulation time 1318749663 ps
CPU time 19.29 seconds
Started Jul 06 05:35:53 PM PDT 24
Finished Jul 06 05:36:13 PM PDT 24
Peak memory 219368 kb
Host smart-26884632-569e-4504-9d72-10dbf000acfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068797013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.4068797013
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2461745309
Short name T343
Test name
Test status
Simulation time 14803445590 ps
CPU time 23.82 seconds
Started Jul 06 05:35:49 PM PDT 24
Finished Jul 06 05:36:13 PM PDT 24
Peak memory 211908 kb
Host smart-3bbebec1-d040-48b1-9735-60cc70595768
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2461745309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2461745309
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1787424555
Short name T137
Test name
Test status
Simulation time 5311355005 ps
CPU time 52.82 seconds
Started Jul 06 05:35:49 PM PDT 24
Finished Jul 06 05:36:42 PM PDT 24
Peak memory 216424 kb
Host smart-692f3ef6-5fb1-441d-81fe-29d3b7d12e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787424555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1787424555
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3060648262
Short name T238
Test name
Test status
Simulation time 1170566003 ps
CPU time 33.12 seconds
Started Jul 06 05:35:48 PM PDT 24
Finished Jul 06 05:36:21 PM PDT 24
Peak memory 219148 kb
Host smart-4beb1428-42fa-40d4-b403-694703bd2b99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060648262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3060648262
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.357419697
Short name T196
Test name
Test status
Simulation time 2575286241 ps
CPU time 22.86 seconds
Started Jul 06 05:36:00 PM PDT 24
Finished Jul 06 05:36:24 PM PDT 24
Peak memory 217328 kb
Host smart-40ddd366-8556-4f4f-ac33-8f06880c568b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357419697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.357419697
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.419163151
Short name T205
Test name
Test status
Simulation time 118061530296 ps
CPU time 313.01 seconds
Started Jul 06 05:36:00 PM PDT 24
Finished Jul 06 05:41:13 PM PDT 24
Peak memory 232716 kb
Host smart-8ba2081d-8638-447a-99e2-5ae5ba819f0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419163151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.419163151
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.929619453
Short name T328
Test name
Test status
Simulation time 3038891240 ps
CPU time 37.4 seconds
Started Jul 06 05:36:01 PM PDT 24
Finished Jul 06 05:36:39 PM PDT 24
Peak memory 219376 kb
Host smart-6dafaecf-4555-493d-988a-d836cfc1da80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929619453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.929619453
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1782780863
Short name T180
Test name
Test status
Simulation time 7983675601 ps
CPU time 26.37 seconds
Started Jul 06 05:35:54 PM PDT 24
Finished Jul 06 05:36:21 PM PDT 24
Peak memory 211592 kb
Host smart-f68cc4cc-223d-4ce6-acc3-baae31e24bf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1782780863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1782780863
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.4153495277
Short name T171
Test name
Test status
Simulation time 3099050428 ps
CPU time 20.46 seconds
Started Jul 06 05:35:55 PM PDT 24
Finished Jul 06 05:36:15 PM PDT 24
Peak memory 216416 kb
Host smart-04fa8a96-5869-4717-8bab-6bdacab59a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153495277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.4153495277
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.4239535837
Short name T60
Test name
Test status
Simulation time 20123328418 ps
CPU time 134.66 seconds
Started Jul 06 05:35:53 PM PDT 24
Finished Jul 06 05:38:08 PM PDT 24
Peak memory 220700 kb
Host smart-1a4d8dc1-9ceb-485c-b8af-ec9d5b40ea50
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239535837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.4239535837
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.4090627484
Short name T241
Test name
Test status
Simulation time 3787712845 ps
CPU time 32.14 seconds
Started Jul 06 05:36:02 PM PDT 24
Finished Jul 06 05:36:35 PM PDT 24
Peak memory 217176 kb
Host smart-4a0e956c-1158-45e4-b1c9-2e05d479dfa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090627484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.4090627484
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1164988100
Short name T204
Test name
Test status
Simulation time 11027081157 ps
CPU time 383.27 seconds
Started Jul 06 05:35:57 PM PDT 24
Finished Jul 06 05:42:21 PM PDT 24
Peak memory 240288 kb
Host smart-ea11f954-dd5d-4ddb-8b11-bb29c1aa0d01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164988100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1164988100
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1540679361
Short name T159
Test name
Test status
Simulation time 3465173337 ps
CPU time 27.23 seconds
Started Jul 06 05:36:00 PM PDT 24
Finished Jul 06 05:36:27 PM PDT 24
Peak memory 219344 kb
Host smart-06d36364-08d5-43f5-933a-538bd04da36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540679361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1540679361
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2821713806
Short name T143
Test name
Test status
Simulation time 3960059514 ps
CPU time 34.79 seconds
Started Jul 06 05:35:58 PM PDT 24
Finished Jul 06 05:36:33 PM PDT 24
Peak memory 219380 kb
Host smart-49135a51-f3ce-4bfe-96a8-5f848f601c2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2821713806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2821713806
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.4093319341
Short name T166
Test name
Test status
Simulation time 7552982758 ps
CPU time 30.44 seconds
Started Jul 06 05:35:58 PM PDT 24
Finished Jul 06 05:36:28 PM PDT 24
Peak memory 217216 kb
Host smart-a4a20ff1-4b35-4d08-abaa-949ccc35b88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093319341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.4093319341
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.4116360758
Short name T329
Test name
Test status
Simulation time 4613446512 ps
CPU time 56.44 seconds
Started Jul 06 05:36:00 PM PDT 24
Finished Jul 06 05:36:57 PM PDT 24
Peak memory 217844 kb
Host smart-9f1cac50-f5ce-44c7-aac6-9b4b41353684
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116360758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.4116360758
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.341506719
Short name T215
Test name
Test status
Simulation time 167465937 ps
CPU time 8.36 seconds
Started Jul 06 05:36:07 PM PDT 24
Finished Jul 06 05:36:15 PM PDT 24
Peak memory 217068 kb
Host smart-f4865c9a-3a19-427b-97f4-f1b28c06895d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341506719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.341506719
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2869054397
Short name T306
Test name
Test status
Simulation time 11124018988 ps
CPU time 186.59 seconds
Started Jul 06 05:35:59 PM PDT 24
Finished Jul 06 05:39:05 PM PDT 24
Peak memory 240328 kb
Host smart-922f0cd4-0684-4c7c-998c-c1ed0540bdc9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869054397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2869054397
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2799824367
Short name T293
Test name
Test status
Simulation time 14459446581 ps
CPU time 53.29 seconds
Started Jul 06 05:36:05 PM PDT 24
Finished Jul 06 05:36:59 PM PDT 24
Peak memory 219328 kb
Host smart-27414ba1-79b9-4f0b-ac69-93ba0362e726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799824367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2799824367
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1341588919
Short name T266
Test name
Test status
Simulation time 717745919 ps
CPU time 10.29 seconds
Started Jul 06 05:35:58 PM PDT 24
Finished Jul 06 05:36:08 PM PDT 24
Peak memory 219272 kb
Host smart-de6ac642-3835-4e0f-bcd7-6b182b01c04d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1341588919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1341588919
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2292368881
Short name T349
Test name
Test status
Simulation time 2840953766 ps
CPU time 38.73 seconds
Started Jul 06 05:35:58 PM PDT 24
Finished Jul 06 05:36:37 PM PDT 24
Peak memory 216328 kb
Host smart-3b3794bd-d1ac-422d-819f-10ca875c8a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292368881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2292368881
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1796023156
Short name T72
Test name
Test status
Simulation time 17384845023 ps
CPU time 71.78 seconds
Started Jul 06 05:35:58 PM PDT 24
Finished Jul 06 05:37:10 PM PDT 24
Peak memory 216332 kb
Host smart-bce6aca1-73fc-4f48-ac13-5cfdfcaef2c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796023156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1796023156
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.455833362
Short name T313
Test name
Test status
Simulation time 2374371159 ps
CPU time 15.69 seconds
Started Jul 06 05:36:05 PM PDT 24
Finished Jul 06 05:36:21 PM PDT 24
Peak memory 217048 kb
Host smart-98368ef5-5053-4a52-a7fe-198bc9972479
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455833362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.455833362
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2966788064
Short name T130
Test name
Test status
Simulation time 259497849605 ps
CPU time 678.32 seconds
Started Jul 06 05:36:06 PM PDT 24
Finished Jul 06 05:47:25 PM PDT 24
Peak memory 239764 kb
Host smart-1b59de14-6dc3-466c-b913-aee8ef37bf2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966788064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2966788064
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.4040245097
Short name T155
Test name
Test status
Simulation time 7695175778 ps
CPU time 61.8 seconds
Started Jul 06 05:36:06 PM PDT 24
Finished Jul 06 05:37:08 PM PDT 24
Peak memory 219400 kb
Host smart-b663e9fb-78c5-41a2-a1c6-c83ad5cfb56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040245097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.4040245097
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3032856969
Short name T221
Test name
Test status
Simulation time 2561796907 ps
CPU time 25.78 seconds
Started Jul 06 05:36:05 PM PDT 24
Finished Jul 06 05:36:31 PM PDT 24
Peak memory 211756 kb
Host smart-336b9b1c-8ae2-4547-9435-1ca02cb9b6b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3032856969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3032856969
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.4251429845
Short name T122
Test name
Test status
Simulation time 10605371127 ps
CPU time 50.84 seconds
Started Jul 06 05:36:04 PM PDT 24
Finished Jul 06 05:36:55 PM PDT 24
Peak memory 219072 kb
Host smart-b18bbcc2-e19a-4918-8b34-3ff2101e5789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251429845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.4251429845
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.423669428
Short name T277
Test name
Test status
Simulation time 2538840650 ps
CPU time 31.89 seconds
Started Jul 06 05:36:03 PM PDT 24
Finished Jul 06 05:36:35 PM PDT 24
Peak memory 217348 kb
Host smart-62936e7a-bd8b-43ed-8d4f-2ae9ccd3568a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423669428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.423669428
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3994668983
Short name T312
Test name
Test status
Simulation time 661454392 ps
CPU time 8.1 seconds
Started Jul 06 05:36:11 PM PDT 24
Finished Jul 06 05:36:19 PM PDT 24
Peak memory 217240 kb
Host smart-a8653ec7-57d5-4c76-b492-22fbf22c62df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994668983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3994668983
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2065577105
Short name T39
Test name
Test status
Simulation time 2995183317 ps
CPU time 244.66 seconds
Started Jul 06 05:36:08 PM PDT 24
Finished Jul 06 05:40:13 PM PDT 24
Peak memory 233912 kb
Host smart-4f8f7903-3eac-4378-9b5f-4c2c661ca24d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065577105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2065577105
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2188474222
Short name T30
Test name
Test status
Simulation time 7228208584 ps
CPU time 60.23 seconds
Started Jul 06 05:36:09 PM PDT 24
Finished Jul 06 05:37:09 PM PDT 24
Peak memory 219304 kb
Host smart-654e95c7-f4cb-4205-b748-6fd9752f5df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188474222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2188474222
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3907198769
Short name T188
Test name
Test status
Simulation time 1606024501 ps
CPU time 19.99 seconds
Started Jul 06 05:36:12 PM PDT 24
Finished Jul 06 05:36:32 PM PDT 24
Peak memory 219360 kb
Host smart-ff72e370-9422-4fb0-8d7c-8363f1e8251f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3907198769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3907198769
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2548912301
Short name T75
Test name
Test status
Simulation time 1693832597 ps
CPU time 20.59 seconds
Started Jul 06 05:36:04 PM PDT 24
Finished Jul 06 05:36:25 PM PDT 24
Peak memory 215568 kb
Host smart-d2792554-0568-413e-bb0f-86d45c44b100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548912301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2548912301
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.153017500
Short name T289
Test name
Test status
Simulation time 10913554204 ps
CPU time 35.33 seconds
Started Jul 06 05:36:08 PM PDT 24
Finished Jul 06 05:36:44 PM PDT 24
Peak memory 214552 kb
Host smart-688e47c0-fd70-4415-938d-044f5878e34f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153017500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.153017500
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2343438690
Short name T176
Test name
Test status
Simulation time 7453331179 ps
CPU time 20.08 seconds
Started Jul 06 05:33:27 PM PDT 24
Finished Jul 06 05:33:48 PM PDT 24
Peak memory 213352 kb
Host smart-fe34dead-724c-49ec-8c25-e77d91062a26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343438690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2343438690
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1925239361
Short name T325
Test name
Test status
Simulation time 69639353893 ps
CPU time 650.86 seconds
Started Jul 06 05:33:25 PM PDT 24
Finished Jul 06 05:44:16 PM PDT 24
Peak memory 226328 kb
Host smart-b892eba6-cd65-4b19-92e5-8a28c5ad1a8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925239361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1925239361
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2606422735
Short name T264
Test name
Test status
Simulation time 5158369510 ps
CPU time 47.22 seconds
Started Jul 06 05:33:26 PM PDT 24
Finished Jul 06 05:34:14 PM PDT 24
Peak memory 219372 kb
Host smart-14e08572-8500-4411-a399-61b6794b46f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606422735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2606422735
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3231503798
Short name T316
Test name
Test status
Simulation time 1100744964 ps
CPU time 10.74 seconds
Started Jul 06 05:33:27 PM PDT 24
Finished Jul 06 05:33:38 PM PDT 24
Peak memory 219292 kb
Host smart-2f131d91-a028-468c-9bc0-9ad5569962b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3231503798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3231503798
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1245547636
Short name T227
Test name
Test status
Simulation time 4316159677 ps
CPU time 46.53 seconds
Started Jul 06 05:33:29 PM PDT 24
Finished Jul 06 05:34:16 PM PDT 24
Peak memory 216592 kb
Host smart-31bee9a4-1f09-447b-885a-9f3110ea3095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245547636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1245547636
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.808368133
Short name T237
Test name
Test status
Simulation time 16080763012 ps
CPU time 152.92 seconds
Started Jul 06 05:33:27 PM PDT 24
Finished Jul 06 05:36:01 PM PDT 24
Peak memory 219556 kb
Host smart-bd7d5e57-8979-4141-a8c6-216fb62e48a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808368133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.808368133
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2046448187
Short name T297
Test name
Test status
Simulation time 2376112639 ps
CPU time 22.01 seconds
Started Jul 06 05:33:32 PM PDT 24
Finished Jul 06 05:33:54 PM PDT 24
Peak memory 217176 kb
Host smart-f48ced8c-8319-42b0-b55a-d34142fb128a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046448187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2046448187
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3184898837
Short name T265
Test name
Test status
Simulation time 107108793529 ps
CPU time 469.07 seconds
Started Jul 06 05:33:36 PM PDT 24
Finished Jul 06 05:41:25 PM PDT 24
Peak memory 228064 kb
Host smart-1d829609-72bf-4502-82ce-c772a6967685
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184898837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3184898837
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2836432711
Short name T139
Test name
Test status
Simulation time 349938408 ps
CPU time 19.83 seconds
Started Jul 06 05:33:35 PM PDT 24
Finished Jul 06 05:33:55 PM PDT 24
Peak memory 219296 kb
Host smart-59dc3a99-c7f7-48b4-a758-035e2601f4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836432711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2836432711
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3627390119
Short name T225
Test name
Test status
Simulation time 3857947686 ps
CPU time 22.18 seconds
Started Jul 06 05:33:34 PM PDT 24
Finished Jul 06 05:33:56 PM PDT 24
Peak memory 219388 kb
Host smart-d6ad063f-0dfd-4cc7-ba5e-e7e25bbd654a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3627390119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3627390119
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.889998034
Short name T178
Test name
Test status
Simulation time 1491908860 ps
CPU time 30.53 seconds
Started Jul 06 05:33:33 PM PDT 24
Finished Jul 06 05:34:03 PM PDT 24
Peak memory 216072 kb
Host smart-51c63df5-46ed-4374-abb6-f6093d296c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889998034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.889998034
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.857849942
Short name T186
Test name
Test status
Simulation time 14344556945 ps
CPU time 92.2 seconds
Started Jul 06 05:33:33 PM PDT 24
Finished Jul 06 05:35:05 PM PDT 24
Peak memory 219392 kb
Host smart-9db8e739-7e17-4abe-8141-e37f93237f79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857849942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.857849942
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1320121212
Short name T200
Test name
Test status
Simulation time 338010679 ps
CPU time 10.73 seconds
Started Jul 06 05:33:40 PM PDT 24
Finished Jul 06 05:33:51 PM PDT 24
Peak memory 216964 kb
Host smart-e3d92b46-2754-49e4-ac3d-61a616829352
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320121212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1320121212
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3331448131
Short name T308
Test name
Test status
Simulation time 29413692465 ps
CPU time 146.82 seconds
Started Jul 06 05:33:41 PM PDT 24
Finished Jul 06 05:36:09 PM PDT 24
Peak memory 225720 kb
Host smart-86be2773-0c25-4630-a202-80d741720b33
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331448131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3331448131
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2217348924
Short name T25
Test name
Test status
Simulation time 12565368796 ps
CPU time 57.58 seconds
Started Jul 06 05:33:39 PM PDT 24
Finished Jul 06 05:34:37 PM PDT 24
Peak memory 219296 kb
Host smart-187f657b-0057-4d15-912b-ad9c0c402a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217348924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2217348924
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2785990768
Short name T151
Test name
Test status
Simulation time 8613160126 ps
CPU time 29.99 seconds
Started Jul 06 05:33:40 PM PDT 24
Finished Jul 06 05:34:10 PM PDT 24
Peak memory 211684 kb
Host smart-a3819d20-fd96-4531-8493-374754f21612
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2785990768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2785990768
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.22005891
Short name T278
Test name
Test status
Simulation time 6335601706 ps
CPU time 69.21 seconds
Started Jul 06 05:33:35 PM PDT 24
Finished Jul 06 05:34:45 PM PDT 24
Peak memory 217392 kb
Host smart-d757a072-b44f-4017-bcc7-a504243541f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22005891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.22005891
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3288630193
Short name T345
Test name
Test status
Simulation time 2381279195 ps
CPU time 49.7 seconds
Started Jul 06 05:33:39 PM PDT 24
Finished Jul 06 05:34:29 PM PDT 24
Peak memory 219356 kb
Host smart-5373b435-a1b9-47e0-b981-b59ab3434524
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288630193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3288630193
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.138720475
Short name T24
Test name
Test status
Simulation time 4425696513 ps
CPU time 33.1 seconds
Started Jul 06 05:33:41 PM PDT 24
Finished Jul 06 05:34:14 PM PDT 24
Peak memory 217312 kb
Host smart-a51c95d7-2037-4232-af1c-4b0860875c02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138720475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.138720475
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.382339017
Short name T20
Test name
Test status
Simulation time 14184978818 ps
CPU time 218.58 seconds
Started Jul 06 05:33:41 PM PDT 24
Finished Jul 06 05:37:20 PM PDT 24
Peak memory 225684 kb
Host smart-ef4968f2-34f8-4d6c-b983-8b1e686c7df6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382339017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.382339017
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.4218526443
Short name T244
Test name
Test status
Simulation time 5949109589 ps
CPU time 54.03 seconds
Started Jul 06 05:33:42 PM PDT 24
Finished Jul 06 05:34:36 PM PDT 24
Peak memory 219384 kb
Host smart-bc39cebb-218e-4fda-995d-45a160ad0e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218526443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.4218526443
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3757763395
Short name T261
Test name
Test status
Simulation time 11880155303 ps
CPU time 25.18 seconds
Started Jul 06 05:33:41 PM PDT 24
Finished Jul 06 05:34:07 PM PDT 24
Peak memory 219328 kb
Host smart-0d906d01-add6-4f28-ae58-24dd5d68e832
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3757763395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3757763395
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.4095087711
Short name T132
Test name
Test status
Simulation time 1041196683 ps
CPU time 28.29 seconds
Started Jul 06 05:33:41 PM PDT 24
Finished Jul 06 05:34:10 PM PDT 24
Peak memory 217296 kb
Host smart-fd19f81e-5b71-4ce4-af58-a039f789b40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095087711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.4095087711
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2746589216
Short name T163
Test name
Test status
Simulation time 14581231546 ps
CPU time 32.1 seconds
Started Jul 06 05:33:41 PM PDT 24
Finished Jul 06 05:34:14 PM PDT 24
Peak memory 214868 kb
Host smart-9014cbed-abb5-494e-b7a6-8997588364be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746589216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2746589216
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3552758945
Short name T246
Test name
Test status
Simulation time 1118536220 ps
CPU time 16.26 seconds
Started Jul 06 05:33:46 PM PDT 24
Finished Jul 06 05:34:02 PM PDT 24
Peak memory 217004 kb
Host smart-a468b838-3909-4003-9b1c-33561abff70e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552758945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3552758945
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2374035972
Short name T116
Test name
Test status
Simulation time 50324015535 ps
CPU time 381.95 seconds
Started Jul 06 05:33:45 PM PDT 24
Finished Jul 06 05:40:07 PM PDT 24
Peak memory 217084 kb
Host smart-3497b65d-aa27-42f5-9f1e-f1f12b74b0d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374035972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2374035972
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.697007820
Short name T356
Test name
Test status
Simulation time 24438986538 ps
CPU time 55.05 seconds
Started Jul 06 05:33:47 PM PDT 24
Finished Jul 06 05:34:42 PM PDT 24
Peak memory 219412 kb
Host smart-08bc11e3-7533-424a-b09c-6e7a59e9e95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697007820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.697007820
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.755564501
Short name T355
Test name
Test status
Simulation time 3650869994 ps
CPU time 21.22 seconds
Started Jul 06 05:33:46 PM PDT 24
Finished Jul 06 05:34:08 PM PDT 24
Peak memory 217784 kb
Host smart-221832cc-5c0f-4e9a-9558-43015ecaa9f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=755564501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.755564501
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.368052400
Short name T235
Test name
Test status
Simulation time 15792723356 ps
CPU time 76.25 seconds
Started Jul 06 05:33:48 PM PDT 24
Finished Jul 06 05:35:05 PM PDT 24
Peak memory 219356 kb
Host smart-9abaeec1-a047-4e26-b7b5-5591eee240e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368052400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.368052400
Directory /workspace/9.rom_ctrl_stress_all/latest
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