Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.21 96.89 91.99 97.68 100.00 98.28 97.30 98.37


Total test records in report: 456
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T304 /workspace/coverage/default/14.rom_ctrl_stress_all.380052062 Jul 09 05:05:51 PM PDT 24 Jul 09 05:06:42 PM PDT 24 15767111178 ps
T305 /workspace/coverage/default/5.rom_ctrl_smoke.512454908 Jul 09 05:05:49 PM PDT 24 Jul 09 05:06:40 PM PDT 24 8569407817 ps
T306 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1492763473 Jul 09 05:06:38 PM PDT 24 Jul 09 05:12:34 PM PDT 24 24089925265 ps
T307 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1445095955 Jul 09 05:05:55 PM PDT 24 Jul 09 05:06:21 PM PDT 24 339044650 ps
T308 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.232046692 Jul 09 05:06:12 PM PDT 24 Jul 09 05:09:04 PM PDT 24 11963370192 ps
T309 /workspace/coverage/default/35.rom_ctrl_smoke.116927094 Jul 09 05:06:36 PM PDT 24 Jul 09 05:07:00 PM PDT 24 1040057360 ps
T310 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1508991354 Jul 09 05:06:51 PM PDT 24 Jul 09 05:14:25 PM PDT 24 77369298084 ps
T311 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2289639683 Jul 09 05:06:10 PM PDT 24 Jul 09 05:09:43 PM PDT 24 8972669245 ps
T29 /workspace/coverage/default/4.rom_ctrl_sec_cm.270539354 Jul 09 05:05:44 PM PDT 24 Jul 09 05:07:45 PM PDT 24 253612522 ps
T312 /workspace/coverage/default/45.rom_ctrl_smoke.1190366418 Jul 09 05:06:55 PM PDT 24 Jul 09 05:07:52 PM PDT 24 26772777226 ps
T313 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2787974244 Jul 09 05:06:54 PM PDT 24 Jul 09 05:08:02 PM PDT 24 12817830896 ps
T314 /workspace/coverage/default/15.rom_ctrl_smoke.3788944918 Jul 09 05:05:50 PM PDT 24 Jul 09 05:06:44 PM PDT 24 4669327527 ps
T315 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2585953347 Jul 09 05:06:55 PM PDT 24 Jul 09 05:07:26 PM PDT 24 7728464227 ps
T316 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2065313300 Jul 09 05:05:55 PM PDT 24 Jul 09 05:06:29 PM PDT 24 12330046970 ps
T317 /workspace/coverage/default/49.rom_ctrl_stress_all.3765411618 Jul 09 05:07:05 PM PDT 24 Jul 09 05:07:59 PM PDT 24 3687119644 ps
T318 /workspace/coverage/default/26.rom_ctrl_alert_test.1608891987 Jul 09 05:06:21 PM PDT 24 Jul 09 05:06:48 PM PDT 24 3234224830 ps
T319 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2632522771 Jul 09 05:06:42 PM PDT 24 Jul 09 05:07:42 PM PDT 24 6747002900 ps
T320 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2078966115 Jul 09 05:06:30 PM PDT 24 Jul 09 05:07:22 PM PDT 24 10698830645 ps
T321 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2758332465 Jul 09 05:05:42 PM PDT 24 Jul 09 05:06:19 PM PDT 24 4105255577 ps
T322 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1835367591 Jul 09 05:05:40 PM PDT 24 Jul 09 05:06:15 PM PDT 24 27997628208 ps
T323 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.473432666 Jul 09 05:06:04 PM PDT 24 Jul 09 05:14:16 PM PDT 24 248920302432 ps
T324 /workspace/coverage/default/25.rom_ctrl_alert_test.2160546107 Jul 09 05:06:22 PM PDT 24 Jul 09 05:06:35 PM PDT 24 1650883153 ps
T325 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.508038602 Jul 09 05:05:50 PM PDT 24 Jul 09 05:06:16 PM PDT 24 1375063628 ps
T326 /workspace/coverage/default/37.rom_ctrl_stress_all.2207759526 Jul 09 05:06:43 PM PDT 24 Jul 09 05:08:28 PM PDT 24 35612240111 ps
T327 /workspace/coverage/default/41.rom_ctrl_stress_all.840258703 Jul 09 05:06:49 PM PDT 24 Jul 09 05:08:08 PM PDT 24 11719981876 ps
T328 /workspace/coverage/default/27.rom_ctrl_stress_all.703933718 Jul 09 05:06:21 PM PDT 24 Jul 09 05:07:03 PM PDT 24 2473354919 ps
T329 /workspace/coverage/default/32.rom_ctrl_stress_all.2457165159 Jul 09 05:06:35 PM PDT 24 Jul 09 05:09:12 PM PDT 24 16756028116 ps
T330 /workspace/coverage/default/19.rom_ctrl_alert_test.3709885955 Jul 09 05:05:56 PM PDT 24 Jul 09 05:06:37 PM PDT 24 11898476710 ps
T331 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.99719078 Jul 09 05:05:56 PM PDT 24 Jul 09 05:07:06 PM PDT 24 7385662229 ps
T332 /workspace/coverage/default/5.rom_ctrl_alert_test.2523717740 Jul 09 05:05:44 PM PDT 24 Jul 09 05:06:05 PM PDT 24 5354654781 ps
T333 /workspace/coverage/default/6.rom_ctrl_stress_all.3030762027 Jul 09 05:05:44 PM PDT 24 Jul 09 05:07:39 PM PDT 24 19452423859 ps
T30 /workspace/coverage/default/0.rom_ctrl_sec_cm.2962587967 Jul 09 05:05:42 PM PDT 24 Jul 09 05:09:38 PM PDT 24 3780115027 ps
T334 /workspace/coverage/default/41.rom_ctrl_smoke.559676332 Jul 09 05:06:47 PM PDT 24 Jul 09 05:07:33 PM PDT 24 17098805098 ps
T335 /workspace/coverage/default/34.rom_ctrl_smoke.1002038946 Jul 09 05:06:37 PM PDT 24 Jul 09 05:07:04 PM PDT 24 4546468512 ps
T336 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3597864809 Jul 09 05:06:26 PM PDT 24 Jul 09 05:07:40 PM PDT 24 93037222998 ps
T337 /workspace/coverage/default/11.rom_ctrl_alert_test.1375727278 Jul 09 05:05:50 PM PDT 24 Jul 09 05:06:29 PM PDT 24 16467562560 ps
T338 /workspace/coverage/default/12.rom_ctrl_smoke.2094342222 Jul 09 05:05:51 PM PDT 24 Jul 09 05:06:17 PM PDT 24 354094638 ps
T339 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2618467155 Jul 09 05:05:47 PM PDT 24 Jul 09 05:06:12 PM PDT 24 1375281915 ps
T340 /workspace/coverage/default/21.rom_ctrl_stress_all.3786759042 Jul 09 05:06:00 PM PDT 24 Jul 09 05:06:43 PM PDT 24 2351773179 ps
T341 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2174043 Jul 09 05:05:41 PM PDT 24 Jul 09 05:06:46 PM PDT 24 7017936459 ps
T342 /workspace/coverage/default/23.rom_ctrl_smoke.2723777436 Jul 09 05:06:13 PM PDT 24 Jul 09 05:06:34 PM PDT 24 1382645161 ps
T343 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2852155283 Jul 09 05:05:44 PM PDT 24 Jul 09 05:26:12 PM PDT 24 527114944560 ps
T344 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1978682964 Jul 09 05:06:17 PM PDT 24 Jul 09 05:17:48 PM PDT 24 78942251552 ps
T345 /workspace/coverage/default/19.rom_ctrl_stress_all.2142067302 Jul 09 05:05:56 PM PDT 24 Jul 09 05:06:28 PM PDT 24 3719566508 ps
T346 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3715105725 Jul 09 05:06:57 PM PDT 24 Jul 09 05:14:12 PM PDT 24 159500862701 ps
T347 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2425422401 Jul 09 05:06:22 PM PDT 24 Jul 09 05:06:55 PM PDT 24 1963916164 ps
T348 /workspace/coverage/default/20.rom_ctrl_smoke.1288644016 Jul 09 05:05:54 PM PDT 24 Jul 09 05:07:03 PM PDT 24 6322603971 ps
T349 /workspace/coverage/default/12.rom_ctrl_stress_all.4053706395 Jul 09 05:05:49 PM PDT 24 Jul 09 05:06:19 PM PDT 24 2039904459 ps
T350 /workspace/coverage/default/10.rom_ctrl_alert_test.3119654853 Jul 09 05:05:49 PM PDT 24 Jul 09 05:06:18 PM PDT 24 2397484648 ps
T351 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.821143354 Jul 09 05:06:22 PM PDT 24 Jul 09 05:06:46 PM PDT 24 2494960558 ps
T352 /workspace/coverage/default/44.rom_ctrl_smoke.1077097538 Jul 09 05:06:53 PM PDT 24 Jul 09 05:07:36 PM PDT 24 3549177433 ps
T353 /workspace/coverage/default/4.rom_ctrl_smoke.4147630703 Jul 09 05:05:44 PM PDT 24 Jul 09 05:06:48 PM PDT 24 22693158898 ps
T354 /workspace/coverage/default/36.rom_ctrl_alert_test.2239304505 Jul 09 05:06:39 PM PDT 24 Jul 09 05:07:11 PM PDT 24 4034966798 ps
T355 /workspace/coverage/default/31.rom_ctrl_smoke.474775592 Jul 09 05:06:30 PM PDT 24 Jul 09 05:07:42 PM PDT 24 7526842352 ps
T356 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.4026484947 Jul 09 05:05:39 PM PDT 24 Jul 09 05:06:12 PM PDT 24 1364914116 ps
T357 /workspace/coverage/default/18.rom_ctrl_smoke.1680265976 Jul 09 05:05:54 PM PDT 24 Jul 09 05:06:23 PM PDT 24 343335235 ps
T358 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1046144531 Jul 09 05:06:43 PM PDT 24 Jul 09 05:06:58 PM PDT 24 617291318 ps
T359 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2259870855 Jul 09 05:06:24 PM PDT 24 Jul 09 05:16:20 PM PDT 24 234738460376 ps
T360 /workspace/coverage/default/47.rom_ctrl_alert_test.1814580561 Jul 09 05:07:06 PM PDT 24 Jul 09 05:07:21 PM PDT 24 1685595188 ps
T361 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3882321027 Jul 09 05:06:39 PM PDT 24 Jul 09 05:07:08 PM PDT 24 11837716336 ps
T362 /workspace/coverage/default/31.rom_ctrl_stress_all.2385276191 Jul 09 05:06:30 PM PDT 24 Jul 09 05:08:12 PM PDT 24 27018453404 ps
T58 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.393907791 Jul 09 05:05:25 PM PDT 24 Jul 09 05:05:43 PM PDT 24 1266768522 ps
T59 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2437323505 Jul 09 05:05:33 PM PDT 24 Jul 09 05:06:01 PM PDT 24 11702413794 ps
T52 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1347518718 Jul 09 05:05:22 PM PDT 24 Jul 09 05:08:02 PM PDT 24 3161821699 ps
T363 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3295899251 Jul 09 05:05:20 PM PDT 24 Jul 09 05:05:48 PM PDT 24 12720767856 ps
T101 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.160405925 Jul 09 05:05:38 PM PDT 24 Jul 09 05:06:11 PM PDT 24 47985175930 ps
T94 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3376902907 Jul 09 05:05:30 PM PDT 24 Jul 09 05:05:42 PM PDT 24 612575749 ps
T70 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1178196491 Jul 09 05:05:37 PM PDT 24 Jul 09 05:05:48 PM PDT 24 174390315 ps
T364 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2830828371 Jul 09 05:05:22 PM PDT 24 Jul 09 05:05:54 PM PDT 24 3693032920 ps
T71 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2685761476 Jul 09 05:05:21 PM PDT 24 Jul 09 05:05:38 PM PDT 24 3942647629 ps
T53 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3654957819 Jul 09 05:05:35 PM PDT 24 Jul 09 05:05:55 PM PDT 24 2993195279 ps
T102 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2891692038 Jul 09 05:05:28 PM PDT 24 Jul 09 05:07:03 PM PDT 24 9715298799 ps
T72 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.14962431 Jul 09 05:05:24 PM PDT 24 Jul 09 05:05:40 PM PDT 24 3757196080 ps
T54 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3632902229 Jul 09 05:05:36 PM PDT 24 Jul 09 05:07:15 PM PDT 24 2971257912 ps
T55 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3766497484 Jul 09 05:05:27 PM PDT 24 Jul 09 05:05:53 PM PDT 24 2842903386 ps
T365 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.43713657 Jul 09 05:05:19 PM PDT 24 Jul 09 05:05:41 PM PDT 24 3128795975 ps
T73 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2100312456 Jul 09 05:05:22 PM PDT 24 Jul 09 05:05:47 PM PDT 24 10242389408 ps
T95 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.407254698 Jul 09 05:05:42 PM PDT 24 Jul 09 05:06:49 PM PDT 24 9925132261 ps
T68 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1286131719 Jul 09 05:05:31 PM PDT 24 Jul 09 05:06:04 PM PDT 24 14103956724 ps
T366 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2256530493 Jul 09 05:05:21 PM PDT 24 Jul 09 05:05:51 PM PDT 24 3365956966 ps
T367 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3054787484 Jul 09 05:05:21 PM PDT 24 Jul 09 05:05:40 PM PDT 24 5593446201 ps
T69 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2777820751 Jul 09 05:05:31 PM PDT 24 Jul 09 05:05:49 PM PDT 24 783303915 ps
T57 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.199593987 Jul 09 05:05:27 PM PDT 24 Jul 09 05:08:16 PM PDT 24 2788537183 ps
T368 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3016029273 Jul 09 05:05:26 PM PDT 24 Jul 09 05:05:53 PM PDT 24 2045669745 ps
T369 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3636819844 Jul 09 05:05:21 PM PDT 24 Jul 09 05:05:55 PM PDT 24 19754355822 ps
T370 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.974687993 Jul 09 05:05:21 PM PDT 24 Jul 09 05:05:50 PM PDT 24 7008877529 ps
T107 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.769687434 Jul 09 05:05:31 PM PDT 24 Jul 09 05:06:55 PM PDT 24 866162449 ps
T74 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2911469568 Jul 09 05:05:33 PM PDT 24 Jul 09 05:05:46 PM PDT 24 2271871583 ps
T75 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2334750196 Jul 09 05:05:26 PM PDT 24 Jul 09 05:05:44 PM PDT 24 1010040627 ps
T371 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.250367248 Jul 09 05:05:39 PM PDT 24 Jul 09 05:06:05 PM PDT 24 2917657036 ps
T372 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.336404385 Jul 09 05:05:30 PM PDT 24 Jul 09 05:05:50 PM PDT 24 2284654369 ps
T373 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1359417439 Jul 09 05:05:25 PM PDT 24 Jul 09 05:05:56 PM PDT 24 14247086091 ps
T96 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1354548146 Jul 09 05:05:29 PM PDT 24 Jul 09 05:05:45 PM PDT 24 691776740 ps
T97 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1700943487 Jul 09 05:05:22 PM PDT 24 Jul 09 05:05:32 PM PDT 24 918015901 ps
T374 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3494282995 Jul 09 05:05:31 PM PDT 24 Jul 09 05:05:50 PM PDT 24 2197015751 ps
T375 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3551220735 Jul 09 05:05:42 PM PDT 24 Jul 09 05:06:00 PM PDT 24 2920630960 ps
T376 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3506126666 Jul 09 05:05:42 PM PDT 24 Jul 09 05:06:08 PM PDT 24 1968660653 ps
T377 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4233940862 Jul 09 05:05:20 PM PDT 24 Jul 09 05:05:46 PM PDT 24 2992407248 ps
T378 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1457278886 Jul 09 05:05:24 PM PDT 24 Jul 09 05:05:34 PM PDT 24 248802053 ps
T110 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.382960358 Jul 09 05:05:24 PM PDT 24 Jul 09 05:08:14 PM PDT 24 6607701070 ps
T76 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1624443301 Jul 09 05:05:42 PM PDT 24 Jul 09 05:06:09 PM PDT 24 17806275825 ps
T379 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1480666523 Jul 09 05:05:22 PM PDT 24 Jul 09 05:05:53 PM PDT 24 3685541640 ps
T380 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.6038991 Jul 09 05:05:29 PM PDT 24 Jul 09 05:05:49 PM PDT 24 2340813680 ps
T77 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3303897005 Jul 09 05:05:29 PM PDT 24 Jul 09 05:06:28 PM PDT 24 2078308047 ps
T381 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1770982156 Jul 09 05:05:24 PM PDT 24 Jul 09 05:05:47 PM PDT 24 27863523667 ps
T114 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2423597922 Jul 09 05:05:26 PM PDT 24 Jul 09 05:08:10 PM PDT 24 1205025290 ps
T82 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3347958 Jul 09 05:05:34 PM PDT 24 Jul 09 05:07:33 PM PDT 24 49246868568 ps
T382 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.801931187 Jul 09 05:05:21 PM PDT 24 Jul 09 05:05:34 PM PDT 24 346805234 ps
T83 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.257080317 Jul 09 05:05:32 PM PDT 24 Jul 09 05:06:33 PM PDT 24 1064914131 ps
T98 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1179316737 Jul 09 05:05:41 PM PDT 24 Jul 09 05:06:14 PM PDT 24 3390080955 ps
T84 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4278763128 Jul 09 05:05:21 PM PDT 24 Jul 09 05:05:38 PM PDT 24 336044845 ps
T383 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2784557247 Jul 09 05:05:27 PM PDT 24 Jul 09 05:05:39 PM PDT 24 338906784 ps
T384 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3747073503 Jul 09 05:05:36 PM PDT 24 Jul 09 05:06:09 PM PDT 24 7977318785 ps
T106 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.65856544 Jul 09 05:05:25 PM PDT 24 Jul 09 05:07:07 PM PDT 24 7734352822 ps
T99 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1758031411 Jul 09 05:05:25 PM PDT 24 Jul 09 05:05:42 PM PDT 24 834554182 ps
T100 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2065266762 Jul 09 05:05:32 PM PDT 24 Jul 09 05:05:53 PM PDT 24 1569106444 ps
T108 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2233436935 Jul 09 05:05:31 PM PDT 24 Jul 09 05:08:28 PM PDT 24 4618549602 ps
T85 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3389460985 Jul 09 05:05:23 PM PDT 24 Jul 09 05:06:48 PM PDT 24 15370391292 ps
T385 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3895522074 Jul 09 05:05:25 PM PDT 24 Jul 09 05:05:37 PM PDT 24 167314342 ps
T118 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3895389511 Jul 09 05:05:34 PM PDT 24 Jul 09 05:06:58 PM PDT 24 1038110028 ps
T386 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1093356899 Jul 09 05:05:34 PM PDT 24 Jul 09 05:05:55 PM PDT 24 6161003285 ps
T109 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3988449068 Jul 09 05:05:21 PM PDT 24 Jul 09 05:08:16 PM PDT 24 4058732367 ps
T86 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.827653070 Jul 09 05:05:31 PM PDT 24 Jul 09 05:07:43 PM PDT 24 12884634142 ps
T387 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1100372141 Jul 09 05:05:29 PM PDT 24 Jul 09 05:08:14 PM PDT 24 5704618086 ps
T388 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1204034448 Jul 09 05:05:29 PM PDT 24 Jul 09 05:05:52 PM PDT 24 743815510 ps
T389 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1672404323 Jul 09 05:05:24 PM PDT 24 Jul 09 05:06:04 PM PDT 24 58361530004 ps
T390 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1002397811 Jul 09 05:05:15 PM PDT 24 Jul 09 05:05:45 PM PDT 24 21023598835 ps
T391 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1787840871 Jul 09 05:05:28 PM PDT 24 Jul 09 05:05:50 PM PDT 24 1083942661 ps
T392 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.902160774 Jul 09 05:05:32 PM PDT 24 Jul 09 05:05:59 PM PDT 24 43800683859 ps
T393 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4000407354 Jul 09 05:05:34 PM PDT 24 Jul 09 05:08:43 PM PDT 24 86786898659 ps
T117 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4146528803 Jul 09 05:05:34 PM PDT 24 Jul 09 05:07:05 PM PDT 24 823951977 ps
T394 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3854761234 Jul 09 05:05:39 PM PDT 24 Jul 09 05:06:34 PM PDT 24 2025017177 ps
T395 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3161034895 Jul 09 05:05:32 PM PDT 24 Jul 09 05:06:08 PM PDT 24 16743442963 ps
T396 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1293120418 Jul 09 05:05:19 PM PDT 24 Jul 09 05:05:29 PM PDT 24 201085792 ps
T397 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1354434149 Jul 09 05:05:32 PM PDT 24 Jul 09 05:08:27 PM PDT 24 37693363295 ps
T398 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4003051963 Jul 09 05:05:25 PM PDT 24 Jul 09 05:05:38 PM PDT 24 1270706919 ps
T399 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1231308926 Jul 09 05:05:30 PM PDT 24 Jul 09 05:06:03 PM PDT 24 17854961685 ps
T111 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2937193091 Jul 09 05:05:31 PM PDT 24 Jul 09 05:07:01 PM PDT 24 8008373249 ps
T400 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.766069440 Jul 09 05:05:34 PM PDT 24 Jul 09 05:06:09 PM PDT 24 3953261700 ps
T401 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.251593095 Jul 09 05:05:26 PM PDT 24 Jul 09 05:05:39 PM PDT 24 167486644 ps
T92 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3092965026 Jul 09 05:05:29 PM PDT 24 Jul 09 05:06:05 PM PDT 24 40211390815 ps
T402 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1173369997 Jul 09 05:05:26 PM PDT 24 Jul 09 05:05:48 PM PDT 24 7073881352 ps
T403 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1459384892 Jul 09 05:05:29 PM PDT 24 Jul 09 05:05:50 PM PDT 24 833813946 ps
T404 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2208120059 Jul 09 05:05:28 PM PDT 24 Jul 09 05:05:44 PM PDT 24 2963204162 ps
T93 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3553017435 Jul 09 05:05:13 PM PDT 24 Jul 09 05:07:28 PM PDT 24 16254588396 ps
T405 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.649828957 Jul 09 05:05:22 PM PDT 24 Jul 09 05:06:01 PM PDT 24 8518257016 ps
T406 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2017310234 Jul 09 05:05:36 PM PDT 24 Jul 09 05:06:08 PM PDT 24 3174949242 ps
T407 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3085651181 Jul 09 05:05:28 PM PDT 24 Jul 09 05:07:17 PM PDT 24 17665845561 ps
T116 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2112425674 Jul 09 05:05:26 PM PDT 24 Jul 09 05:06:51 PM PDT 24 464466270 ps
T408 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.590352607 Jul 09 05:05:22 PM PDT 24 Jul 09 05:05:52 PM PDT 24 3679558884 ps
T409 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1306748674 Jul 09 05:05:36 PM PDT 24 Jul 09 05:06:05 PM PDT 24 11739367098 ps
T410 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2229531773 Jul 09 05:05:23 PM PDT 24 Jul 09 05:07:05 PM PDT 24 44729315124 ps
T87 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1980088310 Jul 09 05:05:39 PM PDT 24 Jul 09 05:06:49 PM PDT 24 9972324149 ps
T88 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3102727317 Jul 09 05:05:31 PM PDT 24 Jul 09 05:05:42 PM PDT 24 169005887 ps
T411 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1628436775 Jul 09 05:05:25 PM PDT 24 Jul 09 05:05:40 PM PDT 24 662122796 ps
T412 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1694938649 Jul 09 05:05:36 PM PDT 24 Jul 09 05:05:49 PM PDT 24 1320332115 ps
T413 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1452061974 Jul 09 05:05:34 PM PDT 24 Jul 09 05:05:48 PM PDT 24 176401770 ps
T414 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1084786223 Jul 09 05:05:33 PM PDT 24 Jul 09 05:07:02 PM PDT 24 17860130966 ps
T415 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4050768559 Jul 09 05:05:22 PM PDT 24 Jul 09 05:05:56 PM PDT 24 7684776463 ps
T416 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2233627598 Jul 09 05:05:36 PM PDT 24 Jul 09 05:05:51 PM PDT 24 338911142 ps
T417 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2857588729 Jul 09 05:05:27 PM PDT 24 Jul 09 05:05:50 PM PDT 24 10515167100 ps
T112 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2215726641 Jul 09 05:05:23 PM PDT 24 Jul 09 05:08:04 PM PDT 24 1733014265 ps
T418 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3825229100 Jul 09 05:05:25 PM PDT 24 Jul 09 05:05:54 PM PDT 24 12271371917 ps
T419 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1555125847 Jul 09 05:05:23 PM PDT 24 Jul 09 05:05:45 PM PDT 24 7845736208 ps
T420 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1891042195 Jul 09 05:05:37 PM PDT 24 Jul 09 05:06:12 PM PDT 24 16714578778 ps
T421 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3750425479 Jul 09 05:05:27 PM PDT 24 Jul 09 05:05:58 PM PDT 24 23864582874 ps
T422 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3536612235 Jul 09 05:05:32 PM PDT 24 Jul 09 05:05:43 PM PDT 24 689517256 ps
T423 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.869596117 Jul 09 05:05:20 PM PDT 24 Jul 09 05:05:45 PM PDT 24 3566886530 ps
T424 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3678042897 Jul 09 05:05:31 PM PDT 24 Jul 09 05:05:46 PM PDT 24 5228323283 ps
T113 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1065474058 Jul 09 05:05:32 PM PDT 24 Jul 09 05:07:00 PM PDT 24 430576480 ps
T425 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3358648396 Jul 09 05:05:26 PM PDT 24 Jul 09 05:06:02 PM PDT 24 4404850922 ps
T426 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2602254182 Jul 09 05:05:33 PM PDT 24 Jul 09 05:06:08 PM PDT 24 28710437575 ps
T427 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3891681134 Jul 09 05:05:38 PM PDT 24 Jul 09 05:07:20 PM PDT 24 3166964374 ps
T115 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4277871070 Jul 09 05:05:34 PM PDT 24 Jul 09 05:07:19 PM PDT 24 3977695438 ps
T89 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4008629101 Jul 09 05:05:21 PM PDT 24 Jul 09 05:05:45 PM PDT 24 2472584249 ps
T428 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2212804999 Jul 09 05:05:28 PM PDT 24 Jul 09 05:05:45 PM PDT 24 673325260 ps
T429 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2489968205 Jul 09 05:05:22 PM PDT 24 Jul 09 05:05:33 PM PDT 24 193616904 ps
T430 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.348694117 Jul 09 05:05:33 PM PDT 24 Jul 09 05:05:50 PM PDT 24 846455874 ps
T431 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2572452917 Jul 09 05:05:33 PM PDT 24 Jul 09 05:06:01 PM PDT 24 4112072786 ps
T432 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2851137535 Jul 09 05:05:28 PM PDT 24 Jul 09 05:05:53 PM PDT 24 8978248485 ps
T433 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1823801240 Jul 09 05:05:26 PM PDT 24 Jul 09 05:06:05 PM PDT 24 3859060574 ps
T434 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1550448027 Jul 09 05:05:35 PM PDT 24 Jul 09 05:05:46 PM PDT 24 347172616 ps
T90 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1227127701 Jul 09 05:05:28 PM PDT 24 Jul 09 05:06:52 PM PDT 24 99058218036 ps
T435 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4085868926 Jul 09 05:05:23 PM PDT 24 Jul 09 05:05:36 PM PDT 24 672847687 ps
T436 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2113396416 Jul 09 05:05:37 PM PDT 24 Jul 09 05:06:12 PM PDT 24 3673812174 ps
T437 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.4222749113 Jul 09 05:05:35 PM PDT 24 Jul 09 05:06:11 PM PDT 24 7798406781 ps
T438 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4205804881 Jul 09 05:05:28 PM PDT 24 Jul 09 05:05:57 PM PDT 24 11776875906 ps
T439 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.122825607 Jul 09 05:05:30 PM PDT 24 Jul 09 05:05:51 PM PDT 24 3059078222 ps
T440 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.694682461 Jul 09 05:05:38 PM PDT 24 Jul 09 05:06:12 PM PDT 24 5779516535 ps
T441 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.421154136 Jul 09 05:05:36 PM PDT 24 Jul 09 05:07:12 PM PDT 24 9786263252 ps
T442 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3197409572 Jul 09 05:05:37 PM PDT 24 Jul 09 05:06:07 PM PDT 24 3135186079 ps
T443 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.287078757 Jul 09 05:05:32 PM PDT 24 Jul 09 05:08:15 PM PDT 24 7988442386 ps
T91 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1860590057 Jul 09 05:05:29 PM PDT 24 Jul 09 05:07:34 PM PDT 24 14749710621 ps
T444 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3579613141 Jul 09 05:05:25 PM PDT 24 Jul 09 05:08:28 PM PDT 24 8826756448 ps
T445 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.61706325 Jul 09 05:05:39 PM PDT 24 Jul 09 05:05:51 PM PDT 24 222233913 ps
T446 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1757024130 Jul 09 05:05:32 PM PDT 24 Jul 09 05:05:55 PM PDT 24 4123260589 ps
T447 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2837528011 Jul 09 05:05:25 PM PDT 24 Jul 09 05:05:38 PM PDT 24 989977735 ps
T448 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3428953829 Jul 09 05:05:31 PM PDT 24 Jul 09 05:05:59 PM PDT 24 11478565539 ps
T449 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3525160894 Jul 09 05:05:24 PM PDT 24 Jul 09 05:05:59 PM PDT 24 8391210414 ps
T450 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1463081094 Jul 09 05:05:40 PM PDT 24 Jul 09 05:07:23 PM PDT 24 9965276540 ps
T451 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.796805374 Jul 09 05:05:26 PM PDT 24 Jul 09 05:05:55 PM PDT 24 2193554213 ps
T452 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2466251338 Jul 09 05:05:38 PM PDT 24 Jul 09 05:06:08 PM PDT 24 10788555524 ps
T453 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2859309475 Jul 09 05:05:40 PM PDT 24 Jul 09 05:07:36 PM PDT 24 36978923942 ps
T454 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3450875033 Jul 09 05:05:35 PM PDT 24 Jul 09 05:05:45 PM PDT 24 170968449 ps
T455 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2710617259 Jul 09 05:05:26 PM PDT 24 Jul 09 05:05:41 PM PDT 24 688545529 ps
T456 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.51909324 Jul 09 05:05:21 PM PDT 24 Jul 09 05:05:44 PM PDT 24 2124641684 ps

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3054767679
Short name T4
Test name
Test status
Simulation time 3051081307 ps
CPU time 48.17 seconds
Started Jul 09 05:06:52 PM PDT 24
Finished Jul 09 05:07:41 PM PDT 24
Peak memory 220244 kb
Host smart-e9947a44-6a37-4513-8224-1cb8bd7c2f95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054767679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3054767679
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.1500977629
Short name T14
Test name
Test status
Simulation time 154969101470 ps
CPU time 1451.4 seconds
Started Jul 09 05:05:49 PM PDT 24
Finished Jul 09 05:30:07 PM PDT 24
Peak memory 243948 kb
Host smart-cc0a1ca1-a87a-4a04-8507-fb5c95736cf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500977629 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.1500977629
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.773447670
Short name T7
Test name
Test status
Simulation time 72568933347 ps
CPU time 784.42 seconds
Started Jul 09 05:06:34 PM PDT 24
Finished Jul 09 05:19:39 PM PDT 24
Peak memory 237600 kb
Host smart-806c00b5-618a-4bf1-8969-a7f1263b7b80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773447670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.773447670
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.199593987
Short name T57
Test name
Test status
Simulation time 2788537183 ps
CPU time 165.49 seconds
Started Jul 09 05:05:27 PM PDT 24
Finished Jul 09 05:08:16 PM PDT 24
Peak memory 213780 kb
Host smart-0c2654d8-6f2a-4ac8-b10b-610c41f22725
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199593987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.199593987
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1744969857
Short name T80
Test name
Test status
Simulation time 683543409 ps
CPU time 20.96 seconds
Started Jul 09 05:05:51 PM PDT 24
Finished Jul 09 05:06:20 PM PDT 24
Peak memory 217428 kb
Host smart-82a98304-67ae-4e25-867b-0ed3d222076b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744969857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1744969857
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.461272946
Short name T215
Test name
Test status
Simulation time 144840319870 ps
CPU time 690.52 seconds
Started Jul 09 05:06:25 PM PDT 24
Finished Jul 09 05:17:57 PM PDT 24
Peak memory 229532 kb
Host smart-cbc18abb-62cf-4022-bc5f-46fd580cfc9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461272946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.461272946
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.909117808
Short name T22
Test name
Test status
Simulation time 6760087314 ps
CPU time 123.72 seconds
Started Jul 09 05:05:43 PM PDT 24
Finished Jul 09 05:07:52 PM PDT 24
Peak memory 236504 kb
Host smart-70a8e3e4-ace9-4508-8544-fd875239c7f6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909117808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.909117808
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2334750196
Short name T75
Test name
Test status
Simulation time 1010040627 ps
CPU time 14.63 seconds
Started Jul 09 05:05:26 PM PDT 24
Finished Jul 09 05:05:44 PM PDT 24
Peak memory 211612 kb
Host smart-dd10d30d-54c9-433a-91c2-3faecc33847e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334750196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2334750196
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3146593131
Short name T142
Test name
Test status
Simulation time 8194428424 ps
CPU time 16.72 seconds
Started Jul 09 05:06:29 PM PDT 24
Finished Jul 09 05:06:47 PM PDT 24
Peak memory 213228 kb
Host smart-8ec1f93f-5e9a-4de8-b38e-d90904c2e7f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146593131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3146593131
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1347518718
Short name T52
Test name
Test status
Simulation time 3161821699 ps
CPU time 158.18 seconds
Started Jul 09 05:05:22 PM PDT 24
Finished Jul 09 05:08:02 PM PDT 24
Peak memory 213800 kb
Host smart-1e763751-322a-4612-b9f2-17c1a53ffdfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347518718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1347518718
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.447894559
Short name T160
Test name
Test status
Simulation time 6616471964 ps
CPU time 58.52 seconds
Started Jul 09 05:05:42 PM PDT 24
Finished Jul 09 05:06:46 PM PDT 24
Peak memory 219300 kb
Host smart-efa72114-91ba-440e-87c6-996ffe331bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447894559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.447894559
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.41117037
Short name T28
Test name
Test status
Simulation time 661906087 ps
CPU time 18.8 seconds
Started Jul 09 05:05:39 PM PDT 24
Finished Jul 09 05:06:03 PM PDT 24
Peak memory 219280 kb
Host smart-9cf45904-4a15-4de2-a78c-6d7e2ce73b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41117037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.41117037
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2215726641
Short name T112
Test name
Test status
Simulation time 1733014265 ps
CPU time 159.07 seconds
Started Jul 09 05:05:23 PM PDT 24
Finished Jul 09 05:08:04 PM PDT 24
Peak memory 213660 kb
Host smart-afaadbd8-32bf-4b22-8bc1-7575c75cd415
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215726641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2215726641
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3376902907
Short name T94
Test name
Test status
Simulation time 612575749 ps
CPU time 8.3 seconds
Started Jul 09 05:05:30 PM PDT 24
Finished Jul 09 05:05:42 PM PDT 24
Peak memory 211028 kb
Host smart-4c29e9e0-fafe-43a1-92e8-0886473b14cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376902907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3376902907
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1065474058
Short name T113
Test name
Test status
Simulation time 430576480 ps
CPU time 84.2 seconds
Started Jul 09 05:05:32 PM PDT 24
Finished Jul 09 05:07:00 PM PDT 24
Peak memory 213112 kb
Host smart-37dbda05-8982-4bea-90fc-242a04843bd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065474058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1065474058
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4146528803
Short name T117
Test name
Test status
Simulation time 823951977 ps
CPU time 88.55 seconds
Started Jul 09 05:05:34 PM PDT 24
Finished Jul 09 05:07:05 PM PDT 24
Peak memory 213304 kb
Host smart-a940dd96-27ce-4ec5-a2fe-e6933f323aba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146528803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.4146528803
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2443576193
Short name T122
Test name
Test status
Simulation time 1077425662 ps
CPU time 17.51 seconds
Started Jul 09 05:05:51 PM PDT 24
Finished Jul 09 05:06:16 PM PDT 24
Peak memory 219220 kb
Host smart-56d4dab4-32c9-4319-bdeb-f9595532f35d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2443576193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2443576193
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1555125847
Short name T419
Test name
Test status
Simulation time 7845736208 ps
CPU time 19.95 seconds
Started Jul 09 05:05:23 PM PDT 24
Finished Jul 09 05:05:45 PM PDT 24
Peak memory 211844 kb
Host smart-0d04e55e-3339-4ee9-a068-22706787220b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555125847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1555125847
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3054787484
Short name T367
Test name
Test status
Simulation time 5593446201 ps
CPU time 17.57 seconds
Started Jul 09 05:05:21 PM PDT 24
Finished Jul 09 05:05:40 PM PDT 24
Peak memory 210644 kb
Host smart-8aa74d11-e2aa-458b-87fc-8afbebd385fa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054787484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3054787484
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4278763128
Short name T84
Test name
Test status
Simulation time 336044845 ps
CPU time 15.56 seconds
Started Jul 09 05:05:21 PM PDT 24
Finished Jul 09 05:05:38 PM PDT 24
Peak memory 211656 kb
Host smart-56bed1e9-ac29-4282-bec7-67858408f5fe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278763128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.4278763128
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1480666523
Short name T379
Test name
Test status
Simulation time 3685541640 ps
CPU time 29.66 seconds
Started Jul 09 05:05:22 PM PDT 24
Finished Jul 09 05:05:53 PM PDT 24
Peak memory 216732 kb
Host smart-24c30d04-9608-41e2-b11e-fbbe43666753
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480666523 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1480666523
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2685761476
Short name T71
Test name
Test status
Simulation time 3942647629 ps
CPU time 15.61 seconds
Started Jul 09 05:05:21 PM PDT 24
Finished Jul 09 05:05:38 PM PDT 24
Peak memory 210848 kb
Host smart-1668b6cf-ea55-420c-8580-63c8003f6f4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685761476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2685761476
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4233940862
Short name T377
Test name
Test status
Simulation time 2992407248 ps
CPU time 24.97 seconds
Started Jul 09 05:05:20 PM PDT 24
Finished Jul 09 05:05:46 PM PDT 24
Peak memory 210552 kb
Host smart-c0fd6691-9ff5-45c2-ad18-2776adab8dc3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233940862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.4233940862
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.974687993
Short name T370
Test name
Test status
Simulation time 7008877529 ps
CPU time 27.44 seconds
Started Jul 09 05:05:21 PM PDT 24
Finished Jul 09 05:05:50 PM PDT 24
Peak memory 210500 kb
Host smart-d1d304e5-0713-4f6c-9df6-365d4e1b76b6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974687993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
974687993
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3553017435
Short name T93
Test name
Test status
Simulation time 16254588396 ps
CPU time 131.03 seconds
Started Jul 09 05:05:13 PM PDT 24
Finished Jul 09 05:07:28 PM PDT 24
Peak memory 214024 kb
Host smart-584bf9bc-10b8-47cf-a54d-9ef5d6aa75f5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553017435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3553017435
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1672404323
Short name T389
Test name
Test status
Simulation time 58361530004 ps
CPU time 38.14 seconds
Started Jul 09 05:05:24 PM PDT 24
Finished Jul 09 05:06:04 PM PDT 24
Peak memory 213272 kb
Host smart-690ee0ff-68f3-4c85-8fd7-cc5872d6b2da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672404323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1672404323
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1002397811
Short name T390
Test name
Test status
Simulation time 21023598835 ps
CPU time 27.01 seconds
Started Jul 09 05:05:15 PM PDT 24
Finished Jul 09 05:05:45 PM PDT 24
Peak memory 218736 kb
Host smart-e706fa31-5b4a-4faf-8ec9-3c59db0914b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002397811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1002397811
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2256530493
Short name T366
Test name
Test status
Simulation time 3365956966 ps
CPU time 28.82 seconds
Started Jul 09 05:05:21 PM PDT 24
Finished Jul 09 05:05:51 PM PDT 24
Peak memory 211012 kb
Host smart-889628bb-bd64-409b-a056-15e663a371be
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256530493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2256530493
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3295899251
Short name T363
Test name
Test status
Simulation time 12720767856 ps
CPU time 27.18 seconds
Started Jul 09 05:05:20 PM PDT 24
Finished Jul 09 05:05:48 PM PDT 24
Peak memory 211584 kb
Host smart-8f2dabc2-98d5-4065-88e1-e8ba970b548a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295899251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3295899251
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.649828957
Short name T405
Test name
Test status
Simulation time 8518257016 ps
CPU time 36.92 seconds
Started Jul 09 05:05:22 PM PDT 24
Finished Jul 09 05:06:01 PM PDT 24
Peak memory 211828 kb
Host smart-360443c0-6c43-436f-9ee7-84206587875f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649828957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.649828957
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2489968205
Short name T429
Test name
Test status
Simulation time 193616904 ps
CPU time 9.53 seconds
Started Jul 09 05:05:22 PM PDT 24
Finished Jul 09 05:05:33 PM PDT 24
Peak memory 217444 kb
Host smart-019febbc-fc01-4302-b0de-71dc7676fdef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489968205 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2489968205
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.590352607
Short name T408
Test name
Test status
Simulation time 3679558884 ps
CPU time 29.32 seconds
Started Jul 09 05:05:22 PM PDT 24
Finished Jul 09 05:05:52 PM PDT 24
Peak memory 211828 kb
Host smart-06d532e6-05ef-43bd-af69-49098581ba44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590352607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.590352607
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1293120418
Short name T396
Test name
Test status
Simulation time 201085792 ps
CPU time 8.45 seconds
Started Jul 09 05:05:19 PM PDT 24
Finished Jul 09 05:05:29 PM PDT 24
Peak memory 210464 kb
Host smart-6cb3677c-de2c-4ef5-b6b8-a02ca5fc4428
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293120418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1293120418
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.43713657
Short name T365
Test name
Test status
Simulation time 3128795975 ps
CPU time 21.14 seconds
Started Jul 09 05:05:19 PM PDT 24
Finished Jul 09 05:05:41 PM PDT 24
Peak memory 210532 kb
Host smart-a5903e83-6c9b-41ad-af80-413cf4fd1d25
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43713657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.43713657
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3389460985
Short name T85
Test name
Test status
Simulation time 15370391292 ps
CPU time 83.22 seconds
Started Jul 09 05:05:23 PM PDT 24
Finished Jul 09 05:06:48 PM PDT 24
Peak memory 213560 kb
Host smart-d3d199e4-5321-42f7-bea6-a03815c062a3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389460985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3389460985
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4085868926
Short name T435
Test name
Test status
Simulation time 672847687 ps
CPU time 10.8 seconds
Started Jul 09 05:05:23 PM PDT 24
Finished Jul 09 05:05:36 PM PDT 24
Peak memory 211452 kb
Host smart-f4f19120-a98f-4844-b29e-6c5bf626d39d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085868926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.4085868926
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.869596117
Short name T423
Test name
Test status
Simulation time 3566886530 ps
CPU time 24.43 seconds
Started Jul 09 05:05:20 PM PDT 24
Finished Jul 09 05:05:45 PM PDT 24
Peak memory 218184 kb
Host smart-1ac5aa52-68b8-43f1-aa3a-1c8c0025f881
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869596117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.869596117
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2777820751
Short name T69
Test name
Test status
Simulation time 783303915 ps
CPU time 13.89 seconds
Started Jul 09 05:05:31 PM PDT 24
Finished Jul 09 05:05:49 PM PDT 24
Peak memory 215964 kb
Host smart-cb85f927-ccbb-4084-8930-e366b8a62d73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777820751 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2777820751
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3102727317
Short name T88
Test name
Test status
Simulation time 169005887 ps
CPU time 8.17 seconds
Started Jul 09 05:05:31 PM PDT 24
Finished Jul 09 05:05:42 PM PDT 24
Peak memory 210968 kb
Host smart-29a011bc-a087-4613-84bb-920d82b6f40d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102727317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3102727317
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.827653070
Short name T86
Test name
Test status
Simulation time 12884634142 ps
CPU time 127.91 seconds
Started Jul 09 05:05:31 PM PDT 24
Finished Jul 09 05:07:43 PM PDT 24
Peak memory 216316 kb
Host smart-ed1bf2f2-0f19-4247-b7de-7fd93e1ae5ba
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827653070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.827653070
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2065266762
Short name T100
Test name
Test status
Simulation time 1569106444 ps
CPU time 17.73 seconds
Started Jul 09 05:05:32 PM PDT 24
Finished Jul 09 05:05:53 PM PDT 24
Peak memory 211084 kb
Host smart-5e35adb9-eccf-4d41-b5d5-b5a7672c0a38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065266762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2065266762
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3494282995
Short name T374
Test name
Test status
Simulation time 2197015751 ps
CPU time 15.19 seconds
Started Jul 09 05:05:31 PM PDT 24
Finished Jul 09 05:05:50 PM PDT 24
Peak memory 217480 kb
Host smart-95b409c0-8ad0-49b8-8b39-f978257a9963
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494282995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3494282995
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1286131719
Short name T68
Test name
Test status
Simulation time 14103956724 ps
CPU time 29.53 seconds
Started Jul 09 05:05:31 PM PDT 24
Finished Jul 09 05:06:04 PM PDT 24
Peak memory 217848 kb
Host smart-c228ac19-158b-4bad-a602-23051f7b386f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286131719 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1286131719
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2437323505
Short name T59
Test name
Test status
Simulation time 11702413794 ps
CPU time 25.1 seconds
Started Jul 09 05:05:33 PM PDT 24
Finished Jul 09 05:06:01 PM PDT 24
Peak memory 211680 kb
Host smart-98b894bd-a1cb-4a47-a766-642773da51dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437323505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2437323505
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1354434149
Short name T397
Test name
Test status
Simulation time 37693363295 ps
CPU time 172 seconds
Started Jul 09 05:05:32 PM PDT 24
Finished Jul 09 05:08:27 PM PDT 24
Peak memory 215016 kb
Host smart-80ac7621-2852-41f1-ae9a-3c568c9bc90e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354434149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1354434149
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1757024130
Short name T446
Test name
Test status
Simulation time 4123260589 ps
CPU time 20.2 seconds
Started Jul 09 05:05:32 PM PDT 24
Finished Jul 09 05:05:55 PM PDT 24
Peak memory 218568 kb
Host smart-a97416b7-204b-49e7-9b14-4c35cdcd0adc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757024130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1757024130
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3895389511
Short name T118
Test name
Test status
Simulation time 1038110028 ps
CPU time 81.46 seconds
Started Jul 09 05:05:34 PM PDT 24
Finished Jul 09 05:06:58 PM PDT 24
Peak memory 213520 kb
Host smart-fc8edcf8-1c3a-4957-8140-4e2df55538e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895389511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3895389511
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3161034895
Short name T395
Test name
Test status
Simulation time 16743442963 ps
CPU time 33.06 seconds
Started Jul 09 05:05:32 PM PDT 24
Finished Jul 09 05:06:08 PM PDT 24
Peak memory 217272 kb
Host smart-e8005c61-3f76-4c1d-b4af-79bf01d01767
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161034895 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3161034895
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2911469568
Short name T74
Test name
Test status
Simulation time 2271871583 ps
CPU time 10.93 seconds
Started Jul 09 05:05:33 PM PDT 24
Finished Jul 09 05:05:46 PM PDT 24
Peak memory 210836 kb
Host smart-aa511068-1024-4212-a480-28cdf688eddd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911469568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2911469568
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.257080317
Short name T83
Test name
Test status
Simulation time 1064914131 ps
CPU time 58.16 seconds
Started Jul 09 05:05:32 PM PDT 24
Finished Jul 09 05:06:33 PM PDT 24
Peak memory 213700 kb
Host smart-a4ba2e88-8df3-4fc1-802e-b3d54f509f6d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257080317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.257080317
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3428953829
Short name T448
Test name
Test status
Simulation time 11478565539 ps
CPU time 24.94 seconds
Started Jul 09 05:05:31 PM PDT 24
Finished Jul 09 05:05:59 PM PDT 24
Peak memory 212304 kb
Host smart-2fc8dc33-0351-404e-806e-7095c51878cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428953829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3428953829
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2572452917
Short name T431
Test name
Test status
Simulation time 4112072786 ps
CPU time 25.08 seconds
Started Jul 09 05:05:33 PM PDT 24
Finished Jul 09 05:06:01 PM PDT 24
Peak memory 218384 kb
Host smart-5d631e7b-8795-4095-b158-ed69097c352f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572452917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2572452917
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.769687434
Short name T107
Test name
Test status
Simulation time 866162449 ps
CPU time 80.95 seconds
Started Jul 09 05:05:31 PM PDT 24
Finished Jul 09 05:06:55 PM PDT 24
Peak memory 213412 kb
Host smart-17e7ca07-13ba-4898-b50e-17f36584026d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769687434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.769687434
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2602254182
Short name T426
Test name
Test status
Simulation time 28710437575 ps
CPU time 32.38 seconds
Started Jul 09 05:05:33 PM PDT 24
Finished Jul 09 05:06:08 PM PDT 24
Peak memory 218972 kb
Host smart-24370fa1-63f3-4beb-8635-cf880cc44918
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602254182 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2602254182
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3092965026
Short name T92
Test name
Test status
Simulation time 40211390815 ps
CPU time 32.1 seconds
Started Jul 09 05:05:29 PM PDT 24
Finished Jul 09 05:06:05 PM PDT 24
Peak memory 212244 kb
Host smart-e604d416-f9fa-4d9e-a844-f2e8073be196
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092965026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3092965026
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1227127701
Short name T90
Test name
Test status
Simulation time 99058218036 ps
CPU time 80.46 seconds
Started Jul 09 05:05:28 PM PDT 24
Finished Jul 09 05:06:52 PM PDT 24
Peak memory 213724 kb
Host smart-a750b876-ac39-42a3-bfa2-3ec2bb5af6c8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227127701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1227127701
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1231308926
Short name T399
Test name
Test status
Simulation time 17854961685 ps
CPU time 29.79 seconds
Started Jul 09 05:05:30 PM PDT 24
Finished Jul 09 05:06:03 PM PDT 24
Peak memory 212588 kb
Host smart-e8627887-ee67-4ad3-b11d-fb95564e002b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231308926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1231308926
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.336404385
Short name T372
Test name
Test status
Simulation time 2284654369 ps
CPU time 16.89 seconds
Started Jul 09 05:05:30 PM PDT 24
Finished Jul 09 05:05:50 PM PDT 24
Peak memory 217372 kb
Host smart-83adec85-4240-43e2-91d6-90d57a99ce25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336404385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.336404385
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2937193091
Short name T111
Test name
Test status
Simulation time 8008373249 ps
CPU time 86.77 seconds
Started Jul 09 05:05:31 PM PDT 24
Finished Jul 09 05:07:01 PM PDT 24
Peak memory 213996 kb
Host smart-f24586cb-12b3-4e4f-9d0d-d0f8494a58af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937193091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2937193091
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1550448027
Short name T434
Test name
Test status
Simulation time 347172616 ps
CPU time 9.17 seconds
Started Jul 09 05:05:35 PM PDT 24
Finished Jul 09 05:05:46 PM PDT 24
Peak memory 216704 kb
Host smart-db954ee1-2d41-417a-98ec-c0ea8ddcf069
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550448027 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1550448027
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.122825607
Short name T439
Test name
Test status
Simulation time 3059078222 ps
CPU time 17.26 seconds
Started Jul 09 05:05:30 PM PDT 24
Finished Jul 09 05:05:51 PM PDT 24
Peak memory 211404 kb
Host smart-cd194d25-8593-42c3-bb38-3656260a3d8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122825607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.122825607
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4000407354
Short name T393
Test name
Test status
Simulation time 86786898659 ps
CPU time 186.38 seconds
Started Jul 09 05:05:34 PM PDT 24
Finished Jul 09 05:08:43 PM PDT 24
Peak memory 214796 kb
Host smart-aee13e6d-9320-4f15-a503-468c52d1f36e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000407354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.4000407354
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3197409572
Short name T442
Test name
Test status
Simulation time 3135186079 ps
CPU time 26.3 seconds
Started Jul 09 05:05:37 PM PDT 24
Finished Jul 09 05:06:07 PM PDT 24
Peak memory 212036 kb
Host smart-c808015b-e749-4703-95c8-4c4169f6b3ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197409572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3197409572
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1204034448
Short name T388
Test name
Test status
Simulation time 743815510 ps
CPU time 18.63 seconds
Started Jul 09 05:05:29 PM PDT 24
Finished Jul 09 05:05:52 PM PDT 24
Peak memory 218416 kb
Host smart-fb12386b-69af-4495-bd63-9fbbfa88de7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204034448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1204034448
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1100372141
Short name T387
Test name
Test status
Simulation time 5704618086 ps
CPU time 161.53 seconds
Started Jul 09 05:05:29 PM PDT 24
Finished Jul 09 05:08:14 PM PDT 24
Peak memory 213876 kb
Host smart-0833cbee-5d66-4543-a704-b935f46d22e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100372141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1100372141
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3747073503
Short name T384
Test name
Test status
Simulation time 7977318785 ps
CPU time 30.12 seconds
Started Jul 09 05:05:36 PM PDT 24
Finished Jul 09 05:06:09 PM PDT 24
Peak memory 217984 kb
Host smart-af78cbe2-e6e3-41ec-adb8-b794bbcd39a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747073503 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3747073503
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1306748674
Short name T409
Test name
Test status
Simulation time 11739367098 ps
CPU time 26.54 seconds
Started Jul 09 05:05:36 PM PDT 24
Finished Jul 09 05:06:05 PM PDT 24
Peak memory 212324 kb
Host smart-404a3a0b-84fd-48de-bfa8-5fb34cf238f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306748674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1306748674
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3854761234
Short name T394
Test name
Test status
Simulation time 2025017177 ps
CPU time 51.27 seconds
Started Jul 09 05:05:39 PM PDT 24
Finished Jul 09 05:06:34 PM PDT 24
Peak memory 212584 kb
Host smart-ca140116-e41d-4533-868a-a7a940599c80
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854761234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3854761234
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1694938649
Short name T412
Test name
Test status
Simulation time 1320332115 ps
CPU time 10.66 seconds
Started Jul 09 05:05:36 PM PDT 24
Finished Jul 09 05:05:49 PM PDT 24
Peak memory 211144 kb
Host smart-0d2f4f4b-8b9d-4a6e-98ed-ae82b523bfb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694938649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1694938649
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.250367248
Short name T371
Test name
Test status
Simulation time 2917657036 ps
CPU time 21.95 seconds
Started Jul 09 05:05:39 PM PDT 24
Finished Jul 09 05:06:05 PM PDT 24
Peak memory 218916 kb
Host smart-1a573ef4-34be-41f7-84c5-6c224d57f37e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250367248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.250367248
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3551220735
Short name T375
Test name
Test status
Simulation time 2920630960 ps
CPU time 13.26 seconds
Started Jul 09 05:05:42 PM PDT 24
Finished Jul 09 05:06:00 PM PDT 24
Peak memory 216280 kb
Host smart-1eb2a7a0-fa7a-4de5-9069-732ace0aacc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551220735 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3551220735
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.61706325
Short name T445
Test name
Test status
Simulation time 222233913 ps
CPU time 8.31 seconds
Started Jul 09 05:05:39 PM PDT 24
Finished Jul 09 05:05:51 PM PDT 24
Peak memory 210596 kb
Host smart-222c2f36-1e6f-483d-b038-8c8350e89d49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61706325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.61706325
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1980088310
Short name T87
Test name
Test status
Simulation time 9972324149 ps
CPU time 65.41 seconds
Started Jul 09 05:05:39 PM PDT 24
Finished Jul 09 05:06:49 PM PDT 24
Peak memory 214152 kb
Host smart-4b7b3937-4b94-4d42-9d5c-a445a5be9460
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980088310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1980088310
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1179316737
Short name T98
Test name
Test status
Simulation time 3390080955 ps
CPU time 27.09 seconds
Started Jul 09 05:05:41 PM PDT 24
Finished Jul 09 05:06:14 PM PDT 24
Peak memory 212068 kb
Host smart-155b9e13-3292-4aa7-a60d-4e5246e32fa4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179316737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1179316737
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1452061974
Short name T413
Test name
Test status
Simulation time 176401770 ps
CPU time 11.42 seconds
Started Jul 09 05:05:34 PM PDT 24
Finished Jul 09 05:05:48 PM PDT 24
Peak memory 216900 kb
Host smart-52330da3-5df7-415c-87f4-4979eec21b0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452061974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1452061974
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4277871070
Short name T115
Test name
Test status
Simulation time 3977695438 ps
CPU time 102.39 seconds
Started Jul 09 05:05:34 PM PDT 24
Finished Jul 09 05:07:19 PM PDT 24
Peak memory 213332 kb
Host smart-8e34925e-3b9e-4437-bc06-1c33fb960cce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277871070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.4277871070
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3654957819
Short name T53
Test name
Test status
Simulation time 2993195279 ps
CPU time 17.77 seconds
Started Jul 09 05:05:35 PM PDT 24
Finished Jul 09 05:05:55 PM PDT 24
Peak memory 217924 kb
Host smart-57e80c80-69ba-4dc8-92d1-1d5aa984d0aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654957819 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3654957819
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2113396416
Short name T436
Test name
Test status
Simulation time 3673812174 ps
CPU time 30.74 seconds
Started Jul 09 05:05:37 PM PDT 24
Finished Jul 09 05:06:12 PM PDT 24
Peak memory 211132 kb
Host smart-b9852da4-670c-40f5-bac5-3194d1901597
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113396416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2113396416
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2859309475
Short name T453
Test name
Test status
Simulation time 36978923942 ps
CPU time 111.85 seconds
Started Jul 09 05:05:40 PM PDT 24
Finished Jul 09 05:07:36 PM PDT 24
Peak memory 214888 kb
Host smart-df9aa48f-d761-4ed5-87b2-9b6b62656096
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859309475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2859309475
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2017310234
Short name T406
Test name
Test status
Simulation time 3174949242 ps
CPU time 30.76 seconds
Started Jul 09 05:05:36 PM PDT 24
Finished Jul 09 05:06:08 PM PDT 24
Peak memory 212560 kb
Host smart-8b6ef367-5815-4baa-8246-018aeadc2f7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017310234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2017310234
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.694682461
Short name T440
Test name
Test status
Simulation time 5779516535 ps
CPU time 29.25 seconds
Started Jul 09 05:05:38 PM PDT 24
Finished Jul 09 05:06:12 PM PDT 24
Peak memory 218344 kb
Host smart-4f26456e-5a04-4b63-a667-b77fd14ac9a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694682461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.694682461
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3891681134
Short name T427
Test name
Test status
Simulation time 3166964374 ps
CPU time 99.21 seconds
Started Jul 09 05:05:38 PM PDT 24
Finished Jul 09 05:07:20 PM PDT 24
Peak memory 212280 kb
Host smart-b9879ad7-49b9-49ee-ae1c-fa97584afbc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891681134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3891681134
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2466251338
Short name T452
Test name
Test status
Simulation time 10788555524 ps
CPU time 25.9 seconds
Started Jul 09 05:05:38 PM PDT 24
Finished Jul 09 05:06:08 PM PDT 24
Peak memory 217852 kb
Host smart-60fa4dcb-600a-483c-a92f-2145c1946c4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466251338 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2466251338
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3506126666
Short name T376
Test name
Test status
Simulation time 1968660653 ps
CPU time 20.56 seconds
Started Jul 09 05:05:42 PM PDT 24
Finished Jul 09 05:06:08 PM PDT 24
Peak memory 210484 kb
Host smart-93de42cd-04b9-49ce-8112-3cf09f618764
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506126666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3506126666
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1463081094
Short name T450
Test name
Test status
Simulation time 9965276540 ps
CPU time 98.65 seconds
Started Jul 09 05:05:40 PM PDT 24
Finished Jul 09 05:07:23 PM PDT 24
Peak memory 214072 kb
Host smart-5c486689-531f-4279-aaf0-4b42a75b6ec1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463081094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1463081094
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1624443301
Short name T76
Test name
Test status
Simulation time 17806275825 ps
CPU time 21.64 seconds
Started Jul 09 05:05:42 PM PDT 24
Finished Jul 09 05:06:09 PM PDT 24
Peak memory 212236 kb
Host smart-65e76ef3-62f5-43ea-a561-0775ef4f849d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624443301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1624443301
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.766069440
Short name T400
Test name
Test status
Simulation time 3953261700 ps
CPU time 33.02 seconds
Started Jul 09 05:05:34 PM PDT 24
Finished Jul 09 05:06:09 PM PDT 24
Peak memory 218324 kb
Host smart-1aa370c0-c3a0-4830-9cc6-6b00f38f17db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766069440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.766069440
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.421154136
Short name T441
Test name
Test status
Simulation time 9786263252 ps
CPU time 94.77 seconds
Started Jul 09 05:05:36 PM PDT 24
Finished Jul 09 05:07:12 PM PDT 24
Peak memory 213864 kb
Host smart-d67c4a30-74e1-4008-b1ed-2edade958d03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421154136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.421154136
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1891042195
Short name T420
Test name
Test status
Simulation time 16714578778 ps
CPU time 32.39 seconds
Started Jul 09 05:05:37 PM PDT 24
Finished Jul 09 05:06:12 PM PDT 24
Peak memory 218880 kb
Host smart-9e321c87-ce99-4236-bef8-3d5a5aaaa70f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891042195 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1891042195
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.160405925
Short name T101
Test name
Test status
Simulation time 47985175930 ps
CPU time 29.6 seconds
Started Jul 09 05:05:38 PM PDT 24
Finished Jul 09 05:06:11 PM PDT 24
Peak memory 211872 kb
Host smart-52b010e3-ea3b-48c4-a865-a64a59367540
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160405925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.160405925
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.407254698
Short name T95
Test name
Test status
Simulation time 9925132261 ps
CPU time 62.22 seconds
Started Jul 09 05:05:42 PM PDT 24
Finished Jul 09 05:06:49 PM PDT 24
Peak memory 213668 kb
Host smart-b2885a5b-98cb-40f5-9822-330a2b702e51
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407254698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.407254698
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1178196491
Short name T70
Test name
Test status
Simulation time 174390315 ps
CPU time 8.38 seconds
Started Jul 09 05:05:37 PM PDT 24
Finished Jul 09 05:05:48 PM PDT 24
Peak memory 211208 kb
Host smart-a7b17d5b-7036-4410-81df-774a0ca5b6bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178196491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1178196491
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2233627598
Short name T416
Test name
Test status
Simulation time 338911142 ps
CPU time 11.92 seconds
Started Jul 09 05:05:36 PM PDT 24
Finished Jul 09 05:05:51 PM PDT 24
Peak memory 217132 kb
Host smart-68da547f-92e3-447e-87e9-29e470f0807b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233627598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2233627598
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3632902229
Short name T54
Test name
Test status
Simulation time 2971257912 ps
CPU time 96.32 seconds
Started Jul 09 05:05:36 PM PDT 24
Finished Jul 09 05:07:15 PM PDT 24
Peak memory 213552 kb
Host smart-59ca854d-d6dd-4b4d-9ee1-8e6bf284f6b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632902229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3632902229
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4008629101
Short name T89
Test name
Test status
Simulation time 2472584249 ps
CPU time 23.2 seconds
Started Jul 09 05:05:21 PM PDT 24
Finished Jul 09 05:05:45 PM PDT 24
Peak memory 211464 kb
Host smart-71b52a8f-9180-4042-9016-ec1b1483aaee
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008629101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.4008629101
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.801931187
Short name T382
Test name
Test status
Simulation time 346805234 ps
CPU time 10.9 seconds
Started Jul 09 05:05:21 PM PDT 24
Finished Jul 09 05:05:34 PM PDT 24
Peak memory 210580 kb
Host smart-f5225094-6277-4bf4-b3c3-3974df9ee929
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801931187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.801931187
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4050768559
Short name T415
Test name
Test status
Simulation time 7684776463 ps
CPU time 32.93 seconds
Started Jul 09 05:05:22 PM PDT 24
Finished Jul 09 05:05:56 PM PDT 24
Peak memory 211568 kb
Host smart-608e7866-fea2-4c0d-8b3f-f57628304433
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050768559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.4050768559
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3358648396
Short name T425
Test name
Test status
Simulation time 4404850922 ps
CPU time 33.2 seconds
Started Jul 09 05:05:26 PM PDT 24
Finished Jul 09 05:06:02 PM PDT 24
Peak memory 217040 kb
Host smart-6f296ae6-6b3f-4b28-abf7-013760254846
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358648396 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3358648396
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2100312456
Short name T73
Test name
Test status
Simulation time 10242389408 ps
CPU time 23.42 seconds
Started Jul 09 05:05:22 PM PDT 24
Finished Jul 09 05:05:47 PM PDT 24
Peak memory 212232 kb
Host smart-f11f5d2e-69be-476f-95b7-dd727d95d699
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100312456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2100312456
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.51909324
Short name T456
Test name
Test status
Simulation time 2124641684 ps
CPU time 21.91 seconds
Started Jul 09 05:05:21 PM PDT 24
Finished Jul 09 05:05:44 PM PDT 24
Peak memory 210488 kb
Host smart-7f74c9a7-c98f-4a62-9ea7-34ec34d5c381
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51909324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_
mem_partial_access.51909324
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2830828371
Short name T364
Test name
Test status
Simulation time 3693032920 ps
CPU time 29.45 seconds
Started Jul 09 05:05:22 PM PDT 24
Finished Jul 09 05:05:54 PM PDT 24
Peak memory 210488 kb
Host smart-6e49e70a-6a99-4775-a125-0ecef1650b59
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830828371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2830828371
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2229531773
Short name T410
Test name
Test status
Simulation time 44729315124 ps
CPU time 99.77 seconds
Started Jul 09 05:05:23 PM PDT 24
Finished Jul 09 05:07:05 PM PDT 24
Peak memory 213748 kb
Host smart-a3ae8140-94ff-4949-b6a8-69fc0c680ed9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229531773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2229531773
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1700943487
Short name T97
Test name
Test status
Simulation time 918015901 ps
CPU time 8.55 seconds
Started Jul 09 05:05:22 PM PDT 24
Finished Jul 09 05:05:32 PM PDT 24
Peak memory 211256 kb
Host smart-def0dc1e-c34b-410a-ba90-38dcbd3a7b13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700943487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1700943487
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3636819844
Short name T369
Test name
Test status
Simulation time 19754355822 ps
CPU time 32.48 seconds
Started Jul 09 05:05:21 PM PDT 24
Finished Jul 09 05:05:55 PM PDT 24
Peak memory 217876 kb
Host smart-0547c1af-1567-48be-91ea-220b159d3ede
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636819844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3636819844
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3988449068
Short name T109
Test name
Test status
Simulation time 4058732367 ps
CPU time 173.77 seconds
Started Jul 09 05:05:21 PM PDT 24
Finished Jul 09 05:08:16 PM PDT 24
Peak memory 212944 kb
Host smart-f302c9e7-2edc-4b76-ad3d-e6faf3de3e26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988449068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3988449068
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.251593095
Short name T401
Test name
Test status
Simulation time 167486644 ps
CPU time 8.69 seconds
Started Jul 09 05:05:26 PM PDT 24
Finished Jul 09 05:05:39 PM PDT 24
Peak memory 210608 kb
Host smart-a665f1a4-d16b-4907-ac8e-91c8154e13a2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251593095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.251593095
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2784557247
Short name T383
Test name
Test status
Simulation time 338906784 ps
CPU time 8.38 seconds
Started Jul 09 05:05:27 PM PDT 24
Finished Jul 09 05:05:39 PM PDT 24
Peak memory 210552 kb
Host smart-62024f0f-0591-4d37-8386-300d063de8f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784557247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2784557247
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2857588729
Short name T417
Test name
Test status
Simulation time 10515167100 ps
CPU time 19.38 seconds
Started Jul 09 05:05:27 PM PDT 24
Finished Jul 09 05:05:50 PM PDT 24
Peak memory 210620 kb
Host smart-f86d841f-c2cb-4e5a-b531-befc037f4a7d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857588729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2857588729
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2212804999
Short name T428
Test name
Test status
Simulation time 673325260 ps
CPU time 13.56 seconds
Started Jul 09 05:05:28 PM PDT 24
Finished Jul 09 05:05:45 PM PDT 24
Peak memory 216988 kb
Host smart-4ef1f2aa-c115-4445-898a-f30ac3e37308
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212804999 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2212804999
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3825229100
Short name T418
Test name
Test status
Simulation time 12271371917 ps
CPU time 25.96 seconds
Started Jul 09 05:05:25 PM PDT 24
Finished Jul 09 05:05:54 PM PDT 24
Peak memory 210852 kb
Host smart-a7fd3ca0-9155-41ff-9816-a58441f472b1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825229100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3825229100
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2837528011
Short name T447
Test name
Test status
Simulation time 989977735 ps
CPU time 9.92 seconds
Started Jul 09 05:05:25 PM PDT 24
Finished Jul 09 05:05:38 PM PDT 24
Peak memory 210600 kb
Host smart-4ece399e-e253-4033-aea3-0cf7ba2eaab6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837528011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2837528011
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2891692038
Short name T102
Test name
Test status
Simulation time 9715298799 ps
CPU time 91.29 seconds
Started Jul 09 05:05:28 PM PDT 24
Finished Jul 09 05:07:03 PM PDT 24
Peak memory 213920 kb
Host smart-dae64ab6-db9c-46be-b036-0314d8b26ebf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891692038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2891692038
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1354548146
Short name T96
Test name
Test status
Simulation time 691776740 ps
CPU time 12.75 seconds
Started Jul 09 05:05:29 PM PDT 24
Finished Jul 09 05:05:45 PM PDT 24
Peak memory 211028 kb
Host smart-65626b2f-c375-4f48-9df5-eb2cf4eec5fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354548146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1354548146
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.796805374
Short name T451
Test name
Test status
Simulation time 2193554213 ps
CPU time 25.81 seconds
Started Jul 09 05:05:26 PM PDT 24
Finished Jul 09 05:05:55 PM PDT 24
Peak memory 217588 kb
Host smart-962ef4b0-05e5-49ec-bfa9-5fd15bafd40a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796805374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.796805374
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.382960358
Short name T110
Test name
Test status
Simulation time 6607701070 ps
CPU time 168.36 seconds
Started Jul 09 05:05:24 PM PDT 24
Finished Jul 09 05:08:14 PM PDT 24
Peak memory 214144 kb
Host smart-1faa3821-1598-4fa6-9180-2d9ce27a2714
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382960358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.382960358
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3525160894
Short name T449
Test name
Test status
Simulation time 8391210414 ps
CPU time 32.94 seconds
Started Jul 09 05:05:24 PM PDT 24
Finished Jul 09 05:05:59 PM PDT 24
Peak memory 212388 kb
Host smart-3c6099ef-ec7e-417f-b4f0-552526fa63ff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525160894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3525160894
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1770982156
Short name T381
Test name
Test status
Simulation time 27863523667 ps
CPU time 21.5 seconds
Started Jul 09 05:05:24 PM PDT 24
Finished Jul 09 05:05:47 PM PDT 24
Peak memory 211912 kb
Host smart-b0fbef01-d00c-49a8-b37f-b224fa7eac43
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770982156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1770982156
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1823801240
Short name T433
Test name
Test status
Simulation time 3859060574 ps
CPU time 34.9 seconds
Started Jul 09 05:05:26 PM PDT 24
Finished Jul 09 05:06:05 PM PDT 24
Peak memory 211268 kb
Host smart-f23bda80-4e37-421d-b88c-476153f648c3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823801240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1823801240
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2851137535
Short name T432
Test name
Test status
Simulation time 8978248485 ps
CPU time 21.11 seconds
Started Jul 09 05:05:28 PM PDT 24
Finished Jul 09 05:05:53 PM PDT 24
Peak memory 218212 kb
Host smart-1a826283-ccb1-4ea3-8928-c7b5a8e03532
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851137535 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2851137535
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.14962431
Short name T72
Test name
Test status
Simulation time 3757196080 ps
CPU time 14.08 seconds
Started Jul 09 05:05:24 PM PDT 24
Finished Jul 09 05:05:40 PM PDT 24
Peak memory 210632 kb
Host smart-e2780f6a-ced5-44d3-bdd6-abcf41487083
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14962431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.14962431
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3895522074
Short name T385
Test name
Test status
Simulation time 167314342 ps
CPU time 8.29 seconds
Started Jul 09 05:05:25 PM PDT 24
Finished Jul 09 05:05:37 PM PDT 24
Peak memory 210612 kb
Host smart-a8e34a81-24a4-4807-b7cb-d5236af83e67
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895522074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3895522074
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3750425479
Short name T421
Test name
Test status
Simulation time 23864582874 ps
CPU time 27.49 seconds
Started Jul 09 05:05:27 PM PDT 24
Finished Jul 09 05:05:58 PM PDT 24
Peak memory 210816 kb
Host smart-6f58aaa4-c03d-4384-bbc0-735d22586de5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750425479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3750425479
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.65856544
Short name T106
Test name
Test status
Simulation time 7734352822 ps
CPU time 100.45 seconds
Started Jul 09 05:05:25 PM PDT 24
Finished Jul 09 05:07:07 PM PDT 24
Peak memory 214204 kb
Host smart-cb6ef2e1-6e20-4ff0-97ef-01223172e930
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65856544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pass
thru_mem_tl_intg_err.65856544
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.393907791
Short name T58
Test name
Test status
Simulation time 1266768522 ps
CPU time 16.13 seconds
Started Jul 09 05:05:25 PM PDT 24
Finished Jul 09 05:05:43 PM PDT 24
Peak memory 211416 kb
Host smart-9b1c2b38-b151-4724-a620-3504bbbb64e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393907791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.393907791
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2710617259
Short name T455
Test name
Test status
Simulation time 688545529 ps
CPU time 11.55 seconds
Started Jul 09 05:05:26 PM PDT 24
Finished Jul 09 05:05:41 PM PDT 24
Peak memory 216956 kb
Host smart-621c2c75-0033-4f21-8541-0afc5beb71d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710617259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2710617259
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2423597922
Short name T114
Test name
Test status
Simulation time 1205025290 ps
CPU time 160.69 seconds
Started Jul 09 05:05:26 PM PDT 24
Finished Jul 09 05:08:10 PM PDT 24
Peak memory 215020 kb
Host smart-3e985f83-7233-4683-91e3-a9c537957466
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423597922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2423597922
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4003051963
Short name T398
Test name
Test status
Simulation time 1270706919 ps
CPU time 9.77 seconds
Started Jul 09 05:05:25 PM PDT 24
Finished Jul 09 05:05:38 PM PDT 24
Peak memory 217248 kb
Host smart-001fbf3f-bf5f-4e57-8094-ba97b921659b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003051963 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.4003051963
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1359417439
Short name T373
Test name
Test status
Simulation time 14247086091 ps
CPU time 28.44 seconds
Started Jul 09 05:05:25 PM PDT 24
Finished Jul 09 05:05:56 PM PDT 24
Peak memory 212320 kb
Host smart-0167da6f-e1b0-4811-a06d-5da22fced1f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359417439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1359417439
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1860590057
Short name T91
Test name
Test status
Simulation time 14749710621 ps
CPU time 120.84 seconds
Started Jul 09 05:05:29 PM PDT 24
Finished Jul 09 05:07:34 PM PDT 24
Peak memory 213988 kb
Host smart-a2b99e2a-e8a5-4a5f-bd7d-5dfbee7bf03f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860590057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1860590057
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1459384892
Short name T403
Test name
Test status
Simulation time 833813946 ps
CPU time 17.43 seconds
Started Jul 09 05:05:29 PM PDT 24
Finished Jul 09 05:05:50 PM PDT 24
Peak memory 212204 kb
Host smart-0ae5c287-31a2-428c-a85d-433e063abf69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459384892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1459384892
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1628436775
Short name T411
Test name
Test status
Simulation time 662122796 ps
CPU time 12.64 seconds
Started Jul 09 05:05:25 PM PDT 24
Finished Jul 09 05:05:40 PM PDT 24
Peak memory 218844 kb
Host smart-4d430803-dd75-432e-9311-ce31af1bc6fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628436775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1628436775
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2112425674
Short name T116
Test name
Test status
Simulation time 464466270 ps
CPU time 80.93 seconds
Started Jul 09 05:05:26 PM PDT 24
Finished Jul 09 05:06:51 PM PDT 24
Peak memory 213372 kb
Host smart-0f6b6af2-900e-4bef-b036-b4806a3a9e1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112425674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2112425674
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1173369997
Short name T402
Test name
Test status
Simulation time 7073881352 ps
CPU time 18.54 seconds
Started Jul 09 05:05:26 PM PDT 24
Finished Jul 09 05:05:48 PM PDT 24
Peak memory 218972 kb
Host smart-6ec89f26-32bd-43cb-9954-ad3fddb1dfd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173369997 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1173369997
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1457278886
Short name T378
Test name
Test status
Simulation time 248802053 ps
CPU time 8.33 seconds
Started Jul 09 05:05:24 PM PDT 24
Finished Jul 09 05:05:34 PM PDT 24
Peak memory 210548 kb
Host smart-dcdf962c-4300-4680-9e58-6268acf05f7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457278886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1457278886
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3303897005
Short name T77
Test name
Test status
Simulation time 2078308047 ps
CPU time 55.88 seconds
Started Jul 09 05:05:29 PM PDT 24
Finished Jul 09 05:06:28 PM PDT 24
Peak memory 213848 kb
Host smart-bf16b16a-544c-4c98-bf3d-753582f2015a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303897005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3303897005
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1758031411
Short name T99
Test name
Test status
Simulation time 834554182 ps
CPU time 15.03 seconds
Started Jul 09 05:05:25 PM PDT 24
Finished Jul 09 05:05:42 PM PDT 24
Peak memory 212380 kb
Host smart-0cb94ef4-7591-4866-b4fd-759ac23e11e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758031411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1758031411
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3016029273
Short name T368
Test name
Test status
Simulation time 2045669745 ps
CPU time 23.83 seconds
Started Jul 09 05:05:26 PM PDT 24
Finished Jul 09 05:05:53 PM PDT 24
Peak memory 218068 kb
Host smart-85e7a6a4-20f7-4ff2-be5e-a25ccad0394c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016029273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3016029273
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3579613141
Short name T444
Test name
Test status
Simulation time 8826756448 ps
CPU time 179.43 seconds
Started Jul 09 05:05:25 PM PDT 24
Finished Jul 09 05:08:28 PM PDT 24
Peak memory 213972 kb
Host smart-316755b3-b5e7-4bfc-984e-e0a8f12d37dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579613141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3579613141
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.6038991
Short name T380
Test name
Test status
Simulation time 2340813680 ps
CPU time 16.21 seconds
Started Jul 09 05:05:29 PM PDT 24
Finished Jul 09 05:05:49 PM PDT 24
Peak memory 217136 kb
Host smart-97047f4f-a79e-40cc-a33d-e7b78612ec97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6038991 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.6038991
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4205804881
Short name T438
Test name
Test status
Simulation time 11776875906 ps
CPU time 25.84 seconds
Started Jul 09 05:05:28 PM PDT 24
Finished Jul 09 05:05:57 PM PDT 24
Peak memory 211632 kb
Host smart-d85da1de-87ac-407d-b6e3-f514da574741
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205804881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.4205804881
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3085651181
Short name T407
Test name
Test status
Simulation time 17665845561 ps
CPU time 105.22 seconds
Started Jul 09 05:05:28 PM PDT 24
Finished Jul 09 05:07:17 PM PDT 24
Peak memory 215128 kb
Host smart-d6cc4004-4948-4a8c-baad-4c5039c22368
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085651181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3085651181
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2208120059
Short name T404
Test name
Test status
Simulation time 2963204162 ps
CPU time 12.64 seconds
Started Jul 09 05:05:28 PM PDT 24
Finished Jul 09 05:05:44 PM PDT 24
Peak memory 210628 kb
Host smart-42fd9c0b-99d5-4226-84f2-cfd7c9aa09eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208120059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2208120059
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1787840871
Short name T391
Test name
Test status
Simulation time 1083942661 ps
CPU time 18.71 seconds
Started Jul 09 05:05:28 PM PDT 24
Finished Jul 09 05:05:50 PM PDT 24
Peak memory 218252 kb
Host smart-04f9521b-e66e-4880-9452-06ac7ebfe3b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787840871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1787840871
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.348694117
Short name T430
Test name
Test status
Simulation time 846455874 ps
CPU time 14.36 seconds
Started Jul 09 05:05:33 PM PDT 24
Finished Jul 09 05:05:50 PM PDT 24
Peak memory 215672 kb
Host smart-35c10841-5da3-4a0e-875f-eb08033a958e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348694117 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.348694117
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3678042897
Short name T424
Test name
Test status
Simulation time 5228323283 ps
CPU time 12.34 seconds
Started Jul 09 05:05:31 PM PDT 24
Finished Jul 09 05:05:46 PM PDT 24
Peak memory 211152 kb
Host smart-112c4760-10e1-47e7-b5f9-7003f50d1430
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678042897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3678042897
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1084786223
Short name T414
Test name
Test status
Simulation time 17860130966 ps
CPU time 85.66 seconds
Started Jul 09 05:05:33 PM PDT 24
Finished Jul 09 05:07:02 PM PDT 24
Peak memory 215012 kb
Host smart-029a2c1e-7cb3-4fce-ad0a-6e7210539f1d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084786223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1084786223
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3450875033
Short name T454
Test name
Test status
Simulation time 170968449 ps
CPU time 8.1 seconds
Started Jul 09 05:05:35 PM PDT 24
Finished Jul 09 05:05:45 PM PDT 24
Peak memory 211048 kb
Host smart-c4ab78b7-6af6-4716-9da9-3effd6c03278
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450875033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3450875033
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3766497484
Short name T55
Test name
Test status
Simulation time 2842903386 ps
CPU time 22.26 seconds
Started Jul 09 05:05:27 PM PDT 24
Finished Jul 09 05:05:53 PM PDT 24
Peak memory 218456 kb
Host smart-15b0764e-3e4e-4bdd-b856-21faab49d256
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766497484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3766497484
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2233436935
Short name T108
Test name
Test status
Simulation time 4618549602 ps
CPU time 173.54 seconds
Started Jul 09 05:05:31 PM PDT 24
Finished Jul 09 05:08:28 PM PDT 24
Peak memory 214152 kb
Host smart-b233a5bc-9391-492d-a892-0fe69a45f963
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233436935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2233436935
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.902160774
Short name T392
Test name
Test status
Simulation time 43800683859 ps
CPU time 24.26 seconds
Started Jul 09 05:05:32 PM PDT 24
Finished Jul 09 05:05:59 PM PDT 24
Peak memory 218264 kb
Host smart-378666b3-e5be-46d0-8f33-00e4f81bed0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902160774 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.902160774
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3536612235
Short name T422
Test name
Test status
Simulation time 689517256 ps
CPU time 8.11 seconds
Started Jul 09 05:05:32 PM PDT 24
Finished Jul 09 05:05:43 PM PDT 24
Peak memory 210852 kb
Host smart-311591c6-04cc-4696-aaea-ecf114c17b8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536612235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3536612235
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3347958
Short name T82
Test name
Test status
Simulation time 49246868568 ps
CPU time 116.51 seconds
Started Jul 09 05:05:34 PM PDT 24
Finished Jul 09 05:07:33 PM PDT 24
Peak memory 211916 kb
Host smart-5c817b44-a96a-46b2-8947-04b502d06fc5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_passt
hru_mem_tl_intg_err.3347958
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1093356899
Short name T386
Test name
Test status
Simulation time 6161003285 ps
CPU time 18.17 seconds
Started Jul 09 05:05:34 PM PDT 24
Finished Jul 09 05:05:55 PM PDT 24
Peak memory 211524 kb
Host smart-8b3877e8-3884-41d9-9dc1-5b2c7492a3ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093356899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1093356899
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.4222749113
Short name T437
Test name
Test status
Simulation time 7798406781 ps
CPU time 34.44 seconds
Started Jul 09 05:05:35 PM PDT 24
Finished Jul 09 05:06:11 PM PDT 24
Peak memory 217532 kb
Host smart-a31a7dcf-d602-44ed-ac58-206a918d7b10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222749113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.4222749113
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.287078757
Short name T443
Test name
Test status
Simulation time 7988442386 ps
CPU time 160.36 seconds
Started Jul 09 05:05:32 PM PDT 24
Finished Jul 09 05:08:15 PM PDT 24
Peak memory 214276 kb
Host smart-915122ef-5a08-495a-9e09-8728e770d1ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287078757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.287078757
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3711734112
Short name T293
Test name
Test status
Simulation time 6874443179 ps
CPU time 26.72 seconds
Started Jul 09 05:05:41 PM PDT 24
Finished Jul 09 05:06:14 PM PDT 24
Peak memory 213132 kb
Host smart-61de50a1-2851-4f18-a130-003e3ae2bc8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711734112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3711734112
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.888003543
Short name T135
Test name
Test status
Simulation time 48818488558 ps
CPU time 553.45 seconds
Started Jul 09 05:05:38 PM PDT 24
Finished Jul 09 05:14:55 PM PDT 24
Peak memory 224560 kb
Host smart-dcfbbae5-30b6-4d96-b6e9-99b17f90db78
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888003543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.888003543
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1835367591
Short name T322
Test name
Test status
Simulation time 27997628208 ps
CPU time 30.5 seconds
Started Jul 09 05:05:40 PM PDT 24
Finished Jul 09 05:06:15 PM PDT 24
Peak memory 211928 kb
Host smart-a5ac2b9a-5c9f-4c83-b0a3-b6e8a91e116f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1835367591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1835367591
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2962587967
Short name T30
Test name
Test status
Simulation time 3780115027 ps
CPU time 231.06 seconds
Started Jul 09 05:05:42 PM PDT 24
Finished Jul 09 05:09:38 PM PDT 24
Peak memory 236852 kb
Host smart-700f93b5-641d-4d95-93e2-0c90cb3ce401
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962587967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2962587967
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2118364496
Short name T126
Test name
Test status
Simulation time 347938026 ps
CPU time 20.21 seconds
Started Jul 09 05:05:36 PM PDT 24
Finished Jul 09 05:05:58 PM PDT 24
Peak memory 215828 kb
Host smart-3bd7ba1e-22d3-437c-98ab-176142d3f2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118364496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2118364496
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3062652260
Short name T280
Test name
Test status
Simulation time 12786304829 ps
CPU time 151.85 seconds
Started Jul 09 05:05:34 PM PDT 24
Finished Jul 09 05:08:08 PM PDT 24
Peak memory 220228 kb
Host smart-e4cb525c-262a-487a-9868-8c9e3daa901b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062652260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3062652260
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1803493385
Short name T191
Test name
Test status
Simulation time 1802634042 ps
CPU time 19.43 seconds
Started Jul 09 05:05:39 PM PDT 24
Finished Jul 09 05:06:02 PM PDT 24
Peak memory 217140 kb
Host smart-f980fd7a-3ff0-4dc0-8015-8b64ab5addca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803493385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1803493385
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2848061401
Short name T38
Test name
Test status
Simulation time 80117405632 ps
CPU time 313.67 seconds
Started Jul 09 05:05:39 PM PDT 24
Finished Jul 09 05:10:56 PM PDT 24
Peak memory 227744 kb
Host smart-2fdda665-db2d-4c1c-8196-657e8c5f1206
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848061401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2848061401
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3193339976
Short name T294
Test name
Test status
Simulation time 4095978453 ps
CPU time 33.94 seconds
Started Jul 09 05:05:38 PM PDT 24
Finished Jul 09 05:06:16 PM PDT 24
Peak memory 219256 kb
Host smart-3d07b910-3e9d-4190-ac72-78c908321eaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3193339976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3193339976
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3969575485
Short name T81
Test name
Test status
Simulation time 13668220914 ps
CPU time 60.04 seconds
Started Jul 09 05:05:37 PM PDT 24
Finished Jul 09 05:06:41 PM PDT 24
Peak memory 215912 kb
Host smart-ea3e3f1f-4ac7-4cf4-af1f-37b1c9143592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969575485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3969575485
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.318924491
Short name T177
Test name
Test status
Simulation time 17293809674 ps
CPU time 156.48 seconds
Started Jul 09 05:05:37 PM PDT 24
Finished Jul 09 05:08:18 PM PDT 24
Peak memory 221060 kb
Host smart-defd4b26-be27-403e-9d03-4bd0f9e8b77c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318924491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.318924491
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3119654853
Short name T350
Test name
Test status
Simulation time 2397484648 ps
CPU time 22.97 seconds
Started Jul 09 05:05:49 PM PDT 24
Finished Jul 09 05:06:18 PM PDT 24
Peak memory 217108 kb
Host smart-63545e22-77eb-448e-9697-e14290a476d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119654853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3119654853
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3618737375
Short name T162
Test name
Test status
Simulation time 25454130477 ps
CPU time 256.89 seconds
Started Jul 09 05:05:49 PM PDT 24
Finished Jul 09 05:10:12 PM PDT 24
Peak memory 233800 kb
Host smart-72edd948-b53a-4ea5-88ee-1a207bdabba4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618737375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3618737375
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.5998677
Short name T165
Test name
Test status
Simulation time 5005474064 ps
CPU time 46.4 seconds
Started Jul 09 05:05:50 PM PDT 24
Finished Jul 09 05:06:42 PM PDT 24
Peak memory 219280 kb
Host smart-2e7777ba-bd96-4a77-be6e-5324b0a075f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5998677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.5998677
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2697828160
Short name T233
Test name
Test status
Simulation time 3112349398 ps
CPU time 28.05 seconds
Started Jul 09 05:05:49 PM PDT 24
Finished Jul 09 05:06:23 PM PDT 24
Peak memory 219256 kb
Host smart-d54e54e3-551e-4bdc-9b34-04e5deca6b06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2697828160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2697828160
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3919007021
Short name T186
Test name
Test status
Simulation time 2480375447 ps
CPU time 27.29 seconds
Started Jul 09 05:05:55 PM PDT 24
Finished Jul 09 05:06:30 PM PDT 24
Peak memory 216668 kb
Host smart-6d506605-f666-472b-8b2e-7fc0b368d68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919007021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3919007021
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.750749835
Short name T131
Test name
Test status
Simulation time 29247048495 ps
CPU time 67.23 seconds
Started Jul 09 05:05:48 PM PDT 24
Finished Jul 09 05:07:01 PM PDT 24
Peak memory 218524 kb
Host smart-d3d97389-ff8c-4579-a3b7-2c573f42cc5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750749835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.750749835
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1375727278
Short name T337
Test name
Test status
Simulation time 16467562560 ps
CPU time 32.44 seconds
Started Jul 09 05:05:50 PM PDT 24
Finished Jul 09 05:06:29 PM PDT 24
Peak memory 217456 kb
Host smart-6bd29d0a-8047-4ab3-a760-196b0a1d3719
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375727278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1375727278
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2628002155
Short name T41
Test name
Test status
Simulation time 8949766274 ps
CPU time 250.63 seconds
Started Jul 09 05:05:50 PM PDT 24
Finished Jul 09 05:10:07 PM PDT 24
Peak memory 234744 kb
Host smart-7b5c1a4e-392a-492d-a051-84e338818c2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628002155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2628002155
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2848472976
Short name T166
Test name
Test status
Simulation time 8344245506 ps
CPU time 67.73 seconds
Started Jul 09 05:05:46 PM PDT 24
Finished Jul 09 05:06:59 PM PDT 24
Peak memory 219300 kb
Host smart-90f91ce2-187a-4b95-8c23-cbf87830babd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848472976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2848472976
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2278086131
Short name T2
Test name
Test status
Simulation time 2801976685 ps
CPU time 40.25 seconds
Started Jul 09 05:05:51 PM PDT 24
Finished Jul 09 05:06:39 PM PDT 24
Peak memory 215804 kb
Host smart-ff6e7d1e-13d3-42e2-b170-d57f1f558d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278086131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2278086131
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.891913474
Short name T105
Test name
Test status
Simulation time 15204876078 ps
CPU time 32.52 seconds
Started Jul 09 05:05:49 PM PDT 24
Finished Jul 09 05:06:27 PM PDT 24
Peak memory 214728 kb
Host smart-45311eb7-5a06-47e3-bad4-baac5b187e80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891913474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.891913474
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1602087919
Short name T185
Test name
Test status
Simulation time 688300904 ps
CPU time 8.28 seconds
Started Jul 09 05:05:56 PM PDT 24
Finished Jul 09 05:06:12 PM PDT 24
Peak memory 217056 kb
Host smart-e64f6366-7966-4501-bdcf-dfc7a8de6ed6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602087919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1602087919
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1808051476
Short name T288
Test name
Test status
Simulation time 94879105799 ps
CPU time 370.19 seconds
Started Jul 09 05:05:53 PM PDT 24
Finished Jul 09 05:12:11 PM PDT 24
Peak memory 233664 kb
Host smart-8757d5bd-f31c-4c7f-872d-bd6a93d8a24f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808051476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1808051476
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2910151627
Short name T277
Test name
Test status
Simulation time 8739639483 ps
CPU time 68.25 seconds
Started Jul 09 05:05:50 PM PDT 24
Finished Jul 09 05:07:05 PM PDT 24
Peak memory 219260 kb
Host smart-40aeee99-51c8-4704-9123-86225979dc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910151627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2910151627
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3874662103
Short name T224
Test name
Test status
Simulation time 362873951 ps
CPU time 10.36 seconds
Started Jul 09 05:05:48 PM PDT 24
Finished Jul 09 05:06:04 PM PDT 24
Peak memory 219248 kb
Host smart-e5a1c8f8-7b3c-415c-91ec-0f88906511ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3874662103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3874662103
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2094342222
Short name T338
Test name
Test status
Simulation time 354094638 ps
CPU time 20.04 seconds
Started Jul 09 05:05:51 PM PDT 24
Finished Jul 09 05:06:17 PM PDT 24
Peak memory 216664 kb
Host smart-339032be-8254-42f0-a4d9-b5ea61a91acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094342222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2094342222
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.4053706395
Short name T349
Test name
Test status
Simulation time 2039904459 ps
CPU time 24.2 seconds
Started Jul 09 05:05:49 PM PDT 24
Finished Jul 09 05:06:19 PM PDT 24
Peak memory 214688 kb
Host smart-93608691-ec30-4fb0-a26e-5817432bf63a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053706395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.4053706395
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2071209734
Short name T172
Test name
Test status
Simulation time 1338291748 ps
CPU time 17.08 seconds
Started Jul 09 05:05:56 PM PDT 24
Finished Jul 09 05:06:20 PM PDT 24
Peak memory 216900 kb
Host smart-253a978d-3b5d-4c24-9273-e1733858bef2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071209734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2071209734
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1462719149
Short name T232
Test name
Test status
Simulation time 193746440950 ps
CPU time 205.12 seconds
Started Jul 09 05:05:51 PM PDT 24
Finished Jul 09 05:09:23 PM PDT 24
Peak memory 219456 kb
Host smart-147508c9-7d87-45c0-816c-c40fade96914
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462719149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1462719149
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.4168266365
Short name T176
Test name
Test status
Simulation time 4095382611 ps
CPU time 25.57 seconds
Started Jul 09 05:05:54 PM PDT 24
Finished Jul 09 05:06:27 PM PDT 24
Peak memory 219244 kb
Host smart-1f8e80d4-3c4f-4b64-8ff9-9f8773f5d290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168266365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.4168266365
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2837757574
Short name T187
Test name
Test status
Simulation time 14028132779 ps
CPU time 31.01 seconds
Started Jul 09 05:05:51 PM PDT 24
Finished Jul 09 05:06:30 PM PDT 24
Peak memory 211864 kb
Host smart-21ed3684-ffaf-4a22-8781-b277b4715aa2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2837757574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2837757574
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1847585482
Short name T132
Test name
Test status
Simulation time 34594605198 ps
CPU time 60.61 seconds
Started Jul 09 05:05:54 PM PDT 24
Finished Jul 09 05:07:02 PM PDT 24
Peak memory 216388 kb
Host smart-bb95d2da-dd44-4621-95f1-ba725aa9d5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847585482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1847585482
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2570138697
Short name T209
Test name
Test status
Simulation time 14696165049 ps
CPU time 25.48 seconds
Started Jul 09 05:05:56 PM PDT 24
Finished Jul 09 05:06:29 PM PDT 24
Peak memory 217560 kb
Host smart-4848d88f-fa65-4dd0-aa1e-bc4afbf6fd38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570138697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2570138697
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1485908964
Short name T119
Test name
Test status
Simulation time 142961104149 ps
CPU time 398.26 seconds
Started Jul 09 05:05:53 PM PDT 24
Finished Jul 09 05:12:39 PM PDT 24
Peak memory 234620 kb
Host smart-69c3a34e-dd17-4f3b-bcb6-1416a1e6e4b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485908964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1485908964
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.777932111
Short name T203
Test name
Test status
Simulation time 6152869904 ps
CPU time 56.98 seconds
Started Jul 09 05:05:51 PM PDT 24
Finished Jul 09 05:06:55 PM PDT 24
Peak memory 219336 kb
Host smart-81ec3edb-64db-4d81-ac26-b2e11cf90961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777932111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.777932111
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2229090674
Short name T268
Test name
Test status
Simulation time 358168593 ps
CPU time 10.33 seconds
Started Jul 09 05:05:51 PM PDT 24
Finished Jul 09 05:06:09 PM PDT 24
Peak memory 218588 kb
Host smart-10c4afd8-41ae-43c5-95f6-a9b823689ed1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2229090674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2229090674
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3840802740
Short name T263
Test name
Test status
Simulation time 23244087298 ps
CPU time 53.99 seconds
Started Jul 09 05:05:52 PM PDT 24
Finished Jul 09 05:06:53 PM PDT 24
Peak memory 216508 kb
Host smart-ff969e65-32d3-4ebc-ab55-3b24e6f16e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840802740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3840802740
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.380052062
Short name T304
Test name
Test status
Simulation time 15767111178 ps
CPU time 44.03 seconds
Started Jul 09 05:05:51 PM PDT 24
Finished Jul 09 05:06:42 PM PDT 24
Peak memory 218328 kb
Host smart-3101a714-1374-4c15-b9af-57b44f86197d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380052062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.380052062
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.419523691
Short name T164
Test name
Test status
Simulation time 17158644729 ps
CPU time 33.3 seconds
Started Jul 09 05:05:56 PM PDT 24
Finished Jul 09 05:06:37 PM PDT 24
Peak memory 217396 kb
Host smart-fc03dc2a-9073-4022-8309-e151bcab99c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419523691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.419523691
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2361148995
Short name T36
Test name
Test status
Simulation time 56072756401 ps
CPU time 523.44 seconds
Started Jul 09 05:05:58 PM PDT 24
Finished Jul 09 05:14:48 PM PDT 24
Peak memory 238460 kb
Host smart-6ae82eb9-0b66-41e1-bda0-c9f53b07e973
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361148995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2361148995
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.225628370
Short name T212
Test name
Test status
Simulation time 16404510488 ps
CPU time 46.32 seconds
Started Jul 09 05:05:51 PM PDT 24
Finished Jul 09 05:06:45 PM PDT 24
Peak memory 219128 kb
Host smart-4da0b960-f64a-4c11-b26d-9160e5f34f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225628370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.225628370
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.484142586
Short name T152
Test name
Test status
Simulation time 10834653048 ps
CPU time 22.7 seconds
Started Jul 09 05:05:53 PM PDT 24
Finished Jul 09 05:06:23 PM PDT 24
Peak memory 211980 kb
Host smart-b6f93805-6f68-4c5f-812f-c9bc81ee262e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=484142586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.484142586
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3788944918
Short name T314
Test name
Test status
Simulation time 4669327527 ps
CPU time 46.73 seconds
Started Jul 09 05:05:50 PM PDT 24
Finished Jul 09 05:06:44 PM PDT 24
Peak memory 216460 kb
Host smart-bb2bb3a7-c959-4821-ae5a-c55a3299fc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788944918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3788944918
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3815611470
Short name T245
Test name
Test status
Simulation time 40769430250 ps
CPU time 104.09 seconds
Started Jul 09 05:05:56 PM PDT 24
Finished Jul 09 05:07:47 PM PDT 24
Peak memory 220204 kb
Host smart-806be8a7-4b6f-4367-9a9a-3ebcb18e2ff8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815611470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3815611470
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3908677247
Short name T195
Test name
Test status
Simulation time 7177687834 ps
CPU time 30.25 seconds
Started Jul 09 05:05:56 PM PDT 24
Finished Jul 09 05:06:33 PM PDT 24
Peak memory 217512 kb
Host smart-9ae135f1-1825-40ee-95e5-170bc76f1691
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908677247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3908677247
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3444822246
Short name T262
Test name
Test status
Simulation time 175801240600 ps
CPU time 446.56 seconds
Started Jul 09 05:05:56 PM PDT 24
Finished Jul 09 05:13:30 PM PDT 24
Peak memory 219400 kb
Host smart-650e7de2-3308-4040-89c4-0c3e85c9cbd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444822246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3444822246
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.579791184
Short name T46
Test name
Test status
Simulation time 751933516 ps
CPU time 19.17 seconds
Started Jul 09 05:05:53 PM PDT 24
Finished Jul 09 05:06:20 PM PDT 24
Peak memory 219188 kb
Host smart-ccaf7aa5-6085-4721-848e-947c4c74eae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579791184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.579791184
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.188130914
Short name T219
Test name
Test status
Simulation time 48220053430 ps
CPU time 31.22 seconds
Started Jul 09 05:05:53 PM PDT 24
Finished Jul 09 05:06:32 PM PDT 24
Peak memory 211948 kb
Host smart-497e2001-dc3b-4428-ab10-07ad9b50c1c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=188130914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.188130914
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1635610304
Short name T161
Test name
Test status
Simulation time 35135657721 ps
CPU time 77.54 seconds
Started Jul 09 05:05:52 PM PDT 24
Finished Jul 09 05:07:17 PM PDT 24
Peak memory 216576 kb
Host smart-5ee827a6-ceb4-4f18-af5b-3aca33d0def4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635610304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1635610304
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2154011184
Short name T254
Test name
Test status
Simulation time 1050254505 ps
CPU time 36.55 seconds
Started Jul 09 05:05:50 PM PDT 24
Finished Jul 09 05:06:33 PM PDT 24
Peak memory 219200 kb
Host smart-05004e00-da96-47c5-8603-72489bac45b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154011184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2154011184
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2901428022
Short name T295
Test name
Test status
Simulation time 6145087324 ps
CPU time 19.29 seconds
Started Jul 09 05:05:57 PM PDT 24
Finished Jul 09 05:06:24 PM PDT 24
Peak memory 217548 kb
Host smart-6188f46e-9a6c-406d-a658-e58ead631d44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901428022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2901428022
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.4194149495
Short name T146
Test name
Test status
Simulation time 103894669264 ps
CPU time 579.14 seconds
Started Jul 09 05:05:54 PM PDT 24
Finished Jul 09 05:15:41 PM PDT 24
Peak memory 219540 kb
Host smart-f6141000-1b28-4871-8d50-a6e314b262f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194149495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.4194149495
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3377024215
Short name T227
Test name
Test status
Simulation time 34680654910 ps
CPU time 37.26 seconds
Started Jul 09 05:05:57 PM PDT 24
Finished Jul 09 05:06:41 PM PDT 24
Peak memory 218832 kb
Host smart-a799c5c3-4879-4652-9a32-ccb1eca05b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377024215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3377024215
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.685765875
Short name T167
Test name
Test status
Simulation time 3983464865 ps
CPU time 31.3 seconds
Started Jul 09 05:05:56 PM PDT 24
Finished Jul 09 05:06:34 PM PDT 24
Peak memory 219196 kb
Host smart-888c867a-0096-4b25-ae32-4255dc147e48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=685765875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.685765875
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.388115299
Short name T134
Test name
Test status
Simulation time 9934532008 ps
CPU time 63.31 seconds
Started Jul 09 05:05:55 PM PDT 24
Finished Jul 09 05:07:05 PM PDT 24
Peak memory 216692 kb
Host smart-a59f8f6f-dc08-4242-b587-7c133c9264dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388115299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.388115299
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1495446267
Short name T216
Test name
Test status
Simulation time 185563371 ps
CPU time 17.55 seconds
Started Jul 09 05:05:55 PM PDT 24
Finished Jul 09 05:06:19 PM PDT 24
Peak memory 218672 kb
Host smart-ae301523-e6e6-4ecb-98ac-c44a82285722
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495446267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1495446267
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2044861836
Short name T62
Test name
Test status
Simulation time 2723141080 ps
CPU time 25.27 seconds
Started Jul 09 05:05:57 PM PDT 24
Finished Jul 09 05:06:29 PM PDT 24
Peak memory 217168 kb
Host smart-100889b6-7475-4555-9ca9-bd4c233b5c8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044861836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2044861836
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1823201631
Short name T141
Test name
Test status
Simulation time 195914903961 ps
CPU time 480.84 seconds
Started Jul 09 05:05:54 PM PDT 24
Finished Jul 09 05:14:03 PM PDT 24
Peak memory 234256 kb
Host smart-a0e9e706-e6fe-4534-9b4a-0e711c4b3bde
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823201631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1823201631
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1445095955
Short name T307
Test name
Test status
Simulation time 339044650 ps
CPU time 19.62 seconds
Started Jul 09 05:05:55 PM PDT 24
Finished Jul 09 05:06:21 PM PDT 24
Peak memory 219540 kb
Host smart-3479f288-f57d-453f-95f3-b57032d6ac68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445095955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1445095955
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2974954121
Short name T169
Test name
Test status
Simulation time 46852777448 ps
CPU time 29.6 seconds
Started Jul 09 05:05:57 PM PDT 24
Finished Jul 09 05:06:34 PM PDT 24
Peak memory 219276 kb
Host smart-37bb0e91-3de6-4426-968c-8c2ea95860a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2974954121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2974954121
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1680265976
Short name T357
Test name
Test status
Simulation time 343335235 ps
CPU time 20.9 seconds
Started Jul 09 05:05:54 PM PDT 24
Finished Jul 09 05:06:23 PM PDT 24
Peak memory 216416 kb
Host smart-ba338b38-200e-482e-9736-097da7004e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680265976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1680265976
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3625540533
Short name T12
Test name
Test status
Simulation time 717071716 ps
CPU time 42.56 seconds
Started Jul 09 05:05:58 PM PDT 24
Finished Jul 09 05:06:48 PM PDT 24
Peak memory 219312 kb
Host smart-cd2a4e46-75c4-4d58-bab6-280f8f4def7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625540533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3625540533
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3709885955
Short name T330
Test name
Test status
Simulation time 11898476710 ps
CPU time 33.81 seconds
Started Jul 09 05:05:56 PM PDT 24
Finished Jul 09 05:06:37 PM PDT 24
Peak memory 217504 kb
Host smart-4bb35798-9cff-43b3-a676-9806dd40086d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709885955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3709885955
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1454260727
Short name T150
Test name
Test status
Simulation time 50746204806 ps
CPU time 495.42 seconds
Started Jul 09 05:05:56 PM PDT 24
Finished Jul 09 05:14:19 PM PDT 24
Peak memory 237928 kb
Host smart-6fddfb83-0798-418b-8d98-0eb98d587922
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454260727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1454260727
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.99719078
Short name T331
Test name
Test status
Simulation time 7385662229 ps
CPU time 62.5 seconds
Started Jul 09 05:05:56 PM PDT 24
Finished Jul 09 05:07:06 PM PDT 24
Peak memory 219348 kb
Host smart-eb363e91-444d-4d90-ab34-99dc59e4590d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99719078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.99719078
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2065313300
Short name T316
Test name
Test status
Simulation time 12330046970 ps
CPU time 26.98 seconds
Started Jul 09 05:05:55 PM PDT 24
Finished Jul 09 05:06:29 PM PDT 24
Peak memory 219256 kb
Host smart-b2e67c6c-84d2-4764-9073-2fe38b64b71a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2065313300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2065313300
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.2715939506
Short name T303
Test name
Test status
Simulation time 6951957630 ps
CPU time 66.74 seconds
Started Jul 09 05:05:54 PM PDT 24
Finished Jul 09 05:07:09 PM PDT 24
Peak memory 217492 kb
Host smart-1cb2bfe7-af23-4363-9409-9ba7e4b0e626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715939506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.2715939506
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2142067302
Short name T345
Test name
Test status
Simulation time 3719566508 ps
CPU time 25.08 seconds
Started Jul 09 05:05:56 PM PDT 24
Finished Jul 09 05:06:28 PM PDT 24
Peak memory 219304 kb
Host smart-2f8b55ec-817d-46a7-88d1-a68c7ef1f914
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142067302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2142067302
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.798314226
Short name T17
Test name
Test status
Simulation time 177146700235 ps
CPU time 1143.73 seconds
Started Jul 09 05:05:55 PM PDT 24
Finished Jul 09 05:25:06 PM PDT 24
Peak memory 235708 kb
Host smart-e3b149fa-9e25-43fe-a60c-f341b4a26a98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798314226 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.798314226
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1026252224
Short name T282
Test name
Test status
Simulation time 1031401263 ps
CPU time 8.51 seconds
Started Jul 09 05:05:38 PM PDT 24
Finished Jul 09 05:05:51 PM PDT 24
Peak memory 216932 kb
Host smart-26caaf8e-6326-4acd-ad78-09612619af4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026252224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1026252224
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.4014717346
Short name T189
Test name
Test status
Simulation time 55281968726 ps
CPU time 671.14 seconds
Started Jul 09 05:05:41 PM PDT 24
Finished Jul 09 05:16:57 PM PDT 24
Peak memory 237608 kb
Host smart-46a7a673-b56c-40ac-946f-63c08c47e651
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014717346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.4014717346
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.4026484947
Short name T356
Test name
Test status
Simulation time 1364914116 ps
CPU time 29.09 seconds
Started Jul 09 05:05:39 PM PDT 24
Finished Jul 09 05:06:12 PM PDT 24
Peak memory 218616 kb
Host smart-a2ab062d-d2ca-4bc3-a4a8-ccd7330fe97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026484947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.4026484947
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1230817095
Short name T202
Test name
Test status
Simulation time 243962044 ps
CPU time 10.46 seconds
Started Jul 09 05:05:39 PM PDT 24
Finished Jul 09 05:05:53 PM PDT 24
Peak memory 219248 kb
Host smart-53c1dd4a-34b9-495c-b406-88c143a8b8bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1230817095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1230817095
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.186449752
Short name T23
Test name
Test status
Simulation time 8740455550 ps
CPU time 141.21 seconds
Started Jul 09 05:05:39 PM PDT 24
Finished Jul 09 05:08:05 PM PDT 24
Peak memory 236884 kb
Host smart-5d900440-d003-4b97-b547-9d50f284d9f5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186449752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.186449752
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3682971463
Short name T236
Test name
Test status
Simulation time 10896799786 ps
CPU time 51.17 seconds
Started Jul 09 05:05:39 PM PDT 24
Finished Jul 09 05:06:34 PM PDT 24
Peak memory 215824 kb
Host smart-4b9e10ca-a7eb-495c-b80e-3a689be28026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682971463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3682971463
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1143555621
Short name T253
Test name
Test status
Simulation time 1871595800 ps
CPU time 53.45 seconds
Started Jul 09 05:05:42 PM PDT 24
Finished Jul 09 05:06:41 PM PDT 24
Peak memory 220168 kb
Host smart-8055c33c-7b5f-43bb-a62b-b4d266fd7cc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143555621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1143555621
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2824365185
Short name T258
Test name
Test status
Simulation time 167516580 ps
CPU time 8.36 seconds
Started Jul 09 05:05:56 PM PDT 24
Finished Jul 09 05:06:12 PM PDT 24
Peak memory 218120 kb
Host smart-d9c5d91b-fae8-41e4-a8f4-0781cc1ac430
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824365185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2824365185
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3235172217
Short name T192
Test name
Test status
Simulation time 100785888595 ps
CPU time 869.43 seconds
Started Jul 09 05:05:56 PM PDT 24
Finished Jul 09 05:20:33 PM PDT 24
Peak memory 227596 kb
Host smart-168361ef-f30a-4512-ad46-de010c5a44cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235172217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3235172217
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3071523342
Short name T207
Test name
Test status
Simulation time 409985366 ps
CPU time 19.51 seconds
Started Jul 09 05:05:57 PM PDT 24
Finished Jul 09 05:06:24 PM PDT 24
Peak memory 219216 kb
Host smart-b18087c8-5eeb-4c44-829f-63297e862f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071523342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3071523342
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.190048275
Short name T184
Test name
Test status
Simulation time 4302319766 ps
CPU time 23.23 seconds
Started Jul 09 05:05:56 PM PDT 24
Finished Jul 09 05:06:27 PM PDT 24
Peak memory 211632 kb
Host smart-02d86b09-11e7-4dc3-8ffe-9e990995644c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=190048275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.190048275
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.1288644016
Short name T348
Test name
Test status
Simulation time 6322603971 ps
CPU time 60.95 seconds
Started Jul 09 05:05:54 PM PDT 24
Finished Jul 09 05:07:03 PM PDT 24
Peak memory 216808 kb
Host smart-e08e2c47-4dc0-4548-ad5c-2fc6962aa4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288644016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.1288644016
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3817389890
Short name T178
Test name
Test status
Simulation time 13092676053 ps
CPU time 72.94 seconds
Started Jul 09 05:05:56 PM PDT 24
Finished Jul 09 05:07:17 PM PDT 24
Peak memory 219216 kb
Host smart-b5e13e05-ed7b-42c1-b578-fe46fcb13dfb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817389890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3817389890
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2118987177
Short name T237
Test name
Test status
Simulation time 7087693924 ps
CPU time 18.42 seconds
Started Jul 09 05:06:08 PM PDT 24
Finished Jul 09 05:06:27 PM PDT 24
Peak memory 217364 kb
Host smart-f187249a-2237-46d0-8b83-5eb5315dfbc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118987177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2118987177
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.473432666
Short name T323
Test name
Test status
Simulation time 248920302432 ps
CPU time 489.2 seconds
Started Jul 09 05:06:04 PM PDT 24
Finished Jul 09 05:14:16 PM PDT 24
Peak memory 232700 kb
Host smart-814f30e6-5471-4054-8618-f87dd208b2ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473432666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.473432666
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.4236476487
Short name T197
Test name
Test status
Simulation time 25092773226 ps
CPU time 67.94 seconds
Started Jul 09 05:06:03 PM PDT 24
Finished Jul 09 05:07:14 PM PDT 24
Peak memory 219624 kb
Host smart-e38ab315-2b95-4eb4-8558-44845193a843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236476487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.4236476487
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3247043336
Short name T65
Test name
Test status
Simulation time 365909064 ps
CPU time 10.64 seconds
Started Jul 09 05:06:00 PM PDT 24
Finished Jul 09 05:06:16 PM PDT 24
Peak memory 219244 kb
Host smart-90e98f08-de9c-4ccd-bb42-6d461193e2e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3247043336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3247043336
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.399856083
Short name T139
Test name
Test status
Simulation time 12042778517 ps
CPU time 34.59 seconds
Started Jul 09 05:05:58 PM PDT 24
Finished Jul 09 05:06:40 PM PDT 24
Peak memory 216432 kb
Host smart-957127b6-0c84-490a-816e-a056bd87ccc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399856083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.399856083
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3786759042
Short name T340
Test name
Test status
Simulation time 2351773179 ps
CPU time 37.16 seconds
Started Jul 09 05:06:00 PM PDT 24
Finished Jul 09 05:06:43 PM PDT 24
Peak memory 219356 kb
Host smart-1e865530-fb46-4299-a3d4-b80166a8df5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786759042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3786759042
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2673809313
Short name T238
Test name
Test status
Simulation time 3304632954 ps
CPU time 14.2 seconds
Started Jul 09 05:06:13 PM PDT 24
Finished Jul 09 05:06:28 PM PDT 24
Peak memory 217256 kb
Host smart-40a5e097-3695-4965-bc93-adf0e57f0b23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673809313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2673809313
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2289639683
Short name T311
Test name
Test status
Simulation time 8972669245 ps
CPU time 212.42 seconds
Started Jul 09 05:06:10 PM PDT 24
Finished Jul 09 05:09:43 PM PDT 24
Peak memory 233700 kb
Host smart-ddff0c1e-b9ba-496e-8bc3-750eee53d602
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289639683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2289639683
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2906684192
Short name T171
Test name
Test status
Simulation time 32118381415 ps
CPU time 64.52 seconds
Started Jul 09 05:06:14 PM PDT 24
Finished Jul 09 05:07:19 PM PDT 24
Peak memory 219516 kb
Host smart-1fc5928b-7597-4293-8cbe-4fc5aa74656d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906684192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2906684192
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3442785880
Short name T9
Test name
Test status
Simulation time 663658436 ps
CPU time 10.5 seconds
Started Jul 09 05:06:12 PM PDT 24
Finished Jul 09 05:06:23 PM PDT 24
Peak memory 219220 kb
Host smart-ddf01d59-fa88-435f-80d4-2f2d52416334
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3442785880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3442785880
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.657211906
Short name T240
Test name
Test status
Simulation time 361726446 ps
CPU time 20.25 seconds
Started Jul 09 05:06:08 PM PDT 24
Finished Jul 09 05:06:29 PM PDT 24
Peak memory 216544 kb
Host smart-462f3bee-b075-4d66-b9a6-0f841d4cb329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657211906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.657211906
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2959685691
Short name T300
Test name
Test status
Simulation time 4208685972 ps
CPU time 34.01 seconds
Started Jul 09 05:06:09 PM PDT 24
Finished Jul 09 05:06:44 PM PDT 24
Peak memory 214456 kb
Host smart-50ea4994-ef99-4fde-a1e5-f5dc26dabc91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959685691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2959685691
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.4136885286
Short name T291
Test name
Test status
Simulation time 16721748128 ps
CPU time 27.43 seconds
Started Jul 09 05:06:17 PM PDT 24
Finished Jul 09 05:06:46 PM PDT 24
Peak memory 217456 kb
Host smart-a1e025e2-1fa9-4195-96ec-e21d68c88946
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136885286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.4136885286
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.232046692
Short name T308
Test name
Test status
Simulation time 11963370192 ps
CPU time 171.24 seconds
Started Jul 09 05:06:12 PM PDT 24
Finished Jul 09 05:09:04 PM PDT 24
Peak memory 216896 kb
Host smart-47cf8342-ab21-4360-ad3b-a393b7d09fe4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232046692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.232046692
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.235362542
Short name T223
Test name
Test status
Simulation time 25470708582 ps
CPU time 58.37 seconds
Started Jul 09 05:06:12 PM PDT 24
Finished Jul 09 05:07:11 PM PDT 24
Peak memory 219204 kb
Host smart-73ca9980-b329-4c3c-8d92-734689289d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235362542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.235362542
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1705820514
Short name T196
Test name
Test status
Simulation time 7981376594 ps
CPU time 33.04 seconds
Started Jul 09 05:06:12 PM PDT 24
Finished Jul 09 05:06:46 PM PDT 24
Peak memory 212096 kb
Host smart-ca1abeb0-ef22-48f2-9545-283d84e8ce02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1705820514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1705820514
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2723777436
Short name T342
Test name
Test status
Simulation time 1382645161 ps
CPU time 20.23 seconds
Started Jul 09 05:06:13 PM PDT 24
Finished Jul 09 05:06:34 PM PDT 24
Peak memory 216020 kb
Host smart-3cb0c947-ecb4-4486-8bf4-e1a67d8c0f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723777436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2723777436
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2708942364
Short name T248
Test name
Test status
Simulation time 335597154 ps
CPU time 14.74 seconds
Started Jul 09 05:06:13 PM PDT 24
Finished Jul 09 05:06:29 PM PDT 24
Peak memory 219212 kb
Host smart-fb109aa9-1b73-4b4f-9c5d-81fd29e3b71e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708942364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2708942364
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3653740702
Short name T259
Test name
Test status
Simulation time 1074147035 ps
CPU time 15.59 seconds
Started Jul 09 05:06:17 PM PDT 24
Finished Jul 09 05:06:33 PM PDT 24
Peak memory 213184 kb
Host smart-518c8bfd-c609-4712-b6ac-b1880e0433e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653740702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3653740702
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1978682964
Short name T344
Test name
Test status
Simulation time 78942251552 ps
CPU time 689.57 seconds
Started Jul 09 05:06:17 PM PDT 24
Finished Jul 09 05:17:48 PM PDT 24
Peak memory 227136 kb
Host smart-75bae7a3-a88a-43b9-8dbd-7ac0fa12ddfd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978682964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1978682964
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1922966328
Short name T257
Test name
Test status
Simulation time 42210901343 ps
CPU time 67.68 seconds
Started Jul 09 05:06:17 PM PDT 24
Finished Jul 09 05:07:26 PM PDT 24
Peak memory 219152 kb
Host smart-7f536289-f869-461f-9d48-96631ff63b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922966328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1922966328
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1383077033
Short name T170
Test name
Test status
Simulation time 706939773 ps
CPU time 10.54 seconds
Started Jul 09 05:06:16 PM PDT 24
Finished Jul 09 05:06:27 PM PDT 24
Peak memory 219224 kb
Host smart-b2c82275-c24a-4bc4-9c18-7d473c9c5779
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1383077033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1383077033
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3693703293
Short name T272
Test name
Test status
Simulation time 8565774840 ps
CPU time 44.38 seconds
Started Jul 09 05:06:17 PM PDT 24
Finished Jul 09 05:07:02 PM PDT 24
Peak memory 217536 kb
Host smart-235a30d2-c2e1-4884-8fd8-04a5f0d8d204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693703293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3693703293
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1705128964
Short name T125
Test name
Test status
Simulation time 15421212361 ps
CPU time 51.58 seconds
Started Jul 09 05:06:18 PM PDT 24
Finished Jul 09 05:07:10 PM PDT 24
Peak memory 217336 kb
Host smart-9771b86e-f569-4f17-8ef3-59f8ce1e9ca5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705128964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1705128964
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2160546107
Short name T324
Test name
Test status
Simulation time 1650883153 ps
CPU time 11.69 seconds
Started Jul 09 05:06:22 PM PDT 24
Finished Jul 09 05:06:35 PM PDT 24
Peak memory 217032 kb
Host smart-4ef32f1c-c2bf-4245-b0d6-ff7f15e2d360
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160546107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2160546107
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.823929163
Short name T292
Test name
Test status
Simulation time 40023271287 ps
CPU time 508.72 seconds
Started Jul 09 05:06:25 PM PDT 24
Finished Jul 09 05:14:55 PM PDT 24
Peak memory 219456 kb
Host smart-3d880257-71f6-46cf-b660-e362914e5a8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823929163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.823929163
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1400015302
Short name T226
Test name
Test status
Simulation time 16745826675 ps
CPU time 62.95 seconds
Started Jul 09 05:06:21 PM PDT 24
Finished Jul 09 05:07:25 PM PDT 24
Peak memory 219204 kb
Host smart-71320f1a-1b5f-4f7c-b288-5cbb15981486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400015302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1400015302
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.821143354
Short name T351
Test name
Test status
Simulation time 2494960558 ps
CPU time 23.41 seconds
Started Jul 09 05:06:22 PM PDT 24
Finished Jul 09 05:06:46 PM PDT 24
Peak memory 219304 kb
Host smart-f33e18bc-74e6-4f34-82c0-c2532c7fbdad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=821143354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.821143354
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3378451059
Short name T34
Test name
Test status
Simulation time 2157355864 ps
CPU time 33.83 seconds
Started Jul 09 05:06:18 PM PDT 24
Finished Jul 09 05:06:53 PM PDT 24
Peak memory 216860 kb
Host smart-89ee134a-357b-470c-ab39-1fb70178c98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378451059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3378451059
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3556182869
Short name T221
Test name
Test status
Simulation time 2714566737 ps
CPU time 38.23 seconds
Started Jul 09 05:06:21 PM PDT 24
Finished Jul 09 05:07:00 PM PDT 24
Peak memory 219272 kb
Host smart-4543a1d5-8766-48d2-94ba-ce6563206aad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556182869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3556182869
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1680041367
Short name T16
Test name
Test status
Simulation time 42284674697 ps
CPU time 1672.49 seconds
Started Jul 09 05:06:22 PM PDT 24
Finished Jul 09 05:34:16 PM PDT 24
Peak memory 235608 kb
Host smart-8fb021e2-918d-4f8c-a170-81ba0ce4ec93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680041367 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.1680041367
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1608891987
Short name T318
Test name
Test status
Simulation time 3234224830 ps
CPU time 26.88 seconds
Started Jul 09 05:06:21 PM PDT 24
Finished Jul 09 05:06:48 PM PDT 24
Peak memory 217200 kb
Host smart-c63fdf36-ab81-4cdb-8def-5f840fca13e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608891987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1608891987
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3753733235
Short name T138
Test name
Test status
Simulation time 29889138103 ps
CPU time 465.52 seconds
Started Jul 09 05:06:22 PM PDT 24
Finished Jul 09 05:14:08 PM PDT 24
Peak memory 225868 kb
Host smart-4b55e433-b908-4287-875d-d907b6df13bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753733235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3753733235
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1373651813
Short name T265
Test name
Test status
Simulation time 3660681366 ps
CPU time 19.91 seconds
Started Jul 09 05:06:23 PM PDT 24
Finished Jul 09 05:06:44 PM PDT 24
Peak memory 219260 kb
Host smart-d9c75465-dbd5-4998-afea-1959fd5c45b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373651813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1373651813
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2265189268
Short name T104
Test name
Test status
Simulation time 2417128440 ps
CPU time 23.67 seconds
Started Jul 09 05:06:20 PM PDT 24
Finished Jul 09 05:06:44 PM PDT 24
Peak memory 219292 kb
Host smart-608834da-ff19-445d-9e69-0869d540b336
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2265189268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2265189268
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3980672508
Short name T241
Test name
Test status
Simulation time 1275120767 ps
CPU time 20.39 seconds
Started Jul 09 05:06:20 PM PDT 24
Finished Jul 09 05:06:40 PM PDT 24
Peak memory 216448 kb
Host smart-dcd4a976-4944-4850-be15-35bd03ee52da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980672508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3980672508
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.900166309
Short name T174
Test name
Test status
Simulation time 3603691438 ps
CPU time 44.36 seconds
Started Jul 09 05:06:22 PM PDT 24
Finished Jul 09 05:07:08 PM PDT 24
Peak memory 219264 kb
Host smart-2bf49e5d-03a1-4183-9fb0-05ab86d8cb2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900166309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.900166309
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2047293381
Short name T26
Test name
Test status
Simulation time 1791774330 ps
CPU time 19.68 seconds
Started Jul 09 05:06:27 PM PDT 24
Finished Jul 09 05:06:48 PM PDT 24
Peak memory 217108 kb
Host smart-478cf32f-d549-4452-b2d4-907300a93ab1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047293381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2047293381
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2259870855
Short name T359
Test name
Test status
Simulation time 234738460376 ps
CPU time 595.69 seconds
Started Jul 09 05:06:24 PM PDT 24
Finished Jul 09 05:16:20 PM PDT 24
Peak memory 216856 kb
Host smart-6646ae80-4fea-4249-80e5-3d315d2a0bdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259870855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2259870855
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2425422401
Short name T347
Test name
Test status
Simulation time 1963916164 ps
CPU time 32.22 seconds
Started Jul 09 05:06:22 PM PDT 24
Finished Jul 09 05:06:55 PM PDT 24
Peak memory 219240 kb
Host smart-78497b01-f13a-40f5-bc64-936805f3b737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425422401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2425422401
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1283837159
Short name T206
Test name
Test status
Simulation time 8034595752 ps
CPU time 26.74 seconds
Started Jul 09 05:06:22 PM PDT 24
Finished Jul 09 05:06:50 PM PDT 24
Peak memory 212012 kb
Host smart-675bcda0-a12a-4075-9f40-d7cf0f7e5963
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1283837159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1283837159
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.814033166
Short name T43
Test name
Test status
Simulation time 1556643192 ps
CPU time 31.29 seconds
Started Jul 09 05:06:21 PM PDT 24
Finished Jul 09 05:06:53 PM PDT 24
Peak memory 216196 kb
Host smart-ee327890-1ae5-48c2-bbd1-9085c16d0376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814033166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.814033166
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.703933718
Short name T328
Test name
Test status
Simulation time 2473354919 ps
CPU time 41.22 seconds
Started Jul 09 05:06:21 PM PDT 24
Finished Jul 09 05:07:03 PM PDT 24
Peak memory 219292 kb
Host smart-a4090e81-1f28-4830-9564-b265d51c2490
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703933718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.703933718
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3634309212
Short name T199
Test name
Test status
Simulation time 17559712014 ps
CPU time 25.49 seconds
Started Jul 09 05:06:26 PM PDT 24
Finished Jul 09 05:06:53 PM PDT 24
Peak memory 217408 kb
Host smart-96d08209-fef0-413a-873b-533b3433f975
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634309212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3634309212
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.241191070
Short name T252
Test name
Test status
Simulation time 21652950507 ps
CPU time 458.5 seconds
Started Jul 09 05:06:25 PM PDT 24
Finished Jul 09 05:14:04 PM PDT 24
Peak memory 234892 kb
Host smart-65ff4b9b-f193-485a-91ea-2d0552a5759d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241191070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.241191070
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3597864809
Short name T336
Test name
Test status
Simulation time 93037222998 ps
CPU time 73.16 seconds
Started Jul 09 05:06:26 PM PDT 24
Finished Jul 09 05:07:40 PM PDT 24
Peak memory 219244 kb
Host smart-131c7c37-3014-4b6c-a0bf-4238c56d6bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597864809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3597864809
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3355627100
Short name T251
Test name
Test status
Simulation time 16453386457 ps
CPU time 20.65 seconds
Started Jul 09 05:06:25 PM PDT 24
Finished Jul 09 05:06:46 PM PDT 24
Peak memory 211864 kb
Host smart-08cec531-ef6c-4ab7-b942-ed42b79156fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3355627100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3355627100
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.461961629
Short name T8
Test name
Test status
Simulation time 9088566424 ps
CPU time 50.35 seconds
Started Jul 09 05:06:25 PM PDT 24
Finished Jul 09 05:07:17 PM PDT 24
Peak memory 216640 kb
Host smart-81a15aa1-7cda-4f24-902a-2d270fb4019f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461961629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.461961629
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3465078126
Short name T128
Test name
Test status
Simulation time 13298234181 ps
CPU time 80.92 seconds
Started Jul 09 05:06:26 PM PDT 24
Finished Jul 09 05:07:48 PM PDT 24
Peak memory 219296 kb
Host smart-d7795f7b-8ac4-4297-99dd-aa485d6e0224
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465078126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3465078126
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3920310096
Short name T193
Test name
Test status
Simulation time 1040975135 ps
CPU time 14.81 seconds
Started Jul 09 05:06:26 PM PDT 24
Finished Jul 09 05:06:42 PM PDT 24
Peak memory 216976 kb
Host smart-3de843b7-1d26-48a6-90d4-51ffa6674cd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920310096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3920310096
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.4036902359
Short name T49
Test name
Test status
Simulation time 13540442475 ps
CPU time 65.58 seconds
Started Jul 09 05:06:27 PM PDT 24
Finished Jul 09 05:07:34 PM PDT 24
Peak memory 219352 kb
Host smart-27851133-c5ec-497a-9818-981adfad803b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036902359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.4036902359
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.4268752913
Short name T37
Test name
Test status
Simulation time 2381687068 ps
CPU time 22.9 seconds
Started Jul 09 05:06:26 PM PDT 24
Finished Jul 09 05:06:50 PM PDT 24
Peak memory 219324 kb
Host smart-d8f836c5-106f-4390-9a7f-b4891b32f4e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4268752913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.4268752913
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.609336637
Short name T228
Test name
Test status
Simulation time 17831034180 ps
CPU time 45.25 seconds
Started Jul 09 05:06:26 PM PDT 24
Finished Jul 09 05:07:12 PM PDT 24
Peak memory 216016 kb
Host smart-1280050c-089c-4ed2-9ada-702a838c70cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609336637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.609336637
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.97995145
Short name T147
Test name
Test status
Simulation time 1016339626 ps
CPU time 21.26 seconds
Started Jul 09 05:06:26 PM PDT 24
Finished Jul 09 05:06:49 PM PDT 24
Peak memory 216708 kb
Host smart-b8421560-e82b-4474-9e33-4924a3940e56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97995145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 29.rom_ctrl_stress_all.97995145
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2758865459
Short name T179
Test name
Test status
Simulation time 7236415508 ps
CPU time 28.94 seconds
Started Jul 09 05:05:42 PM PDT 24
Finished Jul 09 05:06:16 PM PDT 24
Peak memory 217440 kb
Host smart-07937060-6a06-4ed7-8d7c-a6dbdac506f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758865459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2758865459
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1769952197
Short name T48
Test name
Test status
Simulation time 4561630695 ps
CPU time 207.11 seconds
Started Jul 09 05:05:40 PM PDT 24
Finished Jul 09 05:09:12 PM PDT 24
Peak memory 229520 kb
Host smart-726fea5a-f083-4485-b761-64b6a1133e90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769952197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1769952197
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2174043
Short name T341
Test name
Test status
Simulation time 7017936459 ps
CPU time 60.15 seconds
Started Jul 09 05:05:41 PM PDT 24
Finished Jul 09 05:06:46 PM PDT 24
Peak memory 219372 kb
Host smart-a745f861-1fc0-45ff-9687-97dd18a827c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2174043
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1703456901
Short name T297
Test name
Test status
Simulation time 666306492 ps
CPU time 10.26 seconds
Started Jul 09 05:05:39 PM PDT 24
Finished Jul 09 05:05:53 PM PDT 24
Peak memory 219252 kb
Host smart-f75f34a3-2655-4072-b963-9227319efb93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1703456901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1703456901
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.304451312
Short name T21
Test name
Test status
Simulation time 1446364275 ps
CPU time 230.43 seconds
Started Jul 09 05:05:42 PM PDT 24
Finished Jul 09 05:09:38 PM PDT 24
Peak memory 236328 kb
Host smart-7e20937e-78bd-4dbd-99f1-d9fd3f711110
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304451312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.304451312
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1300186582
Short name T79
Test name
Test status
Simulation time 4911476390 ps
CPU time 39.13 seconds
Started Jul 09 05:05:40 PM PDT 24
Finished Jul 09 05:06:24 PM PDT 24
Peak memory 216784 kb
Host smart-8aa55a16-f2ea-431f-8317-208505a66d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300186582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1300186582
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1616678939
Short name T225
Test name
Test status
Simulation time 2379499179 ps
CPU time 23.69 seconds
Started Jul 09 05:05:41 PM PDT 24
Finished Jul 09 05:06:10 PM PDT 24
Peak memory 214624 kb
Host smart-65679781-08eb-4970-b40f-88428d5b6f66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616678939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1616678939
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2460822510
Short name T287
Test name
Test status
Simulation time 8049919872 ps
CPU time 32.37 seconds
Started Jul 09 05:06:29 PM PDT 24
Finished Jul 09 05:07:02 PM PDT 24
Peak memory 217460 kb
Host smart-40e38417-0c77-4dd1-858a-227a6cf0e78c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460822510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2460822510
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.440982381
Short name T250
Test name
Test status
Simulation time 106211446026 ps
CPU time 816.46 seconds
Started Jul 09 05:06:25 PM PDT 24
Finished Jul 09 05:20:02 PM PDT 24
Peak memory 234012 kb
Host smart-3667e4a0-bf34-4934-b4e6-a74ae9f369b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440982381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.440982381
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1666184981
Short name T210
Test name
Test status
Simulation time 3415149893 ps
CPU time 41.5 seconds
Started Jul 09 05:06:27 PM PDT 24
Finished Jul 09 05:07:10 PM PDT 24
Peak memory 219288 kb
Host smart-0bfdc41f-cdde-4971-be42-1588daa6516a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666184981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1666184981
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.830620220
Short name T204
Test name
Test status
Simulation time 2517795212 ps
CPU time 23.78 seconds
Started Jul 09 05:06:29 PM PDT 24
Finished Jul 09 05:06:53 PM PDT 24
Peak memory 211296 kb
Host smart-a78e9177-eef1-433c-930b-21bb1cc8ac8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=830620220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.830620220
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.4277672254
Short name T39
Test name
Test status
Simulation time 4836936286 ps
CPU time 54.82 seconds
Started Jul 09 05:06:24 PM PDT 24
Finished Jul 09 05:07:20 PM PDT 24
Peak memory 216692 kb
Host smart-c4ae186e-ab0a-4c56-a574-c4deb511e12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277672254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.4277672254
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1063282524
Short name T285
Test name
Test status
Simulation time 7271877187 ps
CPU time 31.14 seconds
Started Jul 09 05:06:27 PM PDT 24
Finished Jul 09 05:07:00 PM PDT 24
Peak memory 214840 kb
Host smart-5eac6c5b-6288-4cf9-bda4-53c57a9686f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063282524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1063282524
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2372110612
Short name T181
Test name
Test status
Simulation time 1004003559 ps
CPU time 15.48 seconds
Started Jul 09 05:06:30 PM PDT 24
Finished Jul 09 05:06:46 PM PDT 24
Peak memory 217368 kb
Host smart-6134bbed-34ae-45e2-a9ac-0c4c283fd5de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372110612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2372110612
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1939297498
Short name T286
Test name
Test status
Simulation time 67606052045 ps
CPU time 383.26 seconds
Started Jul 09 05:06:29 PM PDT 24
Finished Jul 09 05:12:53 PM PDT 24
Peak memory 239176 kb
Host smart-30503a7c-068f-4f90-baab-7c81d3ce7459
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939297498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1939297498
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.746290002
Short name T234
Test name
Test status
Simulation time 17906741710 ps
CPU time 57.9 seconds
Started Jul 09 05:06:30 PM PDT 24
Finished Jul 09 05:07:29 PM PDT 24
Peak memory 218628 kb
Host smart-3e0f0313-2a94-4c27-ad33-d9846aff7eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746290002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.746290002
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1582561090
Short name T301
Test name
Test status
Simulation time 2787349098 ps
CPU time 15.69 seconds
Started Jul 09 05:06:33 PM PDT 24
Finished Jul 09 05:06:49 PM PDT 24
Peak memory 219328 kb
Host smart-8a7d3342-2633-4dcf-87e7-b763c072f81f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1582561090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1582561090
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.474775592
Short name T355
Test name
Test status
Simulation time 7526842352 ps
CPU time 71.07 seconds
Started Jul 09 05:06:30 PM PDT 24
Finished Jul 09 05:07:42 PM PDT 24
Peak memory 216868 kb
Host smart-22bd132f-286b-420f-a359-e3afe9c2158d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474775592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.474775592
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2385276191
Short name T362
Test name
Test status
Simulation time 27018453404 ps
CPU time 101.12 seconds
Started Jul 09 05:06:30 PM PDT 24
Finished Jul 09 05:08:12 PM PDT 24
Peak memory 218776 kb
Host smart-7e5c9074-33c8-4b4b-87cf-5a5940d3a9c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385276191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2385276191
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2064599315
Short name T40
Test name
Test status
Simulation time 59092470148 ps
CPU time 656.85 seconds
Started Jul 09 05:06:30 PM PDT 24
Finished Jul 09 05:17:28 PM PDT 24
Peak memory 239296 kb
Host smart-fd94c754-4817-4cca-b861-707d221e662a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064599315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2064599315
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1794222208
Short name T278
Test name
Test status
Simulation time 1320514524 ps
CPU time 19.21 seconds
Started Jul 09 05:06:31 PM PDT 24
Finished Jul 09 05:06:51 PM PDT 24
Peak memory 219296 kb
Host smart-799418ee-e1a7-45b4-ae03-e53b348cb0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794222208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1794222208
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2487442256
Short name T121
Test name
Test status
Simulation time 5840938460 ps
CPU time 19.19 seconds
Started Jul 09 05:06:33 PM PDT 24
Finished Jul 09 05:06:53 PM PDT 24
Peak memory 211952 kb
Host smart-f453e826-2c03-4e3e-b01c-3e64285b9a08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2487442256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2487442256
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1181687011
Short name T18
Test name
Test status
Simulation time 13008227811 ps
CPU time 62.92 seconds
Started Jul 09 05:06:31 PM PDT 24
Finished Jul 09 05:07:35 PM PDT 24
Peak memory 215944 kb
Host smart-97e9ef1a-b47c-4cb8-8594-84696a7c4b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181687011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1181687011
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2457165159
Short name T329
Test name
Test status
Simulation time 16756028116 ps
CPU time 156.2 seconds
Started Jul 09 05:06:35 PM PDT 24
Finished Jul 09 05:09:12 PM PDT 24
Peak memory 219300 kb
Host smart-6e9b595a-ac2a-4336-b547-a638c48a77df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457165159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2457165159
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1843771647
Short name T190
Test name
Test status
Simulation time 506011021 ps
CPU time 10.19 seconds
Started Jul 09 05:06:35 PM PDT 24
Finished Jul 09 05:06:45 PM PDT 24
Peak memory 217124 kb
Host smart-f56a510d-c96a-49e9-81aa-33d7ac9dfcbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843771647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1843771647
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2455628441
Short name T130
Test name
Test status
Simulation time 54621414397 ps
CPU time 489.53 seconds
Started Jul 09 05:06:30 PM PDT 24
Finished Jul 09 05:14:41 PM PDT 24
Peak memory 238184 kb
Host smart-9d1dc3c5-a327-4517-989c-9c668f6a2364
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455628441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2455628441
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2078966115
Short name T320
Test name
Test status
Simulation time 10698830645 ps
CPU time 50.97 seconds
Started Jul 09 05:06:30 PM PDT 24
Finished Jul 09 05:07:22 PM PDT 24
Peak memory 219252 kb
Host smart-50a0a5ec-43e7-4de7-92b7-3bd9a89e26e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078966115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2078966115
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1806041816
Short name T217
Test name
Test status
Simulation time 2123158296 ps
CPU time 22.79 seconds
Started Jul 09 05:06:30 PM PDT 24
Finished Jul 09 05:06:54 PM PDT 24
Peak memory 219272 kb
Host smart-06109f35-6645-4606-9fe7-eb0a0cccd3cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1806041816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1806041816
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1112896907
Short name T218
Test name
Test status
Simulation time 2856759540 ps
CPU time 20.51 seconds
Started Jul 09 05:06:31 PM PDT 24
Finished Jul 09 05:06:52 PM PDT 24
Peak memory 216308 kb
Host smart-35219adb-a7ef-4b3d-9c03-e24ee8caa7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112896907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1112896907
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3937248348
Short name T213
Test name
Test status
Simulation time 189495240 ps
CPU time 17.5 seconds
Started Jul 09 05:06:31 PM PDT 24
Finished Jul 09 05:06:49 PM PDT 24
Peak memory 218536 kb
Host smart-7e5a6b4d-03d6-4f1a-b63d-4f92a6dd234b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937248348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3937248348
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2007574739
Short name T198
Test name
Test status
Simulation time 345443150 ps
CPU time 8.63 seconds
Started Jul 09 05:06:34 PM PDT 24
Finished Jul 09 05:06:43 PM PDT 24
Peak memory 217104 kb
Host smart-84b41b7c-d687-404f-bf1a-cee3bea610c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007574739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2007574739
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.333998952
Short name T168
Test name
Test status
Simulation time 27940956891 ps
CPU time 59.38 seconds
Started Jul 09 05:06:34 PM PDT 24
Finished Jul 09 05:07:34 PM PDT 24
Peak memory 219312 kb
Host smart-69d10744-9d71-4093-b26e-55c2bb7670b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333998952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.333998952
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3864535415
Short name T208
Test name
Test status
Simulation time 8894920527 ps
CPU time 22.31 seconds
Started Jul 09 05:06:36 PM PDT 24
Finished Jul 09 05:06:59 PM PDT 24
Peak memory 219336 kb
Host smart-c0d7479a-fb18-4ba7-b4d6-316341cedc83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3864535415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3864535415
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1002038946
Short name T335
Test name
Test status
Simulation time 4546468512 ps
CPU time 27.21 seconds
Started Jul 09 05:06:37 PM PDT 24
Finished Jul 09 05:07:04 PM PDT 24
Peak memory 216392 kb
Host smart-18b27757-7ab3-4c5f-bc7a-0d12bca809a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002038946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1002038946
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1177944234
Short name T151
Test name
Test status
Simulation time 1551400534 ps
CPU time 33.4 seconds
Started Jul 09 05:06:35 PM PDT 24
Finished Jul 09 05:07:09 PM PDT 24
Peak memory 219208 kb
Host smart-1c5d6de7-59c4-4bc0-90e4-3952f770ec4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177944234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1177944234
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.636025257
Short name T50
Test name
Test status
Simulation time 91341476955 ps
CPU time 931.35 seconds
Started Jul 09 05:06:35 PM PDT 24
Finished Jul 09 05:22:07 PM PDT 24
Peak memory 235780 kb
Host smart-7e598e37-d7a7-49b2-8310-c9063ec14a5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636025257 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.636025257
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.83866265
Short name T136
Test name
Test status
Simulation time 167572957 ps
CPU time 8.43 seconds
Started Jul 09 05:06:39 PM PDT 24
Finished Jul 09 05:06:48 PM PDT 24
Peak memory 217096 kb
Host smart-5ff23ac2-15f6-4d24-95d2-82f9faec27f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83866265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.83866265
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1492763473
Short name T306
Test name
Test status
Simulation time 24089925265 ps
CPU time 354.53 seconds
Started Jul 09 05:06:38 PM PDT 24
Finished Jul 09 05:12:34 PM PDT 24
Peak memory 225588 kb
Host smart-db749d4c-3a1f-43ed-b428-f57468f6787b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492763473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1492763473
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1904689855
Short name T296
Test name
Test status
Simulation time 5239830805 ps
CPU time 51.92 seconds
Started Jul 09 05:06:38 PM PDT 24
Finished Jul 09 05:07:31 PM PDT 24
Peak memory 219328 kb
Host smart-5e39ec2f-5884-438c-978a-c5e4bdb06c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904689855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1904689855
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3193598903
Short name T273
Test name
Test status
Simulation time 2969767419 ps
CPU time 26.25 seconds
Started Jul 09 05:06:38 PM PDT 24
Finished Jul 09 05:07:04 PM PDT 24
Peak memory 219256 kb
Host smart-315bb79c-5cac-4340-ac73-00763a0555b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3193598903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3193598903
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.116927094
Short name T309
Test name
Test status
Simulation time 1040057360 ps
CPU time 23.16 seconds
Started Jul 09 05:06:36 PM PDT 24
Finished Jul 09 05:07:00 PM PDT 24
Peak memory 216740 kb
Host smart-51fe3988-b181-4685-b16f-39dead9ba911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116927094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.116927094
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1137807593
Short name T144
Test name
Test status
Simulation time 10443320151 ps
CPU time 56.27 seconds
Started Jul 09 05:06:34 PM PDT 24
Finished Jul 09 05:07:31 PM PDT 24
Peak memory 217796 kb
Host smart-f7b7122b-58be-4bea-8271-3b076775de4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137807593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1137807593
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2239304505
Short name T354
Test name
Test status
Simulation time 4034966798 ps
CPU time 31.83 seconds
Started Jul 09 05:06:39 PM PDT 24
Finished Jul 09 05:07:11 PM PDT 24
Peak memory 217192 kb
Host smart-dd646714-a1b4-4f78-8cf6-d038dd8ffc2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239304505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2239304505
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2980152068
Short name T290
Test name
Test status
Simulation time 30777051824 ps
CPU time 387.5 seconds
Started Jul 09 05:06:40 PM PDT 24
Finished Jul 09 05:13:08 PM PDT 24
Peak memory 235980 kb
Host smart-b9a1ecfc-0b2b-4083-bcfb-3b0f29f641bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980152068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2980152068
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.350889573
Short name T11
Test name
Test status
Simulation time 36819443855 ps
CPU time 57.86 seconds
Started Jul 09 05:06:39 PM PDT 24
Finished Jul 09 05:07:37 PM PDT 24
Peak memory 219288 kb
Host smart-87dde981-2efb-42ee-8d2c-a531f0ac9782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350889573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.350889573
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3882321027
Short name T361
Test name
Test status
Simulation time 11837716336 ps
CPU time 27.94 seconds
Started Jul 09 05:06:39 PM PDT 24
Finished Jul 09 05:07:08 PM PDT 24
Peak memory 219288 kb
Host smart-a2a8ea47-da2c-4b0b-b4db-17fefa988d58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3882321027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3882321027
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.472528098
Short name T56
Test name
Test status
Simulation time 1431836112 ps
CPU time 20.1 seconds
Started Jul 09 05:06:38 PM PDT 24
Finished Jul 09 05:06:59 PM PDT 24
Peak memory 216880 kb
Host smart-1d5be0c5-65bf-4d35-a85c-283c69589fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472528098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.472528098
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3745846022
Short name T103
Test name
Test status
Simulation time 551367101 ps
CPU time 30.8 seconds
Started Jul 09 05:06:38 PM PDT 24
Finished Jul 09 05:07:10 PM PDT 24
Peak memory 219536 kb
Host smart-dcaef24d-c394-4407-a0d3-719927457204
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745846022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3745846022
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.821872796
Short name T182
Test name
Test status
Simulation time 2891396074 ps
CPU time 17.55 seconds
Started Jul 09 05:06:44 PM PDT 24
Finished Jul 09 05:07:02 PM PDT 24
Peak memory 213300 kb
Host smart-1871c977-762c-4589-ae08-c58a04dcac14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821872796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.821872796
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3930248105
Short name T214
Test name
Test status
Simulation time 411784831630 ps
CPU time 1151.75 seconds
Started Jul 09 05:06:44 PM PDT 24
Finished Jul 09 05:25:56 PM PDT 24
Peak memory 233848 kb
Host smart-99daac97-a908-47a9-99ed-85ad1a4f2ef6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930248105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3930248105
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3258692759
Short name T205
Test name
Test status
Simulation time 4613719707 ps
CPU time 47.96 seconds
Started Jul 09 05:06:43 PM PDT 24
Finished Jul 09 05:07:32 PM PDT 24
Peak memory 219524 kb
Host smart-1f7d4f76-0758-4fca-a8d5-028edee6165a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258692759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3258692759
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.484012717
Short name T270
Test name
Test status
Simulation time 5528187020 ps
CPU time 26.02 seconds
Started Jul 09 05:06:43 PM PDT 24
Finished Jul 09 05:07:10 PM PDT 24
Peak memory 219300 kb
Host smart-17ab6579-a195-4ea4-8dd1-258940094bc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=484012717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.484012717
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.4237067687
Short name T283
Test name
Test status
Simulation time 346182564 ps
CPU time 20.33 seconds
Started Jul 09 05:06:37 PM PDT 24
Finished Jul 09 05:06:58 PM PDT 24
Peak memory 216036 kb
Host smart-12c3df88-7669-4026-82cd-e280711d3e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237067687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.4237067687
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2207759526
Short name T326
Test name
Test status
Simulation time 35612240111 ps
CPU time 104.75 seconds
Started Jul 09 05:06:43 PM PDT 24
Finished Jul 09 05:08:28 PM PDT 24
Peak memory 219304 kb
Host smart-5d03c5b1-610b-4705-a9dd-876f0b7639ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207759526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2207759526
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2878306736
Short name T255
Test name
Test status
Simulation time 6133799201 ps
CPU time 18.1 seconds
Started Jul 09 05:06:47 PM PDT 24
Finished Jul 09 05:07:06 PM PDT 24
Peak memory 217436 kb
Host smart-022f13ec-b2a6-4391-8b44-dcd75cf914ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878306736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2878306736
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1853648339
Short name T235
Test name
Test status
Simulation time 18673136356 ps
CPU time 198.03 seconds
Started Jul 09 05:06:43 PM PDT 24
Finished Jul 09 05:10:01 PM PDT 24
Peak memory 238792 kb
Host smart-91ca72b6-5d26-4118-88d8-022e20077b09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853648339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1853648339
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2632522771
Short name T319
Test name
Test status
Simulation time 6747002900 ps
CPU time 59.84 seconds
Started Jul 09 05:06:42 PM PDT 24
Finished Jul 09 05:07:42 PM PDT 24
Peak memory 219276 kb
Host smart-c76ad6c0-4e31-4ee3-9ec9-0f247b4f9b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632522771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2632522771
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1912499506
Short name T5
Test name
Test status
Simulation time 3528412569 ps
CPU time 23.31 seconds
Started Jul 09 05:06:43 PM PDT 24
Finished Jul 09 05:07:07 PM PDT 24
Peak memory 219272 kb
Host smart-8d97b235-c7dc-4bdd-9499-320df175c58e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1912499506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1912499506
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3180457351
Short name T155
Test name
Test status
Simulation time 7025376457 ps
CPU time 47.93 seconds
Started Jul 09 05:06:44 PM PDT 24
Finished Jul 09 05:07:33 PM PDT 24
Peak memory 217464 kb
Host smart-bfba3d4d-9021-40ed-bca3-0183a041ead7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180457351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3180457351
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1039135885
Short name T188
Test name
Test status
Simulation time 25842220916 ps
CPU time 88.36 seconds
Started Jul 09 05:06:46 PM PDT 24
Finished Jul 09 05:08:15 PM PDT 24
Peak memory 219348 kb
Host smart-fb437f09-d863-49a6-a20d-64fd713233ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039135885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1039135885
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3965849454
Short name T15
Test name
Test status
Simulation time 141937000396 ps
CPU time 1186.59 seconds
Started Jul 09 05:06:44 PM PDT 24
Finished Jul 09 05:26:31 PM PDT 24
Peak memory 236088 kb
Host smart-5a0fff99-cf30-4d3a-a3f2-b7c74601c893
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965849454 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.3965849454
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.198476712
Short name T61
Test name
Test status
Simulation time 2311985659 ps
CPU time 22.19 seconds
Started Jul 09 05:06:47 PM PDT 24
Finished Jul 09 05:07:11 PM PDT 24
Peak memory 213244 kb
Host smart-9bd00640-f704-4334-b406-2ac853838590
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198476712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.198476712
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2668309633
Short name T137
Test name
Test status
Simulation time 449702607220 ps
CPU time 1028.07 seconds
Started Jul 09 05:06:56 PM PDT 24
Finished Jul 09 05:24:05 PM PDT 24
Peak memory 236492 kb
Host smart-92e2198a-636d-42aa-90ef-9c00a88444aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668309633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2668309633
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.724911291
Short name T156
Test name
Test status
Simulation time 16379163367 ps
CPU time 65.24 seconds
Started Jul 09 05:06:46 PM PDT 24
Finished Jul 09 05:07:52 PM PDT 24
Peak memory 219324 kb
Host smart-346031ca-84e7-480f-b955-32a8336a46ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724911291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.724911291
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1046144531
Short name T358
Test name
Test status
Simulation time 617291318 ps
CPU time 14.93 seconds
Started Jul 09 05:06:43 PM PDT 24
Finished Jul 09 05:06:58 PM PDT 24
Peak memory 211192 kb
Host smart-3eb90a8f-22e6-45e8-9713-d62da23b9903
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1046144531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1046144531
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1554509354
Short name T33
Test name
Test status
Simulation time 357917177 ps
CPU time 19.78 seconds
Started Jul 09 05:06:44 PM PDT 24
Finished Jul 09 05:07:04 PM PDT 24
Peak memory 216304 kb
Host smart-a9d58d60-7004-4ccb-95b7-dc783703f616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554509354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1554509354
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3519447715
Short name T222
Test name
Test status
Simulation time 75310203760 ps
CPU time 103.67 seconds
Started Jul 09 05:06:41 PM PDT 24
Finished Jul 09 05:08:25 PM PDT 24
Peak memory 219268 kb
Host smart-a141c7f5-60d9-4bb0-86f2-8f04e01cc3b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519447715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3519447715
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2348091993
Short name T35
Test name
Test status
Simulation time 791897293 ps
CPU time 9.84 seconds
Started Jul 09 05:05:42 PM PDT 24
Finished Jul 09 05:05:57 PM PDT 24
Peak memory 217052 kb
Host smart-27f4c549-0070-4d27-ab0a-df0c0ee8ea1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348091993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2348091993
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2852155283
Short name T343
Test name
Test status
Simulation time 527114944560 ps
CPU time 1223.22 seconds
Started Jul 09 05:05:44 PM PDT 24
Finished Jul 09 05:26:12 PM PDT 24
Peak memory 225348 kb
Host smart-4f514b01-c61e-4c10-bafd-c49e36413371
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852155283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2852155283
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2758332465
Short name T321
Test name
Test status
Simulation time 4105255577 ps
CPU time 31.84 seconds
Started Jul 09 05:05:42 PM PDT 24
Finished Jul 09 05:06:19 PM PDT 24
Peak memory 219316 kb
Host smart-cbbf8d84-f971-4248-822d-7812b44c033d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758332465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2758332465
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.556249467
Short name T154
Test name
Test status
Simulation time 12702028322 ps
CPU time 27.14 seconds
Started Jul 09 05:05:41 PM PDT 24
Finished Jul 09 05:06:13 PM PDT 24
Peak memory 217700 kb
Host smart-911d70b7-d426-4c11-abaa-ee4ec8cef00f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=556249467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.556249467
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.270539354
Short name T29
Test name
Test status
Simulation time 253612522 ps
CPU time 115.97 seconds
Started Jul 09 05:05:44 PM PDT 24
Finished Jul 09 05:07:45 PM PDT 24
Peak memory 237296 kb
Host smart-916599a2-e842-49c7-896c-695f51c2bbb0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270539354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.270539354
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.4147630703
Short name T353
Test name
Test status
Simulation time 22693158898 ps
CPU time 59.07 seconds
Started Jul 09 05:05:44 PM PDT 24
Finished Jul 09 05:06:48 PM PDT 24
Peak memory 217264 kb
Host smart-6cc5d319-1025-4f87-a562-2bf1015cf997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147630703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.4147630703
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2188097330
Short name T124
Test name
Test status
Simulation time 10614451379 ps
CPU time 114.66 seconds
Started Jul 09 05:05:50 PM PDT 24
Finished Jul 09 05:07:52 PM PDT 24
Peak memory 219348 kb
Host smart-62596b37-707b-478c-83bf-5fc880157d2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188097330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2188097330
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.140000980
Short name T60
Test name
Test status
Simulation time 2378983082 ps
CPU time 24.01 seconds
Started Jul 09 05:06:49 PM PDT 24
Finished Jul 09 05:07:14 PM PDT 24
Peak memory 217132 kb
Host smart-c2a8772e-b235-4e5d-b5ff-0c15a473d1cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140000980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.140000980
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2212248468
Short name T246
Test name
Test status
Simulation time 3884982187 ps
CPU time 277.54 seconds
Started Jul 09 05:06:46 PM PDT 24
Finished Jul 09 05:11:25 PM PDT 24
Peak memory 239260 kb
Host smart-faf47f60-4188-4c10-b051-cd24eb674347
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212248468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2212248468
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3988127941
Short name T281
Test name
Test status
Simulation time 5454857700 ps
CPU time 51.2 seconds
Started Jul 09 05:06:47 PM PDT 24
Finished Jul 09 05:07:39 PM PDT 24
Peak memory 219212 kb
Host smart-2aed772d-4f5c-4609-880b-6af1bf022d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988127941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3988127941
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2360687385
Short name T158
Test name
Test status
Simulation time 366859253 ps
CPU time 10.7 seconds
Started Jul 09 05:06:49 PM PDT 24
Finished Jul 09 05:07:01 PM PDT 24
Peak memory 219228 kb
Host smart-acb54072-e16a-4166-8e0b-6677be2894b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2360687385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2360687385
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.788045423
Short name T10
Test name
Test status
Simulation time 32972823529 ps
CPU time 59.81 seconds
Started Jul 09 05:06:46 PM PDT 24
Finished Jul 09 05:07:46 PM PDT 24
Peak memory 216224 kb
Host smart-db6d9165-c6a3-4375-8055-9065768ff405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788045423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.788045423
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.590847998
Short name T220
Test name
Test status
Simulation time 883141151 ps
CPU time 59.7 seconds
Started Jul 09 05:06:49 PM PDT 24
Finished Jul 09 05:07:49 PM PDT 24
Peak memory 219260 kb
Host smart-a68962f5-3d56-4bc5-8862-b5a57a6b47cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590847998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.590847998
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1123929180
Short name T299
Test name
Test status
Simulation time 7383790196 ps
CPU time 29.66 seconds
Started Jul 09 05:06:56 PM PDT 24
Finished Jul 09 05:07:26 PM PDT 24
Peak memory 217356 kb
Host smart-ea02378c-4ce9-41c2-bc41-b66174b201a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123929180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1123929180
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.4069004373
Short name T180
Test name
Test status
Simulation time 135735757139 ps
CPU time 365.03 seconds
Started Jul 09 05:06:47 PM PDT 24
Finished Jul 09 05:12:53 PM PDT 24
Peak memory 229848 kb
Host smart-28366bd5-b680-4e1a-b271-8a4c81ca58fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069004373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.4069004373
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1547199153
Short name T157
Test name
Test status
Simulation time 10411362785 ps
CPU time 49.29 seconds
Started Jul 09 05:06:55 PM PDT 24
Finished Jul 09 05:07:45 PM PDT 24
Peak memory 219152 kb
Host smart-8f961304-d7b2-47ef-a27a-b34c49dca5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547199153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1547199153
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2070196442
Short name T163
Test name
Test status
Simulation time 178077640 ps
CPU time 10.4 seconds
Started Jul 09 05:06:49 PM PDT 24
Finished Jul 09 05:07:00 PM PDT 24
Peak memory 219232 kb
Host smart-445bfcc4-d467-4778-ab18-8765f46ae598
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2070196442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2070196442
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.559676332
Short name T334
Test name
Test status
Simulation time 17098805098 ps
CPU time 45.4 seconds
Started Jul 09 05:06:47 PM PDT 24
Finished Jul 09 05:07:33 PM PDT 24
Peak memory 217240 kb
Host smart-91e0986e-1cda-400c-96e2-03a1f037fc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559676332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.559676332
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.840258703
Short name T327
Test name
Test status
Simulation time 11719981876 ps
CPU time 79.01 seconds
Started Jul 09 05:06:49 PM PDT 24
Finished Jul 09 05:08:08 PM PDT 24
Peak memory 227580 kb
Host smart-ff567ee8-aef6-45b6-962e-5f7b04099984
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840258703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.840258703
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.4162032608
Short name T264
Test name
Test status
Simulation time 15010885428 ps
CPU time 31.97 seconds
Started Jul 09 05:06:50 PM PDT 24
Finished Jul 09 05:07:22 PM PDT 24
Peak memory 217420 kb
Host smart-2226e3dc-e269-452c-80dd-d635ebec1ae0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162032608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.4162032608
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1157650101
Short name T140
Test name
Test status
Simulation time 29770839570 ps
CPU time 305.54 seconds
Started Jul 09 05:06:51 PM PDT 24
Finished Jul 09 05:11:57 PM PDT 24
Peak memory 239196 kb
Host smart-1590a5b1-d78d-45d9-bffa-7cf7c6d21504
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157650101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1157650101
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2272877196
Short name T175
Test name
Test status
Simulation time 1374726810 ps
CPU time 19.76 seconds
Started Jul 09 05:06:51 PM PDT 24
Finished Jul 09 05:07:11 PM PDT 24
Peak memory 219108 kb
Host smart-80d4e662-69f6-4172-9785-9ef19db348c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272877196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2272877196
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1059371787
Short name T3
Test name
Test status
Simulation time 1972237508 ps
CPU time 21.95 seconds
Started Jul 09 05:06:52 PM PDT 24
Finished Jul 09 05:07:14 PM PDT 24
Peak memory 211388 kb
Host smart-dfa6599a-80b4-4568-9cf3-2fd03f5305a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1059371787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1059371787
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.4067206569
Short name T276
Test name
Test status
Simulation time 7547251598 ps
CPU time 79.52 seconds
Started Jul 09 05:06:55 PM PDT 24
Finished Jul 09 05:08:15 PM PDT 24
Peak memory 217204 kb
Host smart-ff0fbf32-9ed0-4eca-8b19-e1a71a138076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067206569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.4067206569
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.483120841
Short name T129
Test name
Test status
Simulation time 17937190414 ps
CPU time 56.63 seconds
Started Jul 09 05:06:56 PM PDT 24
Finished Jul 09 05:07:53 PM PDT 24
Peak memory 218204 kb
Host smart-110e421c-0bbe-485d-b785-a6c79200ad4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483120841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.483120841
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2552670356
Short name T200
Test name
Test status
Simulation time 2313229361 ps
CPU time 22.57 seconds
Started Jul 09 05:06:51 PM PDT 24
Finished Jul 09 05:07:15 PM PDT 24
Peak memory 217124 kb
Host smart-9357106b-2f39-4f51-b2cc-30d3f1fa6211
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552670356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2552670356
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1508991354
Short name T310
Test name
Test status
Simulation time 77369298084 ps
CPU time 453.49 seconds
Started Jul 09 05:06:51 PM PDT 24
Finished Jul 09 05:14:25 PM PDT 24
Peak memory 219520 kb
Host smart-e9100bf2-7190-44db-88b8-ea6c4a57ccd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508991354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1508991354
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1613157794
Short name T153
Test name
Test status
Simulation time 31712848682 ps
CPU time 56 seconds
Started Jul 09 05:06:51 PM PDT 24
Finished Jul 09 05:07:48 PM PDT 24
Peak memory 217708 kb
Host smart-ca6852bb-a8bb-4354-ab72-ca30aab2681e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613157794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1613157794
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3814215844
Short name T44
Test name
Test status
Simulation time 716200268 ps
CPU time 10.12 seconds
Started Jul 09 05:07:27 PM PDT 24
Finished Jul 09 05:07:37 PM PDT 24
Peak memory 219192 kb
Host smart-39a2c7ed-3640-4462-81a0-7346c26e06a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3814215844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3814215844
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3444795080
Short name T230
Test name
Test status
Simulation time 23590073413 ps
CPU time 61.89 seconds
Started Jul 09 05:06:51 PM PDT 24
Finished Jul 09 05:07:54 PM PDT 24
Peak memory 217496 kb
Host smart-07f6f14a-5255-4bf6-aecf-8efa1d406f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444795080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3444795080
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3016725811
Short name T243
Test name
Test status
Simulation time 38226676937 ps
CPU time 110.73 seconds
Started Jul 09 05:06:50 PM PDT 24
Finished Jul 09 05:08:42 PM PDT 24
Peak memory 219308 kb
Host smart-f3aa52d3-fdd6-4be8-b835-e78d52605b8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016725811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3016725811
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1767152193
Short name T25
Test name
Test status
Simulation time 660236825 ps
CPU time 13.1 seconds
Started Jul 09 05:06:57 PM PDT 24
Finished Jul 09 05:07:10 PM PDT 24
Peak memory 217148 kb
Host smart-598ef196-bf56-44a7-879f-08ba71ef729d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767152193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1767152193
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3715105725
Short name T346
Test name
Test status
Simulation time 159500862701 ps
CPU time 435.16 seconds
Started Jul 09 05:06:57 PM PDT 24
Finished Jul 09 05:14:12 PM PDT 24
Peak memory 242176 kb
Host smart-f16b4923-d90a-4491-bcd8-f311ad239395
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715105725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3715105725
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2787974244
Short name T313
Test name
Test status
Simulation time 12817830896 ps
CPU time 68.14 seconds
Started Jul 09 05:06:54 PM PDT 24
Finished Jul 09 05:08:02 PM PDT 24
Peak memory 219356 kb
Host smart-0e02ad9c-e61d-4091-94a5-fc37de58f594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787974244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2787974244
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3996701062
Short name T67
Test name
Test status
Simulation time 7253482274 ps
CPU time 30.4 seconds
Started Jul 09 05:06:55 PM PDT 24
Finished Jul 09 05:07:26 PM PDT 24
Peak memory 211744 kb
Host smart-f9892e88-e756-4131-bd55-101ea0f4d1a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3996701062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3996701062
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1077097538
Short name T352
Test name
Test status
Simulation time 3549177433 ps
CPU time 41.89 seconds
Started Jul 09 05:06:53 PM PDT 24
Finished Jul 09 05:07:36 PM PDT 24
Peak memory 216260 kb
Host smart-eea7bf6a-ff5a-495a-b7b5-40a1bc4b7418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077097538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1077097538
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1646731893
Short name T173
Test name
Test status
Simulation time 2354794475 ps
CPU time 8.57 seconds
Started Jul 09 05:07:00 PM PDT 24
Finished Jul 09 05:07:09 PM PDT 24
Peak memory 217000 kb
Host smart-a9a579f8-5375-468e-8f82-442aff8113c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646731893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1646731893
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.918678036
Short name T31
Test name
Test status
Simulation time 53258429878 ps
CPU time 597.9 seconds
Started Jul 09 05:06:58 PM PDT 24
Finished Jul 09 05:16:56 PM PDT 24
Peak memory 219508 kb
Host smart-6cd79c12-302e-484c-b027-e2476479a09b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918678036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.918678036
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.381856447
Short name T32
Test name
Test status
Simulation time 30842530988 ps
CPU time 62.9 seconds
Started Jul 09 05:06:56 PM PDT 24
Finished Jul 09 05:07:59 PM PDT 24
Peak memory 219392 kb
Host smart-29c4e747-28d4-472d-9ed5-588e00dca5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381856447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.381856447
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2585953347
Short name T315
Test name
Test status
Simulation time 7728464227 ps
CPU time 30.84 seconds
Started Jul 09 05:06:55 PM PDT 24
Finished Jul 09 05:07:26 PM PDT 24
Peak memory 211596 kb
Host smart-11adb1a5-080e-400e-9743-d3ef7dc9f7c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2585953347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2585953347
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1190366418
Short name T312
Test name
Test status
Simulation time 26772777226 ps
CPU time 57.02 seconds
Started Jul 09 05:06:55 PM PDT 24
Finished Jul 09 05:07:52 PM PDT 24
Peak memory 217092 kb
Host smart-6f1fadaa-bf42-4e43-8db4-fd8af96abbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190366418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1190366418
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3394754597
Short name T266
Test name
Test status
Simulation time 5709479209 ps
CPU time 32.03 seconds
Started Jul 09 05:06:56 PM PDT 24
Finished Jul 09 05:07:29 PM PDT 24
Peak memory 214548 kb
Host smart-ee674c29-484f-4688-af67-279bc34124a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394754597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3394754597
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2150630009
Short name T284
Test name
Test status
Simulation time 16457581720 ps
CPU time 33.23 seconds
Started Jul 09 05:06:59 PM PDT 24
Finished Jul 09 05:07:32 PM PDT 24
Peak memory 217364 kb
Host smart-ff2ff60a-96a6-42a0-afca-9256092a0b72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150630009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2150630009
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1242967500
Short name T145
Test name
Test status
Simulation time 338109809116 ps
CPU time 847.3 seconds
Started Jul 09 05:07:01 PM PDT 24
Finished Jul 09 05:21:09 PM PDT 24
Peak memory 235960 kb
Host smart-b2c73094-484d-4ab7-824f-d97a2c060996
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242967500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1242967500
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3467747257
Short name T45
Test name
Test status
Simulation time 1321090648 ps
CPU time 19.08 seconds
Started Jul 09 05:07:04 PM PDT 24
Finished Jul 09 05:07:24 PM PDT 24
Peak memory 219200 kb
Host smart-903ad99e-4266-4ab8-8128-857138536dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467747257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3467747257
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3498091833
Short name T229
Test name
Test status
Simulation time 4236695709 ps
CPU time 34 seconds
Started Jul 09 05:07:00 PM PDT 24
Finished Jul 09 05:07:34 PM PDT 24
Peak memory 211592 kb
Host smart-58b1ef9b-df8a-43d2-bd8e-cb04b7143d71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3498091833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3498091833
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1106350984
Short name T6
Test name
Test status
Simulation time 347883416 ps
CPU time 20.05 seconds
Started Jul 09 05:06:58 PM PDT 24
Finished Jul 09 05:07:18 PM PDT 24
Peak memory 216688 kb
Host smart-1648bc00-1d82-4773-aa94-e50435b4a18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106350984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1106350984
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3756008979
Short name T289
Test name
Test status
Simulation time 23340577673 ps
CPU time 193.32 seconds
Started Jul 09 05:06:59 PM PDT 24
Finished Jul 09 05:10:13 PM PDT 24
Peak memory 227492 kb
Host smart-82ae0040-31f2-43b6-a36a-f80d49d1bd12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756008979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3756008979
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1814580561
Short name T360
Test name
Test status
Simulation time 1685595188 ps
CPU time 13.96 seconds
Started Jul 09 05:07:06 PM PDT 24
Finished Jul 09 05:07:21 PM PDT 24
Peak memory 217068 kb
Host smart-b175fb17-9fe6-4f4f-b0bf-21f64230d81b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814580561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1814580561
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.853768148
Short name T120
Test name
Test status
Simulation time 55518375086 ps
CPU time 286.36 seconds
Started Jul 09 05:07:04 PM PDT 24
Finished Jul 09 05:11:51 PM PDT 24
Peak memory 233888 kb
Host smart-9dcbda00-8a2c-476a-bc5b-bda13e82657f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853768148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.853768148
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1568149440
Short name T194
Test name
Test status
Simulation time 6721598051 ps
CPU time 59.37 seconds
Started Jul 09 05:07:06 PM PDT 24
Finished Jul 09 05:08:06 PM PDT 24
Peak memory 219256 kb
Host smart-49179e12-2de1-4f92-bba6-85a593e01325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568149440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1568149440
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.383121772
Short name T242
Test name
Test status
Simulation time 33796269743 ps
CPU time 31.27 seconds
Started Jul 09 05:07:07 PM PDT 24
Finished Jul 09 05:07:39 PM PDT 24
Peak memory 219272 kb
Host smart-09a7f0ec-8dfe-476a-af95-b7414ab0d67e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=383121772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.383121772
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1791842516
Short name T267
Test name
Test status
Simulation time 12369240648 ps
CPU time 53.71 seconds
Started Jul 09 05:07:05 PM PDT 24
Finished Jul 09 05:07:59 PM PDT 24
Peak memory 216200 kb
Host smart-28de2a80-56db-4df0-9084-012507e0e35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791842516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1791842516
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.4247886520
Short name T78
Test name
Test status
Simulation time 1079848886 ps
CPU time 42 seconds
Started Jul 09 05:07:03 PM PDT 24
Finished Jul 09 05:07:46 PM PDT 24
Peak memory 219324 kb
Host smart-e917dc3e-6279-4bf2-807b-a129f0af9d55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247886520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.4247886520
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3105513324
Short name T239
Test name
Test status
Simulation time 2736300205 ps
CPU time 12.96 seconds
Started Jul 09 05:07:04 PM PDT 24
Finished Jul 09 05:07:18 PM PDT 24
Peak memory 217204 kb
Host smart-05e02ab0-b5bd-4a59-a2a2-5f737df1bd2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105513324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3105513324
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.4232290506
Short name T19
Test name
Test status
Simulation time 151150900898 ps
CPU time 540.52 seconds
Started Jul 09 05:07:04 PM PDT 24
Finished Jul 09 05:16:05 PM PDT 24
Peak memory 218076 kb
Host smart-aea453d9-f5c6-4261-be82-527c0df62817
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232290506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.4232290506
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1938676121
Short name T274
Test name
Test status
Simulation time 1478582124 ps
CPU time 30.25 seconds
Started Jul 09 05:07:05 PM PDT 24
Finished Jul 09 05:07:36 PM PDT 24
Peak memory 219192 kb
Host smart-7c2ee4c5-34f6-43d2-b4d2-8233556753ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938676121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1938676121
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2179338788
Short name T271
Test name
Test status
Simulation time 15368172966 ps
CPU time 18.04 seconds
Started Jul 09 05:07:04 PM PDT 24
Finished Jul 09 05:07:23 PM PDT 24
Peak memory 219328 kb
Host smart-a76fa1cf-adeb-4890-bf3b-020490914468
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2179338788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2179338788
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1176860675
Short name T249
Test name
Test status
Simulation time 19183124740 ps
CPU time 49.02 seconds
Started Jul 09 05:07:05 PM PDT 24
Finished Jul 09 05:07:55 PM PDT 24
Peak memory 216720 kb
Host smart-ea1cfb2f-0abb-4a73-bae7-49a26af7eed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176860675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1176860675
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1889893395
Short name T298
Test name
Test status
Simulation time 821786163 ps
CPU time 11.56 seconds
Started Jul 09 05:07:06 PM PDT 24
Finished Jul 09 05:07:18 PM PDT 24
Peak memory 214512 kb
Host smart-4ff608a4-8bff-4abc-9c8c-1a2a445b40b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889893395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1889893395
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.374711660
Short name T63
Test name
Test status
Simulation time 12927025093 ps
CPU time 27.45 seconds
Started Jul 09 05:07:08 PM PDT 24
Finished Jul 09 05:07:36 PM PDT 24
Peak memory 217576 kb
Host smart-33e1dd34-8ad6-48e6-8d41-e13df7f823e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374711660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.374711660
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2018327426
Short name T47
Test name
Test status
Simulation time 48931396124 ps
CPU time 473.36 seconds
Started Jul 09 05:07:07 PM PDT 24
Finished Jul 09 05:15:01 PM PDT 24
Peak memory 233788 kb
Host smart-c58d0da9-fc75-4e96-a64c-7cab84a1b44d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018327426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2018327426
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1887642883
Short name T24
Test name
Test status
Simulation time 61706263611 ps
CPU time 65.59 seconds
Started Jul 09 05:07:06 PM PDT 24
Finished Jul 09 05:08:12 PM PDT 24
Peak memory 219252 kb
Host smart-1e9cf9bd-292a-4a2d-a933-fd942f630c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887642883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1887642883
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3977038584
Short name T201
Test name
Test status
Simulation time 1812165921 ps
CPU time 21.27 seconds
Started Jul 09 05:07:07 PM PDT 24
Finished Jul 09 05:07:29 PM PDT 24
Peak memory 219184 kb
Host smart-79d39471-7889-4096-89ad-dc11db4fc68c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3977038584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3977038584
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2874526273
Short name T260
Test name
Test status
Simulation time 53559348609 ps
CPU time 52.03 seconds
Started Jul 09 05:07:05 PM PDT 24
Finished Jul 09 05:07:58 PM PDT 24
Peak memory 216988 kb
Host smart-309ad668-b2f4-439e-a786-54b87762ed17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874526273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2874526273
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3765411618
Short name T317
Test name
Test status
Simulation time 3687119644 ps
CPU time 54.04 seconds
Started Jul 09 05:07:05 PM PDT 24
Finished Jul 09 05:07:59 PM PDT 24
Peak memory 227548 kb
Host smart-afae662b-6c8b-4cae-a2e0-14f6ddfbe1b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765411618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3765411618
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2523717740
Short name T332
Test name
Test status
Simulation time 5354654781 ps
CPU time 16.23 seconds
Started Jul 09 05:05:44 PM PDT 24
Finished Jul 09 05:06:05 PM PDT 24
Peak memory 217528 kb
Host smart-f07b8e63-9663-41c9-8d29-0a02bd93b340
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523717740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2523717740
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3163592574
Short name T20
Test name
Test status
Simulation time 7949453462 ps
CPU time 167.95 seconds
Started Jul 09 05:05:43 PM PDT 24
Finished Jul 09 05:08:36 PM PDT 24
Peak memory 233808 kb
Host smart-e75e3812-8304-42ef-a568-1a53e3e822f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163592574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3163592574
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1216841688
Short name T256
Test name
Test status
Simulation time 2538998651 ps
CPU time 19.6 seconds
Started Jul 09 05:05:42 PM PDT 24
Finished Jul 09 05:06:07 PM PDT 24
Peak memory 219296 kb
Host smart-78418257-7469-43ac-b73d-6d8a09c7de19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216841688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1216841688
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3112263923
Short name T1
Test name
Test status
Simulation time 25640863918 ps
CPU time 22.93 seconds
Started Jul 09 05:05:42 PM PDT 24
Finished Jul 09 05:06:10 PM PDT 24
Peak memory 211944 kb
Host smart-bad1ae2c-7975-4eaa-8647-bd1bd0550684
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3112263923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3112263923
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.512454908
Short name T305
Test name
Test status
Simulation time 8569407817 ps
CPU time 46.17 seconds
Started Jul 09 05:05:49 PM PDT 24
Finished Jul 09 05:06:40 PM PDT 24
Peak memory 216932 kb
Host smart-19ef0923-f686-4613-a645-bba8cdc6e306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512454908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.512454908
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.18052891
Short name T247
Test name
Test status
Simulation time 17584177436 ps
CPU time 176.6 seconds
Started Jul 09 05:05:44 PM PDT 24
Finished Jul 09 05:08:45 PM PDT 24
Peak memory 227480 kb
Host smart-46bcae5f-7193-4a4b-a3f2-b2244cd5c05d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18052891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 5.rom_ctrl_stress_all.18052891
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3394837281
Short name T64
Test name
Test status
Simulation time 3524669357 ps
CPU time 19.75 seconds
Started Jul 09 05:05:48 PM PDT 24
Finished Jul 09 05:06:13 PM PDT 24
Peak memory 217072 kb
Host smart-1296e915-a430-4d43-a126-cd801b95df4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394837281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3394837281
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.519043850
Short name T275
Test name
Test status
Simulation time 195320900424 ps
CPU time 705.64 seconds
Started Jul 09 05:05:48 PM PDT 24
Finished Jul 09 05:17:39 PM PDT 24
Peak memory 229536 kb
Host smart-095371ee-65bc-4af9-8eb8-6b7b07aba5db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519043850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.519043850
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3795192951
Short name T261
Test name
Test status
Simulation time 689398820 ps
CPU time 19.51 seconds
Started Jul 09 05:05:51 PM PDT 24
Finished Jul 09 05:06:18 PM PDT 24
Peak memory 219228 kb
Host smart-d998fe42-a145-4db4-8258-23f99906a894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795192951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3795192951
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1484595908
Short name T279
Test name
Test status
Simulation time 2425353208 ps
CPU time 9.95 seconds
Started Jul 09 05:05:43 PM PDT 24
Finished Jul 09 05:05:58 PM PDT 24
Peak memory 219272 kb
Host smart-2d734436-e656-4a8f-836b-897537c82580
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1484595908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1484595908
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1325455507
Short name T149
Test name
Test status
Simulation time 39868015869 ps
CPU time 76.94 seconds
Started Jul 09 05:05:42 PM PDT 24
Finished Jul 09 05:07:05 PM PDT 24
Peak memory 217104 kb
Host smart-7a774602-8ebf-4f5a-b747-0f1f0a1ab22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325455507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1325455507
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3030762027
Short name T333
Test name
Test status
Simulation time 19452423859 ps
CPU time 110.66 seconds
Started Jul 09 05:05:44 PM PDT 24
Finished Jul 09 05:07:39 PM PDT 24
Peak memory 219296 kb
Host smart-16bed94f-b3b7-43fa-95b3-74c4593370f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030762027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3030762027
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2425957790
Short name T27
Test name
Test status
Simulation time 4233299597 ps
CPU time 16.26 seconds
Started Jul 09 05:05:51 PM PDT 24
Finished Jul 09 05:06:14 PM PDT 24
Peak memory 217208 kb
Host smart-3201c613-b9b1-4fb3-9d4d-368c37b899b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425957790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2425957790
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2560722681
Short name T159
Test name
Test status
Simulation time 9135823984 ps
CPU time 199.66 seconds
Started Jul 09 05:05:46 PM PDT 24
Finished Jul 09 05:09:10 PM PDT 24
Peak memory 237644 kb
Host smart-0a76f872-9e17-4617-8737-8edb299153ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560722681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2560722681
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1538425004
Short name T269
Test name
Test status
Simulation time 9550689443 ps
CPU time 48.36 seconds
Started Jul 09 05:05:51 PM PDT 24
Finished Jul 09 05:06:47 PM PDT 24
Peak memory 219144 kb
Host smart-5f4ab920-4a70-487a-9ebf-8bbf33a750d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538425004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1538425004
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2985954092
Short name T66
Test name
Test status
Simulation time 608316161 ps
CPU time 14.21 seconds
Started Jul 09 05:05:51 PM PDT 24
Finished Jul 09 05:06:12 PM PDT 24
Peak memory 218412 kb
Host smart-493186b1-79ea-417a-a974-0be84d7726e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2985954092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2985954092
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1645828472
Short name T13
Test name
Test status
Simulation time 15853618552 ps
CPU time 44.35 seconds
Started Jul 09 05:05:50 PM PDT 24
Finished Jul 09 05:06:40 PM PDT 24
Peak memory 217500 kb
Host smart-b5138ff3-392c-47cb-9998-464b605952fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645828472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1645828472
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3936106607
Short name T231
Test name
Test status
Simulation time 22124633010 ps
CPU time 81.47 seconds
Started Jul 09 05:05:50 PM PDT 24
Finished Jul 09 05:07:18 PM PDT 24
Peak memory 219384 kb
Host smart-98d845d8-f09b-43fa-a36d-3549baf704df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936106607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3936106607
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1424614845
Short name T302
Test name
Test status
Simulation time 2210895494 ps
CPU time 22.69 seconds
Started Jul 09 05:05:51 PM PDT 24
Finished Jul 09 05:06:21 PM PDT 24
Peak memory 217160 kb
Host smart-1234a559-c446-4812-a0d0-4bcfbaa91549
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424614845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1424614845
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.512403734
Short name T244
Test name
Test status
Simulation time 70166264340 ps
CPU time 600.78 seconds
Started Jul 09 05:05:51 PM PDT 24
Finished Jul 09 05:15:59 PM PDT 24
Peak memory 238988 kb
Host smart-08bb7cbb-85d5-4394-8567-e63966117a13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512403734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.512403734
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.508038602
Short name T325
Test name
Test status
Simulation time 1375063628 ps
CPU time 19.14 seconds
Started Jul 09 05:05:50 PM PDT 24
Finished Jul 09 05:06:16 PM PDT 24
Peak memory 219224 kb
Host smart-cb427f61-9cf2-46b5-a9e3-96b28da0daf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508038602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.508038602
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.4138718840
Short name T123
Test name
Test status
Simulation time 338937075 ps
CPU time 10.58 seconds
Started Jul 09 05:05:50 PM PDT 24
Finished Jul 09 05:06:07 PM PDT 24
Peak memory 219288 kb
Host smart-7d31c51b-3e84-436d-80d0-a9eedbcf85ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4138718840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.4138718840
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.37196102
Short name T133
Test name
Test status
Simulation time 689354972 ps
CPU time 20.8 seconds
Started Jul 09 05:05:49 PM PDT 24
Finished Jul 09 05:06:16 PM PDT 24
Peak memory 216536 kb
Host smart-46e909bb-f57d-4875-bbdb-9829efa41955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37196102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.37196102
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3459523166
Short name T143
Test name
Test status
Simulation time 18434282862 ps
CPU time 179.13 seconds
Started Jul 09 05:05:50 PM PDT 24
Finished Jul 09 05:08:55 PM PDT 24
Peak memory 221296 kb
Host smart-4cd64317-24da-464f-951e-1012ddafcf31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459523166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3459523166
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.799418148
Short name T127
Test name
Test status
Simulation time 688993321 ps
CPU time 8.45 seconds
Started Jul 09 05:05:51 PM PDT 24
Finished Jul 09 05:06:07 PM PDT 24
Peak memory 216976 kb
Host smart-7f683ac3-749f-4521-8018-86d9137a085b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799418148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.799418148
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1417912869
Short name T42
Test name
Test status
Simulation time 102812291677 ps
CPU time 576.5 seconds
Started Jul 09 05:05:49 PM PDT 24
Finished Jul 09 05:15:32 PM PDT 24
Peak memory 234836 kb
Host smart-4d2890ef-cab5-4eb3-a14b-53e54bb4f789
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417912869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1417912869
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2618467155
Short name T339
Test name
Test status
Simulation time 1375281915 ps
CPU time 20.01 seconds
Started Jul 09 05:05:47 PM PDT 24
Finished Jul 09 05:06:12 PM PDT 24
Peak memory 219220 kb
Host smart-6c21d8e3-94e1-466e-b48a-33b5ebaf552f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618467155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2618467155
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1953453762
Short name T183
Test name
Test status
Simulation time 1199597493 ps
CPU time 17.88 seconds
Started Jul 09 05:05:49 PM PDT 24
Finished Jul 09 05:06:13 PM PDT 24
Peak memory 219316 kb
Host smart-716b44da-42a4-4d18-a740-f57b1487e4f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1953453762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1953453762
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.753611378
Short name T148
Test name
Test status
Simulation time 347168456 ps
CPU time 20.11 seconds
Started Jul 09 05:05:54 PM PDT 24
Finished Jul 09 05:06:21 PM PDT 24
Peak memory 215912 kb
Host smart-da21f135-b992-4b23-a81d-7f463067e074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753611378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.753611378
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.955798814
Short name T211
Test name
Test status
Simulation time 12736357025 ps
CPU time 40.16 seconds
Started Jul 09 05:05:46 PM PDT 24
Finished Jul 09 05:06:31 PM PDT 24
Peak memory 219272 kb
Host smart-c77ce299-e3c0-43a1-b147-963b295a5624
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955798814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.955798814
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.2604190175
Short name T51
Test name
Test status
Simulation time 127778786644 ps
CPU time 1235.6 seconds
Started Jul 09 05:05:53 PM PDT 24
Finished Jul 09 05:26:36 PM PDT 24
Peak memory 238136 kb
Host smart-6c2ea88c-2d10-487e-9f73-7f0089b921fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604190175 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.2604190175
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%