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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.19 96.89 91.85 97.68 100.00 98.28 97.30 98.37


Total test records in report: 459
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T301 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3856153077 Jul 10 05:07:37 PM PDT 24 Jul 10 05:08:13 PM PDT 24 4022157416 ps
T302 /workspace/coverage/default/27.rom_ctrl_stress_all.1510371242 Jul 10 05:07:40 PM PDT 24 Jul 10 05:08:54 PM PDT 24 2937098467 ps
T303 /workspace/coverage/default/2.rom_ctrl_alert_test.2737364196 Jul 10 05:06:51 PM PDT 24 Jul 10 05:07:16 PM PDT 24 4597093929 ps
T304 /workspace/coverage/default/41.rom_ctrl_alert_test.266989348 Jul 10 05:08:09 PM PDT 24 Jul 10 05:08:28 PM PDT 24 1475238740 ps
T305 /workspace/coverage/default/28.rom_ctrl_smoke.1511664768 Jul 10 05:07:45 PM PDT 24 Jul 10 05:08:43 PM PDT 24 7230116987 ps
T306 /workspace/coverage/default/40.rom_ctrl_alert_test.3098951608 Jul 10 05:08:07 PM PDT 24 Jul 10 05:08:32 PM PDT 24 2632119899 ps
T307 /workspace/coverage/default/14.rom_ctrl_alert_test.3317827719 Jul 10 05:07:14 PM PDT 24 Jul 10 05:07:45 PM PDT 24 3828001175 ps
T308 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1636098563 Jul 10 05:06:58 PM PDT 24 Jul 10 05:12:10 PM PDT 24 35878213330 ps
T309 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.4116432476 Jul 10 05:08:21 PM PDT 24 Jul 10 05:08:32 PM PDT 24 365437663 ps
T310 /workspace/coverage/default/36.rom_ctrl_stress_all.3698960452 Jul 10 05:07:54 PM PDT 24 Jul 10 05:09:41 PM PDT 24 8679468752 ps
T311 /workspace/coverage/default/14.rom_ctrl_smoke.1614258887 Jul 10 05:07:11 PM PDT 24 Jul 10 05:07:38 PM PDT 24 862112611 ps
T312 /workspace/coverage/default/48.rom_ctrl_alert_test.426147680 Jul 10 05:08:33 PM PDT 24 Jul 10 05:09:03 PM PDT 24 15941451019 ps
T313 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2570052499 Jul 10 05:07:29 PM PDT 24 Jul 10 05:08:35 PM PDT 24 31380983397 ps
T314 /workspace/coverage/default/48.rom_ctrl_stress_all.797241689 Jul 10 05:08:31 PM PDT 24 Jul 10 05:09:19 PM PDT 24 3425085496 ps
T315 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.452191578 Jul 10 05:07:04 PM PDT 24 Jul 10 05:07:48 PM PDT 24 14978489815 ps
T46 /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.2875160980 Jul 10 05:07:08 PM PDT 24 Jul 10 05:25:16 PM PDT 24 50769913891 ps
T316 /workspace/coverage/default/38.rom_ctrl_stress_all.3688787019 Jul 10 05:08:03 PM PDT 24 Jul 10 05:09:26 PM PDT 24 24872853452 ps
T317 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1181924359 Jul 10 05:07:27 PM PDT 24 Jul 10 05:07:59 PM PDT 24 6943344060 ps
T318 /workspace/coverage/default/7.rom_ctrl_smoke.397521818 Jul 10 05:06:57 PM PDT 24 Jul 10 05:07:59 PM PDT 24 13660789268 ps
T319 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.4130801665 Jul 10 05:07:05 PM PDT 24 Jul 10 05:07:31 PM PDT 24 2349676305 ps
T320 /workspace/coverage/default/47.rom_ctrl_smoke.1950312747 Jul 10 05:08:32 PM PDT 24 Jul 10 05:09:15 PM PDT 24 21157210584 ps
T321 /workspace/coverage/default/24.rom_ctrl_stress_all.2386175367 Jul 10 05:07:36 PM PDT 24 Jul 10 05:08:59 PM PDT 24 15841180193 ps
T322 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2932401533 Jul 10 05:06:42 PM PDT 24 Jul 10 05:07:13 PM PDT 24 3063229687 ps
T323 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3973303499 Jul 10 05:07:47 PM PDT 24 Jul 10 05:08:54 PM PDT 24 7902084834 ps
T324 /workspace/coverage/default/14.rom_ctrl_stress_all.3393756495 Jul 10 05:07:09 PM PDT 24 Jul 10 05:07:51 PM PDT 24 9295239875 ps
T325 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3854482051 Jul 10 05:06:52 PM PDT 24 Jul 10 05:07:42 PM PDT 24 4902976932 ps
T326 /workspace/coverage/default/5.rom_ctrl_stress_all.2887380719 Jul 10 05:06:52 PM PDT 24 Jul 10 05:08:15 PM PDT 24 4906885954 ps
T327 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.798253710 Jul 10 05:07:56 PM PDT 24 Jul 10 05:08:23 PM PDT 24 25674743220 ps
T328 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.4276687875 Jul 10 05:07:37 PM PDT 24 Jul 10 05:07:59 PM PDT 24 390843750 ps
T329 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.784286980 Jul 10 05:07:49 PM PDT 24 Jul 10 05:08:11 PM PDT 24 1571267222 ps
T330 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.621768821 Jul 10 05:07:57 PM PDT 24 Jul 10 05:08:08 PM PDT 24 1230499472 ps
T331 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.309346909 Jul 10 05:07:19 PM PDT 24 Jul 10 05:07:52 PM PDT 24 29663004498 ps
T332 /workspace/coverage/default/33.rom_ctrl_stress_all.2346638773 Jul 10 05:07:58 PM PDT 24 Jul 10 05:09:34 PM PDT 24 9806137812 ps
T333 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2338559440 Jul 10 05:07:51 PM PDT 24 Jul 10 05:08:02 PM PDT 24 288388269 ps
T334 /workspace/coverage/default/17.rom_ctrl_smoke.2768421047 Jul 10 05:07:18 PM PDT 24 Jul 10 05:07:39 PM PDT 24 1609924970 ps
T335 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.866981647 Jul 10 05:07:27 PM PDT 24 Jul 10 05:07:56 PM PDT 24 6352218293 ps
T336 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1058132054 Jul 10 05:07:42 PM PDT 24 Jul 10 05:08:11 PM PDT 24 7013462900 ps
T337 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3934180987 Jul 10 05:07:55 PM PDT 24 Jul 10 05:13:55 PM PDT 24 33435318019 ps
T338 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1417827295 Jul 10 05:06:57 PM PDT 24 Jul 10 05:07:10 PM PDT 24 185688443 ps
T339 /workspace/coverage/default/39.rom_ctrl_alert_test.3549309679 Jul 10 05:08:01 PM PDT 24 Jul 10 05:08:12 PM PDT 24 1031728174 ps
T340 /workspace/coverage/default/46.rom_ctrl_alert_test.3822137478 Jul 10 05:08:33 PM PDT 24 Jul 10 05:09:09 PM PDT 24 9829053586 ps
T341 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1003264848 Jul 10 05:07:49 PM PDT 24 Jul 10 05:08:23 PM PDT 24 1822419359 ps
T342 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3627494614 Jul 10 05:07:49 PM PDT 24 Jul 10 05:08:10 PM PDT 24 1738497466 ps
T343 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1262976615 Jul 10 05:08:29 PM PDT 24 Jul 10 05:13:05 PM PDT 24 4548960431 ps
T344 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2632362334 Jul 10 05:07:53 PM PDT 24 Jul 10 05:08:14 PM PDT 24 689939092 ps
T345 /workspace/coverage/default/12.rom_ctrl_alert_test.4242037249 Jul 10 05:07:03 PM PDT 24 Jul 10 05:07:14 PM PDT 24 516789372 ps
T346 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1552646761 Jul 10 05:07:35 PM PDT 24 Jul 10 05:22:25 PM PDT 24 85355084850 ps
T347 /workspace/coverage/default/27.rom_ctrl_alert_test.1164028874 Jul 10 05:07:47 PM PDT 24 Jul 10 05:08:10 PM PDT 24 4183842878 ps
T348 /workspace/coverage/default/9.rom_ctrl_stress_all.1045444360 Jul 10 05:06:57 PM PDT 24 Jul 10 05:08:38 PM PDT 24 16038805260 ps
T349 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1761099446 Jul 10 05:07:19 PM PDT 24 Jul 10 05:08:18 PM PDT 24 29108285669 ps
T350 /workspace/coverage/default/18.rom_ctrl_stress_all.3967810 Jul 10 05:07:28 PM PDT 24 Jul 10 05:07:51 PM PDT 24 1515680761 ps
T351 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3766803883 Jul 10 05:07:38 PM PDT 24 Jul 10 05:12:57 PM PDT 24 38645940663 ps
T352 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2006239033 Jul 10 05:07:45 PM PDT 24 Jul 10 05:15:59 PM PDT 24 48222736018 ps
T353 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2815528510 Jul 10 05:08:32 PM PDT 24 Jul 10 05:08:59 PM PDT 24 3422638479 ps
T354 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1422734602 Jul 10 05:06:44 PM PDT 24 Jul 10 05:07:19 PM PDT 24 4019162613 ps
T355 /workspace/coverage/default/33.rom_ctrl_alert_test.2414874748 Jul 10 05:07:57 PM PDT 24 Jul 10 05:08:07 PM PDT 24 689655430 ps
T356 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.4094510100 Jul 10 05:07:47 PM PDT 24 Jul 10 05:19:50 PM PDT 24 274892446370 ps
T357 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.538671311 Jul 10 05:07:38 PM PDT 24 Jul 10 05:08:29 PM PDT 24 28746807954 ps
T358 /workspace/coverage/default/38.rom_ctrl_alert_test.3350280654 Jul 10 05:08:02 PM PDT 24 Jul 10 05:08:25 PM PDT 24 2135742540 ps
T359 /workspace/coverage/default/32.rom_ctrl_alert_test.357849960 Jul 10 05:07:47 PM PDT 24 Jul 10 05:08:17 PM PDT 24 3187710432 ps
T360 /workspace/coverage/default/21.rom_ctrl_stress_all.4007861812 Jul 10 05:07:28 PM PDT 24 Jul 10 05:09:57 PM PDT 24 79475087711 ps
T361 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2651160827 Jul 10 05:07:12 PM PDT 24 Jul 10 05:07:23 PM PDT 24 646519594 ps
T362 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2217858664 Jul 10 05:06:52 PM PDT 24 Jul 10 05:09:34 PM PDT 24 5752738737 ps
T363 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.4254069831 Jul 10 05:07:04 PM PDT 24 Jul 10 05:07:16 PM PDT 24 3504924666 ps
T47 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.586151223 Jul 10 05:06:30 PM PDT 24 Jul 10 05:07:05 PM PDT 24 3320420578 ps
T51 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2365436723 Jul 10 05:06:22 PM PDT 24 Jul 10 05:08:37 PM PDT 24 24266866272 ps
T52 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3715156973 Jul 10 05:06:28 PM PDT 24 Jul 10 05:06:51 PM PDT 24 3777759618 ps
T364 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3712589855 Jul 10 05:06:15 PM PDT 24 Jul 10 05:06:30 PM PDT 24 691610518 ps
T365 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.940376745 Jul 10 05:06:36 PM PDT 24 Jul 10 05:07:03 PM PDT 24 9212480993 ps
T90 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.877138571 Jul 10 05:06:14 PM PDT 24 Jul 10 05:06:36 PM PDT 24 3371247159 ps
T59 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1835067203 Jul 10 05:06:30 PM PDT 24 Jul 10 05:08:45 PM PDT 24 30229334712 ps
T91 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1296590055 Jul 10 05:06:31 PM PDT 24 Jul 10 05:10:02 PM PDT 24 185520714679 ps
T48 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1437512626 Jul 10 05:06:18 PM PDT 24 Jul 10 05:09:00 PM PDT 24 1135053789 ps
T92 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3216953831 Jul 10 05:06:36 PM PDT 24 Jul 10 05:07:07 PM PDT 24 3058405257 ps
T49 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2194285614 Jul 10 05:06:38 PM PDT 24 Jul 10 05:09:16 PM PDT 24 618087947 ps
T60 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2216704094 Jul 10 05:06:15 PM PDT 24 Jul 10 05:06:38 PM PDT 24 2455270120 ps
T366 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3863670846 Jul 10 05:06:14 PM PDT 24 Jul 10 05:06:34 PM PDT 24 169179041 ps
T367 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2964469883 Jul 10 05:06:36 PM PDT 24 Jul 10 05:06:57 PM PDT 24 538555815 ps
T83 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1365317591 Jul 10 05:06:25 PM PDT 24 Jul 10 05:07:02 PM PDT 24 3716871439 ps
T50 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.57019534 Jul 10 05:06:33 PM PDT 24 Jul 10 05:08:18 PM PDT 24 15269846271 ps
T93 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3946475516 Jul 10 05:06:26 PM PDT 24 Jul 10 05:07:05 PM PDT 24 9816050629 ps
T368 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1042138749 Jul 10 05:06:27 PM PDT 24 Jul 10 05:07:06 PM PDT 24 3140034125 ps
T94 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3405108349 Jul 10 05:06:16 PM PDT 24 Jul 10 05:07:18 PM PDT 24 5952236436 ps
T61 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2547671312 Jul 10 05:06:10 PM PDT 24 Jul 10 05:06:48 PM PDT 24 5376377827 ps
T369 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3711837339 Jul 10 05:06:15 PM PDT 24 Jul 10 05:06:49 PM PDT 24 5498295899 ps
T84 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.564667154 Jul 10 05:06:36 PM PDT 24 Jul 10 05:07:02 PM PDT 24 21036498052 ps
T370 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3414417764 Jul 10 05:06:41 PM PDT 24 Jul 10 05:06:53 PM PDT 24 174466198 ps
T85 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3451825010 Jul 10 05:06:24 PM PDT 24 Jul 10 05:06:45 PM PDT 24 708193408 ps
T371 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.633089440 Jul 10 05:06:27 PM PDT 24 Jul 10 05:06:59 PM PDT 24 6917881206 ps
T102 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1769126716 Jul 10 05:06:23 PM PDT 24 Jul 10 05:09:07 PM PDT 24 3773425893 ps
T103 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2505306335 Jul 10 05:06:22 PM PDT 24 Jul 10 05:09:06 PM PDT 24 1817472141 ps
T62 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1165786006 Jul 10 05:06:15 PM PDT 24 Jul 10 05:08:19 PM PDT 24 19337355818 ps
T372 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.92647433 Jul 10 05:06:15 PM PDT 24 Jul 10 05:06:30 PM PDT 24 339138437 ps
T373 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3148871129 Jul 10 05:06:21 PM PDT 24 Jul 10 05:06:52 PM PDT 24 25603506235 ps
T63 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2050752236 Jul 10 05:06:13 PM PDT 24 Jul 10 05:09:03 PM PDT 24 18972738313 ps
T374 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2044787819 Jul 10 05:06:23 PM PDT 24 Jul 10 05:06:49 PM PDT 24 1502259024 ps
T64 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2445198072 Jul 10 05:06:25 PM PDT 24 Jul 10 05:08:11 PM PDT 24 10251353163 ps
T375 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3597323951 Jul 10 05:06:19 PM PDT 24 Jul 10 05:06:35 PM PDT 24 612000988 ps
T376 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2039450933 Jul 10 05:06:16 PM PDT 24 Jul 10 05:06:35 PM PDT 24 349681526 ps
T65 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1876058335 Jul 10 05:06:14 PM PDT 24 Jul 10 05:07:57 PM PDT 24 39183836416 ps
T377 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1031753090 Jul 10 05:06:29 PM PDT 24 Jul 10 05:07:09 PM PDT 24 3756554873 ps
T86 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2134676619 Jul 10 05:06:19 PM PDT 24 Jul 10 05:06:56 PM PDT 24 15003510208 ps
T66 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1364552245 Jul 10 05:06:25 PM PDT 24 Jul 10 05:06:53 PM PDT 24 7556722108 ps
T378 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.225713720 Jul 10 05:06:15 PM PDT 24 Jul 10 05:06:42 PM PDT 24 2134924562 ps
T379 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.197622158 Jul 10 05:06:24 PM PDT 24 Jul 10 05:07:02 PM PDT 24 7432732960 ps
T105 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4095124725 Jul 10 05:06:22 PM PDT 24 Jul 10 05:09:27 PM PDT 24 5720706664 ps
T67 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2999436154 Jul 10 05:06:43 PM PDT 24 Jul 10 05:07:00 PM PDT 24 1674811620 ps
T380 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.344580180 Jul 10 05:06:25 PM PDT 24 Jul 10 05:06:42 PM PDT 24 725525597 ps
T381 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3227481757 Jul 10 05:06:22 PM PDT 24 Jul 10 05:06:52 PM PDT 24 2749763741 ps
T382 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3065648993 Jul 10 05:06:19 PM PDT 24 Jul 10 05:06:56 PM PDT 24 15501718384 ps
T383 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2182912614 Jul 10 05:06:15 PM PDT 24 Jul 10 05:06:49 PM PDT 24 3346887442 ps
T384 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1980706267 Jul 10 05:06:28 PM PDT 24 Jul 10 05:06:45 PM PDT 24 1373360422 ps
T87 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2013944945 Jul 10 05:06:15 PM PDT 24 Jul 10 05:06:45 PM PDT 24 2699631274 ps
T68 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2827854987 Jul 10 05:06:17 PM PDT 24 Jul 10 05:06:52 PM PDT 24 41056890225 ps
T385 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1301406768 Jul 10 05:06:30 PM PDT 24 Jul 10 05:06:46 PM PDT 24 167390531 ps
T88 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2214465329 Jul 10 05:06:38 PM PDT 24 Jul 10 05:07:15 PM PDT 24 8889961953 ps
T89 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.726405569 Jul 10 05:06:31 PM PDT 24 Jul 10 05:07:00 PM PDT 24 4977921170 ps
T386 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3485812155 Jul 10 05:06:24 PM PDT 24 Jul 10 05:07:47 PM PDT 24 2700293301 ps
T387 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.4226828623 Jul 10 05:06:31 PM PDT 24 Jul 10 05:06:58 PM PDT 24 1851732828 ps
T388 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2908666857 Jul 10 05:06:09 PM PDT 24 Jul 10 05:06:41 PM PDT 24 3041570585 ps
T389 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3225882014 Jul 10 05:06:22 PM PDT 24 Jul 10 05:06:38 PM PDT 24 338877356 ps
T106 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2183657211 Jul 10 05:06:29 PM PDT 24 Jul 10 05:08:13 PM PDT 24 5883344289 ps
T390 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.691019518 Jul 10 05:06:31 PM PDT 24 Jul 10 05:08:01 PM PDT 24 1721750798 ps
T75 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.861173184 Jul 10 05:06:14 PM PDT 24 Jul 10 05:06:50 PM PDT 24 68407879071 ps
T391 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1153947636 Jul 10 05:06:21 PM PDT 24 Jul 10 05:06:43 PM PDT 24 4112231626 ps
T76 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.629644554 Jul 10 05:06:35 PM PDT 24 Jul 10 05:07:01 PM PDT 24 1989410500 ps
T392 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3575808645 Jul 10 05:06:34 PM PDT 24 Jul 10 05:08:59 PM PDT 24 69932436566 ps
T77 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.997635465 Jul 10 05:06:39 PM PDT 24 Jul 10 05:07:46 PM PDT 24 15152174600 ps
T393 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.543176226 Jul 10 05:06:22 PM PDT 24 Jul 10 05:07:04 PM PDT 24 4103269747 ps
T394 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3093881548 Jul 10 05:06:13 PM PDT 24 Jul 10 05:06:32 PM PDT 24 890842544 ps
T395 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2076998500 Jul 10 05:06:24 PM PDT 24 Jul 10 05:06:46 PM PDT 24 605509446 ps
T396 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1856577124 Jul 10 05:06:24 PM PDT 24 Jul 10 05:07:10 PM PDT 24 2763727568 ps
T397 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.802289005 Jul 10 05:06:34 PM PDT 24 Jul 10 05:06:59 PM PDT 24 5140608774 ps
T398 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1989824248 Jul 10 05:06:23 PM PDT 24 Jul 10 05:06:39 PM PDT 24 689142653 ps
T399 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.616975919 Jul 10 05:06:31 PM PDT 24 Jul 10 05:07:00 PM PDT 24 6059533931 ps
T400 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1390164618 Jul 10 05:06:28 PM PDT 24 Jul 10 05:06:46 PM PDT 24 1032614910 ps
T401 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.142478818 Jul 10 05:06:29 PM PDT 24 Jul 10 05:06:54 PM PDT 24 3583036694 ps
T402 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3875889880 Jul 10 05:06:10 PM PDT 24 Jul 10 05:06:44 PM PDT 24 6784653819 ps
T403 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1082148792 Jul 10 05:06:29 PM PDT 24 Jul 10 05:06:50 PM PDT 24 7273249563 ps
T404 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.519294058 Jul 10 05:06:39 PM PDT 24 Jul 10 05:07:13 PM PDT 24 11264309690 ps
T112 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2528105344 Jul 10 05:06:22 PM PDT 24 Jul 10 05:09:21 PM PDT 24 4263025041 ps
T79 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.744766238 Jul 10 05:06:24 PM PDT 24 Jul 10 05:06:48 PM PDT 24 1109710673 ps
T405 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3662443864 Jul 10 05:06:36 PM PDT 24 Jul 10 05:07:14 PM PDT 24 4043883759 ps
T406 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2860797969 Jul 10 05:06:26 PM PDT 24 Jul 10 05:06:58 PM PDT 24 29598231191 ps
T407 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2644911877 Jul 10 05:06:23 PM PDT 24 Jul 10 05:06:51 PM PDT 24 3727323220 ps
T408 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1129822465 Jul 10 05:06:30 PM PDT 24 Jul 10 05:06:50 PM PDT 24 532367020 ps
T409 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3194681159 Jul 10 05:06:23 PM PDT 24 Jul 10 05:06:48 PM PDT 24 591617779 ps
T410 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3198334542 Jul 10 05:06:30 PM PDT 24 Jul 10 05:06:49 PM PDT 24 348540213 ps
T411 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1888917514 Jul 10 05:06:18 PM PDT 24 Jul 10 05:06:45 PM PDT 24 2760281801 ps
T78 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.181317425 Jul 10 05:06:29 PM PDT 24 Jul 10 05:06:56 PM PDT 24 7530392104 ps
T412 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1073233569 Jul 10 05:06:19 PM PDT 24 Jul 10 05:06:53 PM PDT 24 3173065927 ps
T413 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2130429004 Jul 10 05:06:17 PM PDT 24 Jul 10 05:06:53 PM PDT 24 4927923920 ps
T414 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1564938639 Jul 10 05:06:22 PM PDT 24 Jul 10 05:07:00 PM PDT 24 17904886572 ps
T107 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3151427060 Jul 10 05:06:24 PM PDT 24 Jul 10 05:09:13 PM PDT 24 855112036 ps
T415 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2062340144 Jul 10 05:06:29 PM PDT 24 Jul 10 05:07:03 PM PDT 24 9737310559 ps
T416 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.342739355 Jul 10 05:06:26 PM PDT 24 Jul 10 05:06:59 PM PDT 24 11660648991 ps
T417 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2047976278 Jul 10 05:06:22 PM PDT 24 Jul 10 05:08:09 PM PDT 24 18924351971 ps
T418 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3616399899 Jul 10 05:06:11 PM PDT 24 Jul 10 05:06:52 PM PDT 24 41637640929 ps
T113 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.236357291 Jul 10 05:06:22 PM PDT 24 Jul 10 05:08:09 PM PDT 24 11808062809 ps
T419 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.159280575 Jul 10 05:06:37 PM PDT 24 Jul 10 05:07:11 PM PDT 24 10831177836 ps
T420 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1901376618 Jul 10 05:06:36 PM PDT 24 Jul 10 05:07:02 PM PDT 24 1961979102 ps
T104 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1976390516 Jul 10 05:06:28 PM PDT 24 Jul 10 05:09:11 PM PDT 24 397652386 ps
T421 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.4217817984 Jul 10 05:06:23 PM PDT 24 Jul 10 05:07:05 PM PDT 24 3539721427 ps
T110 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1979837836 Jul 10 05:06:18 PM PDT 24 Jul 10 05:07:49 PM PDT 24 433422384 ps
T80 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2417818522 Jul 10 05:06:39 PM PDT 24 Jul 10 05:10:02 PM PDT 24 23368629516 ps
T422 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3063485565 Jul 10 05:06:30 PM PDT 24 Jul 10 05:07:57 PM PDT 24 3640098440 ps
T423 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.151396671 Jul 10 05:06:37 PM PDT 24 Jul 10 05:07:11 PM PDT 24 35305870717 ps
T81 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.776533896 Jul 10 05:06:26 PM PDT 24 Jul 10 05:07:02 PM PDT 24 6730773746 ps
T424 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3456674667 Jul 10 05:06:15 PM PDT 24 Jul 10 05:06:42 PM PDT 24 3764570352 ps
T425 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1638928733 Jul 10 05:06:16 PM PDT 24 Jul 10 05:06:31 PM PDT 24 203474994 ps
T114 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3026347550 Jul 10 05:06:26 PM PDT 24 Jul 10 05:08:04 PM PDT 24 6603719368 ps
T426 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3473014646 Jul 10 05:06:15 PM PDT 24 Jul 10 05:06:47 PM PDT 24 26194639503 ps
T427 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.683550724 Jul 10 05:06:15 PM PDT 24 Jul 10 05:06:29 PM PDT 24 170711954 ps
T428 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2518511016 Jul 10 05:06:16 PM PDT 24 Jul 10 05:06:54 PM PDT 24 4433221293 ps
T429 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1368455981 Jul 10 05:06:28 PM PDT 24 Jul 10 05:06:54 PM PDT 24 5979296478 ps
T430 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.436410941 Jul 10 05:06:14 PM PDT 24 Jul 10 05:06:48 PM PDT 24 14238562471 ps
T431 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4174142447 Jul 10 05:06:37 PM PDT 24 Jul 10 05:07:02 PM PDT 24 7238937610 ps
T432 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.125925372 Jul 10 05:06:37 PM PDT 24 Jul 10 05:09:32 PM PDT 24 93722073482 ps
T433 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.424253339 Jul 10 05:06:24 PM PDT 24 Jul 10 05:07:54 PM PDT 24 82066136448 ps
T434 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3900634002 Jul 10 05:06:15 PM PDT 24 Jul 10 05:06:45 PM PDT 24 3354791286 ps
T108 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2609484150 Jul 10 05:06:31 PM PDT 24 Jul 10 05:09:31 PM PDT 24 4282505812 ps
T111 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2509535901 Jul 10 05:06:22 PM PDT 24 Jul 10 05:09:09 PM PDT 24 4896165846 ps
T435 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1998481712 Jul 10 05:06:23 PM PDT 24 Jul 10 05:08:21 PM PDT 24 12998074296 ps
T109 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1566639434 Jul 10 05:06:37 PM PDT 24 Jul 10 05:09:23 PM PDT 24 8372154174 ps
T436 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1784239805 Jul 10 05:06:18 PM PDT 24 Jul 10 05:07:43 PM PDT 24 12015220555 ps
T82 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3696511254 Jul 10 05:06:15 PM PDT 24 Jul 10 05:06:30 PM PDT 24 211572528 ps
T437 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.928713040 Jul 10 05:06:14 PM PDT 24 Jul 10 05:06:45 PM PDT 24 5562286888 ps
T438 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.914097758 Jul 10 05:06:16 PM PDT 24 Jul 10 05:06:55 PM PDT 24 3950722620 ps
T439 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4194458823 Jul 10 05:06:10 PM PDT 24 Jul 10 05:06:28 PM PDT 24 3076393359 ps
T440 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1618115002 Jul 10 05:06:22 PM PDT 24 Jul 10 05:06:58 PM PDT 24 10724818541 ps
T441 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1425356923 Jul 10 05:06:13 PM PDT 24 Jul 10 05:07:43 PM PDT 24 400751013 ps
T442 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2828416301 Jul 10 05:06:29 PM PDT 24 Jul 10 05:09:15 PM PDT 24 513537567 ps
T443 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2467797885 Jul 10 05:06:16 PM PDT 24 Jul 10 05:06:52 PM PDT 24 40486764993 ps
T444 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2885257426 Jul 10 05:06:37 PM PDT 24 Jul 10 05:06:54 PM PDT 24 836914728 ps
T445 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.224330344 Jul 10 05:06:14 PM PDT 24 Jul 10 05:06:48 PM PDT 24 2619714591 ps
T446 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4127954784 Jul 10 05:06:24 PM PDT 24 Jul 10 05:07:07 PM PDT 24 3496466032 ps
T447 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.140009618 Jul 10 05:06:26 PM PDT 24 Jul 10 05:06:48 PM PDT 24 176482117 ps
T448 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1675762173 Jul 10 05:06:21 PM PDT 24 Jul 10 05:06:41 PM PDT 24 2392117484 ps
T449 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1636987653 Jul 10 05:06:22 PM PDT 24 Jul 10 05:06:50 PM PDT 24 3841567504 ps
T450 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4149810786 Jul 10 05:06:29 PM PDT 24 Jul 10 05:08:46 PM PDT 24 61667668617 ps
T451 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.491225350 Jul 10 05:06:24 PM PDT 24 Jul 10 05:07:02 PM PDT 24 11946625140 ps
T452 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4052278567 Jul 10 05:06:17 PM PDT 24 Jul 10 05:06:44 PM PDT 24 7235000525 ps
T453 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3554318917 Jul 10 05:06:24 PM PDT 24 Jul 10 05:06:47 PM PDT 24 3619941139 ps
T454 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1261765966 Jul 10 05:06:17 PM PDT 24 Jul 10 05:06:36 PM PDT 24 760952363 ps
T455 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3138634223 Jul 10 05:06:42 PM PDT 24 Jul 10 05:06:59 PM PDT 24 971117225 ps
T456 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.767053142 Jul 10 05:06:35 PM PDT 24 Jul 10 05:06:50 PM PDT 24 697027524 ps
T457 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.633270784 Jul 10 05:06:36 PM PDT 24 Jul 10 05:07:05 PM PDT 24 29895344351 ps
T458 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1935809443 Jul 10 05:06:37 PM PDT 24 Jul 10 05:08:05 PM PDT 24 932286189 ps
T459 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1636369713 Jul 10 05:06:14 PM PDT 24 Jul 10 05:06:44 PM PDT 24 2605956067 ps

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.3541504380
Short name T3
Test name
Test status
Simulation time 39448598264 ps
CPU time 758.81 seconds
Started Jul 10 05:08:33 PM PDT 24
Finished Jul 10 05:21:14 PM PDT 24
Peak memory 230704 kb
Host smart-6557c285-00fa-41c3-99dd-b4fc4f2825ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541504380 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.3541504380
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3217107521
Short name T1
Test name
Test status
Simulation time 142783961258 ps
CPU time 579.87 seconds
Started Jul 10 05:07:29 PM PDT 24
Finished Jul 10 05:17:10 PM PDT 24
Peak memory 229800 kb
Host smart-eb2eb68c-f119-42e6-8b5b-dadcb54292ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217107521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3217107521
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2953140219
Short name T274
Test name
Test status
Simulation time 33079798864 ps
CPU time 571.44 seconds
Started Jul 10 05:08:00 PM PDT 24
Finished Jul 10 05:17:33 PM PDT 24
Peak memory 229252 kb
Host smart-ca032b32-2673-47a3-ac47-684c9dabc51d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953140219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2953140219
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1437512626
Short name T48
Test name
Test status
Simulation time 1135053789 ps
CPU time 155.84 seconds
Started Jul 10 05:06:18 PM PDT 24
Finished Jul 10 05:09:00 PM PDT 24
Peak memory 213992 kb
Host smart-69788e57-5d3d-44d9-8507-ddd49e9d3afd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437512626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1437512626
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.123214000
Short name T4
Test name
Test status
Simulation time 511967960 ps
CPU time 116.52 seconds
Started Jul 10 05:06:50 PM PDT 24
Finished Jul 10 05:08:49 PM PDT 24
Peak memory 235700 kb
Host smart-d0490523-1868-448e-8358-9089745b327d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123214000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.123214000
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3611668738
Short name T15
Test name
Test status
Simulation time 8526650720 ps
CPU time 47.22 seconds
Started Jul 10 05:07:46 PM PDT 24
Finished Jul 10 05:08:36 PM PDT 24
Peak memory 217612 kb
Host smart-2dcf43fb-8e43-4d56-b2f6-5c36850e2ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611668738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3611668738
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1876058335
Short name T65
Test name
Test status
Simulation time 39183836416 ps
CPU time 97.8 seconds
Started Jul 10 05:06:14 PM PDT 24
Finished Jul 10 05:07:57 PM PDT 24
Peak memory 213812 kb
Host smart-b9a46044-fa4e-484a-be5e-f16633ebb272
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876058335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1876058335
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3141690989
Short name T30
Test name
Test status
Simulation time 68266795956 ps
CPU time 520.22 seconds
Started Jul 10 05:06:51 PM PDT 24
Finished Jul 10 05:15:34 PM PDT 24
Peak memory 226644 kb
Host smart-8fc1f94c-59d1-4101-a717-4958160c484e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141690989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3141690989
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.131090274
Short name T73
Test name
Test status
Simulation time 371370099 ps
CPU time 28.27 seconds
Started Jul 10 05:06:45 PM PDT 24
Finished Jul 10 05:07:17 PM PDT 24
Peak memory 219344 kb
Host smart-7fb1f79d-227f-40bf-aa28-ff19c18d24f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131090274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.131090274
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3151427060
Short name T107
Test name
Test status
Simulation time 855112036 ps
CPU time 160.45 seconds
Started Jul 10 05:06:24 PM PDT 24
Finished Jul 10 05:09:13 PM PDT 24
Peak memory 213644 kb
Host smart-29b5eb04-68c9-4e22-949d-6998c87c9b9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151427060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3151427060
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1541298523
Short name T56
Test name
Test status
Simulation time 473175864 ps
CPU time 8.56 seconds
Started Jul 10 05:06:44 PM PDT 24
Finished Jul 10 05:06:56 PM PDT 24
Peak memory 217192 kb
Host smart-86f88064-3991-4bb4-a9f2-ecbbab9c9282
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541298523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1541298523
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.440995516
Short name T190
Test name
Test status
Simulation time 6528568335 ps
CPU time 56.35 seconds
Started Jul 10 05:07:05 PM PDT 24
Finished Jul 10 05:08:03 PM PDT 24
Peak memory 218896 kb
Host smart-6202c9d4-d8de-46c1-83ec-f482b54b535f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440995516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.440995516
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1913138752
Short name T254
Test name
Test status
Simulation time 333134850 ps
CPU time 19.57 seconds
Started Jul 10 05:07:05 PM PDT 24
Finished Jul 10 05:07:26 PM PDT 24
Peak memory 218800 kb
Host smart-e9b3f325-890f-45ed-a8d5-c4c19855c786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913138752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1913138752
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.57019534
Short name T50
Test name
Test status
Simulation time 15269846271 ps
CPU time 98.56 seconds
Started Jul 10 05:06:33 PM PDT 24
Finished Jul 10 05:08:18 PM PDT 24
Peak memory 213480 kb
Host smart-98de86b3-ae79-4825-9dc9-aa1d27f5aed6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57019534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_int
g_err.57019534
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1296590055
Short name T91
Test name
Test status
Simulation time 185520714679 ps
CPU time 203.75 seconds
Started Jul 10 05:06:31 PM PDT 24
Finished Jul 10 05:10:02 PM PDT 24
Peak memory 215000 kb
Host smart-a3760c08-a066-4992-a28a-b2c04e260e74
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296590055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1296590055
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3585890583
Short name T31
Test name
Test status
Simulation time 158383546184 ps
CPU time 587.09 seconds
Started Jul 10 05:07:03 PM PDT 24
Finished Jul 10 05:16:51 PM PDT 24
Peak memory 225752 kb
Host smart-ec0e26bb-267f-45e2-8a7d-95fd3b6366a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585890583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3585890583
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3026347550
Short name T114
Test name
Test status
Simulation time 6603719368 ps
CPU time 89.95 seconds
Started Jul 10 05:06:26 PM PDT 24
Finished Jul 10 05:08:04 PM PDT 24
Peak memory 213484 kb
Host smart-cf179edd-e9a2-436c-96b9-b0b2f9d27d4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026347550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3026347550
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1566639434
Short name T109
Test name
Test status
Simulation time 8372154174 ps
CPU time 159.92 seconds
Started Jul 10 05:06:37 PM PDT 24
Finished Jul 10 05:09:23 PM PDT 24
Peak memory 214260 kb
Host smart-dd96063c-2bd0-48f0-a409-2d07b10e10df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566639434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1566639434
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2505306335
Short name T103
Test name
Test status
Simulation time 1817472141 ps
CPU time 156.17 seconds
Started Jul 10 05:06:22 PM PDT 24
Finished Jul 10 05:09:06 PM PDT 24
Peak memory 218844 kb
Host smart-2188cf35-15d8-45bb-8e6a-c647aae2a9dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505306335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2505306335
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1638928733
Short name T425
Test name
Test status
Simulation time 203474994 ps
CPU time 8.28 seconds
Started Jul 10 05:06:16 PM PDT 24
Finished Jul 10 05:06:31 PM PDT 24
Peak memory 210708 kb
Host smart-54424c1c-715c-4c11-a64b-888c0b966537
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638928733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1638928733
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.914097758
Short name T438
Test name
Test status
Simulation time 3950722620 ps
CPU time 32.41 seconds
Started Jul 10 05:06:16 PM PDT 24
Finished Jul 10 05:06:55 PM PDT 24
Peak memory 211364 kb
Host smart-fb19b207-6dec-4a22-805e-e6c7ea4031ec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914097758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.914097758
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2547671312
Short name T61
Test name
Test status
Simulation time 5376377827 ps
CPU time 32.4 seconds
Started Jul 10 05:06:10 PM PDT 24
Finished Jul 10 05:06:48 PM PDT 24
Peak memory 211864 kb
Host smart-3f0c7794-843f-465c-92ad-0935ef48a67d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547671312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2547671312
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3712589855
Short name T364
Test name
Test status
Simulation time 691610518 ps
CPU time 8.96 seconds
Started Jul 10 05:06:15 PM PDT 24
Finished Jul 10 05:06:30 PM PDT 24
Peak memory 217312 kb
Host smart-aeb7c891-49f4-4bfa-8d62-a942645287e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712589855 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3712589855
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3875889880
Short name T402
Test name
Test status
Simulation time 6784653819 ps
CPU time 28.93 seconds
Started Jul 10 05:06:10 PM PDT 24
Finished Jul 10 05:06:44 PM PDT 24
Peak memory 212340 kb
Host smart-6bc222e2-015c-4c53-9d5d-de83c376abfd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875889880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3875889880
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4194458823
Short name T439
Test name
Test status
Simulation time 3076393359 ps
CPU time 12.06 seconds
Started Jul 10 05:06:10 PM PDT 24
Finished Jul 10 05:06:28 PM PDT 24
Peak memory 210548 kb
Host smart-3953a5d1-7919-4ee6-afcd-d112559de395
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194458823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.4194458823
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2908666857
Short name T388
Test name
Test status
Simulation time 3041570585 ps
CPU time 26.36 seconds
Started Jul 10 05:06:09 PM PDT 24
Finished Jul 10 05:06:41 PM PDT 24
Peak memory 210544 kb
Host smart-862eae9a-58d0-4cfc-8e1a-f3befb6def7f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908666857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2908666857
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2050752236
Short name T63
Test name
Test status
Simulation time 18972738313 ps
CPU time 164.16 seconds
Started Jul 10 05:06:13 PM PDT 24
Finished Jul 10 05:09:03 PM PDT 24
Peak memory 214884 kb
Host smart-28d598fd-5ca0-4de7-b769-0c33575c8a07
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050752236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2050752236
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2013944945
Short name T87
Test name
Test status
Simulation time 2699631274 ps
CPU time 23.77 seconds
Started Jul 10 05:06:15 PM PDT 24
Finished Jul 10 05:06:45 PM PDT 24
Peak memory 211828 kb
Host smart-b725b98c-3cea-42ba-8a59-8d6a8d9b782f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013944945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2013944945
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3616399899
Short name T418
Test name
Test status
Simulation time 41637640929 ps
CPU time 35.52 seconds
Started Jul 10 05:06:11 PM PDT 24
Finished Jul 10 05:06:52 PM PDT 24
Peak memory 218556 kb
Host smart-db8f55bf-d7db-4ee7-a47c-09d2b732ba57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616399899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3616399899
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1425356923
Short name T441
Test name
Test status
Simulation time 400751013 ps
CPU time 84 seconds
Started Jul 10 05:06:13 PM PDT 24
Finished Jul 10 05:07:43 PM PDT 24
Peak memory 213780 kb
Host smart-82245f00-fc69-4baf-8e2a-2830a703575b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425356923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1425356923
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2216704094
Short name T60
Test name
Test status
Simulation time 2455270120 ps
CPU time 16.39 seconds
Started Jul 10 05:06:15 PM PDT 24
Finished Jul 10 05:06:38 PM PDT 24
Peak memory 211368 kb
Host smart-f18d257c-fcf6-45cc-ba25-21e8f49bcb5c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216704094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2216704094
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3597323951
Short name T375
Test name
Test status
Simulation time 612000988 ps
CPU time 8.26 seconds
Started Jul 10 05:06:19 PM PDT 24
Finished Jul 10 05:06:35 PM PDT 24
Peak memory 210616 kb
Host smart-5f74619b-12ed-458a-aa2d-11c6947fecd9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597323951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3597323951
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1888917514
Short name T411
Test name
Test status
Simulation time 2760281801 ps
CPU time 19.49 seconds
Started Jul 10 05:06:18 PM PDT 24
Finished Jul 10 05:06:45 PM PDT 24
Peak memory 211964 kb
Host smart-0974c5c9-cb46-4239-a059-d2de45c052f0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888917514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1888917514
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3093881548
Short name T394
Test name
Test status
Simulation time 890842544 ps
CPU time 12.82 seconds
Started Jul 10 05:06:13 PM PDT 24
Finished Jul 10 05:06:32 PM PDT 24
Peak memory 215740 kb
Host smart-5e240f18-0a40-485a-98e0-108b3d81b841
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093881548 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3093881548
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1636369713
Short name T459
Test name
Test status
Simulation time 2605956067 ps
CPU time 23.47 seconds
Started Jul 10 05:06:14 PM PDT 24
Finished Jul 10 05:06:44 PM PDT 24
Peak memory 211624 kb
Host smart-10756d7f-75b1-4e01-a6f9-e3c7fc8fc3e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636369713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1636369713
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.928713040
Short name T437
Test name
Test status
Simulation time 5562286888 ps
CPU time 24.32 seconds
Started Jul 10 05:06:14 PM PDT 24
Finished Jul 10 05:06:45 PM PDT 24
Peak memory 210548 kb
Host smart-ac76f21b-7d5f-4a68-a494-8a133f2e9a63
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928713040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.928713040
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.92647433
Short name T372
Test name
Test status
Simulation time 339138437 ps
CPU time 8.2 seconds
Started Jul 10 05:06:15 PM PDT 24
Finished Jul 10 05:06:30 PM PDT 24
Peak memory 210480 kb
Host smart-e4a2a7a8-4225-41dd-83ea-97fd27d3401e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92647433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.92647433
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.543176226
Short name T393
Test name
Test status
Simulation time 4103269747 ps
CPU time 34.69 seconds
Started Jul 10 05:06:22 PM PDT 24
Finished Jul 10 05:07:04 PM PDT 24
Peak memory 212332 kb
Host smart-8edf6564-a4e9-4845-8c3b-0e0c4507038b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543176226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.543176226
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3863670846
Short name T366
Test name
Test status
Simulation time 169179041 ps
CPU time 12.93 seconds
Started Jul 10 05:06:14 PM PDT 24
Finished Jul 10 05:06:34 PM PDT 24
Peak memory 217320 kb
Host smart-95f38c0c-a788-4d19-98a7-68b67df55dd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863670846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3863670846
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2509535901
Short name T111
Test name
Test status
Simulation time 4896165846 ps
CPU time 160.14 seconds
Started Jul 10 05:06:22 PM PDT 24
Finished Jul 10 05:09:09 PM PDT 24
Peak memory 212864 kb
Host smart-bb910e2c-63df-4760-a9a9-a736ae59077f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509535901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2509535901
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2644911877
Short name T407
Test name
Test status
Simulation time 3727323220 ps
CPU time 19.84 seconds
Started Jul 10 05:06:23 PM PDT 24
Finished Jul 10 05:06:51 PM PDT 24
Peak memory 216732 kb
Host smart-11c1d828-ec91-4d22-a7fb-200e76504899
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644911877 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2644911877
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.776533896
Short name T81
Test name
Test status
Simulation time 6730773746 ps
CPU time 27.88 seconds
Started Jul 10 05:06:26 PM PDT 24
Finished Jul 10 05:07:02 PM PDT 24
Peak memory 211644 kb
Host smart-62a85e0b-3f9b-45c4-bc51-328e22422522
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776533896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.776533896
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3485812155
Short name T386
Test name
Test status
Simulation time 2700293301 ps
CPU time 74.48 seconds
Started Jul 10 05:06:24 PM PDT 24
Finished Jul 10 05:07:47 PM PDT 24
Peak memory 213752 kb
Host smart-f355b0be-5d65-4f19-af8d-36f05ccd17f2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485812155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3485812155
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1564938639
Short name T414
Test name
Test status
Simulation time 17904886572 ps
CPU time 30.59 seconds
Started Jul 10 05:06:22 PM PDT 24
Finished Jul 10 05:07:00 PM PDT 24
Peak memory 212424 kb
Host smart-e9cacbda-19fe-4889-bff7-0680d7e979cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564938639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1564938639
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.491225350
Short name T451
Test name
Test status
Simulation time 11946625140 ps
CPU time 29.14 seconds
Started Jul 10 05:06:24 PM PDT 24
Finished Jul 10 05:07:02 PM PDT 24
Peak memory 217840 kb
Host smart-40495e5c-5339-4805-9da7-963efd8bf1f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491225350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.491225350
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1980706267
Short name T384
Test name
Test status
Simulation time 1373360422 ps
CPU time 9.41 seconds
Started Jul 10 05:06:28 PM PDT 24
Finished Jul 10 05:06:45 PM PDT 24
Peak memory 218840 kb
Host smart-bbed0b8d-4103-46af-8945-0c3f38bfa2ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980706267 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1980706267
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3715156973
Short name T52
Test name
Test status
Simulation time 3777759618 ps
CPU time 14.75 seconds
Started Jul 10 05:06:28 PM PDT 24
Finished Jul 10 05:06:51 PM PDT 24
Peak memory 211120 kb
Host smart-5ec2a6b3-b95a-446d-8750-2eea116b824b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715156973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3715156973
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1856577124
Short name T396
Test name
Test status
Simulation time 2763727568 ps
CPU time 37.53 seconds
Started Jul 10 05:06:24 PM PDT 24
Finished Jul 10 05:07:10 PM PDT 24
Peak memory 213752 kb
Host smart-67d4a603-ed65-44e1-a5e7-7c4c14e08053
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856577124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1856577124
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.616975919
Short name T399
Test name
Test status
Simulation time 6059533931 ps
CPU time 22.08 seconds
Started Jul 10 05:06:31 PM PDT 24
Finished Jul 10 05:07:00 PM PDT 24
Peak memory 212696 kb
Host smart-17712fd0-37a6-4f82-ad20-bd29c2f95c93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616975919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.616975919
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.633089440
Short name T371
Test name
Test status
Simulation time 6917881206 ps
CPU time 25.04 seconds
Started Jul 10 05:06:27 PM PDT 24
Finished Jul 10 05:06:59 PM PDT 24
Peak memory 218784 kb
Host smart-4530201b-e46f-4e39-a69d-64a7b3e1773f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633089440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.633089440
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2828416301
Short name T442
Test name
Test status
Simulation time 513537567 ps
CPU time 159.27 seconds
Started Jul 10 05:06:29 PM PDT 24
Finished Jul 10 05:09:15 PM PDT 24
Peak memory 214048 kb
Host smart-3b196466-f507-46af-994d-f2dc7c112312
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828416301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2828416301
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1129822465
Short name T408
Test name
Test status
Simulation time 532367020 ps
CPU time 12.45 seconds
Started Jul 10 05:06:30 PM PDT 24
Finished Jul 10 05:06:50 PM PDT 24
Peak memory 216012 kb
Host smart-a0489ffd-bd3b-47de-a00d-7a7da7d6c59e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129822465 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1129822465
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.181317425
Short name T78
Test name
Test status
Simulation time 7530392104 ps
CPU time 19.82 seconds
Started Jul 10 05:06:29 PM PDT 24
Finished Jul 10 05:06:56 PM PDT 24
Peak memory 211892 kb
Host smart-68a66bf1-7047-4aaf-bc1e-9711dd8ba46d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181317425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.181317425
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3063485565
Short name T422
Test name
Test status
Simulation time 3640098440 ps
CPU time 79.48 seconds
Started Jul 10 05:06:30 PM PDT 24
Finished Jul 10 05:07:57 PM PDT 24
Peak memory 216152 kb
Host smart-c8681627-f483-4056-ba88-e37ea15bcafe
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063485565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3063485565
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3198334542
Short name T410
Test name
Test status
Simulation time 348540213 ps
CPU time 10.8 seconds
Started Jul 10 05:06:30 PM PDT 24
Finished Jul 10 05:06:49 PM PDT 24
Peak memory 211196 kb
Host smart-d5291f4e-e600-42e1-b187-21893b52486c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198334542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3198334542
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2062340144
Short name T415
Test name
Test status
Simulation time 9737310559 ps
CPU time 26.31 seconds
Started Jul 10 05:06:29 PM PDT 24
Finished Jul 10 05:07:03 PM PDT 24
Peak memory 218408 kb
Host smart-cca33c83-961e-486c-8cb1-25f3caeb48e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062340144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2062340144
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.691019518
Short name T390
Test name
Test status
Simulation time 1721750798 ps
CPU time 83.71 seconds
Started Jul 10 05:06:31 PM PDT 24
Finished Jul 10 05:08:01 PM PDT 24
Peak memory 213636 kb
Host smart-dcf0352f-2e59-4023-92f3-ff56f153db2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691019518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.691019518
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1082148792
Short name T403
Test name
Test status
Simulation time 7273249563 ps
CPU time 12.82 seconds
Started Jul 10 05:06:29 PM PDT 24
Finished Jul 10 05:06:50 PM PDT 24
Peak memory 217696 kb
Host smart-5dae45c4-6aac-4a0f-bdb8-ba4364413d87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082148792 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1082148792
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1368455981
Short name T429
Test name
Test status
Simulation time 5979296478 ps
CPU time 17.48 seconds
Started Jul 10 05:06:28 PM PDT 24
Finished Jul 10 05:06:54 PM PDT 24
Peak memory 211944 kb
Host smart-e67cfa4d-e8f8-411d-ab9c-6d153458c1fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368455981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1368455981
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1835067203
Short name T59
Test name
Test status
Simulation time 30229334712 ps
CPU time 127.37 seconds
Started Jul 10 05:06:30 PM PDT 24
Finished Jul 10 05:08:45 PM PDT 24
Peak memory 213740 kb
Host smart-c6025479-d181-4274-bc16-7f982212826b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835067203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1835067203
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1390164618
Short name T400
Test name
Test status
Simulation time 1032614910 ps
CPU time 9.82 seconds
Started Jul 10 05:06:28 PM PDT 24
Finished Jul 10 05:06:46 PM PDT 24
Peak memory 211232 kb
Host smart-35274267-ae89-469e-b0ce-a1b215d250e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390164618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1390164618
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1031753090
Short name T377
Test name
Test status
Simulation time 3756554873 ps
CPU time 32 seconds
Started Jul 10 05:06:29 PM PDT 24
Finished Jul 10 05:07:09 PM PDT 24
Peak memory 216148 kb
Host smart-0ea8496a-7f4e-4d22-8778-08947589cd0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031753090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1031753090
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2183657211
Short name T106
Test name
Test status
Simulation time 5883344289 ps
CPU time 96.36 seconds
Started Jul 10 05:06:29 PM PDT 24
Finished Jul 10 05:08:13 PM PDT 24
Peak memory 213896 kb
Host smart-bbb74310-f230-45b5-82e5-f42a5c343630
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183657211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2183657211
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.586151223
Short name T47
Test name
Test status
Simulation time 3320420578 ps
CPU time 27.54 seconds
Started Jul 10 05:06:30 PM PDT 24
Finished Jul 10 05:07:05 PM PDT 24
Peak memory 216408 kb
Host smart-96f3bddf-8131-40df-a4dd-d7435b6923a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586151223 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.586151223
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1301406768
Short name T385
Test name
Test status
Simulation time 167390531 ps
CPU time 8.26 seconds
Started Jul 10 05:06:30 PM PDT 24
Finished Jul 10 05:06:46 PM PDT 24
Peak memory 210548 kb
Host smart-ab9c981c-cf50-415a-8187-f24571723756
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301406768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1301406768
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4149810786
Short name T450
Test name
Test status
Simulation time 61667668617 ps
CPU time 129.34 seconds
Started Jul 10 05:06:29 PM PDT 24
Finished Jul 10 05:08:46 PM PDT 24
Peak memory 213760 kb
Host smart-c52b4b10-7786-4f01-adc0-4f8a48be8c39
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149810786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.4149810786
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.726405569
Short name T89
Test name
Test status
Simulation time 4977921170 ps
CPU time 22.06 seconds
Started Jul 10 05:06:31 PM PDT 24
Finished Jul 10 05:07:00 PM PDT 24
Peak memory 212748 kb
Host smart-58264275-83da-43ea-8a9f-9b17295a62ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726405569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.726405569
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.142478818
Short name T401
Test name
Test status
Simulation time 3583036694 ps
CPU time 17.26 seconds
Started Jul 10 05:06:29 PM PDT 24
Finished Jul 10 05:06:54 PM PDT 24
Peak memory 218008 kb
Host smart-3aac8d0e-1d83-4286-80b8-7846c5b0515e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142478818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.142478818
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1976390516
Short name T104
Test name
Test status
Simulation time 397652386 ps
CPU time 155.37 seconds
Started Jul 10 05:06:28 PM PDT 24
Finished Jul 10 05:09:11 PM PDT 24
Peak memory 218848 kb
Host smart-6fdf4324-1cef-4fdf-ba41-57572c324156
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976390516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1976390516
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.940376745
Short name T365
Test name
Test status
Simulation time 9212480993 ps
CPU time 22 seconds
Started Jul 10 05:06:36 PM PDT 24
Finished Jul 10 05:07:03 PM PDT 24
Peak memory 217340 kb
Host smart-1d6a8617-2f48-42b0-8921-edd2a8855a7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940376745 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.940376745
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3216953831
Short name T92
Test name
Test status
Simulation time 3058405257 ps
CPU time 25.22 seconds
Started Jul 10 05:06:36 PM PDT 24
Finished Jul 10 05:07:07 PM PDT 24
Peak memory 211688 kb
Host smart-59121f0b-2e3e-449f-9f6e-9900541f9484
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216953831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3216953831
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2214465329
Short name T88
Test name
Test status
Simulation time 8889961953 ps
CPU time 31.91 seconds
Started Jul 10 05:06:38 PM PDT 24
Finished Jul 10 05:07:15 PM PDT 24
Peak memory 212448 kb
Host smart-c0d57b5d-e8d9-49ca-8718-4ce901e802f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214465329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2214465329
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.4226828623
Short name T387
Test name
Test status
Simulation time 1851732828 ps
CPU time 18.81 seconds
Started Jul 10 05:06:31 PM PDT 24
Finished Jul 10 05:06:58 PM PDT 24
Peak memory 218424 kb
Host smart-5861cac4-a6f1-491c-bc54-f6deeb692d90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226828623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.4226828623
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2609484150
Short name T108
Test name
Test status
Simulation time 4282505812 ps
CPU time 172.17 seconds
Started Jul 10 05:06:31 PM PDT 24
Finished Jul 10 05:09:31 PM PDT 24
Peak memory 213828 kb
Host smart-21c5e7c3-f2f8-41f7-a6ae-28ae7f910252
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609484150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2609484150
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.633270784
Short name T457
Test name
Test status
Simulation time 29895344351 ps
CPU time 23.61 seconds
Started Jul 10 05:06:36 PM PDT 24
Finished Jul 10 05:07:05 PM PDT 24
Peak memory 216984 kb
Host smart-e7384011-2616-4a46-8e01-1af8b754cd17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633270784 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.633270784
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4174142447
Short name T431
Test name
Test status
Simulation time 7238937610 ps
CPU time 19.29 seconds
Started Jul 10 05:06:37 PM PDT 24
Finished Jul 10 05:07:02 PM PDT 24
Peak memory 212268 kb
Host smart-b7e89189-1ab2-4b6f-aa72-60c47a6db870
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174142447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.4174142447
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2417818522
Short name T80
Test name
Test status
Simulation time 23368629516 ps
CPU time 198.54 seconds
Started Jul 10 05:06:39 PM PDT 24
Finished Jul 10 05:10:02 PM PDT 24
Peak memory 214976 kb
Host smart-4fbbb139-cabb-4d5a-a8c6-79259ea5a719
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417818522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2417818522
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.159280575
Short name T419
Test name
Test status
Simulation time 10831177836 ps
CPU time 28.6 seconds
Started Jul 10 05:06:37 PM PDT 24
Finished Jul 10 05:07:11 PM PDT 24
Peak memory 212736 kb
Host smart-fbdfaed3-859a-44bc-aead-267ee63d8c92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159280575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.159280575
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2964469883
Short name T367
Test name
Test status
Simulation time 538555815 ps
CPU time 15.38 seconds
Started Jul 10 05:06:36 PM PDT 24
Finished Jul 10 05:06:57 PM PDT 24
Peak memory 217116 kb
Host smart-8da12697-a578-4d2a-a71b-7f3849455dbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964469883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2964469883
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.767053142
Short name T456
Test name
Test status
Simulation time 697027524 ps
CPU time 9.35 seconds
Started Jul 10 05:06:35 PM PDT 24
Finished Jul 10 05:06:50 PM PDT 24
Peak memory 217100 kb
Host smart-7ab1aa64-1233-4375-bd98-5e10092a083e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767053142 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.767053142
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2885257426
Short name T444
Test name
Test status
Simulation time 836914728 ps
CPU time 11.1 seconds
Started Jul 10 05:06:37 PM PDT 24
Finished Jul 10 05:06:54 PM PDT 24
Peak memory 210508 kb
Host smart-f8b7ae2f-e40f-45bd-ab3a-f9a01478334e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885257426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2885257426
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.997635465
Short name T77
Test name
Test status
Simulation time 15152174600 ps
CPU time 61.98 seconds
Started Jul 10 05:06:39 PM PDT 24
Finished Jul 10 05:07:46 PM PDT 24
Peak memory 213556 kb
Host smart-7f0650fc-4663-4283-82ad-115025d9ea66
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997635465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.997635465
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.564667154
Short name T84
Test name
Test status
Simulation time 21036498052 ps
CPU time 20.22 seconds
Started Jul 10 05:06:36 PM PDT 24
Finished Jul 10 05:07:02 PM PDT 24
Peak memory 212644 kb
Host smart-f19bc945-e7eb-4fc6-90df-6b97e070df8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564667154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.564667154
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.151396671
Short name T423
Test name
Test status
Simulation time 35305870717 ps
CPU time 28.77 seconds
Started Jul 10 05:06:37 PM PDT 24
Finished Jul 10 05:07:11 PM PDT 24
Peak memory 218872 kb
Host smart-55e16849-ff4e-424b-afac-2623258555ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151396671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.151396671
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1901376618
Short name T420
Test name
Test status
Simulation time 1961979102 ps
CPU time 20.34 seconds
Started Jul 10 05:06:36 PM PDT 24
Finished Jul 10 05:07:02 PM PDT 24
Peak memory 217172 kb
Host smart-568bd499-3d7a-4943-83f1-e5c9c1b3118f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901376618 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1901376618
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.629644554
Short name T76
Test name
Test status
Simulation time 1989410500 ps
CPU time 20.31 seconds
Started Jul 10 05:06:35 PM PDT 24
Finished Jul 10 05:07:01 PM PDT 24
Peak memory 210612 kb
Host smart-cdf8d615-986d-4d82-be4a-0a5e4def77b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629644554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.629644554
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.125925372
Short name T432
Test name
Test status
Simulation time 93722073482 ps
CPU time 169.06 seconds
Started Jul 10 05:06:37 PM PDT 24
Finished Jul 10 05:09:32 PM PDT 24
Peak memory 215172 kb
Host smart-b13f59cf-5f33-48c5-95a5-8fd4a7e19f11
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125925372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pa
ssthru_mem_tl_intg_err.125925372
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3662443864
Short name T405
Test name
Test status
Simulation time 4043883759 ps
CPU time 32.09 seconds
Started Jul 10 05:06:36 PM PDT 24
Finished Jul 10 05:07:14 PM PDT 24
Peak memory 212500 kb
Host smart-64d12796-9fb2-4bd8-a1b4-fd725a59c0c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662443864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3662443864
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.802289005
Short name T397
Test name
Test status
Simulation time 5140608774 ps
CPU time 19.28 seconds
Started Jul 10 05:06:34 PM PDT 24
Finished Jul 10 05:06:59 PM PDT 24
Peak memory 219004 kb
Host smart-caed3d25-6691-477a-aab7-8abf28397466
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802289005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.802289005
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1935809443
Short name T458
Test name
Test status
Simulation time 932286189 ps
CPU time 82.37 seconds
Started Jul 10 05:06:37 PM PDT 24
Finished Jul 10 05:08:05 PM PDT 24
Peak memory 213464 kb
Host smart-a8249855-d5f1-45bc-9fd4-aaa88b4d6215
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935809443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1935809443
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3138634223
Short name T455
Test name
Test status
Simulation time 971117225 ps
CPU time 13.33 seconds
Started Jul 10 05:06:42 PM PDT 24
Finished Jul 10 05:06:59 PM PDT 24
Peak memory 216080 kb
Host smart-aa5c963d-7d0d-4f1c-b6e3-4ebc9a922e1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138634223 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3138634223
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3414417764
Short name T370
Test name
Test status
Simulation time 174466198 ps
CPU time 8 seconds
Started Jul 10 05:06:41 PM PDT 24
Finished Jul 10 05:06:53 PM PDT 24
Peak memory 210692 kb
Host smart-a2a6fd7f-e0ef-4c01-91a5-c739f6187882
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414417764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3414417764
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3575808645
Short name T392
Test name
Test status
Simulation time 69932436566 ps
CPU time 138.97 seconds
Started Jul 10 05:06:34 PM PDT 24
Finished Jul 10 05:08:59 PM PDT 24
Peak memory 215096 kb
Host smart-6c0499fd-e7e2-487c-a605-642e6a4d6c04
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575808645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3575808645
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2999436154
Short name T67
Test name
Test status
Simulation time 1674811620 ps
CPU time 13.47 seconds
Started Jul 10 05:06:43 PM PDT 24
Finished Jul 10 05:07:00 PM PDT 24
Peak memory 212124 kb
Host smart-7e973efc-4521-4447-a3ce-f8318ca49f44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999436154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2999436154
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.519294058
Short name T404
Test name
Test status
Simulation time 11264309690 ps
CPU time 28.88 seconds
Started Jul 10 05:06:39 PM PDT 24
Finished Jul 10 05:07:13 PM PDT 24
Peak memory 217584 kb
Host smart-3be53181-78ce-42c2-9f97-b422299f7d45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519294058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.519294058
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2194285614
Short name T49
Test name
Test status
Simulation time 618087947 ps
CPU time 152.67 seconds
Started Jul 10 05:06:38 PM PDT 24
Finished Jul 10 05:09:16 PM PDT 24
Peak memory 214052 kb
Host smart-37e2879c-4a4d-4c32-b32a-c67377ba37f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194285614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2194285614
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3696511254
Short name T82
Test name
Test status
Simulation time 211572528 ps
CPU time 8.25 seconds
Started Jul 10 05:06:15 PM PDT 24
Finished Jul 10 05:06:30 PM PDT 24
Peak memory 210708 kb
Host smart-a0fd76fa-c2c5-4622-a2ae-c4ffe4250b52
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696511254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3696511254
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3456674667
Short name T424
Test name
Test status
Simulation time 3764570352 ps
CPU time 20.88 seconds
Started Jul 10 05:06:15 PM PDT 24
Finished Jul 10 05:06:42 PM PDT 24
Peak memory 211064 kb
Host smart-0908fcd1-6a78-41e9-8737-b6f3a1eea619
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456674667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3456674667
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.877138571
Short name T90
Test name
Test status
Simulation time 3371247159 ps
CPU time 15.49 seconds
Started Jul 10 05:06:14 PM PDT 24
Finished Jul 10 05:06:36 PM PDT 24
Peak memory 211952 kb
Host smart-da902181-bf0f-4e3d-bd14-6b8f8072fcea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877138571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.877138571
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2182912614
Short name T383
Test name
Test status
Simulation time 3346887442 ps
CPU time 27.35 seconds
Started Jul 10 05:06:15 PM PDT 24
Finished Jul 10 05:06:49 PM PDT 24
Peak memory 217616 kb
Host smart-c1ce4024-a67b-4fa8-8608-4600c70e5505
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182912614 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2182912614
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3900634002
Short name T434
Test name
Test status
Simulation time 3354791286 ps
CPU time 22.86 seconds
Started Jul 10 05:06:15 PM PDT 24
Finished Jul 10 05:06:45 PM PDT 24
Peak memory 211516 kb
Host smart-49d2b18d-59df-492c-a111-71ea58c557cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900634002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3900634002
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.683550724
Short name T427
Test name
Test status
Simulation time 170711954 ps
CPU time 7.98 seconds
Started Jul 10 05:06:15 PM PDT 24
Finished Jul 10 05:06:29 PM PDT 24
Peak memory 210576 kb
Host smart-39f58eb1-9318-451b-9739-1f769ddaa1f2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683550724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.683550724
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1073233569
Short name T412
Test name
Test status
Simulation time 3173065927 ps
CPU time 27 seconds
Started Jul 10 05:06:19 PM PDT 24
Finished Jul 10 05:06:53 PM PDT 24
Peak memory 210568 kb
Host smart-6d3afc1d-3894-4e93-9833-da506d38dc08
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073233569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1073233569
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1784239805
Short name T436
Test name
Test status
Simulation time 12015220555 ps
CPU time 77.3 seconds
Started Jul 10 05:06:18 PM PDT 24
Finished Jul 10 05:07:43 PM PDT 24
Peak memory 215804 kb
Host smart-01416c9e-02c2-44b7-8b54-7ecc78647474
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784239805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1784239805
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2467797885
Short name T443
Test name
Test status
Simulation time 40486764993 ps
CPU time 28.88 seconds
Started Jul 10 05:06:16 PM PDT 24
Finished Jul 10 05:06:52 PM PDT 24
Peak memory 212568 kb
Host smart-fb18e7a9-36e8-4229-995a-1d3c46802c99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467797885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2467797885
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3711837339
Short name T369
Test name
Test status
Simulation time 5498295899 ps
CPU time 27.93 seconds
Started Jul 10 05:06:15 PM PDT 24
Finished Jul 10 05:06:49 PM PDT 24
Peak memory 218672 kb
Host smart-bec7f7c0-42d9-4093-9434-6214e2693150
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711837339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3711837339
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1979837836
Short name T110
Test name
Test status
Simulation time 433422384 ps
CPU time 84.05 seconds
Started Jul 10 05:06:18 PM PDT 24
Finished Jul 10 05:07:49 PM PDT 24
Peak memory 213592 kb
Host smart-98ea6af2-4250-401b-bf8b-5f3c24320117
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979837836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1979837836
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2827854987
Short name T68
Test name
Test status
Simulation time 41056890225 ps
CPU time 28.11 seconds
Started Jul 10 05:06:17 PM PDT 24
Finished Jul 10 05:06:52 PM PDT 24
Peak memory 212416 kb
Host smart-fd965e7a-30da-427f-8186-9ce6e2b1a7d4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827854987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2827854987
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3554318917
Short name T453
Test name
Test status
Simulation time 3619941139 ps
CPU time 14.41 seconds
Started Jul 10 05:06:24 PM PDT 24
Finished Jul 10 05:06:47 PM PDT 24
Peak memory 211292 kb
Host smart-0de84bfd-012c-4dea-b6bf-9473a5bcb538
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554318917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3554318917
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1261765966
Short name T454
Test name
Test status
Simulation time 760952363 ps
CPU time 12.11 seconds
Started Jul 10 05:06:17 PM PDT 24
Finished Jul 10 05:06:36 PM PDT 24
Peak memory 210644 kb
Host smart-23a221b0-824b-4b4a-a258-f9f0ae01b069
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261765966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1261765966
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3227481757
Short name T381
Test name
Test status
Simulation time 2749763741 ps
CPU time 22.86 seconds
Started Jul 10 05:06:22 PM PDT 24
Finished Jul 10 05:06:52 PM PDT 24
Peak memory 215116 kb
Host smart-03560a23-3377-448d-a94f-ff56b323df47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227481757 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3227481757
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4052278567
Short name T452
Test name
Test status
Simulation time 7235000525 ps
CPU time 19.68 seconds
Started Jul 10 05:06:17 PM PDT 24
Finished Jul 10 05:06:44 PM PDT 24
Peak memory 212024 kb
Host smart-2f7f0a76-4bc0-42d7-8ab9-0ac30c3459e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052278567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.4052278567
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2518511016
Short name T428
Test name
Test status
Simulation time 4433221293 ps
CPU time 31.71 seconds
Started Jul 10 05:06:16 PM PDT 24
Finished Jul 10 05:06:54 PM PDT 24
Peak memory 210740 kb
Host smart-d90bdc15-8381-47b8-83df-a0c3075a2df0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518511016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2518511016
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.436410941
Short name T430
Test name
Test status
Simulation time 14238562471 ps
CPU time 28.68 seconds
Started Jul 10 05:06:14 PM PDT 24
Finished Jul 10 05:06:48 PM PDT 24
Peak memory 210544 kb
Host smart-288711f7-9eda-4d5f-944e-7970bbe80d23
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436410941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
436410941
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1165786006
Short name T62
Test name
Test status
Simulation time 19337355818 ps
CPU time 116.61 seconds
Started Jul 10 05:06:15 PM PDT 24
Finished Jul 10 05:08:19 PM PDT 24
Peak memory 215264 kb
Host smart-f52f892c-1977-4a7d-a3a2-cd3f161f6ed6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165786006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1165786006
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2134676619
Short name T86
Test name
Test status
Simulation time 15003510208 ps
CPU time 29.94 seconds
Started Jul 10 05:06:19 PM PDT 24
Finished Jul 10 05:06:56 PM PDT 24
Peak memory 212832 kb
Host smart-b47e92c1-bd99-4bf0-9e02-c1e92a9ee682
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134676619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2134676619
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.224330344
Short name T445
Test name
Test status
Simulation time 2619714591 ps
CPU time 27.22 seconds
Started Jul 10 05:06:14 PM PDT 24
Finished Jul 10 05:06:48 PM PDT 24
Peak memory 217128 kb
Host smart-2a557f3e-7469-4d77-8fe5-e7d362bf7667
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224330344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.224330344
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.236357291
Short name T113
Test name
Test status
Simulation time 11808062809 ps
CPU time 100.18 seconds
Started Jul 10 05:06:22 PM PDT 24
Finished Jul 10 05:08:09 PM PDT 24
Peak memory 213816 kb
Host smart-99729cd7-0907-4f78-ba88-187ecd57b137
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236357291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.236357291
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3148871129
Short name T373
Test name
Test status
Simulation time 25603506235 ps
CPU time 23.84 seconds
Started Jul 10 05:06:21 PM PDT 24
Finished Jul 10 05:06:52 PM PDT 24
Peak memory 211820 kb
Host smart-917b85d8-be59-4c0c-af8b-39eb0f715be8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148871129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3148871129
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1153947636
Short name T391
Test name
Test status
Simulation time 4112231626 ps
CPU time 14.61 seconds
Started Jul 10 05:06:21 PM PDT 24
Finished Jul 10 05:06:43 PM PDT 24
Peak memory 210676 kb
Host smart-56b83a09-a369-45e3-8d5f-570f58e949fd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153947636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1153947636
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2039450933
Short name T376
Test name
Test status
Simulation time 349681526 ps
CPU time 11.76 seconds
Started Jul 10 05:06:16 PM PDT 24
Finished Jul 10 05:06:35 PM PDT 24
Peak memory 210688 kb
Host smart-f59e5409-c73d-40f2-9499-59dbd4bfe754
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039450933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2039450933
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.197622158
Short name T379
Test name
Test status
Simulation time 7432732960 ps
CPU time 29.41 seconds
Started Jul 10 05:06:24 PM PDT 24
Finished Jul 10 05:07:02 PM PDT 24
Peak memory 217000 kb
Host smart-0c6f627f-1c0b-425e-9ba5-dbeb3c6181cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197622158 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.197622158
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.861173184
Short name T75
Test name
Test status
Simulation time 68407879071 ps
CPU time 29.14 seconds
Started Jul 10 05:06:14 PM PDT 24
Finished Jul 10 05:06:50 PM PDT 24
Peak memory 212112 kb
Host smart-789c86ba-b382-49a7-949c-a5abea90e7cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861173184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.861173184
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3473014646
Short name T426
Test name
Test status
Simulation time 26194639503 ps
CPU time 25.79 seconds
Started Jul 10 05:06:15 PM PDT 24
Finished Jul 10 05:06:47 PM PDT 24
Peak memory 210552 kb
Host smart-cb44a6c6-f3ae-43b9-8ce1-3db245f10909
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473014646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3473014646
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.225713720
Short name T378
Test name
Test status
Simulation time 2134924562 ps
CPU time 20.56 seconds
Started Jul 10 05:06:15 PM PDT 24
Finished Jul 10 05:06:42 PM PDT 24
Peak memory 210480 kb
Host smart-0ffe10e9-e174-4696-9876-4f3eb84b7feb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225713720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
225713720
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3405108349
Short name T94
Test name
Test status
Simulation time 5952236436 ps
CPU time 54.48 seconds
Started Jul 10 05:06:16 PM PDT 24
Finished Jul 10 05:07:18 PM PDT 24
Peak memory 214144 kb
Host smart-c953c80a-7de3-420f-b467-880c8fcc7795
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405108349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3405108349
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1636987653
Short name T449
Test name
Test status
Simulation time 3841567504 ps
CPU time 20.86 seconds
Started Jul 10 05:06:22 PM PDT 24
Finished Jul 10 05:06:50 PM PDT 24
Peak memory 212116 kb
Host smart-af9b1073-f1ec-4f44-95f7-80dd67f6e27c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636987653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1636987653
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2130429004
Short name T413
Test name
Test status
Simulation time 4927923920 ps
CPU time 27.92 seconds
Started Jul 10 05:06:17 PM PDT 24
Finished Jul 10 05:06:53 PM PDT 24
Peak memory 218712 kb
Host smart-2f0d8a56-1d40-4640-af8d-0a94295d0325
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130429004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2130429004
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2076998500
Short name T395
Test name
Test status
Simulation time 605509446 ps
CPU time 13.37 seconds
Started Jul 10 05:06:24 PM PDT 24
Finished Jul 10 05:06:46 PM PDT 24
Peak memory 217032 kb
Host smart-4c0191ac-8398-45af-8bf0-141de75553c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076998500 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2076998500
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3946475516
Short name T93
Test name
Test status
Simulation time 9816050629 ps
CPU time 30.6 seconds
Started Jul 10 05:06:26 PM PDT 24
Finished Jul 10 05:07:05 PM PDT 24
Peak memory 211524 kb
Host smart-dbc5cc12-222e-4015-94f2-24316ce1650c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946475516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3946475516
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2365436723
Short name T51
Test name
Test status
Simulation time 24266866272 ps
CPU time 127.69 seconds
Started Jul 10 05:06:22 PM PDT 24
Finished Jul 10 05:08:37 PM PDT 24
Peak memory 215592 kb
Host smart-d70b25e2-58df-4225-a0a9-fbcf89c102cf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365436723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2365436723
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4127954784
Short name T446
Test name
Test status
Simulation time 3496466032 ps
CPU time 33.74 seconds
Started Jul 10 05:06:24 PM PDT 24
Finished Jul 10 05:07:07 PM PDT 24
Peak memory 212180 kb
Host smart-0ec1cdd5-b1c7-4ebd-8051-bb120860b119
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127954784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.4127954784
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.140009618
Short name T447
Test name
Test status
Simulation time 176482117 ps
CPU time 14.07 seconds
Started Jul 10 05:06:26 PM PDT 24
Finished Jul 10 05:06:48 PM PDT 24
Peak memory 217420 kb
Host smart-d1f06fa1-8a06-4aa0-a98f-9ccb63e3f211
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140009618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.140009618
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2044787819
Short name T374
Test name
Test status
Simulation time 1502259024 ps
CPU time 17.8 seconds
Started Jul 10 05:06:23 PM PDT 24
Finished Jul 10 05:06:49 PM PDT 24
Peak memory 216364 kb
Host smart-49b7c08d-b51a-4992-b061-a66f8e38b448
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044787819 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2044787819
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3225882014
Short name T389
Test name
Test status
Simulation time 338877356 ps
CPU time 8.22 seconds
Started Jul 10 05:06:22 PM PDT 24
Finished Jul 10 05:06:38 PM PDT 24
Peak memory 210872 kb
Host smart-fb9e9029-54c3-4e41-b188-2614b9bd933b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225882014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3225882014
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2445198072
Short name T64
Test name
Test status
Simulation time 10251353163 ps
CPU time 97.67 seconds
Started Jul 10 05:06:25 PM PDT 24
Finished Jul 10 05:08:11 PM PDT 24
Peak memory 213696 kb
Host smart-9160b539-427c-4150-9988-482fa4ade344
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445198072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2445198072
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3451825010
Short name T85
Test name
Test status
Simulation time 708193408 ps
CPU time 12.3 seconds
Started Jul 10 05:06:24 PM PDT 24
Finished Jul 10 05:06:45 PM PDT 24
Peak memory 212356 kb
Host smart-5743b8eb-f1d6-4710-a53f-80ff5816e93e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451825010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3451825010
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3194681159
Short name T409
Test name
Test status
Simulation time 591617779 ps
CPU time 17.1 seconds
Started Jul 10 05:06:23 PM PDT 24
Finished Jul 10 05:06:48 PM PDT 24
Peak memory 217296 kb
Host smart-e13d26f3-fd5f-4daf-8529-68993e95f196
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194681159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3194681159
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2528105344
Short name T112
Test name
Test status
Simulation time 4263025041 ps
CPU time 171.88 seconds
Started Jul 10 05:06:22 PM PDT 24
Finished Jul 10 05:09:21 PM PDT 24
Peak memory 213824 kb
Host smart-c3a2947f-4e6d-4031-a560-eda814ef17b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528105344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2528105344
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3065648993
Short name T382
Test name
Test status
Simulation time 15501718384 ps
CPU time 29.37 seconds
Started Jul 10 05:06:19 PM PDT 24
Finished Jul 10 05:06:56 PM PDT 24
Peak memory 217136 kb
Host smart-e72385df-97af-46d7-a436-03ad35428b46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065648993 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3065648993
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1364552245
Short name T66
Test name
Test status
Simulation time 7556722108 ps
CPU time 19.87 seconds
Started Jul 10 05:06:25 PM PDT 24
Finished Jul 10 05:06:53 PM PDT 24
Peak memory 211128 kb
Host smart-4facfd09-ae7a-44ff-a5e2-03489cb4adf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364552245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1364552245
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.424253339
Short name T433
Test name
Test status
Simulation time 82066136448 ps
CPU time 81.45 seconds
Started Jul 10 05:06:24 PM PDT 24
Finished Jul 10 05:07:54 PM PDT 24
Peak memory 213840 kb
Host smart-9949a6a5-09ad-4154-8160-86b4a7994651
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424253339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.424253339
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1675762173
Short name T448
Test name
Test status
Simulation time 2392117484 ps
CPU time 11.98 seconds
Started Jul 10 05:06:21 PM PDT 24
Finished Jul 10 05:06:41 PM PDT 24
Peak memory 211452 kb
Host smart-b621571e-a8a7-4eef-ba66-74998471dacf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675762173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1675762173
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1618115002
Short name T440
Test name
Test status
Simulation time 10724818541 ps
CPU time 28.25 seconds
Started Jul 10 05:06:22 PM PDT 24
Finished Jul 10 05:06:58 PM PDT 24
Peak memory 217384 kb
Host smart-3f418aab-8f78-4ddb-844b-5de34c1d4758
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618115002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1618115002
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4095124725
Short name T105
Test name
Test status
Simulation time 5720706664 ps
CPU time 177.34 seconds
Started Jul 10 05:06:22 PM PDT 24
Finished Jul 10 05:09:27 PM PDT 24
Peak memory 214296 kb
Host smart-d8a32d82-d1a6-43f2-89e6-7cee8aef53bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095124725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.4095124725
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.344580180
Short name T380
Test name
Test status
Simulation time 725525597 ps
CPU time 8.53 seconds
Started Jul 10 05:06:25 PM PDT 24
Finished Jul 10 05:06:42 PM PDT 24
Peak memory 215716 kb
Host smart-5aa59b06-d1c9-4313-8366-079242eb1395
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344580180 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.344580180
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.744766238
Short name T79
Test name
Test status
Simulation time 1109710673 ps
CPU time 15.01 seconds
Started Jul 10 05:06:24 PM PDT 24
Finished Jul 10 05:06:48 PM PDT 24
Peak memory 210748 kb
Host smart-3fd601b6-debd-4bee-8029-766f513eefe3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744766238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.744766238
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1998481712
Short name T435
Test name
Test status
Simulation time 12998074296 ps
CPU time 110.63 seconds
Started Jul 10 05:06:23 PM PDT 24
Finished Jul 10 05:08:21 PM PDT 24
Peak memory 214128 kb
Host smart-8c3355f6-e4a2-43a4-82df-45476e4e56b5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998481712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1998481712
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1365317591
Short name T83
Test name
Test status
Simulation time 3716871439 ps
CPU time 28.75 seconds
Started Jul 10 05:06:25 PM PDT 24
Finished Jul 10 05:07:02 PM PDT 24
Peak memory 212248 kb
Host smart-60c4a631-58b0-413a-a478-55b1de3ec693
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365317591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1365317591
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1042138749
Short name T368
Test name
Test status
Simulation time 3140034125 ps
CPU time 31.14 seconds
Started Jul 10 05:06:27 PM PDT 24
Finished Jul 10 05:07:06 PM PDT 24
Peak memory 218656 kb
Host smart-cacb94e1-efa1-4dc3-812e-027d55ded787
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042138749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1042138749
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1769126716
Short name T102
Test name
Test status
Simulation time 3773425893 ps
CPU time 156.16 seconds
Started Jul 10 05:06:23 PM PDT 24
Finished Jul 10 05:09:07 PM PDT 24
Peak memory 214100 kb
Host smart-a0a94bfb-aab9-4019-b8d2-051e585c045f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769126716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1769126716
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.342739355
Short name T416
Test name
Test status
Simulation time 11660648991 ps
CPU time 24.83 seconds
Started Jul 10 05:06:26 PM PDT 24
Finished Jul 10 05:06:59 PM PDT 24
Peak memory 217232 kb
Host smart-06a22db7-2faf-4078-9d78-8a072265f80a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342739355 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.342739355
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2860797969
Short name T406
Test name
Test status
Simulation time 29598231191 ps
CPU time 24 seconds
Started Jul 10 05:06:26 PM PDT 24
Finished Jul 10 05:06:58 PM PDT 24
Peak memory 212144 kb
Host smart-40a44cd1-86e4-441a-847f-1583cb6638be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860797969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2860797969
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2047976278
Short name T417
Test name
Test status
Simulation time 18924351971 ps
CPU time 99.6 seconds
Started Jul 10 05:06:22 PM PDT 24
Finished Jul 10 05:08:09 PM PDT 24
Peak memory 215784 kb
Host smart-37b2e5ac-e990-4983-91f8-17c30c6f9f8d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047976278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2047976278
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1989824248
Short name T398
Test name
Test status
Simulation time 689142653 ps
CPU time 8.52 seconds
Started Jul 10 05:06:23 PM PDT 24
Finished Jul 10 05:06:39 PM PDT 24
Peak memory 211040 kb
Host smart-c7f82fc1-06a7-4b89-ba97-7bd0c299235d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989824248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1989824248
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.4217817984
Short name T421
Test name
Test status
Simulation time 3539721427 ps
CPU time 34.02 seconds
Started Jul 10 05:06:23 PM PDT 24
Finished Jul 10 05:07:05 PM PDT 24
Peak memory 218632 kb
Host smart-0e0049c2-8a2d-4be0-b343-235abd619e45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217817984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.4217817984
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.891015321
Short name T275
Test name
Test status
Simulation time 100937420059 ps
CPU time 368.02 seconds
Started Jul 10 05:06:42 PM PDT 24
Finished Jul 10 05:12:54 PM PDT 24
Peak memory 226560 kb
Host smart-7a01fa13-a1b2-433c-bd0d-d04c1be68727
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891015321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.891015321
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.265040337
Short name T286
Test name
Test status
Simulation time 9324421892 ps
CPU time 41.17 seconds
Started Jul 10 05:06:42 PM PDT 24
Finished Jul 10 05:07:27 PM PDT 24
Peak memory 219348 kb
Host smart-441c2f78-40e5-45b3-822f-1a9eb03fc2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265040337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.265040337
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2932401533
Short name T322
Test name
Test status
Simulation time 3063229687 ps
CPU time 26.57 seconds
Started Jul 10 05:06:42 PM PDT 24
Finished Jul 10 05:07:13 PM PDT 24
Peak memory 219384 kb
Host smart-382eca38-7fec-44a6-870d-423d2922cdaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2932401533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2932401533
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1866221348
Short name T22
Test name
Test status
Simulation time 1350456827 ps
CPU time 121.28 seconds
Started Jul 10 05:06:41 PM PDT 24
Finished Jul 10 05:08:46 PM PDT 24
Peak memory 235200 kb
Host smart-e68f17cf-7001-4801-90a6-a1713be9698e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866221348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1866221348
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2920199367
Short name T166
Test name
Test status
Simulation time 9765946065 ps
CPU time 66.2 seconds
Started Jul 10 05:06:43 PM PDT 24
Finished Jul 10 05:07:53 PM PDT 24
Peak memory 216680 kb
Host smart-1b64b81c-f5b7-4854-a811-510b60d1ab0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920199367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2920199367
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.117587679
Short name T211
Test name
Test status
Simulation time 5688968770 ps
CPU time 53.77 seconds
Started Jul 10 05:06:44 PM PDT 24
Finished Jul 10 05:07:41 PM PDT 24
Peak memory 219932 kb
Host smart-fc960bc8-c0ff-4368-8864-5fc5c0d1e13c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117587679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.117587679
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2849719044
Short name T200
Test name
Test status
Simulation time 4074507766 ps
CPU time 31.91 seconds
Started Jul 10 05:06:43 PM PDT 24
Finished Jul 10 05:07:19 PM PDT 24
Peak memory 217124 kb
Host smart-ee729398-6f94-44a6-9349-97bdb3ef4172
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849719044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2849719044
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3805833153
Short name T128
Test name
Test status
Simulation time 332360401294 ps
CPU time 878.37 seconds
Started Jul 10 05:06:42 PM PDT 24
Finished Jul 10 05:21:25 PM PDT 24
Peak memory 234284 kb
Host smart-2c0cd25e-2a2c-4dea-9c52-3dc37e2a1534
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805833153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3805833153
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.210537238
Short name T265
Test name
Test status
Simulation time 11414566890 ps
CPU time 42.03 seconds
Started Jul 10 05:06:43 PM PDT 24
Finished Jul 10 05:07:29 PM PDT 24
Peak memory 219348 kb
Host smart-52f416fd-3a9a-45c1-bbd5-37730e067072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210537238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.210537238
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1422734602
Short name T354
Test name
Test status
Simulation time 4019162613 ps
CPU time 31.19 seconds
Started Jul 10 05:06:44 PM PDT 24
Finished Jul 10 05:07:19 PM PDT 24
Peak memory 219300 kb
Host smart-8845f7cc-5250-47e3-b604-428039f2d77c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1422734602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1422734602
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3996544344
Short name T29
Test name
Test status
Simulation time 3393131291 ps
CPU time 133.61 seconds
Started Jul 10 05:06:43 PM PDT 24
Finished Jul 10 05:09:00 PM PDT 24
Peak memory 238416 kb
Host smart-eb78bfa7-333d-4c14-91cd-41afaf033bac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996544344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3996544344
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2264548594
Short name T137
Test name
Test status
Simulation time 359349511 ps
CPU time 19.72 seconds
Started Jul 10 05:06:42 PM PDT 24
Finished Jul 10 05:07:06 PM PDT 24
Peak memory 215924 kb
Host smart-30a7b7de-cc8b-4487-84d4-463e6f80db3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264548594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2264548594
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2329118185
Short name T160
Test name
Test status
Simulation time 174652503 ps
CPU time 8.42 seconds
Started Jul 10 05:06:58 PM PDT 24
Finished Jul 10 05:07:09 PM PDT 24
Peak memory 217108 kb
Host smart-45ae06c5-b905-44bb-af61-1ec71b7e4382
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329118185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2329118185
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2548963404
Short name T179
Test name
Test status
Simulation time 56930799697 ps
CPU time 598.09 seconds
Started Jul 10 05:06:57 PM PDT 24
Finished Jul 10 05:16:58 PM PDT 24
Peak memory 240084 kb
Host smart-a2cf8492-e8ea-4fc2-b61a-8a409bf849dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548963404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2548963404
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3381470650
Short name T257
Test name
Test status
Simulation time 38576512802 ps
CPU time 68.48 seconds
Started Jul 10 05:06:57 PM PDT 24
Finished Jul 10 05:08:08 PM PDT 24
Peak memory 219268 kb
Host smart-be89baf3-edf0-427d-9f55-e64310a7a78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381470650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3381470650
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3998442752
Short name T267
Test name
Test status
Simulation time 1016350984 ps
CPU time 10.47 seconds
Started Jul 10 05:06:59 PM PDT 24
Finished Jul 10 05:07:12 PM PDT 24
Peak memory 219292 kb
Host smart-9921de79-cbb5-4c4f-82b8-7638afb7b461
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3998442752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3998442752
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.4270643371
Short name T12
Test name
Test status
Simulation time 527310483 ps
CPU time 24.01 seconds
Started Jul 10 05:06:57 PM PDT 24
Finished Jul 10 05:07:24 PM PDT 24
Peak memory 216652 kb
Host smart-a00c7ba6-6d7c-400b-9278-cb5de00fe674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270643371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.4270643371
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1429450373
Short name T167
Test name
Test status
Simulation time 391955480 ps
CPU time 21.55 seconds
Started Jul 10 05:06:59 PM PDT 24
Finished Jul 10 05:07:23 PM PDT 24
Peak memory 218884 kb
Host smart-fc5e7bed-9a40-4bde-8b44-cb06116b83a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429450373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1429450373
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2075757877
Short name T180
Test name
Test status
Simulation time 738349916 ps
CPU time 13.51 seconds
Started Jul 10 05:07:04 PM PDT 24
Finished Jul 10 05:07:19 PM PDT 24
Peak memory 217060 kb
Host smart-74f93bfc-7b66-4d9f-91da-933c0f056928
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075757877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2075757877
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.612323736
Short name T250
Test name
Test status
Simulation time 12416977496 ps
CPU time 300.44 seconds
Started Jul 10 05:07:03 PM PDT 24
Finished Jul 10 05:12:05 PM PDT 24
Peak memory 229124 kb
Host smart-54df7a28-1ba3-4f1c-9ff7-02f479fd9a89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612323736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.612323736
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.4130801665
Short name T319
Test name
Test status
Simulation time 2349676305 ps
CPU time 24 seconds
Started Jul 10 05:07:05 PM PDT 24
Finished Jul 10 05:07:31 PM PDT 24
Peak memory 211612 kb
Host smart-eed32053-dbe3-4b1f-970c-db68b776fec4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4130801665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.4130801665
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.654228239
Short name T294
Test name
Test status
Simulation time 13873445141 ps
CPU time 62.92 seconds
Started Jul 10 05:06:59 PM PDT 24
Finished Jul 10 05:08:04 PM PDT 24
Peak memory 217072 kb
Host smart-828be809-f879-4788-ab99-11439a25362c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654228239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.654228239
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1625386551
Short name T157
Test name
Test status
Simulation time 15949700222 ps
CPU time 48.54 seconds
Started Jul 10 05:07:03 PM PDT 24
Finished Jul 10 05:07:53 PM PDT 24
Peak memory 217728 kb
Host smart-206c5e08-6295-472d-adc7-3c03e64657ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625386551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1625386551
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.4242037249
Short name T345
Test name
Test status
Simulation time 516789372 ps
CPU time 9.92 seconds
Started Jul 10 05:07:03 PM PDT 24
Finished Jul 10 05:07:14 PM PDT 24
Peak memory 216996 kb
Host smart-45b515ac-1ffa-49a2-81dc-192accfcd85b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242037249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.4242037249
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3944367851
Short name T116
Test name
Test status
Simulation time 159769098223 ps
CPU time 278.33 seconds
Started Jul 10 05:07:06 PM PDT 24
Finished Jul 10 05:11:45 PM PDT 24
Peak memory 224600 kb
Host smart-5507b99c-f466-4540-a998-f9f9e1baf189
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944367851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3944367851
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.452191578
Short name T315
Test name
Test status
Simulation time 14978489815 ps
CPU time 42.89 seconds
Started Jul 10 05:07:04 PM PDT 24
Finished Jul 10 05:07:48 PM PDT 24
Peak memory 219136 kb
Host smart-41bec3d0-78d5-46f9-99aa-406b6f6c6d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452191578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.452191578
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.4254069831
Short name T363
Test name
Test status
Simulation time 3504924666 ps
CPU time 10.82 seconds
Started Jul 10 05:07:04 PM PDT 24
Finished Jul 10 05:07:16 PM PDT 24
Peak memory 219300 kb
Host smart-de430d2e-da47-4dbb-bac8-87f35be5bb08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4254069831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.4254069831
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.59964824
Short name T177
Test name
Test status
Simulation time 1371092142 ps
CPU time 25.81 seconds
Started Jul 10 05:07:04 PM PDT 24
Finished Jul 10 05:07:31 PM PDT 24
Peak memory 216704 kb
Host smart-bcb73187-7ea9-4fff-b8f3-7a1effe7fedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59964824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.59964824
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3329210921
Short name T158
Test name
Test status
Simulation time 16553095637 ps
CPU time 87.08 seconds
Started Jul 10 05:07:06 PM PDT 24
Finished Jul 10 05:08:34 PM PDT 24
Peak memory 220668 kb
Host smart-da6ad877-2f3b-404d-b12f-599b99a62798
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329210921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3329210921
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2630416259
Short name T210
Test name
Test status
Simulation time 3430496212 ps
CPU time 19.23 seconds
Started Jul 10 05:07:09 PM PDT 24
Finished Jul 10 05:07:30 PM PDT 24
Peak memory 217188 kb
Host smart-ebb3dc49-3685-4730-bf3b-aaca674ea33a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630416259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2630416259
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3511076377
Short name T281
Test name
Test status
Simulation time 713585774 ps
CPU time 10.24 seconds
Started Jul 10 05:07:03 PM PDT 24
Finished Jul 10 05:07:15 PM PDT 24
Peak memory 219268 kb
Host smart-f5d900e7-b317-4f47-8a3e-e97c11bddc46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3511076377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3511076377
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3863494743
Short name T138
Test name
Test status
Simulation time 5191777864 ps
CPU time 59.84 seconds
Started Jul 10 05:07:05 PM PDT 24
Finished Jul 10 05:08:06 PM PDT 24
Peak memory 216968 kb
Host smart-7a94808a-dc18-4a3e-9da0-2f7bc5945ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863494743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3863494743
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2752540418
Short name T279
Test name
Test status
Simulation time 38448072235 ps
CPU time 170.4 seconds
Started Jul 10 05:07:04 PM PDT 24
Finished Jul 10 05:09:55 PM PDT 24
Peak memory 220252 kb
Host smart-608b3d8e-9164-48a3-a016-1688efeb689b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752540418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2752540418
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3317827719
Short name T307
Test name
Test status
Simulation time 3828001175 ps
CPU time 30.33 seconds
Started Jul 10 05:07:14 PM PDT 24
Finished Jul 10 05:07:45 PM PDT 24
Peak memory 217460 kb
Host smart-d45f3fb0-9ead-4cc1-8f64-c8c08be9e443
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317827719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3317827719
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3385957768
Short name T20
Test name
Test status
Simulation time 211995618378 ps
CPU time 413.09 seconds
Started Jul 10 05:07:10 PM PDT 24
Finished Jul 10 05:14:04 PM PDT 24
Peak memory 238016 kb
Host smart-d4190d4d-ddbd-426b-b33c-bcccb23cc8b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385957768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3385957768
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.182001405
Short name T299
Test name
Test status
Simulation time 30316570014 ps
CPU time 65.5 seconds
Started Jul 10 05:07:10 PM PDT 24
Finished Jul 10 05:08:17 PM PDT 24
Peak memory 219328 kb
Host smart-b61e43ed-93eb-4a17-8af7-3c415e4b72f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182001405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.182001405
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3165018276
Short name T178
Test name
Test status
Simulation time 16488900583 ps
CPU time 34.17 seconds
Started Jul 10 05:07:10 PM PDT 24
Finished Jul 10 05:07:45 PM PDT 24
Peak memory 211640 kb
Host smart-5bc81eb0-9e77-4978-9404-6eb47a20ce0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3165018276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3165018276
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1614258887
Short name T311
Test name
Test status
Simulation time 862112611 ps
CPU time 26.72 seconds
Started Jul 10 05:07:11 PM PDT 24
Finished Jul 10 05:07:38 PM PDT 24
Peak memory 216084 kb
Host smart-51f09a9a-eae8-430e-93eb-0232ce52bfef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614258887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1614258887
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3393756495
Short name T324
Test name
Test status
Simulation time 9295239875 ps
CPU time 41.85 seconds
Started Jul 10 05:07:09 PM PDT 24
Finished Jul 10 05:07:51 PM PDT 24
Peak memory 219296 kb
Host smart-74a816bb-fff5-4b31-a13b-624db0a82075
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393756495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3393756495
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.2875160980
Short name T46
Test name
Test status
Simulation time 50769913891 ps
CPU time 1087.66 seconds
Started Jul 10 05:07:08 PM PDT 24
Finished Jul 10 05:25:16 PM PDT 24
Peak memory 237736 kb
Host smart-61371423-948d-44cc-949a-aaec44d2bef7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875160980 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.2875160980
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.820043856
Short name T135
Test name
Test status
Simulation time 174473508 ps
CPU time 8.14 seconds
Started Jul 10 05:07:20 PM PDT 24
Finished Jul 10 05:07:29 PM PDT 24
Peak memory 217092 kb
Host smart-a259abf5-dd15-4f25-84ba-b53e907c85d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820043856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.820043856
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3194630116
Short name T237
Test name
Test status
Simulation time 16343054012 ps
CPU time 252.43 seconds
Started Jul 10 05:07:10 PM PDT 24
Finished Jul 10 05:11:24 PM PDT 24
Peak memory 237760 kb
Host smart-22122c51-d23f-4608-b618-d3c5360826a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194630116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3194630116
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3224782107
Short name T230
Test name
Test status
Simulation time 917279165 ps
CPU time 19.8 seconds
Started Jul 10 05:07:11 PM PDT 24
Finished Jul 10 05:07:31 PM PDT 24
Peak memory 219292 kb
Host smart-fec6af55-138b-43b8-a3e5-57cca41d5809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224782107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3224782107
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2651160827
Short name T361
Test name
Test status
Simulation time 646519594 ps
CPU time 10.91 seconds
Started Jul 10 05:07:12 PM PDT 24
Finished Jul 10 05:07:23 PM PDT 24
Peak memory 219252 kb
Host smart-5ee5e130-5436-4d22-957a-e3fa9fcd75c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2651160827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2651160827
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.2380608730
Short name T69
Test name
Test status
Simulation time 350595038 ps
CPU time 20.79 seconds
Started Jul 10 05:07:11 PM PDT 24
Finished Jul 10 05:07:32 PM PDT 24
Peak memory 216632 kb
Host smart-aff5506c-a2a9-410e-a9dc-1814fdf0c5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380608730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2380608730
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2381777382
Short name T184
Test name
Test status
Simulation time 4893804985 ps
CPU time 62.7 seconds
Started Jul 10 05:07:09 PM PDT 24
Finished Jul 10 05:08:12 PM PDT 24
Peak memory 219312 kb
Host smart-68a9b4d9-cd11-43d7-aa98-3632c3cfb08f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381777382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2381777382
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.743782973
Short name T144
Test name
Test status
Simulation time 1032568006 ps
CPU time 8.55 seconds
Started Jul 10 05:07:17 PM PDT 24
Finished Jul 10 05:07:27 PM PDT 24
Peak memory 217100 kb
Host smart-a5036379-506b-4e80-a75b-d5dcb36e97a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743782973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.743782973
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3580517566
Short name T40
Test name
Test status
Simulation time 17917354827 ps
CPU time 383.59 seconds
Started Jul 10 05:07:18 PM PDT 24
Finished Jul 10 05:13:43 PM PDT 24
Peak memory 233968 kb
Host smart-ea565320-830d-4c3b-af25-97b4c028afcf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580517566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3580517566
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1761099446
Short name T349
Test name
Test status
Simulation time 29108285669 ps
CPU time 58.42 seconds
Started Jul 10 05:07:19 PM PDT 24
Finished Jul 10 05:08:18 PM PDT 24
Peak memory 218664 kb
Host smart-06a0328e-292d-438d-a3ef-1b1454ec1714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761099446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1761099446
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2084054532
Short name T155
Test name
Test status
Simulation time 4502669982 ps
CPU time 23.17 seconds
Started Jul 10 05:07:19 PM PDT 24
Finished Jul 10 05:07:44 PM PDT 24
Peak memory 211812 kb
Host smart-621d943e-231a-4d5b-b7e4-6bcf71aa4c3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2084054532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2084054532
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1984077663
Short name T198
Test name
Test status
Simulation time 14173445195 ps
CPU time 33.14 seconds
Started Jul 10 05:07:18 PM PDT 24
Finished Jul 10 05:07:52 PM PDT 24
Peak memory 217328 kb
Host smart-114c5aaf-b9e6-4cc6-8a2c-bf0113fbce5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984077663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1984077663
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3793436921
Short name T124
Test name
Test status
Simulation time 21277842874 ps
CPU time 174.24 seconds
Started Jul 10 05:07:20 PM PDT 24
Finished Jul 10 05:10:15 PM PDT 24
Peak memory 220904 kb
Host smart-c01a4de8-c2a9-4afd-9848-8dbab2a11ed0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793436921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3793436921
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3965506522
Short name T24
Test name
Test status
Simulation time 8753203231 ps
CPU time 31.67 seconds
Started Jul 10 05:07:28 PM PDT 24
Finished Jul 10 05:08:00 PM PDT 24
Peak memory 217548 kb
Host smart-f1461450-b94a-44f8-9dbe-545b5f26b59f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965506522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3965506522
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.365141874
Short name T196
Test name
Test status
Simulation time 578210168117 ps
CPU time 752.42 seconds
Started Jul 10 05:07:20 PM PDT 24
Finished Jul 10 05:19:53 PM PDT 24
Peak memory 237068 kb
Host smart-f674f3ea-b77f-40d7-ba41-1fcb41bdac88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365141874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.365141874
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1927802450
Short name T192
Test name
Test status
Simulation time 72506190243 ps
CPU time 67.42 seconds
Started Jul 10 05:07:18 PM PDT 24
Finished Jul 10 05:08:27 PM PDT 24
Peak memory 219280 kb
Host smart-cb5f2ff7-ae32-4754-a32b-fa52b2d83e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927802450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1927802450
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.309346909
Short name T331
Test name
Test status
Simulation time 29663004498 ps
CPU time 32.22 seconds
Started Jul 10 05:07:19 PM PDT 24
Finished Jul 10 05:07:52 PM PDT 24
Peak memory 211844 kb
Host smart-a9820213-0048-47a6-8995-993596343c4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=309346909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.309346909
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2768421047
Short name T334
Test name
Test status
Simulation time 1609924970 ps
CPU time 19.62 seconds
Started Jul 10 05:07:18 PM PDT 24
Finished Jul 10 05:07:39 PM PDT 24
Peak memory 217388 kb
Host smart-7e9be22d-c57c-47ee-84e6-51a22da9c097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768421047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2768421047
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.868526684
Short name T187
Test name
Test status
Simulation time 179260309 ps
CPU time 17.45 seconds
Started Jul 10 05:07:17 PM PDT 24
Finished Jul 10 05:07:36 PM PDT 24
Peak memory 218628 kb
Host smart-ea7d5ddd-a762-420c-a11d-ad3c6babee1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868526684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.868526684
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2441125632
Short name T129
Test name
Test status
Simulation time 21808502718 ps
CPU time 31.36 seconds
Started Jul 10 05:07:29 PM PDT 24
Finished Jul 10 05:08:02 PM PDT 24
Peak memory 217456 kb
Host smart-d9c2f797-4c14-43ab-9dc6-8c37c6a27dfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441125632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2441125632
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1106576168
Short name T199
Test name
Test status
Simulation time 139962976749 ps
CPU time 299.18 seconds
Started Jul 10 05:07:27 PM PDT 24
Finished Jul 10 05:12:28 PM PDT 24
Peak memory 239764 kb
Host smart-5ea02be8-a982-4c4b-9db7-7196a9f9bb7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106576168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1106576168
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2169473410
Short name T231
Test name
Test status
Simulation time 17086274037 ps
CPU time 43.43 seconds
Started Jul 10 05:07:27 PM PDT 24
Finished Jul 10 05:08:12 PM PDT 24
Peak memory 219312 kb
Host smart-98e193e5-8f00-4c02-8510-dd71c0fdf65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169473410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2169473410
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.530855595
Short name T232
Test name
Test status
Simulation time 7215409451 ps
CPU time 30.05 seconds
Started Jul 10 05:07:28 PM PDT 24
Finished Jul 10 05:08:00 PM PDT 24
Peak memory 219368 kb
Host smart-a3118fa8-6587-4b41-992b-3fefae70eff9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=530855595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.530855595
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2728479547
Short name T202
Test name
Test status
Simulation time 1428351859 ps
CPU time 20.94 seconds
Started Jul 10 05:07:28 PM PDT 24
Finished Jul 10 05:07:50 PM PDT 24
Peak memory 216280 kb
Host smart-1374385c-bf60-4f39-899d-fc24a92d8da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728479547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2728479547
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3967810
Short name T350
Test name
Test status
Simulation time 1515680761 ps
CPU time 20.99 seconds
Started Jul 10 05:07:28 PM PDT 24
Finished Jul 10 05:07:51 PM PDT 24
Peak memory 218196 kb
Host smart-857d94ff-2520-4b8e-b920-ffbe7d85ce7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.rom_ctrl_stress_all.3967810
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2066988495
Short name T14
Test name
Test status
Simulation time 1049274992992 ps
CPU time 4358.3 seconds
Started Jul 10 05:07:28 PM PDT 24
Finished Jul 10 06:20:09 PM PDT 24
Peak memory 252160 kb
Host smart-853b7e16-3ace-4d67-b8f3-8d27f2e3cf23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066988495 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.2066988495
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2491092441
Short name T222
Test name
Test status
Simulation time 5215257648 ps
CPU time 32.5 seconds
Started Jul 10 05:07:28 PM PDT 24
Finished Jul 10 05:08:01 PM PDT 24
Peak memory 217604 kb
Host smart-af78739c-8fa0-41ee-b80b-e76b41d3ae66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491092441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2491092441
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1672948574
Short name T182
Test name
Test status
Simulation time 27219435272 ps
CPU time 163.62 seconds
Started Jul 10 05:07:28 PM PDT 24
Finished Jul 10 05:10:13 PM PDT 24
Peak memory 215660 kb
Host smart-7b4abf37-a790-460e-9011-9a7a3e19aa7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672948574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1672948574
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1895413496
Short name T258
Test name
Test status
Simulation time 59060694511 ps
CPU time 65.88 seconds
Started Jul 10 05:07:26 PM PDT 24
Finished Jul 10 05:08:33 PM PDT 24
Peak memory 219312 kb
Host smart-8b9d87ae-47ef-4b5a-aacf-91ae6fe3832e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895413496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1895413496
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.342021405
Short name T283
Test name
Test status
Simulation time 3756707866 ps
CPU time 29.36 seconds
Started Jul 10 05:07:28 PM PDT 24
Finished Jul 10 05:07:59 PM PDT 24
Peak memory 219324 kb
Host smart-75199733-b072-4248-a5c6-f57adab24ccc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=342021405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.342021405
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1168235609
Short name T194
Test name
Test status
Simulation time 1002823704 ps
CPU time 29.15 seconds
Started Jul 10 05:07:26 PM PDT 24
Finished Jul 10 05:07:56 PM PDT 24
Peak memory 216384 kb
Host smart-78d8dd51-e5eb-4774-86d9-bc8eebcb0701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168235609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1168235609
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1428618335
Short name T133
Test name
Test status
Simulation time 8083020769 ps
CPU time 70.24 seconds
Started Jul 10 05:07:25 PM PDT 24
Finished Jul 10 05:08:37 PM PDT 24
Peak memory 219336 kb
Host smart-326a55e1-c6fb-4d27-abeb-fb738f4a6214
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428618335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1428618335
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2737364196
Short name T303
Test name
Test status
Simulation time 4597093929 ps
CPU time 21.5 seconds
Started Jul 10 05:06:51 PM PDT 24
Finished Jul 10 05:07:16 PM PDT 24
Peak memory 217408 kb
Host smart-e41dea41-045c-479d-9372-8305397a5e84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737364196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2737364196
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.4150556731
Short name T33
Test name
Test status
Simulation time 198058692837 ps
CPU time 599.43 seconds
Started Jul 10 05:06:44 PM PDT 24
Finished Jul 10 05:16:48 PM PDT 24
Peak memory 236192 kb
Host smart-93b000a6-896b-4b11-b218-b83888d50d0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150556731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.4150556731
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1522290914
Short name T290
Test name
Test status
Simulation time 19636257470 ps
CPU time 38.67 seconds
Started Jul 10 05:06:45 PM PDT 24
Finished Jul 10 05:07:28 PM PDT 24
Peak memory 219316 kb
Host smart-ec83ea3b-48c5-4b9a-bbcb-6dc5f8b18d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522290914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1522290914
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2293163685
Short name T264
Test name
Test status
Simulation time 1982156259 ps
CPU time 21.86 seconds
Started Jul 10 05:06:43 PM PDT 24
Finished Jul 10 05:07:09 PM PDT 24
Peak memory 211624 kb
Host smart-2beeb96d-cf5e-4327-83ec-02617d4b38c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2293163685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2293163685
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1712872295
Short name T23
Test name
Test status
Simulation time 11537380200 ps
CPU time 132.76 seconds
Started Jul 10 05:06:43 PM PDT 24
Finished Jul 10 05:09:00 PM PDT 24
Peak memory 237508 kb
Host smart-75805d62-c5a4-4b46-9ec0-345c1cac254f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712872295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1712872295
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3963017007
Short name T260
Test name
Test status
Simulation time 7252503485 ps
CPU time 34.22 seconds
Started Jul 10 05:06:44 PM PDT 24
Finished Jul 10 05:07:22 PM PDT 24
Peak memory 218688 kb
Host smart-a109a9db-2ab0-410b-afda-e6af1a22d799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963017007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3963017007
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3716953680
Short name T122
Test name
Test status
Simulation time 16469433952 ps
CPU time 164.72 seconds
Started Jul 10 05:06:43 PM PDT 24
Finished Jul 10 05:09:32 PM PDT 24
Peak memory 221368 kb
Host smart-279ec9a5-dda3-4cae-b892-30cd4f2ed903
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716953680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3716953680
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3032110277
Short name T185
Test name
Test status
Simulation time 2379398419 ps
CPU time 22.34 seconds
Started Jul 10 05:07:29 PM PDT 24
Finished Jul 10 05:07:53 PM PDT 24
Peak memory 217180 kb
Host smart-e10048cd-6292-4abb-aea1-6dfed4746ec6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032110277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3032110277
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2570052499
Short name T313
Test name
Test status
Simulation time 31380983397 ps
CPU time 63.85 seconds
Started Jul 10 05:07:29 PM PDT 24
Finished Jul 10 05:08:35 PM PDT 24
Peak memory 219292 kb
Host smart-30531b73-4922-4c35-91ea-70523b8e5c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570052499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2570052499
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.866981647
Short name T335
Test name
Test status
Simulation time 6352218293 ps
CPU time 27.9 seconds
Started Jul 10 05:07:27 PM PDT 24
Finished Jul 10 05:07:56 PM PDT 24
Peak memory 211988 kb
Host smart-d55154ef-259f-44c3-8038-1402d1ec5a53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=866981647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.866981647
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.1189932645
Short name T125
Test name
Test status
Simulation time 532482563 ps
CPU time 23.13 seconds
Started Jul 10 05:07:28 PM PDT 24
Finished Jul 10 05:07:53 PM PDT 24
Peak memory 215764 kb
Host smart-29738c8c-9c95-405b-9f4f-7d91ac7c50ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189932645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.1189932645
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2258849077
Short name T162
Test name
Test status
Simulation time 8605591998 ps
CPU time 49.78 seconds
Started Jul 10 05:07:27 PM PDT 24
Finished Jul 10 05:08:18 PM PDT 24
Peak memory 219312 kb
Host smart-3764e1bd-5fb4-43bf-9ebd-4aa1829389c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258849077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2258849077
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2907902427
Short name T58
Test name
Test status
Simulation time 338745557 ps
CPU time 8.57 seconds
Started Jul 10 05:07:37 PM PDT 24
Finished Jul 10 05:07:48 PM PDT 24
Peak memory 217148 kb
Host smart-70cc43e7-e9a0-43d9-862d-4bed19449d0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907902427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2907902427
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1552646761
Short name T346
Test name
Test status
Simulation time 85355084850 ps
CPU time 888.23 seconds
Started Jul 10 05:07:35 PM PDT 24
Finished Jul 10 05:22:25 PM PDT 24
Peak memory 217932 kb
Host smart-04355480-f431-4518-b3a6-db654f133df5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552646761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1552646761
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.742989962
Short name T217
Test name
Test status
Simulation time 8047418530 ps
CPU time 60.71 seconds
Started Jul 10 05:07:40 PM PDT 24
Finished Jul 10 05:08:42 PM PDT 24
Peak memory 219356 kb
Host smart-fe15dcfe-061e-447f-b9e2-c7beff8a2b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742989962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.742989962
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1181924359
Short name T317
Test name
Test status
Simulation time 6943344060 ps
CPU time 31.3 seconds
Started Jul 10 05:07:27 PM PDT 24
Finished Jul 10 05:07:59 PM PDT 24
Peak memory 219316 kb
Host smart-d82293a4-31ac-476b-8e05-f8f8ba93950d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1181924359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1181924359
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.710213070
Short name T17
Test name
Test status
Simulation time 7013290897 ps
CPU time 56.06 seconds
Started Jul 10 05:07:30 PM PDT 24
Finished Jul 10 05:08:27 PM PDT 24
Peak memory 216728 kb
Host smart-60e39ce3-f680-46e8-92eb-6eb7a8118da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710213070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.710213070
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.4007861812
Short name T360
Test name
Test status
Simulation time 79475087711 ps
CPU time 147.32 seconds
Started Jul 10 05:07:28 PM PDT 24
Finished Jul 10 05:09:57 PM PDT 24
Peak memory 219548 kb
Host smart-42326284-042f-4cba-a12f-28bd1b055633
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007861812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.4007861812
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3260167658
Short name T131
Test name
Test status
Simulation time 1643889733 ps
CPU time 13.52 seconds
Started Jul 10 05:07:36 PM PDT 24
Finished Jul 10 05:07:52 PM PDT 24
Peak memory 217064 kb
Host smart-b0fe06dc-0e05-4794-bd2d-93a557f6f5c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260167658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3260167658
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2426115509
Short name T163
Test name
Test status
Simulation time 65842845945 ps
CPU time 623.12 seconds
Started Jul 10 05:07:41 PM PDT 24
Finished Jul 10 05:18:05 PM PDT 24
Peak memory 238668 kb
Host smart-a8241335-b2c4-40ef-8b7a-9b6464415c56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426115509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2426115509
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.4109273195
Short name T181
Test name
Test status
Simulation time 30368795965 ps
CPU time 58.59 seconds
Started Jul 10 05:07:35 PM PDT 24
Finished Jul 10 05:08:36 PM PDT 24
Peak memory 219488 kb
Host smart-c4fc9f82-b1ff-4a2c-ae69-d14e9d986f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109273195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.4109273195
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.71433758
Short name T216
Test name
Test status
Simulation time 23239788195 ps
CPU time 32.41 seconds
Started Jul 10 05:07:36 PM PDT 24
Finished Jul 10 05:08:10 PM PDT 24
Peak memory 211988 kb
Host smart-6667422d-2462-4b17-9cb4-49a451523daa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=71433758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.71433758
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.423465459
Short name T70
Test name
Test status
Simulation time 9226880450 ps
CPU time 33.06 seconds
Started Jul 10 05:07:37 PM PDT 24
Finished Jul 10 05:08:13 PM PDT 24
Peak memory 217296 kb
Host smart-1851cde1-c6c3-4f3a-abee-9ba7219d7bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423465459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.423465459
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1704717482
Short name T95
Test name
Test status
Simulation time 7132051210 ps
CPU time 31.88 seconds
Started Jul 10 05:07:36 PM PDT 24
Finished Jul 10 05:08:10 PM PDT 24
Peak memory 220056 kb
Host smart-fb8e10ee-4078-4a21-8241-3c9f55399d41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704717482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1704717482
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3846789204
Short name T13
Test name
Test status
Simulation time 210285401900 ps
CPU time 4091.09 seconds
Started Jul 10 05:07:35 PM PDT 24
Finished Jul 10 06:15:48 PM PDT 24
Peak memory 252212 kb
Host smart-e2581d27-14cf-4013-bc70-8525afcc37bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846789204 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.3846789204
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3597928906
Short name T186
Test name
Test status
Simulation time 17442741387 ps
CPU time 32.2 seconds
Started Jul 10 05:07:35 PM PDT 24
Finished Jul 10 05:08:10 PM PDT 24
Peak memory 217508 kb
Host smart-121b6ae5-0954-44ab-8ebe-6a98516cd121
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597928906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3597928906
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3766803883
Short name T351
Test name
Test status
Simulation time 38645940663 ps
CPU time 316.03 seconds
Started Jul 10 05:07:38 PM PDT 24
Finished Jul 10 05:12:57 PM PDT 24
Peak memory 240472 kb
Host smart-cc43399c-cc6a-4a37-8c44-445024d32853
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766803883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3766803883
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1190089227
Short name T27
Test name
Test status
Simulation time 1376205305 ps
CPU time 19.18 seconds
Started Jul 10 05:07:37 PM PDT 24
Finished Jul 10 05:07:59 PM PDT 24
Peak memory 219316 kb
Host smart-19843f81-d404-4a8f-bcb5-85cbdd5ebaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190089227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1190089227
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1790836132
Short name T212
Test name
Test status
Simulation time 3971665665 ps
CPU time 16.54 seconds
Started Jul 10 05:07:35 PM PDT 24
Finished Jul 10 05:07:53 PM PDT 24
Peak memory 218864 kb
Host smart-820ded87-5b7d-4f0d-a3e8-4f21782cc335
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1790836132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1790836132
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1386536278
Short name T71
Test name
Test status
Simulation time 37869265721 ps
CPU time 44.95 seconds
Started Jul 10 05:07:38 PM PDT 24
Finished Jul 10 05:08:25 PM PDT 24
Peak memory 216396 kb
Host smart-2845f9d2-a7f6-485f-80da-65ca3d93eefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386536278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1386536278
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2434151040
Short name T273
Test name
Test status
Simulation time 234302420 ps
CPU time 11.26 seconds
Started Jul 10 05:07:36 PM PDT 24
Finished Jul 10 05:07:50 PM PDT 24
Peak memory 214796 kb
Host smart-95e84f86-b7e7-4880-b4e1-d0f8c761f526
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434151040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2434151040
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.763552132
Short name T245
Test name
Test status
Simulation time 7673734169 ps
CPU time 30.74 seconds
Started Jul 10 05:07:38 PM PDT 24
Finished Jul 10 05:08:11 PM PDT 24
Peak memory 217440 kb
Host smart-7fce86bb-cc91-425f-8356-b57b7920dd03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763552132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.763552132
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2091927725
Short name T141
Test name
Test status
Simulation time 13562105694 ps
CPU time 156.84 seconds
Started Jul 10 05:07:36 PM PDT 24
Finished Jul 10 05:10:15 PM PDT 24
Peak memory 236044 kb
Host smart-37cf3dc3-7ab4-4be6-892a-c8bb1decbc33
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091927725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2091927725
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.4276687875
Short name T328
Test name
Test status
Simulation time 390843750 ps
CPU time 19.3 seconds
Started Jul 10 05:07:37 PM PDT 24
Finished Jul 10 05:07:59 PM PDT 24
Peak memory 219248 kb
Host smart-acee8b11-6123-473c-ad77-d8472ace0f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276687875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.4276687875
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1058132054
Short name T336
Test name
Test status
Simulation time 7013462900 ps
CPU time 28.68 seconds
Started Jul 10 05:07:42 PM PDT 24
Finished Jul 10 05:08:11 PM PDT 24
Peak memory 217668 kb
Host smart-72759438-3eb4-47bb-87cc-1a87dbe3f6c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1058132054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1058132054
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.2253889353
Short name T284
Test name
Test status
Simulation time 688472681 ps
CPU time 20.47 seconds
Started Jul 10 05:07:37 PM PDT 24
Finished Jul 10 05:08:00 PM PDT 24
Peak memory 216276 kb
Host smart-a13a6fe3-3f82-4b61-8444-85a26eee5561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253889353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.2253889353
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2386175367
Short name T321
Test name
Test status
Simulation time 15841180193 ps
CPU time 80.85 seconds
Started Jul 10 05:07:36 PM PDT 24
Finished Jul 10 05:08:59 PM PDT 24
Peak memory 219336 kb
Host smart-e4836842-db3f-4069-91ac-621ced53da2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386175367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2386175367
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.44330455
Short name T171
Test name
Test status
Simulation time 171020859 ps
CPU time 8.35 seconds
Started Jul 10 05:07:36 PM PDT 24
Finished Jul 10 05:07:47 PM PDT 24
Peak memory 217120 kb
Host smart-f698b3e2-5931-4bc7-8f0b-da5df1c92100
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44330455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.44330455
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.671797906
Short name T242
Test name
Test status
Simulation time 21339663361 ps
CPU time 351.27 seconds
Started Jul 10 05:07:35 PM PDT 24
Finished Jul 10 05:13:28 PM PDT 24
Peak memory 218600 kb
Host smart-18036ff6-fedd-43f9-9d91-58e9491b0829
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671797906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.671797906
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1554648571
Short name T214
Test name
Test status
Simulation time 19688576293 ps
CPU time 63.29 seconds
Started Jul 10 05:07:37 PM PDT 24
Finished Jul 10 05:08:43 PM PDT 24
Peak memory 219356 kb
Host smart-2cf7224a-b7f5-4888-a15c-7770af2ef17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554648571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1554648571
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.924202215
Short name T151
Test name
Test status
Simulation time 14487155802 ps
CPU time 32.09 seconds
Started Jul 10 05:07:36 PM PDT 24
Finished Jul 10 05:08:11 PM PDT 24
Peak memory 219344 kb
Host smart-f8e5fe74-00c6-4bd8-b7bf-49d242d404ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=924202215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.924202215
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1627561294
Short name T220
Test name
Test status
Simulation time 691550212 ps
CPU time 19.41 seconds
Started Jul 10 05:07:36 PM PDT 24
Finished Jul 10 05:07:58 PM PDT 24
Peak memory 217276 kb
Host smart-59cd02bd-696c-40c0-8ab2-0eddc5367b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627561294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1627561294
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2782373810
Short name T119
Test name
Test status
Simulation time 2318985656 ps
CPU time 47.32 seconds
Started Jul 10 05:07:38 PM PDT 24
Finished Jul 10 05:08:28 PM PDT 24
Peak memory 219288 kb
Host smart-dd8b7f47-173c-4e04-b2ab-6854200a3199
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782373810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2782373810
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3395512874
Short name T221
Test name
Test status
Simulation time 10461663732 ps
CPU time 22.73 seconds
Started Jul 10 05:07:36 PM PDT 24
Finished Jul 10 05:08:02 PM PDT 24
Peak memory 217444 kb
Host smart-08205666-058c-4299-89fa-f92aec72655f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395512874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3395512874
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.949534028
Short name T206
Test name
Test status
Simulation time 54645439755 ps
CPU time 379.87 seconds
Started Jul 10 05:07:36 PM PDT 24
Finished Jul 10 05:13:58 PM PDT 24
Peak memory 233788 kb
Host smart-cf9563d3-ab57-42c6-baab-9d6d0958e676
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949534028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.949534028
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.538671311
Short name T357
Test name
Test status
Simulation time 28746807954 ps
CPU time 48.53 seconds
Started Jul 10 05:07:38 PM PDT 24
Finished Jul 10 05:08:29 PM PDT 24
Peak memory 219292 kb
Host smart-fcc12832-67e9-4351-93f3-4dc474a5bda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538671311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.538671311
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3856153077
Short name T301
Test name
Test status
Simulation time 4022157416 ps
CPU time 33.4 seconds
Started Jul 10 05:07:37 PM PDT 24
Finished Jul 10 05:08:13 PM PDT 24
Peak memory 211416 kb
Host smart-3190ff67-7152-4b2f-9f33-dff30a2e1eb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3856153077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3856153077
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.991177432
Short name T248
Test name
Test status
Simulation time 10186540716 ps
CPU time 55.97 seconds
Started Jul 10 05:07:37 PM PDT 24
Finished Jul 10 05:08:35 PM PDT 24
Peak memory 215816 kb
Host smart-6ef0e9ba-1ccc-4c0d-bc93-7c491a74bc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991177432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.991177432
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3972992964
Short name T101
Test name
Test status
Simulation time 29618902749 ps
CPU time 75.58 seconds
Started Jul 10 05:07:37 PM PDT 24
Finished Jul 10 05:08:55 PM PDT 24
Peak memory 219628 kb
Host smart-0f7b6ea5-7ed2-4281-9bf5-cdfdff3a6293
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972992964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3972992964
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1164028874
Short name T347
Test name
Test status
Simulation time 4183842878 ps
CPU time 20.77 seconds
Started Jul 10 05:07:47 PM PDT 24
Finished Jul 10 05:08:10 PM PDT 24
Peak memory 217132 kb
Host smart-64bbd855-15ba-4645-a0be-d3da7f69fc0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164028874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1164028874
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1264242392
Short name T298
Test name
Test status
Simulation time 72709429931 ps
CPU time 304.93 seconds
Started Jul 10 05:07:37 PM PDT 24
Finished Jul 10 05:12:44 PM PDT 24
Peak memory 228676 kb
Host smart-e933d845-5df8-4711-b614-93e240443734
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264242392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1264242392
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.991661868
Short name T209
Test name
Test status
Simulation time 13397327568 ps
CPU time 58.8 seconds
Started Jul 10 05:07:47 PM PDT 24
Finished Jul 10 05:08:48 PM PDT 24
Peak memory 219380 kb
Host smart-df2be645-8bb8-46f3-8184-16b7a27609be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991661868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.991661868
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1833048505
Short name T282
Test name
Test status
Simulation time 6907946463 ps
CPU time 30.04 seconds
Started Jul 10 05:07:39 PM PDT 24
Finished Jul 10 05:08:11 PM PDT 24
Peak memory 211984 kb
Host smart-90b0f6f2-4b1d-440c-aad6-f5b0e881ff60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1833048505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1833048505
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2884763960
Short name T120
Test name
Test status
Simulation time 15357144100 ps
CPU time 61.69 seconds
Started Jul 10 05:07:40 PM PDT 24
Finished Jul 10 05:08:43 PM PDT 24
Peak memory 216592 kb
Host smart-dfb33bbf-aa59-466a-bc51-b37096ca16fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884763960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2884763960
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1510371242
Short name T302
Test name
Test status
Simulation time 2937098467 ps
CPU time 72.65 seconds
Started Jul 10 05:07:40 PM PDT 24
Finished Jul 10 05:08:54 PM PDT 24
Peak memory 220788 kb
Host smart-fc0f7e16-0617-40b0-bce6-94e8528bc675
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510371242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1510371242
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.943583036
Short name T146
Test name
Test status
Simulation time 174536758 ps
CPU time 8.4 seconds
Started Jul 10 05:07:46 PM PDT 24
Finished Jul 10 05:07:57 PM PDT 24
Peak memory 217072 kb
Host smart-533c40cd-a8f1-4fc8-bcc2-7da086b296ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943583036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.943583036
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.4094510100
Short name T356
Test name
Test status
Simulation time 274892446370 ps
CPU time 721.03 seconds
Started Jul 10 05:07:47 PM PDT 24
Finished Jul 10 05:19:50 PM PDT 24
Peak memory 219464 kb
Host smart-abb3ee1a-aaf1-4abe-b56a-6dc1a35637d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094510100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.4094510100
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3973303499
Short name T323
Test name
Test status
Simulation time 7902084834 ps
CPU time 65.09 seconds
Started Jul 10 05:07:47 PM PDT 24
Finished Jul 10 05:08:54 PM PDT 24
Peak memory 219328 kb
Host smart-c7cceeb2-3a9e-4469-9d7d-71a3454e92cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973303499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3973303499
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1655147880
Short name T256
Test name
Test status
Simulation time 1081423650 ps
CPU time 17.14 seconds
Started Jul 10 05:07:45 PM PDT 24
Finished Jul 10 05:08:03 PM PDT 24
Peak memory 219252 kb
Host smart-6f3b7dd8-1187-4f74-8f8f-8b24b8969e47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1655147880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1655147880
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1511664768
Short name T305
Test name
Test status
Simulation time 7230116987 ps
CPU time 57.01 seconds
Started Jul 10 05:07:45 PM PDT 24
Finished Jul 10 05:08:43 PM PDT 24
Peak memory 216624 kb
Host smart-4317d247-bd8b-4dab-9ea5-93f36325196e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511664768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1511664768
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.4113220507
Short name T252
Test name
Test status
Simulation time 57241940934 ps
CPU time 101.17 seconds
Started Jul 10 05:07:45 PM PDT 24
Finished Jul 10 05:09:27 PM PDT 24
Peak memory 219368 kb
Host smart-d528e7b0-86a8-4b73-b935-869f58cec2bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113220507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.4113220507
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3102706350
Short name T272
Test name
Test status
Simulation time 494585388 ps
CPU time 10.24 seconds
Started Jul 10 05:07:49 PM PDT 24
Finished Jul 10 05:08:01 PM PDT 24
Peak memory 217108 kb
Host smart-d7904402-99fe-4858-849e-641f33a8ff79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102706350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3102706350
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3554675713
Short name T115
Test name
Test status
Simulation time 123750653247 ps
CPU time 401.63 seconds
Started Jul 10 05:07:47 PM PDT 24
Finished Jul 10 05:14:30 PM PDT 24
Peak memory 227356 kb
Host smart-57faf528-91af-4646-a66d-acaabc3959c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554675713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3554675713
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1003264848
Short name T341
Test name
Test status
Simulation time 1822419359 ps
CPU time 31.48 seconds
Started Jul 10 05:07:49 PM PDT 24
Finished Jul 10 05:08:23 PM PDT 24
Peak memory 219292 kb
Host smart-ba3f2d44-7efe-42b0-8b58-7062774d5f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003264848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1003264848
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1596465660
Short name T251
Test name
Test status
Simulation time 8901631061 ps
CPU time 23.54 seconds
Started Jul 10 05:07:44 PM PDT 24
Finished Jul 10 05:08:09 PM PDT 24
Peak memory 217616 kb
Host smart-c91c8c3b-ff1b-49ae-b676-efc788a0f1b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1596465660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1596465660
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3225823206
Short name T16
Test name
Test status
Simulation time 46401915234 ps
CPU time 74.77 seconds
Started Jul 10 05:07:48 PM PDT 24
Finished Jul 10 05:09:05 PM PDT 24
Peak memory 216212 kb
Host smart-dfbe971f-2ab0-467a-a3d0-7395b2435b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225823206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3225823206
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1730433755
Short name T121
Test name
Test status
Simulation time 20700364182 ps
CPU time 62.61 seconds
Started Jul 10 05:07:48 PM PDT 24
Finished Jul 10 05:08:53 PM PDT 24
Peak memory 219252 kb
Host smart-e0b184ed-c583-48b2-aa71-867ff73ee6c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730433755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1730433755
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.470198683
Short name T225
Test name
Test status
Simulation time 661126211 ps
CPU time 8.46 seconds
Started Jul 10 05:06:50 PM PDT 24
Finished Jul 10 05:07:02 PM PDT 24
Peak memory 217108 kb
Host smart-7a53947f-c7ae-43c1-aa17-1fab97e14963
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470198683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.470198683
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2217858664
Short name T362
Test name
Test status
Simulation time 5752738737 ps
CPU time 158.69 seconds
Started Jul 10 05:06:52 PM PDT 24
Finished Jul 10 05:09:34 PM PDT 24
Peak memory 219484 kb
Host smart-5a064588-12f2-4c55-8115-a4bcbe62b26a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217858664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2217858664
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3243590467
Short name T296
Test name
Test status
Simulation time 5903245379 ps
CPU time 29.56 seconds
Started Jul 10 05:06:50 PM PDT 24
Finished Jul 10 05:07:22 PM PDT 24
Peak memory 219300 kb
Host smart-356de0a4-3295-489b-9f8d-88065e6a6e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243590467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3243590467
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.628108711
Short name T11
Test name
Test status
Simulation time 28169597411 ps
CPU time 23.39 seconds
Started Jul 10 05:06:50 PM PDT 24
Finished Jul 10 05:07:17 PM PDT 24
Peak memory 217856 kb
Host smart-02b1d176-1a0e-460b-9eed-e1515259e041
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=628108711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.628108711
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2556582372
Short name T253
Test name
Test status
Simulation time 19610104440 ps
CPU time 55.78 seconds
Started Jul 10 05:06:50 PM PDT 24
Finished Jul 10 05:07:49 PM PDT 24
Peak memory 216712 kb
Host smart-872c877c-3b2b-458c-8380-3d7d555879e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556582372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2556582372
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.271892162
Short name T261
Test name
Test status
Simulation time 14488980058 ps
CPU time 132.09 seconds
Started Jul 10 05:06:51 PM PDT 24
Finished Jul 10 05:09:06 PM PDT 24
Peak memory 219584 kb
Host smart-65505d10-bb9d-4ab4-b437-f7001ea6158e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271892162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.271892162
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3390632358
Short name T57
Test name
Test status
Simulation time 4860719111 ps
CPU time 15.47 seconds
Started Jul 10 05:07:47 PM PDT 24
Finished Jul 10 05:08:05 PM PDT 24
Peak memory 217528 kb
Host smart-3fac5cfe-8935-4214-9d74-bad87fcde072
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390632358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3390632358
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1156851334
Short name T21
Test name
Test status
Simulation time 75238757766 ps
CPU time 385.13 seconds
Started Jul 10 05:07:47 PM PDT 24
Finished Jul 10 05:14:14 PM PDT 24
Peak memory 226044 kb
Host smart-0cbc5e5e-a555-477b-a78e-e983aeaa77ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156851334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1156851334
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1887891348
Short name T37
Test name
Test status
Simulation time 332371257 ps
CPU time 19.54 seconds
Started Jul 10 05:07:47 PM PDT 24
Finished Jul 10 05:08:09 PM PDT 24
Peak memory 219320 kb
Host smart-408c73d0-7ead-4f0e-935c-0a830b216d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887891348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1887891348
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1180456906
Short name T100
Test name
Test status
Simulation time 16945794640 ps
CPU time 30.06 seconds
Started Jul 10 05:07:45 PM PDT 24
Finished Jul 10 05:08:17 PM PDT 24
Peak memory 219608 kb
Host smart-da0c155c-4f32-46d4-b988-56f2029cd31b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1180456906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1180456906
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.4129942314
Short name T96
Test name
Test status
Simulation time 27758810091 ps
CPU time 204.21 seconds
Started Jul 10 05:07:45 PM PDT 24
Finished Jul 10 05:11:11 PM PDT 24
Peak memory 222376 kb
Host smart-3d617664-91a2-4705-9984-bc9ac3c967dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129942314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.4129942314
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.3680150464
Short name T44
Test name
Test status
Simulation time 15373835784 ps
CPU time 536.94 seconds
Started Jul 10 05:07:48 PM PDT 24
Finished Jul 10 05:16:48 PM PDT 24
Peak memory 235408 kb
Host smart-0fbc33d1-fda6-4268-9012-f5b06bdb350d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680150464 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.3680150464
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1658263799
Short name T271
Test name
Test status
Simulation time 60429383706 ps
CPU time 27.51 seconds
Started Jul 10 05:07:47 PM PDT 24
Finished Jul 10 05:08:16 PM PDT 24
Peak memory 217472 kb
Host smart-bb061b6a-5516-44a7-a005-7b73650b5b91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658263799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1658263799
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1525496735
Short name T35
Test name
Test status
Simulation time 144875839144 ps
CPU time 721.02 seconds
Started Jul 10 05:07:47 PM PDT 24
Finished Jul 10 05:19:50 PM PDT 24
Peak memory 216968 kb
Host smart-8f44ce85-92c2-480e-8b11-37473c221b28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525496735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1525496735
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.784286980
Short name T329
Test name
Test status
Simulation time 1571267222 ps
CPU time 19.74 seconds
Started Jul 10 05:07:49 PM PDT 24
Finished Jul 10 05:08:11 PM PDT 24
Peak memory 219296 kb
Host smart-73faa5a4-4002-4e83-a95a-d37f0a515392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784286980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.784286980
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1374208688
Short name T197
Test name
Test status
Simulation time 9573544131 ps
CPU time 23.21 seconds
Started Jul 10 05:07:48 PM PDT 24
Finished Jul 10 05:08:13 PM PDT 24
Peak memory 217716 kb
Host smart-4a9bfe9b-ca1d-4c0c-b24e-8388096cc1cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1374208688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1374208688
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3988558836
Short name T224
Test name
Test status
Simulation time 1319220678 ps
CPU time 20.13 seconds
Started Jul 10 05:07:46 PM PDT 24
Finished Jul 10 05:08:08 PM PDT 24
Peak memory 216748 kb
Host smart-13c57af7-a7d3-4a31-99f4-8bea3b4445ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988558836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3988558836
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2699206948
Short name T150
Test name
Test status
Simulation time 8884732827 ps
CPU time 35.85 seconds
Started Jul 10 05:07:49 PM PDT 24
Finished Jul 10 05:08:27 PM PDT 24
Peak memory 214788 kb
Host smart-55251387-0da5-499e-9183-737954148a73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699206948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2699206948
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.357849960
Short name T359
Test name
Test status
Simulation time 3187710432 ps
CPU time 27.64 seconds
Started Jul 10 05:07:47 PM PDT 24
Finished Jul 10 05:08:17 PM PDT 24
Peak memory 217216 kb
Host smart-d0d8b627-6fac-4f46-a412-eb0b45b5a754
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357849960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.357849960
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2006239033
Short name T352
Test name
Test status
Simulation time 48222736018 ps
CPU time 493.42 seconds
Started Jul 10 05:07:45 PM PDT 24
Finished Jul 10 05:15:59 PM PDT 24
Peak memory 237264 kb
Host smart-21e1f823-e548-4b4b-89be-3f8d2f03f246
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006239033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2006239033
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3627494614
Short name T342
Test name
Test status
Simulation time 1738497466 ps
CPU time 18.72 seconds
Started Jul 10 05:07:49 PM PDT 24
Finished Jul 10 05:08:10 PM PDT 24
Peak memory 219240 kb
Host smart-abc6ddfb-2471-4427-9af8-20068c09b8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627494614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3627494614
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2338559440
Short name T333
Test name
Test status
Simulation time 288388269 ps
CPU time 10.07 seconds
Started Jul 10 05:07:51 PM PDT 24
Finished Jul 10 05:08:02 PM PDT 24
Peak memory 219272 kb
Host smart-3ca0221a-fc41-445e-9781-a061d4b008b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2338559440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2338559440
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2703898566
Short name T161
Test name
Test status
Simulation time 4509022109 ps
CPU time 44.34 seconds
Started Jul 10 05:07:47 PM PDT 24
Finished Jul 10 05:08:33 PM PDT 24
Peak memory 216932 kb
Host smart-94a82de0-a29a-459a-a500-7f56df7d45f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703898566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2703898566
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1729072868
Short name T130
Test name
Test status
Simulation time 98834750058 ps
CPU time 94.97 seconds
Started Jul 10 05:07:50 PM PDT 24
Finished Jul 10 05:09:27 PM PDT 24
Peak memory 219620 kb
Host smart-2b90bbce-8b51-4751-bdc4-b073c9c22233
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729072868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1729072868
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2414874748
Short name T355
Test name
Test status
Simulation time 689655430 ps
CPU time 8.53 seconds
Started Jul 10 05:07:57 PM PDT 24
Finished Jul 10 05:08:07 PM PDT 24
Peak memory 217148 kb
Host smart-d027b3ad-40d7-4cc3-9836-7dea2ebf7b80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414874748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2414874748
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3934180987
Short name T337
Test name
Test status
Simulation time 33435318019 ps
CPU time 358.7 seconds
Started Jul 10 05:07:55 PM PDT 24
Finished Jul 10 05:13:55 PM PDT 24
Peak memory 235880 kb
Host smart-90df0e88-a33c-4647-a9ce-04916d4ff71c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934180987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3934180987
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2632362334
Short name T344
Test name
Test status
Simulation time 689939092 ps
CPU time 18.78 seconds
Started Jul 10 05:07:53 PM PDT 24
Finished Jul 10 05:08:14 PM PDT 24
Peak memory 219228 kb
Host smart-4929df41-7dfc-4920-b723-fd429d7de03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632362334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2632362334
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.798253710
Short name T327
Test name
Test status
Simulation time 25674743220 ps
CPU time 26.33 seconds
Started Jul 10 05:07:56 PM PDT 24
Finished Jul 10 05:08:23 PM PDT 24
Peak memory 211860 kb
Host smart-e1ec01b7-fc37-4db1-bc57-46594f410736
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=798253710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.798253710
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.4115581304
Short name T218
Test name
Test status
Simulation time 9732731930 ps
CPU time 64.08 seconds
Started Jul 10 05:07:47 PM PDT 24
Finished Jul 10 05:08:53 PM PDT 24
Peak memory 216552 kb
Host smart-04a875fe-4242-426c-9b1b-3abe234ca199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115581304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.4115581304
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2346638773
Short name T332
Test name
Test status
Simulation time 9806137812 ps
CPU time 94.78 seconds
Started Jul 10 05:07:58 PM PDT 24
Finished Jul 10 05:09:34 PM PDT 24
Peak memory 219336 kb
Host smart-1a31830e-ef83-4173-a26a-d0f8a31e1ae6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346638773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2346638773
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1930927979
Short name T143
Test name
Test status
Simulation time 11080897396 ps
CPU time 23.88 seconds
Started Jul 10 05:07:53 PM PDT 24
Finished Jul 10 05:08:18 PM PDT 24
Peak memory 217580 kb
Host smart-ecb6c97d-008c-4d22-a3a6-ae86a9fc7775
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930927979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1930927979
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2165057294
Short name T269
Test name
Test status
Simulation time 4502015032 ps
CPU time 313.17 seconds
Started Jul 10 05:07:53 PM PDT 24
Finished Jul 10 05:13:07 PM PDT 24
Peak memory 226136 kb
Host smart-b3b3f07b-110b-4f07-9e54-801aa637a5fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165057294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2165057294
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.963700432
Short name T36
Test name
Test status
Simulation time 1378034108 ps
CPU time 19.53 seconds
Started Jul 10 05:07:55 PM PDT 24
Finished Jul 10 05:08:16 PM PDT 24
Peak memory 219344 kb
Host smart-5e1bf86b-4435-4606-94d5-43e6191ab242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963700432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.963700432
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1528355167
Short name T235
Test name
Test status
Simulation time 1394945267 ps
CPU time 18.77 seconds
Started Jul 10 05:07:54 PM PDT 24
Finished Jul 10 05:08:15 PM PDT 24
Peak memory 219292 kb
Host smart-67c86f9a-8a51-489f-8bab-03c0b0712826
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1528355167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1528355167
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.914006656
Short name T213
Test name
Test status
Simulation time 2123203228 ps
CPU time 23.2 seconds
Started Jul 10 05:07:57 PM PDT 24
Finished Jul 10 05:08:22 PM PDT 24
Peak memory 216200 kb
Host smart-3fcc90ce-ebae-45f8-893b-2bf19882e5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914006656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.914006656
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.4170066256
Short name T139
Test name
Test status
Simulation time 44978418482 ps
CPU time 117.58 seconds
Started Jul 10 05:07:59 PM PDT 24
Finished Jul 10 05:09:58 PM PDT 24
Peak memory 219548 kb
Host smart-ba006c70-9ed7-48c6-9a00-c9927856c441
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170066256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.4170066256
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1974272875
Short name T295
Test name
Test status
Simulation time 3127095455 ps
CPU time 25.68 seconds
Started Jul 10 05:07:56 PM PDT 24
Finished Jul 10 05:08:23 PM PDT 24
Peak memory 217216 kb
Host smart-b8db84fb-9e46-41e6-8da7-1d80bda31c93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974272875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1974272875
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2247155791
Short name T173
Test name
Test status
Simulation time 7875166453 ps
CPU time 32.81 seconds
Started Jul 10 05:07:58 PM PDT 24
Finished Jul 10 05:08:32 PM PDT 24
Peak memory 219336 kb
Host smart-c39e257e-d4ba-474c-b6af-195d7d5fe6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247155791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2247155791
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2714893269
Short name T99
Test name
Test status
Simulation time 3902212068 ps
CPU time 30.82 seconds
Started Jul 10 05:07:54 PM PDT 24
Finished Jul 10 05:08:26 PM PDT 24
Peak memory 219264 kb
Host smart-5bd2983b-d91c-4fa8-8452-2b505b809599
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2714893269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2714893269
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3147869803
Short name T255
Test name
Test status
Simulation time 350627393 ps
CPU time 21.3 seconds
Started Jul 10 05:08:00 PM PDT 24
Finished Jul 10 05:08:22 PM PDT 24
Peak memory 217328 kb
Host smart-b13efef7-c04e-4485-9924-bf3c73042260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147869803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3147869803
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.75767551
Short name T249
Test name
Test status
Simulation time 96466009600 ps
CPU time 199.81 seconds
Started Jul 10 05:07:54 PM PDT 24
Finished Jul 10 05:11:15 PM PDT 24
Peak memory 220696 kb
Host smart-d0b3e14a-b716-4e9d-807f-60a7d0ec233e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75767551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 35.rom_ctrl_stress_all.75767551
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3706550620
Short name T189
Test name
Test status
Simulation time 2777672713 ps
CPU time 17.37 seconds
Started Jul 10 05:07:54 PM PDT 24
Finished Jul 10 05:08:12 PM PDT 24
Peak memory 217404 kb
Host smart-cf348496-4149-474d-a4e3-4e145135399a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706550620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3706550620
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1819115725
Short name T38
Test name
Test status
Simulation time 70198259439 ps
CPU time 548.88 seconds
Started Jul 10 05:07:55 PM PDT 24
Finished Jul 10 05:17:05 PM PDT 24
Peak memory 238572 kb
Host smart-b1c1c113-dc04-4f96-aa68-492a6ab7d374
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819115725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1819115725
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2632087786
Short name T247
Test name
Test status
Simulation time 18210136497 ps
CPU time 49.77 seconds
Started Jul 10 05:07:54 PM PDT 24
Finished Jul 10 05:08:45 PM PDT 24
Peak memory 219396 kb
Host smart-1b7fd0c3-cb93-4a88-996f-5710bf655c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632087786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2632087786
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.621768821
Short name T330
Test name
Test status
Simulation time 1230499472 ps
CPU time 10.11 seconds
Started Jul 10 05:07:57 PM PDT 24
Finished Jul 10 05:08:08 PM PDT 24
Peak memory 219280 kb
Host smart-37e99581-379d-4171-a26e-cb1f9b0a7df5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=621768821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.621768821
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3657200641
Short name T142
Test name
Test status
Simulation time 17895980294 ps
CPU time 49.99 seconds
Started Jul 10 05:07:54 PM PDT 24
Finished Jul 10 05:08:46 PM PDT 24
Peak memory 216908 kb
Host smart-9d3c65f5-6304-4e0d-8718-6c1137d178d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657200641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3657200641
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3698960452
Short name T310
Test name
Test status
Simulation time 8679468752 ps
CPU time 105.69 seconds
Started Jul 10 05:07:54 PM PDT 24
Finished Jul 10 05:09:41 PM PDT 24
Peak memory 219312 kb
Host smart-75661189-2d2c-4aa8-9f4b-d05a65d390f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698960452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3698960452
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.393854928
Short name T45
Test name
Test status
Simulation time 49875857158 ps
CPU time 569.44 seconds
Started Jul 10 05:07:55 PM PDT 24
Finished Jul 10 05:17:26 PM PDT 24
Peak memory 229724 kb
Host smart-a90c71c5-82dd-4e8b-856e-7989c0f422ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393854928 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.393854928
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1785551194
Short name T263
Test name
Test status
Simulation time 3183472720 ps
CPU time 27.61 seconds
Started Jul 10 05:07:59 PM PDT 24
Finished Jul 10 05:08:27 PM PDT 24
Peak memory 217284 kb
Host smart-16203acc-49d4-41d0-96ae-afbdcd980dc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785551194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1785551194
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2273360885
Short name T34
Test name
Test status
Simulation time 3048936643 ps
CPU time 201.56 seconds
Started Jul 10 05:07:56 PM PDT 24
Finished Jul 10 05:11:19 PM PDT 24
Peak memory 219532 kb
Host smart-2c18696b-1d87-46c3-80ae-41a57382307a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273360885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2273360885
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.250063160
Short name T215
Test name
Test status
Simulation time 25216273961 ps
CPU time 57.65 seconds
Started Jul 10 05:08:00 PM PDT 24
Finished Jul 10 05:08:59 PM PDT 24
Peak memory 219320 kb
Host smart-5cccfa41-ebc4-4434-a861-a412dfa07caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250063160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.250063160
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1459161392
Short name T280
Test name
Test status
Simulation time 1841386930 ps
CPU time 21.14 seconds
Started Jul 10 05:07:57 PM PDT 24
Finished Jul 10 05:08:20 PM PDT 24
Peak memory 211512 kb
Host smart-a9a3b049-1599-4a5e-8194-a795f901e1a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1459161392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1459161392
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.4191575621
Short name T219
Test name
Test status
Simulation time 20610396575 ps
CPU time 32.23 seconds
Started Jul 10 05:07:53 PM PDT 24
Finished Jul 10 05:08:27 PM PDT 24
Peak memory 217512 kb
Host smart-471055c0-e764-47cc-ba9a-8651cd3ec9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191575621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.4191575621
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2561952187
Short name T240
Test name
Test status
Simulation time 15764357015 ps
CPU time 31.23 seconds
Started Jul 10 05:07:53 PM PDT 24
Finished Jul 10 05:08:26 PM PDT 24
Peak memory 219200 kb
Host smart-53165e5b-e563-449c-9a7a-57e0fd856502
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561952187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2561952187
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3350280654
Short name T358
Test name
Test status
Simulation time 2135742540 ps
CPU time 21.03 seconds
Started Jul 10 05:08:02 PM PDT 24
Finished Jul 10 05:08:25 PM PDT 24
Peak memory 217232 kb
Host smart-c23d4a2e-a273-4701-b1a4-00729f237f4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350280654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3350280654
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3276510090
Short name T123
Test name
Test status
Simulation time 11319157695 ps
CPU time 175.14 seconds
Started Jul 10 05:08:06 PM PDT 24
Finished Jul 10 05:11:02 PM PDT 24
Peak memory 229544 kb
Host smart-7b341dcb-4d87-4d35-866d-5d41c1818a52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276510090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3276510090
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3557857195
Short name T205
Test name
Test status
Simulation time 5793548474 ps
CPU time 53.74 seconds
Started Jul 10 05:08:01 PM PDT 24
Finished Jul 10 05:08:57 PM PDT 24
Peak memory 219324 kb
Host smart-20d7f184-8220-4313-a897-70cdf479f4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557857195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3557857195
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2001982458
Short name T147
Test name
Test status
Simulation time 8545663080 ps
CPU time 22.9 seconds
Started Jul 10 05:07:59 PM PDT 24
Finished Jul 10 05:08:24 PM PDT 24
Peak memory 211992 kb
Host smart-c32ff4b0-328c-42aa-a005-b255f30ccf72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2001982458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2001982458
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.788500773
Short name T136
Test name
Test status
Simulation time 2485940512 ps
CPU time 39.95 seconds
Started Jul 10 05:08:02 PM PDT 24
Finished Jul 10 05:08:44 PM PDT 24
Peak memory 216444 kb
Host smart-f9ab3673-b089-4736-8654-e40f4e6dc784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788500773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.788500773
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3688787019
Short name T316
Test name
Test status
Simulation time 24872853452 ps
CPU time 81.19 seconds
Started Jul 10 05:08:03 PM PDT 24
Finished Jul 10 05:09:26 PM PDT 24
Peak memory 219812 kb
Host smart-c495705e-c0f5-4df6-9465-ab6918b11779
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688787019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3688787019
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3549309679
Short name T339
Test name
Test status
Simulation time 1031728174 ps
CPU time 8.4 seconds
Started Jul 10 05:08:01 PM PDT 24
Finished Jul 10 05:08:12 PM PDT 24
Peak memory 216956 kb
Host smart-9f7d77e7-f2a3-4746-bb29-7ff2a5636f6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549309679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3549309679
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2454319887
Short name T170
Test name
Test status
Simulation time 70938230030 ps
CPU time 463.22 seconds
Started Jul 10 05:08:01 PM PDT 24
Finished Jul 10 05:15:46 PM PDT 24
Peak memory 240112 kb
Host smart-6a8f6e2a-4c85-44f8-bf9e-1bed4cf725c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454319887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2454319887
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.892261908
Short name T278
Test name
Test status
Simulation time 345962503 ps
CPU time 19.3 seconds
Started Jul 10 05:08:01 PM PDT 24
Finished Jul 10 05:08:23 PM PDT 24
Peak memory 219220 kb
Host smart-0188f97a-a500-43f9-9264-55f54bc73844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892261908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.892261908
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.4228952218
Short name T172
Test name
Test status
Simulation time 15436690542 ps
CPU time 30.1 seconds
Started Jul 10 05:08:01 PM PDT 24
Finished Jul 10 05:08:34 PM PDT 24
Peak memory 211560 kb
Host smart-dc28c134-60b2-4787-9451-f0cad05af6a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4228952218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.4228952218
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2927533839
Short name T74
Test name
Test status
Simulation time 347316672 ps
CPU time 20.22 seconds
Started Jul 10 05:08:03 PM PDT 24
Finished Jul 10 05:08:25 PM PDT 24
Peak memory 216200 kb
Host smart-8e6b294b-7464-47aa-a9cc-e9d40fd3aecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927533839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2927533839
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1509348819
Short name T289
Test name
Test status
Simulation time 26379289251 ps
CPU time 222.63 seconds
Started Jul 10 05:08:00 PM PDT 24
Finished Jul 10 05:11:44 PM PDT 24
Peak memory 220596 kb
Host smart-61743a64-231f-4311-b527-ec6da009d796
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509348819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1509348819
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.1104832656
Short name T42
Test name
Test status
Simulation time 28863535786 ps
CPU time 3565.75 seconds
Started Jul 10 05:08:07 PM PDT 24
Finished Jul 10 06:07:34 PM PDT 24
Peak memory 235756 kb
Host smart-11c7d71d-1f96-40cf-9575-f5503331f121
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104832656 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.1104832656
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2204096301
Short name T10
Test name
Test status
Simulation time 3325672457 ps
CPU time 28.02 seconds
Started Jul 10 05:06:49 PM PDT 24
Finished Jul 10 05:07:20 PM PDT 24
Peak memory 217240 kb
Host smart-f16e26aa-95c0-4707-8e2f-da3ec44dd7ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204096301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2204096301
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2269421975
Short name T228
Test name
Test status
Simulation time 87672457178 ps
CPU time 481.34 seconds
Started Jul 10 05:06:50 PM PDT 24
Finished Jul 10 05:14:55 PM PDT 24
Peak memory 237992 kb
Host smart-717dc512-d72f-42f6-b89e-2bd01f9e1eb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269421975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2269421975
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1780932542
Short name T26
Test name
Test status
Simulation time 7221530836 ps
CPU time 42.2 seconds
Started Jul 10 05:06:50 PM PDT 24
Finished Jul 10 05:07:35 PM PDT 24
Peak memory 219152 kb
Host smart-0e63c959-406f-4713-853a-b893676b96f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780932542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1780932542
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1717038238
Short name T148
Test name
Test status
Simulation time 14773786641 ps
CPU time 30.13 seconds
Started Jul 10 05:06:49 PM PDT 24
Finished Jul 10 05:07:22 PM PDT 24
Peak memory 219380 kb
Host smart-e0788113-ab8b-4962-9c11-48241b1d1d6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1717038238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1717038238
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.4027246576
Short name T28
Test name
Test status
Simulation time 4271985485 ps
CPU time 251.41 seconds
Started Jul 10 05:06:51 PM PDT 24
Finished Jul 10 05:11:06 PM PDT 24
Peak memory 238940 kb
Host smart-7a49a5cc-cf1b-4819-99af-b15cf5d3678a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027246576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.4027246576
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1551439447
Short name T168
Test name
Test status
Simulation time 2967712505 ps
CPU time 33.26 seconds
Started Jul 10 05:06:49 PM PDT 24
Finished Jul 10 05:07:25 PM PDT 24
Peak memory 215852 kb
Host smart-befebf6e-3ddc-4827-858c-2c6e6287ce56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551439447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1551439447
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2846415766
Short name T126
Test name
Test status
Simulation time 1762996662 ps
CPU time 62.46 seconds
Started Jul 10 05:06:49 PM PDT 24
Finished Jul 10 05:07:54 PM PDT 24
Peak memory 219244 kb
Host smart-66842429-0099-40eb-871c-fd6b32b67eda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846415766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2846415766
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3098951608
Short name T306
Test name
Test status
Simulation time 2632119899 ps
CPU time 23.77 seconds
Started Jul 10 05:08:07 PM PDT 24
Finished Jul 10 05:08:32 PM PDT 24
Peak memory 217128 kb
Host smart-a2e84a63-a348-4247-922e-b7bd5b206d5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098951608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3098951608
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4088109826
Short name T262
Test name
Test status
Simulation time 24448079363 ps
CPU time 251.05 seconds
Started Jul 10 05:08:03 PM PDT 24
Finished Jul 10 05:12:15 PM PDT 24
Peak memory 240468 kb
Host smart-10adce84-89af-4112-86d0-d67f97614a64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088109826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.4088109826
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2862031871
Short name T244
Test name
Test status
Simulation time 14499997403 ps
CPU time 64.62 seconds
Started Jul 10 05:08:10 PM PDT 24
Finished Jul 10 05:09:16 PM PDT 24
Peak memory 219280 kb
Host smart-9ec22553-22ef-4c88-abde-d10270d583f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862031871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2862031871
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2077449148
Short name T98
Test name
Test status
Simulation time 2787422835 ps
CPU time 25.8 seconds
Started Jul 10 05:08:01 PM PDT 24
Finished Jul 10 05:08:29 PM PDT 24
Peak memory 219328 kb
Host smart-97f43aad-dc86-4298-8186-98efc2d5f469
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2077449148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2077449148
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1780731876
Short name T9
Test name
Test status
Simulation time 21049515163 ps
CPU time 55.83 seconds
Started Jul 10 05:08:01 PM PDT 24
Finished Jul 10 05:08:59 PM PDT 24
Peak memory 215728 kb
Host smart-4643890d-823f-4b4c-b8ca-e610a5e2d88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780731876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1780731876
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3927910462
Short name T159
Test name
Test status
Simulation time 530994887 ps
CPU time 34.05 seconds
Started Jul 10 05:08:03 PM PDT 24
Finished Jul 10 05:08:39 PM PDT 24
Peak memory 219252 kb
Host smart-a592c71b-b073-4515-a233-9081c73ed6bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927910462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3927910462
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.266989348
Short name T304
Test name
Test status
Simulation time 1475238740 ps
CPU time 16.82 seconds
Started Jul 10 05:08:09 PM PDT 24
Finished Jul 10 05:08:28 PM PDT 24
Peak memory 217236 kb
Host smart-d7621301-02c3-48f5-ab5c-3d034912e6d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266989348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.266989348
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2998532323
Short name T191
Test name
Test status
Simulation time 113519867259 ps
CPU time 648.75 seconds
Started Jul 10 05:08:06 PM PDT 24
Finished Jul 10 05:18:56 PM PDT 24
Peak memory 236616 kb
Host smart-eff7876d-eab4-4d0e-a943-2a34e40ee824
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998532323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2998532323
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3234716602
Short name T226
Test name
Test status
Simulation time 13799491605 ps
CPU time 59.67 seconds
Started Jul 10 05:08:10 PM PDT 24
Finished Jul 10 05:09:11 PM PDT 24
Peak memory 219280 kb
Host smart-245e1c59-0a31-4dc8-ae19-a517354e9318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234716602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3234716602
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.4240187562
Short name T183
Test name
Test status
Simulation time 180792285 ps
CPU time 10.76 seconds
Started Jul 10 05:08:08 PM PDT 24
Finished Jul 10 05:08:20 PM PDT 24
Peak memory 219240 kb
Host smart-83398a35-3edb-4aac-8da7-84dd4dcb12c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4240187562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.4240187562
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3037433261
Short name T204
Test name
Test status
Simulation time 37096365577 ps
CPU time 51.48 seconds
Started Jul 10 05:08:07 PM PDT 24
Finished Jul 10 05:09:00 PM PDT 24
Peak memory 217128 kb
Host smart-0c8a2e38-1e23-46d5-b182-d8001ff68491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037433261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3037433261
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2664385096
Short name T208
Test name
Test status
Simulation time 45395556157 ps
CPU time 63.43 seconds
Started Jul 10 05:08:06 PM PDT 24
Finished Jul 10 05:09:11 PM PDT 24
Peak memory 216968 kb
Host smart-f652ea4c-cfe2-4d8e-a8af-1b7cd6cc0560
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664385096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2664385096
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.4235732644
Short name T259
Test name
Test status
Simulation time 174675619 ps
CPU time 8.28 seconds
Started Jul 10 05:08:15 PM PDT 24
Finished Jul 10 05:08:24 PM PDT 24
Peak memory 217088 kb
Host smart-d5534ff5-00e0-4202-9ea1-73878846c6b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235732644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.4235732644
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2428158298
Short name T287
Test name
Test status
Simulation time 156487145070 ps
CPU time 588.33 seconds
Started Jul 10 05:08:06 PM PDT 24
Finished Jul 10 05:17:56 PM PDT 24
Peak memory 234188 kb
Host smart-07bfee75-55b8-4082-bfa7-858b44e98432
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428158298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2428158298
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2322623661
Short name T39
Test name
Test status
Simulation time 15749901195 ps
CPU time 43 seconds
Started Jul 10 05:08:07 PM PDT 24
Finished Jul 10 05:08:52 PM PDT 24
Peak memory 219316 kb
Host smart-f3c4a023-d45f-4d24-858e-4996c7cedb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322623661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2322623661
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.23328345
Short name T149
Test name
Test status
Simulation time 495494225 ps
CPU time 12.51 seconds
Started Jul 10 05:08:06 PM PDT 24
Finished Jul 10 05:08:19 PM PDT 24
Peak memory 219316 kb
Host smart-5e2171d0-4872-4c47-907d-fcea9840eb9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=23328345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.23328345
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2439954234
Short name T127
Test name
Test status
Simulation time 7875206012 ps
CPU time 75.41 seconds
Started Jul 10 05:08:06 PM PDT 24
Finished Jul 10 05:09:23 PM PDT 24
Peak memory 216812 kb
Host smart-2be63eb0-96bd-4bf3-8d34-5644e945834f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439954234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2439954234
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3329393180
Short name T117
Test name
Test status
Simulation time 39276082985 ps
CPU time 168.62 seconds
Started Jul 10 05:08:10 PM PDT 24
Finished Jul 10 05:11:00 PM PDT 24
Peak memory 227544 kb
Host smart-bbf048ff-7c9f-46a8-b93e-3e05e9e0d12f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329393180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3329393180
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3853274951
Short name T223
Test name
Test status
Simulation time 3762280371 ps
CPU time 30.49 seconds
Started Jul 10 05:08:21 PM PDT 24
Finished Jul 10 05:08:53 PM PDT 24
Peak memory 217256 kb
Host smart-1627ee17-7153-4ddf-a4ec-669fb8f7cb7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853274951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3853274951
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3095755570
Short name T176
Test name
Test status
Simulation time 20919173706 ps
CPU time 331.65 seconds
Started Jul 10 05:08:15 PM PDT 24
Finished Jul 10 05:13:48 PM PDT 24
Peak memory 235532 kb
Host smart-d8ff2445-768f-40a3-b247-005afc1b04e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095755570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3095755570
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1040912169
Short name T239
Test name
Test status
Simulation time 34065352668 ps
CPU time 67.64 seconds
Started Jul 10 05:08:15 PM PDT 24
Finished Jul 10 05:09:23 PM PDT 24
Peak memory 219300 kb
Host smart-4c3e5ca0-33fc-4b52-acb8-92cbea7d32f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040912169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1040912169
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2673386545
Short name T292
Test name
Test status
Simulation time 6527433208 ps
CPU time 22.77 seconds
Started Jul 10 05:08:17 PM PDT 24
Finished Jul 10 05:08:40 PM PDT 24
Peak memory 219380 kb
Host smart-2e694afb-de2b-4acc-853a-aae5c39ac9c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2673386545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2673386545
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2225152845
Short name T203
Test name
Test status
Simulation time 31379961251 ps
CPU time 72.19 seconds
Started Jul 10 05:08:17 PM PDT 24
Finished Jul 10 05:09:30 PM PDT 24
Peak memory 216800 kb
Host smart-3d189a8c-89df-41db-913f-9e96c4c83da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225152845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2225152845
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2824151995
Short name T18
Test name
Test status
Simulation time 13801489101 ps
CPU time 157.66 seconds
Started Jul 10 05:08:16 PM PDT 24
Finished Jul 10 05:10:54 PM PDT 24
Peak memory 222576 kb
Host smart-9348b773-b5f0-499a-bfff-4f9a05bb8d36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824151995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2824151995
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.1264196036
Short name T43
Test name
Test status
Simulation time 61787440984 ps
CPU time 831.8 seconds
Started Jul 10 05:08:14 PM PDT 24
Finished Jul 10 05:22:07 PM PDT 24
Peak memory 235808 kb
Host smart-e72d5644-a311-4d1b-a76d-b334b1910c66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264196036 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.1264196036
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3300075042
Short name T54
Test name
Test status
Simulation time 1033404592 ps
CPU time 9.89 seconds
Started Jul 10 05:08:23 PM PDT 24
Finished Jul 10 05:08:34 PM PDT 24
Peak memory 217244 kb
Host smart-1e15850f-3e62-4ba1-80d7-87eb72918329
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300075042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3300075042
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1933579998
Short name T246
Test name
Test status
Simulation time 321976156157 ps
CPU time 410.92 seconds
Started Jul 10 05:08:24 PM PDT 24
Finished Jul 10 05:15:16 PM PDT 24
Peak memory 237228 kb
Host smart-04697bd8-aeaf-4d09-a377-c4eb929cfdb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933579998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1933579998
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.512011830
Short name T238
Test name
Test status
Simulation time 10619953682 ps
CPU time 50.09 seconds
Started Jul 10 05:08:22 PM PDT 24
Finished Jul 10 05:09:13 PM PDT 24
Peak memory 219356 kb
Host smart-7fb9b1c5-5c06-42da-80c7-030e384d45fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512011830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.512011830
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.700729349
Short name T175
Test name
Test status
Simulation time 367059245 ps
CPU time 10.46 seconds
Started Jul 10 05:08:30 PM PDT 24
Finished Jul 10 05:08:41 PM PDT 24
Peak memory 219320 kb
Host smart-a43094bf-0105-42a8-ada2-3df3d7cdc9cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=700729349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.700729349
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2113092349
Short name T132
Test name
Test status
Simulation time 2041208625 ps
CPU time 24.39 seconds
Started Jul 10 05:08:23 PM PDT 24
Finished Jul 10 05:08:49 PM PDT 24
Peak memory 216360 kb
Host smart-7ddd8961-3477-478a-9fa3-34f23f03c09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113092349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2113092349
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2113092710
Short name T7
Test name
Test status
Simulation time 433510919 ps
CPU time 17.38 seconds
Started Jul 10 05:08:28 PM PDT 24
Finished Jul 10 05:08:46 PM PDT 24
Peak memory 219000 kb
Host smart-5b5991e2-ddfb-46f6-b4bd-fa057bb4109c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113092710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2113092710
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2736554084
Short name T164
Test name
Test status
Simulation time 3158158414 ps
CPU time 26.46 seconds
Started Jul 10 05:08:22 PM PDT 24
Finished Jul 10 05:08:50 PM PDT 24
Peak memory 217128 kb
Host smart-09e0a88c-5df9-4d0a-8176-2605d251875a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736554084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2736554084
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1312044454
Short name T32
Test name
Test status
Simulation time 131431982413 ps
CPU time 587.65 seconds
Started Jul 10 05:08:22 PM PDT 24
Finished Jul 10 05:18:10 PM PDT 24
Peak memory 233584 kb
Host smart-35687f93-1368-4d28-8148-2c74ef216c27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312044454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1312044454
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3152710134
Short name T8
Test name
Test status
Simulation time 6724693594 ps
CPU time 57.92 seconds
Started Jul 10 05:08:25 PM PDT 24
Finished Jul 10 05:09:23 PM PDT 24
Peak memory 219340 kb
Host smart-6519dee2-7f78-41f3-af4d-e8575c2ba205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152710134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3152710134
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.4116432476
Short name T309
Test name
Test status
Simulation time 365437663 ps
CPU time 10.51 seconds
Started Jul 10 05:08:21 PM PDT 24
Finished Jul 10 05:08:32 PM PDT 24
Peak memory 219316 kb
Host smart-be48b167-543b-4009-9eb7-c33b62f64efa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4116432476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.4116432476
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.3889204082
Short name T268
Test name
Test status
Simulation time 57774342617 ps
CPU time 71.88 seconds
Started Jul 10 05:08:31 PM PDT 24
Finished Jul 10 05:09:44 PM PDT 24
Peak memory 216076 kb
Host smart-3ba116ce-2e90-4fec-9246-6a13eeff690e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889204082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.3889204082
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3410644695
Short name T2
Test name
Test status
Simulation time 7016994981 ps
CPU time 37.09 seconds
Started Jul 10 05:08:25 PM PDT 24
Finished Jul 10 05:09:03 PM PDT 24
Peak memory 219184 kb
Host smart-4e35c6ad-561c-4e52-85df-66d658b5abc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410644695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3410644695
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3822137478
Short name T340
Test name
Test status
Simulation time 9829053586 ps
CPU time 33.95 seconds
Started Jul 10 05:08:33 PM PDT 24
Finished Jul 10 05:09:09 PM PDT 24
Peak memory 217400 kb
Host smart-699ca183-d237-4a5b-bfc6-6cf525e254da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822137478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3822137478
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1262976615
Short name T343
Test name
Test status
Simulation time 4548960431 ps
CPU time 275.43 seconds
Started Jul 10 05:08:29 PM PDT 24
Finished Jul 10 05:13:05 PM PDT 24
Peak memory 239484 kb
Host smart-0c6fa57b-05b4-4c13-8c4b-7122f6cb6b46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262976615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1262976615
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2854235019
Short name T227
Test name
Test status
Simulation time 7779268897 ps
CPU time 38.6 seconds
Started Jul 10 05:08:22 PM PDT 24
Finished Jul 10 05:09:01 PM PDT 24
Peak memory 219244 kb
Host smart-0f0f2e53-7a95-4635-b0f1-18bc71f102c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854235019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2854235019
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3525173646
Short name T174
Test name
Test status
Simulation time 3396970980 ps
CPU time 30.42 seconds
Started Jul 10 05:08:24 PM PDT 24
Finished Jul 10 05:08:55 PM PDT 24
Peak memory 211592 kb
Host smart-9c4fe017-d0ed-41f8-a3d7-cc9109d7c0ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3525173646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3525173646
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.2151058620
Short name T291
Test name
Test status
Simulation time 12370360640 ps
CPU time 53.68 seconds
Started Jul 10 05:08:25 PM PDT 24
Finished Jul 10 05:09:20 PM PDT 24
Peak memory 215912 kb
Host smart-f64005fe-178d-42aa-a550-0fc5e0e2f457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151058620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2151058620
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.580448782
Short name T156
Test name
Test status
Simulation time 2904014595 ps
CPU time 26.65 seconds
Started Jul 10 05:08:24 PM PDT 24
Finished Jul 10 05:08:51 PM PDT 24
Peak memory 214588 kb
Host smart-3d790eeb-fbb9-4072-ba73-de0b6eea6314
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580448782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.580448782
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3349047957
Short name T195
Test name
Test status
Simulation time 18123633532 ps
CPU time 29.77 seconds
Started Jul 10 05:08:32 PM PDT 24
Finished Jul 10 05:09:05 PM PDT 24
Peak memory 217528 kb
Host smart-21ee373f-14ee-459f-bf76-23f786938553
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349047957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3349047957
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2702409220
Short name T165
Test name
Test status
Simulation time 25499112076 ps
CPU time 260.01 seconds
Started Jul 10 05:08:33 PM PDT 24
Finished Jul 10 05:12:55 PM PDT 24
Peak memory 239672 kb
Host smart-dbb7e022-9b23-456d-9da6-102cb180dba9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702409220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2702409220
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1962682944
Short name T270
Test name
Test status
Simulation time 2995905574 ps
CPU time 18.91 seconds
Started Jul 10 05:08:32 PM PDT 24
Finished Jul 10 05:08:54 PM PDT 24
Peak memory 219296 kb
Host smart-6b567564-9080-4d0b-826d-f3d5a5d86d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962682944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1962682944
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3280100238
Short name T193
Test name
Test status
Simulation time 5295965544 ps
CPU time 26 seconds
Started Jul 10 05:08:32 PM PDT 24
Finished Jul 10 05:09:00 PM PDT 24
Peak memory 219332 kb
Host smart-827a0d8b-a19d-46d1-9363-0a458232b168
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3280100238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3280100238
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1950312747
Short name T320
Test name
Test status
Simulation time 21157210584 ps
CPU time 41.33 seconds
Started Jul 10 05:08:32 PM PDT 24
Finished Jul 10 05:09:15 PM PDT 24
Peak memory 217296 kb
Host smart-b6ce8aed-9db1-4ab4-91ed-2e126a8ff06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950312747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1950312747
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3127325545
Short name T19
Test name
Test status
Simulation time 768689603 ps
CPU time 10.71 seconds
Started Jul 10 05:08:34 PM PDT 24
Finished Jul 10 05:08:46 PM PDT 24
Peak memory 218728 kb
Host smart-3f7ba4aa-0ec1-4766-9b45-3d746a6c759b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127325545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3127325545
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.426147680
Short name T312
Test name
Test status
Simulation time 15941451019 ps
CPU time 28.04 seconds
Started Jul 10 05:08:33 PM PDT 24
Finished Jul 10 05:09:03 PM PDT 24
Peak memory 217416 kb
Host smart-73a360ac-bb7c-4bae-8177-8b44f7d4f7ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426147680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.426147680
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1250286687
Short name T293
Test name
Test status
Simulation time 614787469129 ps
CPU time 544.18 seconds
Started Jul 10 05:08:32 PM PDT 24
Finished Jul 10 05:17:38 PM PDT 24
Peak memory 225624 kb
Host smart-a7a050e7-ce39-44e5-ae63-eb40a8d2b7b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250286687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1250286687
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.821521339
Short name T266
Test name
Test status
Simulation time 12915194087 ps
CPU time 31.76 seconds
Started Jul 10 05:08:35 PM PDT 24
Finished Jul 10 05:09:08 PM PDT 24
Peak memory 219328 kb
Host smart-bd66fb2f-d3aa-4319-8e98-9c209eb43914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821521339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.821521339
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1849716110
Short name T188
Test name
Test status
Simulation time 1206856632 ps
CPU time 18.08 seconds
Started Jul 10 05:08:32 PM PDT 24
Finished Jul 10 05:08:52 PM PDT 24
Peak memory 211316 kb
Host smart-831ef9ba-0409-4fec-bda1-d04161875b68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1849716110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1849716110
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3950170177
Short name T243
Test name
Test status
Simulation time 2766647973 ps
CPU time 26.8 seconds
Started Jul 10 05:08:33 PM PDT 24
Finished Jul 10 05:09:02 PM PDT 24
Peak memory 218024 kb
Host smart-57bec57b-92a1-4884-a82e-bd2a14f47a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950170177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3950170177
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.797241689
Short name T314
Test name
Test status
Simulation time 3425085496 ps
CPU time 46.72 seconds
Started Jul 10 05:08:31 PM PDT 24
Finished Jul 10 05:09:19 PM PDT 24
Peak memory 217272 kb
Host smart-83aac7ea-f2a8-4494-945b-846209f43321
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797241689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.797241689
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1633508962
Short name T233
Test name
Test status
Simulation time 6633606833 ps
CPU time 28.81 seconds
Started Jul 10 05:08:32 PM PDT 24
Finished Jul 10 05:09:03 PM PDT 24
Peak memory 217520 kb
Host smart-633c3ceb-cf03-481d-9a76-9837bf607aae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633508962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1633508962
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.615927739
Short name T285
Test name
Test status
Simulation time 142329350416 ps
CPU time 441.53 seconds
Started Jul 10 05:08:35 PM PDT 24
Finished Jul 10 05:15:58 PM PDT 24
Peak memory 235872 kb
Host smart-896309c2-4680-4fa2-8a99-71ea3973f23f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615927739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.615927739
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2815528510
Short name T353
Test name
Test status
Simulation time 3422638479 ps
CPU time 26 seconds
Started Jul 10 05:08:32 PM PDT 24
Finished Jul 10 05:08:59 PM PDT 24
Peak memory 219352 kb
Host smart-144c3902-895c-42f9-bd2d-9c6e146df3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815528510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2815528510
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.4106994503
Short name T169
Test name
Test status
Simulation time 12148330260 ps
CPU time 28.46 seconds
Started Jul 10 05:08:33 PM PDT 24
Finished Jul 10 05:09:04 PM PDT 24
Peak memory 217652 kb
Host smart-fd6ac13d-6a9f-4aec-acf4-a355217ba27f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4106994503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.4106994503
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3912493163
Short name T134
Test name
Test status
Simulation time 8237265056 ps
CPU time 74.25 seconds
Started Jul 10 05:08:34 PM PDT 24
Finished Jul 10 05:09:50 PM PDT 24
Peak memory 216564 kb
Host smart-bc7bd65d-341f-4ec0-9e7f-712cb554af63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912493163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3912493163
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.897461775
Short name T153
Test name
Test status
Simulation time 4236091815 ps
CPU time 70.06 seconds
Started Jul 10 05:08:32 PM PDT 24
Finished Jul 10 05:09:44 PM PDT 24
Peak memory 219360 kb
Host smart-42e3100a-8506-4714-88b0-a22b7354a6ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897461775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.897461775
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1375240368
Short name T25
Test name
Test status
Simulation time 4303456059 ps
CPU time 15.32 seconds
Started Jul 10 05:06:51 PM PDT 24
Finished Jul 10 05:07:10 PM PDT 24
Peak memory 217344 kb
Host smart-30c981e9-13bb-4261-9ff4-015d5031c881
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375240368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1375240368
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2761378878
Short name T140
Test name
Test status
Simulation time 63619039188 ps
CPU time 379.78 seconds
Started Jul 10 05:06:51 PM PDT 24
Finished Jul 10 05:13:15 PM PDT 24
Peak memory 229540 kb
Host smart-46acd83a-c2d5-4049-8fb5-9b75bc30ed97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761378878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2761378878
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1837557340
Short name T288
Test name
Test status
Simulation time 2839401431 ps
CPU time 25.33 seconds
Started Jul 10 05:06:54 PM PDT 24
Finished Jul 10 05:07:21 PM PDT 24
Peak memory 219304 kb
Host smart-d6f827bc-8348-4044-ae95-d488a276e9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837557340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1837557340
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2270330057
Short name T118
Test name
Test status
Simulation time 9867190942 ps
CPU time 24.73 seconds
Started Jul 10 05:06:50 PM PDT 24
Finished Jul 10 05:07:18 PM PDT 24
Peak memory 211960 kb
Host smart-1ec52cdc-7d74-4afe-a783-22a20e7b843f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2270330057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2270330057
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2975368591
Short name T72
Test name
Test status
Simulation time 37008469712 ps
CPU time 69.16 seconds
Started Jul 10 05:06:51 PM PDT 24
Finished Jul 10 05:08:03 PM PDT 24
Peak memory 216740 kb
Host smart-60adfed9-4c42-41ec-8cbc-0662867f4d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975368591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2975368591
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2887380719
Short name T326
Test name
Test status
Simulation time 4906885954 ps
CPU time 80.46 seconds
Started Jul 10 05:06:52 PM PDT 24
Finished Jul 10 05:08:15 PM PDT 24
Peak memory 220196 kb
Host smart-54915387-1211-4f06-95eb-b99848ce40eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887380719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2887380719
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1781428729
Short name T152
Test name
Test status
Simulation time 749021154 ps
CPU time 13.74 seconds
Started Jul 10 05:06:59 PM PDT 24
Finished Jul 10 05:07:15 PM PDT 24
Peak memory 217076 kb
Host smart-ab71ca19-4ee7-4b2a-bb7f-46a0a6f0ae3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781428729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1781428729
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3854482051
Short name T325
Test name
Test status
Simulation time 4902976932 ps
CPU time 47.24 seconds
Started Jul 10 05:06:52 PM PDT 24
Finished Jul 10 05:07:42 PM PDT 24
Peak memory 219352 kb
Host smart-b5ac38e6-c6e1-431c-9b6e-02870939eca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854482051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3854482051
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3500720549
Short name T6
Test name
Test status
Simulation time 536111343 ps
CPU time 14.01 seconds
Started Jul 10 05:06:51 PM PDT 24
Finished Jul 10 05:07:08 PM PDT 24
Peak memory 219432 kb
Host smart-9374f852-ee46-4c0c-9714-5fd7bab8da60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3500720549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3500720549
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2719613101
Short name T297
Test name
Test status
Simulation time 2949719376 ps
CPU time 38.06 seconds
Started Jul 10 05:06:50 PM PDT 24
Finished Jul 10 05:07:32 PM PDT 24
Peak memory 217432 kb
Host smart-029406ed-5262-47b5-aacf-466f8318b98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719613101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2719613101
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1090129884
Short name T236
Test name
Test status
Simulation time 11242364970 ps
CPU time 45.34 seconds
Started Jul 10 05:06:50 PM PDT 24
Finished Jul 10 05:07:39 PM PDT 24
Peak memory 219316 kb
Host smart-68d5f84f-edf8-41c4-aebb-c5ba078cf2b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090129884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1090129884
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.57789501
Short name T145
Test name
Test status
Simulation time 7584581460 ps
CPU time 14.55 seconds
Started Jul 10 05:06:57 PM PDT 24
Finished Jul 10 05:07:15 PM PDT 24
Peak memory 217348 kb
Host smart-bf2bbe18-8733-4f70-811b-c295ae330e57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57789501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.57789501
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2034782422
Short name T229
Test name
Test status
Simulation time 33600736953 ps
CPU time 205.84 seconds
Started Jul 10 05:06:57 PM PDT 24
Finished Jul 10 05:10:25 PM PDT 24
Peak memory 218712 kb
Host smart-b0706935-aa6d-4ab4-8169-8471519022bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034782422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2034782422
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1728319219
Short name T277
Test name
Test status
Simulation time 33542580241 ps
CPU time 53.88 seconds
Started Jul 10 05:07:01 PM PDT 24
Finished Jul 10 05:07:56 PM PDT 24
Peak memory 219296 kb
Host smart-8d3db743-38d0-4ff6-b1e2-f7a58bb229e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728319219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1728319219
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2519313372
Short name T97
Test name
Test status
Simulation time 1557832250 ps
CPU time 15.98 seconds
Started Jul 10 05:06:58 PM PDT 24
Finished Jul 10 05:07:17 PM PDT 24
Peak memory 219204 kb
Host smart-dff9b503-23f9-43cf-8b0f-2ff4d4fa85f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2519313372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2519313372
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.397521818
Short name T318
Test name
Test status
Simulation time 13660789268 ps
CPU time 58.67 seconds
Started Jul 10 05:06:57 PM PDT 24
Finished Jul 10 05:07:59 PM PDT 24
Peak memory 217204 kb
Host smart-05ae5bda-dfc8-4cd0-8ed8-71e65199fe79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397521818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.397521818
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3424912137
Short name T276
Test name
Test status
Simulation time 5183615134 ps
CPU time 81.08 seconds
Started Jul 10 05:07:00 PM PDT 24
Finished Jul 10 05:08:23 PM PDT 24
Peak memory 220432 kb
Host smart-dd8d3336-676a-45d0-85db-d26e634cb853
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424912137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3424912137
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2299617059
Short name T53
Test name
Test status
Simulation time 5124985034 ps
CPU time 23.48 seconds
Started Jul 10 05:06:58 PM PDT 24
Finished Jul 10 05:07:24 PM PDT 24
Peak memory 217524 kb
Host smart-895e743c-07f3-4f64-b679-e3b492c067ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299617059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2299617059
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1636098563
Short name T308
Test name
Test status
Simulation time 35878213330 ps
CPU time 309.44 seconds
Started Jul 10 05:06:58 PM PDT 24
Finished Jul 10 05:12:10 PM PDT 24
Peak memory 224680 kb
Host smart-a8e23826-5ccb-400a-ac18-ee3368b0532b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636098563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1636098563
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.258326281
Short name T207
Test name
Test status
Simulation time 27506506302 ps
CPU time 60.31 seconds
Started Jul 10 05:06:57 PM PDT 24
Finished Jul 10 05:08:00 PM PDT 24
Peak memory 219408 kb
Host smart-1299a692-5571-46f8-a604-9bce99776930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258326281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.258326281
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1417827295
Short name T338
Test name
Test status
Simulation time 185688443 ps
CPU time 10.41 seconds
Started Jul 10 05:06:57 PM PDT 24
Finished Jul 10 05:07:10 PM PDT 24
Peak memory 219288 kb
Host smart-564aa3b8-4dd7-433e-a496-5211515f5fd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1417827295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1417827295
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3781216233
Short name T201
Test name
Test status
Simulation time 28691282812 ps
CPU time 59.05 seconds
Started Jul 10 05:06:58 PM PDT 24
Finished Jul 10 05:08:00 PM PDT 24
Peak memory 216364 kb
Host smart-41ee91a8-9bc5-4ee2-a101-366d780857f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781216233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3781216233
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.399066639
Short name T5
Test name
Test status
Simulation time 56238139863 ps
CPU time 119.38 seconds
Started Jul 10 05:06:59 PM PDT 24
Finished Jul 10 05:09:00 PM PDT 24
Peak memory 219408 kb
Host smart-9ace247a-51fe-4727-8d1e-0084bca06909
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399066639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.399066639
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.2495118980
Short name T41
Test name
Test status
Simulation time 161964320623 ps
CPU time 9512.23 seconds
Started Jul 10 05:06:56 PM PDT 24
Finished Jul 10 07:45:32 PM PDT 24
Peak memory 238348 kb
Host smart-593b04f2-5d82-4576-b709-ceac659b050b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495118980 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.2495118980
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.584407010
Short name T55
Test name
Test status
Simulation time 2319514947 ps
CPU time 13.51 seconds
Started Jul 10 05:06:56 PM PDT 24
Finished Jul 10 05:07:12 PM PDT 24
Peak memory 217176 kb
Host smart-78c59182-357c-4f8c-89c4-67beaf94fc2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584407010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.584407010
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2129434942
Short name T241
Test name
Test status
Simulation time 18303804821 ps
CPU time 150.81 seconds
Started Jul 10 05:06:56 PM PDT 24
Finished Jul 10 05:09:30 PM PDT 24
Peak memory 238976 kb
Host smart-48deee94-b63a-4691-b5fc-dcd8f66d570c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129434942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2129434942
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2413376786
Short name T234
Test name
Test status
Simulation time 10446331645 ps
CPU time 61.69 seconds
Started Jul 10 05:06:58 PM PDT 24
Finished Jul 10 05:08:02 PM PDT 24
Peak memory 219216 kb
Host smart-e691f43c-0949-4e9d-8aa3-e8b5e683defa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413376786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2413376786
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2202690351
Short name T154
Test name
Test status
Simulation time 370188290 ps
CPU time 10.94 seconds
Started Jul 10 05:06:57 PM PDT 24
Finished Jul 10 05:07:10 PM PDT 24
Peak memory 219228 kb
Host smart-63871bc3-6151-4184-9b49-620ffe445211
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2202690351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2202690351
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1995901979
Short name T300
Test name
Test status
Simulation time 677759403 ps
CPU time 20.42 seconds
Started Jul 10 05:06:57 PM PDT 24
Finished Jul 10 05:07:20 PM PDT 24
Peak memory 216260 kb
Host smart-3b03e85e-9175-4a6a-918a-17847c632bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995901979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1995901979
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1045444360
Short name T348
Test name
Test status
Simulation time 16038805260 ps
CPU time 98.2 seconds
Started Jul 10 05:06:57 PM PDT 24
Finished Jul 10 05:08:38 PM PDT 24
Peak memory 221144 kb
Host smart-8b9b135b-dc63-40d1-a0d2-d00f9c956922
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045444360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1045444360
Directory /workspace/9.rom_ctrl_stress_all/latest
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