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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.21 96.89 91.99 97.68 100.00 98.28 97.30 98.37


Total test records in report: 455
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T305 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3900348386 Jul 11 04:29:21 PM PDT 24 Jul 11 04:30:33 PM PDT 24 35063307668 ps
T306 /workspace/coverage/default/32.rom_ctrl_smoke.2483263628 Jul 11 04:30:14 PM PDT 24 Jul 11 04:31:45 PM PDT 24 8838125323 ps
T307 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3765947476 Jul 11 04:28:29 PM PDT 24 Jul 11 04:33:51 PM PDT 24 80767618678 ps
T308 /workspace/coverage/default/27.rom_ctrl_alert_test.582358995 Jul 11 04:29:18 PM PDT 24 Jul 11 04:29:29 PM PDT 24 167569624 ps
T309 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1811444251 Jul 11 04:29:37 PM PDT 24 Jul 11 04:30:40 PM PDT 24 111346518087 ps
T310 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1577915609 Jul 11 04:28:25 PM PDT 24 Jul 11 04:31:10 PM PDT 24 2316963141 ps
T311 /workspace/coverage/default/41.rom_ctrl_stress_all.2103183279 Jul 11 04:29:13 PM PDT 24 Jul 11 04:29:41 PM PDT 24 4713660972 ps
T312 /workspace/coverage/default/7.rom_ctrl_alert_test.3797273632 Jul 11 04:28:36 PM PDT 24 Jul 11 04:28:58 PM PDT 24 2062717290 ps
T313 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1705975315 Jul 11 04:28:53 PM PDT 24 Jul 11 04:35:51 PM PDT 24 498809016685 ps
T314 /workspace/coverage/default/10.rom_ctrl_smoke.1881105617 Jul 11 04:28:55 PM PDT 24 Jul 11 04:29:17 PM PDT 24 354062551 ps
T315 /workspace/coverage/default/13.rom_ctrl_alert_test.689458383 Jul 11 04:28:55 PM PDT 24 Jul 11 04:29:23 PM PDT 24 12227203277 ps
T316 /workspace/coverage/default/17.rom_ctrl_alert_test.3111916486 Jul 11 04:29:17 PM PDT 24 Jul 11 04:29:53 PM PDT 24 4269584564 ps
T317 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3094615320 Jul 11 04:29:13 PM PDT 24 Jul 11 04:36:24 PM PDT 24 40760899589 ps
T15 /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.3651373532 Jul 11 04:28:45 PM PDT 24 Jul 11 04:39:05 PM PDT 24 67992043400 ps
T318 /workspace/coverage/default/28.rom_ctrl_smoke.3051917031 Jul 11 04:29:01 PM PDT 24 Jul 11 04:29:35 PM PDT 24 1750207485 ps
T319 /workspace/coverage/default/45.rom_ctrl_smoke.4026552170 Jul 11 04:29:26 PM PDT 24 Jul 11 04:30:21 PM PDT 24 75363078535 ps
T56 /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1469705155 Jul 11 04:29:25 PM PDT 24 Jul 11 04:46:46 PM PDT 24 8794443120 ps
T320 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1598911955 Jul 11 04:28:54 PM PDT 24 Jul 11 04:33:26 PM PDT 24 14155362992 ps
T321 /workspace/coverage/default/23.rom_ctrl_smoke.1045884012 Jul 11 04:28:49 PM PDT 24 Jul 11 04:29:10 PM PDT 24 2437461481 ps
T16 /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3284432247 Jul 11 04:28:59 PM PDT 24 Jul 11 06:46:28 PM PDT 24 62559668011 ps
T322 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3442887567 Jul 11 04:29:19 PM PDT 24 Jul 11 04:29:56 PM PDT 24 53639158775 ps
T323 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1401595355 Jul 11 04:28:50 PM PDT 24 Jul 11 04:29:02 PM PDT 24 700725628 ps
T324 /workspace/coverage/default/18.rom_ctrl_stress_all.2228452564 Jul 11 04:29:08 PM PDT 24 Jul 11 04:30:37 PM PDT 24 12592689134 ps
T325 /workspace/coverage/default/16.rom_ctrl_alert_test.4015469176 Jul 11 04:28:51 PM PDT 24 Jul 11 04:29:04 PM PDT 24 2495076058 ps
T326 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3282907475 Jul 11 04:28:45 PM PDT 24 Jul 11 04:29:11 PM PDT 24 24640937470 ps
T327 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.981587230 Jul 11 04:29:24 PM PDT 24 Jul 11 04:45:18 PM PDT 24 387072662855 ps
T328 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.759461648 Jul 11 04:29:24 PM PDT 24 Jul 11 04:30:26 PM PDT 24 7039261718 ps
T329 /workspace/coverage/default/2.rom_ctrl_stress_all.1650664146 Jul 11 04:29:10 PM PDT 24 Jul 11 04:29:39 PM PDT 24 396032105 ps
T330 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1373912764 Jul 11 04:29:20 PM PDT 24 Jul 11 04:29:43 PM PDT 24 7562301970 ps
T331 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2590572123 Jul 11 04:30:03 PM PDT 24 Jul 11 04:40:58 PM PDT 24 256960397412 ps
T332 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.4088474434 Jul 11 04:29:25 PM PDT 24 Jul 11 04:33:54 PM PDT 24 22974439865 ps
T333 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.684234280 Jul 11 04:29:15 PM PDT 24 Jul 11 04:35:14 PM PDT 24 34235860806 ps
T334 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3510908135 Jul 11 04:29:06 PM PDT 24 Jul 11 04:33:53 PM PDT 24 30618958937 ps
T335 /workspace/coverage/default/35.rom_ctrl_smoke.3679993125 Jul 11 04:29:18 PM PDT 24 Jul 11 04:30:11 PM PDT 24 5631779268 ps
T336 /workspace/coverage/default/26.rom_ctrl_alert_test.2536732255 Jul 11 04:29:06 PM PDT 24 Jul 11 04:29:17 PM PDT 24 167673581 ps
T337 /workspace/coverage/default/33.rom_ctrl_smoke.3820975910 Jul 11 04:29:15 PM PDT 24 Jul 11 04:30:27 PM PDT 24 6462367835 ps
T338 /workspace/coverage/default/25.rom_ctrl_stress_all.972942530 Jul 11 04:29:15 PM PDT 24 Jul 11 04:31:41 PM PDT 24 69573006048 ps
T339 /workspace/coverage/default/24.rom_ctrl_stress_all.3905062675 Jul 11 04:29:05 PM PDT 24 Jul 11 04:30:53 PM PDT 24 21310256247 ps
T340 /workspace/coverage/default/35.rom_ctrl_stress_all.1687838256 Jul 11 04:29:09 PM PDT 24 Jul 11 04:29:37 PM PDT 24 1617069717 ps
T341 /workspace/coverage/default/31.rom_ctrl_stress_all.3508432091 Jul 11 04:30:46 PM PDT 24 Jul 11 04:31:57 PM PDT 24 40123262272 ps
T342 /workspace/coverage/default/18.rom_ctrl_alert_test.1568398541 Jul 11 04:28:52 PM PDT 24 Jul 11 04:29:15 PM PDT 24 2505441486 ps
T343 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1642444229 Jul 11 04:28:18 PM PDT 24 Jul 11 04:28:46 PM PDT 24 10825525428 ps
T344 /workspace/coverage/default/29.rom_ctrl_smoke.2571205213 Jul 11 04:29:09 PM PDT 24 Jul 11 04:29:46 PM PDT 24 14186726300 ps
T345 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3476674631 Jul 11 04:28:51 PM PDT 24 Jul 11 04:45:25 PM PDT 24 377252159340 ps
T346 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2823780499 Jul 11 04:28:54 PM PDT 24 Jul 11 04:29:48 PM PDT 24 10865570070 ps
T347 /workspace/coverage/default/15.rom_ctrl_stress_all.3255045176 Jul 11 04:28:36 PM PDT 24 Jul 11 04:29:58 PM PDT 24 26233671940 ps
T348 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3046380451 Jul 11 04:29:22 PM PDT 24 Jul 11 04:29:44 PM PDT 24 689325746 ps
T349 /workspace/coverage/default/43.rom_ctrl_stress_all.1179486166 Jul 11 04:29:38 PM PDT 24 Jul 11 04:32:21 PM PDT 24 67749107944 ps
T350 /workspace/coverage/default/0.rom_ctrl_stress_all.3590376594 Jul 11 04:28:12 PM PDT 24 Jul 11 04:30:17 PM PDT 24 52663484596 ps
T351 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3659935530 Jul 11 04:29:21 PM PDT 24 Jul 11 04:41:08 PM PDT 24 134054755710 ps
T352 /workspace/coverage/default/28.rom_ctrl_alert_test.4121890036 Jul 11 04:29:17 PM PDT 24 Jul 11 04:29:39 PM PDT 24 1808382458 ps
T353 /workspace/coverage/default/40.rom_ctrl_alert_test.2706703678 Jul 11 04:29:39 PM PDT 24 Jul 11 04:29:57 PM PDT 24 3956880184 ps
T354 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3401689345 Jul 11 04:29:11 PM PDT 24 Jul 11 04:29:32 PM PDT 24 21417402159 ps
T355 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.4137822306 Jul 11 04:28:59 PM PDT 24 Jul 11 04:29:46 PM PDT 24 17065848189 ps
T356 /workspace/coverage/default/12.rom_ctrl_stress_all.3230239901 Jul 11 04:28:53 PM PDT 24 Jul 11 04:31:02 PM PDT 24 62920003924 ps
T357 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2861656887 Jul 11 04:29:09 PM PDT 24 Jul 11 04:29:31 PM PDT 24 1532227444 ps
T358 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.790014354 Jul 11 04:28:58 PM PDT 24 Jul 11 04:29:37 PM PDT 24 7546028590 ps
T359 /workspace/coverage/default/3.rom_ctrl_alert_test.578138007 Jul 11 04:28:29 PM PDT 24 Jul 11 04:28:39 PM PDT 24 176223649 ps
T360 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2791775811 Jul 11 04:29:11 PM PDT 24 Jul 11 04:29:49 PM PDT 24 10235938000 ps
T361 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.4237588042 Jul 11 04:28:23 PM PDT 24 Jul 11 04:28:47 PM PDT 24 6883068479 ps
T60 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1646700460 Jul 11 06:19:23 PM PDT 24 Jul 11 06:19:34 PM PDT 24 214245648 ps
T57 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2134188407 Jul 11 06:19:23 PM PDT 24 Jul 11 06:21:03 PM PDT 24 3095565375 ps
T61 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2102168853 Jul 11 06:19:43 PM PDT 24 Jul 11 06:20:12 PM PDT 24 2472429838 ps
T65 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.719343836 Jul 11 06:19:53 PM PDT 24 Jul 11 06:20:17 PM PDT 24 1822624967 ps
T68 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.4019608492 Jul 11 06:19:57 PM PDT 24 Jul 11 06:20:33 PM PDT 24 16589773034 ps
T69 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1397309115 Jul 11 06:19:45 PM PDT 24 Jul 11 06:20:59 PM PDT 24 12011473205 ps
T101 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1046704122 Jul 11 06:19:48 PM PDT 24 Jul 11 06:20:03 PM PDT 24 674714525 ps
T102 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3388538188 Jul 11 06:19:55 PM PDT 24 Jul 11 06:20:22 PM PDT 24 21034661888 ps
T362 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3330863190 Jul 11 06:19:42 PM PDT 24 Jul 11 06:20:10 PM PDT 24 11696040790 ps
T70 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1668868716 Jul 11 06:19:51 PM PDT 24 Jul 11 06:20:29 PM PDT 24 720214190 ps
T363 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2850575496 Jul 11 06:19:51 PM PDT 24 Jul 11 06:20:01 PM PDT 24 794951395 ps
T58 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4247155393 Jul 11 06:19:42 PM PDT 24 Jul 11 06:21:27 PM PDT 24 4118854310 ps
T71 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2612509569 Jul 11 06:19:49 PM PDT 24 Jul 11 06:19:59 PM PDT 24 170969729 ps
T364 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2279689652 Jul 11 06:19:38 PM PDT 24 Jul 11 06:19:48 PM PDT 24 177232154 ps
T365 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1940791959 Jul 11 06:19:40 PM PDT 24 Jul 11 06:20:06 PM PDT 24 27326915625 ps
T72 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.130726777 Jul 11 06:19:51 PM PDT 24 Jul 11 06:20:00 PM PDT 24 174429483 ps
T73 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1259446301 Jul 11 06:19:39 PM PDT 24 Jul 11 06:20:19 PM PDT 24 706961756 ps
T103 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.114951324 Jul 11 06:19:34 PM PDT 24 Jul 11 06:19:56 PM PDT 24 2172766764 ps
T98 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.975337342 Jul 11 06:19:43 PM PDT 24 Jul 11 06:21:24 PM PDT 24 6698711164 ps
T59 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1276392225 Jul 11 06:19:56 PM PDT 24 Jul 11 06:22:33 PM PDT 24 342270463 ps
T366 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3526533262 Jul 11 06:19:32 PM PDT 24 Jul 11 06:20:08 PM PDT 24 4383034711 ps
T74 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1786561217 Jul 11 06:19:39 PM PDT 24 Jul 11 06:19:59 PM PDT 24 1503799941 ps
T75 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1091469399 Jul 11 06:19:33 PM PDT 24 Jul 11 06:19:45 PM PDT 24 787316937 ps
T367 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.4086161840 Jul 11 06:19:41 PM PDT 24 Jul 11 06:19:55 PM PDT 24 3072419631 ps
T117 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1247733852 Jul 11 06:19:50 PM PDT 24 Jul 11 06:21:25 PM PDT 24 5390652012 ps
T368 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4029334590 Jul 11 06:19:30 PM PDT 24 Jul 11 06:19:55 PM PDT 24 4420124315 ps
T108 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2363010402 Jul 11 06:19:48 PM PDT 24 Jul 11 06:21:12 PM PDT 24 309504124 ps
T369 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1223839203 Jul 11 06:19:56 PM PDT 24 Jul 11 06:20:17 PM PDT 24 2192641705 ps
T107 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1397377056 Jul 11 06:19:52 PM PDT 24 Jul 11 06:21:16 PM PDT 24 1943889688 ps
T76 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3158708749 Jul 11 06:19:55 PM PDT 24 Jul 11 06:21:29 PM PDT 24 32796339050 ps
T83 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1019631152 Jul 11 06:19:44 PM PDT 24 Jul 11 06:21:46 PM PDT 24 14438784226 ps
T370 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3965523567 Jul 11 06:19:58 PM PDT 24 Jul 11 06:20:09 PM PDT 24 746256805 ps
T371 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.130507578 Jul 11 06:19:32 PM PDT 24 Jul 11 06:19:56 PM PDT 24 5895378764 ps
T99 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1305328890 Jul 11 06:19:47 PM PDT 24 Jul 11 06:19:57 PM PDT 24 870205181 ps
T100 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2373000200 Jul 11 06:19:42 PM PDT 24 Jul 11 06:20:21 PM PDT 24 29623719240 ps
T84 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3523195635 Jul 11 06:19:33 PM PDT 24 Jul 11 06:20:06 PM PDT 24 41167095143 ps
T111 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.298144020 Jul 11 06:19:34 PM PDT 24 Jul 11 06:22:14 PM PDT 24 2250961023 ps
T85 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1600858593 Jul 11 06:19:23 PM PDT 24 Jul 11 06:19:48 PM PDT 24 9243661828 ps
T112 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1344422185 Jul 11 06:19:43 PM PDT 24 Jul 11 06:21:26 PM PDT 24 25652265161 ps
T372 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2554229522 Jul 11 06:19:35 PM PDT 24 Jul 11 06:20:02 PM PDT 24 2606367376 ps
T373 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.325831716 Jul 11 06:19:43 PM PDT 24 Jul 11 06:20:08 PM PDT 24 4731202288 ps
T109 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1875865035 Jul 11 06:19:47 PM PDT 24 Jul 11 06:22:32 PM PDT 24 2771563810 ps
T374 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3365980773 Jul 11 06:19:33 PM PDT 24 Jul 11 06:19:44 PM PDT 24 174437262 ps
T375 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2003824828 Jul 11 06:19:43 PM PDT 24 Jul 11 06:20:05 PM PDT 24 1883630945 ps
T376 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2012297243 Jul 11 06:19:33 PM PDT 24 Jul 11 06:19:45 PM PDT 24 176185288 ps
T377 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1042365781 Jul 11 06:19:52 PM PDT 24 Jul 11 06:20:05 PM PDT 24 424362808 ps
T378 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3073419330 Jul 11 06:19:52 PM PDT 24 Jul 11 06:23:03 PM PDT 24 98499889180 ps
T379 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1462659902 Jul 11 06:19:56 PM PDT 24 Jul 11 06:20:30 PM PDT 24 8532974918 ps
T118 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.4250018944 Jul 11 06:19:43 PM PDT 24 Jul 11 06:22:25 PM PDT 24 6472726621 ps
T380 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.664252460 Jul 11 06:19:38 PM PDT 24 Jul 11 06:19:48 PM PDT 24 170803362 ps
T381 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1831942405 Jul 11 06:19:46 PM PDT 24 Jul 11 06:20:12 PM PDT 24 5011241521 ps
T382 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2059032996 Jul 11 06:19:38 PM PDT 24 Jul 11 06:19:58 PM PDT 24 1472897512 ps
T383 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1482913954 Jul 11 06:19:42 PM PDT 24 Jul 11 06:19:53 PM PDT 24 636779807 ps
T86 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.680296101 Jul 11 06:19:53 PM PDT 24 Jul 11 06:22:11 PM PDT 24 17742767181 ps
T87 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.484127847 Jul 11 06:19:45 PM PDT 24 Jul 11 06:19:55 PM PDT 24 534386150 ps
T105 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2085841432 Jul 11 06:19:45 PM PDT 24 Jul 11 06:22:00 PM PDT 24 16128257772 ps
T384 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3072151644 Jul 11 06:19:43 PM PDT 24 Jul 11 06:20:16 PM PDT 24 26054371665 ps
T385 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3200304990 Jul 11 06:19:45 PM PDT 24 Jul 11 06:20:10 PM PDT 24 5900203976 ps
T88 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2423809912 Jul 11 06:19:52 PM PDT 24 Jul 11 06:20:01 PM PDT 24 787644949 ps
T386 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1084497636 Jul 11 06:19:40 PM PDT 24 Jul 11 06:20:10 PM PDT 24 13068024395 ps
T387 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2834394494 Jul 11 06:19:31 PM PDT 24 Jul 11 06:19:55 PM PDT 24 4335452100 ps
T89 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3519388600 Jul 11 06:19:37 PM PDT 24 Jul 11 06:22:51 PM PDT 24 130322012153 ps
T119 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.893323743 Jul 11 06:19:43 PM PDT 24 Jul 11 06:21:13 PM PDT 24 5197665908 ps
T388 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1339783922 Jul 11 06:19:30 PM PDT 24 Jul 11 06:19:41 PM PDT 24 179823455 ps
T389 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2178072330 Jul 11 06:19:44 PM PDT 24 Jul 11 06:19:55 PM PDT 24 356501569 ps
T390 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.940572812 Jul 11 06:19:45 PM PDT 24 Jul 11 06:20:01 PM PDT 24 636090889 ps
T391 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.815083675 Jul 11 06:19:31 PM PDT 24 Jul 11 06:19:43 PM PDT 24 762075635 ps
T392 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1496571540 Jul 11 06:19:35 PM PDT 24 Jul 11 06:20:00 PM PDT 24 10985793187 ps
T393 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1998753739 Jul 11 06:19:56 PM PDT 24 Jul 11 06:20:11 PM PDT 24 338122149 ps
T394 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1213636946 Jul 11 06:19:32 PM PDT 24 Jul 11 06:19:48 PM PDT 24 2565852965 ps
T96 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3135355632 Jul 11 06:19:57 PM PDT 24 Jul 11 06:20:17 PM PDT 24 5319612386 ps
T90 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2126452862 Jul 11 06:19:48 PM PDT 24 Jul 11 06:20:23 PM PDT 24 24992365475 ps
T395 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2640314005 Jul 11 06:19:36 PM PDT 24 Jul 11 06:20:05 PM PDT 24 6975283908 ps
T114 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1844432969 Jul 11 06:19:59 PM PDT 24 Jul 11 06:21:43 PM PDT 24 3489291475 ps
T396 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2816754255 Jul 11 06:19:36 PM PDT 24 Jul 11 06:20:11 PM PDT 24 25123468081 ps
T397 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3585729211 Jul 11 06:19:41 PM PDT 24 Jul 11 06:19:51 PM PDT 24 339105222 ps
T398 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1668228604 Jul 11 06:19:38 PM PDT 24 Jul 11 06:19:58 PM PDT 24 1671999709 ps
T91 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2139838464 Jul 11 06:19:31 PM PDT 24 Jul 11 06:21:21 PM PDT 24 16768837725 ps
T399 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.20364390 Jul 11 06:19:47 PM PDT 24 Jul 11 06:20:19 PM PDT 24 6226221234 ps
T115 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2325350488 Jul 11 06:19:46 PM PDT 24 Jul 11 06:22:24 PM PDT 24 405095512 ps
T400 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2158027001 Jul 11 06:19:44 PM PDT 24 Jul 11 06:20:14 PM PDT 24 8864947812 ps
T401 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1372646332 Jul 11 06:19:52 PM PDT 24 Jul 11 06:20:18 PM PDT 24 11133511192 ps
T113 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1845447744 Jul 11 06:19:54 PM PDT 24 Jul 11 06:22:39 PM PDT 24 7452009886 ps
T402 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3500104331 Jul 11 06:19:41 PM PDT 24 Jul 11 06:19:53 PM PDT 24 338036987 ps
T92 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3364733588 Jul 11 06:19:42 PM PDT 24 Jul 11 06:21:59 PM PDT 24 12341439401 ps
T403 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2957048943 Jul 11 06:19:39 PM PDT 24 Jul 11 06:20:14 PM PDT 24 8568112196 ps
T404 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2111055538 Jul 11 06:19:40 PM PDT 24 Jul 11 06:20:14 PM PDT 24 15880881770 ps
T405 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2134989717 Jul 11 06:19:44 PM PDT 24 Jul 11 06:19:55 PM PDT 24 751543087 ps
T406 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3333377566 Jul 11 06:19:47 PM PDT 24 Jul 11 06:19:57 PM PDT 24 167363278 ps
T93 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3962690278 Jul 11 06:19:48 PM PDT 24 Jul 11 06:20:16 PM PDT 24 2699148760 ps
T407 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1072365055 Jul 11 06:19:45 PM PDT 24 Jul 11 06:20:16 PM PDT 24 3592406307 ps
T408 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.508103747 Jul 11 06:19:21 PM PDT 24 Jul 11 06:20:37 PM PDT 24 6374877978 ps
T409 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3584549276 Jul 11 06:19:30 PM PDT 24 Jul 11 06:19:41 PM PDT 24 1101036715 ps
T116 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2352399968 Jul 11 06:19:39 PM PDT 24 Jul 11 06:21:24 PM PDT 24 5553678665 ps
T410 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1209616246 Jul 11 06:19:43 PM PDT 24 Jul 11 06:20:07 PM PDT 24 4582240685 ps
T411 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1297983713 Jul 11 06:19:41 PM PDT 24 Jul 11 06:19:59 PM PDT 24 2493999451 ps
T412 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2533117479 Jul 11 06:19:51 PM PDT 24 Jul 11 06:20:14 PM PDT 24 19340750684 ps
T110 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1562192114 Jul 11 06:19:45 PM PDT 24 Jul 11 06:22:26 PM PDT 24 4228584236 ps
T413 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.731350793 Jul 11 06:19:33 PM PDT 24 Jul 11 06:19:49 PM PDT 24 172853778 ps
T97 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.607821337 Jul 11 06:19:33 PM PDT 24 Jul 11 06:19:54 PM PDT 24 1564166952 ps
T414 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4033365071 Jul 11 06:19:50 PM PDT 24 Jul 11 06:22:31 PM PDT 24 5855877574 ps
T415 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1043719670 Jul 11 06:19:56 PM PDT 24 Jul 11 06:20:16 PM PDT 24 1977137009 ps
T416 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.567179126 Jul 11 06:19:31 PM PDT 24 Jul 11 06:19:57 PM PDT 24 7703180155 ps
T417 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2523987771 Jul 11 06:19:43 PM PDT 24 Jul 11 06:19:54 PM PDT 24 660861783 ps
T418 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3568753443 Jul 11 06:19:43 PM PDT 24 Jul 11 06:20:16 PM PDT 24 3902869510 ps
T419 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2317968778 Jul 11 06:19:43 PM PDT 24 Jul 11 06:21:06 PM PDT 24 13937773941 ps
T420 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.797269821 Jul 11 06:19:50 PM PDT 24 Jul 11 06:19:59 PM PDT 24 175161876 ps
T421 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1580918318 Jul 11 06:19:30 PM PDT 24 Jul 11 06:20:54 PM PDT 24 283125859 ps
T422 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1277167314 Jul 11 06:19:52 PM PDT 24 Jul 11 06:20:26 PM PDT 24 4169032619 ps
T423 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3743702186 Jul 11 06:19:32 PM PDT 24 Jul 11 06:19:59 PM PDT 24 2689649864 ps
T424 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.224794956 Jul 11 06:19:52 PM PDT 24 Jul 11 06:20:18 PM PDT 24 11963220712 ps
T106 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.593018150 Jul 11 06:19:45 PM PDT 24 Jul 11 06:20:26 PM PDT 24 1438383345 ps
T425 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3881150335 Jul 11 06:19:39 PM PDT 24 Jul 11 06:20:09 PM PDT 24 5184287065 ps
T426 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2980362270 Jul 11 06:19:51 PM PDT 24 Jul 11 06:21:43 PM PDT 24 12672877834 ps
T427 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2252607064 Jul 11 06:19:58 PM PDT 24 Jul 11 06:20:38 PM PDT 24 19965039902 ps
T94 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2134715233 Jul 11 06:19:34 PM PDT 24 Jul 11 06:21:52 PM PDT 24 68077713052 ps
T428 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2647713091 Jul 11 06:19:50 PM PDT 24 Jul 11 06:20:16 PM PDT 24 8527785562 ps
T429 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3426365291 Jul 11 06:19:47 PM PDT 24 Jul 11 06:20:11 PM PDT 24 6204031844 ps
T430 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1154756142 Jul 11 06:19:33 PM PDT 24 Jul 11 06:19:45 PM PDT 24 2748394991 ps
T431 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2702360993 Jul 11 06:19:41 PM PDT 24 Jul 11 06:20:04 PM PDT 24 36737127216 ps
T432 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3075428248 Jul 11 06:20:00 PM PDT 24 Jul 11 06:20:11 PM PDT 24 679022356 ps
T433 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3807540967 Jul 11 06:19:31 PM PDT 24 Jul 11 06:19:42 PM PDT 24 687759573 ps
T434 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2501432545 Jul 11 06:19:58 PM PDT 24 Jul 11 06:20:14 PM PDT 24 869544970 ps
T435 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.356805587 Jul 11 06:19:46 PM PDT 24 Jul 11 06:21:32 PM PDT 24 11084528696 ps
T436 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2960196104 Jul 11 06:19:50 PM PDT 24 Jul 11 06:19:59 PM PDT 24 167594035 ps
T437 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3372996283 Jul 11 06:19:40 PM PDT 24 Jul 11 06:20:06 PM PDT 24 2953162504 ps
T438 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.895119353 Jul 11 06:19:47 PM PDT 24 Jul 11 06:20:15 PM PDT 24 3023209522 ps
T439 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2963859687 Jul 11 06:19:32 PM PDT 24 Jul 11 06:19:56 PM PDT 24 2216983316 ps
T440 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.583048016 Jul 11 06:19:44 PM PDT 24 Jul 11 06:20:20 PM PDT 24 16021923443 ps
T441 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1984820503 Jul 11 06:19:31 PM PDT 24 Jul 11 06:19:43 PM PDT 24 1375066374 ps
T95 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3122171396 Jul 11 06:19:37 PM PDT 24 Jul 11 06:21:33 PM PDT 24 51269960239 ps
T442 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1789511134 Jul 11 06:19:36 PM PDT 24 Jul 11 06:20:10 PM PDT 24 4203309154 ps
T443 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3349467951 Jul 11 06:19:51 PM PDT 24 Jul 11 06:20:27 PM PDT 24 16735678617 ps
T444 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4232453426 Jul 11 06:19:30 PM PDT 24 Jul 11 06:19:44 PM PDT 24 2144066229 ps
T445 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3786141696 Jul 11 06:19:57 PM PDT 24 Jul 11 06:20:24 PM PDT 24 11754961815 ps
T446 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3555920230 Jul 11 06:19:45 PM PDT 24 Jul 11 06:20:06 PM PDT 24 6365326947 ps
T447 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2914638954 Jul 11 06:19:43 PM PDT 24 Jul 11 06:20:16 PM PDT 24 3211877358 ps
T448 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.654116078 Jul 11 06:19:32 PM PDT 24 Jul 11 06:20:06 PM PDT 24 24014641633 ps
T449 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.536391710 Jul 11 06:19:57 PM PDT 24 Jul 11 06:21:16 PM PDT 24 6186395474 ps
T450 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2565196835 Jul 11 06:19:52 PM PDT 24 Jul 11 06:20:22 PM PDT 24 3679871006 ps
T451 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1215585401 Jul 11 06:19:39 PM PDT 24 Jul 11 06:19:49 PM PDT 24 174493009 ps
T452 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2796282856 Jul 11 06:19:33 PM PDT 24 Jul 11 06:22:27 PM PDT 24 11575961773 ps
T453 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3229666713 Jul 11 06:19:48 PM PDT 24 Jul 11 06:20:13 PM PDT 24 4644037131 ps
T454 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.603713394 Jul 11 06:19:26 PM PDT 24 Jul 11 06:19:43 PM PDT 24 698619841 ps
T455 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3562437902 Jul 11 06:19:42 PM PDT 24 Jul 11 06:21:12 PM PDT 24 1714511889 ps

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.782232684
Short name T5
Test name
Test status
Simulation time 134348104464 ps
CPU time 5184.59 seconds
Started Jul 11 04:29:10 PM PDT 24
Finished Jul 11 05:55:39 PM PDT 24
Peak memory 260276 kb
Host smart-80862414-ae76-45f6-bef3-550e1c8d0e9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782232684 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.782232684
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3713187147
Short name T20
Test name
Test status
Simulation time 758020331128 ps
CPU time 630.65 seconds
Started Jul 11 04:28:17 PM PDT 24
Finished Jul 11 04:38:50 PM PDT 24
Peak memory 216716 kb
Host smart-5e5fa54d-6071-4ec3-83b9-4a3b1ef514d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713187147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3713187147
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1050163275
Short name T9
Test name
Test status
Simulation time 20935288142 ps
CPU time 34.59 seconds
Started Jul 11 04:28:45 PM PDT 24
Finished Jul 11 04:29:21 PM PDT 24
Peak memory 217492 kb
Host smart-5627a5b5-63be-406c-91c0-bee828eb5d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050163275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1050163275
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.680440748
Short name T50
Test name
Test status
Simulation time 69562424130 ps
CPU time 578.29 seconds
Started Jul 11 04:29:22 PM PDT 24
Finished Jul 11 04:39:04 PM PDT 24
Peak memory 216848 kb
Host smart-2af8c9c7-2292-4e14-bbd5-40e4fb830d07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680440748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.680440748
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1276392225
Short name T59
Test name
Test status
Simulation time 342270463 ps
CPU time 154.28 seconds
Started Jul 11 06:19:56 PM PDT 24
Finished Jul 11 06:22:33 PM PDT 24
Peak memory 214040 kb
Host smart-b60de400-1cea-4800-af05-819888483e2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276392225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1276392225
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.4211231114
Short name T63
Test name
Test status
Simulation time 6838037469 ps
CPU time 28.11 seconds
Started Jul 11 04:29:06 PM PDT 24
Finished Jul 11 04:29:37 PM PDT 24
Peak memory 217492 kb
Host smart-4d062453-e1a9-438d-8b6b-d753cf7f44b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211231114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.4211231114
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3463559370
Short name T25
Test name
Test status
Simulation time 3866140725 ps
CPU time 231.91 seconds
Started Jul 11 04:29:10 PM PDT 24
Finished Jul 11 04:33:05 PM PDT 24
Peak memory 237612 kb
Host smart-6c1e113b-871d-46d8-abb8-91e4a72a3461
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463559370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3463559370
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2851491118
Short name T17
Test name
Test status
Simulation time 523589305 ps
CPU time 34.37 seconds
Started Jul 11 04:29:15 PM PDT 24
Finished Jul 11 04:30:02 PM PDT 24
Peak memory 219220 kb
Host smart-0d94bee9-1996-4baa-9529-ec25108c6588
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851491118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2851491118
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3158708749
Short name T76
Test name
Test status
Simulation time 32796339050 ps
CPU time 92.09 seconds
Started Jul 11 06:19:55 PM PDT 24
Finished Jul 11 06:21:29 PM PDT 24
Peak memory 213916 kb
Host smart-1ab0c662-2ec7-47ee-8b96-e16f71551b6a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158708749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3158708749
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.298144020
Short name T111
Test name
Test status
Simulation time 2250961023 ps
CPU time 157.49 seconds
Started Jul 11 06:19:34 PM PDT 24
Finished Jul 11 06:22:14 PM PDT 24
Peak memory 214052 kb
Host smart-e7ddfba7-3d09-4388-a9ce-e2beef01561f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298144020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.298144020
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.4179367964
Short name T22
Test name
Test status
Simulation time 77022318863 ps
CPU time 585.98 seconds
Started Jul 11 04:29:21 PM PDT 24
Finished Jul 11 04:39:10 PM PDT 24
Peak memory 226512 kb
Host smart-55752481-1471-4af7-bf54-5f30fa328cf7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179367964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.4179367964
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2139838464
Short name T91
Test name
Test status
Simulation time 16768837725 ps
CPU time 106.62 seconds
Started Jul 11 06:19:31 PM PDT 24
Finished Jul 11 06:21:21 PM PDT 24
Peak memory 210864 kb
Host smart-b6a75618-3ae8-4cb2-89f8-35a5ebfb5b04
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139838464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2139838464
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3342580972
Short name T2
Test name
Test status
Simulation time 52243935431 ps
CPU time 68.42 seconds
Started Jul 11 04:29:13 PM PDT 24
Finished Jul 11 04:30:24 PM PDT 24
Peak memory 219232 kb
Host smart-1d21aed6-b7a7-4af8-b921-314aebb13c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342580972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3342580972
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.4112567572
Short name T252
Test name
Test status
Simulation time 353800092 ps
CPU time 19.07 seconds
Started Jul 11 04:28:38 PM PDT 24
Finished Jul 11 04:28:58 PM PDT 24
Peak memory 219160 kb
Host smart-5f64ba19-e3ef-41d8-ae49-76a5623d3c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112567572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.4112567572
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1397377056
Short name T107
Test name
Test status
Simulation time 1943889688 ps
CPU time 83.17 seconds
Started Jul 11 06:19:52 PM PDT 24
Finished Jul 11 06:21:16 PM PDT 24
Peak memory 213384 kb
Host smart-327c0733-b965-409f-99ef-031fb12be462
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397377056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1397377056
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1397309115
Short name T69
Test name
Test status
Simulation time 12011473205 ps
CPU time 71.78 seconds
Started Jul 11 06:19:45 PM PDT 24
Finished Jul 11 06:20:59 PM PDT 24
Peak memory 214388 kb
Host smart-c31f90f9-a3b0-403e-875e-84acad18460c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397309115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1397309115
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2771318292
Short name T49
Test name
Test status
Simulation time 88260985024 ps
CPU time 137.06 seconds
Started Jul 11 04:29:14 PM PDT 24
Finished Jul 11 04:31:35 PM PDT 24
Peak memory 220128 kb
Host smart-1fbbe7be-0878-4ad1-abbc-15015d39a199
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771318292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2771318292
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.4250018944
Short name T118
Test name
Test status
Simulation time 6472726621 ps
CPU time 159.26 seconds
Started Jul 11 06:19:43 PM PDT 24
Finished Jul 11 06:22:25 PM PDT 24
Peak memory 214360 kb
Host smart-ad9df8be-f7ee-4673-8040-df83d80fe9de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250018944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.4250018944
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1875865035
Short name T109
Test name
Test status
Simulation time 2771563810 ps
CPU time 162.68 seconds
Started Jul 11 06:19:47 PM PDT 24
Finished Jul 11 06:22:32 PM PDT 24
Peak memory 219084 kb
Host smart-e099fbe1-2b3e-42c2-96d5-c6aea0fc353f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875865035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1875865035
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.3651373532
Short name T15
Test name
Test status
Simulation time 67992043400 ps
CPU time 618.71 seconds
Started Jul 11 04:28:45 PM PDT 24
Finished Jul 11 04:39:05 PM PDT 24
Peak memory 235704 kb
Host smart-e69e7d5a-6836-400f-973e-d1cde11b4fdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651373532 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.3651373532
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2628566615
Short name T214
Test name
Test status
Simulation time 16400273413 ps
CPU time 43.2 seconds
Started Jul 11 04:28:48 PM PDT 24
Finished Jul 11 04:29:33 PM PDT 24
Peak memory 216620 kb
Host smart-f1ce0ce7-9514-4240-937f-fda2e424bdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628566615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2628566615
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1600858593
Short name T85
Test name
Test status
Simulation time 9243661828 ps
CPU time 22.29 seconds
Started Jul 11 06:19:23 PM PDT 24
Finished Jul 11 06:19:48 PM PDT 24
Peak memory 212296 kb
Host smart-d8cdf9e8-3428-4971-8a5c-b806ab217eee
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600858593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1600858593
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1646700460
Short name T60
Test name
Test status
Simulation time 214245648 ps
CPU time 8.74 seconds
Started Jul 11 06:19:23 PM PDT 24
Finished Jul 11 06:19:34 PM PDT 24
Peak memory 210716 kb
Host smart-fb78d60d-d83f-4549-b128-f2f79f35bd48
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646700460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1646700460
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.603713394
Short name T454
Test name
Test status
Simulation time 698619841 ps
CPU time 15.27 seconds
Started Jul 11 06:19:26 PM PDT 24
Finished Jul 11 06:19:43 PM PDT 24
Peak memory 211944 kb
Host smart-2fbe93c0-f729-461a-869a-435254fef16c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603713394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.603713394
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1209616246
Short name T410
Test name
Test status
Simulation time 4582240685 ps
CPU time 21.98 seconds
Started Jul 11 06:19:43 PM PDT 24
Finished Jul 11 06:20:07 PM PDT 24
Peak memory 215588 kb
Host smart-8d7a485e-b471-4632-b2bd-4b089dcdd232
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209616246 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1209616246
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2963859687
Short name T439
Test name
Test status
Simulation time 2216983316 ps
CPU time 20.93 seconds
Started Jul 11 06:19:32 PM PDT 24
Finished Jul 11 06:19:56 PM PDT 24
Peak memory 211540 kb
Host smart-9e74b8b1-5dc9-43bb-a48b-00427c84cb14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963859687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2963859687
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1789511134
Short name T442
Test name
Test status
Simulation time 4203309154 ps
CPU time 32.35 seconds
Started Jul 11 06:19:36 PM PDT 24
Finished Jul 11 06:20:10 PM PDT 24
Peak memory 210716 kb
Host smart-5dbc1442-9b8f-4bef-9f1d-e9ef02751ff1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789511134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1789511134
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3584549276
Short name T409
Test name
Test status
Simulation time 1101036715 ps
CPU time 8.18 seconds
Started Jul 11 06:19:30 PM PDT 24
Finished Jul 11 06:19:41 PM PDT 24
Peak memory 210648 kb
Host smart-e0dbede9-5824-460e-abfb-ea0e1124ab72
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584549276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3584549276
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2317968778
Short name T419
Test name
Test status
Simulation time 13937773941 ps
CPU time 80.61 seconds
Started Jul 11 06:19:43 PM PDT 24
Finished Jul 11 06:21:06 PM PDT 24
Peak memory 215008 kb
Host smart-50dc0d1d-cb33-4279-9ab6-ca6417338b32
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317968778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2317968778
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3568753443
Short name T418
Test name
Test status
Simulation time 3902869510 ps
CPU time 30.04 seconds
Started Jul 11 06:19:43 PM PDT 24
Finished Jul 11 06:20:16 PM PDT 24
Peak memory 212340 kb
Host smart-3ae3caff-01b0-426e-a6e0-ad5a0296f81b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568753443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3568753443
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2914638954
Short name T447
Test name
Test status
Simulation time 3211877358 ps
CPU time 31.64 seconds
Started Jul 11 06:19:43 PM PDT 24
Finished Jul 11 06:20:16 PM PDT 24
Peak memory 219044 kb
Host smart-8546026f-8eac-48e9-a56b-75412f4e2900
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914638954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2914638954
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1580918318
Short name T421
Test name
Test status
Simulation time 283125859 ps
CPU time 82.15 seconds
Started Jul 11 06:19:30 PM PDT 24
Finished Jul 11 06:20:54 PM PDT 24
Peak memory 213804 kb
Host smart-8bc45daf-445c-4721-8aa1-1a4b2dc52f04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580918318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1580918318
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3523195635
Short name T84
Test name
Test status
Simulation time 41167095143 ps
CPU time 29.81 seconds
Started Jul 11 06:19:33 PM PDT 24
Finished Jul 11 06:20:06 PM PDT 24
Peak memory 211852 kb
Host smart-aa76887a-2fba-47e8-a291-358c95906339
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523195635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3523195635
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2523987771
Short name T417
Test name
Test status
Simulation time 660861783 ps
CPU time 8.68 seconds
Started Jul 11 06:19:43 PM PDT 24
Finished Jul 11 06:19:54 PM PDT 24
Peak memory 210756 kb
Host smart-f28648c4-551e-4dc6-ba1f-981c3e7a0de9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523987771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2523987771
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.567179126
Short name T416
Test name
Test status
Simulation time 7703180155 ps
CPU time 23.09 seconds
Started Jul 11 06:19:31 PM PDT 24
Finished Jul 11 06:19:57 PM PDT 24
Peak memory 212172 kb
Host smart-44c77678-1b57-425f-a173-43e348a6fd70
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567179126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.567179126
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3229666713
Short name T453
Test name
Test status
Simulation time 4644037131 ps
CPU time 22.93 seconds
Started Jul 11 06:19:48 PM PDT 24
Finished Jul 11 06:20:13 PM PDT 24
Peak memory 218836 kb
Host smart-aa618726-2946-44a0-ba01-637515888694
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229666713 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3229666713
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4232453426
Short name T444
Test name
Test status
Simulation time 2144066229 ps
CPU time 11.95 seconds
Started Jul 11 06:19:30 PM PDT 24
Finished Jul 11 06:19:44 PM PDT 24
Peak memory 211076 kb
Host smart-10d730c2-a8d5-40e7-9c00-a4be7831d457
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232453426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.4232453426
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4029334590
Short name T368
Test name
Test status
Simulation time 4420124315 ps
CPU time 22.16 seconds
Started Jul 11 06:19:30 PM PDT 24
Finished Jul 11 06:19:55 PM PDT 24
Peak memory 210584 kb
Host smart-0df0faf0-394b-4f34-a53c-f4df0968dd43
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029334590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.4029334590
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1339783922
Short name T388
Test name
Test status
Simulation time 179823455 ps
CPU time 8.17 seconds
Started Jul 11 06:19:30 PM PDT 24
Finished Jul 11 06:19:41 PM PDT 24
Peak memory 210652 kb
Host smart-df20d6e3-0209-42c9-97e6-57bab657c79f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339783922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1339783922
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.508103747
Short name T408
Test name
Test status
Simulation time 6374877978 ps
CPU time 73.68 seconds
Started Jul 11 06:19:21 PM PDT 24
Finished Jul 11 06:20:37 PM PDT 24
Peak memory 214236 kb
Host smart-dfb4f275-e4fe-48c8-81b0-dced1cea132a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508103747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.508103747
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1154756142
Short name T430
Test name
Test status
Simulation time 2748394991 ps
CPU time 8.3 seconds
Started Jul 11 06:19:33 PM PDT 24
Finished Jul 11 06:19:45 PM PDT 24
Peak memory 211324 kb
Host smart-341826ef-fcc9-4c45-9a42-e999337ab057
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154756142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1154756142
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.325831716
Short name T373
Test name
Test status
Simulation time 4731202288 ps
CPU time 22.4 seconds
Started Jul 11 06:19:43 PM PDT 24
Finished Jul 11 06:20:08 PM PDT 24
Peak memory 217324 kb
Host smart-0535fff1-3f9f-46f7-a4a7-05afb2002a03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325831716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.325831716
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2134188407
Short name T57
Test name
Test status
Simulation time 3095565375 ps
CPU time 97.22 seconds
Started Jul 11 06:19:23 PM PDT 24
Finished Jul 11 06:21:03 PM PDT 24
Peak memory 213856 kb
Host smart-8b9439d4-d3a7-4979-b7e1-683128b8c0e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134188407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2134188407
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1297983713
Short name T411
Test name
Test status
Simulation time 2493999451 ps
CPU time 16.83 seconds
Started Jul 11 06:19:41 PM PDT 24
Finished Jul 11 06:19:59 PM PDT 24
Peak memory 216520 kb
Host smart-5b47ceba-1638-4ebc-bb31-86abee63ca80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297983713 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1297983713
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3333377566
Short name T406
Test name
Test status
Simulation time 167363278 ps
CPU time 8.1 seconds
Started Jul 11 06:19:47 PM PDT 24
Finished Jul 11 06:19:57 PM PDT 24
Peak memory 210868 kb
Host smart-6a707572-a21b-4e50-971f-56a33dbb3fc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333377566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3333377566
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2373000200
Short name T100
Test name
Test status
Simulation time 29623719240 ps
CPU time 38 seconds
Started Jul 11 06:19:42 PM PDT 24
Finished Jul 11 06:20:21 PM PDT 24
Peak memory 212764 kb
Host smart-32c542af-c66b-4c99-833d-e82a0a48a350
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373000200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2373000200
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3426365291
Short name T429
Test name
Test status
Simulation time 6204031844 ps
CPU time 22.04 seconds
Started Jul 11 06:19:47 PM PDT 24
Finished Jul 11 06:20:11 PM PDT 24
Peak memory 217800 kb
Host smart-45f45651-3f40-4424-9e47-00bca6ec7f32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426365291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3426365291
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1344422185
Short name T112
Test name
Test status
Simulation time 25652265161 ps
CPU time 100.01 seconds
Started Jul 11 06:19:43 PM PDT 24
Finished Jul 11 06:21:26 PM PDT 24
Peak memory 212836 kb
Host smart-a6f0b0a3-481e-498e-926e-3adf109152a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344422185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1344422185
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3330863190
Short name T362
Test name
Test status
Simulation time 11696040790 ps
CPU time 26.64 seconds
Started Jul 11 06:19:42 PM PDT 24
Finished Jul 11 06:20:10 PM PDT 24
Peak memory 218704 kb
Host smart-0a90a832-5090-487c-aa4a-fc83964fc69e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330863190 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3330863190
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1482913954
Short name T383
Test name
Test status
Simulation time 636779807 ps
CPU time 8.72 seconds
Started Jul 11 06:19:42 PM PDT 24
Finished Jul 11 06:19:53 PM PDT 24
Peak memory 210720 kb
Host smart-93d520fa-2653-4351-8fcd-5ef2c53363ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482913954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1482913954
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1019631152
Short name T83
Test name
Test status
Simulation time 14438784226 ps
CPU time 120.03 seconds
Started Jul 11 06:19:44 PM PDT 24
Finished Jul 11 06:21:46 PM PDT 24
Peak memory 214300 kb
Host smart-2870bfeb-825c-450b-85f9-dd2e76b4be06
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019631152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1019631152
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1305328890
Short name T99
Test name
Test status
Simulation time 870205181 ps
CPU time 8.41 seconds
Started Jul 11 06:19:47 PM PDT 24
Finished Jul 11 06:19:57 PM PDT 24
Peak memory 211148 kb
Host smart-692ea9e6-97d2-426a-8123-db1f0ec8f100
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305328890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1305328890
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3072151644
Short name T384
Test name
Test status
Simulation time 26054371665 ps
CPU time 30.48 seconds
Started Jul 11 06:19:43 PM PDT 24
Finished Jul 11 06:20:16 PM PDT 24
Peak memory 218928 kb
Host smart-12d546df-3a72-445d-881f-cb61596a1d04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072151644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3072151644
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2325350488
Short name T115
Test name
Test status
Simulation time 405095512 ps
CPU time 156.33 seconds
Started Jul 11 06:19:46 PM PDT 24
Finished Jul 11 06:22:24 PM PDT 24
Peak memory 214104 kb
Host smart-b79f3007-8c8f-4f1b-b00e-9aba068adcdf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325350488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2325350488
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2134989717
Short name T405
Test name
Test status
Simulation time 751543087 ps
CPU time 9.15 seconds
Started Jul 11 06:19:44 PM PDT 24
Finished Jul 11 06:19:55 PM PDT 24
Peak memory 216920 kb
Host smart-1c9aa0b8-cdd6-4ff3-8b08-ea4d5f8ac26b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134989717 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2134989717
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.484127847
Short name T87
Test name
Test status
Simulation time 534386150 ps
CPU time 7.9 seconds
Started Jul 11 06:19:45 PM PDT 24
Finished Jul 11 06:19:55 PM PDT 24
Peak memory 210708 kb
Host smart-0c174ee4-d568-4b0f-9635-d61d5a2dda83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484127847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.484127847
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.356805587
Short name T435
Test name
Test status
Simulation time 11084528696 ps
CPU time 103.84 seconds
Started Jul 11 06:19:46 PM PDT 24
Finished Jul 11 06:21:32 PM PDT 24
Peak memory 214948 kb
Host smart-dc905403-60aa-4659-ac84-ea027d8ebfda
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356805587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.356805587
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2102168853
Short name T61
Test name
Test status
Simulation time 2472429838 ps
CPU time 26 seconds
Started Jul 11 06:19:43 PM PDT 24
Finished Jul 11 06:20:12 PM PDT 24
Peak memory 212516 kb
Host smart-0615a667-8e69-4f7a-906a-470682d87757
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102168853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2102168853
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2158027001
Short name T400
Test name
Test status
Simulation time 8864947812 ps
CPU time 27.85 seconds
Started Jul 11 06:19:44 PM PDT 24
Finished Jul 11 06:20:14 PM PDT 24
Peak memory 218872 kb
Host smart-eb8942be-ad4b-4f98-9a4f-a4b242d6847d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158027001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2158027001
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2850575496
Short name T363
Test name
Test status
Simulation time 794951395 ps
CPU time 8.98 seconds
Started Jul 11 06:19:51 PM PDT 24
Finished Jul 11 06:20:01 PM PDT 24
Peak memory 215960 kb
Host smart-5f6bb6a0-637c-44f9-b988-823df04dbddb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850575496 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2850575496
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1831942405
Short name T381
Test name
Test status
Simulation time 5011241521 ps
CPU time 24.04 seconds
Started Jul 11 06:19:46 PM PDT 24
Finished Jul 11 06:20:12 PM PDT 24
Peak memory 212284 kb
Host smart-453725b6-e689-4334-8e0b-b45b30acd0df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831942405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1831942405
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.593018150
Short name T106
Test name
Test status
Simulation time 1438383345 ps
CPU time 38.49 seconds
Started Jul 11 06:19:45 PM PDT 24
Finished Jul 11 06:20:26 PM PDT 24
Peak memory 218960 kb
Host smart-1c67ede7-8241-4954-9942-96ba05d288d8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593018150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.593018150
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2702360993
Short name T431
Test name
Test status
Simulation time 36737127216 ps
CPU time 21.69 seconds
Started Jul 11 06:19:41 PM PDT 24
Finished Jul 11 06:20:04 PM PDT 24
Peak memory 212724 kb
Host smart-d0a1bab8-8561-419c-a88b-18b4e63f34d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702360993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2702360993
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.583048016
Short name T440
Test name
Test status
Simulation time 16021923443 ps
CPU time 33.89 seconds
Started Jul 11 06:19:44 PM PDT 24
Finished Jul 11 06:20:20 PM PDT 24
Peak memory 218692 kb
Host smart-3a08ac1d-c6a1-4b08-8a78-2ac020c54dd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583048016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.583048016
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1277167314
Short name T422
Test name
Test status
Simulation time 4169032619 ps
CPU time 32.81 seconds
Started Jul 11 06:19:52 PM PDT 24
Finished Jul 11 06:20:26 PM PDT 24
Peak memory 217000 kb
Host smart-a6787627-d5b1-42f8-bb80-6938b75a8478
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277167314 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1277167314
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.4019608492
Short name T68
Test name
Test status
Simulation time 16589773034 ps
CPU time 33.48 seconds
Started Jul 11 06:19:57 PM PDT 24
Finished Jul 11 06:20:33 PM PDT 24
Peak memory 212260 kb
Host smart-72e5f6b6-c36a-4542-b3c9-9026880f5bae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019608492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.4019608492
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1668868716
Short name T70
Test name
Test status
Simulation time 720214190 ps
CPU time 37.06 seconds
Started Jul 11 06:19:51 PM PDT 24
Finished Jul 11 06:20:29 PM PDT 24
Peak memory 213856 kb
Host smart-7391eddf-cd9b-4baa-9242-4620d88f3ec0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668868716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1668868716
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.130726777
Short name T72
Test name
Test status
Simulation time 174429483 ps
CPU time 8.02 seconds
Started Jul 11 06:19:51 PM PDT 24
Finished Jul 11 06:20:00 PM PDT 24
Peak memory 211100 kb
Host smart-a58c4b70-f704-441a-97dd-e9fe31fd3261
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130726777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.130726777
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2647713091
Short name T428
Test name
Test status
Simulation time 8527785562 ps
CPU time 25 seconds
Started Jul 11 06:19:50 PM PDT 24
Finished Jul 11 06:20:16 PM PDT 24
Peak memory 218964 kb
Host smart-cf7e24a6-8c82-481c-8912-05c3d47ca097
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647713091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2647713091
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1247733852
Short name T117
Test name
Test status
Simulation time 5390652012 ps
CPU time 93.95 seconds
Started Jul 11 06:19:50 PM PDT 24
Finished Jul 11 06:21:25 PM PDT 24
Peak memory 212632 kb
Host smart-fd4c2ada-1cd6-4aa6-9e8a-68cda02be015
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247733852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1247733852
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1042365781
Short name T377
Test name
Test status
Simulation time 424362808 ps
CPU time 11.65 seconds
Started Jul 11 06:19:52 PM PDT 24
Finished Jul 11 06:20:05 PM PDT 24
Peak memory 216392 kb
Host smart-ddeb869b-069c-4fe4-955f-b6cd533a69cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042365781 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1042365781
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2565196835
Short name T450
Test name
Test status
Simulation time 3679871006 ps
CPU time 28.06 seconds
Started Jul 11 06:19:52 PM PDT 24
Finished Jul 11 06:20:22 PM PDT 24
Peak memory 211756 kb
Host smart-f470e267-8029-4e75-99ba-a4228931b7ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565196835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2565196835
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3073419330
Short name T378
Test name
Test status
Simulation time 98499889180 ps
CPU time 189.97 seconds
Started Jul 11 06:19:52 PM PDT 24
Finished Jul 11 06:23:03 PM PDT 24
Peak memory 215192 kb
Host smart-061dcbc7-f916-401b-825d-6fcf7b57f809
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073419330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3073419330
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.224794956
Short name T424
Test name
Test status
Simulation time 11963220712 ps
CPU time 25.09 seconds
Started Jul 11 06:19:52 PM PDT 24
Finished Jul 11 06:20:18 PM PDT 24
Peak memory 212744 kb
Host smart-6ac156c4-6aed-4dfd-8f98-7fb463bd8835
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224794956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.224794956
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.719343836
Short name T65
Test name
Test status
Simulation time 1822624967 ps
CPU time 22.6 seconds
Started Jul 11 06:19:53 PM PDT 24
Finished Jul 11 06:20:17 PM PDT 24
Peak memory 217456 kb
Host smart-ac0ac579-619d-4751-9fbc-955336d18d00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719343836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.719343836
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1844432969
Short name T114
Test name
Test status
Simulation time 3489291475 ps
CPU time 101.22 seconds
Started Jul 11 06:19:59 PM PDT 24
Finished Jul 11 06:21:43 PM PDT 24
Peak memory 213544 kb
Host smart-41ac767b-e3be-4d03-9eaa-55461b674d18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844432969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1844432969
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1372646332
Short name T401
Test name
Test status
Simulation time 11133511192 ps
CPU time 24.26 seconds
Started Jul 11 06:19:52 PM PDT 24
Finished Jul 11 06:20:18 PM PDT 24
Peak memory 216340 kb
Host smart-308784e1-ab3c-4fa5-b507-52f690dc7e7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372646332 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1372646332
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2423809912
Short name T88
Test name
Test status
Simulation time 787644949 ps
CPU time 8.24 seconds
Started Jul 11 06:19:52 PM PDT 24
Finished Jul 11 06:20:01 PM PDT 24
Peak memory 210784 kb
Host smart-6261397b-ec7e-4d2e-9132-f0fbebb08eb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423809912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2423809912
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.680296101
Short name T86
Test name
Test status
Simulation time 17742767181 ps
CPU time 136.67 seconds
Started Jul 11 06:19:53 PM PDT 24
Finished Jul 11 06:22:11 PM PDT 24
Peak memory 213912 kb
Host smart-4f566d55-ac45-4484-8bae-708765c801b4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680296101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.680296101
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2612509569
Short name T71
Test name
Test status
Simulation time 170969729 ps
CPU time 8.64 seconds
Started Jul 11 06:19:49 PM PDT 24
Finished Jul 11 06:19:59 PM PDT 24
Peak memory 211452 kb
Host smart-e26c2554-b6d2-4079-9602-8a29cbdc65f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612509569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2612509569
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2252607064
Short name T427
Test name
Test status
Simulation time 19965039902 ps
CPU time 36.77 seconds
Started Jul 11 06:19:58 PM PDT 24
Finished Jul 11 06:20:38 PM PDT 24
Peak memory 217756 kb
Host smart-863c310f-7d35-4a4c-ad4f-2bb32a81bb8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252607064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2252607064
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4033365071
Short name T414
Test name
Test status
Simulation time 5855877574 ps
CPU time 160.3 seconds
Started Jul 11 06:19:50 PM PDT 24
Finished Jul 11 06:22:31 PM PDT 24
Peak memory 214092 kb
Host smart-3f146396-ece8-422b-95dc-8c0201467b8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033365071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.4033365071
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3075428248
Short name T432
Test name
Test status
Simulation time 679022356 ps
CPU time 8.9 seconds
Started Jul 11 06:20:00 PM PDT 24
Finished Jul 11 06:20:11 PM PDT 24
Peak memory 219016 kb
Host smart-d0d817aa-6c48-4237-98f6-4dadeda90cef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075428248 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3075428248
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2533117479
Short name T412
Test name
Test status
Simulation time 19340750684 ps
CPU time 21.52 seconds
Started Jul 11 06:19:51 PM PDT 24
Finished Jul 11 06:20:14 PM PDT 24
Peak memory 212632 kb
Host smart-dced83db-88ec-4160-bbd4-e5a4e73846e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533117479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2533117479
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2980362270
Short name T426
Test name
Test status
Simulation time 12672877834 ps
CPU time 109.98 seconds
Started Jul 11 06:19:51 PM PDT 24
Finished Jul 11 06:21:43 PM PDT 24
Peak memory 213924 kb
Host smart-60dae9c6-bb17-4928-aeb4-6b15680c1bad
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980362270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2980362270
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1998753739
Short name T393
Test name
Test status
Simulation time 338122149 ps
CPU time 12.52 seconds
Started Jul 11 06:19:56 PM PDT 24
Finished Jul 11 06:20:11 PM PDT 24
Peak memory 212380 kb
Host smart-f7c23d7a-259d-4fba-aab8-26079b1351cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998753739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1998753739
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3349467951
Short name T443
Test name
Test status
Simulation time 16735678617 ps
CPU time 34.97 seconds
Started Jul 11 06:19:51 PM PDT 24
Finished Jul 11 06:20:27 PM PDT 24
Peak memory 217672 kb
Host smart-97810c98-c52c-4933-8d77-978b6e3075de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349467951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3349467951
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3786141696
Short name T445
Test name
Test status
Simulation time 11754961815 ps
CPU time 25.15 seconds
Started Jul 11 06:19:57 PM PDT 24
Finished Jul 11 06:20:24 PM PDT 24
Peak memory 218040 kb
Host smart-28354177-6736-4630-8a5d-4c4171004a49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786141696 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3786141696
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3388538188
Short name T102
Test name
Test status
Simulation time 21034661888 ps
CPU time 25.59 seconds
Started Jul 11 06:19:55 PM PDT 24
Finished Jul 11 06:20:22 PM PDT 24
Peak memory 211348 kb
Host smart-faacf2c8-ccfa-4792-adb9-55c939447e24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388538188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3388538188
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1043719670
Short name T415
Test name
Test status
Simulation time 1977137009 ps
CPU time 17.91 seconds
Started Jul 11 06:19:56 PM PDT 24
Finished Jul 11 06:20:16 PM PDT 24
Peak memory 212476 kb
Host smart-6f2593fc-69d8-437c-b248-7fac5265b4fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043719670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1043719670
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1223839203
Short name T369
Test name
Test status
Simulation time 2192641705 ps
CPU time 18.36 seconds
Started Jul 11 06:19:56 PM PDT 24
Finished Jul 11 06:20:17 PM PDT 24
Peak memory 218256 kb
Host smart-ebba171d-f52a-4f85-8042-fc2b8008c919
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223839203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1223839203
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1845447744
Short name T113
Test name
Test status
Simulation time 7452009886 ps
CPU time 163.02 seconds
Started Jul 11 06:19:54 PM PDT 24
Finished Jul 11 06:22:39 PM PDT 24
Peak memory 214112 kb
Host smart-b4efa63c-822d-4827-86f8-56766fe0d325
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845447744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1845447744
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3965523567
Short name T370
Test name
Test status
Simulation time 746256805 ps
CPU time 8.97 seconds
Started Jul 11 06:19:58 PM PDT 24
Finished Jul 11 06:20:09 PM PDT 24
Peak memory 216000 kb
Host smart-e1d15d7d-a9de-4552-a56f-89f1ee505743
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965523567 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3965523567
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3135355632
Short name T96
Test name
Test status
Simulation time 5319612386 ps
CPU time 16.96 seconds
Started Jul 11 06:19:57 PM PDT 24
Finished Jul 11 06:20:17 PM PDT 24
Peak memory 212440 kb
Host smart-2c4733a4-51ce-47e3-a428-8bc6a73cb750
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135355632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3135355632
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.536391710
Short name T449
Test name
Test status
Simulation time 6186395474 ps
CPU time 75.55 seconds
Started Jul 11 06:19:57 PM PDT 24
Finished Jul 11 06:21:16 PM PDT 24
Peak memory 214728 kb
Host smart-3015ff2a-ead7-4b2c-a45b-474e7ea86f81
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536391710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.536391710
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1462659902
Short name T379
Test name
Test status
Simulation time 8532974918 ps
CPU time 32.47 seconds
Started Jul 11 06:19:56 PM PDT 24
Finished Jul 11 06:20:30 PM PDT 24
Peak memory 212696 kb
Host smart-26c2ba3e-86c8-4104-bf94-b415b89d2207
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462659902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1462659902
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2501432545
Short name T434
Test name
Test status
Simulation time 869544970 ps
CPU time 13.02 seconds
Started Jul 11 06:19:58 PM PDT 24
Finished Jul 11 06:20:14 PM PDT 24
Peak memory 219068 kb
Host smart-e8f4232f-496a-4a78-a3f4-41cdbd066726
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501432545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2501432545
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.607821337
Short name T97
Test name
Test status
Simulation time 1564166952 ps
CPU time 18.32 seconds
Started Jul 11 06:19:33 PM PDT 24
Finished Jul 11 06:19:54 PM PDT 24
Peak memory 211280 kb
Host smart-3f7eb3f9-f5d9-4659-b000-84ad5af18667
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607821337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.607821337
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2554229522
Short name T372
Test name
Test status
Simulation time 2606367376 ps
CPU time 24.69 seconds
Started Jul 11 06:19:35 PM PDT 24
Finished Jul 11 06:20:02 PM PDT 24
Peak memory 211624 kb
Host smart-525cddc5-e22a-4bbc-a11a-524e3af5e478
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554229522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2554229522
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1496571540
Short name T392
Test name
Test status
Simulation time 10985793187 ps
CPU time 22.31 seconds
Started Jul 11 06:19:35 PM PDT 24
Finished Jul 11 06:20:00 PM PDT 24
Peak memory 212192 kb
Host smart-9b13755a-5969-4c8b-a591-08ee22bcbfbc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496571540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1496571540
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1213636946
Short name T394
Test name
Test status
Simulation time 2565852965 ps
CPU time 12.6 seconds
Started Jul 11 06:19:32 PM PDT 24
Finished Jul 11 06:19:48 PM PDT 24
Peak memory 217064 kb
Host smart-42017f6e-b3c7-4b1b-b929-2daebb3ff587
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213636946 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1213636946
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2012297243
Short name T376
Test name
Test status
Simulation time 176185288 ps
CPU time 8.29 seconds
Started Jul 11 06:19:33 PM PDT 24
Finished Jul 11 06:19:45 PM PDT 24
Peak memory 210632 kb
Host smart-5d8a8730-2e31-473b-94df-1c59aeb83c43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012297243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2012297243
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.654116078
Short name T448
Test name
Test status
Simulation time 24014641633 ps
CPU time 30.3 seconds
Started Jul 11 06:19:32 PM PDT 24
Finished Jul 11 06:20:06 PM PDT 24
Peak memory 210960 kb
Host smart-c48c0ca8-38ab-41f7-9e8e-45ceb3e7ed9a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654116078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.654116078
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3807540967
Short name T433
Test name
Test status
Simulation time 687759573 ps
CPU time 8.26 seconds
Started Jul 11 06:19:31 PM PDT 24
Finished Jul 11 06:19:42 PM PDT 24
Peak memory 210628 kb
Host smart-024c3e05-29ef-421f-b3f0-ff6c7dcc32a6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807540967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3807540967
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3365980773
Short name T374
Test name
Test status
Simulation time 174437262 ps
CPU time 8.25 seconds
Started Jul 11 06:19:33 PM PDT 24
Finished Jul 11 06:19:44 PM PDT 24
Peak memory 211464 kb
Host smart-1e308e0c-bdb7-426e-9759-316007624dc7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365980773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3365980773
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.130507578
Short name T371
Test name
Test status
Simulation time 5895378764 ps
CPU time 20.37 seconds
Started Jul 11 06:19:32 PM PDT 24
Finished Jul 11 06:19:56 PM PDT 24
Peak memory 218664 kb
Host smart-6b5ade31-fe80-4e41-a10b-4c423034e48b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130507578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.130507578
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.114951324
Short name T103
Test name
Test status
Simulation time 2172766764 ps
CPU time 18.99 seconds
Started Jul 11 06:19:34 PM PDT 24
Finished Jul 11 06:19:56 PM PDT 24
Peak memory 211812 kb
Host smart-853b2296-4ace-4c62-90eb-7aa6f16b5349
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114951324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.114951324
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2003824828
Short name T375
Test name
Test status
Simulation time 1883630945 ps
CPU time 20.3 seconds
Started Jul 11 06:19:43 PM PDT 24
Finished Jul 11 06:20:05 PM PDT 24
Peak memory 211024 kb
Host smart-4b414539-70b3-4f47-a055-3a3fcfcdcd39
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003824828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2003824828
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1046704122
Short name T101
Test name
Test status
Simulation time 674714525 ps
CPU time 13.46 seconds
Started Jul 11 06:19:48 PM PDT 24
Finished Jul 11 06:20:03 PM PDT 24
Peak memory 210764 kb
Host smart-816ad101-4919-4773-a427-af209f0d4919
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046704122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1046704122
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.815083675
Short name T391
Test name
Test status
Simulation time 762075635 ps
CPU time 8.48 seconds
Started Jul 11 06:19:31 PM PDT 24
Finished Jul 11 06:19:43 PM PDT 24
Peak memory 214952 kb
Host smart-94be7e01-0c58-473d-9c14-8717fec2859a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815083675 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.815083675
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2640314005
Short name T395
Test name
Test status
Simulation time 6975283908 ps
CPU time 27.18 seconds
Started Jul 11 06:19:36 PM PDT 24
Finished Jul 11 06:20:05 PM PDT 24
Peak memory 211748 kb
Host smart-8d779862-efc1-4148-b4a9-aa4dfa6ad4b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640314005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2640314005
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3526533262
Short name T366
Test name
Test status
Simulation time 4383034711 ps
CPU time 32.3 seconds
Started Jul 11 06:19:32 PM PDT 24
Finished Jul 11 06:20:08 PM PDT 24
Peak memory 210716 kb
Host smart-64a1177f-dba8-4e0b-8a16-6b3c48c40fee
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526533262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3526533262
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2816754255
Short name T396
Test name
Test status
Simulation time 25123468081 ps
CPU time 32.78 seconds
Started Jul 11 06:19:36 PM PDT 24
Finished Jul 11 06:20:11 PM PDT 24
Peak memory 211004 kb
Host smart-c2a53cee-4bd9-4eab-98a2-be4a355598e8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816754255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2816754255
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.975337342
Short name T98
Test name
Test status
Simulation time 6698711164 ps
CPU time 98.7 seconds
Started Jul 11 06:19:43 PM PDT 24
Finished Jul 11 06:21:24 PM PDT 24
Peak memory 218848 kb
Host smart-5b620fba-d1a5-4377-a608-9d61583cf29e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975337342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.975337342
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1091469399
Short name T75
Test name
Test status
Simulation time 787316937 ps
CPU time 8.35 seconds
Started Jul 11 06:19:33 PM PDT 24
Finished Jul 11 06:19:45 PM PDT 24
Peak memory 211356 kb
Host smart-b20f5d00-7f5a-45fb-9ed5-3540e18676a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091469399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1091469399
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.731350793
Short name T413
Test name
Test status
Simulation time 172853778 ps
CPU time 12.83 seconds
Started Jul 11 06:19:33 PM PDT 24
Finished Jul 11 06:19:49 PM PDT 24
Peak memory 217524 kb
Host smart-d7295e0d-1f86-4819-9b5a-e9b6c59abf41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731350793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.731350793
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2796282856
Short name T452
Test name
Test status
Simulation time 11575961773 ps
CPU time 170.19 seconds
Started Jul 11 06:19:33 PM PDT 24
Finished Jul 11 06:22:27 PM PDT 24
Peak memory 214344 kb
Host smart-1ccd27e6-27a2-42a8-b64c-f127f83acb00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796282856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2796282856
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2126452862
Short name T90
Test name
Test status
Simulation time 24992365475 ps
CPU time 33.5 seconds
Started Jul 11 06:19:48 PM PDT 24
Finished Jul 11 06:20:23 PM PDT 24
Peak memory 212264 kb
Host smart-dad32387-add5-406c-93ca-3316e029f4b1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126452862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2126452862
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.664252460
Short name T380
Test name
Test status
Simulation time 170803362 ps
CPU time 8.45 seconds
Started Jul 11 06:19:38 PM PDT 24
Finished Jul 11 06:19:48 PM PDT 24
Peak memory 210924 kb
Host smart-c48c843d-8736-44e7-a625-9c33c5334a33
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664252460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.664252460
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3962690278
Short name T93
Test name
Test status
Simulation time 2699148760 ps
CPU time 25.76 seconds
Started Jul 11 06:19:48 PM PDT 24
Finished Jul 11 06:20:16 PM PDT 24
Peak memory 210828 kb
Host smart-4203bf59-4ee3-4c3c-9728-cd4ddd85c0b0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962690278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3962690278
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.895119353
Short name T438
Test name
Test status
Simulation time 3023209522 ps
CPU time 25.96 seconds
Started Jul 11 06:19:47 PM PDT 24
Finished Jul 11 06:20:15 PM PDT 24
Peak memory 215780 kb
Host smart-d4ce903a-9fe2-4632-8266-973ec1f0df3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895119353 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.895119353
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1668228604
Short name T398
Test name
Test status
Simulation time 1671999709 ps
CPU time 18.56 seconds
Started Jul 11 06:19:38 PM PDT 24
Finished Jul 11 06:19:58 PM PDT 24
Peak memory 211912 kb
Host smart-ef7e9d5a-e47d-40e8-807b-fafe28f09f0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668228604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1668228604
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2834394494
Short name T387
Test name
Test status
Simulation time 4335452100 ps
CPU time 21.44 seconds
Started Jul 11 06:19:31 PM PDT 24
Finished Jul 11 06:19:55 PM PDT 24
Peak memory 210972 kb
Host smart-8985f4b3-0682-4d9d-960b-3d61f9e21a92
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834394494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2834394494
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1984820503
Short name T441
Test name
Test status
Simulation time 1375066374 ps
CPU time 8.44 seconds
Started Jul 11 06:19:31 PM PDT 24
Finished Jul 11 06:19:43 PM PDT 24
Peak memory 210660 kb
Host smart-6c6bb12d-431d-4ada-a8cc-dfd00335c0a8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984820503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1984820503
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2134715233
Short name T94
Test name
Test status
Simulation time 68077713052 ps
CPU time 135.41 seconds
Started Jul 11 06:19:34 PM PDT 24
Finished Jul 11 06:21:52 PM PDT 24
Peak memory 214284 kb
Host smart-b1bbc5f0-0f75-4978-a305-f2365e9e1704
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134715233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2134715233
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1786561217
Short name T74
Test name
Test status
Simulation time 1503799941 ps
CPU time 18.12 seconds
Started Jul 11 06:19:39 PM PDT 24
Finished Jul 11 06:19:59 PM PDT 24
Peak memory 211416 kb
Host smart-f95de688-ca3e-4ff0-89fe-97f17815555c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786561217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1786561217
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3743702186
Short name T423
Test name
Test status
Simulation time 2689649864 ps
CPU time 22.94 seconds
Started Jul 11 06:19:32 PM PDT 24
Finished Jul 11 06:19:59 PM PDT 24
Peak memory 217312 kb
Host smart-66a9e1d2-74da-45de-8aac-f39f2c1f0266
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743702186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3743702186
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2363010402
Short name T108
Test name
Test status
Simulation time 309504124 ps
CPU time 82.47 seconds
Started Jul 11 06:19:48 PM PDT 24
Finished Jul 11 06:21:12 PM PDT 24
Peak memory 213664 kb
Host smart-7366f933-c706-4337-861f-69bc3c3bba30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363010402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2363010402
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2279689652
Short name T364
Test name
Test status
Simulation time 177232154 ps
CPU time 8.93 seconds
Started Jul 11 06:19:38 PM PDT 24
Finished Jul 11 06:19:48 PM PDT 24
Peak memory 215848 kb
Host smart-18f7a2fb-9911-4d25-8ecf-36a443d4b2dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279689652 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2279689652
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2111055538
Short name T404
Test name
Test status
Simulation time 15880881770 ps
CPU time 32.63 seconds
Started Jul 11 06:19:40 PM PDT 24
Finished Jul 11 06:20:14 PM PDT 24
Peak memory 211868 kb
Host smart-7ae89da3-cc7b-4f1f-8dfe-038010defc19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111055538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2111055538
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3364733588
Short name T92
Test name
Test status
Simulation time 12341439401 ps
CPU time 134.88 seconds
Started Jul 11 06:19:42 PM PDT 24
Finished Jul 11 06:21:59 PM PDT 24
Peak memory 215652 kb
Host smart-d8a5fcb3-28ba-45b3-ac15-39b7edf78913
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364733588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3364733588
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1084497636
Short name T386
Test name
Test status
Simulation time 13068024395 ps
CPU time 28.28 seconds
Started Jul 11 06:19:40 PM PDT 24
Finished Jul 11 06:20:10 PM PDT 24
Peak memory 212592 kb
Host smart-6c86d0fc-8041-46b9-9115-d7e0d8a29d8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084497636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1084497636
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3200304990
Short name T385
Test name
Test status
Simulation time 5900203976 ps
CPU time 23 seconds
Started Jul 11 06:19:45 PM PDT 24
Finished Jul 11 06:20:10 PM PDT 24
Peak memory 216924 kb
Host smart-f39a6b0b-6e96-4aa9-ac75-f850ec097eab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200304990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3200304990
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1562192114
Short name T110
Test name
Test status
Simulation time 4228584236 ps
CPU time 158.28 seconds
Started Jul 11 06:19:45 PM PDT 24
Finished Jul 11 06:22:26 PM PDT 24
Peak memory 214104 kb
Host smart-432eac77-3df1-42c7-aaf3-cbc225afe2fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562192114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1562192114
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.4086161840
Short name T367
Test name
Test status
Simulation time 3072419631 ps
CPU time 13.34 seconds
Started Jul 11 06:19:41 PM PDT 24
Finished Jul 11 06:19:55 PM PDT 24
Peak memory 219056 kb
Host smart-2fcc3b3f-5c20-4efc-b0dc-b50ccb665041
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086161840 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.4086161840
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3555920230
Short name T446
Test name
Test status
Simulation time 6365326947 ps
CPU time 18.98 seconds
Started Jul 11 06:19:45 PM PDT 24
Finished Jul 11 06:20:06 PM PDT 24
Peak memory 212044 kb
Host smart-4d1e5a64-befb-4d92-9614-95fb24a30890
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555920230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3555920230
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3519388600
Short name T89
Test name
Test status
Simulation time 130322012153 ps
CPU time 192.75 seconds
Started Jul 11 06:19:37 PM PDT 24
Finished Jul 11 06:22:51 PM PDT 24
Peak memory 215108 kb
Host smart-cb25993b-9e35-4c8c-916c-7cb61c26b145
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519388600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3519388600
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3500104331
Short name T402
Test name
Test status
Simulation time 338036987 ps
CPU time 10.56 seconds
Started Jul 11 06:19:41 PM PDT 24
Finished Jul 11 06:19:53 PM PDT 24
Peak memory 211500 kb
Host smart-5a917c5b-f1e1-4f1b-a1f8-7793af3f3f66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500104331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3500104331
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1940791959
Short name T365
Test name
Test status
Simulation time 27326915625 ps
CPU time 24.42 seconds
Started Jul 11 06:19:40 PM PDT 24
Finished Jul 11 06:20:06 PM PDT 24
Peak memory 219012 kb
Host smart-8467a936-5e38-4e1c-8c45-a76e92a4bded
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940791959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1940791959
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3562437902
Short name T455
Test name
Test status
Simulation time 1714511889 ps
CPU time 87.76 seconds
Started Jul 11 06:19:42 PM PDT 24
Finished Jul 11 06:21:12 PM PDT 24
Peak memory 213516 kb
Host smart-6dd68c39-459d-4d7e-ba09-0a6371a8be88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562437902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3562437902
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1072365055
Short name T407
Test name
Test status
Simulation time 3592406307 ps
CPU time 28.34 seconds
Started Jul 11 06:19:45 PM PDT 24
Finished Jul 11 06:20:16 PM PDT 24
Peak memory 216696 kb
Host smart-423ba712-f8ce-45f8-8b2c-2ced518ea9b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072365055 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1072365055
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2059032996
Short name T382
Test name
Test status
Simulation time 1472897512 ps
CPU time 18.47 seconds
Started Jul 11 06:19:38 PM PDT 24
Finished Jul 11 06:19:58 PM PDT 24
Peak memory 211972 kb
Host smart-c1c999ad-3277-4986-a55c-3a3f16d39de9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059032996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2059032996
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1259446301
Short name T73
Test name
Test status
Simulation time 706961756 ps
CPU time 38.5 seconds
Started Jul 11 06:19:39 PM PDT 24
Finished Jul 11 06:20:19 PM PDT 24
Peak memory 213828 kb
Host smart-f2727c11-7449-4c21-b33d-29166e72fbc5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259446301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1259446301
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3585729211
Short name T397
Test name
Test status
Simulation time 339105222 ps
CPU time 8.39 seconds
Started Jul 11 06:19:41 PM PDT 24
Finished Jul 11 06:19:51 PM PDT 24
Peak memory 211428 kb
Host smart-6e9d9627-b5b8-4605-91f0-4b088ab6052d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585729211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3585729211
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3881150335
Short name T425
Test name
Test status
Simulation time 5184287065 ps
CPU time 27.98 seconds
Started Jul 11 06:19:39 PM PDT 24
Finished Jul 11 06:20:09 PM PDT 24
Peak memory 218896 kb
Host smart-b49b5dac-b3b5-485e-9137-17de8bd19af6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881150335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3881150335
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4247155393
Short name T58
Test name
Test status
Simulation time 4118854310 ps
CPU time 104.5 seconds
Started Jul 11 06:19:42 PM PDT 24
Finished Jul 11 06:21:27 PM PDT 24
Peak memory 213216 kb
Host smart-c2af86ea-d56b-4bdd-92dc-cfc51f1c565d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247155393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.4247155393
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2178072330
Short name T389
Test name
Test status
Simulation time 356501569 ps
CPU time 8.6 seconds
Started Jul 11 06:19:44 PM PDT 24
Finished Jul 11 06:19:55 PM PDT 24
Peak memory 214612 kb
Host smart-e00fb949-12cf-442b-a656-1c4d63b4b0f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178072330 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2178072330
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2957048943
Short name T403
Test name
Test status
Simulation time 8568112196 ps
CPU time 33.29 seconds
Started Jul 11 06:19:39 PM PDT 24
Finished Jul 11 06:20:14 PM PDT 24
Peak memory 212192 kb
Host smart-9f7b5cfc-e9dc-4b04-a852-e3b8a588d224
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957048943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2957048943
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3122171396
Short name T95
Test name
Test status
Simulation time 51269960239 ps
CPU time 114.07 seconds
Started Jul 11 06:19:37 PM PDT 24
Finished Jul 11 06:21:33 PM PDT 24
Peak memory 213920 kb
Host smart-e174085e-585a-4cbb-b00d-25ea508d593f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122171396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3122171396
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1215585401
Short name T451
Test name
Test status
Simulation time 174493009 ps
CPU time 8.57 seconds
Started Jul 11 06:19:39 PM PDT 24
Finished Jul 11 06:19:49 PM PDT 24
Peak memory 211300 kb
Host smart-159ca320-0596-4392-8341-cdea7d3776b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215585401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1215585401
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3372996283
Short name T437
Test name
Test status
Simulation time 2953162504 ps
CPU time 24.26 seconds
Started Jul 11 06:19:40 PM PDT 24
Finished Jul 11 06:20:06 PM PDT 24
Peak memory 217416 kb
Host smart-e553ac03-9fde-4116-9cc7-3bfc48ca5b9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372996283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3372996283
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2352399968
Short name T116
Test name
Test status
Simulation time 5553678665 ps
CPU time 103.92 seconds
Started Jul 11 06:19:39 PM PDT 24
Finished Jul 11 06:21:24 PM PDT 24
Peak memory 213776 kb
Host smart-e70cc12c-6f86-4c62-ae9a-ad90807c24a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352399968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2352399968
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.797269821
Short name T420
Test name
Test status
Simulation time 175161876 ps
CPU time 8.55 seconds
Started Jul 11 06:19:50 PM PDT 24
Finished Jul 11 06:19:59 PM PDT 24
Peak memory 214320 kb
Host smart-aa1194aa-31cb-4fdf-9771-af6d2e835136
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797269821 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.797269821
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2960196104
Short name T436
Test name
Test status
Simulation time 167594035 ps
CPU time 8.31 seconds
Started Jul 11 06:19:50 PM PDT 24
Finished Jul 11 06:19:59 PM PDT 24
Peak memory 210668 kb
Host smart-56c4c7fa-90fd-4f76-983b-3f0180dbdcc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960196104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2960196104
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2085841432
Short name T105
Test name
Test status
Simulation time 16128257772 ps
CPU time 132.39 seconds
Started Jul 11 06:19:45 PM PDT 24
Finished Jul 11 06:22:00 PM PDT 24
Peak memory 214928 kb
Host smart-c8bd2815-9e01-4cdc-bed8-7a2daab9ccf5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085841432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2085841432
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.20364390
Short name T399
Test name
Test status
Simulation time 6226221234 ps
CPU time 30.32 seconds
Started Jul 11 06:19:47 PM PDT 24
Finished Jul 11 06:20:19 PM PDT 24
Peak memory 212692 kb
Host smart-bb0ff9af-ef55-4f77-a4f1-a6bc016b674a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20364390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctr
l_same_csr_outstanding.20364390
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.940572812
Short name T390
Test name
Test status
Simulation time 636090889 ps
CPU time 13.37 seconds
Started Jul 11 06:19:45 PM PDT 24
Finished Jul 11 06:20:01 PM PDT 24
Peak memory 217524 kb
Host smart-484083d8-aac4-4414-8a90-7410a41d3c73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940572812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.940572812
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.893323743
Short name T119
Test name
Test status
Simulation time 5197665908 ps
CPU time 87.46 seconds
Started Jul 11 06:19:43 PM PDT 24
Finished Jul 11 06:21:13 PM PDT 24
Peak memory 212768 kb
Host smart-38c04ce0-34eb-415a-82a9-f3360ce63c1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893323743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.893323743
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.682507745
Short name T304
Test name
Test status
Simulation time 174340839 ps
CPU time 8.55 seconds
Started Jul 11 04:29:52 PM PDT 24
Finished Jul 11 04:30:03 PM PDT 24
Peak memory 216964 kb
Host smart-cb81c706-f8e5-4496-97b0-a3f1b73262e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682507745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.682507745
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1736456555
Short name T39
Test name
Test status
Simulation time 50273701443 ps
CPU time 520.34 seconds
Started Jul 11 04:28:26 PM PDT 24
Finished Jul 11 04:37:08 PM PDT 24
Peak memory 219408 kb
Host smart-716851e5-dbe0-4ba2-9110-a3949c412f44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736456555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1736456555
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1943239437
Short name T266
Test name
Test status
Simulation time 345847876 ps
CPU time 18.88 seconds
Started Jul 11 04:28:22 PM PDT 24
Finished Jul 11 04:28:43 PM PDT 24
Peak memory 219172 kb
Host smart-df4a0081-951b-407e-a317-5e3c4ec10c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943239437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1943239437
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1642444229
Short name T343
Test name
Test status
Simulation time 10825525428 ps
CPU time 25.6 seconds
Started Jul 11 04:28:18 PM PDT 24
Finished Jul 11 04:28:46 PM PDT 24
Peak memory 219232 kb
Host smart-6673062c-7a55-4857-9e22-7b9b3c2a887a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1642444229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1642444229
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1644272606
Short name T26
Test name
Test status
Simulation time 4698338638 ps
CPU time 127.05 seconds
Started Jul 11 04:28:25 PM PDT 24
Finished Jul 11 04:30:34 PM PDT 24
Peak memory 238364 kb
Host smart-df70247b-62ac-4746-a461-bf9cc865beed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644272606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1644272606
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3002253990
Short name T249
Test name
Test status
Simulation time 2448642487 ps
CPU time 19.48 seconds
Started Jul 11 04:28:19 PM PDT 24
Finished Jul 11 04:28:40 PM PDT 24
Peak memory 216420 kb
Host smart-1806b48c-3680-457d-9bcc-9274edc094bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002253990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3002253990
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3590376594
Short name T350
Test name
Test status
Simulation time 52663484596 ps
CPU time 124.5 seconds
Started Jul 11 04:28:12 PM PDT 24
Finished Jul 11 04:30:17 PM PDT 24
Peak memory 220944 kb
Host smart-ee426571-e437-44ff-b8bf-e25305fc0826
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590376594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3590376594
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1315746823
Short name T224
Test name
Test status
Simulation time 3673990061 ps
CPU time 19.22 seconds
Started Jul 11 04:28:30 PM PDT 24
Finished Jul 11 04:28:51 PM PDT 24
Peak memory 217100 kb
Host smart-188881c1-46f8-4c8d-ae9d-b708ffed279e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315746823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1315746823
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1577915609
Short name T310
Test name
Test status
Simulation time 2316963141 ps
CPU time 163.1 seconds
Started Jul 11 04:28:25 PM PDT 24
Finished Jul 11 04:31:10 PM PDT 24
Peak memory 238248 kb
Host smart-5b1aa0d2-1158-4f61-9d54-698dd784e889
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577915609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1577915609
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3849790084
Short name T265
Test name
Test status
Simulation time 2133738123 ps
CPU time 31.77 seconds
Started Jul 11 04:29:31 PM PDT 24
Finished Jul 11 04:30:03 PM PDT 24
Peak memory 219216 kb
Host smart-ffd4c12e-6ddd-4d81-a789-e519d41aeee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849790084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3849790084
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1267749001
Short name T66
Test name
Test status
Simulation time 6152763652 ps
CPU time 19.26 seconds
Started Jul 11 04:28:54 PM PDT 24
Finished Jul 11 04:29:15 PM PDT 24
Peak memory 211928 kb
Host smart-e95f80f2-5569-4fcd-b8d8-4c9d23f69fec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1267749001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1267749001
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.337478138
Short name T29
Test name
Test status
Simulation time 4019081605 ps
CPU time 138.09 seconds
Started Jul 11 04:28:26 PM PDT 24
Finished Jul 11 04:30:51 PM PDT 24
Peak memory 238264 kb
Host smart-9af45972-49f3-4eda-889e-07482f52d80a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337478138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.337478138
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1197862405
Short name T182
Test name
Test status
Simulation time 2518316297 ps
CPU time 28.8 seconds
Started Jul 11 04:28:11 PM PDT 24
Finished Jul 11 04:28:41 PM PDT 24
Peak memory 216564 kb
Host smart-78a2e781-1bb6-4ab7-92de-4fb79d0ba130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197862405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1197862405
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.800935008
Short name T251
Test name
Test status
Simulation time 923741522 ps
CPU time 56.6 seconds
Started Jul 11 04:28:23 PM PDT 24
Finished Jul 11 04:29:22 PM PDT 24
Peak memory 219188 kb
Host smart-2f9bd3c2-af17-4a10-9249-dc7e52ef23f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800935008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.800935008
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1600004291
Short name T270
Test name
Test status
Simulation time 2159857847 ps
CPU time 11 seconds
Started Jul 11 04:28:33 PM PDT 24
Finished Jul 11 04:28:46 PM PDT 24
Peak memory 216972 kb
Host smart-31d3ecba-0c86-4217-a91b-fc8382e9aa12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600004291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1600004291
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2793016759
Short name T188
Test name
Test status
Simulation time 108092329201 ps
CPU time 338 seconds
Started Jul 11 04:29:06 PM PDT 24
Finished Jul 11 04:34:47 PM PDT 24
Peak memory 237828 kb
Host smart-9237a226-6a7d-43ba-b5a4-c8e6a00bd6b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793016759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2793016759
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.4290394208
Short name T184
Test name
Test status
Simulation time 29086619097 ps
CPU time 35.11 seconds
Started Jul 11 04:28:40 PM PDT 24
Finished Jul 11 04:29:16 PM PDT 24
Peak memory 219236 kb
Host smart-0739d332-a091-48df-ae28-69a11b1a554c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290394208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.4290394208
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3923254249
Short name T232
Test name
Test status
Simulation time 6021599496 ps
CPU time 26.16 seconds
Started Jul 11 04:29:21 PM PDT 24
Finished Jul 11 04:29:50 PM PDT 24
Peak memory 217796 kb
Host smart-82731cfc-82a4-4a22-814f-57c2de69035f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3923254249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3923254249
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1881105617
Short name T314
Test name
Test status
Simulation time 354062551 ps
CPU time 20.01 seconds
Started Jul 11 04:28:55 PM PDT 24
Finished Jul 11 04:29:17 PM PDT 24
Peak memory 216124 kb
Host smart-dc8432e9-8ed9-493f-adc4-54c8f4d76ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881105617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1881105617
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1572449741
Short name T35
Test name
Test status
Simulation time 28053538078 ps
CPU time 64.16 seconds
Started Jul 11 04:28:34 PM PDT 24
Finished Jul 11 04:29:41 PM PDT 24
Peak memory 219980 kb
Host smart-93f369fc-6bf8-4159-ac56-794a11d551ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572449741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1572449741
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3145220129
Short name T231
Test name
Test status
Simulation time 1885871130 ps
CPU time 19.97 seconds
Started Jul 11 04:28:27 PM PDT 24
Finished Jul 11 04:28:50 PM PDT 24
Peak memory 217116 kb
Host smart-d3d44370-22ff-45e4-955d-2a76bd2cb9c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145220129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3145220129
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3061756975
Short name T257
Test name
Test status
Simulation time 47320780205 ps
CPU time 234.92 seconds
Started Jul 11 04:28:25 PM PDT 24
Finished Jul 11 04:32:22 PM PDT 24
Peak memory 225308 kb
Host smart-53a91858-afad-48f0-bf1d-cd01780b4209
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061756975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3061756975
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3636955028
Short name T33
Test name
Test status
Simulation time 30824060779 ps
CPU time 63.15 seconds
Started Jul 11 04:29:12 PM PDT 24
Finished Jul 11 04:30:18 PM PDT 24
Peak memory 219212 kb
Host smart-8ad6a5c3-d182-47b7-adf3-816b8135c435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636955028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3636955028
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1401595355
Short name T323
Test name
Test status
Simulation time 700725628 ps
CPU time 10.66 seconds
Started Jul 11 04:28:50 PM PDT 24
Finished Jul 11 04:29:02 PM PDT 24
Peak memory 219208 kb
Host smart-c08d9c20-6372-432c-aed5-98a927853880
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1401595355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1401595355
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.279939989
Short name T142
Test name
Test status
Simulation time 18286401950 ps
CPU time 63.16 seconds
Started Jul 11 04:29:09 PM PDT 24
Finished Jul 11 04:30:15 PM PDT 24
Peak memory 217180 kb
Host smart-bea3dade-39cf-41f9-a3de-7c457e92d81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279939989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.279939989
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.239878396
Short name T291
Test name
Test status
Simulation time 6161633859 ps
CPU time 17.26 seconds
Started Jul 11 04:28:30 PM PDT 24
Finished Jul 11 04:28:49 PM PDT 24
Peak memory 217460 kb
Host smart-4b7db1e5-5585-4528-8e3d-e883ef4607b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239878396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.239878396
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3092142729
Short name T280
Test name
Test status
Simulation time 299089058923 ps
CPU time 832.62 seconds
Started Jul 11 04:28:37 PM PDT 24
Finished Jul 11 04:42:31 PM PDT 24
Peak memory 234224 kb
Host smart-cb1c5b14-a095-4985-a584-49f174d31507
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092142729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3092142729
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.4137822306
Short name T355
Test name
Test status
Simulation time 17065848189 ps
CPU time 44.88 seconds
Started Jul 11 04:28:59 PM PDT 24
Finished Jul 11 04:29:46 PM PDT 24
Peak memory 219188 kb
Host smart-3d5232b4-4450-4740-a50d-545fdfdcac15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137822306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.4137822306
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2892108960
Short name T207
Test name
Test status
Simulation time 14842466900 ps
CPU time 29.84 seconds
Started Jul 11 04:28:25 PM PDT 24
Finished Jul 11 04:28:57 PM PDT 24
Peak memory 217628 kb
Host smart-3fc58374-0e00-4005-80e2-d7e36d317d1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2892108960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2892108960
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1895839510
Short name T301
Test name
Test status
Simulation time 35070601923 ps
CPU time 81.29 seconds
Started Jul 11 04:28:46 PM PDT 24
Finished Jul 11 04:30:09 PM PDT 24
Peak memory 217052 kb
Host smart-0fd79bb9-03c4-4b77-9849-250dd243b3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895839510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1895839510
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3230239901
Short name T356
Test name
Test status
Simulation time 62920003924 ps
CPU time 127.39 seconds
Started Jul 11 04:28:53 PM PDT 24
Finished Jul 11 04:31:02 PM PDT 24
Peak memory 220112 kb
Host smart-60bb95cf-0c03-44b0-97be-cc1ca4a5d708
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230239901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3230239901
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.689458383
Short name T315
Test name
Test status
Simulation time 12227203277 ps
CPU time 25.94 seconds
Started Jul 11 04:28:55 PM PDT 24
Finished Jul 11 04:29:23 PM PDT 24
Peak memory 213168 kb
Host smart-e4ad2079-2ab2-46cf-a946-958e73212151
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689458383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.689458383
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3765947476
Short name T307
Test name
Test status
Simulation time 80767618678 ps
CPU time 314.59 seconds
Started Jul 11 04:28:29 PM PDT 24
Finished Jul 11 04:33:51 PM PDT 24
Peak memory 236672 kb
Host smart-ff8e2c17-a559-45fc-9030-305126822cbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765947476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3765947476
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2615656858
Short name T298
Test name
Test status
Simulation time 589904859 ps
CPU time 22.31 seconds
Started Jul 11 04:28:31 PM PDT 24
Finished Jul 11 04:28:55 PM PDT 24
Peak memory 219228 kb
Host smart-847224fb-ada7-4d29-9ca8-2ac9614c83d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615656858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2615656858
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3282907475
Short name T326
Test name
Test status
Simulation time 24640937470 ps
CPU time 23.76 seconds
Started Jul 11 04:28:45 PM PDT 24
Finished Jul 11 04:29:11 PM PDT 24
Peak memory 211776 kb
Host smart-e985ba1f-48a6-4a5c-9ae1-caaa2d5f2610
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3282907475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3282907475
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1224268429
Short name T192
Test name
Test status
Simulation time 36265130134 ps
CPU time 167.35 seconds
Started Jul 11 04:29:19 PM PDT 24
Finished Jul 11 04:32:09 PM PDT 24
Peak memory 222648 kb
Host smart-44019cf5-c71d-47a5-bec6-62993f6317db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224268429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1224268429
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2865053327
Short name T199
Test name
Test status
Simulation time 14305917264 ps
CPU time 29.22 seconds
Started Jul 11 04:28:34 PM PDT 24
Finished Jul 11 04:29:05 PM PDT 24
Peak memory 217476 kb
Host smart-3b6bda39-21a1-46d2-b62d-154762585cf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865053327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2865053327
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.949285058
Short name T194
Test name
Test status
Simulation time 2242100938 ps
CPU time 160.16 seconds
Started Jul 11 04:28:38 PM PDT 24
Finished Jul 11 04:31:20 PM PDT 24
Peak memory 229468 kb
Host smart-9451a573-51be-4ceb-9abe-04cd80aa0493
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949285058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.949285058
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1560850311
Short name T148
Test name
Test status
Simulation time 13108844079 ps
CPU time 39.17 seconds
Started Jul 11 04:29:10 PM PDT 24
Finished Jul 11 04:29:53 PM PDT 24
Peak memory 219288 kb
Host smart-a00146bb-3bcb-452e-952e-c7aed621c962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560850311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1560850311
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3471030651
Short name T175
Test name
Test status
Simulation time 8916420114 ps
CPU time 35.22 seconds
Started Jul 11 04:28:42 PM PDT 24
Finished Jul 11 04:29:19 PM PDT 24
Peak memory 219268 kb
Host smart-cc73af23-994a-4f8a-bdce-fd1aeaea03c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3471030651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3471030651
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.204370803
Short name T165
Test name
Test status
Simulation time 12272848379 ps
CPU time 51.44 seconds
Started Jul 11 04:29:09 PM PDT 24
Finished Jul 11 04:30:03 PM PDT 24
Peak memory 216136 kb
Host smart-6e031e69-2f0e-4dfd-8746-90228201bb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204370803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.204370803
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1815623700
Short name T290
Test name
Test status
Simulation time 190131078 ps
CPU time 8.4 seconds
Started Jul 11 04:28:41 PM PDT 24
Finished Jul 11 04:28:50 PM PDT 24
Peak memory 217040 kb
Host smart-3d3403fa-85bc-4292-a464-fe65a4102109
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815623700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1815623700
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1508123253
Short name T191
Test name
Test status
Simulation time 17543251273 ps
CPU time 334.21 seconds
Started Jul 11 04:28:49 PM PDT 24
Finished Jul 11 04:34:25 PM PDT 24
Peak memory 228320 kb
Host smart-be5dcdb5-85cf-4c39-94dc-6ee7c335126d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508123253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1508123253
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.162887747
Short name T152
Test name
Test status
Simulation time 15643811681 ps
CPU time 63.22 seconds
Started Jul 11 04:28:36 PM PDT 24
Finished Jul 11 04:29:41 PM PDT 24
Peak memory 219220 kb
Host smart-09cccaf4-d82d-4f0e-92a6-1cc7fd1022a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162887747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.162887747
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1304622046
Short name T236
Test name
Test status
Simulation time 3866396583 ps
CPU time 24.03 seconds
Started Jul 11 04:28:54 PM PDT 24
Finished Jul 11 04:29:19 PM PDT 24
Peak memory 211636 kb
Host smart-a7754a32-0092-49e2-abad-66d0267f79b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1304622046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1304622046
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3255045176
Short name T347
Test name
Test status
Simulation time 26233671940 ps
CPU time 80.93 seconds
Started Jul 11 04:28:36 PM PDT 24
Finished Jul 11 04:29:58 PM PDT 24
Peak memory 219608 kb
Host smart-38ad48cd-847a-4417-83e5-f282798e1caa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255045176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3255045176
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1838911757
Short name T14
Test name
Test status
Simulation time 135127659649 ps
CPU time 7061.22 seconds
Started Jul 11 04:28:32 PM PDT 24
Finished Jul 11 06:26:16 PM PDT 24
Peak memory 243984 kb
Host smart-bd9eb04d-6dcf-4fb1-88ee-3f204718847e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838911757 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.1838911757
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.4015469176
Short name T325
Test name
Test status
Simulation time 2495076058 ps
CPU time 11.95 seconds
Started Jul 11 04:28:51 PM PDT 24
Finished Jul 11 04:29:04 PM PDT 24
Peak memory 216968 kb
Host smart-ccfc044a-95cc-4e26-9541-996f92dc5674
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015469176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.4015469176
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2129672600
Short name T140
Test name
Test status
Simulation time 9602690264 ps
CPU time 149.38 seconds
Started Jul 11 04:28:34 PM PDT 24
Finished Jul 11 04:31:06 PM PDT 24
Peak memory 215720 kb
Host smart-708bb75b-0895-420b-b392-7d3b5d93a7eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129672600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2129672600
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3894601900
Short name T268
Test name
Test status
Simulation time 18739348358 ps
CPU time 43.33 seconds
Started Jul 11 04:29:13 PM PDT 24
Finished Jul 11 04:29:59 PM PDT 24
Peak memory 219012 kb
Host smart-c1c386a7-ea81-42ba-add0-d405b35c44f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894601900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3894601900
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3126548244
Short name T201
Test name
Test status
Simulation time 1488930898 ps
CPU time 13.85 seconds
Started Jul 11 04:29:12 PM PDT 24
Finished Jul 11 04:29:29 PM PDT 24
Peak memory 219200 kb
Host smart-6f2a6e52-f665-4eba-9fb5-80bdf7c36f1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3126548244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3126548244
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1882423008
Short name T303
Test name
Test status
Simulation time 18616379716 ps
CPU time 75.72 seconds
Started Jul 11 04:28:49 PM PDT 24
Finished Jul 11 04:30:06 PM PDT 24
Peak memory 218064 kb
Host smart-dc8f1e04-df20-4c2d-90b7-66e4cc27fc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882423008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1882423008
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2925784538
Short name T144
Test name
Test status
Simulation time 209109042 ps
CPU time 17.37 seconds
Started Jul 11 04:29:09 PM PDT 24
Finished Jul 11 04:29:30 PM PDT 24
Peak memory 219212 kb
Host smart-3e6b6009-7238-47a8-997b-bde3bc57f78b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925784538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2925784538
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3111916486
Short name T316
Test name
Test status
Simulation time 4269584564 ps
CPU time 33.07 seconds
Started Jul 11 04:29:17 PM PDT 24
Finished Jul 11 04:29:53 PM PDT 24
Peak memory 217076 kb
Host smart-33d67984-8d92-463c-b271-4aa1ea6680f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111916486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3111916486
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1197665762
Short name T255
Test name
Test status
Simulation time 204929675251 ps
CPU time 622.25 seconds
Started Jul 11 04:28:46 PM PDT 24
Finished Jul 11 04:39:10 PM PDT 24
Peak memory 239612 kb
Host smart-2cf57fe3-72ea-41a7-a641-31e3e220ca6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197665762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1197665762
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1627160623
Short name T138
Test name
Test status
Simulation time 358505041 ps
CPU time 10.47 seconds
Started Jul 11 04:28:39 PM PDT 24
Finished Jul 11 04:28:51 PM PDT 24
Peak memory 218472 kb
Host smart-7de7b217-0040-4683-b551-7c0d5e08366a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1627160623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1627160623
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2689519518
Short name T261
Test name
Test status
Simulation time 18868840952 ps
CPU time 45.61 seconds
Started Jul 11 04:28:33 PM PDT 24
Finished Jul 11 04:29:21 PM PDT 24
Peak memory 216760 kb
Host smart-341946e9-abf8-495a-89f1-abd32556a5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689519518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2689519518
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.4188433958
Short name T38
Test name
Test status
Simulation time 8720234362 ps
CPU time 37.53 seconds
Started Jul 11 04:29:11 PM PDT 24
Finished Jul 11 04:29:51 PM PDT 24
Peak memory 219132 kb
Host smart-b8309c36-3629-4952-b46a-c79c70c40c85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188433958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.4188433958
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1568398541
Short name T342
Test name
Test status
Simulation time 2505441486 ps
CPU time 21.76 seconds
Started Jul 11 04:28:52 PM PDT 24
Finished Jul 11 04:29:15 PM PDT 24
Peak memory 216628 kb
Host smart-23a92f1e-1189-452c-9dd8-f029088faf9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568398541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1568398541
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3486558027
Short name T40
Test name
Test status
Simulation time 286938606649 ps
CPU time 825.31 seconds
Started Jul 11 04:29:25 PM PDT 24
Finished Jul 11 04:43:13 PM PDT 24
Peak memory 218928 kb
Host smart-958612fb-9ee0-4675-adb6-e7527ad315b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486558027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3486558027
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.894817048
Short name T46
Test name
Test status
Simulation time 6877475825 ps
CPU time 56.78 seconds
Started Jul 11 04:28:49 PM PDT 24
Finished Jul 11 04:29:48 PM PDT 24
Peak memory 219268 kb
Host smart-72be2765-1ee5-4d75-be36-54fb88e52e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894817048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.894817048
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.5010840
Short name T267
Test name
Test status
Simulation time 53845013323 ps
CPU time 27.27 seconds
Started Jul 11 04:29:19 PM PDT 24
Finished Jul 11 04:29:54 PM PDT 24
Peak memory 217568 kb
Host smart-dd00466d-b60f-4d90-8878-5326046a8e46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=5010840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.5010840
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1973842792
Short name T212
Test name
Test status
Simulation time 57906346008 ps
CPU time 68.48 seconds
Started Jul 11 04:29:06 PM PDT 24
Finished Jul 11 04:30:17 PM PDT 24
Peak memory 217908 kb
Host smart-48a2fa1f-7208-4b13-a413-54f92f7896c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973842792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1973842792
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2228452564
Short name T324
Test name
Test status
Simulation time 12592689134 ps
CPU time 86.24 seconds
Started Jul 11 04:29:08 PM PDT 24
Finished Jul 11 04:30:37 PM PDT 24
Peak memory 219240 kb
Host smart-e593c595-962c-4a73-9ff1-5ff403b984de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228452564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2228452564
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1858288274
Short name T294
Test name
Test status
Simulation time 4013798852 ps
CPU time 30.29 seconds
Started Jul 11 04:29:24 PM PDT 24
Finished Jul 11 04:29:57 PM PDT 24
Peak memory 217036 kb
Host smart-a5b3ddfd-5d1a-4cc9-a7b0-9f642194f0dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858288274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1858288274
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2590572123
Short name T331
Test name
Test status
Simulation time 256960397412 ps
CPU time 645.99 seconds
Started Jul 11 04:30:03 PM PDT 24
Finished Jul 11 04:40:58 PM PDT 24
Peak memory 239500 kb
Host smart-3ba448ac-cc41-427a-8eb1-05614587d84f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590572123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2590572123
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2823780499
Short name T346
Test name
Test status
Simulation time 10865570070 ps
CPU time 51.75 seconds
Started Jul 11 04:28:54 PM PDT 24
Finished Jul 11 04:29:48 PM PDT 24
Peak memory 219100 kb
Host smart-0b8af214-4348-45f6-aa33-34036a347be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823780499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2823780499
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.944043215
Short name T243
Test name
Test status
Simulation time 4441398489 ps
CPU time 34.52 seconds
Started Jul 11 04:29:09 PM PDT 24
Finished Jul 11 04:29:46 PM PDT 24
Peak memory 219252 kb
Host smart-bad12439-6123-4def-aee2-565bc6a4e748
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=944043215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.944043215
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3568339231
Short name T276
Test name
Test status
Simulation time 2212864816 ps
CPU time 22.62 seconds
Started Jul 11 04:29:01 PM PDT 24
Finished Jul 11 04:29:25 PM PDT 24
Peak memory 215792 kb
Host smart-39112d2f-a9bf-4f58-ac92-0891723cc23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568339231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3568339231
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2897385733
Short name T205
Test name
Test status
Simulation time 414462047 ps
CPU time 10.83 seconds
Started Jul 11 04:28:32 PM PDT 24
Finished Jul 11 04:28:45 PM PDT 24
Peak memory 218476 kb
Host smart-cd4d1d4e-65a2-4cea-8e9f-7b3f4be0abab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897385733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2897385733
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3405889814
Short name T250
Test name
Test status
Simulation time 9539929840 ps
CPU time 23.86 seconds
Started Jul 11 04:28:29 PM PDT 24
Finished Jul 11 04:28:55 PM PDT 24
Peak memory 217388 kb
Host smart-f2b13bcf-dca9-4216-a8e6-8557e1081ea0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405889814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3405889814
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2924791376
Short name T297
Test name
Test status
Simulation time 100760147945 ps
CPU time 545.05 seconds
Started Jul 11 04:28:23 PM PDT 24
Finished Jul 11 04:37:30 PM PDT 24
Peak memory 214800 kb
Host smart-18c8d102-30a5-4d76-bd3d-02aa2b47b070
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924791376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2924791376
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.4225128796
Short name T248
Test name
Test status
Simulation time 1500260159 ps
CPU time 19.46 seconds
Started Jul 11 04:28:31 PM PDT 24
Finished Jul 11 04:28:52 PM PDT 24
Peak memory 219236 kb
Host smart-3ee04f97-315a-409e-b361-cbfacab902ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225128796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.4225128796
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.4237588042
Short name T361
Test name
Test status
Simulation time 6883068479 ps
CPU time 20.94 seconds
Started Jul 11 04:28:23 PM PDT 24
Finished Jul 11 04:28:47 PM PDT 24
Peak memory 219260 kb
Host smart-2ae22e3e-ff7a-43ce-b4cc-8b0fe8e95cfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4237588042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.4237588042
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1971274877
Short name T187
Test name
Test status
Simulation time 4875839498 ps
CPU time 53.25 seconds
Started Jul 11 04:29:05 PM PDT 24
Finished Jul 11 04:30:01 PM PDT 24
Peak memory 216124 kb
Host smart-86a6b530-0239-4bf4-aa7c-132839eb0c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971274877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1971274877
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1650664146
Short name T329
Test name
Test status
Simulation time 396032105 ps
CPU time 25.45 seconds
Started Jul 11 04:29:10 PM PDT 24
Finished Jul 11 04:29:39 PM PDT 24
Peak memory 219196 kb
Host smart-5f2edbd4-8b2f-4072-8ed3-d564060c409f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650664146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1650664146
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.644824354
Short name T27
Test name
Test status
Simulation time 2194757305 ps
CPU time 21.33 seconds
Started Jul 11 04:28:39 PM PDT 24
Finished Jul 11 04:29:01 PM PDT 24
Peak memory 217088 kb
Host smart-3c828d82-b46f-463e-baad-fa1c31df0f69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644824354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.644824354
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1598911955
Short name T320
Test name
Test status
Simulation time 14155362992 ps
CPU time 270.59 seconds
Started Jul 11 04:28:54 PM PDT 24
Finished Jul 11 04:33:26 PM PDT 24
Peak memory 237960 kb
Host smart-89ba6002-5687-4abe-9464-c1e5ea29b998
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598911955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1598911955
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.4277050781
Short name T245
Test name
Test status
Simulation time 4595053513 ps
CPU time 34.18 seconds
Started Jul 11 04:28:52 PM PDT 24
Finished Jul 11 04:29:28 PM PDT 24
Peak memory 219264 kb
Host smart-6b52bb2b-8c9f-4bd5-8ff4-fdcd4c1b6dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277050781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.4277050781
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1133096421
Short name T143
Test name
Test status
Simulation time 962177665 ps
CPU time 16.41 seconds
Started Jul 11 04:29:03 PM PDT 24
Finished Jul 11 04:29:21 PM PDT 24
Peak memory 219180 kb
Host smart-57fc460c-0f4a-4545-a731-329b92402869
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1133096421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1133096421
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.665193843
Short name T31
Test name
Test status
Simulation time 747958529 ps
CPU time 27.7 seconds
Started Jul 11 04:28:31 PM PDT 24
Finished Jul 11 04:29:01 PM PDT 24
Peak memory 219184 kb
Host smart-2940dec5-11bc-4e6d-b43d-0ffcc577d483
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665193843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.665193843
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1265392194
Short name T176
Test name
Test status
Simulation time 2563615003 ps
CPU time 22.54 seconds
Started Jul 11 04:28:54 PM PDT 24
Finished Jul 11 04:29:18 PM PDT 24
Peak memory 217088 kb
Host smart-c4f41e0d-5bb1-4d05-af59-335ae5bfbcd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265392194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1265392194
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1705975315
Short name T313
Test name
Test status
Simulation time 498809016685 ps
CPU time 416.19 seconds
Started Jul 11 04:28:53 PM PDT 24
Finished Jul 11 04:35:51 PM PDT 24
Peak memory 229668 kb
Host smart-cc2b3bba-0e0a-4e57-861e-346fcb32f9c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705975315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1705975315
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1360400610
Short name T210
Test name
Test status
Simulation time 3296414319 ps
CPU time 19.06 seconds
Started Jul 11 04:28:35 PM PDT 24
Finished Jul 11 04:28:56 PM PDT 24
Peak memory 219264 kb
Host smart-cedfd316-519c-413b-9522-8f3f1bf305cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360400610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1360400610
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.625183542
Short name T281
Test name
Test status
Simulation time 3691008775 ps
CPU time 30.48 seconds
Started Jul 11 04:29:03 PM PDT 24
Finished Jul 11 04:29:41 PM PDT 24
Peak memory 219228 kb
Host smart-be912e84-24cd-44eb-a07b-2c280cde02ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=625183542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.625183542
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.356626832
Short name T219
Test name
Test status
Simulation time 7528348305 ps
CPU time 60.25 seconds
Started Jul 11 04:28:59 PM PDT 24
Finished Jul 11 04:30:02 PM PDT 24
Peak memory 216776 kb
Host smart-9714efb1-6f51-41ae-a529-450ced10aa5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356626832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.356626832
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3811308129
Short name T181
Test name
Test status
Simulation time 5565451522 ps
CPU time 56.63 seconds
Started Jul 11 04:28:54 PM PDT 24
Finished Jul 11 04:29:52 PM PDT 24
Peak memory 217968 kb
Host smart-8364b59c-3db7-48c2-aaf5-b09c918f2907
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811308129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3811308129
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1635284458
Short name T177
Test name
Test status
Simulation time 1856183775 ps
CPU time 18.85 seconds
Started Jul 11 04:29:09 PM PDT 24
Finished Jul 11 04:29:31 PM PDT 24
Peak memory 217064 kb
Host smart-3ead9b17-76ab-4b20-8dc2-5d339bf4c9cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635284458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1635284458
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2984239755
Short name T23
Test name
Test status
Simulation time 27894923247 ps
CPU time 223.12 seconds
Started Jul 11 04:28:58 PM PDT 24
Finished Jul 11 04:32:44 PM PDT 24
Peak memory 215700 kb
Host smart-1babca26-54c4-4e53-b155-a959e0b84d25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984239755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2984239755
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.902506763
Short name T11
Test name
Test status
Simulation time 34698823746 ps
CPU time 56.28 seconds
Started Jul 11 04:28:38 PM PDT 24
Finished Jul 11 04:29:36 PM PDT 24
Peak memory 219176 kb
Host smart-c0e5d200-d061-4544-9b4d-9d0b0c1aa689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902506763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.902506763
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2076352008
Short name T132
Test name
Test status
Simulation time 368634280 ps
CPU time 10.58 seconds
Started Jul 11 04:29:05 PM PDT 24
Finished Jul 11 04:29:19 PM PDT 24
Peak memory 219236 kb
Host smart-6032ceef-40b2-400a-92fb-78e1518339fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2076352008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2076352008
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2925870293
Short name T293
Test name
Test status
Simulation time 50701878169 ps
CPU time 60 seconds
Started Jul 11 04:28:39 PM PDT 24
Finished Jul 11 04:29:40 PM PDT 24
Peak memory 217012 kb
Host smart-ca7d4c71-e322-4e1e-a35e-e3fd9042ff04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925870293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2925870293
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2779634122
Short name T81
Test name
Test status
Simulation time 12219918241 ps
CPU time 108.76 seconds
Started Jul 11 04:28:57 PM PDT 24
Finished Jul 11 04:30:49 PM PDT 24
Peak memory 219784 kb
Host smart-1ace003e-9ff1-4d19-b70f-eac11ffe1533
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779634122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2779634122
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.976747480
Short name T42
Test name
Test status
Simulation time 3204278345 ps
CPU time 26.66 seconds
Started Jul 11 04:29:00 PM PDT 24
Finished Jul 11 04:29:29 PM PDT 24
Peak memory 217368 kb
Host smart-4819d96b-5158-4d74-b9c0-d5b0c993fe19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976747480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.976747480
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3476674631
Short name T345
Test name
Test status
Simulation time 377252159340 ps
CPU time 992.65 seconds
Started Jul 11 04:28:51 PM PDT 24
Finished Jul 11 04:45:25 PM PDT 24
Peak memory 216076 kb
Host smart-0795af1a-170f-4a34-a10e-52c9f33265a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476674631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3476674631
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2789886368
Short name T170
Test name
Test status
Simulation time 4676593194 ps
CPU time 38.53 seconds
Started Jul 11 04:29:01 PM PDT 24
Finished Jul 11 04:29:41 PM PDT 24
Peak memory 219232 kb
Host smart-dec8233d-0cf2-4b24-b919-f9bdc7202153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789886368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2789886368
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2567504496
Short name T223
Test name
Test status
Simulation time 693087673 ps
CPU time 9.9 seconds
Started Jul 11 04:28:34 PM PDT 24
Finished Jul 11 04:28:46 PM PDT 24
Peak memory 219224 kb
Host smart-0efedba5-3293-4a60-aee5-93d5a41ebad6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2567504496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2567504496
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1045884012
Short name T321
Test name
Test status
Simulation time 2437461481 ps
CPU time 19.16 seconds
Started Jul 11 04:28:49 PM PDT 24
Finished Jul 11 04:29:10 PM PDT 24
Peak memory 216572 kb
Host smart-428200b2-b172-4ee4-a8e3-e96640fbcec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045884012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1045884012
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3466091713
Short name T221
Test name
Test status
Simulation time 26320659327 ps
CPU time 146.01 seconds
Started Jul 11 04:29:05 PM PDT 24
Finished Jul 11 04:31:34 PM PDT 24
Peak memory 222856 kb
Host smart-1d9f39db-0672-4e7c-991f-91f2e28aa9fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466091713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3466091713
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1315093636
Short name T154
Test name
Test status
Simulation time 10350881992 ps
CPU time 18.35 seconds
Started Jul 11 04:29:19 PM PDT 24
Finished Jul 11 04:29:40 PM PDT 24
Peak memory 217524 kb
Host smart-f728c28d-f6ec-48b5-b57c-eb78b28df38a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315093636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1315093636
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3510908135
Short name T334
Test name
Test status
Simulation time 30618958937 ps
CPU time 283.85 seconds
Started Jul 11 04:29:06 PM PDT 24
Finished Jul 11 04:33:53 PM PDT 24
Peak memory 224596 kb
Host smart-29a31631-3b15-4b4f-80e5-3286da2b0563
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510908135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3510908135
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2584121516
Short name T282
Test name
Test status
Simulation time 69830250423 ps
CPU time 67.31 seconds
Started Jul 11 04:29:10 PM PDT 24
Finished Jul 11 04:30:21 PM PDT 24
Peak memory 219592 kb
Host smart-f74566bc-d1b3-47e0-b5e2-04f3c5236c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584121516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2584121516
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2966835339
Short name T227
Test name
Test status
Simulation time 3234113645 ps
CPU time 28.54 seconds
Started Jul 11 04:28:54 PM PDT 24
Finished Jul 11 04:29:25 PM PDT 24
Peak memory 211252 kb
Host smart-7a90c02f-7152-4761-a666-1ad64cce3a4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2966835339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2966835339
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3719419676
Short name T155
Test name
Test status
Simulation time 1369636121 ps
CPU time 19.46 seconds
Started Jul 11 04:29:15 PM PDT 24
Finished Jul 11 04:29:37 PM PDT 24
Peak memory 215700 kb
Host smart-4318c132-b584-420a-aa1f-58e092034340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719419676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3719419676
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3905062675
Short name T339
Test name
Test status
Simulation time 21310256247 ps
CPU time 104.85 seconds
Started Jul 11 04:29:05 PM PDT 24
Finished Jul 11 04:30:53 PM PDT 24
Peak memory 219184 kb
Host smart-256c4be0-b595-468c-a64a-25892df40b00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905062675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3905062675
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1798510352
Short name T220
Test name
Test status
Simulation time 1564064754 ps
CPU time 12.93 seconds
Started Jul 11 04:29:11 PM PDT 24
Finished Jul 11 04:29:27 PM PDT 24
Peak memory 217056 kb
Host smart-10570bcf-2dc2-44dc-9c84-fff5c5cdc1da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798510352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1798510352
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3412825586
Short name T206
Test name
Test status
Simulation time 69586072524 ps
CPU time 755.67 seconds
Started Jul 11 04:29:08 PM PDT 24
Finished Jul 11 04:41:47 PM PDT 24
Peak memory 235576 kb
Host smart-ded713b6-70a0-469d-87df-65d02a4e95c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412825586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3412825586
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2628269174
Short name T289
Test name
Test status
Simulation time 3509394320 ps
CPU time 40.12 seconds
Started Jul 11 04:29:01 PM PDT 24
Finished Jul 11 04:29:43 PM PDT 24
Peak memory 218780 kb
Host smart-84db9977-85fa-4e19-a6f9-6536dd17b0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628269174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2628269174
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2642095642
Short name T195
Test name
Test status
Simulation time 2227882612 ps
CPU time 23.79 seconds
Started Jul 11 04:28:47 PM PDT 24
Finished Jul 11 04:29:13 PM PDT 24
Peak memory 211612 kb
Host smart-700131b7-2671-4e80-8e2d-84d2301f6e9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2642095642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2642095642
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1480875738
Short name T202
Test name
Test status
Simulation time 26718983675 ps
CPU time 33.38 seconds
Started Jul 11 04:28:58 PM PDT 24
Finished Jul 11 04:29:34 PM PDT 24
Peak memory 216688 kb
Host smart-35700186-c04d-4a1d-851c-c05c28731605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480875738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1480875738
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.972942530
Short name T338
Test name
Test status
Simulation time 69573006048 ps
CPU time 143.61 seconds
Started Jul 11 04:29:15 PM PDT 24
Finished Jul 11 04:31:41 PM PDT 24
Peak memory 219752 kb
Host smart-f55b356c-7273-411c-8dde-25dafcfdbc1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972942530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.972942530
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2536732255
Short name T336
Test name
Test status
Simulation time 167673581 ps
CPU time 8.22 seconds
Started Jul 11 04:29:06 PM PDT 24
Finished Jul 11 04:29:17 PM PDT 24
Peak memory 217108 kb
Host smart-9e1f4477-43b8-45a4-8dca-34061c0cd980
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536732255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2536732255
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3525960372
Short name T180
Test name
Test status
Simulation time 1810067708 ps
CPU time 150.53 seconds
Started Jul 11 04:28:58 PM PDT 24
Finished Jul 11 04:31:31 PM PDT 24
Peak memory 236908 kb
Host smart-8b326d6f-62ce-4fd3-a5c9-6eea6bcc250f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525960372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3525960372
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.790014354
Short name T358
Test name
Test status
Simulation time 7546028590 ps
CPU time 36.63 seconds
Started Jul 11 04:28:58 PM PDT 24
Finished Jul 11 04:29:37 PM PDT 24
Peak memory 219280 kb
Host smart-12cdfcb0-8592-4ee8-922d-5151e503c65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790014354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.790014354
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3442887567
Short name T322
Test name
Test status
Simulation time 53639158775 ps
CPU time 34.28 seconds
Started Jul 11 04:29:19 PM PDT 24
Finished Jul 11 04:29:56 PM PDT 24
Peak memory 219268 kb
Host smart-2d36bb6c-a576-46b3-9f91-cb9c1484747b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3442887567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3442887567
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1978075212
Short name T158
Test name
Test status
Simulation time 2673351805 ps
CPU time 19.43 seconds
Started Jul 11 04:28:54 PM PDT 24
Finished Jul 11 04:29:21 PM PDT 24
Peak memory 215600 kb
Host smart-5a2df20e-930d-4f3e-bdae-211472d4e0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978075212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1978075212
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1404840637
Short name T209
Test name
Test status
Simulation time 87158523644 ps
CPU time 186.12 seconds
Started Jul 11 04:29:08 PM PDT 24
Finished Jul 11 04:32:17 PM PDT 24
Peak memory 219428 kb
Host smart-5c9a9d14-ace2-4e48-8b31-a89279c0d9fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404840637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1404840637
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.582358995
Short name T308
Test name
Test status
Simulation time 167569624 ps
CPU time 8.38 seconds
Started Jul 11 04:29:18 PM PDT 24
Finished Jul 11 04:29:29 PM PDT 24
Peak memory 218092 kb
Host smart-e57aca3e-ac83-47de-b08f-4c7580830611
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582358995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.582358995
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.684234280
Short name T333
Test name
Test status
Simulation time 34235860806 ps
CPU time 355.03 seconds
Started Jul 11 04:29:15 PM PDT 24
Finished Jul 11 04:35:14 PM PDT 24
Peak memory 237652 kb
Host smart-d9f13a4f-1eff-4360-8a53-c73cab875d86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684234280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.684234280
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1208354165
Short name T197
Test name
Test status
Simulation time 5248473819 ps
CPU time 50.79 seconds
Started Jul 11 04:29:16 PM PDT 24
Finished Jul 11 04:30:10 PM PDT 24
Peak memory 219296 kb
Host smart-dc2f4568-ca63-4b96-99e2-c4d32283969f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208354165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1208354165
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3669195456
Short name T1
Test name
Test status
Simulation time 3149144249 ps
CPU time 27.82 seconds
Started Jul 11 04:29:08 PM PDT 24
Finished Jul 11 04:29:38 PM PDT 24
Peak memory 211336 kb
Host smart-c3924753-a85f-41fa-95bb-27b7454493e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3669195456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3669195456
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3363756473
Short name T77
Test name
Test status
Simulation time 36662161359 ps
CPU time 80.38 seconds
Started Jul 11 04:29:06 PM PDT 24
Finished Jul 11 04:30:30 PM PDT 24
Peak memory 216436 kb
Host smart-1e6c0bba-cfb1-423d-9808-6b033c658df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363756473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3363756473
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3580111650
Short name T186
Test name
Test status
Simulation time 714483489 ps
CPU time 16.46 seconds
Started Jul 11 04:29:15 PM PDT 24
Finished Jul 11 04:29:35 PM PDT 24
Peak memory 214636 kb
Host smart-1b6782fb-3226-4d34-bf92-5cd57b6cab3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580111650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3580111650
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.4121890036
Short name T352
Test name
Test status
Simulation time 1808382458 ps
CPU time 19.3 seconds
Started Jul 11 04:29:17 PM PDT 24
Finished Jul 11 04:29:39 PM PDT 24
Peak memory 217008 kb
Host smart-0843cc63-6441-437a-aeda-021df396123c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121890036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.4121890036
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.654257598
Short name T139
Test name
Test status
Simulation time 3595561414 ps
CPU time 240.74 seconds
Started Jul 11 04:29:04 PM PDT 24
Finished Jul 11 04:33:06 PM PDT 24
Peak memory 227220 kb
Host smart-e17e0d84-ba3d-477e-a000-879805455616
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654257598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.654257598
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2475390814
Short name T283
Test name
Test status
Simulation time 10805689212 ps
CPU time 40.41 seconds
Started Jul 11 04:28:55 PM PDT 24
Finished Jul 11 04:29:38 PM PDT 24
Peak memory 219248 kb
Host smart-dcc228eb-efa1-4d71-ac4d-0192c7af5283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475390814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2475390814
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.138599876
Short name T133
Test name
Test status
Simulation time 3532340350 ps
CPU time 29.42 seconds
Started Jul 11 04:29:08 PM PDT 24
Finished Jul 11 04:29:40 PM PDT 24
Peak memory 219236 kb
Host smart-f11f37aa-99c0-406c-8bed-f76fd7b07536
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=138599876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.138599876
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3051917031
Short name T318
Test name
Test status
Simulation time 1750207485 ps
CPU time 32.09 seconds
Started Jul 11 04:29:01 PM PDT 24
Finished Jul 11 04:29:35 PM PDT 24
Peak memory 216492 kb
Host smart-6979b91e-28c8-43b3-a98c-106d640bf714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051917031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3051917031
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3724070040
Short name T67
Test name
Test status
Simulation time 361566436 ps
CPU time 27.26 seconds
Started Jul 11 04:29:13 PM PDT 24
Finished Jul 11 04:29:43 PM PDT 24
Peak memory 219168 kb
Host smart-0138d2fe-bd32-4b95-8273-0f77ed635726
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724070040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3724070040
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1346974112
Short name T174
Test name
Test status
Simulation time 45342585237 ps
CPU time 307.36 seconds
Started Jul 11 04:29:07 PM PDT 24
Finished Jul 11 04:34:17 PM PDT 24
Peak memory 233816 kb
Host smart-2c1966d0-4904-4bf7-af0c-747228719768
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346974112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1346974112
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2861656887
Short name T357
Test name
Test status
Simulation time 1532227444 ps
CPU time 18.9 seconds
Started Jul 11 04:29:09 PM PDT 24
Finished Jul 11 04:29:31 PM PDT 24
Peak memory 219132 kb
Host smart-13db3f80-ac91-44a8-9748-eb9722f63c16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2861656887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2861656887
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2571205213
Short name T344
Test name
Test status
Simulation time 14186726300 ps
CPU time 33.58 seconds
Started Jul 11 04:29:09 PM PDT 24
Finished Jul 11 04:29:46 PM PDT 24
Peak memory 216740 kb
Host smart-3e54f249-e0c0-4a1b-b6e8-7fecbeb7f432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571205213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2571205213
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3919274342
Short name T19
Test name
Test status
Simulation time 21834017231 ps
CPU time 63.76 seconds
Started Jul 11 04:29:21 PM PDT 24
Finished Jul 11 04:30:27 PM PDT 24
Peak memory 220860 kb
Host smart-588a5c21-f083-43bc-9154-d36ee55ec94a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919274342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3919274342
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.578138007
Short name T359
Test name
Test status
Simulation time 176223649 ps
CPU time 8.31 seconds
Started Jul 11 04:28:29 PM PDT 24
Finished Jul 11 04:28:39 PM PDT 24
Peak memory 217056 kb
Host smart-9ce1874e-683d-43e1-a34f-41c5bff074d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578138007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.578138007
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2523172403
Short name T162
Test name
Test status
Simulation time 19836438313 ps
CPU time 383.33 seconds
Started Jul 11 04:29:28 PM PDT 24
Finished Jul 11 04:35:53 PM PDT 24
Peak memory 230772 kb
Host smart-7d772750-8d45-4ea9-9b26-f1fb7d7e4aa4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523172403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2523172403
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.4288603331
Short name T211
Test name
Test status
Simulation time 2400730644 ps
CPU time 34.22 seconds
Started Jul 11 04:28:27 PM PDT 24
Finished Jul 11 04:29:04 PM PDT 24
Peak memory 219264 kb
Host smart-dbbde665-39d5-4207-a692-f35670d7fbe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288603331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.4288603331
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3292810340
Short name T146
Test name
Test status
Simulation time 724335387 ps
CPU time 10.12 seconds
Started Jul 11 04:28:34 PM PDT 24
Finished Jul 11 04:28:46 PM PDT 24
Peak memory 219204 kb
Host smart-0934dcce-c862-4f0c-b365-d7da574babfb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3292810340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3292810340
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.198948113
Short name T24
Test name
Test status
Simulation time 4552689378 ps
CPU time 226.09 seconds
Started Jul 11 04:28:27 PM PDT 24
Finished Jul 11 04:32:20 PM PDT 24
Peak memory 237884 kb
Host smart-b7808f89-3879-4a8c-ab52-257ff8f02bd7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198948113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.198948113
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3801336427
Short name T196
Test name
Test status
Simulation time 4925466821 ps
CPU time 48.96 seconds
Started Jul 11 04:28:25 PM PDT 24
Finished Jul 11 04:29:16 PM PDT 24
Peak memory 216068 kb
Host smart-90147895-1dd9-4b3b-9b5a-a6b1b317cb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801336427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3801336427
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.106573771
Short name T149
Test name
Test status
Simulation time 12101292088 ps
CPU time 92.15 seconds
Started Jul 11 04:29:16 PM PDT 24
Finished Jul 11 04:30:52 PM PDT 24
Peak memory 218496 kb
Host smart-3d40debb-0710-456e-9902-22c413b2e8fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106573771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.106573771
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3036755530
Short name T271
Test name
Test status
Simulation time 8699622031 ps
CPU time 22.96 seconds
Started Jul 11 04:29:06 PM PDT 24
Finished Jul 11 04:29:32 PM PDT 24
Peak memory 217456 kb
Host smart-89cb94a4-3361-46d0-a661-76deb4d0c23b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036755530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3036755530
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3955882976
Short name T253
Test name
Test status
Simulation time 303632727345 ps
CPU time 747.62 seconds
Started Jul 11 04:29:15 PM PDT 24
Finished Jul 11 04:41:51 PM PDT 24
Peak memory 218840 kb
Host smart-1dab5db8-ec47-449f-a059-450eaacd42f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955882976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3955882976
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1672622079
Short name T277
Test name
Test status
Simulation time 11167041457 ps
CPU time 37.12 seconds
Started Jul 11 04:29:15 PM PDT 24
Finished Jul 11 04:29:55 PM PDT 24
Peak memory 219232 kb
Host smart-ea61be8e-0a12-433b-8874-6dfe72a6e4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672622079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1672622079
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.177947966
Short name T18
Test name
Test status
Simulation time 7725874495 ps
CPU time 31.19 seconds
Started Jul 11 04:29:14 PM PDT 24
Finished Jul 11 04:29:48 PM PDT 24
Peak memory 211496 kb
Host smart-a790cfb5-9cb0-4091-af4c-d00b9b3708ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=177947966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.177947966
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1859064221
Short name T104
Test name
Test status
Simulation time 3434997700 ps
CPU time 19 seconds
Started Jul 11 04:29:08 PM PDT 24
Finished Jul 11 04:29:29 PM PDT 24
Peak memory 216656 kb
Host smart-6e3fd98f-fe52-4ac0-8548-cf6d2dba3c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859064221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1859064221
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2245260355
Short name T163
Test name
Test status
Simulation time 203423997 ps
CPU time 8.01 seconds
Started Jul 11 04:30:45 PM PDT 24
Finished Jul 11 04:30:56 PM PDT 24
Peak memory 217076 kb
Host smart-461a4c16-1a62-4899-ae79-d27e34fcee7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245260355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2245260355
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.981587230
Short name T327
Test name
Test status
Simulation time 387072662855 ps
CPU time 950.97 seconds
Started Jul 11 04:29:24 PM PDT 24
Finished Jul 11 04:45:18 PM PDT 24
Peak memory 234168 kb
Host smart-e34dbe79-d9c9-4991-a8d8-d6d2da907986
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981587230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.981587230
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.190569446
Short name T48
Test name
Test status
Simulation time 689855473 ps
CPU time 18.86 seconds
Started Jul 11 04:29:13 PM PDT 24
Finished Jul 11 04:29:35 PM PDT 24
Peak memory 219208 kb
Host smart-174ddead-f236-41c5-91d9-53859d638508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190569446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.190569446
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1760346776
Short name T12
Test name
Test status
Simulation time 2543621183 ps
CPU time 14.65 seconds
Started Jul 11 04:29:27 PM PDT 24
Finished Jul 11 04:29:48 PM PDT 24
Peak memory 218512 kb
Host smart-9518a897-9d67-4d06-8fc0-445a03fd6c65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1760346776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1760346776
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1512753936
Short name T134
Test name
Test status
Simulation time 2767343584 ps
CPU time 36.72 seconds
Started Jul 11 04:29:10 PM PDT 24
Finished Jul 11 04:29:49 PM PDT 24
Peak memory 216496 kb
Host smart-c0504576-6938-4eb5-abea-fbabd3cb62c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512753936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1512753936
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3508432091
Short name T341
Test name
Test status
Simulation time 40123262272 ps
CPU time 68.39 seconds
Started Jul 11 04:30:46 PM PDT 24
Finished Jul 11 04:31:57 PM PDT 24
Peak memory 215920 kb
Host smart-72610b6d-60ca-4961-a93f-5b6c04767bfd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508432091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3508432091
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.4172102311
Short name T37
Test name
Test status
Simulation time 170900050 ps
CPU time 8.05 seconds
Started Jul 11 04:30:14 PM PDT 24
Finished Jul 11 04:30:32 PM PDT 24
Peak memory 216604 kb
Host smart-0c89501e-3a2b-4e6b-a3cb-35fb92178231
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172102311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.4172102311
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2386666138
Short name T141
Test name
Test status
Simulation time 23282467925 ps
CPU time 190.26 seconds
Started Jul 11 04:29:22 PM PDT 24
Finished Jul 11 04:32:35 PM PDT 24
Peak memory 241024 kb
Host smart-3172b7e7-952c-4efa-9d4d-8be29e6b5085
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386666138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2386666138
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3290645255
Short name T150
Test name
Test status
Simulation time 8454203386 ps
CPU time 66.4 seconds
Started Jul 11 04:29:08 PM PDT 24
Finished Jul 11 04:30:17 PM PDT 24
Peak memory 219260 kb
Host smart-dee40aef-d0db-458c-a935-9451304a2c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290645255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3290645255
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3401689345
Short name T354
Test name
Test status
Simulation time 21417402159 ps
CPU time 17.66 seconds
Started Jul 11 04:29:11 PM PDT 24
Finished Jul 11 04:29:32 PM PDT 24
Peak memory 219272 kb
Host smart-cc54f761-2ef2-4409-9f9c-e93d647087b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3401689345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3401689345
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2483263628
Short name T306
Test name
Test status
Simulation time 8838125323 ps
CPU time 81.36 seconds
Started Jul 11 04:30:14 PM PDT 24
Finished Jul 11 04:31:45 PM PDT 24
Peak memory 215072 kb
Host smart-73ccdf84-713c-41b4-be09-3b184042ec78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483263628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2483263628
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3351192259
Short name T247
Test name
Test status
Simulation time 689174817 ps
CPU time 14.73 seconds
Started Jul 11 04:29:09 PM PDT 24
Finished Jul 11 04:29:26 PM PDT 24
Peak memory 219208 kb
Host smart-e93d281f-ec47-43e2-ba7f-9de0748ea9be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351192259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3351192259
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.4192854516
Short name T53
Test name
Test status
Simulation time 117683932368 ps
CPU time 1117.6 seconds
Started Jul 11 04:29:22 PM PDT 24
Finished Jul 11 04:48:03 PM PDT 24
Peak memory 231984 kb
Host smart-37910ee9-2926-49de-8849-7cbd4bf2893a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192854516 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.4192854516
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2430594425
Short name T161
Test name
Test status
Simulation time 1452181077 ps
CPU time 16.82 seconds
Started Jul 11 04:29:17 PM PDT 24
Finished Jul 11 04:29:37 PM PDT 24
Peak memory 217144 kb
Host smart-cedcb52b-15af-40c7-b77e-4f9639c30470
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430594425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2430594425
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3703075774
Short name T51
Test name
Test status
Simulation time 31718842232 ps
CPU time 278.82 seconds
Started Jul 11 04:29:10 PM PDT 24
Finished Jul 11 04:33:52 PM PDT 24
Peak memory 219412 kb
Host smart-d5891c9f-17f0-44a0-a3b6-32a240c72caf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703075774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3703075774
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2791775811
Short name T360
Test name
Test status
Simulation time 10235938000 ps
CPU time 34.75 seconds
Started Jul 11 04:29:11 PM PDT 24
Finished Jul 11 04:29:49 PM PDT 24
Peak memory 219288 kb
Host smart-dd414aed-40bb-41ec-9daa-b3596ba4af3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791775811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2791775811
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3732420046
Short name T145
Test name
Test status
Simulation time 7708394122 ps
CPU time 26.16 seconds
Started Jul 11 04:29:12 PM PDT 24
Finished Jul 11 04:29:41 PM PDT 24
Peak memory 219296 kb
Host smart-cdb65a44-7240-4e36-aa21-d553cc322f64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3732420046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3732420046
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3820975910
Short name T337
Test name
Test status
Simulation time 6462367835 ps
CPU time 68.42 seconds
Started Jul 11 04:29:15 PM PDT 24
Finished Jul 11 04:30:27 PM PDT 24
Peak memory 216448 kb
Host smart-1567fadd-c732-4c74-999a-f5d3abff9747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820975910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3820975910
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3038258892
Short name T122
Test name
Test status
Simulation time 4398890392 ps
CPU time 53.38 seconds
Started Jul 11 04:29:16 PM PDT 24
Finished Jul 11 04:30:12 PM PDT 24
Peak memory 219424 kb
Host smart-7969b7d6-ef63-4312-a9db-015d29f709d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038258892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3038258892
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2994884083
Short name T157
Test name
Test status
Simulation time 3328511476 ps
CPU time 28.08 seconds
Started Jul 11 04:29:18 PM PDT 24
Finished Jul 11 04:29:49 PM PDT 24
Peak memory 217212 kb
Host smart-0eb2b478-2168-415c-a4ca-2fdd42ecbed4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994884083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2994884083
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3094615320
Short name T317
Test name
Test status
Simulation time 40760899589 ps
CPU time 428.83 seconds
Started Jul 11 04:29:13 PM PDT 24
Finished Jul 11 04:36:24 PM PDT 24
Peak memory 233724 kb
Host smart-0aa70a03-c510-44ef-8120-28045fc382eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094615320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3094615320
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2250946
Short name T233
Test name
Test status
Simulation time 16020421488 ps
CPU time 65.8 seconds
Started Jul 11 04:29:19 PM PDT 24
Finished Jul 11 04:30:27 PM PDT 24
Peak memory 219160 kb
Host smart-9def578b-b5ea-48dc-83de-44855c7ebc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2250946
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1894411980
Short name T21
Test name
Test status
Simulation time 227186844 ps
CPU time 10 seconds
Started Jul 11 04:29:10 PM PDT 24
Finished Jul 11 04:29:23 PM PDT 24
Peak memory 219208 kb
Host smart-24508e42-311d-41c6-9bfb-b501b21a6b36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1894411980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1894411980
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.419241358
Short name T264
Test name
Test status
Simulation time 1373682243 ps
CPU time 19.04 seconds
Started Jul 11 04:30:33 PM PDT 24
Finished Jul 11 04:31:01 PM PDT 24
Peak memory 216508 kb
Host smart-3733453b-88c6-40c1-a4d0-628b33ad8eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419241358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.419241358
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1232682489
Short name T30
Test name
Test status
Simulation time 16197598832 ps
CPU time 154.6 seconds
Started Jul 11 04:30:14 PM PDT 24
Finished Jul 11 04:32:58 PM PDT 24
Peak memory 226472 kb
Host smart-c07442b9-73d8-488b-995d-88c87eec2c24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232682489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1232682489
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2571545541
Short name T55
Test name
Test status
Simulation time 24285551411 ps
CPU time 932.94 seconds
Started Jul 11 04:29:29 PM PDT 24
Finished Jul 11 04:45:03 PM PDT 24
Peak memory 235684 kb
Host smart-e68f7aa2-9a65-4126-a23f-c7ce0357700f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571545541 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.2571545541
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2032656234
Short name T234
Test name
Test status
Simulation time 660677064 ps
CPU time 8.35 seconds
Started Jul 11 04:29:23 PM PDT 24
Finished Jul 11 04:29:34 PM PDT 24
Peak memory 216932 kb
Host smart-2163c1b4-1240-44b2-9e08-8b9e86699123
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032656234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2032656234
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3848287709
Short name T263
Test name
Test status
Simulation time 208821667845 ps
CPU time 836.17 seconds
Started Jul 11 04:29:22 PM PDT 24
Finished Jul 11 04:43:21 PM PDT 24
Peak memory 234032 kb
Host smart-aeb5a1d0-cf5e-416c-95ad-aabe3b9ff794
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848287709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3848287709
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2086521213
Short name T295
Test name
Test status
Simulation time 6867069140 ps
CPU time 56.57 seconds
Started Jul 11 04:30:45 PM PDT 24
Finished Jul 11 04:31:45 PM PDT 24
Peak memory 219252 kb
Host smart-973e2d8b-61d5-4278-b65b-75a2682bf301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086521213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2086521213
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3718493031
Short name T262
Test name
Test status
Simulation time 852576701 ps
CPU time 15.65 seconds
Started Jul 11 04:29:20 PM PDT 24
Finished Jul 11 04:29:37 PM PDT 24
Peak memory 219208 kb
Host smart-7377285c-8148-4d6d-9ddb-67875745888c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3718493031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3718493031
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3679993125
Short name T335
Test name
Test status
Simulation time 5631779268 ps
CPU time 50.46 seconds
Started Jul 11 04:29:18 PM PDT 24
Finished Jul 11 04:30:11 PM PDT 24
Peak memory 216796 kb
Host smart-07ae9454-7bf5-4a7b-a686-8501e2fcff57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679993125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3679993125
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1687838256
Short name T340
Test name
Test status
Simulation time 1617069717 ps
CPU time 24.09 seconds
Started Jul 11 04:29:09 PM PDT 24
Finished Jul 11 04:29:37 PM PDT 24
Peak memory 219232 kb
Host smart-ff9072f2-20f1-4ea6-a7ac-6ab7b9148921
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687838256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1687838256
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1678944040
Short name T160
Test name
Test status
Simulation time 8859752679 ps
CPU time 21.78 seconds
Started Jul 11 04:29:21 PM PDT 24
Finished Jul 11 04:29:45 PM PDT 24
Peak memory 217596 kb
Host smart-5c0da775-6c74-48d6-9c87-dde4cd3c8bd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678944040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1678944040
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3659935530
Short name T351
Test name
Test status
Simulation time 134054755710 ps
CPU time 704.02 seconds
Started Jul 11 04:29:21 PM PDT 24
Finished Jul 11 04:41:08 PM PDT 24
Peak memory 229156 kb
Host smart-f2c09ff9-c617-4b91-bf66-94d6fa3a2379
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659935530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3659935530
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.271653740
Short name T123
Test name
Test status
Simulation time 4770152022 ps
CPU time 46.94 seconds
Started Jul 11 04:29:55 PM PDT 24
Finished Jul 11 04:30:47 PM PDT 24
Peak memory 219060 kb
Host smart-b6c06977-9a0c-46fc-9072-ab0c9b2b56da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271653740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.271653740
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.992207366
Short name T190
Test name
Test status
Simulation time 901337846 ps
CPU time 11.28 seconds
Started Jul 11 04:29:10 PM PDT 24
Finished Jul 11 04:29:24 PM PDT 24
Peak memory 219176 kb
Host smart-941b73af-72e3-4675-84e8-8db0668350a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=992207366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.992207366
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3259871340
Short name T272
Test name
Test status
Simulation time 679206049 ps
CPU time 24.12 seconds
Started Jul 11 04:29:14 PM PDT 24
Finished Jul 11 04:29:42 PM PDT 24
Peak memory 216548 kb
Host smart-954e1f71-6910-44bc-9f0c-804170f190d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259871340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3259871340
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.4120985034
Short name T179
Test name
Test status
Simulation time 10256489413 ps
CPU time 92.17 seconds
Started Jul 11 04:29:03 PM PDT 24
Finished Jul 11 04:30:36 PM PDT 24
Peak memory 219272 kb
Host smart-b67accd9-032f-47c5-b80c-350c306a6642
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120985034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.4120985034
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.59137403
Short name T147
Test name
Test status
Simulation time 345461946 ps
CPU time 8.35 seconds
Started Jul 11 04:29:30 PM PDT 24
Finished Jul 11 04:29:40 PM PDT 24
Peak memory 216972 kb
Host smart-12d8eb7f-99dd-4e12-8132-b97e7e591dca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59137403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.59137403
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3900348386
Short name T305
Test name
Test status
Simulation time 35063307668 ps
CPU time 68.49 seconds
Started Jul 11 04:29:21 PM PDT 24
Finished Jul 11 04:30:33 PM PDT 24
Peak memory 219296 kb
Host smart-8838b415-c9d9-45aa-b941-af59b8283bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900348386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3900348386
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.906846394
Short name T136
Test name
Test status
Simulation time 951144905 ps
CPU time 15.92 seconds
Started Jul 11 04:29:23 PM PDT 24
Finished Jul 11 04:29:42 PM PDT 24
Peak memory 219196 kb
Host smart-2dd43461-a011-4584-b9a8-8d5525dfd0c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=906846394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.906846394
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.372197914
Short name T273
Test name
Test status
Simulation time 7735743294 ps
CPU time 46.59 seconds
Started Jul 11 04:29:48 PM PDT 24
Finished Jul 11 04:30:37 PM PDT 24
Peak memory 218992 kb
Host smart-0c12ffcb-c666-499b-b92c-28f5f777c085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372197914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.372197914
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2598450426
Short name T226
Test name
Test status
Simulation time 5442569075 ps
CPU time 72.12 seconds
Started Jul 11 04:29:21 PM PDT 24
Finished Jul 11 04:30:35 PM PDT 24
Peak memory 219224 kb
Host smart-2905bee9-aca1-40c8-9267-dbdb6ae3df08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598450426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2598450426
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1469705155
Short name T56
Test name
Test status
Simulation time 8794443120 ps
CPU time 1038.22 seconds
Started Jul 11 04:29:25 PM PDT 24
Finished Jul 11 04:46:46 PM PDT 24
Peak memory 235748 kb
Host smart-10d7c832-85a0-4f77-b823-70ef52288990
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469705155 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.1469705155
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2057316377
Short name T125
Test name
Test status
Simulation time 2355574504 ps
CPU time 8.24 seconds
Started Jul 11 04:29:21 PM PDT 24
Finished Jul 11 04:29:32 PM PDT 24
Peak memory 217156 kb
Host smart-db98e770-fc7e-4bbf-8a32-d58aff1db108
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057316377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2057316377
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2833500291
Short name T168
Test name
Test status
Simulation time 394974881052 ps
CPU time 642.07 seconds
Started Jul 11 04:29:25 PM PDT 24
Finished Jul 11 04:40:10 PM PDT 24
Peak memory 216908 kb
Host smart-7b87bb43-8591-4eb3-a82c-7862cc70255d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833500291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2833500291
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3663472206
Short name T216
Test name
Test status
Simulation time 49324398618 ps
CPU time 50.83 seconds
Started Jul 11 04:30:00 PM PDT 24
Finished Jul 11 04:31:00 PM PDT 24
Peak memory 219160 kb
Host smart-431f8c0e-7407-49bd-9f44-0387ff352f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663472206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3663472206
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1373912764
Short name T330
Test name
Test status
Simulation time 7562301970 ps
CPU time 20.99 seconds
Started Jul 11 04:29:20 PM PDT 24
Finished Jul 11 04:29:43 PM PDT 24
Peak memory 219268 kb
Host smart-c2cb5394-fea6-4aad-8bc3-8d695907d5fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1373912764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1373912764
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3061517021
Short name T208
Test name
Test status
Simulation time 8701638378 ps
CPU time 52.53 seconds
Started Jul 11 04:29:21 PM PDT 24
Finished Jul 11 04:30:16 PM PDT 24
Peak memory 216996 kb
Host smart-7cae9a0d-d322-4317-91e2-2f12b9de1347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061517021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3061517021
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1123654571
Short name T169
Test name
Test status
Simulation time 16505754322 ps
CPU time 67.43 seconds
Started Jul 11 04:29:06 PM PDT 24
Finished Jul 11 04:30:17 PM PDT 24
Peak memory 217368 kb
Host smart-7dd2497d-5d57-4373-a251-50931fa285fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123654571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1123654571
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1009450904
Short name T278
Test name
Test status
Simulation time 17602078904 ps
CPU time 28.35 seconds
Started Jul 11 04:29:45 PM PDT 24
Finished Jul 11 04:30:15 PM PDT 24
Peak memory 217460 kb
Host smart-0b0079a6-3aa8-4375-9c74-6a73a94c3d2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009450904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1009450904
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2826157543
Short name T45
Test name
Test status
Simulation time 675385452 ps
CPU time 18.65 seconds
Started Jul 11 04:29:15 PM PDT 24
Finished Jul 11 04:29:37 PM PDT 24
Peak memory 219200 kb
Host smart-5e6c645c-9e21-4667-a9a2-6d685172475a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826157543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2826157543
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3869186580
Short name T185
Test name
Test status
Simulation time 3936911662 ps
CPU time 31.91 seconds
Started Jul 11 04:29:26 PM PDT 24
Finished Jul 11 04:30:00 PM PDT 24
Peak memory 219236 kb
Host smart-39f73a32-ae8a-4a89-82c7-e227d87f69e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3869186580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3869186580
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.4285483549
Short name T237
Test name
Test status
Simulation time 30738471547 ps
CPU time 75.89 seconds
Started Jul 11 04:29:18 PM PDT 24
Finished Jul 11 04:30:37 PM PDT 24
Peak memory 216220 kb
Host smart-e934b78d-1373-4910-8c9b-b879ab0cfdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285483549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.4285483549
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2102321191
Short name T284
Test name
Test status
Simulation time 4249202011 ps
CPU time 23.42 seconds
Started Jul 11 04:29:22 PM PDT 24
Finished Jul 11 04:29:49 PM PDT 24
Peak memory 217752 kb
Host smart-132184e6-e4ac-4084-a1b9-4ce15277007b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102321191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2102321191
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.405467591
Short name T167
Test name
Test status
Simulation time 3492460959 ps
CPU time 27.21 seconds
Started Jul 11 04:28:43 PM PDT 24
Finished Jul 11 04:29:12 PM PDT 24
Peak memory 213240 kb
Host smart-1e8d7ac4-227d-4129-a810-e5ac3e2e9000
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405467591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.405467591
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1671224827
Short name T203
Test name
Test status
Simulation time 49060700037 ps
CPU time 271.25 seconds
Started Jul 11 04:29:01 PM PDT 24
Finished Jul 11 04:33:34 PM PDT 24
Peak memory 219344 kb
Host smart-e6d769f4-cd70-4ec6-a525-6e74337a4161
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671224827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1671224827
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.266978935
Short name T164
Test name
Test status
Simulation time 30487051243 ps
CPU time 63.01 seconds
Started Jul 11 04:28:33 PM PDT 24
Finished Jul 11 04:29:38 PM PDT 24
Peak memory 219288 kb
Host smart-711010e0-cb13-4f0e-92e0-b6242c1d2393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266978935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.266978935
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1634189757
Short name T126
Test name
Test status
Simulation time 6865964421 ps
CPU time 28.71 seconds
Started Jul 11 04:28:29 PM PDT 24
Finished Jul 11 04:29:09 PM PDT 24
Peak memory 219284 kb
Host smart-980350a2-9861-4b48-99a2-2269ec2068c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1634189757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1634189757
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3432239415
Short name T28
Test name
Test status
Simulation time 2651831858 ps
CPU time 129.43 seconds
Started Jul 11 04:28:27 PM PDT 24
Finished Jul 11 04:30:38 PM PDT 24
Peak memory 239664 kb
Host smart-e58b6b4a-6b67-4e2b-8959-5032e3d2a333
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432239415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3432239415
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3844514924
Short name T296
Test name
Test status
Simulation time 23229225769 ps
CPU time 56.23 seconds
Started Jul 11 04:29:13 PM PDT 24
Finished Jul 11 04:30:13 PM PDT 24
Peak memory 216868 kb
Host smart-706d516a-5199-4ac4-abcc-7187da12d26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844514924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3844514924
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1025977134
Short name T156
Test name
Test status
Simulation time 520471713 ps
CPU time 33.52 seconds
Started Jul 11 04:28:30 PM PDT 24
Finished Jul 11 04:29:05 PM PDT 24
Peak memory 219236 kb
Host smart-92d57654-b979-4a90-be64-1e2cf27c7ccc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025977134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1025977134
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2706703678
Short name T353
Test name
Test status
Simulation time 3956880184 ps
CPU time 15.04 seconds
Started Jul 11 04:29:39 PM PDT 24
Finished Jul 11 04:29:57 PM PDT 24
Peak memory 217116 kb
Host smart-bf0d04e6-c04a-470f-8f2f-036937562b38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706703678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2706703678
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3891604298
Short name T287
Test name
Test status
Simulation time 12791873215 ps
CPU time 258.75 seconds
Started Jul 11 04:29:16 PM PDT 24
Finished Jul 11 04:33:38 PM PDT 24
Peak memory 242672 kb
Host smart-e1c9af19-7ca6-40fc-b7a8-aa2b37d65363
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891604298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3891604298
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.76314078
Short name T279
Test name
Test status
Simulation time 26789958658 ps
CPU time 58.47 seconds
Started Jul 11 04:29:18 PM PDT 24
Finished Jul 11 04:30:19 PM PDT 24
Peak memory 219332 kb
Host smart-442bf006-5b5c-4635-bee4-de9a15978b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76314078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.76314078
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1685811909
Short name T178
Test name
Test status
Simulation time 186257553 ps
CPU time 10.12 seconds
Started Jul 11 04:29:23 PM PDT 24
Finished Jul 11 04:29:36 PM PDT 24
Peak memory 219244 kb
Host smart-937b5ced-87f0-43ae-aa5c-b6e1c9676595
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1685811909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1685811909
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3196581658
Short name T189
Test name
Test status
Simulation time 23286213449 ps
CPU time 50.79 seconds
Started Jul 11 04:29:14 PM PDT 24
Finished Jul 11 04:30:07 PM PDT 24
Peak memory 216964 kb
Host smart-a6164340-cb58-4706-9fff-85d0ef36d657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196581658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3196581658
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2147719118
Short name T299
Test name
Test status
Simulation time 4179040545 ps
CPU time 63.2 seconds
Started Jul 11 04:29:19 PM PDT 24
Finished Jul 11 04:30:25 PM PDT 24
Peak memory 222552 kb
Host smart-e5b38747-d093-4887-9c28-33f14c61f620
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147719118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2147719118
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2073966216
Short name T44
Test name
Test status
Simulation time 3541279056 ps
CPU time 28.99 seconds
Started Jul 11 04:29:57 PM PDT 24
Finished Jul 11 04:30:33 PM PDT 24
Peak memory 216788 kb
Host smart-edac78f8-0cd1-42e6-9536-c664fe467696
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073966216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2073966216
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.759461648
Short name T328
Test name
Test status
Simulation time 7039261718 ps
CPU time 58.63 seconds
Started Jul 11 04:29:24 PM PDT 24
Finished Jul 11 04:30:26 PM PDT 24
Peak memory 219348 kb
Host smart-509f5923-5e74-48b7-987a-b8101d147d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759461648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.759461648
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.806460412
Short name T153
Test name
Test status
Simulation time 11690827687 ps
CPU time 14.35 seconds
Started Jul 11 04:29:21 PM PDT 24
Finished Jul 11 04:29:39 PM PDT 24
Peak memory 217704 kb
Host smart-634ca227-d52c-45f4-8352-8133fc126db0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=806460412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.806460412
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2038170296
Short name T274
Test name
Test status
Simulation time 29132511402 ps
CPU time 61.21 seconds
Started Jul 11 04:29:39 PM PDT 24
Finished Jul 11 04:30:43 PM PDT 24
Peak memory 218732 kb
Host smart-c93c4b6d-f4f5-43c0-98a2-b5168b7fe909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038170296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2038170296
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2103183279
Short name T311
Test name
Test status
Simulation time 4713660972 ps
CPU time 24.62 seconds
Started Jul 11 04:29:13 PM PDT 24
Finished Jul 11 04:29:41 PM PDT 24
Peak memory 214788 kb
Host smart-90ded6f5-2e8e-4ef0-860a-b54645c37031
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103183279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2103183279
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2441667215
Short name T13
Test name
Test status
Simulation time 59989630754 ps
CPU time 2310.29 seconds
Started Jul 11 04:29:24 PM PDT 24
Finished Jul 11 05:07:57 PM PDT 24
Peak memory 243968 kb
Host smart-3e84175d-d357-4317-97e8-262ad750a834
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441667215 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.2441667215
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1978332590
Short name T7
Test name
Test status
Simulation time 662014498 ps
CPU time 8.38 seconds
Started Jul 11 04:29:43 PM PDT 24
Finished Jul 11 04:29:53 PM PDT 24
Peak memory 217052 kb
Host smart-b778a1b4-1493-4fec-85aa-56ad6a8120e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978332590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1978332590
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.4088474434
Short name T332
Test name
Test status
Simulation time 22974439865 ps
CPU time 265.99 seconds
Started Jul 11 04:29:25 PM PDT 24
Finished Jul 11 04:33:54 PM PDT 24
Peak memory 233672 kb
Host smart-932b4f12-12c5-4a48-a8e4-ce86488ef350
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088474434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.4088474434
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3578043210
Short name T47
Test name
Test status
Simulation time 1222208001 ps
CPU time 19.23 seconds
Started Jul 11 04:29:42 PM PDT 24
Finished Jul 11 04:30:02 PM PDT 24
Peak memory 219228 kb
Host smart-d6f0c9cc-9544-448e-8d8a-3c7b1e271843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578043210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3578043210
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.996122497
Short name T130
Test name
Test status
Simulation time 4891557333 ps
CPU time 23.45 seconds
Started Jul 11 04:29:26 PM PDT 24
Finished Jul 11 04:29:52 PM PDT 24
Peak memory 219228 kb
Host smart-bb22b4a9-9713-47e4-9065-828d4c3005ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=996122497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.996122497
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1344495451
Short name T228
Test name
Test status
Simulation time 6062748021 ps
CPU time 37.58 seconds
Started Jul 11 04:29:38 PM PDT 24
Finished Jul 11 04:30:18 PM PDT 24
Peak memory 216440 kb
Host smart-e7b6170b-0b20-45f9-aa3b-d8fed9af01ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344495451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1344495451
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.217033919
Short name T79
Test name
Test status
Simulation time 577722546 ps
CPU time 38.66 seconds
Started Jul 11 04:29:48 PM PDT 24
Finished Jul 11 04:30:29 PM PDT 24
Peak memory 219512 kb
Host smart-57773ddf-131c-480a-be02-2336b73bb5c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217033919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.217033919
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.4275753749
Short name T259
Test name
Test status
Simulation time 2609261430 ps
CPU time 23.51 seconds
Started Jul 11 04:29:20 PM PDT 24
Finished Jul 11 04:29:46 PM PDT 24
Peak memory 217016 kb
Host smart-b18f15f4-dda0-422b-84f2-8c88d4264d3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275753749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.4275753749
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2342551797
Short name T120
Test name
Test status
Simulation time 4457448624 ps
CPU time 321.56 seconds
Started Jul 11 04:29:23 PM PDT 24
Finished Jul 11 04:34:48 PM PDT 24
Peak memory 241984 kb
Host smart-b5eb11a3-2883-439d-b927-2f1e3a72cb39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342551797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2342551797
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3800169921
Short name T238
Test name
Test status
Simulation time 26444827614 ps
CPU time 68.21 seconds
Started Jul 11 04:29:21 PM PDT 24
Finished Jul 11 04:30:33 PM PDT 24
Peak memory 219572 kb
Host smart-173260af-a30c-4b22-bfab-627e9b0aa01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800169921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3800169921
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.960941447
Short name T4
Test name
Test status
Simulation time 699918548 ps
CPU time 12.91 seconds
Started Jul 11 04:29:39 PM PDT 24
Finished Jul 11 04:29:55 PM PDT 24
Peak memory 218384 kb
Host smart-ea51e917-3a4a-402a-927b-5ab2042d298a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=960941447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.960941447
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3480510282
Short name T254
Test name
Test status
Simulation time 361826834 ps
CPU time 20.11 seconds
Started Jul 11 04:29:52 PM PDT 24
Finished Jul 11 04:30:15 PM PDT 24
Peak memory 216788 kb
Host smart-4e14d378-bd5c-45ba-ab7d-b243007785b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480510282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3480510282
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1179486166
Short name T349
Test name
Test status
Simulation time 67749107944 ps
CPU time 161.12 seconds
Started Jul 11 04:29:38 PM PDT 24
Finished Jul 11 04:32:21 PM PDT 24
Peak memory 221384 kb
Host smart-21203355-87c7-4653-8596-405b4788188b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179486166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1179486166
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2427632819
Short name T62
Test name
Test status
Simulation time 4074064424 ps
CPU time 31.17 seconds
Started Jul 11 04:29:38 PM PDT 24
Finished Jul 11 04:30:13 PM PDT 24
Peak memory 216544 kb
Host smart-58ad2a9b-3883-4e0b-8a4d-d1aa0db6a13e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427632819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2427632819
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3751041753
Short name T131
Test name
Test status
Simulation time 226899432210 ps
CPU time 527.79 seconds
Started Jul 11 04:29:20 PM PDT 24
Finished Jul 11 04:38:10 PM PDT 24
Peak memory 242584 kb
Host smart-312fbb2c-7694-4235-9100-4a2861762cf8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751041753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3751041753
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1307987610
Short name T269
Test name
Test status
Simulation time 346046008 ps
CPU time 18.84 seconds
Started Jul 11 04:29:27 PM PDT 24
Finished Jul 11 04:29:48 PM PDT 24
Peak memory 219204 kb
Host smart-0c1fd1be-ff01-4100-b3c5-a2345395d084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307987610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1307987610
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3675969205
Short name T198
Test name
Test status
Simulation time 1949630406 ps
CPU time 10.59 seconds
Started Jul 11 04:29:26 PM PDT 24
Finished Jul 11 04:29:38 PM PDT 24
Peak memory 218936 kb
Host smart-4ccc0aaf-771a-4cfc-b26d-6f8fb8bbaaf4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3675969205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3675969205
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3243671841
Short name T241
Test name
Test status
Simulation time 1365322485 ps
CPU time 19.52 seconds
Started Jul 11 04:29:38 PM PDT 24
Finished Jul 11 04:30:01 PM PDT 24
Peak memory 216584 kb
Host smart-93bb7d2d-3159-4a85-ae75-b7aa9a8b4b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243671841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3243671841
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.449551899
Short name T137
Test name
Test status
Simulation time 27816609616 ps
CPU time 121.18 seconds
Started Jul 11 04:29:55 PM PDT 24
Finished Jul 11 04:32:02 PM PDT 24
Peak memory 220732 kb
Host smart-6148dfcd-9030-4d6f-b98d-9751e2a1854e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449551899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.449551899
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.4247584756
Short name T151
Test name
Test status
Simulation time 4861180214 ps
CPU time 31.69 seconds
Started Jul 11 04:29:40 PM PDT 24
Finished Jul 11 04:30:14 PM PDT 24
Peak memory 217484 kb
Host smart-ab775888-437b-4e30-991d-c44a4516f9f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247584756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.4247584756
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1319304099
Short name T302
Test name
Test status
Simulation time 28420651041 ps
CPU time 385.32 seconds
Started Jul 11 04:29:39 PM PDT 24
Finished Jul 11 04:36:08 PM PDT 24
Peak memory 227068 kb
Host smart-9a6ee17d-38c7-4da9-81fd-93f6acb03310
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319304099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1319304099
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1811444251
Short name T309
Test name
Test status
Simulation time 111346518087 ps
CPU time 61.49 seconds
Started Jul 11 04:29:37 PM PDT 24
Finished Jul 11 04:30:40 PM PDT 24
Peak memory 219136 kb
Host smart-51e109c8-c21d-479c-aec7-5b97ef1ffad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811444251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1811444251
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3296116261
Short name T129
Test name
Test status
Simulation time 2366277007 ps
CPU time 22.84 seconds
Started Jul 11 04:29:20 PM PDT 24
Finished Jul 11 04:29:45 PM PDT 24
Peak memory 211232 kb
Host smart-332c8f58-b8db-48a4-99de-b5e204e801d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3296116261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3296116261
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.4026552170
Short name T319
Test name
Test status
Simulation time 75363078535 ps
CPU time 52.2 seconds
Started Jul 11 04:29:26 PM PDT 24
Finished Jul 11 04:30:21 PM PDT 24
Peak memory 216752 kb
Host smart-96ac2fc7-491e-44c2-9db5-f5b895a89400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026552170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.4026552170
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.604396688
Short name T260
Test name
Test status
Simulation time 8592773892 ps
CPU time 35.24 seconds
Started Jul 11 04:29:45 PM PDT 24
Finished Jul 11 04:30:22 PM PDT 24
Peak memory 219108 kb
Host smart-82adbdf0-d32e-4111-8dc3-c739d7c48272
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604396688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.604396688
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3256600722
Short name T204
Test name
Test status
Simulation time 4636101447 ps
CPU time 23.39 seconds
Started Jul 11 04:29:37 PM PDT 24
Finished Jul 11 04:30:03 PM PDT 24
Peak memory 217464 kb
Host smart-82660b85-2d9d-4619-a44e-f1b87321d152
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256600722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3256600722
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3681251640
Short name T240
Test name
Test status
Simulation time 57974761276 ps
CPU time 421.1 seconds
Started Jul 11 04:29:41 PM PDT 24
Finished Jul 11 04:36:44 PM PDT 24
Peak memory 228460 kb
Host smart-1aa639b7-b325-45e1-8de7-1a14ce1f8ffa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681251640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3681251640
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3778122691
Short name T256
Test name
Test status
Simulation time 1320186151 ps
CPU time 18.93 seconds
Started Jul 11 04:29:23 PM PDT 24
Finished Jul 11 04:29:45 PM PDT 24
Peak memory 219164 kb
Host smart-24a070cf-0345-465d-8e40-57bb81c625ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778122691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3778122691
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2048845911
Short name T229
Test name
Test status
Simulation time 28390114232 ps
CPU time 31.27 seconds
Started Jul 11 04:29:32 PM PDT 24
Finished Jul 11 04:30:04 PM PDT 24
Peak memory 219240 kb
Host smart-da4c2d57-ebc2-429c-9245-683db018fe33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2048845911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2048845911
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.4206958580
Short name T242
Test name
Test status
Simulation time 7617565569 ps
CPU time 62.65 seconds
Started Jul 11 04:29:44 PM PDT 24
Finished Jul 11 04:30:48 PM PDT 24
Peak memory 216720 kb
Host smart-c5252af3-6040-471c-8dc8-bf156c8e7401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206958580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.4206958580
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.121473914
Short name T3
Test name
Test status
Simulation time 31646895319 ps
CPU time 65.3 seconds
Started Jul 11 04:29:44 PM PDT 24
Finished Jul 11 04:30:51 PM PDT 24
Peak memory 219292 kb
Host smart-b6e12698-f718-4912-8a11-7e7bfcc21f85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121473914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.121473914
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.125900425
Short name T217
Test name
Test status
Simulation time 1372236186 ps
CPU time 8.24 seconds
Started Jul 11 04:29:44 PM PDT 24
Finished Jul 11 04:29:54 PM PDT 24
Peak memory 217064 kb
Host smart-aee27022-192d-4b62-860b-8f90d489a543
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125900425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.125900425
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3236570208
Short name T41
Test name
Test status
Simulation time 34124503827 ps
CPU time 332.44 seconds
Started Jul 11 04:29:39 PM PDT 24
Finished Jul 11 04:35:14 PM PDT 24
Peak memory 233940 kb
Host smart-a983840d-85fc-4d49-bea6-ec6639b0a7ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236570208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3236570208
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2065340279
Short name T225
Test name
Test status
Simulation time 2352798072 ps
CPU time 19.59 seconds
Started Jul 11 04:29:24 PM PDT 24
Finished Jul 11 04:29:50 PM PDT 24
Peak memory 219300 kb
Host smart-0affc5aa-d8b3-4e5a-bc1f-9d365bec672b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065340279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2065340279
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3001735719
Short name T246
Test name
Test status
Simulation time 7362655716 ps
CPU time 33.86 seconds
Started Jul 11 04:30:00 PM PDT 24
Finished Jul 11 04:30:43 PM PDT 24
Peak memory 219216 kb
Host smart-7d96425e-d765-442d-a145-0d1dfcff92cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3001735719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3001735719
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2552516039
Short name T10
Test name
Test status
Simulation time 1561403757 ps
CPU time 20.16 seconds
Started Jul 11 04:29:43 PM PDT 24
Finished Jul 11 04:30:05 PM PDT 24
Peak memory 216912 kb
Host smart-26ff25b1-10a1-429e-831d-0012ef3250ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552516039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2552516039
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2165268855
Short name T166
Test name
Test status
Simulation time 47291059850 ps
CPU time 126.12 seconds
Started Jul 11 04:29:21 PM PDT 24
Finished Jul 11 04:31:35 PM PDT 24
Peak memory 220056 kb
Host smart-2a43ab5d-3ec8-4974-9c2b-e84450fd9346
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165268855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2165268855
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.49312513
Short name T286
Test name
Test status
Simulation time 613264096 ps
CPU time 8.05 seconds
Started Jul 11 04:29:35 PM PDT 24
Finished Jul 11 04:29:44 PM PDT 24
Peak memory 216776 kb
Host smart-84ec09e6-b467-4995-adb5-956daeafe9f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49312513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.49312513
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2752471828
Short name T230
Test name
Test status
Simulation time 588322263325 ps
CPU time 522.64 seconds
Started Jul 11 04:29:24 PM PDT 24
Finished Jul 11 04:38:09 PM PDT 24
Peak memory 219424 kb
Host smart-1aa840ff-d79f-4d0d-877f-104bcb092aab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752471828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2752471828
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3046380451
Short name T348
Test name
Test status
Simulation time 689325746 ps
CPU time 18.84 seconds
Started Jul 11 04:29:22 PM PDT 24
Finished Jul 11 04:29:44 PM PDT 24
Peak memory 219224 kb
Host smart-928365b6-070e-4866-87e5-f0f080b05cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046380451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3046380451
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2377757249
Short name T32
Test name
Test status
Simulation time 3383694719 ps
CPU time 20.71 seconds
Started Jul 11 04:29:39 PM PDT 24
Finished Jul 11 04:30:03 PM PDT 24
Peak memory 211324 kb
Host smart-31e1babc-d37b-4ba4-8df3-29121f7e3379
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2377757249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2377757249
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.246704566
Short name T222
Test name
Test status
Simulation time 33609100065 ps
CPU time 54.99 seconds
Started Jul 11 04:29:36 PM PDT 24
Finished Jul 11 04:30:32 PM PDT 24
Peak memory 216080 kb
Host smart-c7987883-3eb3-4c17-aaab-9db2012cdd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246704566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.246704566
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.369027656
Short name T135
Test name
Test status
Simulation time 38464116800 ps
CPU time 186.44 seconds
Started Jul 11 04:29:38 PM PDT 24
Finished Jul 11 04:32:48 PM PDT 24
Peak memory 220304 kb
Host smart-82b8e45b-5273-4313-a8ea-736b8a32f04e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369027656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.369027656
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3727347647
Short name T292
Test name
Test status
Simulation time 22113664637 ps
CPU time 31.32 seconds
Started Jul 11 04:29:44 PM PDT 24
Finished Jul 11 04:30:17 PM PDT 24
Peak memory 217916 kb
Host smart-1248f2c0-8a31-4ab2-b880-3d97c4872674
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727347647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3727347647
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2974951303
Short name T34
Test name
Test status
Simulation time 66141750593 ps
CPU time 448.6 seconds
Started Jul 11 04:29:37 PM PDT 24
Finished Jul 11 04:37:07 PM PDT 24
Peak memory 226196 kb
Host smart-9416b85f-4c2b-4698-9409-0c614a1b374f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974951303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2974951303
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1341930972
Short name T6
Test name
Test status
Simulation time 11612909068 ps
CPU time 36.55 seconds
Started Jul 11 04:29:26 PM PDT 24
Finished Jul 11 04:30:05 PM PDT 24
Peak memory 219108 kb
Host smart-b001a415-23f1-426a-a741-bf16d30ba154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341930972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1341930972
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1325463530
Short name T235
Test name
Test status
Simulation time 11676741342 ps
CPU time 26.82 seconds
Started Jul 11 04:29:57 PM PDT 24
Finished Jul 11 04:30:29 PM PDT 24
Peak memory 219236 kb
Host smart-645cb657-a31d-4e8e-84a3-6f3a17ed79c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1325463530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1325463530
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.644189150
Short name T244
Test name
Test status
Simulation time 3479080117 ps
CPU time 40.76 seconds
Started Jul 11 04:29:26 PM PDT 24
Finished Jul 11 04:30:09 PM PDT 24
Peak memory 216320 kb
Host smart-623471a0-e803-493e-875b-e15d92b37280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644189150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.644189150
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2042774151
Short name T64
Test name
Test status
Simulation time 613244269 ps
CPU time 8.08 seconds
Started Jul 11 04:28:35 PM PDT 24
Finished Jul 11 04:28:45 PM PDT 24
Peak memory 217060 kb
Host smart-409d4ebb-a210-409e-b97d-0a56b8186800
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042774151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2042774151
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3756590543
Short name T275
Test name
Test status
Simulation time 9294499439 ps
CPU time 51.94 seconds
Started Jul 11 04:29:03 PM PDT 24
Finished Jul 11 04:29:56 PM PDT 24
Peak memory 219236 kb
Host smart-1bc70042-47ff-4d2d-8946-97681e5b4213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756590543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3756590543
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1102868721
Short name T127
Test name
Test status
Simulation time 8568379653 ps
CPU time 22.02 seconds
Started Jul 11 04:28:21 PM PDT 24
Finished Jul 11 04:28:45 PM PDT 24
Peak memory 219260 kb
Host smart-f0a7f92c-b892-41be-b56b-3b9fc89cfd14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1102868721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1102868721
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3576738493
Short name T258
Test name
Test status
Simulation time 6418190733 ps
CPU time 56.39 seconds
Started Jul 11 04:29:12 PM PDT 24
Finished Jul 11 04:30:11 PM PDT 24
Peak memory 216996 kb
Host smart-c8cd4936-588b-458b-b0c5-26aad283dc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576738493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3576738493
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2943809240
Short name T288
Test name
Test status
Simulation time 543078352 ps
CPU time 27.5 seconds
Started Jul 11 04:28:32 PM PDT 24
Finished Jul 11 04:29:01 PM PDT 24
Peak memory 219184 kb
Host smart-062abebb-ceb3-4598-8cd7-ba300d4c2bb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943809240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2943809240
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3284432247
Short name T16
Test name
Test status
Simulation time 62559668011 ps
CPU time 8245.18 seconds
Started Jul 11 04:28:59 PM PDT 24
Finished Jul 11 06:46:28 PM PDT 24
Peak memory 240376 kb
Host smart-5332679b-cef5-4fd5-bacb-6a3d71efdb10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284432247 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.3284432247
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3599021737
Short name T8
Test name
Test status
Simulation time 174675981 ps
CPU time 8.18 seconds
Started Jul 11 04:28:34 PM PDT 24
Finished Jul 11 04:28:44 PM PDT 24
Peak memory 217052 kb
Host smart-7226011a-7aa9-40a1-aa62-86db8b998dcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599021737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3599021737
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.100051181
Short name T171
Test name
Test status
Simulation time 53989590893 ps
CPU time 568.34 seconds
Started Jul 11 04:28:47 PM PDT 24
Finished Jul 11 04:38:17 PM PDT 24
Peak memory 233668 kb
Host smart-54eceb97-939a-44c1-a804-7fc6fe78a448
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100051181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.100051181
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3603268802
Short name T121
Test name
Test status
Simulation time 50631497543 ps
CPU time 59.11 seconds
Started Jul 11 04:28:34 PM PDT 24
Finished Jul 11 04:29:36 PM PDT 24
Peak memory 219176 kb
Host smart-05ad7cd4-6e1d-4e12-9695-594139c6b009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603268802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3603268802
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.904373259
Short name T300
Test name
Test status
Simulation time 2829300965 ps
CPU time 26.44 seconds
Started Jul 11 04:28:53 PM PDT 24
Finished Jul 11 04:29:21 PM PDT 24
Peak memory 219208 kb
Host smart-19e2b5cf-23c5-4946-b009-d248ecc395ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=904373259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.904373259
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.4244971944
Short name T80
Test name
Test status
Simulation time 6473292709 ps
CPU time 63.44 seconds
Started Jul 11 04:28:59 PM PDT 24
Finished Jul 11 04:30:05 PM PDT 24
Peak memory 216664 kb
Host smart-717abdfd-ecb8-4646-888a-752abf9d0011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244971944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.4244971944
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2469163073
Short name T82
Test name
Test status
Simulation time 582520825 ps
CPU time 31.37 seconds
Started Jul 11 04:28:33 PM PDT 24
Finished Jul 11 04:29:06 PM PDT 24
Peak memory 219232 kb
Host smart-94bb596b-ae9b-46e7-85a1-57a2aa76f2be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469163073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2469163073
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3797273632
Short name T312
Test name
Test status
Simulation time 2062717290 ps
CPU time 20.4 seconds
Started Jul 11 04:28:36 PM PDT 24
Finished Jul 11 04:28:58 PM PDT 24
Peak memory 217076 kb
Host smart-d74b490a-b31a-419c-938b-0c034b1dcd2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797273632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3797273632
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3049765366
Short name T36
Test name
Test status
Simulation time 55285549581 ps
CPU time 598.11 seconds
Started Jul 11 04:28:28 PM PDT 24
Finished Jul 11 04:38:29 PM PDT 24
Peak memory 233788 kb
Host smart-33fbbbf9-95ad-4545-9d29-6f11f8baddd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049765366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3049765366
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.326051791
Short name T124
Test name
Test status
Simulation time 7198818389 ps
CPU time 39.4 seconds
Started Jul 11 04:28:58 PM PDT 24
Finished Jul 11 04:29:41 PM PDT 24
Peak memory 219244 kb
Host smart-ce92fa71-460d-4ea0-8f0e-675cc3869a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326051791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.326051791
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1425256237
Short name T43
Test name
Test status
Simulation time 1056287187 ps
CPU time 11.74 seconds
Started Jul 11 04:28:16 PM PDT 24
Finished Jul 11 04:28:30 PM PDT 24
Peak memory 219204 kb
Host smart-bf89decd-49bc-4248-a952-e81df0494d90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1425256237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1425256237
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2444877341
Short name T218
Test name
Test status
Simulation time 1193371524 ps
CPU time 19.98 seconds
Started Jul 11 04:28:34 PM PDT 24
Finished Jul 11 04:28:56 PM PDT 24
Peak memory 216816 kb
Host smart-76e2b0ff-4723-47a3-9800-cb981e2b972d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444877341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2444877341
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.4247012826
Short name T200
Test name
Test status
Simulation time 30258820495 ps
CPU time 129.36 seconds
Started Jul 11 04:28:58 PM PDT 24
Finished Jul 11 04:31:10 PM PDT 24
Peak memory 219528 kb
Host smart-2b34fbde-e907-4dfe-8074-28864c68a60c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247012826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.4247012826
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1872332944
Short name T193
Test name
Test status
Simulation time 3586035665 ps
CPU time 29.63 seconds
Started Jul 11 04:28:49 PM PDT 24
Finished Jul 11 04:29:20 PM PDT 24
Peak memory 217168 kb
Host smart-af8ca6d3-17e3-4b3d-b2bd-80865d76bd9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872332944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1872332944
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2803959291
Short name T285
Test name
Test status
Simulation time 7464226848 ps
CPU time 114.74 seconds
Started Jul 11 04:28:32 PM PDT 24
Finished Jul 11 04:30:29 PM PDT 24
Peak memory 225084 kb
Host smart-13cc79bc-b404-449f-9119-440412ee3604
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803959291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2803959291
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1316267554
Short name T172
Test name
Test status
Simulation time 346182906 ps
CPU time 18.73 seconds
Started Jul 11 04:28:45 PM PDT 24
Finished Jul 11 04:29:05 PM PDT 24
Peak memory 219176 kb
Host smart-6fd28a84-6687-4d51-b685-226f695275fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316267554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1316267554
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.670711787
Short name T128
Test name
Test status
Simulation time 3770017817 ps
CPU time 12.56 seconds
Started Jul 11 04:28:36 PM PDT 24
Finished Jul 11 04:28:51 PM PDT 24
Peak memory 218884 kb
Host smart-0c4ce6fb-a96f-4023-b81c-355a097cfec4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=670711787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.670711787
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.43933912
Short name T215
Test name
Test status
Simulation time 7986719264 ps
CPU time 64.57 seconds
Started Jul 11 04:28:42 PM PDT 24
Finished Jul 11 04:29:48 PM PDT 24
Peak memory 216604 kb
Host smart-510e3f81-2518-487e-82cd-bb7594a1ef9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43933912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.43933912
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.29642000
Short name T239
Test name
Test status
Simulation time 2006453441 ps
CPU time 24.35 seconds
Started Jul 11 04:28:38 PM PDT 24
Finished Jul 11 04:29:04 PM PDT 24
Peak memory 214540 kb
Host smart-2ee5a7dd-9d16-4d8a-8797-c9dd1fe58287
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29642000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 8.rom_ctrl_stress_all.29642000
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3040770794
Short name T159
Test name
Test status
Simulation time 169357764 ps
CPU time 8.45 seconds
Started Jul 11 04:28:44 PM PDT 24
Finished Jul 11 04:28:53 PM PDT 24
Peak memory 213164 kb
Host smart-10766d5d-cd1e-48d3-a94b-1de8813ad540
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040770794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3040770794
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2310900550
Short name T52
Test name
Test status
Simulation time 122331733186 ps
CPU time 481.29 seconds
Started Jul 11 04:28:38 PM PDT 24
Finished Jul 11 04:36:40 PM PDT 24
Peak memory 219384 kb
Host smart-780719e2-fb55-4770-aa95-3d8038268654
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310900550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2310900550
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3205628132
Short name T213
Test name
Test status
Simulation time 395517369 ps
CPU time 19.48 seconds
Started Jul 11 04:28:35 PM PDT 24
Finished Jul 11 04:28:56 PM PDT 24
Peak memory 219208 kb
Host smart-938d0161-71c0-42e4-b930-8a6558347554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205628132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3205628132
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3809732600
Short name T173
Test name
Test status
Simulation time 4623474811 ps
CPU time 22.96 seconds
Started Jul 11 04:28:57 PM PDT 24
Finished Jul 11 04:29:22 PM PDT 24
Peak memory 217672 kb
Host smart-9c8c273b-534e-4998-92d8-675787ec9182
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3809732600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3809732600
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2900818394
Short name T78
Test name
Test status
Simulation time 13053079125 ps
CPU time 61.57 seconds
Started Jul 11 04:28:24 PM PDT 24
Finished Jul 11 04:29:28 PM PDT 24
Peak memory 217440 kb
Host smart-d90cda35-3a18-4971-a3e4-380f685cff01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900818394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2900818394
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2594034563
Short name T183
Test name
Test status
Simulation time 2646461886 ps
CPU time 31.83 seconds
Started Jul 11 04:29:23 PM PDT 24
Finished Jul 11 04:29:57 PM PDT 24
Peak memory 211676 kb
Host smart-0795ec7d-dc4f-4142-a371-6fdae645eb67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594034563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2594034563
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.3303018390
Short name T54
Test name
Test status
Simulation time 136287354742 ps
CPU time 1410.61 seconds
Started Jul 11 04:28:52 PM PDT 24
Finished Jul 11 04:52:24 PM PDT 24
Peak memory 243912 kb
Host smart-b3e8ffea-6242-41b7-9985-c2da99751fbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303018390 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.3303018390
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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