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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.29 96.89 91.99 97.68 100.00 98.62 97.45 98.37


Total test records in report: 456
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T305 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1659245853 Jul 12 04:35:06 PM PDT 24 Jul 12 04:35:46 PM PDT 24 11348003653 ps
T306 /workspace/coverage/default/44.rom_ctrl_stress_all.703765641 Jul 12 04:35:25 PM PDT 24 Jul 12 04:37:03 PM PDT 24 38980653923 ps
T307 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3292598794 Jul 12 04:34:48 PM PDT 24 Jul 12 04:35:28 PM PDT 24 23260671064 ps
T308 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2065112056 Jul 12 04:34:45 PM PDT 24 Jul 12 04:35:26 PM PDT 24 16450956318 ps
T309 /workspace/coverage/default/19.rom_ctrl_smoke.880014568 Jul 12 04:35:11 PM PDT 24 Jul 12 04:35:32 PM PDT 24 691813554 ps
T310 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.4268103663 Jul 12 04:35:30 PM PDT 24 Jul 12 04:36:09 PM PDT 24 1481274552 ps
T311 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2636216682 Jul 12 04:35:20 PM PDT 24 Jul 12 04:35:39 PM PDT 24 4867598110 ps
T312 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.324976321 Jul 12 04:35:13 PM PDT 24 Jul 12 04:39:19 PM PDT 24 6988046412 ps
T313 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.203182589 Jul 12 04:35:27 PM PDT 24 Jul 12 04:46:32 PM PDT 24 321741036690 ps
T314 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2009150805 Jul 12 04:35:20 PM PDT 24 Jul 12 04:36:27 PM PDT 24 20424595287 ps
T315 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.4090439196 Jul 12 04:35:15 PM PDT 24 Jul 12 04:35:32 PM PDT 24 748489950 ps
T316 /workspace/coverage/default/26.rom_ctrl_smoke.1164575542 Jul 12 04:35:21 PM PDT 24 Jul 12 04:35:48 PM PDT 24 2892546493 ps
T317 /workspace/coverage/default/23.rom_ctrl_smoke.3108232253 Jul 12 04:35:01 PM PDT 24 Jul 12 04:35:58 PM PDT 24 4849905524 ps
T318 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3706856025 Jul 12 04:35:30 PM PDT 24 Jul 12 04:36:07 PM PDT 24 2907344369 ps
T319 /workspace/coverage/default/36.rom_ctrl_stress_all.3387492607 Jul 12 04:35:27 PM PDT 24 Jul 12 04:37:51 PM PDT 24 62033355174 ps
T24 /workspace/coverage/default/0.rom_ctrl_sec_cm.1542296187 Jul 12 04:34:35 PM PDT 24 Jul 12 04:38:43 PM PDT 24 14874100171 ps
T320 /workspace/coverage/default/27.rom_ctrl_stress_all.3590707794 Jul 12 04:35:08 PM PDT 24 Jul 12 04:35:33 PM PDT 24 3183238012 ps
T321 /workspace/coverage/default/33.rom_ctrl_smoke.2814976019 Jul 12 04:35:29 PM PDT 24 Jul 12 04:36:17 PM PDT 24 2858899389 ps
T322 /workspace/coverage/default/41.rom_ctrl_alert_test.3127196841 Jul 12 04:35:18 PM PDT 24 Jul 12 04:35:44 PM PDT 24 5376442701 ps
T25 /workspace/coverage/default/1.rom_ctrl_sec_cm.3141062386 Jul 12 04:34:40 PM PDT 24 Jul 12 04:38:39 PM PDT 24 585015104 ps
T323 /workspace/coverage/default/22.rom_ctrl_smoke.4100770559 Jul 12 04:35:15 PM PDT 24 Jul 12 04:36:37 PM PDT 24 8208038503 ps
T324 /workspace/coverage/default/29.rom_ctrl_alert_test.1585947894 Jul 12 04:35:13 PM PDT 24 Jul 12 04:35:31 PM PDT 24 1246269107 ps
T325 /workspace/coverage/default/48.rom_ctrl_alert_test.3032849031 Jul 12 04:35:36 PM PDT 24 Jul 12 04:36:02 PM PDT 24 331399444 ps
T326 /workspace/coverage/default/18.rom_ctrl_smoke.1953460292 Jul 12 04:35:20 PM PDT 24 Jul 12 04:36:00 PM PDT 24 42289000301 ps
T327 /workspace/coverage/default/10.rom_ctrl_smoke.2597625001 Jul 12 04:34:56 PM PDT 24 Jul 12 04:36:21 PM PDT 24 17081636846 ps
T328 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2861946879 Jul 12 04:35:32 PM PDT 24 Jul 12 04:36:03 PM PDT 24 332326610 ps
T329 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2785834072 Jul 12 04:35:02 PM PDT 24 Jul 12 04:35:32 PM PDT 24 2289093742 ps
T330 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3056234953 Jul 12 04:34:45 PM PDT 24 Jul 12 04:41:17 PM PDT 24 15177378630 ps
T331 /workspace/coverage/default/38.rom_ctrl_stress_all.3144359200 Jul 12 04:35:29 PM PDT 24 Jul 12 04:36:12 PM PDT 24 526992101 ps
T332 /workspace/coverage/default/9.rom_ctrl_alert_test.2471724939 Jul 12 04:34:59 PM PDT 24 Jul 12 04:35:28 PM PDT 24 31114561777 ps
T333 /workspace/coverage/default/1.rom_ctrl_alert_test.2391311212 Jul 12 04:34:44 PM PDT 24 Jul 12 04:35:14 PM PDT 24 11469824591 ps
T334 /workspace/coverage/default/8.rom_ctrl_stress_all.3481508046 Jul 12 04:34:59 PM PDT 24 Jul 12 04:36:58 PM PDT 24 41209792522 ps
T335 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1069613960 Jul 12 04:35:08 PM PDT 24 Jul 12 04:35:29 PM PDT 24 3291304933 ps
T336 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.654860285 Jul 12 04:35:26 PM PDT 24 Jul 12 04:35:58 PM PDT 24 12482119272 ps
T337 /workspace/coverage/default/17.rom_ctrl_alert_test.2580360367 Jul 12 04:35:04 PM PDT 24 Jul 12 04:35:14 PM PDT 24 635259675 ps
T338 /workspace/coverage/default/5.rom_ctrl_smoke.1526650723 Jul 12 04:34:47 PM PDT 24 Jul 12 04:35:40 PM PDT 24 11212351298 ps
T339 /workspace/coverage/default/21.rom_ctrl_alert_test.373757820 Jul 12 04:34:59 PM PDT 24 Jul 12 04:35:14 PM PDT 24 3292181252 ps
T340 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1299271459 Jul 12 04:35:25 PM PDT 24 Jul 12 04:35:54 PM PDT 24 4115590933 ps
T341 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2688608014 Jul 12 04:35:39 PM PDT 24 Jul 12 04:36:17 PM PDT 24 3928781711 ps
T342 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.4199215504 Jul 12 04:35:02 PM PDT 24 Jul 12 04:36:05 PM PDT 24 27303543417 ps
T343 /workspace/coverage/default/49.rom_ctrl_stress_all.715911935 Jul 12 04:35:38 PM PDT 24 Jul 12 04:36:43 PM PDT 24 5633745344 ps
T344 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2149778715 Jul 12 04:35:17 PM PDT 24 Jul 12 04:36:09 PM PDT 24 5266163172 ps
T345 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.244690476 Jul 12 04:34:48 PM PDT 24 Jul 12 04:35:52 PM PDT 24 8769913208 ps
T346 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3702414664 Jul 12 04:34:37 PM PDT 24 Jul 12 04:35:09 PM PDT 24 2580638815 ps
T347 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1313492118 Jul 12 04:34:41 PM PDT 24 Jul 12 04:44:41 PM PDT 24 53277468612 ps
T348 /workspace/coverage/default/32.rom_ctrl_stress_all.258713662 Jul 12 04:35:25 PM PDT 24 Jul 12 04:35:40 PM PDT 24 210431299 ps
T349 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.833208568 Jul 12 04:34:59 PM PDT 24 Jul 12 04:35:28 PM PDT 24 2911718209 ps
T350 /workspace/coverage/default/45.rom_ctrl_smoke.1755625105 Jul 12 04:35:31 PM PDT 24 Jul 12 04:36:46 PM PDT 24 7221089094 ps
T351 /workspace/coverage/default/0.rom_ctrl_alert_test.2280181431 Jul 12 04:34:41 PM PDT 24 Jul 12 04:35:07 PM PDT 24 2209129785 ps
T352 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2336774678 Jul 12 04:35:31 PM PDT 24 Jul 12 04:36:00 PM PDT 24 661338824 ps
T353 /workspace/coverage/default/36.rom_ctrl_alert_test.1221190100 Jul 12 04:35:27 PM PDT 24 Jul 12 04:35:51 PM PDT 24 11254591542 ps
T354 /workspace/coverage/default/24.rom_ctrl_smoke.536446633 Jul 12 04:35:02 PM PDT 24 Jul 12 04:35:55 PM PDT 24 4033885370 ps
T355 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.159444447 Jul 12 04:35:29 PM PDT 24 Jul 12 04:41:21 PM PDT 24 20098284937 ps
T356 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1329870726 Jul 12 04:36:16 PM PDT 24 Jul 12 04:42:09 PM PDT 24 12663083438 ps
T357 /workspace/coverage/default/35.rom_ctrl_smoke.1010393185 Jul 12 04:35:30 PM PDT 24 Jul 12 04:36:42 PM PDT 24 29320737809 ps
T358 /workspace/coverage/default/14.rom_ctrl_smoke.442434043 Jul 12 04:34:59 PM PDT 24 Jul 12 04:36:03 PM PDT 24 7399684909 ps
T359 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1430844122 Jul 12 04:34:58 PM PDT 24 Jul 12 04:48:11 PM PDT 24 278275638021 ps
T54 /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1330980846 Jul 12 04:35:30 PM PDT 24 Jul 12 05:08:37 PM PDT 24 254774281053 ps
T360 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1890444271 Jul 12 04:34:37 PM PDT 24 Jul 12 04:35:22 PM PDT 24 6248990568 ps
T361 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1451293163 Jul 12 04:35:25 PM PDT 24 Jul 12 04:41:20 PM PDT 24 232994377700 ps
T362 /workspace/coverage/default/18.rom_ctrl_alert_test.759604619 Jul 12 04:35:11 PM PDT 24 Jul 12 04:35:30 PM PDT 24 1479381248 ps
T55 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1686882923 Jul 12 04:35:50 PM PDT 24 Jul 12 04:36:33 PM PDT 24 3369150724 ps
T60 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.499167122 Jul 12 04:36:00 PM PDT 24 Jul 12 04:38:33 PM PDT 24 15467110453 ps
T363 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3402237525 Jul 12 04:35:45 PM PDT 24 Jul 12 04:36:29 PM PDT 24 3279468139 ps
T61 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.35612417 Jul 12 04:36:20 PM PDT 24 Jul 12 04:36:55 PM PDT 24 3939764765 ps
T56 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3948665741 Jul 12 04:36:15 PM PDT 24 Jul 12 04:36:47 PM PDT 24 3727934079 ps
T103 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1455835559 Jul 12 04:36:23 PM PDT 24 Jul 12 04:36:35 PM PDT 24 174680837 ps
T98 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2661446920 Jul 12 04:35:43 PM PDT 24 Jul 12 04:36:26 PM PDT 24 2911345709 ps
T99 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.204430565 Jul 12 04:36:21 PM PDT 24 Jul 12 04:36:45 PM PDT 24 21502857936 ps
T57 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.170670907 Jul 12 04:35:40 PM PDT 24 Jul 12 04:37:17 PM PDT 24 240656148 ps
T104 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1751522255 Jul 12 04:36:16 PM PDT 24 Jul 12 04:36:52 PM PDT 24 11406258459 ps
T67 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1812669831 Jul 12 04:35:32 PM PDT 24 Jul 12 04:35:56 PM PDT 24 4124984561 ps
T70 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.4166069161 Jul 12 04:36:14 PM PDT 24 Jul 12 04:38:02 PM PDT 24 11516414346 ps
T68 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3803916272 Jul 12 04:36:31 PM PDT 24 Jul 12 04:37:01 PM PDT 24 10636763386 ps
T58 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3850371515 Jul 12 04:36:30 PM PDT 24 Jul 12 04:39:17 PM PDT 24 2031963918 ps
T364 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4128644910 Jul 12 04:35:50 PM PDT 24 Jul 12 04:36:38 PM PDT 24 15948649646 ps
T71 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1984632238 Jul 12 04:36:20 PM PDT 24 Jul 12 04:39:48 PM PDT 24 35468360460 ps
T365 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.233507516 Jul 12 04:35:43 PM PDT 24 Jul 12 04:36:09 PM PDT 24 176294914 ps
T72 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.711865859 Jul 12 04:35:36 PM PDT 24 Jul 12 04:36:02 PM PDT 24 603025330 ps
T73 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1594267137 Jul 12 04:36:06 PM PDT 24 Jul 12 04:36:22 PM PDT 24 167447206 ps
T74 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3682284944 Jul 12 04:35:58 PM PDT 24 Jul 12 04:36:43 PM PDT 24 16119751606 ps
T366 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2231482166 Jul 12 04:36:36 PM PDT 24 Jul 12 04:37:11 PM PDT 24 16777967890 ps
T367 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3206871289 Jul 12 04:35:43 PM PDT 24 Jul 12 04:36:29 PM PDT 24 3673610398 ps
T368 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3018779428 Jul 12 04:36:22 PM PDT 24 Jul 12 04:36:35 PM PDT 24 364323132 ps
T75 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.50860987 Jul 12 04:35:57 PM PDT 24 Jul 12 04:36:26 PM PDT 24 4098962480 ps
T76 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.893885862 Jul 12 04:36:12 PM PDT 24 Jul 12 04:36:51 PM PDT 24 3504306798 ps
T369 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3069613801 Jul 12 04:35:57 PM PDT 24 Jul 12 04:36:35 PM PDT 24 7585811996 ps
T370 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2956879086 Jul 12 04:35:43 PM PDT 24 Jul 12 04:36:09 PM PDT 24 1650943037 ps
T371 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3531212288 Jul 12 04:35:51 PM PDT 24 Jul 12 04:36:21 PM PDT 24 331582458 ps
T77 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1117939399 Jul 12 04:36:30 PM PDT 24 Jul 12 04:37:29 PM PDT 24 4131338794 ps
T78 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.507606111 Jul 12 04:35:36 PM PDT 24 Jul 12 04:35:59 PM PDT 24 825253720 ps
T85 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2104058125 Jul 12 04:35:34 PM PDT 24 Jul 12 04:38:06 PM PDT 24 13567473390 ps
T372 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.269971569 Jul 12 04:35:32 PM PDT 24 Jul 12 04:36:07 PM PDT 24 2822085936 ps
T373 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3804600741 Jul 12 04:36:29 PM PDT 24 Jul 12 04:36:39 PM PDT 24 172639209 ps
T374 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2130391255 Jul 12 04:35:58 PM PDT 24 Jul 12 04:36:32 PM PDT 24 2844975205 ps
T86 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1033686637 Jul 12 04:36:30 PM PDT 24 Jul 12 04:36:43 PM PDT 24 673219319 ps
T375 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2356894652 Jul 12 04:36:35 PM PDT 24 Jul 12 04:37:05 PM PDT 24 3240588941 ps
T376 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2853084382 Jul 12 04:35:34 PM PDT 24 Jul 12 04:36:05 PM PDT 24 859007004 ps
T377 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2771218268 Jul 12 04:36:01 PM PDT 24 Jul 12 04:36:39 PM PDT 24 12325079991 ps
T100 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.485546990 Jul 12 04:36:22 PM PDT 24 Jul 12 04:36:42 PM PDT 24 894668822 ps
T378 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3947417800 Jul 12 04:35:47 PM PDT 24 Jul 12 04:36:38 PM PDT 24 4812468934 ps
T59 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4243392611 Jul 12 04:36:09 PM PDT 24 Jul 12 04:38:00 PM PDT 24 4364769043 ps
T110 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.651438626 Jul 12 04:35:34 PM PDT 24 Jul 12 04:38:44 PM PDT 24 18460834246 ps
T111 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3297168668 Jul 12 04:36:27 PM PDT 24 Jul 12 04:39:12 PM PDT 24 2118182180 ps
T88 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1648579055 Jul 12 04:35:32 PM PDT 24 Jul 12 04:37:01 PM PDT 24 3669041487 ps
T87 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2486279130 Jul 12 04:35:34 PM PDT 24 Jul 12 04:36:20 PM PDT 24 4114488213 ps
T89 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.161504026 Jul 12 04:35:42 PM PDT 24 Jul 12 04:36:25 PM PDT 24 15007370229 ps
T379 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1484533495 Jul 12 04:35:47 PM PDT 24 Jul 12 04:39:01 PM PDT 24 21234675115 ps
T101 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.4041040099 Jul 12 04:36:02 PM PDT 24 Jul 12 04:36:31 PM PDT 24 3358816090 ps
T109 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4042637549 Jul 12 04:36:12 PM PDT 24 Jul 12 04:36:56 PM PDT 24 3118260128 ps
T114 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.4190085888 Jul 12 04:36:13 PM PDT 24 Jul 12 04:38:01 PM PDT 24 3998175501 ps
T102 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1602749428 Jul 12 04:35:55 PM PDT 24 Jul 12 04:36:16 PM PDT 24 244911245 ps
T90 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3291162893 Jul 12 04:35:53 PM PDT 24 Jul 12 04:36:15 PM PDT 24 325678317 ps
T380 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2457725295 Jul 12 04:36:31 PM PDT 24 Jul 12 04:36:49 PM PDT 24 1131450385 ps
T117 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1139666441 Jul 12 04:36:36 PM PDT 24 Jul 12 04:39:19 PM PDT 24 4963239768 ps
T118 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2630115260 Jul 12 04:36:31 PM PDT 24 Jul 12 04:39:22 PM PDT 24 6334118147 ps
T381 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2250134202 Jul 12 04:36:08 PM PDT 24 Jul 12 04:36:50 PM PDT 24 6835031109 ps
T382 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2806436098 Jul 12 04:35:50 PM PDT 24 Jul 12 04:36:17 PM PDT 24 661265338 ps
T112 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.438971630 Jul 12 04:36:01 PM PDT 24 Jul 12 04:38:50 PM PDT 24 1361019542 ps
T383 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2228633253 Jul 12 04:36:38 PM PDT 24 Jul 12 04:36:59 PM PDT 24 5803130427 ps
T384 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.812796251 Jul 12 04:36:08 PM PDT 24 Jul 12 04:36:51 PM PDT 24 66558932712 ps
T385 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3702478163 Jul 12 04:36:11 PM PDT 24 Jul 12 04:36:26 PM PDT 24 169460253 ps
T386 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2458456530 Jul 12 04:36:29 PM PDT 24 Jul 12 04:37:00 PM PDT 24 13369096422 ps
T387 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2057148941 Jul 12 04:36:21 PM PDT 24 Jul 12 04:36:44 PM PDT 24 4192132231 ps
T115 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3032508470 Jul 12 04:36:21 PM PDT 24 Jul 12 04:39:14 PM PDT 24 7773251449 ps
T91 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3056256993 Jul 12 04:35:33 PM PDT 24 Jul 12 04:36:11 PM PDT 24 6778760143 ps
T388 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1439052724 Jul 12 04:36:12 PM PDT 24 Jul 12 04:36:31 PM PDT 24 662080179 ps
T92 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1963331482 Jul 12 04:36:36 PM PDT 24 Jul 12 04:38:22 PM PDT 24 11022095816 ps
T389 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2784453821 Jul 12 04:35:40 PM PDT 24 Jul 12 04:36:20 PM PDT 24 1874397774 ps
T390 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.228075323 Jul 12 04:35:51 PM PDT 24 Jul 12 04:36:33 PM PDT 24 8198960264 ps
T95 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2471909549 Jul 12 04:35:52 PM PDT 24 Jul 12 04:36:25 PM PDT 24 37785347386 ps
T391 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2783256437 Jul 12 04:36:45 PM PDT 24 Jul 12 04:37:19 PM PDT 24 3288826615 ps
T96 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3242072686 Jul 12 04:35:58 PM PDT 24 Jul 12 04:38:17 PM PDT 24 62829062862 ps
T392 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.876060571 Jul 12 04:36:13 PM PDT 24 Jul 12 04:36:26 PM PDT 24 1831414602 ps
T393 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2791778651 Jul 12 04:36:30 PM PDT 24 Jul 12 04:36:58 PM PDT 24 2013835720 ps
T394 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1659344473 Jul 12 04:35:58 PM PDT 24 Jul 12 04:36:39 PM PDT 24 7194431251 ps
T93 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2784926190 Jul 12 04:36:20 PM PDT 24 Jul 12 04:36:55 PM PDT 24 8381175134 ps
T395 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1368154007 Jul 12 04:35:38 PM PDT 24 Jul 12 04:36:20 PM PDT 24 8269812323 ps
T396 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3413627083 Jul 12 04:35:43 PM PDT 24 Jul 12 04:36:32 PM PDT 24 31023606265 ps
T119 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3630464911 Jul 12 04:35:59 PM PDT 24 Jul 12 04:37:51 PM PDT 24 7159497044 ps
T397 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3104778674 Jul 12 04:36:32 PM PDT 24 Jul 12 04:36:57 PM PDT 24 4811761116 ps
T398 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3702930360 Jul 12 04:36:19 PM PDT 24 Jul 12 04:36:38 PM PDT 24 2740950099 ps
T120 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1805321276 Jul 12 04:35:46 PM PDT 24 Jul 12 04:37:36 PM PDT 24 25582659514 ps
T399 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2380504021 Jul 12 04:36:34 PM PDT 24 Jul 12 04:36:51 PM PDT 24 1024242374 ps
T400 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1912105163 Jul 12 04:35:59 PM PDT 24 Jul 12 04:36:28 PM PDT 24 2958929277 ps
T401 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1670853653 Jul 12 04:36:06 PM PDT 24 Jul 12 04:36:48 PM PDT 24 8376500252 ps
T402 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.299495900 Jul 12 04:35:56 PM PDT 24 Jul 12 04:36:22 PM PDT 24 822146797 ps
T403 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2768423515 Jul 12 04:36:36 PM PDT 24 Jul 12 04:37:14 PM PDT 24 4283770470 ps
T404 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3654152878 Jul 12 04:35:34 PM PDT 24 Jul 12 04:36:38 PM PDT 24 2106273446 ps
T405 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1570612823 Jul 12 04:36:07 PM PDT 24 Jul 12 04:36:24 PM PDT 24 184034933 ps
T116 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1434771794 Jul 12 04:36:13 PM PDT 24 Jul 12 04:39:08 PM PDT 24 8042667706 ps
T406 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2771673780 Jul 12 04:35:35 PM PDT 24 Jul 12 04:36:19 PM PDT 24 3734275566 ps
T407 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2189909387 Jul 12 04:36:07 PM PDT 24 Jul 12 04:36:39 PM PDT 24 12015540956 ps
T408 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2571998712 Jul 12 04:36:22 PM PDT 24 Jul 12 04:39:16 PM PDT 24 7248102311 ps
T409 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3374292375 Jul 12 04:35:36 PM PDT 24 Jul 12 04:36:05 PM PDT 24 986269307 ps
T410 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3008657260 Jul 12 04:36:01 PM PDT 24 Jul 12 04:38:09 PM PDT 24 27375044901 ps
T411 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1561041461 Jul 12 04:35:52 PM PDT 24 Jul 12 04:36:27 PM PDT 24 8547338743 ps
T412 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3590613347 Jul 12 04:36:30 PM PDT 24 Jul 12 04:36:57 PM PDT 24 11894571793 ps
T413 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3894873685 Jul 12 04:36:10 PM PDT 24 Jul 12 04:36:54 PM PDT 24 1504492595 ps
T414 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1236682537 Jul 12 04:36:01 PM PDT 24 Jul 12 04:36:40 PM PDT 24 9340500658 ps
T415 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2696652861 Jul 12 04:36:06 PM PDT 24 Jul 12 04:37:37 PM PDT 24 3743744013 ps
T416 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3103008669 Jul 12 04:36:18 PM PDT 24 Jul 12 04:36:56 PM PDT 24 14585041223 ps
T417 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.600318839 Jul 12 04:35:33 PM PDT 24 Jul 12 04:36:08 PM PDT 24 33953775870 ps
T418 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.756812282 Jul 12 04:35:58 PM PDT 24 Jul 12 04:38:08 PM PDT 24 15314656630 ps
T121 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2692275301 Jul 12 04:35:44 PM PDT 24 Jul 12 04:38:48 PM PDT 24 2879369489 ps
T419 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3850413457 Jul 12 04:35:33 PM PDT 24 Jul 12 04:38:21 PM PDT 24 826758111 ps
T420 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.4206270344 Jul 12 04:36:31 PM PDT 24 Jul 12 04:37:56 PM PDT 24 469775537 ps
T421 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4104533679 Jul 12 04:36:14 PM PDT 24 Jul 12 04:36:36 PM PDT 24 601658305 ps
T422 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3107320861 Jul 12 04:36:12 PM PDT 24 Jul 12 04:36:42 PM PDT 24 5867095956 ps
T423 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1829205223 Jul 12 04:35:46 PM PDT 24 Jul 12 04:36:37 PM PDT 24 4135537831 ps
T424 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1114743615 Jul 12 04:36:20 PM PDT 24 Jul 12 04:37:46 PM PDT 24 300328374 ps
T425 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.283380458 Jul 12 04:36:30 PM PDT 24 Jul 12 04:36:53 PM PDT 24 4639613104 ps
T426 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.4161874635 Jul 12 04:35:49 PM PDT 24 Jul 12 04:36:27 PM PDT 24 1966552511 ps
T94 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3707541853 Jul 12 04:36:20 PM PDT 24 Jul 12 04:38:39 PM PDT 24 55686692729 ps
T427 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2534249603 Jul 12 04:36:20 PM PDT 24 Jul 12 04:36:47 PM PDT 24 3015150957 ps
T428 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1823746578 Jul 12 04:36:30 PM PDT 24 Jul 12 04:37:05 PM PDT 24 4015372799 ps
T429 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3928043916 Jul 12 04:35:49 PM PDT 24 Jul 12 04:37:27 PM PDT 24 7182333029 ps
T430 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1666810825 Jul 12 04:36:35 PM PDT 24 Jul 12 04:36:54 PM PDT 24 19213777537 ps
T431 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2337244305 Jul 12 04:35:44 PM PDT 24 Jul 12 04:36:30 PM PDT 24 14484615052 ps
T432 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.546456360 Jul 12 04:36:03 PM PDT 24 Jul 12 04:36:32 PM PDT 24 18012130003 ps
T433 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4263613968 Jul 12 04:37:56 PM PDT 24 Jul 12 04:39:48 PM PDT 24 38399876424 ps
T434 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.933809595 Jul 12 04:36:30 PM PDT 24 Jul 12 04:36:59 PM PDT 24 11983262851 ps
T435 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3172621415 Jul 12 04:36:04 PM PDT 24 Jul 12 04:37:42 PM PDT 24 30572071997 ps
T436 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.936824317 Jul 12 04:35:30 PM PDT 24 Jul 12 04:35:49 PM PDT 24 661385142 ps
T437 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1151794233 Jul 12 04:35:31 PM PDT 24 Jul 12 04:35:56 PM PDT 24 2059637707 ps
T438 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2240732831 Jul 12 04:36:03 PM PDT 24 Jul 12 04:36:21 PM PDT 24 169433699 ps
T439 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2322885266 Jul 12 04:36:04 PM PDT 24 Jul 12 04:36:37 PM PDT 24 6227149545 ps
T113 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.16782249 Jul 12 04:36:02 PM PDT 24 Jul 12 04:37:42 PM PDT 24 1328015677 ps
T440 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.991491726 Jul 12 04:36:33 PM PDT 24 Jul 12 04:37:07 PM PDT 24 14263818363 ps
T441 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3397788488 Jul 12 04:36:23 PM PDT 24 Jul 12 04:36:35 PM PDT 24 546959138 ps
T442 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.79693353 Jul 12 04:35:53 PM PDT 24 Jul 12 04:36:23 PM PDT 24 4526380720 ps
T443 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3797561734 Jul 12 04:35:56 PM PDT 24 Jul 12 04:36:31 PM PDT 24 1608151565 ps
T444 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2453984383 Jul 12 04:35:45 PM PDT 24 Jul 12 04:36:31 PM PDT 24 3703687308 ps
T445 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3837008173 Jul 12 04:35:46 PM PDT 24 Jul 12 04:36:30 PM PDT 24 12733620267 ps
T446 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1295836202 Jul 12 04:36:01 PM PDT 24 Jul 12 04:36:37 PM PDT 24 24604900919 ps
T447 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2263617330 Jul 12 04:35:43 PM PDT 24 Jul 12 04:36:08 PM PDT 24 339017534 ps
T448 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3518178672 Jul 12 04:36:14 PM PDT 24 Jul 12 04:36:27 PM PDT 24 751487390 ps
T449 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3758023043 Jul 12 04:35:48 PM PDT 24 Jul 12 04:36:29 PM PDT 24 12282639729 ps
T450 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2085334430 Jul 12 04:35:49 PM PDT 24 Jul 12 04:36:34 PM PDT 24 3758214336 ps
T451 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2215653211 Jul 12 04:36:31 PM PDT 24 Jul 12 04:38:39 PM PDT 24 15651222537 ps
T452 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3132541246 Jul 12 04:36:19 PM PDT 24 Jul 12 04:36:52 PM PDT 24 65717999242 ps
T453 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.672051479 Jul 12 04:35:29 PM PDT 24 Jul 12 04:36:16 PM PDT 24 8744852030 ps
T454 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.4060981602 Jul 12 04:36:02 PM PDT 24 Jul 12 04:36:20 PM PDT 24 660765758 ps
T455 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2540374550 Jul 12 04:36:05 PM PDT 24 Jul 12 04:36:27 PM PDT 24 669956152 ps
T456 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.910333293 Jul 12 04:36:28 PM PDT 24 Jul 12 04:36:44 PM PDT 24 1679042361 ps
T97 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.4205993567 Jul 12 04:36:32 PM PDT 24 Jul 12 04:37:51 PM PDT 24 12504286947 ps

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3187139700
Short name T7
Test name
Test status
Simulation time 107282807968 ps
CPU time 2037.77 seconds
Started Jul 12 04:35:21 PM PDT 24
Finished Jul 12 05:09:21 PM PDT 24
Peak memory 249248 kb
Host smart-a7aba2b2-6f1f-4272-a143-2e3ea03c33d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187139700 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.3187139700
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1573379608
Short name T6
Test name
Test status
Simulation time 209918736390 ps
CPU time 550.65 seconds
Started Jul 12 04:35:04 PM PDT 24
Finished Jul 12 04:44:16 PM PDT 24
Peak memory 240692 kb
Host smart-4369c143-24b0-43c2-8944-4de6c85ba457
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573379608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1573379608
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3056234953
Short name T330
Test name
Test status
Simulation time 15177378630 ps
CPU time 387.56 seconds
Started Jul 12 04:34:45 PM PDT 24
Finished Jul 12 04:41:17 PM PDT 24
Peak memory 224304 kb
Host smart-253e835a-698c-4f35-b936-1d4b4aa54ce1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056234953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3056234953
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3850371515
Short name T58
Test name
Test status
Simulation time 2031963918 ps
CPU time 163.58 seconds
Started Jul 12 04:36:30 PM PDT 24
Finished Jul 12 04:39:17 PM PDT 24
Peak memory 214132 kb
Host smart-6d2e9137-0a5c-4fab-84e2-e33edbb94f81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850371515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3850371515
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.2603166397
Short name T51
Test name
Test status
Simulation time 15028544383 ps
CPU time 540.46 seconds
Started Jul 12 04:35:01 PM PDT 24
Finished Jul 12 04:44:04 PM PDT 24
Peak memory 235708 kb
Host smart-e3f66558-d736-42c5-94af-72fc748c3396
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603166397 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.2603166397
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3974104307
Short name T17
Test name
Test status
Simulation time 21989120334 ps
CPU time 246.12 seconds
Started Jul 12 04:34:44 PM PDT 24
Finished Jul 12 04:38:55 PM PDT 24
Peak memory 236060 kb
Host smart-562174ef-c346-46bf-a8d8-25f723f2ef5a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974104307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3974104307
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2468771148
Short name T11
Test name
Test status
Simulation time 9904718024 ps
CPU time 24.52 seconds
Started Jul 12 04:35:23 PM PDT 24
Finished Jul 12 04:35:49 PM PDT 24
Peak memory 219256 kb
Host smart-864a8dff-c9d0-4a9b-ab58-6f35e3de4cd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2468771148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2468771148
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.711865859
Short name T72
Test name
Test status
Simulation time 603025330 ps
CPU time 11.52 seconds
Started Jul 12 04:35:36 PM PDT 24
Finished Jul 12 04:36:02 PM PDT 24
Peak memory 210632 kb
Host smart-7b56cada-8fe0-4eca-974a-cd9ae80aae58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711865859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.711865859
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3810894368
Short name T63
Test name
Test status
Simulation time 174194770 ps
CPU time 8.11 seconds
Started Jul 12 04:35:20 PM PDT 24
Finished Jul 12 04:35:30 PM PDT 24
Peak memory 217112 kb
Host smart-b0f66eb1-1b18-4216-9245-1d7b63b955b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810894368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3810894368
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.170670907
Short name T57
Test name
Test status
Simulation time 240656148 ps
CPU time 80.58 seconds
Started Jul 12 04:35:40 PM PDT 24
Finished Jul 12 04:37:17 PM PDT 24
Peak memory 212268 kb
Host smart-d69d5a03-b40a-43e2-a983-85e8d126ed37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170670907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.170670907
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3836937977
Short name T136
Test name
Test status
Simulation time 18352929194 ps
CPU time 47.37 seconds
Started Jul 12 04:35:30 PM PDT 24
Finished Jul 12 04:36:27 PM PDT 24
Peak memory 219232 kb
Host smart-44a07d25-d25b-4ce6-a43b-670a1e91423f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836937977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3836937977
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.907219184
Short name T212
Test name
Test status
Simulation time 661135856 ps
CPU time 19.38 seconds
Started Jul 12 04:34:54 PM PDT 24
Finished Jul 12 04:35:15 PM PDT 24
Peak memory 219216 kb
Host smart-b5013221-a16e-424d-8c47-35c29613baf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907219184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.907219184
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.4108520346
Short name T47
Test name
Test status
Simulation time 8694583740 ps
CPU time 67.53 seconds
Started Jul 12 04:35:29 PM PDT 24
Finished Jul 12 04:36:45 PM PDT 24
Peak memory 218820 kb
Host smart-17a84dc1-fa51-4d2a-8e05-68cf0d60d970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108520346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.4108520346
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3850413457
Short name T419
Test name
Test status
Simulation time 826758111 ps
CPU time 155.04 seconds
Started Jul 12 04:35:33 PM PDT 24
Finished Jul 12 04:38:21 PM PDT 24
Peak memory 214032 kb
Host smart-9142b42b-0b02-4027-9f3d-9d29fff8648f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850413457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3850413457
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.438971630
Short name T112
Test name
Test status
Simulation time 1361019542 ps
CPU time 158.63 seconds
Started Jul 12 04:36:01 PM PDT 24
Finished Jul 12 04:38:50 PM PDT 24
Peak memory 218816 kb
Host smart-b0badaa8-cf47-4241-9fcd-61302b913362
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438971630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.438971630
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3991089091
Short name T35
Test name
Test status
Simulation time 80209910293 ps
CPU time 866.23 seconds
Started Jul 12 04:35:04 PM PDT 24
Finished Jul 12 04:49:32 PM PDT 24
Peak memory 225708 kb
Host smart-c736d684-1104-4c56-af13-111c38251789
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991089091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3991089091
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3894873685
Short name T413
Test name
Test status
Simulation time 1504492595 ps
CPU time 37.63 seconds
Started Jul 12 04:36:10 PM PDT 24
Finished Jul 12 04:36:54 PM PDT 24
Peak memory 211676 kb
Host smart-9df86b58-149e-416c-adc2-c73a40a347c4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894873685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3894873685
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.554691390
Short name T30
Test name
Test status
Simulation time 355030245 ps
CPU time 20.95 seconds
Started Jul 12 04:34:55 PM PDT 24
Finished Jul 12 04:35:17 PM PDT 24
Peak memory 216304 kb
Host smart-da5b2ae0-cbbf-4343-8967-1d33293b1cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554691390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.554691390
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.507606111
Short name T78
Test name
Test status
Simulation time 825253720 ps
CPU time 8.02 seconds
Started Jul 12 04:35:36 PM PDT 24
Finished Jul 12 04:35:59 PM PDT 24
Peak memory 210556 kb
Host smart-e625c824-5e8e-4955-bddf-85dadaaba333
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507606111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.507606111
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2956879086
Short name T370
Test name
Test status
Simulation time 1650943037 ps
CPU time 8.69 seconds
Started Jul 12 04:35:43 PM PDT 24
Finished Jul 12 04:36:09 PM PDT 24
Peak memory 210512 kb
Host smart-5ff916b2-bcad-4bc4-b8b7-8a954ac719d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956879086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2956879086
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2784453821
Short name T389
Test name
Test status
Simulation time 1874397774 ps
CPU time 24.52 seconds
Started Jul 12 04:35:40 PM PDT 24
Finished Jul 12 04:36:20 PM PDT 24
Peak memory 211492 kb
Host smart-ff1e872e-fd7e-4da2-8381-f11bb9f6a45b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784453821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2784453821
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1812669831
Short name T67
Test name
Test status
Simulation time 4124984561 ps
CPU time 11.42 seconds
Started Jul 12 04:35:32 PM PDT 24
Finished Jul 12 04:35:56 PM PDT 24
Peak memory 213952 kb
Host smart-703750ee-c3f0-44db-844f-77c27446d31a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812669831 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1812669831
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2486279130
Short name T87
Test name
Test status
Simulation time 4114488213 ps
CPU time 32 seconds
Started Jul 12 04:35:34 PM PDT 24
Finished Jul 12 04:36:20 PM PDT 24
Peak memory 211756 kb
Host smart-7a7a1e6d-e208-438b-a5d6-bc34a68ffdd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486279130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2486279130
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.936824317
Short name T436
Test name
Test status
Simulation time 661385142 ps
CPU time 8.25 seconds
Started Jul 12 04:35:30 PM PDT 24
Finished Jul 12 04:35:49 PM PDT 24
Peak memory 210440 kb
Host smart-40fe7ad6-7019-49fd-92e4-69acd6dde8fa
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936824317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.936824317
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.600318839
Short name T417
Test name
Test status
Simulation time 33953775870 ps
CPU time 21.68 seconds
Started Jul 12 04:35:33 PM PDT 24
Finished Jul 12 04:36:08 PM PDT 24
Peak memory 210748 kb
Host smart-a7055131-2048-47ca-9f2f-0a1a220907c7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600318839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
600318839
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1648579055
Short name T88
Test name
Test status
Simulation time 3669041487 ps
CPU time 77.2 seconds
Started Jul 12 04:35:32 PM PDT 24
Finished Jul 12 04:37:01 PM PDT 24
Peak memory 215132 kb
Host smart-e097863e-f694-411f-aba2-bce15638772d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648579055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1648579055
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3374292375
Short name T409
Test name
Test status
Simulation time 986269307 ps
CPU time 14.75 seconds
Started Jul 12 04:35:36 PM PDT 24
Finished Jul 12 04:36:05 PM PDT 24
Peak memory 210912 kb
Host smart-bba1f627-6dee-4b12-bcbd-3ed36f590793
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374292375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3374292375
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1151794233
Short name T437
Test name
Test status
Simulation time 2059637707 ps
CPU time 12.61 seconds
Started Jul 12 04:35:31 PM PDT 24
Finished Jul 12 04:35:56 PM PDT 24
Peak memory 217000 kb
Host smart-d883913e-bba1-4bf1-bacd-264e7b9888f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151794233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1151794233
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.161504026
Short name T89
Test name
Test status
Simulation time 15007370229 ps
CPU time 25.67 seconds
Started Jul 12 04:35:42 PM PDT 24
Finished Jul 12 04:36:25 PM PDT 24
Peak memory 211856 kb
Host smart-3b8e45cd-d979-4fb8-901a-e19b54c04853
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161504026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.161504026
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3758023043
Short name T449
Test name
Test status
Simulation time 12282639729 ps
CPU time 26.21 seconds
Started Jul 12 04:35:48 PM PDT 24
Finished Jul 12 04:36:29 PM PDT 24
Peak memory 211276 kb
Host smart-85aa5c71-6c8a-4cbd-abef-43bad4fcce0c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758023043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3758023043
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.672051479
Short name T453
Test name
Test status
Simulation time 8744852030 ps
CPU time 36.34 seconds
Started Jul 12 04:35:29 PM PDT 24
Finished Jul 12 04:36:16 PM PDT 24
Peak memory 211988 kb
Host smart-38c39960-9ba3-4d3c-9834-c08881296e4c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672051479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.672051479
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2453984383
Short name T444
Test name
Test status
Simulation time 3703687308 ps
CPU time 29.88 seconds
Started Jul 12 04:35:45 PM PDT 24
Finished Jul 12 04:36:31 PM PDT 24
Peak memory 217992 kb
Host smart-20d70101-8a41-4260-8d2b-ad1037e190ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453984383 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2453984383
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3056256993
Short name T91
Test name
Test status
Simulation time 6778760143 ps
CPU time 26.67 seconds
Started Jul 12 04:35:33 PM PDT 24
Finished Jul 12 04:36:11 PM PDT 24
Peak memory 211948 kb
Host smart-aa7b0f40-6685-4c58-ac84-492eb6b11613
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056256993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3056256993
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.269971569
Short name T372
Test name
Test status
Simulation time 2822085936 ps
CPU time 23.53 seconds
Started Jul 12 04:35:32 PM PDT 24
Finished Jul 12 04:36:07 PM PDT 24
Peak memory 210464 kb
Host smart-c4cf260d-0936-4af3-87a5-e6259b9f5226
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269971569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.269971569
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2771673780
Short name T406
Test name
Test status
Simulation time 3734275566 ps
CPU time 29.09 seconds
Started Jul 12 04:35:35 PM PDT 24
Finished Jul 12 04:36:19 PM PDT 24
Peak memory 210524 kb
Host smart-080c5fd7-aa14-4602-af49-a747392b32df
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771673780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2771673780
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2104058125
Short name T85
Test name
Test status
Simulation time 13567473390 ps
CPU time 137.96 seconds
Started Jul 12 04:35:34 PM PDT 24
Finished Jul 12 04:38:06 PM PDT 24
Peak memory 214864 kb
Host smart-8359a975-283d-4c74-91e0-735c98cf2738
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104058125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2104058125
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2337244305
Short name T431
Test name
Test status
Simulation time 14484615052 ps
CPU time 29.87 seconds
Started Jul 12 04:35:44 PM PDT 24
Finished Jul 12 04:36:30 PM PDT 24
Peak memory 212492 kb
Host smart-6d7bbdf1-a047-4c3b-919d-755e5f04afc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337244305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2337244305
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.4161874635
Short name T426
Test name
Test status
Simulation time 1966552511 ps
CPU time 23.82 seconds
Started Jul 12 04:35:49 PM PDT 24
Finished Jul 12 04:36:27 PM PDT 24
Peak memory 218156 kb
Host smart-9d42227f-d1a9-4feb-bd53-224028c3bf04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161874635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.4161874635
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.651438626
Short name T110
Test name
Test status
Simulation time 18460834246 ps
CPU time 175.31 seconds
Started Jul 12 04:35:34 PM PDT 24
Finished Jul 12 04:38:44 PM PDT 24
Peak memory 213988 kb
Host smart-4784fc42-7aa9-4c64-bcbb-ae79988a1675
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651438626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.651438626
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3107320861
Short name T422
Test name
Test status
Simulation time 5867095956 ps
CPU time 25.05 seconds
Started Jul 12 04:36:12 PM PDT 24
Finished Jul 12 04:36:42 PM PDT 24
Peak memory 216784 kb
Host smart-fd591ed7-3190-4710-a170-e909d80296f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107320861 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3107320861
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1751522255
Short name T104
Test name
Test status
Simulation time 11406258459 ps
CPU time 32.56 seconds
Started Jul 12 04:36:16 PM PDT 24
Finished Jul 12 04:36:52 PM PDT 24
Peak memory 212224 kb
Host smart-ff4c6abd-1662-4718-b8f4-76ffa9036e42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751522255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1751522255
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.893885862
Short name T76
Test name
Test status
Simulation time 3504306798 ps
CPU time 32.97 seconds
Started Jul 12 04:36:12 PM PDT 24
Finished Jul 12 04:36:51 PM PDT 24
Peak memory 212240 kb
Host smart-8b6c0d78-5fb3-4f94-80ae-6b0018732856
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893885862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.893885862
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1439052724
Short name T388
Test name
Test status
Simulation time 662080179 ps
CPU time 13.11 seconds
Started Jul 12 04:36:12 PM PDT 24
Finished Jul 12 04:36:31 PM PDT 24
Peak memory 217152 kb
Host smart-0393cbfa-7743-414c-92c9-8956ca72e36b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439052724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1439052724
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.4190085888
Short name T114
Test name
Test status
Simulation time 3998175501 ps
CPU time 102.73 seconds
Started Jul 12 04:36:13 PM PDT 24
Finished Jul 12 04:38:01 PM PDT 24
Peak memory 214404 kb
Host smart-bbdd540c-e30d-4994-9873-1e2c077a5965
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190085888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.4190085888
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3948665741
Short name T56
Test name
Test status
Simulation time 3727934079 ps
CPU time 27.8 seconds
Started Jul 12 04:36:15 PM PDT 24
Finished Jul 12 04:36:47 PM PDT 24
Peak memory 217328 kb
Host smart-cda7d560-b204-4696-b9ca-d4e682301cac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948665741 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3948665741
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3518178672
Short name T448
Test name
Test status
Simulation time 751487390 ps
CPU time 8.07 seconds
Started Jul 12 04:36:14 PM PDT 24
Finished Jul 12 04:36:27 PM PDT 24
Peak memory 210480 kb
Host smart-63e616b5-7123-4058-b975-e9cf36de4e5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518178672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3518178672
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4042637549
Short name T109
Test name
Test status
Simulation time 3118260128 ps
CPU time 38.37 seconds
Started Jul 12 04:36:12 PM PDT 24
Finished Jul 12 04:36:56 PM PDT 24
Peak memory 213168 kb
Host smart-54f71909-56cb-4ef5-9295-38d19b76fae1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042637549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.4042637549
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.876060571
Short name T392
Test name
Test status
Simulation time 1831414602 ps
CPU time 8.25 seconds
Started Jul 12 04:36:13 PM PDT 24
Finished Jul 12 04:36:26 PM PDT 24
Peak memory 210916 kb
Host smart-7221ea49-560b-4bd2-9638-29b7b359f920
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876060571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.876060571
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4104533679
Short name T421
Test name
Test status
Simulation time 601658305 ps
CPU time 16.54 seconds
Started Jul 12 04:36:14 PM PDT 24
Finished Jul 12 04:36:36 PM PDT 24
Peak memory 217352 kb
Host smart-3c896dc4-b106-4cf0-b396-f2e3f2378ff3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104533679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.4104533679
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1434771794
Short name T116
Test name
Test status
Simulation time 8042667706 ps
CPU time 169.89 seconds
Started Jul 12 04:36:13 PM PDT 24
Finished Jul 12 04:39:08 PM PDT 24
Peak memory 214300 kb
Host smart-06fe2c5f-bcfc-42f9-bd1f-5f8024a2eb30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434771794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1434771794
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3018779428
Short name T368
Test name
Test status
Simulation time 364323132 ps
CPU time 9.06 seconds
Started Jul 12 04:36:22 PM PDT 24
Finished Jul 12 04:36:35 PM PDT 24
Peak memory 217340 kb
Host smart-6cbfa95b-be21-4b4d-b3ab-64e7dff8b670
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018779428 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3018779428
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.35612417
Short name T61
Test name
Test status
Simulation time 3939764765 ps
CPU time 31.79 seconds
Started Jul 12 04:36:20 PM PDT 24
Finished Jul 12 04:36:55 PM PDT 24
Peak memory 211592 kb
Host smart-191083cb-7918-4658-81ff-5353bce787e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35612417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.35612417
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.4166069161
Short name T70
Test name
Test status
Simulation time 11516414346 ps
CPU time 103.13 seconds
Started Jul 12 04:36:14 PM PDT 24
Finished Jul 12 04:38:02 PM PDT 24
Peak memory 213816 kb
Host smart-6b63ccb3-60da-4275-84e9-a3212956747a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166069161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.4166069161
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3132541246
Short name T452
Test name
Test status
Simulation time 65717999242 ps
CPU time 29.73 seconds
Started Jul 12 04:36:19 PM PDT 24
Finished Jul 12 04:36:52 PM PDT 24
Peak memory 212256 kb
Host smart-270e262b-1047-4a51-9159-1a72ec193776
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132541246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3132541246
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3103008669
Short name T416
Test name
Test status
Simulation time 14585041223 ps
CPU time 33.75 seconds
Started Jul 12 04:36:18 PM PDT 24
Finished Jul 12 04:36:56 PM PDT 24
Peak memory 217388 kb
Host smart-75e344b3-fb5a-47c6-b4bd-ec49e17192fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103008669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3103008669
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2571998712
Short name T408
Test name
Test status
Simulation time 7248102311 ps
CPU time 170.08 seconds
Started Jul 12 04:36:22 PM PDT 24
Finished Jul 12 04:39:16 PM PDT 24
Peak memory 214180 kb
Host smart-8b3c7bf7-0604-4873-a993-d580c05080ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571998712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2571998712
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2057148941
Short name T387
Test name
Test status
Simulation time 4192132231 ps
CPU time 20.15 seconds
Started Jul 12 04:36:21 PM PDT 24
Finished Jul 12 04:36:44 PM PDT 24
Peak memory 215956 kb
Host smart-c2aa0658-c649-483c-9278-adc4bc4b4ab4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057148941 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2057148941
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2784926190
Short name T93
Test name
Test status
Simulation time 8381175134 ps
CPU time 31.36 seconds
Started Jul 12 04:36:20 PM PDT 24
Finished Jul 12 04:36:55 PM PDT 24
Peak memory 211948 kb
Host smart-537af359-faab-4f8a-a1ce-88a024df244a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784926190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2784926190
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3707541853
Short name T94
Test name
Test status
Simulation time 55686692729 ps
CPU time 135.46 seconds
Started Jul 12 04:36:20 PM PDT 24
Finished Jul 12 04:38:39 PM PDT 24
Peak memory 214988 kb
Host smart-b2b621cd-fcc1-4ba1-a3c5-672317e00847
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707541853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3707541853
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.485546990
Short name T100
Test name
Test status
Simulation time 894668822 ps
CPU time 17.06 seconds
Started Jul 12 04:36:22 PM PDT 24
Finished Jul 12 04:36:42 PM PDT 24
Peak memory 212348 kb
Host smart-a08a71fb-476f-4fb0-851d-b1d6ba594162
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485546990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.485546990
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3702930360
Short name T398
Test name
Test status
Simulation time 2740950099 ps
CPU time 15.62 seconds
Started Jul 12 04:36:19 PM PDT 24
Finished Jul 12 04:36:38 PM PDT 24
Peak memory 217348 kb
Host smart-5778ff47-6849-48e1-8611-40f61707c8c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702930360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3702930360
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1114743615
Short name T424
Test name
Test status
Simulation time 300328374 ps
CPU time 82.96 seconds
Started Jul 12 04:36:20 PM PDT 24
Finished Jul 12 04:37:46 PM PDT 24
Peak memory 213744 kb
Host smart-1bd4ce72-59fc-4fae-bb23-69ed6836aebe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114743615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1114743615
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3397788488
Short name T441
Test name
Test status
Simulation time 546959138 ps
CPU time 9.24 seconds
Started Jul 12 04:36:23 PM PDT 24
Finished Jul 12 04:36:35 PM PDT 24
Peak memory 217276 kb
Host smart-de1390ba-f2a7-4ff9-b9ca-5e3f85c81aef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397788488 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3397788488
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1455835559
Short name T103
Test name
Test status
Simulation time 174680837 ps
CPU time 8.38 seconds
Started Jul 12 04:36:23 PM PDT 24
Finished Jul 12 04:36:35 PM PDT 24
Peak memory 210732 kb
Host smart-2de8d17f-56b0-4bf2-9de5-c3cbd712c9d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455835559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1455835559
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1984632238
Short name T71
Test name
Test status
Simulation time 35468360460 ps
CPU time 204.36 seconds
Started Jul 12 04:36:20 PM PDT 24
Finished Jul 12 04:39:48 PM PDT 24
Peak memory 215104 kb
Host smart-73f67bb6-3dae-4c92-b4af-ae2281e74d72
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984632238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1984632238
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.204430565
Short name T99
Test name
Test status
Simulation time 21502857936 ps
CPU time 19.97 seconds
Started Jul 12 04:36:21 PM PDT 24
Finished Jul 12 04:36:45 PM PDT 24
Peak memory 211480 kb
Host smart-defe14bc-ccbf-4254-8410-4d1c51e3b049
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204430565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.204430565
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2534249603
Short name T427
Test name
Test status
Simulation time 3015150957 ps
CPU time 23.34 seconds
Started Jul 12 04:36:20 PM PDT 24
Finished Jul 12 04:36:47 PM PDT 24
Peak memory 218920 kb
Host smart-d62b5958-c991-4a22-9be7-a5d3bee9b1e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534249603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2534249603
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3032508470
Short name T115
Test name
Test status
Simulation time 7773251449 ps
CPU time 169.09 seconds
Started Jul 12 04:36:21 PM PDT 24
Finished Jul 12 04:39:14 PM PDT 24
Peak memory 214160 kb
Host smart-cc6a6e04-f011-4690-ac7a-d5cf0ea88b97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032508470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3032508470
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1666810825
Short name T430
Test name
Test status
Simulation time 19213777537 ps
CPU time 17.21 seconds
Started Jul 12 04:36:35 PM PDT 24
Finished Jul 12 04:36:54 PM PDT 24
Peak memory 218004 kb
Host smart-dce81eb0-98c9-4859-af36-24c008c0c5b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666810825 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1666810825
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3804600741
Short name T373
Test name
Test status
Simulation time 172639209 ps
CPU time 8.21 seconds
Started Jul 12 04:36:29 PM PDT 24
Finished Jul 12 04:36:39 PM PDT 24
Peak memory 210480 kb
Host smart-090d9e20-cc14-4704-ae2d-67f55d23a7bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804600741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3804600741
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4263613968
Short name T433
Test name
Test status
Simulation time 38399876424 ps
CPU time 106.35 seconds
Started Jul 12 04:37:56 PM PDT 24
Finished Jul 12 04:39:48 PM PDT 24
Peak memory 213804 kb
Host smart-d5aff60c-67df-4d25-85c1-b9a8dd9189e0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263613968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.4263613968
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3104778674
Short name T397
Test name
Test status
Simulation time 4811761116 ps
CPU time 23.02 seconds
Started Jul 12 04:36:32 PM PDT 24
Finished Jul 12 04:36:57 PM PDT 24
Peak memory 212264 kb
Host smart-ce98619a-5a70-47d1-8f4e-d4832838f398
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104778674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3104778674
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3803916272
Short name T68
Test name
Test status
Simulation time 10636763386 ps
CPU time 27.16 seconds
Started Jul 12 04:36:31 PM PDT 24
Finished Jul 12 04:37:01 PM PDT 24
Peak memory 217356 kb
Host smart-93a2a3b1-50df-4489-8781-c3442023a74e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803916272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3803916272
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2458456530
Short name T386
Test name
Test status
Simulation time 13369096422 ps
CPU time 28.91 seconds
Started Jul 12 04:36:29 PM PDT 24
Finished Jul 12 04:37:00 PM PDT 24
Peak memory 217660 kb
Host smart-8863cab9-b0d4-4339-a744-3716d58586b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458456530 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2458456530
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1033686637
Short name T86
Test name
Test status
Simulation time 673219319 ps
CPU time 10.59 seconds
Started Jul 12 04:36:30 PM PDT 24
Finished Jul 12 04:36:43 PM PDT 24
Peak memory 211016 kb
Host smart-56ddeb2e-2f01-4599-9ff9-140892452f63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033686637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1033686637
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.4205993567
Short name T97
Test name
Test status
Simulation time 12504286947 ps
CPU time 76.89 seconds
Started Jul 12 04:36:32 PM PDT 24
Finished Jul 12 04:37:51 PM PDT 24
Peak memory 213928 kb
Host smart-3527f353-26a9-429b-ba7d-618eafa4106d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205993567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.4205993567
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1823746578
Short name T428
Test name
Test status
Simulation time 4015372799 ps
CPU time 32.01 seconds
Started Jul 12 04:36:30 PM PDT 24
Finished Jul 12 04:37:05 PM PDT 24
Peak memory 212296 kb
Host smart-2c001e2f-341d-4482-9b28-fe547007c5a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823746578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1823746578
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2783256437
Short name T391
Test name
Test status
Simulation time 3288826615 ps
CPU time 29.1 seconds
Started Jul 12 04:36:45 PM PDT 24
Finished Jul 12 04:37:19 PM PDT 24
Peak memory 217952 kb
Host smart-e5f748d3-683e-4a0e-b700-33eb3aa1e04b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783256437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2783256437
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2630115260
Short name T118
Test name
Test status
Simulation time 6334118147 ps
CPU time 168.28 seconds
Started Jul 12 04:36:31 PM PDT 24
Finished Jul 12 04:39:22 PM PDT 24
Peak memory 214192 kb
Host smart-9089d4e8-d5ed-4664-9f2e-ce055b6385f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630115260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2630115260
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.933809595
Short name T434
Test name
Test status
Simulation time 11983262851 ps
CPU time 25.88 seconds
Started Jul 12 04:36:30 PM PDT 24
Finished Jul 12 04:36:59 PM PDT 24
Peak memory 216828 kb
Host smart-059f1114-5307-44cf-8fef-14ceb5fc8cd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933809595 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.933809595
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3590613347
Short name T412
Test name
Test status
Simulation time 11894571793 ps
CPU time 24.42 seconds
Started Jul 12 04:36:30 PM PDT 24
Finished Jul 12 04:36:57 PM PDT 24
Peak memory 212228 kb
Host smart-11a2d901-f0cd-4a0d-8011-850a00d162eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590613347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3590613347
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1963331482
Short name T92
Test name
Test status
Simulation time 11022095816 ps
CPU time 102.87 seconds
Started Jul 12 04:36:36 PM PDT 24
Finished Jul 12 04:38:22 PM PDT 24
Peak memory 214132 kb
Host smart-a81c952e-0c09-47ef-9143-d06a33ec5931
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963331482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1963331482
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2228633253
Short name T383
Test name
Test status
Simulation time 5803130427 ps
CPU time 16.9 seconds
Started Jul 12 04:36:38 PM PDT 24
Finished Jul 12 04:36:59 PM PDT 24
Peak memory 211504 kb
Host smart-e1523ec3-6fd3-4797-a478-569c757f9857
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228633253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2228633253
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2768423515
Short name T403
Test name
Test status
Simulation time 4283770470 ps
CPU time 35.71 seconds
Started Jul 12 04:36:36 PM PDT 24
Finished Jul 12 04:37:14 PM PDT 24
Peak memory 217312 kb
Host smart-4402b40f-d4c8-4dc5-a841-c65fcd0f7612
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768423515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2768423515
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.4206270344
Short name T420
Test name
Test status
Simulation time 469775537 ps
CPU time 82.02 seconds
Started Jul 12 04:36:31 PM PDT 24
Finished Jul 12 04:37:56 PM PDT 24
Peak memory 213416 kb
Host smart-2d043cf7-b2d1-4b1d-bfdf-1bb590457ed4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206270344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.4206270344
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2457725295
Short name T380
Test name
Test status
Simulation time 1131450385 ps
CPU time 15.5 seconds
Started Jul 12 04:36:31 PM PDT 24
Finished Jul 12 04:36:49 PM PDT 24
Peak memory 217824 kb
Host smart-5a4a4851-e305-4d86-921c-8e64b183da0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457725295 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2457725295
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.910333293
Short name T456
Test name
Test status
Simulation time 1679042361 ps
CPU time 14.29 seconds
Started Jul 12 04:36:28 PM PDT 24
Finished Jul 12 04:36:44 PM PDT 24
Peak memory 210616 kb
Host smart-0ea7dab0-7468-4f3e-91de-d55d22ea1f43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910333293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.910333293
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2215653211
Short name T451
Test name
Test status
Simulation time 15651222537 ps
CPU time 125.34 seconds
Started Jul 12 04:36:31 PM PDT 24
Finished Jul 12 04:38:39 PM PDT 24
Peak memory 214228 kb
Host smart-db22cc89-a1aa-4ee6-b464-6e010c1b9983
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215653211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2215653211
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2380504021
Short name T399
Test name
Test status
Simulation time 1024242374 ps
CPU time 15.43 seconds
Started Jul 12 04:36:34 PM PDT 24
Finished Jul 12 04:36:51 PM PDT 24
Peak memory 212180 kb
Host smart-fa59dd15-4192-457c-b9ff-9f548a975dda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380504021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2380504021
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2791778651
Short name T393
Test name
Test status
Simulation time 2013835720 ps
CPU time 24.36 seconds
Started Jul 12 04:36:30 PM PDT 24
Finished Jul 12 04:36:58 PM PDT 24
Peak memory 218352 kb
Host smart-caa54cd1-1c08-4baf-85bd-08d6f5074c42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791778651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2791778651
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1139666441
Short name T117
Test name
Test status
Simulation time 4963239768 ps
CPU time 160.14 seconds
Started Jul 12 04:36:36 PM PDT 24
Finished Jul 12 04:39:19 PM PDT 24
Peak memory 218892 kb
Host smart-a84d24f2-66b2-42c9-9387-e248cd12b508
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139666441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1139666441
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2356894652
Short name T375
Test name
Test status
Simulation time 3240588941 ps
CPU time 27.29 seconds
Started Jul 12 04:36:35 PM PDT 24
Finished Jul 12 04:37:05 PM PDT 24
Peak memory 217972 kb
Host smart-45595534-4920-422b-8bdf-8eb9d08b8308
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356894652 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2356894652
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2231482166
Short name T366
Test name
Test status
Simulation time 16777967890 ps
CPU time 31.69 seconds
Started Jul 12 04:36:36 PM PDT 24
Finished Jul 12 04:37:11 PM PDT 24
Peak memory 211700 kb
Host smart-c25915af-157a-40d8-8da6-e396ea4c9d87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231482166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2231482166
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1117939399
Short name T77
Test name
Test status
Simulation time 4131338794 ps
CPU time 56.66 seconds
Started Jul 12 04:36:30 PM PDT 24
Finished Jul 12 04:37:29 PM PDT 24
Peak memory 215320 kb
Host smart-cf8bb37d-ec12-42f5-b4b6-824408609248
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117939399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1117939399
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.991491726
Short name T440
Test name
Test status
Simulation time 14263818363 ps
CPU time 32.33 seconds
Started Jul 12 04:36:33 PM PDT 24
Finished Jul 12 04:37:07 PM PDT 24
Peak memory 212496 kb
Host smart-ffac8c4b-a16b-4a7e-adb1-85bbc65a44a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991491726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.991491726
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.283380458
Short name T425
Test name
Test status
Simulation time 4639613104 ps
CPU time 19.52 seconds
Started Jul 12 04:36:30 PM PDT 24
Finished Jul 12 04:36:53 PM PDT 24
Peak memory 217612 kb
Host smart-ab220abe-5cbf-4a89-afa1-2dc6ebd5ad72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283380458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.283380458
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3297168668
Short name T111
Test name
Test status
Simulation time 2118182180 ps
CPU time 163.56 seconds
Started Jul 12 04:36:27 PM PDT 24
Finished Jul 12 04:39:12 PM PDT 24
Peak memory 213696 kb
Host smart-52d82134-d530-49e7-9822-f1e41a913061
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297168668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3297168668
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.546456360
Short name T432
Test name
Test status
Simulation time 18012130003 ps
CPU time 19.08 seconds
Started Jul 12 04:36:03 PM PDT 24
Finished Jul 12 04:36:32 PM PDT 24
Peak memory 211904 kb
Host smart-48369010-ab80-41ee-915a-0d8f94561444
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546456360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.546456360
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3206871289
Short name T367
Test name
Test status
Simulation time 3673610398 ps
CPU time 29.05 seconds
Started Jul 12 04:35:43 PM PDT 24
Finished Jul 12 04:36:29 PM PDT 24
Peak memory 210720 kb
Host smart-ec3e5fc1-07e0-4349-b12b-f0c07ce56692
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206871289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3206871289
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1368154007
Short name T395
Test name
Test status
Simulation time 8269812323 ps
CPU time 26.64 seconds
Started Jul 12 04:35:38 PM PDT 24
Finished Jul 12 04:36:20 PM PDT 24
Peak memory 210588 kb
Host smart-aeb4badc-f035-47b8-9be0-ade3e52b9311
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368154007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1368154007
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1686882923
Short name T55
Test name
Test status
Simulation time 3369150724 ps
CPU time 27.87 seconds
Started Jul 12 04:35:50 PM PDT 24
Finished Jul 12 04:36:33 PM PDT 24
Peak memory 216100 kb
Host smart-83bafceb-be9e-4c39-bfd5-274bdf8cd163
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686882923 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1686882923
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3402237525
Short name T363
Test name
Test status
Simulation time 3279468139 ps
CPU time 27.8 seconds
Started Jul 12 04:35:45 PM PDT 24
Finished Jul 12 04:36:29 PM PDT 24
Peak memory 210496 kb
Host smart-b2973f55-f885-4db5-b66e-8ecd615cf8fb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402237525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3402237525
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3413627083
Short name T396
Test name
Test status
Simulation time 31023606265 ps
CPU time 31.37 seconds
Started Jul 12 04:35:43 PM PDT 24
Finished Jul 12 04:36:32 PM PDT 24
Peak memory 210672 kb
Host smart-d045969d-da76-4c92-a276-340f5ebbe371
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413627083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3413627083
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3654152878
Short name T404
Test name
Test status
Simulation time 2106273446 ps
CPU time 51.99 seconds
Started Jul 12 04:35:34 PM PDT 24
Finished Jul 12 04:36:38 PM PDT 24
Peak memory 213720 kb
Host smart-c2991dcd-21c0-4383-89a3-31122dc556ce
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654152878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3654152878
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2661446920
Short name T98
Test name
Test status
Simulation time 2911345709 ps
CPU time 26.17 seconds
Started Jul 12 04:35:43 PM PDT 24
Finished Jul 12 04:36:26 PM PDT 24
Peak memory 211976 kb
Host smart-2058b281-2286-492b-a779-fb3545ca976b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661446920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2661446920
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2853084382
Short name T376
Test name
Test status
Simulation time 859007004 ps
CPU time 17.02 seconds
Started Jul 12 04:35:34 PM PDT 24
Finished Jul 12 04:36:05 PM PDT 24
Peak memory 217240 kb
Host smart-d549a33a-7b04-43e2-b545-e1e7b668dec5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853084382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2853084382
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3291162893
Short name T90
Test name
Test status
Simulation time 325678317 ps
CPU time 8.48 seconds
Started Jul 12 04:35:53 PM PDT 24
Finished Jul 12 04:36:15 PM PDT 24
Peak memory 210596 kb
Host smart-960bb976-71e9-47e2-af4a-205df5b8ceca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291162893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3291162893
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.233507516
Short name T365
Test name
Test status
Simulation time 176294914 ps
CPU time 8.72 seconds
Started Jul 12 04:35:43 PM PDT 24
Finished Jul 12 04:36:09 PM PDT 24
Peak memory 210588 kb
Host smart-e5c25336-dae1-491f-93e0-d5c09973bbc6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233507516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.233507516
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1829205223
Short name T423
Test name
Test status
Simulation time 4135537831 ps
CPU time 34.41 seconds
Started Jul 12 04:35:46 PM PDT 24
Finished Jul 12 04:36:37 PM PDT 24
Peak memory 211520 kb
Host smart-a075c62c-ab41-42a0-b695-e5c432ac9e23
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829205223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1829205223
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.79693353
Short name T442
Test name
Test status
Simulation time 4526380720 ps
CPU time 16.63 seconds
Started Jul 12 04:35:53 PM PDT 24
Finished Jul 12 04:36:23 PM PDT 24
Peak memory 218104 kb
Host smart-ab7c9caf-76ae-4418-8dec-145651f9a95f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79693353 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.79693353
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3837008173
Short name T445
Test name
Test status
Simulation time 12733620267 ps
CPU time 27.68 seconds
Started Jul 12 04:35:46 PM PDT 24
Finished Jul 12 04:36:30 PM PDT 24
Peak memory 212388 kb
Host smart-0c430620-60c7-47cc-aac1-572cfbbeb456
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837008173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3837008173
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4128644910
Short name T364
Test name
Test status
Simulation time 15948649646 ps
CPU time 32.83 seconds
Started Jul 12 04:35:50 PM PDT 24
Finished Jul 12 04:36:38 PM PDT 24
Peak memory 210776 kb
Host smart-84304d9a-cb5b-4269-93c1-5996ac7b0cc0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128644910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.4128644910
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2263617330
Short name T447
Test name
Test status
Simulation time 339017534 ps
CPU time 8.16 seconds
Started Jul 12 04:35:43 PM PDT 24
Finished Jul 12 04:36:08 PM PDT 24
Peak memory 210552 kb
Host smart-88266402-3e6d-49ba-9404-fbee97cad357
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263617330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2263617330
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1484533495
Short name T379
Test name
Test status
Simulation time 21234675115 ps
CPU time 178.14 seconds
Started Jul 12 04:35:47 PM PDT 24
Finished Jul 12 04:39:01 PM PDT 24
Peak memory 214796 kb
Host smart-ba2b62a2-e1b0-4e19-b6de-f111a4e46f1e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484533495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1484533495
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2085334430
Short name T450
Test name
Test status
Simulation time 3758214336 ps
CPU time 29.91 seconds
Started Jul 12 04:35:49 PM PDT 24
Finished Jul 12 04:36:34 PM PDT 24
Peak memory 212080 kb
Host smart-0dd2dbc3-126c-4691-9b7f-fcac7cbbd7cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085334430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2085334430
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2806436098
Short name T382
Test name
Test status
Simulation time 661265338 ps
CPU time 13.04 seconds
Started Jul 12 04:35:50 PM PDT 24
Finished Jul 12 04:36:17 PM PDT 24
Peak memory 217420 kb
Host smart-522a791a-377a-4c27-a58d-ec8713f3c1f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806436098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2806436098
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1805321276
Short name T120
Test name
Test status
Simulation time 25582659514 ps
CPU time 94.36 seconds
Started Jul 12 04:35:46 PM PDT 24
Finished Jul 12 04:37:36 PM PDT 24
Peak memory 213832 kb
Host smart-726831b3-db0a-4caa-b467-542f0e6d1d97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805321276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1805321276
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2471909549
Short name T95
Test name
Test status
Simulation time 37785347386 ps
CPU time 19.87 seconds
Started Jul 12 04:35:52 PM PDT 24
Finished Jul 12 04:36:25 PM PDT 24
Peak memory 212176 kb
Host smart-101d6520-75a2-4086-88e7-4a25b6016bb4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471909549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2471909549
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.228075323
Short name T390
Test name
Test status
Simulation time 8198960264 ps
CPU time 28.05 seconds
Started Jul 12 04:35:51 PM PDT 24
Finished Jul 12 04:36:33 PM PDT 24
Peak memory 211328 kb
Host smart-3155e480-d5d2-463b-9c9f-2aad80a1fe62
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228075323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.228075323
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3531212288
Short name T371
Test name
Test status
Simulation time 331582458 ps
CPU time 15.5 seconds
Started Jul 12 04:35:51 PM PDT 24
Finished Jul 12 04:36:21 PM PDT 24
Peak memory 210544 kb
Host smart-84aeada8-fb55-48cb-93d5-33db00934bc2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531212288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3531212288
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1659344473
Short name T394
Test name
Test status
Simulation time 7194431251 ps
CPU time 29.72 seconds
Started Jul 12 04:35:58 PM PDT 24
Finished Jul 12 04:36:39 PM PDT 24
Peak memory 217744 kb
Host smart-bf49e5eb-ee04-4632-baeb-63ae8881e20b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659344473 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1659344473
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.50860987
Short name T75
Test name
Test status
Simulation time 4098962480 ps
CPU time 16.67 seconds
Started Jul 12 04:35:57 PM PDT 24
Finished Jul 12 04:36:26 PM PDT 24
Peak memory 211996 kb
Host smart-535dd781-c72f-4f4c-8c3b-dcd0c9213d5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50860987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.50860987
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1561041461
Short name T411
Test name
Test status
Simulation time 8547338743 ps
CPU time 21.39 seconds
Started Jul 12 04:35:52 PM PDT 24
Finished Jul 12 04:36:27 PM PDT 24
Peak memory 210716 kb
Host smart-d3e3265e-3ea5-428b-b9e7-f29bc5c0f908
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561041461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1561041461
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.299495900
Short name T402
Test name
Test status
Simulation time 822146797 ps
CPU time 13.69 seconds
Started Jul 12 04:35:56 PM PDT 24
Finished Jul 12 04:36:22 PM PDT 24
Peak memory 210812 kb
Host smart-d6971619-0f27-4766-8b19-351384054c41
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299495900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
299495900
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3928043916
Short name T429
Test name
Test status
Simulation time 7182333029 ps
CPU time 83.94 seconds
Started Jul 12 04:35:49 PM PDT 24
Finished Jul 12 04:37:27 PM PDT 24
Peak memory 214432 kb
Host smart-b85d9e55-4c0f-42f9-a829-a3e24d21cc9d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928043916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3928043916
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1602749428
Short name T102
Test name
Test status
Simulation time 244911245 ps
CPU time 8.22 seconds
Started Jul 12 04:35:55 PM PDT 24
Finished Jul 12 04:36:16 PM PDT 24
Peak memory 210888 kb
Host smart-99e45779-b8ac-49b5-9f8b-9b1d0a4fe8b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602749428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1602749428
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3947417800
Short name T378
Test name
Test status
Simulation time 4812468934 ps
CPU time 35.54 seconds
Started Jul 12 04:35:47 PM PDT 24
Finished Jul 12 04:36:38 PM PDT 24
Peak memory 217532 kb
Host smart-e7b27068-0945-489c-aacd-58d7bf92a263
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947417800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3947417800
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2692275301
Short name T121
Test name
Test status
Simulation time 2879369489 ps
CPU time 167.28 seconds
Started Jul 12 04:35:44 PM PDT 24
Finished Jul 12 04:38:48 PM PDT 24
Peak memory 213856 kb
Host smart-8db23e05-ff9f-4e6b-b851-2b3ac57d1582
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692275301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2692275301
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1912105163
Short name T400
Test name
Test status
Simulation time 2958929277 ps
CPU time 18.07 seconds
Started Jul 12 04:35:59 PM PDT 24
Finished Jul 12 04:36:28 PM PDT 24
Peak memory 217320 kb
Host smart-e20ed2df-854e-46e6-b3dd-e67bf6b92b4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912105163 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1912105163
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.4060981602
Short name T454
Test name
Test status
Simulation time 660765758 ps
CPU time 8.31 seconds
Started Jul 12 04:36:02 PM PDT 24
Finished Jul 12 04:36:20 PM PDT 24
Peak memory 210548 kb
Host smart-3b7e0ff7-7484-48d8-9de6-df52748f74e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060981602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.4060981602
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.756812282
Short name T418
Test name
Test status
Simulation time 15314656630 ps
CPU time 118.31 seconds
Started Jul 12 04:35:58 PM PDT 24
Finished Jul 12 04:38:08 PM PDT 24
Peak memory 215344 kb
Host smart-6912beb4-b4fb-4ebf-8c4f-7fd3c319654a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756812282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.756812282
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2322885266
Short name T439
Test name
Test status
Simulation time 6227149545 ps
CPU time 23.36 seconds
Started Jul 12 04:36:04 PM PDT 24
Finished Jul 12 04:36:37 PM PDT 24
Peak memory 211992 kb
Host smart-9bfee611-7744-4392-a747-15671f7330f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322885266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2322885266
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3797561734
Short name T443
Test name
Test status
Simulation time 1608151565 ps
CPU time 22.79 seconds
Started Jul 12 04:35:56 PM PDT 24
Finished Jul 12 04:36:31 PM PDT 24
Peak memory 217420 kb
Host smart-aceb4576-1b5a-4647-b324-a8cb08543155
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797561734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3797561734
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2771218268
Short name T377
Test name
Test status
Simulation time 12325079991 ps
CPU time 27.06 seconds
Started Jul 12 04:36:01 PM PDT 24
Finished Jul 12 04:36:39 PM PDT 24
Peak memory 218356 kb
Host smart-f35c9cf5-9f87-4558-8d93-0c61aef505c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771218268 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2771218268
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1295836202
Short name T446
Test name
Test status
Simulation time 24604900919 ps
CPU time 24.89 seconds
Started Jul 12 04:36:01 PM PDT 24
Finished Jul 12 04:36:37 PM PDT 24
Peak memory 211940 kb
Host smart-1d36d5f4-1575-4d29-8387-275d8045786b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295836202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1295836202
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3242072686
Short name T96
Test name
Test status
Simulation time 62829062862 ps
CPU time 127.83 seconds
Started Jul 12 04:35:58 PM PDT 24
Finished Jul 12 04:38:17 PM PDT 24
Peak memory 213820 kb
Host smart-8a5f6cae-ab8a-4fe5-823e-a069afb6d9e2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242072686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3242072686
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.4041040099
Short name T101
Test name
Test status
Simulation time 3358816090 ps
CPU time 18.68 seconds
Started Jul 12 04:36:02 PM PDT 24
Finished Jul 12 04:36:31 PM PDT 24
Peak memory 211724 kb
Host smart-fa0b64bc-a09c-4921-93fa-4c1f4c09069a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041040099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.4041040099
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1236682537
Short name T414
Test name
Test status
Simulation time 9340500658 ps
CPU time 28.27 seconds
Started Jul 12 04:36:01 PM PDT 24
Finished Jul 12 04:36:40 PM PDT 24
Peak memory 217340 kb
Host smart-34ca29a6-172f-4b0f-bb8c-1209a5949b37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236682537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1236682537
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.16782249
Short name T113
Test name
Test status
Simulation time 1328015677 ps
CPU time 89.79 seconds
Started Jul 12 04:36:02 PM PDT 24
Finished Jul 12 04:37:42 PM PDT 24
Peak memory 213336 kb
Host smart-64fc08d5-63a8-4590-a734-062952be5f4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16782249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_intg
_err.16782249
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3069613801
Short name T369
Test name
Test status
Simulation time 7585811996 ps
CPU time 25.95 seconds
Started Jul 12 04:35:57 PM PDT 24
Finished Jul 12 04:36:35 PM PDT 24
Peak memory 214964 kb
Host smart-60072f43-4cb4-4ffc-971f-9a206bbea69b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069613801 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3069613801
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3682284944
Short name T74
Test name
Test status
Simulation time 16119751606 ps
CPU time 33.04 seconds
Started Jul 12 04:35:58 PM PDT 24
Finished Jul 12 04:36:43 PM PDT 24
Peak memory 211320 kb
Host smart-0b62acc0-a0b9-4d67-a798-1deca0caa802
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682284944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3682284944
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.499167122
Short name T60
Test name
Test status
Simulation time 15467110453 ps
CPU time 142.92 seconds
Started Jul 12 04:36:00 PM PDT 24
Finished Jul 12 04:38:33 PM PDT 24
Peak memory 215276 kb
Host smart-ca6a8bcc-6261-4aa0-ad2a-c203a16cc261
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499167122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.499167122
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2240732831
Short name T438
Test name
Test status
Simulation time 169433699 ps
CPU time 8.23 seconds
Started Jul 12 04:36:03 PM PDT 24
Finished Jul 12 04:36:21 PM PDT 24
Peak memory 210968 kb
Host smart-28242b41-5352-4bcb-aedd-a7c08ab40fd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240732831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2240732831
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2130391255
Short name T374
Test name
Test status
Simulation time 2844975205 ps
CPU time 22.65 seconds
Started Jul 12 04:35:58 PM PDT 24
Finished Jul 12 04:36:32 PM PDT 24
Peak memory 218388 kb
Host smart-12236f59-64e8-4f45-8c70-521547dae5ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130391255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2130391255
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3630464911
Short name T119
Test name
Test status
Simulation time 7159497044 ps
CPU time 100.92 seconds
Started Jul 12 04:35:59 PM PDT 24
Finished Jul 12 04:37:51 PM PDT 24
Peak memory 213476 kb
Host smart-75cf9965-bdf2-4bab-b56f-e571c46ee479
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630464911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3630464911
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1570612823
Short name T405
Test name
Test status
Simulation time 184034933 ps
CPU time 8.75 seconds
Started Jul 12 04:36:07 PM PDT 24
Finished Jul 12 04:36:24 PM PDT 24
Peak memory 215496 kb
Host smart-453b4656-b815-4d42-bcd0-34c1330b6632
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570612823 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1570612823
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3702478163
Short name T385
Test name
Test status
Simulation time 169460253 ps
CPU time 8.36 seconds
Started Jul 12 04:36:11 PM PDT 24
Finished Jul 12 04:36:26 PM PDT 24
Peak memory 210880 kb
Host smart-941169ea-0dd8-4e57-a194-98b1bdcbc71f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702478163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3702478163
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3008657260
Short name T410
Test name
Test status
Simulation time 27375044901 ps
CPU time 116.71 seconds
Started Jul 12 04:36:01 PM PDT 24
Finished Jul 12 04:38:09 PM PDT 24
Peak memory 211912 kb
Host smart-3d07abe0-8590-47b1-9ee3-89ab9a4f0e0d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008657260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3008657260
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2540374550
Short name T455
Test name
Test status
Simulation time 669956152 ps
CPU time 13.08 seconds
Started Jul 12 04:36:05 PM PDT 24
Finished Jul 12 04:36:27 PM PDT 24
Peak memory 211292 kb
Host smart-425f69cc-af46-4d98-84f0-56c634185ef4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540374550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2540374550
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.812796251
Short name T384
Test name
Test status
Simulation time 66558932712 ps
CPU time 34.81 seconds
Started Jul 12 04:36:08 PM PDT 24
Finished Jul 12 04:36:51 PM PDT 24
Peak memory 218044 kb
Host smart-100d1061-65b9-492f-871c-325233679334
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812796251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.812796251
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4243392611
Short name T59
Test name
Test status
Simulation time 4364769043 ps
CPU time 103.67 seconds
Started Jul 12 04:36:09 PM PDT 24
Finished Jul 12 04:38:00 PM PDT 24
Peak memory 213960 kb
Host smart-2c4b9d52-08d4-468e-bb58-83b0a53e79ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243392611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.4243392611
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1670853653
Short name T401
Test name
Test status
Simulation time 8376500252 ps
CPU time 33.69 seconds
Started Jul 12 04:36:06 PM PDT 24
Finished Jul 12 04:36:48 PM PDT 24
Peak memory 218208 kb
Host smart-2af91f86-6b9c-49a8-b63b-591bf95c35cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670853653 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1670853653
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2189909387
Short name T407
Test name
Test status
Simulation time 12015540956 ps
CPU time 24.5 seconds
Started Jul 12 04:36:07 PM PDT 24
Finished Jul 12 04:36:39 PM PDT 24
Peak memory 212424 kb
Host smart-341fab49-9c18-471b-aaa4-fc615f0a4715
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189909387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2189909387
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3172621415
Short name T435
Test name
Test status
Simulation time 30572071997 ps
CPU time 88.44 seconds
Started Jul 12 04:36:04 PM PDT 24
Finished Jul 12 04:37:42 PM PDT 24
Peak memory 213792 kb
Host smart-7d64b0a8-b8ee-49e6-8503-f8c7036bc260
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172621415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3172621415
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1594267137
Short name T73
Test name
Test status
Simulation time 167447206 ps
CPU time 8.07 seconds
Started Jul 12 04:36:06 PM PDT 24
Finished Jul 12 04:36:22 PM PDT 24
Peak memory 210780 kb
Host smart-74702a19-24fb-412f-92cf-88fd4e0cd6d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594267137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1594267137
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2250134202
Short name T381
Test name
Test status
Simulation time 6835031109 ps
CPU time 33.91 seconds
Started Jul 12 04:36:08 PM PDT 24
Finished Jul 12 04:36:50 PM PDT 24
Peak memory 218784 kb
Host smart-21e815aa-7d43-4b82-a9bd-120077b0dee6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250134202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2250134202
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2696652861
Short name T415
Test name
Test status
Simulation time 3743744013 ps
CPU time 82.68 seconds
Started Jul 12 04:36:06 PM PDT 24
Finished Jul 12 04:37:37 PM PDT 24
Peak memory 213756 kb
Host smart-927c26e1-5d8e-4643-8fb0-b605a029bedc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696652861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2696652861
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2280181431
Short name T351
Test name
Test status
Simulation time 2209129785 ps
CPU time 20.86 seconds
Started Jul 12 04:34:41 PM PDT 24
Finished Jul 12 04:35:07 PM PDT 24
Peak memory 216872 kb
Host smart-aa83810c-d071-4b75-8e0c-0b74042c8677
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280181431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2280181431
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1313492118
Short name T347
Test name
Test status
Simulation time 53277468612 ps
CPU time 594.6 seconds
Started Jul 12 04:34:41 PM PDT 24
Finished Jul 12 04:44:41 PM PDT 24
Peak memory 237796 kb
Host smart-ebf0e950-c4c8-4628-bb6b-3afa4027e706
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313492118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1313492118
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1890444271
Short name T360
Test name
Test status
Simulation time 6248990568 ps
CPU time 39.99 seconds
Started Jul 12 04:34:37 PM PDT 24
Finished Jul 12 04:35:22 PM PDT 24
Peak memory 219240 kb
Host smart-f66e8868-b2dc-4c59-a1aa-db4105ccdb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890444271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1890444271
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3702414664
Short name T346
Test name
Test status
Simulation time 2580638815 ps
CPU time 25.18 seconds
Started Jul 12 04:34:37 PM PDT 24
Finished Jul 12 04:35:09 PM PDT 24
Peak memory 219268 kb
Host smart-5203136c-66fc-48a8-9c81-33010f08673d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3702414664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3702414664
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1542296187
Short name T24
Test name
Test status
Simulation time 14874100171 ps
CPU time 242.22 seconds
Started Jul 12 04:34:35 PM PDT 24
Finished Jul 12 04:38:43 PM PDT 24
Peak memory 237912 kb
Host smart-e05c80a9-61c7-4765-b7d1-dc16c3561baf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542296187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1542296187
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2391535996
Short name T230
Test name
Test status
Simulation time 701864719 ps
CPU time 20.15 seconds
Started Jul 12 04:34:44 PM PDT 24
Finished Jul 12 04:35:08 PM PDT 24
Peak memory 216632 kb
Host smart-feb1001c-a0ed-4c5c-b46f-3a5a225713b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391535996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2391535996
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3949034689
Short name T132
Test name
Test status
Simulation time 9863243774 ps
CPU time 35.04 seconds
Started Jul 12 04:34:41 PM PDT 24
Finished Jul 12 04:35:20 PM PDT 24
Peak memory 219152 kb
Host smart-7cd43e6a-7369-4fee-b5e5-ca3e2533b226
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949034689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3949034689
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2391311212
Short name T333
Test name
Test status
Simulation time 11469824591 ps
CPU time 26.04 seconds
Started Jul 12 04:34:44 PM PDT 24
Finished Jul 12 04:35:14 PM PDT 24
Peak memory 217140 kb
Host smart-4b8bf9d3-382f-4eb6-b66a-933e891648e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391311212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2391311212
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2468586646
Short name T49
Test name
Test status
Simulation time 54036871970 ps
CPU time 194.8 seconds
Started Jul 12 04:34:44 PM PDT 24
Finished Jul 12 04:38:03 PM PDT 24
Peak memory 224260 kb
Host smart-3f2c41ab-80ca-430a-a4c5-bf1bf02d062b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468586646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2468586646
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.244690476
Short name T345
Test name
Test status
Simulation time 8769913208 ps
CPU time 61.29 seconds
Started Jul 12 04:34:48 PM PDT 24
Finished Jul 12 04:35:52 PM PDT 24
Peak memory 219284 kb
Host smart-1e021d4a-6c69-4746-a3b0-ad098c6c3e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244690476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.244690476
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3249834122
Short name T183
Test name
Test status
Simulation time 1224055147 ps
CPU time 17.71 seconds
Started Jul 12 04:34:41 PM PDT 24
Finished Jul 12 04:35:04 PM PDT 24
Peak memory 211472 kb
Host smart-a2b840da-52df-4fea-a4c2-514e16ba1e6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3249834122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3249834122
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3141062386
Short name T25
Test name
Test status
Simulation time 585015104 ps
CPU time 234.89 seconds
Started Jul 12 04:34:40 PM PDT 24
Finished Jul 12 04:38:39 PM PDT 24
Peak memory 237696 kb
Host smart-46957b1e-14c1-40da-9927-ac7a14025700
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141062386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3141062386
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.198683496
Short name T176
Test name
Test status
Simulation time 1351369643 ps
CPU time 21.08 seconds
Started Jul 12 04:34:44 PM PDT 24
Finished Jul 12 04:35:09 PM PDT 24
Peak memory 215860 kb
Host smart-b687b9b4-e357-4a12-acb2-8448fdea8567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198683496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.198683496
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1184686821
Short name T5
Test name
Test status
Simulation time 3751565428 ps
CPU time 19.5 seconds
Started Jul 12 04:34:46 PM PDT 24
Finished Jul 12 04:35:09 PM PDT 24
Peak memory 217088 kb
Host smart-077aebfc-f57c-4cae-a6a3-2f2517455ea0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184686821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1184686821
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2105720175
Short name T172
Test name
Test status
Simulation time 169109511 ps
CPU time 8.28 seconds
Started Jul 12 04:34:55 PM PDT 24
Finished Jul 12 04:35:05 PM PDT 24
Peak memory 218172 kb
Host smart-c21d8779-b812-4e9c-afaa-f279c01a2ed1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105720175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2105720175
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1430844122
Short name T359
Test name
Test status
Simulation time 278275638021 ps
CPU time 789.78 seconds
Started Jul 12 04:34:58 PM PDT 24
Finished Jul 12 04:48:11 PM PDT 24
Peak memory 235648 kb
Host smart-9145f74d-288a-4655-ac2d-c735cae84ab9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430844122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1430844122
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1727237310
Short name T228
Test name
Test status
Simulation time 15513967872 ps
CPU time 25.7 seconds
Started Jul 12 04:34:55 PM PDT 24
Finished Jul 12 04:35:22 PM PDT 24
Peak memory 211800 kb
Host smart-ebd60237-c382-4449-b5af-6f125503064a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1727237310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1727237310
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2597625001
Short name T327
Test name
Test status
Simulation time 17081636846 ps
CPU time 83.4 seconds
Started Jul 12 04:34:56 PM PDT 24
Finished Jul 12 04:36:21 PM PDT 24
Peak memory 216464 kb
Host smart-c0fc25fe-0d3d-43dd-8d8d-0d42bc4173fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597625001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2597625001
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1589490134
Short name T255
Test name
Test status
Simulation time 5263542523 ps
CPU time 58.11 seconds
Started Jul 12 04:34:53 PM PDT 24
Finished Jul 12 04:35:53 PM PDT 24
Peak memory 219212 kb
Host smart-6384ca39-3792-4a15-bc88-2b8757bc8cd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589490134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1589490134
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3615559196
Short name T211
Test name
Test status
Simulation time 4773973437 ps
CPU time 23.11 seconds
Started Jul 12 04:34:56 PM PDT 24
Finished Jul 12 04:35:20 PM PDT 24
Peak memory 217436 kb
Host smart-af328792-1f55-4aa4-bf6a-54370252ec86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615559196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3615559196
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.953266910
Short name T233
Test name
Test status
Simulation time 8558576629 ps
CPU time 271.48 seconds
Started Jul 12 04:34:54 PM PDT 24
Finished Jul 12 04:39:27 PM PDT 24
Peak memory 230876 kb
Host smart-af114ed8-b592-4b3b-a483-6bb9e1a812da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953266910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.953266910
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3217606867
Short name T222
Test name
Test status
Simulation time 349999881 ps
CPU time 19.34 seconds
Started Jul 12 04:34:56 PM PDT 24
Finished Jul 12 04:35:16 PM PDT 24
Peak memory 219216 kb
Host smart-4f315601-ef95-499e-8d9d-7d3983dd4c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217606867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3217606867
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.389519357
Short name T175
Test name
Test status
Simulation time 781646527 ps
CPU time 15.37 seconds
Started Jul 12 04:34:58 PM PDT 24
Finished Jul 12 04:35:16 PM PDT 24
Peak memory 219300 kb
Host smart-3074d6a1-f39e-4bff-8048-e4657d110565
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=389519357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.389519357
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.646535671
Short name T83
Test name
Test status
Simulation time 5184812618 ps
CPU time 94.92 seconds
Started Jul 12 04:34:52 PM PDT 24
Finished Jul 12 04:36:28 PM PDT 24
Peak memory 220472 kb
Host smart-1f8b8636-21bd-438e-9e1b-6584fd06dc64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646535671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.646535671
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2761944032
Short name T29
Test name
Test status
Simulation time 176036683 ps
CPU time 8.59 seconds
Started Jul 12 04:34:55 PM PDT 24
Finished Jul 12 04:35:05 PM PDT 24
Peak memory 218096 kb
Host smart-6d935873-baec-4570-a258-d1701bdadde9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761944032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2761944032
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1689779826
Short name T42
Test name
Test status
Simulation time 7888991149 ps
CPU time 296.21 seconds
Started Jul 12 04:34:57 PM PDT 24
Finished Jul 12 04:39:54 PM PDT 24
Peak memory 233204 kb
Host smart-8ed02221-d0cf-4b18-b835-9e5b54563dd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689779826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1689779826
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1810686319
Short name T252
Test name
Test status
Simulation time 7751109716 ps
CPU time 63.02 seconds
Started Jul 12 04:34:54 PM PDT 24
Finished Jul 12 04:35:59 PM PDT 24
Peak memory 219280 kb
Host smart-eb5ffcbd-2129-479a-8c6e-3ebcf3c48fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810686319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1810686319
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.204182645
Short name T217
Test name
Test status
Simulation time 3650867599 ps
CPU time 29.83 seconds
Started Jul 12 04:34:56 PM PDT 24
Finished Jul 12 04:35:27 PM PDT 24
Peak memory 219240 kb
Host smart-37801e3d-a992-4543-b01c-89513f356512
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=204182645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.204182645
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.151486274
Short name T241
Test name
Test status
Simulation time 41160324649 ps
CPU time 35.14 seconds
Started Jul 12 04:34:59 PM PDT 24
Finished Jul 12 04:35:36 PM PDT 24
Peak memory 217140 kb
Host smart-ee918008-8317-44ba-a8b0-e34e3c62fcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151486274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.151486274
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2810023122
Short name T203
Test name
Test status
Simulation time 36344196431 ps
CPU time 112.03 seconds
Started Jul 12 04:34:58 PM PDT 24
Finished Jul 12 04:36:53 PM PDT 24
Peak memory 220800 kb
Host smart-908ee4f8-492a-456d-bdc7-dc2267c10612
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810023122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2810023122
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.484398836
Short name T196
Test name
Test status
Simulation time 27579835472 ps
CPU time 26.96 seconds
Started Jul 12 04:34:55 PM PDT 24
Finished Jul 12 04:35:23 PM PDT 24
Peak memory 213216 kb
Host smart-b13982bc-743c-4856-8a68-bf28786af588
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484398836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.484398836
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2007758316
Short name T200
Test name
Test status
Simulation time 114710452347 ps
CPU time 415.49 seconds
Started Jul 12 04:34:56 PM PDT 24
Finished Jul 12 04:41:53 PM PDT 24
Peak memory 235228 kb
Host smart-54aa69ad-63b5-4fe6-9dec-6237f316ed20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007758316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2007758316
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1659245853
Short name T305
Test name
Test status
Simulation time 11348003653 ps
CPU time 39.12 seconds
Started Jul 12 04:35:06 PM PDT 24
Finished Jul 12 04:35:46 PM PDT 24
Peak memory 219268 kb
Host smart-519bc3dd-8bb4-4abb-8603-d6daf410b74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659245853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1659245853
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3008050901
Short name T287
Test name
Test status
Simulation time 703567033 ps
CPU time 10.17 seconds
Started Jul 12 04:34:54 PM PDT 24
Finished Jul 12 04:35:05 PM PDT 24
Peak memory 219212 kb
Host smart-fc3c2ffe-83af-4dc9-9efc-6898814493d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3008050901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3008050901
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2703769744
Short name T80
Test name
Test status
Simulation time 2881208962 ps
CPU time 20.46 seconds
Started Jul 12 04:34:57 PM PDT 24
Finished Jul 12 04:35:18 PM PDT 24
Peak memory 216660 kb
Host smart-b6c09968-2599-4e1e-ba77-2c3f926baf44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703769744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2703769744
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.4244265802
Short name T108
Test name
Test status
Simulation time 13142074990 ps
CPU time 117.42 seconds
Started Jul 12 04:34:55 PM PDT 24
Finished Jul 12 04:36:54 PM PDT 24
Peak memory 219564 kb
Host smart-0347b530-d056-492e-be6e-97828725135a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244265802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.4244265802
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2191604300
Short name T129
Test name
Test status
Simulation time 9699269953 ps
CPU time 23.41 seconds
Started Jul 12 04:35:11 PM PDT 24
Finished Jul 12 04:35:36 PM PDT 24
Peak memory 217384 kb
Host smart-cf52ecfe-e012-4733-aff3-1b7013c653a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191604300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2191604300
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1292592156
Short name T138
Test name
Test status
Simulation time 40276545040 ps
CPU time 345.78 seconds
Started Jul 12 04:34:58 PM PDT 24
Finished Jul 12 04:40:47 PM PDT 24
Peak memory 236956 kb
Host smart-e821c341-066a-4e69-b58f-77971c0330e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292592156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1292592156
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3405019195
Short name T250
Test name
Test status
Simulation time 22423310045 ps
CPU time 52.9 seconds
Started Jul 12 04:34:53 PM PDT 24
Finished Jul 12 04:35:47 PM PDT 24
Peak memory 219172 kb
Host smart-5a766adc-523f-425a-996d-6bc1486a76fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405019195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3405019195
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1640384538
Short name T267
Test name
Test status
Simulation time 10969295428 ps
CPU time 23.47 seconds
Started Jul 12 04:35:02 PM PDT 24
Finished Jul 12 04:35:27 PM PDT 24
Peak memory 219232 kb
Host smart-9502b667-e4e3-4f4f-a8d4-1d83a4631afa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1640384538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1640384538
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.442434043
Short name T358
Test name
Test status
Simulation time 7399684909 ps
CPU time 61.83 seconds
Started Jul 12 04:34:59 PM PDT 24
Finished Jul 12 04:36:03 PM PDT 24
Peak memory 216348 kb
Host smart-c3ff6c3a-7e15-470b-8f0d-0deb7e8320c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442434043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.442434043
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2211385678
Short name T126
Test name
Test status
Simulation time 4064720766 ps
CPU time 17.12 seconds
Started Jul 12 04:34:59 PM PDT 24
Finished Jul 12 04:35:19 PM PDT 24
Peak memory 214424 kb
Host smart-6592b461-ec03-4df4-b2a2-b4e42207a58e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211385678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2211385678
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.509934591
Short name T302
Test name
Test status
Simulation time 174456264 ps
CPU time 8.12 seconds
Started Jul 12 04:35:04 PM PDT 24
Finished Jul 12 04:35:14 PM PDT 24
Peak memory 217112 kb
Host smart-ffb638f3-edc5-4918-9849-635fc037eac2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509934591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.509934591
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2243378913
Short name T149
Test name
Test status
Simulation time 8887167339 ps
CPU time 69.14 seconds
Started Jul 12 04:35:01 PM PDT 24
Finished Jul 12 04:36:13 PM PDT 24
Peak memory 219296 kb
Host smart-6857e706-4049-4fa2-a3a2-4b0e4a970437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243378913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2243378913
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.4090439196
Short name T315
Test name
Test status
Simulation time 748489950 ps
CPU time 15.28 seconds
Started Jul 12 04:35:15 PM PDT 24
Finished Jul 12 04:35:32 PM PDT 24
Peak memory 211616 kb
Host smart-feddde9a-b3fb-4247-9423-9a11aa4a9e45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4090439196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.4090439196
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3169718226
Short name T79
Test name
Test status
Simulation time 1786208376 ps
CPU time 20.59 seconds
Started Jul 12 04:34:59 PM PDT 24
Finished Jul 12 04:35:22 PM PDT 24
Peak memory 216136 kb
Host smart-ecb6c5a0-806e-4fd2-9353-e014f9685131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169718226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3169718226
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.611988917
Short name T226
Test name
Test status
Simulation time 7827991433 ps
CPU time 76.95 seconds
Started Jul 12 04:35:06 PM PDT 24
Finished Jul 12 04:36:24 PM PDT 24
Peak memory 219332 kb
Host smart-fa7bb494-5bcf-4afa-8ad7-14a3cb74d5d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611988917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.611988917
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1300157818
Short name T280
Test name
Test status
Simulation time 64859523776 ps
CPU time 598.48 seconds
Started Jul 12 04:35:12 PM PDT 24
Finished Jul 12 04:45:12 PM PDT 24
Peak memory 219448 kb
Host smart-d6934727-5f94-48da-a8d1-f5a563eb472d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300157818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1300157818
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2785834072
Short name T329
Test name
Test status
Simulation time 2289093742 ps
CPU time 27.91 seconds
Started Jul 12 04:35:02 PM PDT 24
Finished Jul 12 04:35:32 PM PDT 24
Peak memory 219252 kb
Host smart-22a4f07b-1cb1-4a12-acbd-25c45074f55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785834072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2785834072
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.867858184
Short name T187
Test name
Test status
Simulation time 182141266 ps
CPU time 10.27 seconds
Started Jul 12 04:35:00 PM PDT 24
Finished Jul 12 04:35:12 PM PDT 24
Peak memory 219192 kb
Host smart-44d1413c-ffcb-4be7-b150-fe6a35f835da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=867858184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.867858184
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1918705870
Short name T185
Test name
Test status
Simulation time 59850926008 ps
CPU time 57.15 seconds
Started Jul 12 04:35:22 PM PDT 24
Finished Jul 12 04:36:21 PM PDT 24
Peak memory 216620 kb
Host smart-7c4e6f7e-e241-48e1-a4fd-07a677312f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918705870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1918705870
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2427094508
Short name T213
Test name
Test status
Simulation time 2345878275 ps
CPU time 11.43 seconds
Started Jul 12 04:35:08 PM PDT 24
Finished Jul 12 04:35:21 PM PDT 24
Peak memory 214552 kb
Host smart-52f9e7c0-d279-4663-979c-c5fbc6dc958f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427094508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2427094508
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2580360367
Short name T337
Test name
Test status
Simulation time 635259675 ps
CPU time 8.29 seconds
Started Jul 12 04:35:04 PM PDT 24
Finished Jul 12 04:35:14 PM PDT 24
Peak memory 213172 kb
Host smart-8a80f2d9-4767-4cad-8dfb-3fedac6dfb1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580360367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2580360367
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2700409251
Short name T180
Test name
Test status
Simulation time 40810669188 ps
CPU time 272.89 seconds
Started Jul 12 04:35:16 PM PDT 24
Finished Jul 12 04:39:50 PM PDT 24
Peak memory 224660 kb
Host smart-ae45fe87-5c89-4bc1-8ba2-a0b75e629389
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700409251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2700409251
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2181390790
Short name T23
Test name
Test status
Simulation time 1005030761 ps
CPU time 25.09 seconds
Started Jul 12 04:35:02 PM PDT 24
Finished Jul 12 04:35:29 PM PDT 24
Peak memory 219180 kb
Host smart-ff72ffce-de76-4e12-917b-3791a873ca99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181390790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2181390790
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1069613960
Short name T335
Test name
Test status
Simulation time 3291304933 ps
CPU time 20.68 seconds
Started Jul 12 04:35:08 PM PDT 24
Finished Jul 12 04:35:29 PM PDT 24
Peak memory 219552 kb
Host smart-87c40095-60cb-4e11-a10f-04268f018ff6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1069613960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1069613960
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3971355847
Short name T14
Test name
Test status
Simulation time 846327845 ps
CPU time 26.42 seconds
Started Jul 12 04:35:17 PM PDT 24
Finished Jul 12 04:35:44 PM PDT 24
Peak memory 216148 kb
Host smart-79836e81-86c9-4a4a-be24-c3b039a639fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971355847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3971355847
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.901591822
Short name T266
Test name
Test status
Simulation time 52663676357 ps
CPU time 129.02 seconds
Started Jul 12 04:35:22 PM PDT 24
Finished Jul 12 04:37:33 PM PDT 24
Peak memory 219424 kb
Host smart-b63afb84-d1fa-4076-9f89-6f579a478250
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901591822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.901591822
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.759604619
Short name T362
Test name
Test status
Simulation time 1479381248 ps
CPU time 17.06 seconds
Started Jul 12 04:35:11 PM PDT 24
Finished Jul 12 04:35:30 PM PDT 24
Peak memory 216804 kb
Host smart-5b04bd0b-e864-45eb-9a28-4e596db9365f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759604619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.759604619
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.90342054
Short name T127
Test name
Test status
Simulation time 15827420728 ps
CPU time 268.23 seconds
Started Jul 12 04:35:02 PM PDT 24
Finished Jul 12 04:39:33 PM PDT 24
Peak memory 235836 kb
Host smart-f344f241-16ad-4ee2-9358-74e93dbdd070
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90342054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_co
rrupt_sig_fatal_chk.90342054
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3003392578
Short name T260
Test name
Test status
Simulation time 28703640772 ps
CPU time 34.12 seconds
Started Jul 12 04:35:03 PM PDT 24
Finished Jul 12 04:35:39 PM PDT 24
Peak memory 215552 kb
Host smart-2c396c5e-85d0-4b24-844f-6a56fb669340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003392578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3003392578
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1768813153
Short name T265
Test name
Test status
Simulation time 1949736623 ps
CPU time 10.53 seconds
Started Jul 12 04:35:05 PM PDT 24
Finished Jul 12 04:35:17 PM PDT 24
Peak memory 219184 kb
Host smart-3383b302-92d4-4da7-936d-ccaa27cb2e08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1768813153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1768813153
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1953460292
Short name T326
Test name
Test status
Simulation time 42289000301 ps
CPU time 38.66 seconds
Started Jul 12 04:35:20 PM PDT 24
Finished Jul 12 04:36:00 PM PDT 24
Peak memory 216924 kb
Host smart-591ee769-0390-450a-95b3-b93d1cfb1a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953460292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1953460292
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1614120932
Short name T262
Test name
Test status
Simulation time 6721916720 ps
CPU time 74.35 seconds
Started Jul 12 04:35:12 PM PDT 24
Finished Jul 12 04:36:28 PM PDT 24
Peak memory 220480 kb
Host smart-8405232e-aec8-472e-bb80-6945dea3228e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614120932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1614120932
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.842247111
Short name T168
Test name
Test status
Simulation time 167340664 ps
CPU time 8.27 seconds
Started Jul 12 04:35:15 PM PDT 24
Finished Jul 12 04:35:25 PM PDT 24
Peak memory 218104 kb
Host smart-3714aaed-9b41-4037-a866-538be9f5425b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842247111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.842247111
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2170906910
Short name T151
Test name
Test status
Simulation time 96596243897 ps
CPU time 973.78 seconds
Started Jul 12 04:35:12 PM PDT 24
Finished Jul 12 04:51:27 PM PDT 24
Peak memory 234144 kb
Host smart-34ba7c98-e806-4be5-9f07-6f6f86073a5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170906910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2170906910
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.763037314
Short name T247
Test name
Test status
Simulation time 9736222623 ps
CPU time 68.15 seconds
Started Jul 12 04:35:04 PM PDT 24
Finished Jul 12 04:36:14 PM PDT 24
Peak memory 219232 kb
Host smart-3713518b-37d0-4946-9245-28741fcf7606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763037314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.763037314
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3249676704
Short name T259
Test name
Test status
Simulation time 3077191052 ps
CPU time 28.17 seconds
Started Jul 12 04:35:03 PM PDT 24
Finished Jul 12 04:35:33 PM PDT 24
Peak memory 211620 kb
Host smart-2fbc7bab-425a-491d-a6a1-aea19fa6b466
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3249676704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3249676704
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.880014568
Short name T309
Test name
Test status
Simulation time 691813554 ps
CPU time 19.86 seconds
Started Jul 12 04:35:11 PM PDT 24
Finished Jul 12 04:35:32 PM PDT 24
Peak memory 216176 kb
Host smart-22ea4bbb-6c1d-4a3d-adc1-3ec001fe3466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880014568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.880014568
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1603739457
Short name T277
Test name
Test status
Simulation time 399678532 ps
CPU time 31.88 seconds
Started Jul 12 04:35:01 PM PDT 24
Finished Jul 12 04:35:35 PM PDT 24
Peak memory 219220 kb
Host smart-d8de5313-ff96-4e2c-967f-c09982efea70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603739457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1603739457
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1410301962
Short name T13
Test name
Test status
Simulation time 138816894066 ps
CPU time 1777.32 seconds
Started Jul 12 04:35:08 PM PDT 24
Finished Jul 12 05:04:47 PM PDT 24
Peak memory 244580 kb
Host smart-053f3474-01e8-40ac-9e1d-e1e23efc0a46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410301962 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.1410301962
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.430632431
Short name T231
Test name
Test status
Simulation time 174191023 ps
CPU time 8.23 seconds
Started Jul 12 04:34:41 PM PDT 24
Finished Jul 12 04:34:54 PM PDT 24
Peak memory 217072 kb
Host smart-ff12e535-c153-4b08-a408-da6a1183e3c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430632431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.430632431
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2916772111
Short name T170
Test name
Test status
Simulation time 128687839468 ps
CPU time 374.71 seconds
Started Jul 12 04:34:49 PM PDT 24
Finished Jul 12 04:41:06 PM PDT 24
Peak memory 225896 kb
Host smart-edddd830-a7f9-4e5a-ac18-382bf355b2ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916772111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2916772111
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3292598794
Short name T307
Test name
Test status
Simulation time 23260671064 ps
CPU time 36.95 seconds
Started Jul 12 04:34:48 PM PDT 24
Finished Jul 12 04:35:28 PM PDT 24
Peak memory 218696 kb
Host smart-f6c36b30-2a0f-4003-9ec6-687c75670c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292598794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3292598794
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3110280438
Short name T178
Test name
Test status
Simulation time 545509864 ps
CPU time 10.77 seconds
Started Jul 12 04:34:37 PM PDT 24
Finished Jul 12 04:34:53 PM PDT 24
Peak memory 219172 kb
Host smart-5504648f-847b-4ed0-a48e-0e5026e16808
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3110280438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3110280438
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.580584833
Short name T18
Test name
Test status
Simulation time 15341007654 ps
CPU time 140.54 seconds
Started Jul 12 04:34:38 PM PDT 24
Finished Jul 12 04:37:04 PM PDT 24
Peak memory 236348 kb
Host smart-a58a9d3e-6e2b-47fe-90ff-2c3b5c400c46
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580584833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.580584833
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1473461225
Short name T235
Test name
Test status
Simulation time 3958255183 ps
CPU time 43.85 seconds
Started Jul 12 04:34:41 PM PDT 24
Finished Jul 12 04:35:29 PM PDT 24
Peak memory 215572 kb
Host smart-0b865571-2982-4aea-9aa7-e1fb6dd29f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473461225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1473461225
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1328902749
Short name T9
Test name
Test status
Simulation time 8425605094 ps
CPU time 56.62 seconds
Started Jul 12 04:34:47 PM PDT 24
Finished Jul 12 04:35:47 PM PDT 24
Peak memory 218240 kb
Host smart-4ddc68e8-d602-429b-9b12-7bb631ef7b99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328902749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1328902749
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2163156747
Short name T229
Test name
Test status
Simulation time 41864144547 ps
CPU time 34.15 seconds
Started Jul 12 04:35:10 PM PDT 24
Finished Jul 12 04:35:45 PM PDT 24
Peak memory 217484 kb
Host smart-ee918f8b-07b5-4fc5-9406-39b854800c28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163156747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2163156747
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.136863923
Short name T285
Test name
Test status
Simulation time 12065246109 ps
CPU time 290.51 seconds
Started Jul 12 04:35:08 PM PDT 24
Finished Jul 12 04:40:00 PM PDT 24
Peak memory 217972 kb
Host smart-5a326791-af91-4027-a993-a6536c280058
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136863923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.136863923
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.112840495
Short name T289
Test name
Test status
Simulation time 43181773822 ps
CPU time 55.15 seconds
Started Jul 12 04:35:19 PM PDT 24
Finished Jul 12 04:36:15 PM PDT 24
Peak memory 219324 kb
Host smart-4544d877-6868-4345-9643-b8b7275bd1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112840495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.112840495
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.632207093
Short name T251
Test name
Test status
Simulation time 178028639 ps
CPU time 10.44 seconds
Started Jul 12 04:35:14 PM PDT 24
Finished Jul 12 04:35:26 PM PDT 24
Peak memory 219212 kb
Host smart-1c1b301c-0754-4403-b657-f1984f83dca6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=632207093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.632207093
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.4272166233
Short name T295
Test name
Test status
Simulation time 5198530602 ps
CPU time 52.54 seconds
Started Jul 12 04:35:01 PM PDT 24
Finished Jul 12 04:35:56 PM PDT 24
Peak memory 216908 kb
Host smart-f1d21a96-ef2e-456c-a471-a0160ff85a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272166233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.4272166233
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2046008840
Short name T240
Test name
Test status
Simulation time 722972105 ps
CPU time 44.04 seconds
Started Jul 12 04:35:05 PM PDT 24
Finished Jul 12 04:35:50 PM PDT 24
Peak memory 219248 kb
Host smart-ff7aab71-8ca0-4073-a2f6-967aba0cc4ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046008840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2046008840
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.373757820
Short name T339
Test name
Test status
Simulation time 3292181252 ps
CPU time 12.27 seconds
Started Jul 12 04:34:59 PM PDT 24
Finished Jul 12 04:35:14 PM PDT 24
Peak memory 217092 kb
Host smart-d2351a0e-902d-477e-a5f6-78a9d3865974
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373757820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.373757820
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3052260860
Short name T2
Test name
Test status
Simulation time 8019337239 ps
CPU time 65.44 seconds
Started Jul 12 04:35:08 PM PDT 24
Finished Jul 12 04:36:15 PM PDT 24
Peak memory 219204 kb
Host smart-7422dd70-0802-4737-9d4c-6472f339281d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052260860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3052260860
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2782837101
Short name T290
Test name
Test status
Simulation time 11899980246 ps
CPU time 25.92 seconds
Started Jul 12 04:35:11 PM PDT 24
Finished Jul 12 04:35:38 PM PDT 24
Peak memory 211644 kb
Host smart-013bd2fc-f49b-49cf-9470-6382f2b683d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2782837101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2782837101
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.4254430661
Short name T34
Test name
Test status
Simulation time 3484144483 ps
CPU time 32.48 seconds
Started Jul 12 04:35:01 PM PDT 24
Finished Jul 12 04:35:35 PM PDT 24
Peak memory 216224 kb
Host smart-c147f7fb-f087-4db9-99cd-52bbb57ce77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254430661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.4254430661
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2932347115
Short name T164
Test name
Test status
Simulation time 31807861225 ps
CPU time 97.91 seconds
Started Jul 12 04:35:05 PM PDT 24
Finished Jul 12 04:36:44 PM PDT 24
Peak memory 220440 kb
Host smart-c046a4be-c46e-4b1b-87c0-08e04aef9c5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932347115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2932347115
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3742579098
Short name T167
Test name
Test status
Simulation time 6640171302 ps
CPU time 19.32 seconds
Started Jul 12 04:35:00 PM PDT 24
Finished Jul 12 04:35:22 PM PDT 24
Peak memory 217452 kb
Host smart-66d878eb-cc94-497c-b8c7-30d1813a96f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742579098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3742579098
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3817216307
Short name T148
Test name
Test status
Simulation time 31796166833 ps
CPU time 341.61 seconds
Started Jul 12 04:35:12 PM PDT 24
Finished Jul 12 04:40:55 PM PDT 24
Peak memory 218544 kb
Host smart-67620931-0241-4064-b81c-dca0d875ff30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817216307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3817216307
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.293543580
Short name T210
Test name
Test status
Simulation time 18337945755 ps
CPU time 48.69 seconds
Started Jul 12 04:35:08 PM PDT 24
Finished Jul 12 04:35:58 PM PDT 24
Peak memory 219072 kb
Host smart-eebc5e5d-4c18-4d3b-a22f-33cfeb6bc406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293543580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.293543580
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1670993147
Short name T106
Test name
Test status
Simulation time 1438569730 ps
CPU time 10.37 seconds
Started Jul 12 04:35:11 PM PDT 24
Finished Jul 12 04:35:22 PM PDT 24
Peak memory 219200 kb
Host smart-a9776f87-4525-44c7-8670-1c389b5b1ad5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1670993147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1670993147
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.4100770559
Short name T323
Test name
Test status
Simulation time 8208038503 ps
CPU time 80.36 seconds
Started Jul 12 04:35:15 PM PDT 24
Finished Jul 12 04:36:37 PM PDT 24
Peak memory 216560 kb
Host smart-3eedb53d-3f1b-499d-8bb3-b80757da68b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100770559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.4100770559
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.710376884
Short name T191
Test name
Test status
Simulation time 3103144293 ps
CPU time 56.05 seconds
Started Jul 12 04:35:11 PM PDT 24
Finished Jul 12 04:36:08 PM PDT 24
Peak memory 219728 kb
Host smart-a9e97b6a-6940-4210-bb46-a7ec462412e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710376884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.710376884
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1459201482
Short name T20
Test name
Test status
Simulation time 1646356617 ps
CPU time 8.39 seconds
Started Jul 12 04:35:01 PM PDT 24
Finished Jul 12 04:35:12 PM PDT 24
Peak memory 216836 kb
Host smart-af02ebbe-2e97-4fa8-aecd-ca069793dfc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459201482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1459201482
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.741761471
Short name T270
Test name
Test status
Simulation time 14746297383 ps
CPU time 235.28 seconds
Started Jul 12 04:35:01 PM PDT 24
Finished Jul 12 04:38:58 PM PDT 24
Peak memory 234448 kb
Host smart-4eb33421-845f-4016-a716-a6a7d8ced2ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741761471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.741761471
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1359375536
Short name T137
Test name
Test status
Simulation time 4121589574 ps
CPU time 24.75 seconds
Started Jul 12 04:35:09 PM PDT 24
Finished Jul 12 04:35:35 PM PDT 24
Peak memory 215824 kb
Host smart-0adeb346-f27b-4375-be81-6d04fce54610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359375536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1359375536
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.342822643
Short name T197
Test name
Test status
Simulation time 439923627 ps
CPU time 13.47 seconds
Started Jul 12 04:35:19 PM PDT 24
Finished Jul 12 04:35:33 PM PDT 24
Peak memory 218384 kb
Host smart-1559ace6-12ad-461c-8efb-ca0ac2ff32ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=342822643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.342822643
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3108232253
Short name T317
Test name
Test status
Simulation time 4849905524 ps
CPU time 54.76 seconds
Started Jul 12 04:35:01 PM PDT 24
Finished Jul 12 04:35:58 PM PDT 24
Peak memory 216188 kb
Host smart-bbbb8664-add4-4f2c-b819-c6cdf30e2a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108232253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3108232253
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2376160797
Short name T131
Test name
Test status
Simulation time 22112865052 ps
CPU time 25.97 seconds
Started Jul 12 04:34:58 PM PDT 24
Finished Jul 12 04:35:27 PM PDT 24
Peak memory 219072 kb
Host smart-4a350482-b063-4268-80e5-60711f8f59a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376160797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2376160797
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2675656354
Short name T143
Test name
Test status
Simulation time 7561197117 ps
CPU time 20.43 seconds
Started Jul 12 04:35:14 PM PDT 24
Finished Jul 12 04:35:36 PM PDT 24
Peak memory 213484 kb
Host smart-9c88e2c2-c590-4a88-9ab6-1fa561cde604
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675656354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2675656354
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1329870726
Short name T356
Test name
Test status
Simulation time 12663083438 ps
CPU time 348.35 seconds
Started Jul 12 04:36:16 PM PDT 24
Finished Jul 12 04:42:09 PM PDT 24
Peak memory 242684 kb
Host smart-2368153a-2cbe-4e05-ad69-0b501d639852
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329870726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1329870726
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2952873698
Short name T238
Test name
Test status
Simulation time 98468815142 ps
CPU time 60.05 seconds
Started Jul 12 04:35:19 PM PDT 24
Finished Jul 12 04:36:21 PM PDT 24
Peak memory 219264 kb
Host smart-1c8834e9-ec27-4f8c-8182-f50187fce21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952873698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2952873698
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3236391976
Short name T199
Test name
Test status
Simulation time 3601374876 ps
CPU time 29.92 seconds
Started Jul 12 04:35:27 PM PDT 24
Finished Jul 12 04:36:03 PM PDT 24
Peak memory 219268 kb
Host smart-2284b39c-db86-4ff6-99d2-c4ec3582e25c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3236391976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3236391976
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.536446633
Short name T354
Test name
Test status
Simulation time 4033885370 ps
CPU time 51.05 seconds
Started Jul 12 04:35:02 PM PDT 24
Finished Jul 12 04:35:55 PM PDT 24
Peak memory 215972 kb
Host smart-f1e96f3b-e61b-4d3f-bb32-e3790adc6ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536446633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.536446633
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.512866142
Short name T227
Test name
Test status
Simulation time 28572299666 ps
CPU time 65.47 seconds
Started Jul 12 04:35:27 PM PDT 24
Finished Jul 12 04:36:39 PM PDT 24
Peak memory 217840 kb
Host smart-680904b4-2096-4a92-98d1-46a1fe5f37ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512866142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.512866142
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2331950678
Short name T272
Test name
Test status
Simulation time 4091913573 ps
CPU time 30.51 seconds
Started Jul 12 04:35:10 PM PDT 24
Finished Jul 12 04:35:42 PM PDT 24
Peak memory 217196 kb
Host smart-d4926a27-7c8e-45f6-97f3-d866784e819f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331950678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2331950678
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1217433004
Short name T50
Test name
Test status
Simulation time 3035316546 ps
CPU time 220.74 seconds
Started Jul 12 04:35:17 PM PDT 24
Finished Jul 12 04:38:59 PM PDT 24
Peak memory 239544 kb
Host smart-f13bb8aa-2c28-480a-8d26-417df89b6bc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217433004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1217433004
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1475876046
Short name T216
Test name
Test status
Simulation time 9899966180 ps
CPU time 47.95 seconds
Started Jul 12 04:35:28 PM PDT 24
Finished Jul 12 04:36:25 PM PDT 24
Peak memory 219148 kb
Host smart-4470474a-aa7e-431c-81c8-32a718a91d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475876046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1475876046
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2461399630
Short name T208
Test name
Test status
Simulation time 1257511873 ps
CPU time 18.02 seconds
Started Jul 12 04:35:15 PM PDT 24
Finished Jul 12 04:35:35 PM PDT 24
Peak memory 211196 kb
Host smart-5dd9c07c-9661-4be8-95dc-e077e096949b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2461399630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2461399630
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.708055554
Short name T171
Test name
Test status
Simulation time 5297758053 ps
CPU time 59.13 seconds
Started Jul 12 04:35:20 PM PDT 24
Finished Jul 12 04:36:21 PM PDT 24
Peak memory 216412 kb
Host smart-1dcd486e-d953-48ad-8649-85043b891a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708055554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.708055554
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2394156537
Short name T258
Test name
Test status
Simulation time 5757608824 ps
CPU time 82.75 seconds
Started Jul 12 04:35:24 PM PDT 24
Finished Jul 12 04:36:49 PM PDT 24
Peak memory 227504 kb
Host smart-a8ca7957-a46e-4952-b10c-20fcdea73da0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394156537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2394156537
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3281842745
Short name T158
Test name
Test status
Simulation time 174347002 ps
CPU time 8.03 seconds
Started Jul 12 04:35:28 PM PDT 24
Finished Jul 12 04:35:44 PM PDT 24
Peak memory 216960 kb
Host smart-0d32dada-5270-4104-97bb-99b55cff1b19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281842745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3281842745
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2643858694
Short name T145
Test name
Test status
Simulation time 9132960549 ps
CPU time 141.61 seconds
Started Jul 12 04:35:13 PM PDT 24
Finished Jul 12 04:37:37 PM PDT 24
Peak memory 225128 kb
Host smart-05d9c29e-408d-4d05-8f6e-b34e4ccd4ac6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643858694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2643858694
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.353760569
Short name T221
Test name
Test status
Simulation time 1910141759 ps
CPU time 22.42 seconds
Started Jul 12 04:35:20 PM PDT 24
Finished Jul 12 04:35:44 PM PDT 24
Peak memory 219208 kb
Host smart-3231ffac-9538-48e9-97b5-e5aa3cf0a9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353760569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.353760569
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.654860285
Short name T336
Test name
Test status
Simulation time 12482119272 ps
CPU time 27.7 seconds
Started Jul 12 04:35:26 PM PDT 24
Finished Jul 12 04:35:58 PM PDT 24
Peak memory 211880 kb
Host smart-b7289fc1-a061-4342-b348-4b41a7f5eab2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=654860285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.654860285
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1164575542
Short name T316
Test name
Test status
Simulation time 2892546493 ps
CPU time 25.45 seconds
Started Jul 12 04:35:21 PM PDT 24
Finished Jul 12 04:35:48 PM PDT 24
Peak memory 217284 kb
Host smart-bbb1d3cc-f65d-4cb6-9887-81dbd1344c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164575542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1164575542
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3794524447
Short name T169
Test name
Test status
Simulation time 124502927579 ps
CPU time 114.51 seconds
Started Jul 12 04:35:15 PM PDT 24
Finished Jul 12 04:37:11 PM PDT 24
Peak memory 219720 kb
Host smart-a02c2692-107b-4226-823f-2abfa4b3a91f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794524447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3794524447
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.3437123863
Short name T52
Test name
Test status
Simulation time 100535259572 ps
CPU time 9731.06 seconds
Started Jul 12 04:35:14 PM PDT 24
Finished Jul 12 07:17:27 PM PDT 24
Peak memory 243936 kb
Host smart-536eb62f-42ef-4686-84ea-f1c6915f80ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437123863 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.3437123863
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1543438841
Short name T263
Test name
Test status
Simulation time 7815734482 ps
CPU time 19.58 seconds
Started Jul 12 04:35:30 PM PDT 24
Finished Jul 12 04:36:00 PM PDT 24
Peak memory 217592 kb
Host smart-d450ac27-66f0-4f2a-bc1f-fee4e5260e70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543438841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1543438841
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.324976321
Short name T312
Test name
Test status
Simulation time 6988046412 ps
CPU time 245.05 seconds
Started Jul 12 04:35:13 PM PDT 24
Finished Jul 12 04:39:19 PM PDT 24
Peak memory 233952 kb
Host smart-b4087a76-04c1-4478-b863-52e780ad5935
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324976321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.324976321
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.543716916
Short name T135
Test name
Test status
Simulation time 7487951299 ps
CPU time 65.24 seconds
Started Jul 12 04:35:20 PM PDT 24
Finished Jul 12 04:36:27 PM PDT 24
Peak memory 219220 kb
Host smart-05a64d33-5251-4835-8760-a84acb9545c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543716916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.543716916
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2608051583
Short name T273
Test name
Test status
Simulation time 359140370 ps
CPU time 10.31 seconds
Started Jul 12 04:35:24 PM PDT 24
Finished Jul 12 04:35:36 PM PDT 24
Peak memory 219172 kb
Host smart-f2985952-70b2-41f6-90cf-fa3e30fb8dfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2608051583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2608051583
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.290231144
Short name T304
Test name
Test status
Simulation time 360518147 ps
CPU time 19.5 seconds
Started Jul 12 04:35:20 PM PDT 24
Finished Jul 12 04:35:41 PM PDT 24
Peak memory 216164 kb
Host smart-5ab80158-3f53-48bd-9085-772708336692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290231144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.290231144
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3590707794
Short name T320
Test name
Test status
Simulation time 3183238012 ps
CPU time 23.76 seconds
Started Jul 12 04:35:08 PM PDT 24
Finished Jul 12 04:35:33 PM PDT 24
Peak memory 219280 kb
Host smart-0a039523-fe8c-4441-ab86-7d05fe3e7f15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590707794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3590707794
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3149185560
Short name T271
Test name
Test status
Simulation time 25448215128 ps
CPU time 28.64 seconds
Started Jul 12 04:35:15 PM PDT 24
Finished Jul 12 04:35:46 PM PDT 24
Peak memory 217544 kb
Host smart-9ba76592-640b-4568-9938-7ac3421e02dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149185560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3149185560
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1752605907
Short name T193
Test name
Test status
Simulation time 6812619277 ps
CPU time 356.92 seconds
Started Jul 12 04:35:10 PM PDT 24
Finished Jul 12 04:41:08 PM PDT 24
Peak memory 236536 kb
Host smart-1b7ee867-bcf5-4300-8b22-e53b8c8cbee6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752605907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1752605907
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.651622706
Short name T28
Test name
Test status
Simulation time 346056011 ps
CPU time 18.91 seconds
Started Jul 12 04:35:23 PM PDT 24
Finished Jul 12 04:35:44 PM PDT 24
Peak memory 219200 kb
Host smart-a993345d-5dca-4e70-a44b-9ab789d5a0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651622706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.651622706
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1376461328
Short name T220
Test name
Test status
Simulation time 690412064 ps
CPU time 9.97 seconds
Started Jul 12 04:35:11 PM PDT 24
Finished Jul 12 04:35:22 PM PDT 24
Peak memory 219192 kb
Host smart-13636439-2f8b-4766-b3c7-acf6c670add8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1376461328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1376461328
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2843378625
Short name T33
Test name
Test status
Simulation time 4419349557 ps
CPU time 45.28 seconds
Started Jul 12 04:35:26 PM PDT 24
Finished Jul 12 04:36:15 PM PDT 24
Peak memory 216536 kb
Host smart-739f74d6-59e8-4e83-bd35-ba9552172f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843378625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2843378625
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1585947894
Short name T324
Test name
Test status
Simulation time 1246269107 ps
CPU time 16.43 seconds
Started Jul 12 04:35:13 PM PDT 24
Finished Jul 12 04:35:31 PM PDT 24
Peak memory 217044 kb
Host smart-1ff5dd07-141f-4ae9-85b0-8b7fbbcf8db8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585947894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1585947894
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1451293163
Short name T361
Test name
Test status
Simulation time 232994377700 ps
CPU time 351.11 seconds
Started Jul 12 04:35:25 PM PDT 24
Finished Jul 12 04:41:20 PM PDT 24
Peak memory 236876 kb
Host smart-f53588d3-406c-400d-9172-e96f216e76ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451293163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1451293163
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.319091632
Short name T209
Test name
Test status
Simulation time 24215266908 ps
CPU time 55.67 seconds
Started Jul 12 04:35:18 PM PDT 24
Finished Jul 12 04:36:15 PM PDT 24
Peak memory 219236 kb
Host smart-06a7c15b-a90d-492a-91fa-1d9964b1b0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319091632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.319091632
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2416276704
Short name T15
Test name
Test status
Simulation time 2999194227 ps
CPU time 26.26 seconds
Started Jul 12 04:35:11 PM PDT 24
Finished Jul 12 04:35:38 PM PDT 24
Peak memory 211304 kb
Host smart-3f04f956-afce-4d29-be43-0c39863ffc5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2416276704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2416276704
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3294353108
Short name T130
Test name
Test status
Simulation time 2015250065 ps
CPU time 19.68 seconds
Started Jul 12 04:35:17 PM PDT 24
Finished Jul 12 04:35:38 PM PDT 24
Peak memory 216492 kb
Host smart-ec2df005-cb48-433c-b7cc-35fc2951c164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294353108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3294353108
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.4163741909
Short name T10
Test name
Test status
Simulation time 4503043570 ps
CPU time 80.48 seconds
Started Jul 12 04:35:08 PM PDT 24
Finished Jul 12 04:36:29 PM PDT 24
Peak memory 219304 kb
Host smart-ee6b5ae7-ce12-4ea8-b202-003b52da15de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163741909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.4163741909
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1623412071
Short name T21
Test name
Test status
Simulation time 12067893124 ps
CPU time 25.02 seconds
Started Jul 12 04:34:47 PM PDT 24
Finished Jul 12 04:35:16 PM PDT 24
Peak memory 217348 kb
Host smart-276568fe-75a5-4618-86ea-fe661d3fd121
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623412071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1623412071
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2917393805
Short name T8
Test name
Test status
Simulation time 2787500372 ps
CPU time 162.51 seconds
Started Jul 12 04:34:44 PM PDT 24
Finished Jul 12 04:37:31 PM PDT 24
Peak memory 218084 kb
Host smart-8af49e60-e051-4de0-a0ea-c76b75329430
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917393805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2917393805
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2556311165
Short name T44
Test name
Test status
Simulation time 346344486 ps
CPU time 19.54 seconds
Started Jul 12 04:34:44 PM PDT 24
Finished Jul 12 04:35:08 PM PDT 24
Peak memory 219408 kb
Host smart-7c1d9c7f-eaeb-466a-9f2d-9b80d3ba0c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556311165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2556311165
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3372730790
Short name T177
Test name
Test status
Simulation time 5303091409 ps
CPU time 24.97 seconds
Started Jul 12 04:34:48 PM PDT 24
Finished Jul 12 04:35:16 PM PDT 24
Peak memory 219288 kb
Host smart-38ae380b-53af-406a-9941-5096cf96b606
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3372730790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3372730790
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3724532596
Short name T19
Test name
Test status
Simulation time 3635616804 ps
CPU time 136.73 seconds
Started Jul 12 04:34:41 PM PDT 24
Finished Jul 12 04:37:03 PM PDT 24
Peak memory 235820 kb
Host smart-3c1fd7f5-a929-42c0-9265-9dfe03195eb2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724532596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3724532596
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.648399618
Short name T1
Test name
Test status
Simulation time 2675357076 ps
CPU time 29.08 seconds
Started Jul 12 04:34:41 PM PDT 24
Finished Jul 12 04:35:16 PM PDT 24
Peak memory 216348 kb
Host smart-d3bd11ba-6266-49c2-bcb4-6b70ba490dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648399618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.648399618
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.978403077
Short name T190
Test name
Test status
Simulation time 19846292417 ps
CPU time 120.91 seconds
Started Jul 12 04:34:44 PM PDT 24
Finished Jul 12 04:36:49 PM PDT 24
Peak memory 227480 kb
Host smart-863eb07a-f320-42f3-b15b-5a505b5ecc45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978403077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.978403077
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3523728355
Short name T269
Test name
Test status
Simulation time 591507163 ps
CPU time 8.49 seconds
Started Jul 12 04:35:09 PM PDT 24
Finished Jul 12 04:35:19 PM PDT 24
Peak memory 216988 kb
Host smart-4b49188d-3f47-462c-9dad-63d8755c41e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523728355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3523728355
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.732593987
Short name T274
Test name
Test status
Simulation time 301365116364 ps
CPU time 719.95 seconds
Started Jul 12 04:35:08 PM PDT 24
Finished Jul 12 04:47:09 PM PDT 24
Peak memory 233772 kb
Host smart-c57a9960-e707-42a7-bddb-18766322b47c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732593987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.732593987
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2009150805
Short name T314
Test name
Test status
Simulation time 20424595287 ps
CPU time 65.8 seconds
Started Jul 12 04:35:20 PM PDT 24
Finished Jul 12 04:36:27 PM PDT 24
Peak memory 219248 kb
Host smart-08cf9c82-dcda-4df9-962f-ccdc8817d508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009150805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2009150805
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2509436397
Short name T161
Test name
Test status
Simulation time 15564927220 ps
CPU time 32.61 seconds
Started Jul 12 04:35:22 PM PDT 24
Finished Jul 12 04:35:56 PM PDT 24
Peak memory 211956 kb
Host smart-4945daa2-d46b-4791-86d5-17414fe19a8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2509436397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2509436397
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1228466379
Short name T253
Test name
Test status
Simulation time 4924595015 ps
CPU time 39.79 seconds
Started Jul 12 04:35:10 PM PDT 24
Finished Jul 12 04:35:51 PM PDT 24
Peak memory 216752 kb
Host smart-80c4fc13-1fa7-41d9-a9ae-40575cdb539d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228466379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1228466379
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1464564290
Short name T163
Test name
Test status
Simulation time 65757811965 ps
CPU time 59.88 seconds
Started Jul 12 04:35:23 PM PDT 24
Finished Jul 12 04:36:24 PM PDT 24
Peak memory 217132 kb
Host smart-5ec1c39a-4d9b-490e-9634-d90b44e99f80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464564290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1464564290
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.420831139
Short name T286
Test name
Test status
Simulation time 4287371459 ps
CPU time 20.61 seconds
Started Jul 12 04:35:24 PM PDT 24
Finished Jul 12 04:35:48 PM PDT 24
Peak memory 213204 kb
Host smart-5aef0d7f-00b9-4cd4-ab38-e6267a072c4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420831139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.420831139
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2954594501
Short name T46
Test name
Test status
Simulation time 87404768831 ps
CPU time 341.21 seconds
Started Jul 12 04:35:19 PM PDT 24
Finished Jul 12 04:41:02 PM PDT 24
Peak memory 233068 kb
Host smart-d28063f1-ba62-4953-8eb0-c57ae90739b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954594501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2954594501
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1229849613
Short name T301
Test name
Test status
Simulation time 2631135212 ps
CPU time 36.68 seconds
Started Jul 12 04:35:14 PM PDT 24
Finished Jul 12 04:35:52 PM PDT 24
Peak memory 219268 kb
Host smart-b65d8d31-c51b-4d49-8641-de2363a0b4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229849613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1229849613
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.700379586
Short name T281
Test name
Test status
Simulation time 7024274503 ps
CPU time 57.05 seconds
Started Jul 12 04:35:18 PM PDT 24
Finished Jul 12 04:36:16 PM PDT 24
Peak memory 216708 kb
Host smart-520d78f1-2421-42f1-84a3-46080a90556f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700379586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.700379586
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3732147946
Short name T181
Test name
Test status
Simulation time 4361734577 ps
CPU time 55.71 seconds
Started Jul 12 04:35:29 PM PDT 24
Finished Jul 12 04:36:33 PM PDT 24
Peak memory 220192 kb
Host smart-8fb4f1c5-f0c7-41dd-b1f8-3db11c65abf6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732147946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3732147946
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.480382797
Short name T65
Test name
Test status
Simulation time 2060516069 ps
CPU time 12.19 seconds
Started Jul 12 04:35:30 PM PDT 24
Finished Jul 12 04:35:53 PM PDT 24
Peak memory 216780 kb
Host smart-d7236709-24e2-46ba-85a8-8dd3de7df978
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480382797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.480382797
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2224900172
Short name T45
Test name
Test status
Simulation time 184103536796 ps
CPU time 439.27 seconds
Started Jul 12 04:35:09 PM PDT 24
Finished Jul 12 04:42:29 PM PDT 24
Peak memory 233776 kb
Host smart-7ed414cc-463e-48c7-baf9-1ca4b3e737ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224900172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2224900172
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2149778715
Short name T344
Test name
Test status
Simulation time 5266163172 ps
CPU time 50.88 seconds
Started Jul 12 04:35:17 PM PDT 24
Finished Jul 12 04:36:09 PM PDT 24
Peak memory 219292 kb
Host smart-0dcd60f8-c437-4d32-b264-d081debc99bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149778715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2149778715
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.572392202
Short name T284
Test name
Test status
Simulation time 24932805773 ps
CPU time 35.35 seconds
Started Jul 12 04:35:11 PM PDT 24
Finished Jul 12 04:35:47 PM PDT 24
Peak memory 219264 kb
Host smart-d2670ae5-0a0b-4e83-876e-9c5669fecf3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=572392202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.572392202
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2805999456
Short name T243
Test name
Test status
Simulation time 8407331807 ps
CPU time 42.16 seconds
Started Jul 12 04:35:27 PM PDT 24
Finished Jul 12 04:36:15 PM PDT 24
Peak memory 216776 kb
Host smart-9402b6c4-3f95-403a-ba42-84081e8c5539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805999456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2805999456
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.258713662
Short name T348
Test name
Test status
Simulation time 210431299 ps
CPU time 10.77 seconds
Started Jul 12 04:35:25 PM PDT 24
Finished Jul 12 04:35:40 PM PDT 24
Peak memory 214660 kb
Host smart-846910ad-36f3-427b-9537-80f20075106e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258713662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.258713662
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1170902011
Short name T232
Test name
Test status
Simulation time 689705077 ps
CPU time 8.42 seconds
Started Jul 12 04:35:25 PM PDT 24
Finished Jul 12 04:35:36 PM PDT 24
Peak memory 217072 kb
Host smart-ace83b1f-2a95-4d3c-aee9-780d49c8adfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170902011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1170902011
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2543241495
Short name T39
Test name
Test status
Simulation time 178807674752 ps
CPU time 504.82 seconds
Started Jul 12 04:35:21 PM PDT 24
Finished Jul 12 04:43:48 PM PDT 24
Peak memory 238768 kb
Host smart-f5be9ab9-c3b1-483e-aaa5-afbf8d8b83fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543241495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2543241495
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3035818829
Short name T48
Test name
Test status
Simulation time 3971322068 ps
CPU time 44.08 seconds
Started Jul 12 04:35:09 PM PDT 24
Finished Jul 12 04:35:54 PM PDT 24
Peak memory 219252 kb
Host smart-a41961b4-0711-4b38-9e9c-ff77dd917467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035818829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3035818829
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.4032197024
Short name T188
Test name
Test status
Simulation time 2998053307 ps
CPU time 15.18 seconds
Started Jul 12 04:35:15 PM PDT 24
Finished Jul 12 04:35:32 PM PDT 24
Peak memory 219292 kb
Host smart-baee59e7-b86d-4031-b854-3bba5e336cce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4032197024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.4032197024
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2814976019
Short name T321
Test name
Test status
Simulation time 2858899389 ps
CPU time 39.98 seconds
Started Jul 12 04:35:29 PM PDT 24
Finished Jul 12 04:36:17 PM PDT 24
Peak memory 216104 kb
Host smart-34646ff4-d516-4941-b31f-463b0b097d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814976019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2814976019
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.4008159746
Short name T236
Test name
Test status
Simulation time 16510550693 ps
CPU time 32.33 seconds
Started Jul 12 04:35:28 PM PDT 24
Finished Jul 12 04:36:10 PM PDT 24
Peak memory 214512 kb
Host smart-a7d724c9-c7dc-45da-a284-a89e0509682d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008159746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.4008159746
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3219892636
Short name T194
Test name
Test status
Simulation time 688482544 ps
CPU time 8.49 seconds
Started Jul 12 04:35:17 PM PDT 24
Finished Jul 12 04:35:27 PM PDT 24
Peak memory 216948 kb
Host smart-f2c67ec4-9c4a-460c-a91c-61e3b3ba5496
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219892636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3219892636
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2765896308
Short name T299
Test name
Test status
Simulation time 182059179753 ps
CPU time 611.24 seconds
Started Jul 12 04:35:23 PM PDT 24
Finished Jul 12 04:45:37 PM PDT 24
Peak memory 236440 kb
Host smart-2f9a0f46-8408-4eef-971c-6dc923e34b67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765896308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2765896308
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2861946879
Short name T328
Test name
Test status
Simulation time 332326610 ps
CPU time 19.63 seconds
Started Jul 12 04:35:32 PM PDT 24
Finished Jul 12 04:36:03 PM PDT 24
Peak memory 219168 kb
Host smart-3d6a88e0-2498-435a-93c0-9be88b310fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861946879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2861946879
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.804637801
Short name T214
Test name
Test status
Simulation time 14254858005 ps
CPU time 30.83 seconds
Started Jul 12 04:35:21 PM PDT 24
Finished Jul 12 04:35:54 PM PDT 24
Peak memory 217852 kb
Host smart-f5cb2fd0-2693-4485-b01d-790ab5e05862
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=804637801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.804637801
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.243885458
Short name T244
Test name
Test status
Simulation time 14349001437 ps
CPU time 64.93 seconds
Started Jul 12 04:35:22 PM PDT 24
Finished Jul 12 04:36:29 PM PDT 24
Peak memory 216544 kb
Host smart-d7892a4d-317a-4f2a-87be-8ad6165a68a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243885458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.243885458
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2598220702
Short name T195
Test name
Test status
Simulation time 28175958211 ps
CPU time 67.98 seconds
Started Jul 12 04:35:25 PM PDT 24
Finished Jul 12 04:36:37 PM PDT 24
Peak memory 218892 kb
Host smart-8ecb6254-f3b1-458c-b4c8-2eb34e61fd7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598220702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2598220702
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2601090178
Short name T303
Test name
Test status
Simulation time 3457449078 ps
CPU time 29.23 seconds
Started Jul 12 04:35:27 PM PDT 24
Finished Jul 12 04:36:04 PM PDT 24
Peak memory 217080 kb
Host smart-eb1977f2-511b-448b-9e37-d367a8e5ac9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601090178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2601090178
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3668049809
Short name T248
Test name
Test status
Simulation time 11400021946 ps
CPU time 304.63 seconds
Started Jul 12 04:35:28 PM PDT 24
Finished Jul 12 04:40:40 PM PDT 24
Peak memory 234980 kb
Host smart-cc7b144f-6e69-40a3-9831-0febe3bc8eb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668049809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3668049809
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3189938135
Short name T153
Test name
Test status
Simulation time 18588076132 ps
CPU time 19.34 seconds
Started Jul 12 04:35:25 PM PDT 24
Finished Jul 12 04:35:48 PM PDT 24
Peak memory 211808 kb
Host smart-f73ad95e-e7fa-43d6-a142-2ec597358974
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3189938135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3189938135
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1010393185
Short name T357
Test name
Test status
Simulation time 29320737809 ps
CPU time 61.94 seconds
Started Jul 12 04:35:30 PM PDT 24
Finished Jul 12 04:36:42 PM PDT 24
Peak memory 216772 kb
Host smart-f105f3d1-af81-4da1-bd90-52d5859fa13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010393185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1010393185
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1369902272
Short name T224
Test name
Test status
Simulation time 4798204642 ps
CPU time 67.57 seconds
Started Jul 12 04:35:23 PM PDT 24
Finished Jul 12 04:36:32 PM PDT 24
Peak memory 220468 kb
Host smart-57ea0553-132e-4439-9130-0b2d8e9bcc98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369902272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1369902272
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1221190100
Short name T353
Test name
Test status
Simulation time 11254591542 ps
CPU time 18.19 seconds
Started Jul 12 04:35:27 PM PDT 24
Finished Jul 12 04:35:51 PM PDT 24
Peak memory 213240 kb
Host smart-cd314ed3-e260-4094-8286-66f72011b15b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221190100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1221190100
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1413304158
Short name T41
Test name
Test status
Simulation time 769726033444 ps
CPU time 804.63 seconds
Started Jul 12 04:35:29 PM PDT 24
Finished Jul 12 04:49:04 PM PDT 24
Peak memory 239568 kb
Host smart-601ea701-35f0-4f62-b917-95f6eabb8c7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413304158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1413304158
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2863920207
Short name T154
Test name
Test status
Simulation time 1148021597 ps
CPU time 26.97 seconds
Started Jul 12 04:35:29 PM PDT 24
Finished Jul 12 04:36:05 PM PDT 24
Peak memory 219168 kb
Host smart-87ba19b8-44c5-46f4-b2fc-3f77ea74a13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863920207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2863920207
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1873377442
Short name T105
Test name
Test status
Simulation time 9916926027 ps
CPU time 24.53 seconds
Started Jul 12 04:35:23 PM PDT 24
Finished Jul 12 04:35:49 PM PDT 24
Peak memory 211964 kb
Host smart-ab15a49b-71aa-49ce-94ac-b5d41657a4cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1873377442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1873377442
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2334522772
Short name T3
Test name
Test status
Simulation time 8907809179 ps
CPU time 44.77 seconds
Started Jul 12 04:35:27 PM PDT 24
Finished Jul 12 04:36:18 PM PDT 24
Peak memory 216500 kb
Host smart-ed67485b-bafc-4c36-aa2f-ade83609536e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334522772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2334522772
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3387492607
Short name T319
Test name
Test status
Simulation time 62033355174 ps
CPU time 137.91 seconds
Started Jul 12 04:35:27 PM PDT 24
Finished Jul 12 04:37:51 PM PDT 24
Peak memory 219912 kb
Host smart-4d2d5aa7-14b7-4328-9f40-60fcbaab5686
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387492607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3387492607
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3190283297
Short name T207
Test name
Test status
Simulation time 3752819364 ps
CPU time 29.47 seconds
Started Jul 12 04:35:25 PM PDT 24
Finished Jul 12 04:35:58 PM PDT 24
Peak memory 217080 kb
Host smart-8ab374d1-5048-4e43-9b56-f0fb1f0e6758
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190283297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3190283297
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2536274258
Short name T43
Test name
Test status
Simulation time 18822580968 ps
CPU time 134.72 seconds
Started Jul 12 04:35:33 PM PDT 24
Finished Jul 12 04:38:01 PM PDT 24
Peak memory 218252 kb
Host smart-4ff2ed2c-9da5-4c66-b303-9af37ff5cb3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536274258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2536274258
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2107969202
Short name T239
Test name
Test status
Simulation time 16466093660 ps
CPU time 26.52 seconds
Started Jul 12 04:35:30 PM PDT 24
Finished Jul 12 04:36:07 PM PDT 24
Peak memory 219240 kb
Host smart-32e8f167-9290-4c39-af5d-e9682840daca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107969202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2107969202
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1414051074
Short name T173
Test name
Test status
Simulation time 2491027854 ps
CPU time 13.27 seconds
Started Jul 12 04:35:33 PM PDT 24
Finished Jul 12 04:35:58 PM PDT 24
Peak memory 211028 kb
Host smart-fab6087a-6471-4c8b-98e1-8d682c3111db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1414051074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1414051074
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.485534218
Short name T293
Test name
Test status
Simulation time 3613918412 ps
CPU time 27.78 seconds
Started Jul 12 04:35:29 PM PDT 24
Finished Jul 12 04:36:05 PM PDT 24
Peak memory 215888 kb
Host smart-f8428c27-64cb-406a-979b-da0708d465bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485534218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.485534218
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.4229445005
Short name T234
Test name
Test status
Simulation time 17207507867 ps
CPU time 87.44 seconds
Started Jul 12 04:35:30 PM PDT 24
Finished Jul 12 04:37:08 PM PDT 24
Peak memory 219276 kb
Host smart-968ac913-bbf8-4759-9abc-707b79661efb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229445005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.4229445005
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1032508539
Short name T201
Test name
Test status
Simulation time 5104934041 ps
CPU time 16.39 seconds
Started Jul 12 04:35:24 PM PDT 24
Finished Jul 12 04:35:43 PM PDT 24
Peak memory 213240 kb
Host smart-c47d3ac8-dea9-454c-b67d-b5f72aa73da2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032508539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1032508539
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.159444447
Short name T355
Test name
Test status
Simulation time 20098284937 ps
CPU time 343.82 seconds
Started Jul 12 04:35:29 PM PDT 24
Finished Jul 12 04:41:21 PM PDT 24
Peak memory 234728 kb
Host smart-440d7712-e78d-443f-9c24-68b34e39c6bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159444447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.159444447
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2529167169
Short name T205
Test name
Test status
Simulation time 347342983 ps
CPU time 18.95 seconds
Started Jul 12 04:35:29 PM PDT 24
Finished Jul 12 04:35:56 PM PDT 24
Peak memory 219168 kb
Host smart-fb5b4af9-7873-4ae4-8d23-ac127b6bc4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529167169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2529167169
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2782501999
Short name T125
Test name
Test status
Simulation time 366755101 ps
CPU time 10.51 seconds
Started Jul 12 04:35:29 PM PDT 24
Finished Jul 12 04:35:48 PM PDT 24
Peak memory 219164 kb
Host smart-f8fbb38d-ffe4-40ca-b15b-bf3b7fe81710
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2782501999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2782501999
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.1458288091
Short name T257
Test name
Test status
Simulation time 5742706279 ps
CPU time 35.96 seconds
Started Jul 12 04:35:23 PM PDT 24
Finished Jul 12 04:36:01 PM PDT 24
Peak memory 216768 kb
Host smart-6ddd5f8d-c0c6-4eeb-9ef1-f154b25da97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458288091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1458288091
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3144359200
Short name T331
Test name
Test status
Simulation time 526992101 ps
CPU time 32.41 seconds
Started Jul 12 04:35:29 PM PDT 24
Finished Jul 12 04:36:12 PM PDT 24
Peak memory 219208 kb
Host smart-021e77f2-bcd6-4364-8bcc-a3c804760ea1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144359200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3144359200
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3134506059
Short name T206
Test name
Test status
Simulation time 20773903754 ps
CPU time 23.65 seconds
Started Jul 12 04:35:27 PM PDT 24
Finished Jul 12 04:35:57 PM PDT 24
Peak memory 217548 kb
Host smart-80811725-8fe8-4782-9677-411a6b7332d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134506059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3134506059
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.203182589
Short name T313
Test name
Test status
Simulation time 321741036690 ps
CPU time 659.12 seconds
Started Jul 12 04:35:27 PM PDT 24
Finished Jul 12 04:46:32 PM PDT 24
Peak memory 225728 kb
Host smart-ea9c1a99-7e6f-47af-9506-0c6ba8a5cb30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203182589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.203182589
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1299271459
Short name T340
Test name
Test status
Simulation time 4115590933 ps
CPU time 26.54 seconds
Started Jul 12 04:35:25 PM PDT 24
Finished Jul 12 04:35:54 PM PDT 24
Peak memory 219204 kb
Host smart-a8436b49-522d-473b-a7d8-b1a3b9de5498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299271459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1299271459
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.785565080
Short name T124
Test name
Test status
Simulation time 7326677624 ps
CPU time 17.99 seconds
Started Jul 12 04:35:19 PM PDT 24
Finished Jul 12 04:35:39 PM PDT 24
Peak memory 218984 kb
Host smart-1e2e07c0-c78b-4007-8fff-fb60da4ea972
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=785565080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.785565080
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.776696502
Short name T144
Test name
Test status
Simulation time 8246549034 ps
CPU time 42.5 seconds
Started Jul 12 04:35:28 PM PDT 24
Finished Jul 12 04:36:18 PM PDT 24
Peak memory 217060 kb
Host smart-453a3a26-489b-457c-87d3-8aa753ba37eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776696502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.776696502
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1825648887
Short name T215
Test name
Test status
Simulation time 6718459940 ps
CPU time 70.46 seconds
Started Jul 12 04:35:26 PM PDT 24
Finished Jul 12 04:36:41 PM PDT 24
Peak memory 216716 kb
Host smart-914f6b05-acb6-42dc-b695-35adcfe6dc21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825648887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1825648887
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1611440852
Short name T174
Test name
Test status
Simulation time 5705813977 ps
CPU time 17.83 seconds
Started Jul 12 04:34:47 PM PDT 24
Finished Jul 12 04:35:08 PM PDT 24
Peak memory 217472 kb
Host smart-9acfec1c-3d9a-42a7-be12-394c5e93d7f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611440852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1611440852
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2442971501
Short name T261
Test name
Test status
Simulation time 91854256839 ps
CPU time 594.77 seconds
Started Jul 12 04:34:46 PM PDT 24
Finished Jul 12 04:44:44 PM PDT 24
Peak memory 233704 kb
Host smart-7cba4f4b-8802-4b86-b26f-33e408aae672
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442971501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2442971501
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.123981631
Short name T22
Test name
Test status
Simulation time 335654067 ps
CPU time 19.11 seconds
Started Jul 12 04:34:59 PM PDT 24
Finished Jul 12 04:35:20 PM PDT 24
Peak memory 219152 kb
Host smart-10824edc-b082-4946-85f2-1c27f221fc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123981631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.123981631
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3689415005
Short name T223
Test name
Test status
Simulation time 12898647097 ps
CPU time 28.03 seconds
Started Jul 12 04:34:46 PM PDT 24
Finished Jul 12 04:35:18 PM PDT 24
Peak memory 217656 kb
Host smart-6725c5f5-a9b6-419b-8ae4-550045106947
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3689415005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3689415005
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2566342836
Short name T160
Test name
Test status
Simulation time 20014730935 ps
CPU time 43.05 seconds
Started Jul 12 04:34:45 PM PDT 24
Finished Jul 12 04:35:32 PM PDT 24
Peak memory 216340 kb
Host smart-2503ac67-8786-4bf2-b124-1d1de6820912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566342836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2566342836
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2742922661
Short name T84
Test name
Test status
Simulation time 1709580277 ps
CPU time 31.21 seconds
Started Jul 12 04:34:44 PM PDT 24
Finished Jul 12 04:35:20 PM PDT 24
Peak memory 219208 kb
Host smart-7e8691bf-3912-4578-968e-3405d6b85bb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742922661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2742922661
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1684842426
Short name T294
Test name
Test status
Simulation time 21128348197 ps
CPU time 30.46 seconds
Started Jul 12 04:35:26 PM PDT 24
Finished Jul 12 04:36:00 PM PDT 24
Peak memory 217252 kb
Host smart-61dbcea1-045b-422a-8cc2-05c39419e885
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684842426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1684842426
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3979055305
Short name T36
Test name
Test status
Simulation time 82986756366 ps
CPU time 792.32 seconds
Started Jul 12 04:35:20 PM PDT 24
Finished Jul 12 04:48:34 PM PDT 24
Peak memory 233920 kb
Host smart-2ee883a9-d23f-49a6-a889-dfc55b6ba35b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979055305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3979055305
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3706856025
Short name T318
Test name
Test status
Simulation time 2907344369 ps
CPU time 26.49 seconds
Started Jul 12 04:35:30 PM PDT 24
Finished Jul 12 04:36:07 PM PDT 24
Peak memory 219232 kb
Host smart-db4644cd-822b-465e-bb58-e34940db8492
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3706856025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3706856025
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1698137373
Short name T225
Test name
Test status
Simulation time 6798614951 ps
CPU time 57.85 seconds
Started Jul 12 04:35:30 PM PDT 24
Finished Jul 12 04:36:38 PM PDT 24
Peak memory 217076 kb
Host smart-c7e7583e-299d-4635-bd30-f49a2795fa97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698137373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1698137373
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3869120937
Short name T268
Test name
Test status
Simulation time 7153790450 ps
CPU time 74.72 seconds
Started Jul 12 04:35:26 PM PDT 24
Finished Jul 12 04:36:45 PM PDT 24
Peak memory 219140 kb
Host smart-bb32179e-1f2e-4ab2-a780-afe64330a3d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869120937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3869120937
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3127196841
Short name T322
Test name
Test status
Simulation time 5376442701 ps
CPU time 23.74 seconds
Started Jul 12 04:35:18 PM PDT 24
Finished Jul 12 04:35:44 PM PDT 24
Peak memory 213432 kb
Host smart-8431901a-10f4-479f-8aed-3fa59a9bf18b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127196841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3127196841
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2925840218
Short name T40
Test name
Test status
Simulation time 66952901557 ps
CPU time 617.54 seconds
Started Jul 12 04:35:36 PM PDT 24
Finished Jul 12 04:46:08 PM PDT 24
Peak memory 219452 kb
Host smart-95a91626-86cc-40f7-a132-d1f50d6fa407
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925840218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2925840218
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1391982271
Short name T150
Test name
Test status
Simulation time 5420494046 ps
CPU time 48.3 seconds
Started Jul 12 04:35:18 PM PDT 24
Finished Jul 12 04:36:08 PM PDT 24
Peak memory 219200 kb
Host smart-abb0b16a-0e6d-4f27-88be-30be188323ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391982271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1391982271
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.435129553
Short name T264
Test name
Test status
Simulation time 10538078929 ps
CPU time 26.22 seconds
Started Jul 12 04:35:26 PM PDT 24
Finished Jul 12 04:35:56 PM PDT 24
Peak memory 211920 kb
Host smart-93088159-1a66-4049-9c94-bbda78f62eaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=435129553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.435129553
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1535493792
Short name T297
Test name
Test status
Simulation time 18316218256 ps
CPU time 47.2 seconds
Started Jul 12 04:35:28 PM PDT 24
Finished Jul 12 04:36:23 PM PDT 24
Peak memory 216000 kb
Host smart-ea9431f0-ff95-48d5-ae74-9cb22b3a1b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535493792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1535493792
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.675214239
Short name T283
Test name
Test status
Simulation time 26331401699 ps
CPU time 69.1 seconds
Started Jul 12 04:35:30 PM PDT 24
Finished Jul 12 04:36:50 PM PDT 24
Peak memory 219252 kb
Host smart-2b4fbac3-47ef-4eb5-ad0b-6f42ceae135f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675214239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.675214239
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2516643548
Short name T62
Test name
Test status
Simulation time 2118645397 ps
CPU time 20.78 seconds
Started Jul 12 04:35:19 PM PDT 24
Finished Jul 12 04:35:41 PM PDT 24
Peak memory 217064 kb
Host smart-c5befb1c-4a39-4b45-85b4-12ba41d52ed7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516643548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2516643548
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2394590289
Short name T218
Test name
Test status
Simulation time 2173023382 ps
CPU time 162.81 seconds
Started Jul 12 04:35:23 PM PDT 24
Finished Jul 12 04:38:07 PM PDT 24
Peak memory 239104 kb
Host smart-c022a5e4-ba90-4dfe-aca2-96712d01901c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394590289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2394590289
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1544283904
Short name T134
Test name
Test status
Simulation time 19936094890 ps
CPU time 46.45 seconds
Started Jul 12 04:35:23 PM PDT 24
Finished Jul 12 04:36:12 PM PDT 24
Peak memory 219248 kb
Host smart-c2c4c2a0-21b5-459b-813a-20f1555b290a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544283904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1544283904
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2545728796
Short name T155
Test name
Test status
Simulation time 358593263 ps
CPU time 10.62 seconds
Started Jul 12 04:35:29 PM PDT 24
Finished Jul 12 04:35:48 PM PDT 24
Peak memory 219168 kb
Host smart-aefdf0e8-75b9-42ab-b36f-2edd4cbac68a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2545728796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2545728796
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1303832636
Short name T298
Test name
Test status
Simulation time 6099304053 ps
CPU time 56.02 seconds
Started Jul 12 04:35:25 PM PDT 24
Finished Jul 12 04:36:25 PM PDT 24
Peak memory 215968 kb
Host smart-a1b66ff0-9acd-43cd-b576-ab99d3b763e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303832636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1303832636
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1406810865
Short name T82
Test name
Test status
Simulation time 581180501 ps
CPU time 43.23 seconds
Started Jul 12 04:35:29 PM PDT 24
Finished Jul 12 04:36:23 PM PDT 24
Peak memory 219176 kb
Host smart-bd856551-847a-46a3-bcd9-2d1f486cf0bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406810865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1406810865
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2545993267
Short name T66
Test name
Test status
Simulation time 6328728497 ps
CPU time 25.94 seconds
Started Jul 12 04:35:26 PM PDT 24
Finished Jul 12 04:35:57 PM PDT 24
Peak memory 217208 kb
Host smart-94f1c0a1-3029-41a9-a36b-c263e7d18286
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545993267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2545993267
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3525367615
Short name T237
Test name
Test status
Simulation time 22384880465 ps
CPU time 236.15 seconds
Started Jul 12 04:35:27 PM PDT 24
Finished Jul 12 04:39:29 PM PDT 24
Peak memory 237912 kb
Host smart-25f7969f-01c4-42a4-a9fa-6ed33ad0a22d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525367615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3525367615
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2218378760
Short name T139
Test name
Test status
Simulation time 5227024064 ps
CPU time 35.01 seconds
Started Jul 12 04:35:28 PM PDT 24
Finished Jul 12 04:36:10 PM PDT 24
Peak memory 219284 kb
Host smart-7f3b0ce0-2419-454b-9b04-ff2b0af11ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218378760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2218378760
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.533876858
Short name T31
Test name
Test status
Simulation time 8168866362 ps
CPU time 29.31 seconds
Started Jul 12 04:35:23 PM PDT 24
Finished Jul 12 04:35:54 PM PDT 24
Peak memory 211504 kb
Host smart-e06264bb-6824-4c81-b979-6b5d05c2908c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=533876858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.533876858
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.662917076
Short name T198
Test name
Test status
Simulation time 3796935598 ps
CPU time 41.85 seconds
Started Jul 12 04:35:28 PM PDT 24
Finished Jul 12 04:36:19 PM PDT 24
Peak memory 216288 kb
Host smart-cc16fb1f-5e3e-4338-a37a-b60961901f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662917076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.662917076
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3472760937
Short name T275
Test name
Test status
Simulation time 13063426785 ps
CPU time 58.05 seconds
Started Jul 12 04:35:26 PM PDT 24
Finished Jul 12 04:36:30 PM PDT 24
Peak memory 217552 kb
Host smart-bc8ad7c2-c102-45ee-b246-c31d0fb66130
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472760937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3472760937
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2472786990
Short name T4
Test name
Test status
Simulation time 12384296330 ps
CPU time 26.25 seconds
Started Jul 12 04:35:30 PM PDT 24
Finished Jul 12 04:36:07 PM PDT 24
Peak memory 217536 kb
Host smart-c529b760-a943-432e-a84b-93e416ec05d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472786990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2472786990
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1670205535
Short name T37
Test name
Test status
Simulation time 30631895486 ps
CPU time 387.61 seconds
Started Jul 12 04:35:29 PM PDT 24
Finished Jul 12 04:42:07 PM PDT 24
Peak memory 219432 kb
Host smart-8c6795c2-bd0d-44c6-82cb-cacd3dae7ffd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670205535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1670205535
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3712444010
Short name T202
Test name
Test status
Simulation time 9818000627 ps
CPU time 49.94 seconds
Started Jul 12 04:35:26 PM PDT 24
Finished Jul 12 04:36:22 PM PDT 24
Peak memory 219240 kb
Host smart-022bc83e-e96a-4b3d-ac4c-4b8453fba6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712444010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3712444010
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2636216682
Short name T311
Test name
Test status
Simulation time 4867598110 ps
CPU time 16.92 seconds
Started Jul 12 04:35:20 PM PDT 24
Finished Jul 12 04:35:39 PM PDT 24
Peak memory 219252 kb
Host smart-fc818008-e511-4598-a819-ae1ab1b2f45c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2636216682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2636216682
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2066443857
Short name T166
Test name
Test status
Simulation time 8559198518 ps
CPU time 33.61 seconds
Started Jul 12 04:35:24 PM PDT 24
Finished Jul 12 04:36:01 PM PDT 24
Peak memory 217540 kb
Host smart-3b9d03f4-3d33-4b00-bfa9-205e80b5acba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066443857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2066443857
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.703765641
Short name T306
Test name
Test status
Simulation time 38980653923 ps
CPU time 92.83 seconds
Started Jul 12 04:35:25 PM PDT 24
Finished Jul 12 04:37:03 PM PDT 24
Peak memory 219232 kb
Host smart-3733f4b7-7288-46a8-9162-e8b67dd3166a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703765641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.703765641
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.1623826429
Short name T53
Test name
Test status
Simulation time 110417194762 ps
CPU time 2314.56 seconds
Started Jul 12 04:35:29 PM PDT 24
Finished Jul 12 05:14:12 PM PDT 24
Peak memory 246688 kb
Host smart-2f11cd15-5207-46ae-aa79-ecc5cf81bd41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623826429 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.1623826429
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2856430412
Short name T179
Test name
Test status
Simulation time 32821507489 ps
CPU time 18.64 seconds
Started Jul 12 04:35:30 PM PDT 24
Finished Jul 12 04:35:59 PM PDT 24
Peak memory 217348 kb
Host smart-63bc0d2f-249f-412d-a3ce-2e93382016ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856430412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2856430412
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.692129234
Short name T16
Test name
Test status
Simulation time 185222760051 ps
CPU time 445.5 seconds
Started Jul 12 04:35:33 PM PDT 24
Finished Jul 12 04:43:11 PM PDT 24
Peak memory 216752 kb
Host smart-6910d124-4ed7-453b-8884-537a926aeb65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692129234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.692129234
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2941088014
Short name T133
Test name
Test status
Simulation time 4875479590 ps
CPU time 45 seconds
Started Jul 12 04:35:34 PM PDT 24
Finished Jul 12 04:36:33 PM PDT 24
Peak memory 219332 kb
Host smart-8c5c53ec-a8da-4b7d-ac24-4d414ac6cc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941088014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2941088014
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.56044448
Short name T123
Test name
Test status
Simulation time 361839323 ps
CPU time 9.92 seconds
Started Jul 12 04:35:32 PM PDT 24
Finished Jul 12 04:35:54 PM PDT 24
Peak memory 219204 kb
Host smart-ed94d833-4f1f-4d94-a0f9-8f6032a376b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=56044448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.56044448
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1755625105
Short name T350
Test name
Test status
Simulation time 7221089094 ps
CPU time 62.64 seconds
Started Jul 12 04:35:31 PM PDT 24
Finished Jul 12 04:36:46 PM PDT 24
Peak memory 216988 kb
Host smart-fd1ea619-c19c-416d-be3f-ab9c2a9abd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755625105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1755625105
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2930811153
Short name T26
Test name
Test status
Simulation time 94109343571 ps
CPU time 186.84 seconds
Started Jul 12 04:35:31 PM PDT 24
Finished Jul 12 04:38:51 PM PDT 24
Peak memory 227492 kb
Host smart-ba92db52-6d38-408c-9613-648167171f5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930811153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2930811153
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2110904587
Short name T12
Test name
Test status
Simulation time 73639403948 ps
CPU time 4597.24 seconds
Started Jul 12 04:35:36 PM PDT 24
Finished Jul 12 05:52:28 PM PDT 24
Peak memory 235712 kb
Host smart-180505b4-2456-4270-8d46-db316bbb9871
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110904587 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.2110904587
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2361381843
Short name T64
Test name
Test status
Simulation time 20316142747 ps
CPU time 33.6 seconds
Started Jul 12 04:35:27 PM PDT 24
Finished Jul 12 04:36:06 PM PDT 24
Peak memory 217472 kb
Host smart-9493273c-7f43-48f6-866e-2044c6fc895b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361381843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2361381843
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3646225197
Short name T300
Test name
Test status
Simulation time 62755938415 ps
CPU time 278.09 seconds
Started Jul 12 04:35:38 PM PDT 24
Finished Jul 12 04:40:32 PM PDT 24
Peak memory 237840 kb
Host smart-9ea46de7-fed3-44bc-ae9e-135fe213378f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646225197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3646225197
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.4268103663
Short name T310
Test name
Test status
Simulation time 1481274552 ps
CPU time 28.86 seconds
Started Jul 12 04:35:30 PM PDT 24
Finished Jul 12 04:36:09 PM PDT 24
Peak memory 218900 kb
Host smart-2bb9a190-82ae-4366-bcc3-4854e57cf39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268103663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.4268103663
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3693651844
Short name T282
Test name
Test status
Simulation time 4950454933 ps
CPU time 24.89 seconds
Started Jul 12 04:35:33 PM PDT 24
Finished Jul 12 04:36:11 PM PDT 24
Peak memory 217812 kb
Host smart-b8d068ae-41fe-48aa-82e0-8b90d4b95dce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3693651844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3693651844
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1796990149
Short name T278
Test name
Test status
Simulation time 13096871276 ps
CPU time 80.58 seconds
Started Jul 12 04:35:46 PM PDT 24
Finished Jul 12 04:37:23 PM PDT 24
Peak memory 218824 kb
Host smart-eb4b1cd7-88a4-4a46-8367-f664d4b1dbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796990149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1796990149
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1541941346
Short name T245
Test name
Test status
Simulation time 4224077980 ps
CPU time 42.23 seconds
Started Jul 12 04:35:35 PM PDT 24
Finished Jul 12 04:36:32 PM PDT 24
Peak memory 219280 kb
Host smart-0976d6f5-a19b-46a4-8b12-30eba5ee03f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541941346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1541941346
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1330980846
Short name T54
Test name
Test status
Simulation time 254774281053 ps
CPU time 1976.09 seconds
Started Jul 12 04:35:30 PM PDT 24
Finished Jul 12 05:08:37 PM PDT 24
Peak memory 243944 kb
Host smart-d2719363-d860-4b57-91e1-e169fd48117e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330980846 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.1330980846
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2108967853
Short name T27
Test name
Test status
Simulation time 916201737 ps
CPU time 8.53 seconds
Started Jul 12 04:35:28 PM PDT 24
Finished Jul 12 04:35:46 PM PDT 24
Peak memory 217084 kb
Host smart-4273d10a-8c54-41ce-8a60-10ced83c131e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108967853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2108967853
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3626653732
Short name T189
Test name
Test status
Simulation time 2681318036 ps
CPU time 191.05 seconds
Started Jul 12 04:35:33 PM PDT 24
Finished Jul 12 04:38:57 PM PDT 24
Peak memory 237840 kb
Host smart-f591d9a1-da09-42a9-a43c-e74e81cd01f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626653732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3626653732
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1563139221
Short name T128
Test name
Test status
Simulation time 29246995498 ps
CPU time 59.36 seconds
Started Jul 12 04:35:30 PM PDT 24
Finished Jul 12 04:36:40 PM PDT 24
Peak memory 219252 kb
Host smart-8ca9d44e-b7ad-4385-9a57-b5b0a169b068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563139221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1563139221
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1987241924
Short name T165
Test name
Test status
Simulation time 8589363861 ps
CPU time 34.11 seconds
Started Jul 12 04:35:30 PM PDT 24
Finished Jul 12 04:36:14 PM PDT 24
Peak memory 219244 kb
Host smart-a0d15d4c-9649-446c-9205-a3b9ad7f3924
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1987241924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1987241924
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3314834913
Short name T147
Test name
Test status
Simulation time 6351149303 ps
CPU time 38.69 seconds
Started Jul 12 04:35:35 PM PDT 24
Finished Jul 12 04:36:28 PM PDT 24
Peak memory 216864 kb
Host smart-76634cda-80ce-4a9d-857b-52248d0cddf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314834913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3314834913
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.279470478
Short name T192
Test name
Test status
Simulation time 3291090366 ps
CPU time 57.62 seconds
Started Jul 12 04:35:33 PM PDT 24
Finished Jul 12 04:36:42 PM PDT 24
Peak memory 219288 kb
Host smart-d4bd9121-4552-40a1-bdd7-38559eba4e38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279470478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.279470478
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3032849031
Short name T325
Test name
Test status
Simulation time 331399444 ps
CPU time 10.78 seconds
Started Jul 12 04:35:36 PM PDT 24
Finished Jul 12 04:36:02 PM PDT 24
Peak memory 217128 kb
Host smart-cac15137-eeb6-438c-af16-5846b9f7e8b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032849031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3032849031
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1577302442
Short name T242
Test name
Test status
Simulation time 3428863352 ps
CPU time 260.95 seconds
Started Jul 12 04:35:33 PM PDT 24
Finished Jul 12 04:40:05 PM PDT 24
Peak memory 226068 kb
Host smart-b941b8b7-bcca-4538-afb1-40cc8af0ff76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577302442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1577302442
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2336774678
Short name T352
Test name
Test status
Simulation time 661338824 ps
CPU time 18.72 seconds
Started Jul 12 04:35:31 PM PDT 24
Finished Jul 12 04:36:00 PM PDT 24
Peak memory 219168 kb
Host smart-b29dcfbf-f044-49fd-b135-9ce5090dc9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336774678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2336774678
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1857475355
Short name T182
Test name
Test status
Simulation time 193853654 ps
CPU time 10.38 seconds
Started Jul 12 04:35:30 PM PDT 24
Finished Jul 12 04:35:50 PM PDT 24
Peak memory 219240 kb
Host smart-da6c45f6-a3dd-4489-a53d-d3c3625ebaaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1857475355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1857475355
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3785953932
Short name T69
Test name
Test status
Simulation time 8867096382 ps
CPU time 68.39 seconds
Started Jul 12 04:35:31 PM PDT 24
Finished Jul 12 04:36:50 PM PDT 24
Peak memory 216776 kb
Host smart-affad0ff-af6c-4b36-a704-a1d955a91ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785953932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3785953932
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1396494673
Short name T157
Test name
Test status
Simulation time 65717573204 ps
CPU time 242.57 seconds
Started Jul 12 04:35:33 PM PDT 24
Finished Jul 12 04:39:48 PM PDT 24
Peak memory 222304 kb
Host smart-7bc3cdd3-07c6-4eb9-a327-b2331766589f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396494673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1396494673
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1677093933
Short name T292
Test name
Test status
Simulation time 5267640418 ps
CPU time 25.27 seconds
Started Jul 12 04:35:32 PM PDT 24
Finished Jul 12 04:36:09 PM PDT 24
Peak memory 217468 kb
Host smart-94805c5e-bad7-44fd-8fe1-9201eba7a0c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677093933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1677093933
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.108416500
Short name T279
Test name
Test status
Simulation time 116915194850 ps
CPU time 523.86 seconds
Started Jul 12 04:35:39 PM PDT 24
Finished Jul 12 04:44:39 PM PDT 24
Peak memory 237760 kb
Host smart-1facf499-661c-4cec-adff-22a8283e36c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108416500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.108416500
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.42897916
Short name T142
Test name
Test status
Simulation time 12365683877 ps
CPU time 37.38 seconds
Started Jul 12 04:35:33 PM PDT 24
Finished Jul 12 04:36:23 PM PDT 24
Peak memory 219260 kb
Host smart-fe8659af-aaa4-489c-ab91-25ee3e1613f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42897916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.42897916
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2688608014
Short name T341
Test name
Test status
Simulation time 3928781711 ps
CPU time 22.38 seconds
Started Jul 12 04:35:39 PM PDT 24
Finished Jul 12 04:36:17 PM PDT 24
Peak memory 219268 kb
Host smart-952e319c-09f7-47e1-bb63-67c76c77b1d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2688608014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2688608014
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2257092563
Short name T246
Test name
Test status
Simulation time 1391721157 ps
CPU time 20.07 seconds
Started Jul 12 04:35:33 PM PDT 24
Finished Jul 12 04:36:06 PM PDT 24
Peak memory 216788 kb
Host smart-74570125-8de0-403a-8e63-32ab37361505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257092563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2257092563
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.715911935
Short name T343
Test name
Test status
Simulation time 5633745344 ps
CPU time 49.48 seconds
Started Jul 12 04:35:38 PM PDT 24
Finished Jul 12 04:36:43 PM PDT 24
Peak memory 220496 kb
Host smart-cff99e7f-c672-4e65-8279-70c2a0a085ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715911935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.715911935
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.240302587
Short name T152
Test name
Test status
Simulation time 2797477111 ps
CPU time 24.95 seconds
Started Jul 12 04:35:00 PM PDT 24
Finished Jul 12 04:35:27 PM PDT 24
Peak memory 217088 kb
Host smart-f4c1e4fa-eb16-483b-8bcf-428683b396f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240302587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.240302587
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.907717415
Short name T38
Test name
Test status
Simulation time 161981336460 ps
CPU time 766.35 seconds
Started Jul 12 04:34:44 PM PDT 24
Finished Jul 12 04:47:35 PM PDT 24
Peak memory 234724 kb
Host smart-6baa8390-3ad3-4bc3-991a-4acc60b71e15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907717415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.907717415
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2065112056
Short name T308
Test name
Test status
Simulation time 16450956318 ps
CPU time 36.68 seconds
Started Jul 12 04:34:45 PM PDT 24
Finished Jul 12 04:35:26 PM PDT 24
Peak memory 219248 kb
Host smart-34c3e8bc-023e-4d54-8f2d-da35406e17dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065112056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2065112056
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.833208568
Short name T349
Test name
Test status
Simulation time 2911718209 ps
CPU time 26.26 seconds
Started Jul 12 04:34:59 PM PDT 24
Finished Jul 12 04:35:28 PM PDT 24
Peak memory 219200 kb
Host smart-5d40fe3b-e632-40f7-a7f9-97fa9b6daf5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=833208568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.833208568
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1526650723
Short name T338
Test name
Test status
Simulation time 11212351298 ps
CPU time 49.14 seconds
Started Jul 12 04:34:47 PM PDT 24
Finished Jul 12 04:35:40 PM PDT 24
Peak memory 217104 kb
Host smart-a179d942-0b8e-43db-9354-b912611512f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526650723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1526650723
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.4278181006
Short name T249
Test name
Test status
Simulation time 2852652869 ps
CPU time 44.14 seconds
Started Jul 12 04:34:47 PM PDT 24
Finished Jul 12 04:35:34 PM PDT 24
Peak memory 219268 kb
Host smart-0630a49f-84e8-4327-b137-6e97ae9cbfad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278181006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.4278181006
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1729069290
Short name T162
Test name
Test status
Simulation time 3643000977 ps
CPU time 30.07 seconds
Started Jul 12 04:34:45 PM PDT 24
Finished Jul 12 04:35:19 PM PDT 24
Peak memory 217228 kb
Host smart-6318e2bb-26d4-4673-aa4a-6363bccc7282
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729069290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1729069290
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2051957192
Short name T140
Test name
Test status
Simulation time 9198358522 ps
CPU time 54.07 seconds
Started Jul 12 04:34:44 PM PDT 24
Finished Jul 12 04:35:43 PM PDT 24
Peak memory 219228 kb
Host smart-d448d725-5d50-4ae6-9e37-c761ab6c42f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051957192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2051957192
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.432444573
Short name T107
Test name
Test status
Simulation time 3857839043 ps
CPU time 31.01 seconds
Started Jul 12 04:34:46 PM PDT 24
Finished Jul 12 04:35:20 PM PDT 24
Peak memory 219264 kb
Host smart-e47b0467-95e5-40fa-9351-193969bc108c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=432444573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.432444573
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2563621150
Short name T296
Test name
Test status
Simulation time 17093406596 ps
CPU time 65.41 seconds
Started Jul 12 04:34:59 PM PDT 24
Finished Jul 12 04:36:07 PM PDT 24
Peak memory 216256 kb
Host smart-5b741b6a-ddae-43b1-a18c-662d22b9989e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563621150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2563621150
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.762039572
Short name T254
Test name
Test status
Simulation time 4674965870 ps
CPU time 47.33 seconds
Started Jul 12 04:34:44 PM PDT 24
Finished Jul 12 04:35:36 PM PDT 24
Peak memory 217460 kb
Host smart-f4ccd773-8f01-420e-8e4e-b2eeba447916
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762039572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.762039572
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3587832537
Short name T159
Test name
Test status
Simulation time 11973950413 ps
CPU time 28.15 seconds
Started Jul 12 04:34:56 PM PDT 24
Finished Jul 12 04:35:31 PM PDT 24
Peak memory 217328 kb
Host smart-f17c3d54-0cbc-43a6-94e1-e311dbbf96de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587832537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3587832537
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2369427580
Short name T32
Test name
Test status
Simulation time 7921923423 ps
CPU time 148.29 seconds
Started Jul 12 04:34:52 PM PDT 24
Finished Jul 12 04:37:21 PM PDT 24
Peak memory 237772 kb
Host smart-ec75c70f-c607-4c77-8a9b-1892848a4d2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369427580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2369427580
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3405071741
Short name T219
Test name
Test status
Simulation time 9720426954 ps
CPU time 49.37 seconds
Started Jul 12 04:34:41 PM PDT 24
Finished Jul 12 04:35:35 PM PDT 24
Peak memory 219292 kb
Host smart-0f076a4d-f05e-42bd-a915-b512cb7d5726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405071741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3405071741
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2010581812
Short name T122
Test name
Test status
Simulation time 9318965144 ps
CPU time 24.89 seconds
Started Jul 12 04:34:46 PM PDT 24
Finished Jul 12 04:35:14 PM PDT 24
Peak memory 219224 kb
Host smart-899ec57c-b2a2-4388-ab6e-c50ad2b41897
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2010581812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2010581812
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1873467131
Short name T81
Test name
Test status
Simulation time 707438219 ps
CPU time 20.49 seconds
Started Jul 12 04:34:52 PM PDT 24
Finished Jul 12 04:35:13 PM PDT 24
Peak memory 215916 kb
Host smart-2d55e6fb-f265-4ca9-8938-e01731d3655c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873467131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1873467131
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2050463702
Short name T186
Test name
Test status
Simulation time 1710589731 ps
CPU time 57.47 seconds
Started Jul 12 04:34:43 PM PDT 24
Finished Jul 12 04:35:45 PM PDT 24
Peak memory 221200 kb
Host smart-1c41e408-2c0d-4ef5-8bdc-27f13d4afb67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050463702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2050463702
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2861867054
Short name T276
Test name
Test status
Simulation time 172582210 ps
CPU time 8.92 seconds
Started Jul 12 04:34:56 PM PDT 24
Finished Jul 12 04:35:07 PM PDT 24
Peak memory 213132 kb
Host smart-561ed3e7-8b45-4bd5-a392-d2a86195f868
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861867054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2861867054
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.959443074
Short name T141
Test name
Test status
Simulation time 70288251012 ps
CPU time 369.49 seconds
Started Jul 12 04:35:02 PM PDT 24
Finished Jul 12 04:41:14 PM PDT 24
Peak memory 225952 kb
Host smart-51d40bf8-644b-4e0b-b55e-2b817349ea59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959443074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.959443074
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.217565349
Short name T256
Test name
Test status
Simulation time 3782466076 ps
CPU time 42.93 seconds
Started Jul 12 04:35:11 PM PDT 24
Finished Jul 12 04:35:55 PM PDT 24
Peak memory 219316 kb
Host smart-94408a35-00ef-4bb5-99be-5967c7ac1263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217565349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.217565349
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3371935460
Short name T204
Test name
Test status
Simulation time 682264425 ps
CPU time 14.7 seconds
Started Jul 12 04:35:03 PM PDT 24
Finished Jul 12 04:35:19 PM PDT 24
Peak memory 218532 kb
Host smart-fcc10a5d-8b26-4173-a7e8-912dd3125dfc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3371935460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3371935460
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2253080069
Short name T146
Test name
Test status
Simulation time 8338485715 ps
CPU time 43.16 seconds
Started Jul 12 04:34:56 PM PDT 24
Finished Jul 12 04:35:40 PM PDT 24
Peak memory 217748 kb
Host smart-f5fdab58-ae23-490c-ae34-050fa235cd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253080069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2253080069
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3481508046
Short name T334
Test name
Test status
Simulation time 41209792522 ps
CPU time 116.93 seconds
Started Jul 12 04:34:59 PM PDT 24
Finished Jul 12 04:36:58 PM PDT 24
Peak memory 220632 kb
Host smart-6223a5e4-94d6-455a-9ffb-fb30bbe992a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481508046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3481508046
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2471724939
Short name T332
Test name
Test status
Simulation time 31114561777 ps
CPU time 26.54 seconds
Started Jul 12 04:34:59 PM PDT 24
Finished Jul 12 04:35:28 PM PDT 24
Peak memory 217552 kb
Host smart-1e3dc388-373c-4614-8292-ad6277ce6239
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471724939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2471724939
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1435889704
Short name T156
Test name
Test status
Simulation time 549091643682 ps
CPU time 403.56 seconds
Started Jul 12 04:34:59 PM PDT 24
Finished Jul 12 04:41:45 PM PDT 24
Peak memory 237832 kb
Host smart-cb7e9a3a-f4ad-4b9b-9d18-264da54cb066
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435889704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1435889704
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.4199215504
Short name T342
Test name
Test status
Simulation time 27303543417 ps
CPU time 60.41 seconds
Started Jul 12 04:35:02 PM PDT 24
Finished Jul 12 04:36:05 PM PDT 24
Peak memory 219272 kb
Host smart-b89f610f-2c93-47fa-a927-10db7fb32390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199215504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.4199215504
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.76645162
Short name T288
Test name
Test status
Simulation time 596135752 ps
CPU time 10.47 seconds
Started Jul 12 04:34:55 PM PDT 24
Finished Jul 12 04:35:06 PM PDT 24
Peak memory 219492 kb
Host smart-ac7bd3b6-8123-41e3-b323-e2efe8537225
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=76645162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.76645162
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2228668022
Short name T291
Test name
Test status
Simulation time 709939611 ps
CPU time 20.83 seconds
Started Jul 12 04:34:54 PM PDT 24
Finished Jul 12 04:35:16 PM PDT 24
Peak memory 216516 kb
Host smart-8b0b52e7-3f3b-49a4-8fac-52f0a80c18f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228668022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2228668022
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3375447552
Short name T184
Test name
Test status
Simulation time 98847880581 ps
CPU time 90.28 seconds
Started Jul 12 04:34:58 PM PDT 24
Finished Jul 12 04:36:31 PM PDT 24
Peak memory 219296 kb
Host smart-b696f0f4-e450-4231-b116-4e5ab1714c25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375447552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3375447552
Directory /workspace/9.rom_ctrl_stress_all/latest
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