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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.31 96.89 92.13 97.68 100.00 98.62 97.45 98.37


Total test records in report: 454
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T298 /workspace/coverage/default/48.rom_ctrl_smoke.2731396858 Jul 13 04:44:47 PM PDT 24 Jul 13 04:45:44 PM PDT 24 4702413090 ps
T299 /workspace/coverage/default/14.rom_ctrl_smoke.895918676 Jul 13 04:43:40 PM PDT 24 Jul 13 04:44:02 PM PDT 24 358255913 ps
T300 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.616319046 Jul 13 04:44:14 PM PDT 24 Jul 13 04:44:39 PM PDT 24 7031370006 ps
T301 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2095007309 Jul 13 04:43:42 PM PDT 24 Jul 13 04:44:15 PM PDT 24 15501490594 ps
T302 /workspace/coverage/default/25.rom_ctrl_smoke.127640836 Jul 13 04:43:53 PM PDT 24 Jul 13 04:44:31 PM PDT 24 4131288298 ps
T303 /workspace/coverage/default/49.rom_ctrl_smoke.1995252961 Jul 13 04:44:45 PM PDT 24 Jul 13 04:45:17 PM PDT 24 3567143793 ps
T304 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1784700129 Jul 13 04:44:03 PM PDT 24 Jul 13 04:51:42 PM PDT 24 48484619919 ps
T305 /workspace/coverage/default/12.rom_ctrl_smoke.692863797 Jul 13 04:43:41 PM PDT 24 Jul 13 04:44:44 PM PDT 24 28919304239 ps
T29 /workspace/coverage/default/3.rom_ctrl_sec_cm.1576118687 Jul 13 04:44:32 PM PDT 24 Jul 13 04:46:43 PM PDT 24 3095761525 ps
T306 /workspace/coverage/default/18.rom_ctrl_stress_all.3600690122 Jul 13 04:43:45 PM PDT 24 Jul 13 04:46:40 PM PDT 24 83701699744 ps
T307 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.338619347 Jul 13 04:43:38 PM PDT 24 Jul 13 04:50:54 PM PDT 24 78571007143 ps
T308 /workspace/coverage/default/8.rom_ctrl_smoke.1752565660 Jul 13 04:43:38 PM PDT 24 Jul 13 04:44:30 PM PDT 24 5595488903 ps
T309 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1677085024 Jul 13 04:44:34 PM PDT 24 Jul 13 04:44:57 PM PDT 24 1840735814 ps
T310 /workspace/coverage/default/36.rom_ctrl_smoke.1540718258 Jul 13 04:44:09 PM PDT 24 Jul 13 04:45:03 PM PDT 24 25381951535 ps
T311 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.913057930 Jul 13 04:44:25 PM PDT 24 Jul 13 04:44:55 PM PDT 24 15298833592 ps
T312 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1487820337 Jul 13 04:44:34 PM PDT 24 Jul 13 04:45:32 PM PDT 24 13347948692 ps
T313 /workspace/coverage/default/41.rom_ctrl_alert_test.3072035307 Jul 13 04:44:25 PM PDT 24 Jul 13 04:44:34 PM PDT 24 345516950 ps
T314 /workspace/coverage/default/7.rom_ctrl_alert_test.921289301 Jul 13 04:43:33 PM PDT 24 Jul 13 04:43:57 PM PDT 24 10075342315 ps
T315 /workspace/coverage/default/3.rom_ctrl_stress_all.369189592 Jul 13 04:43:28 PM PDT 24 Jul 13 04:44:20 PM PDT 24 19040032204 ps
T316 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.4217489984 Jul 13 04:43:27 PM PDT 24 Jul 13 04:54:06 PM PDT 24 252794239657 ps
T317 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3377091389 Jul 13 04:43:55 PM PDT 24 Jul 13 04:44:25 PM PDT 24 14920322253 ps
T318 /workspace/coverage/default/16.rom_ctrl_stress_all.1163467647 Jul 13 04:43:49 PM PDT 24 Jul 13 04:44:21 PM PDT 24 1154584124 ps
T319 /workspace/coverage/default/27.rom_ctrl_smoke.2001779703 Jul 13 04:43:52 PM PDT 24 Jul 13 04:44:40 PM PDT 24 8940705948 ps
T320 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.160946286 Jul 13 04:44:44 PM PDT 24 Jul 13 04:45:15 PM PDT 24 1678195933 ps
T321 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.4264381055 Jul 13 04:44:01 PM PDT 24 Jul 13 04:44:23 PM PDT 24 346195932 ps
T322 /workspace/coverage/default/36.rom_ctrl_stress_all.2508080005 Jul 13 04:44:12 PM PDT 24 Jul 13 04:45:02 PM PDT 24 2098349231 ps
T323 /workspace/coverage/default/21.rom_ctrl_stress_all.425753457 Jul 13 04:44:41 PM PDT 24 Jul 13 04:45:30 PM PDT 24 3744553549 ps
T324 /workspace/coverage/default/11.rom_ctrl_stress_all.280764904 Jul 13 04:43:39 PM PDT 24 Jul 13 04:45:51 PM PDT 24 19581723433 ps
T325 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.960949327 Jul 13 04:43:42 PM PDT 24 Jul 13 04:44:05 PM PDT 24 4315149195 ps
T326 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2388917405 Jul 13 04:43:27 PM PDT 24 Jul 13 04:44:35 PM PDT 24 8354416663 ps
T327 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2028676117 Jul 13 04:44:46 PM PDT 24 Jul 13 04:50:30 PM PDT 24 36191163391 ps
T328 /workspace/coverage/default/19.rom_ctrl_alert_test.2213838737 Jul 13 04:43:48 PM PDT 24 Jul 13 04:44:09 PM PDT 24 2045055458 ps
T329 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.550145656 Jul 13 04:44:47 PM PDT 24 Jul 13 04:45:26 PM PDT 24 3023069392 ps
T330 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3946598603 Jul 13 04:43:30 PM PDT 24 Jul 13 04:43:59 PM PDT 24 2299865930 ps
T331 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3676278064 Jul 13 04:43:38 PM PDT 24 Jul 13 04:43:58 PM PDT 24 11979508005 ps
T332 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.46454955 Jul 13 04:43:49 PM PDT 24 Jul 13 04:44:39 PM PDT 24 5232047766 ps
T333 /workspace/coverage/default/18.rom_ctrl_alert_test.1427186173 Jul 13 04:43:42 PM PDT 24 Jul 13 04:44:04 PM PDT 24 2163031553 ps
T334 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1068399112 Jul 13 04:43:28 PM PDT 24 Jul 13 04:46:05 PM PDT 24 2178283415 ps
T335 /workspace/coverage/default/5.rom_ctrl_alert_test.418575776 Jul 13 04:43:28 PM PDT 24 Jul 13 04:43:39 PM PDT 24 661576357 ps
T336 /workspace/coverage/default/28.rom_ctrl_smoke.3844425222 Jul 13 04:44:01 PM PDT 24 Jul 13 04:44:49 PM PDT 24 5755002333 ps
T51 /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.90507541 Jul 13 04:44:44 PM PDT 24 Jul 13 04:57:17 PM PDT 24 37328350578 ps
T337 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1435689956 Jul 13 04:43:33 PM PDT 24 Jul 13 04:43:44 PM PDT 24 189857839 ps
T338 /workspace/coverage/default/47.rom_ctrl_stress_all.2088343374 Jul 13 04:44:34 PM PDT 24 Jul 13 04:45:58 PM PDT 24 5981715257 ps
T30 /workspace/coverage/default/4.rom_ctrl_sec_cm.1878673762 Jul 13 04:43:31 PM PDT 24 Jul 13 04:45:51 PM PDT 24 3522445921 ps
T339 /workspace/coverage/default/30.rom_ctrl_alert_test.869283154 Jul 13 04:43:59 PM PDT 24 Jul 13 04:44:21 PM PDT 24 7847625606 ps
T340 /workspace/coverage/default/40.rom_ctrl_smoke.2017206043 Jul 13 04:44:17 PM PDT 24 Jul 13 04:44:54 PM PDT 24 9873699598 ps
T341 /workspace/coverage/default/22.rom_ctrl_smoke.551851384 Jul 13 04:43:43 PM PDT 24 Jul 13 04:44:04 PM PDT 24 1527085591 ps
T342 /workspace/coverage/default/45.rom_ctrl_smoke.4024149836 Jul 13 04:44:37 PM PDT 24 Jul 13 04:45:14 PM PDT 24 4961540837 ps
T343 /workspace/coverage/default/17.rom_ctrl_smoke.939802430 Jul 13 04:43:45 PM PDT 24 Jul 13 04:44:32 PM PDT 24 68665667834 ps
T344 /workspace/coverage/default/31.rom_ctrl_smoke.3258734273 Jul 13 04:44:00 PM PDT 24 Jul 13 04:45:17 PM PDT 24 16139282730 ps
T345 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3127640019 Jul 13 04:44:43 PM PDT 24 Jul 13 04:45:41 PM PDT 24 24569522069 ps
T346 /workspace/coverage/default/16.rom_ctrl_alert_test.4152869576 Jul 13 04:43:44 PM PDT 24 Jul 13 04:44:11 PM PDT 24 4523561647 ps
T347 /workspace/coverage/default/29.rom_ctrl_stress_all.516409014 Jul 13 04:44:00 PM PDT 24 Jul 13 04:46:52 PM PDT 24 15591046570 ps
T348 /workspace/coverage/default/16.rom_ctrl_smoke.3822605212 Jul 13 04:43:49 PM PDT 24 Jul 13 04:44:09 PM PDT 24 722522390 ps
T349 /workspace/coverage/default/7.rom_ctrl_stress_all.1744330706 Jul 13 04:44:50 PM PDT 24 Jul 13 04:47:20 PM PDT 24 16113032440 ps
T350 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3883220421 Jul 13 04:44:26 PM PDT 24 Jul 13 04:45:28 PM PDT 24 7495770259 ps
T351 /workspace/coverage/default/0.rom_ctrl_alert_test.2421696255 Jul 13 04:43:27 PM PDT 24 Jul 13 04:44:04 PM PDT 24 4469389171 ps
T352 /workspace/coverage/default/20.rom_ctrl_alert_test.1135948923 Jul 13 04:43:48 PM PDT 24 Jul 13 04:44:20 PM PDT 24 5960974935 ps
T353 /workspace/coverage/default/27.rom_ctrl_alert_test.3098006597 Jul 13 04:44:03 PM PDT 24 Jul 13 04:44:13 PM PDT 24 307844068 ps
T354 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.463713754 Jul 13 04:43:38 PM PDT 24 Jul 13 04:47:22 PM PDT 24 49898356107 ps
T52 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.889925225 Jul 13 04:39:48 PM PDT 24 Jul 13 04:40:01 PM PDT 24 185669916 ps
T53 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3653849057 Jul 13 04:39:38 PM PDT 24 Jul 13 04:42:13 PM PDT 24 1485217728 ps
T65 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2125606442 Jul 13 04:39:26 PM PDT 24 Jul 13 04:40:00 PM PDT 24 11223329443 ps
T54 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.755888967 Jul 13 04:39:22 PM PDT 24 Jul 13 04:42:13 PM PDT 24 13030167114 ps
T72 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2505459812 Jul 13 04:39:19 PM PDT 24 Jul 13 04:40:00 PM PDT 24 2761809781 ps
T63 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1624396901 Jul 13 04:39:36 PM PDT 24 Jul 13 04:41:14 PM PDT 24 3106129193 ps
T106 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2992219018 Jul 13 04:39:41 PM PDT 24 Jul 13 04:40:06 PM PDT 24 7866495629 ps
T112 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.533074822 Jul 13 04:39:43 PM PDT 24 Jul 13 04:41:26 PM PDT 24 16447279695 ps
T355 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3382343819 Jul 13 04:39:40 PM PDT 24 Jul 13 04:39:56 PM PDT 24 1263982960 ps
T70 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3520607392 Jul 13 04:39:36 PM PDT 24 Jul 13 04:40:03 PM PDT 24 9448531587 ps
T71 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2649823255 Jul 13 04:39:21 PM PDT 24 Jul 13 04:39:51 PM PDT 24 5578567943 ps
T356 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1745252450 Jul 13 04:39:25 PM PDT 24 Jul 13 04:39:41 PM PDT 24 688859871 ps
T357 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1686935434 Jul 13 04:39:41 PM PDT 24 Jul 13 04:40:09 PM PDT 24 7260403974 ps
T73 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3070124504 Jul 13 04:39:39 PM PDT 24 Jul 13 04:40:31 PM PDT 24 27816158711 ps
T107 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2104208771 Jul 13 04:39:40 PM PDT 24 Jul 13 04:40:02 PM PDT 24 2170703712 ps
T358 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3960892358 Jul 13 04:39:25 PM PDT 24 Jul 13 04:39:52 PM PDT 24 29990530253 ps
T74 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2889158826 Jul 13 04:39:40 PM PDT 24 Jul 13 04:40:20 PM PDT 24 781149568 ps
T359 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1591485030 Jul 13 04:39:45 PM PDT 24 Jul 13 04:40:01 PM PDT 24 6472797474 ps
T360 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1929460271 Jul 13 04:39:21 PM PDT 24 Jul 13 04:39:41 PM PDT 24 6534512872 ps
T361 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1575103061 Jul 13 04:39:28 PM PDT 24 Jul 13 04:39:40 PM PDT 24 569438733 ps
T362 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.29945529 Jul 13 04:39:38 PM PDT 24 Jul 13 04:39:54 PM PDT 24 1166608692 ps
T75 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2911361486 Jul 13 04:39:26 PM PDT 24 Jul 13 04:39:56 PM PDT 24 6495289902 ps
T363 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.993654827 Jul 13 04:39:36 PM PDT 24 Jul 13 04:39:58 PM PDT 24 8881867400 ps
T115 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2256751700 Jul 13 04:39:52 PM PDT 24 Jul 13 04:42:48 PM PDT 24 4541383135 ps
T364 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.9725058 Jul 13 04:39:36 PM PDT 24 Jul 13 04:40:10 PM PDT 24 47483788468 ps
T365 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.4262057295 Jul 13 04:39:42 PM PDT 24 Jul 13 04:40:06 PM PDT 24 27896824168 ps
T116 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2099956008 Jul 13 04:40:24 PM PDT 24 Jul 13 04:41:51 PM PDT 24 350845777 ps
T366 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3507517748 Jul 13 04:39:36 PM PDT 24 Jul 13 04:39:56 PM PDT 24 6930828994 ps
T367 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3900705089 Jul 13 04:39:33 PM PDT 24 Jul 13 04:39:57 PM PDT 24 7705509821 ps
T113 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1653157312 Jul 13 04:39:32 PM PDT 24 Jul 13 04:39:57 PM PDT 24 2428128441 ps
T76 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.580398261 Jul 13 04:39:27 PM PDT 24 Jul 13 04:40:03 PM PDT 24 17102760900 ps
T108 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2816829429 Jul 13 04:39:13 PM PDT 24 Jul 13 04:39:41 PM PDT 24 18935035982 ps
T368 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2527661366 Jul 13 04:39:24 PM PDT 24 Jul 13 04:39:53 PM PDT 24 13030544428 ps
T117 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1084323276 Jul 13 04:39:18 PM PDT 24 Jul 13 04:42:07 PM PDT 24 2742115965 ps
T369 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.721422072 Jul 13 04:39:25 PM PDT 24 Jul 13 04:39:59 PM PDT 24 6602744718 ps
T124 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.4244190481 Jul 13 04:39:25 PM PDT 24 Jul 13 04:42:23 PM PDT 24 15919854399 ps
T370 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3959347219 Jul 13 04:39:30 PM PDT 24 Jul 13 04:40:05 PM PDT 24 2895150646 ps
T118 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2750815881 Jul 13 04:39:32 PM PDT 24 Jul 13 04:40:58 PM PDT 24 2740563197 ps
T109 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.309104524 Jul 13 04:39:39 PM PDT 24 Jul 13 04:40:06 PM PDT 24 17894423190 ps
T110 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3751994947 Jul 13 04:39:21 PM PDT 24 Jul 13 04:39:50 PM PDT 24 6624943334 ps
T371 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3173593317 Jul 13 04:39:25 PM PDT 24 Jul 13 04:39:55 PM PDT 24 3091703302 ps
T372 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.198106818 Jul 13 04:39:30 PM PDT 24 Jul 13 04:40:03 PM PDT 24 19566432042 ps
T373 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.31435605 Jul 13 04:39:31 PM PDT 24 Jul 13 04:39:47 PM PDT 24 1709838688 ps
T374 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.63307894 Jul 13 04:39:34 PM PDT 24 Jul 13 04:39:43 PM PDT 24 194468399 ps
T119 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3878718773 Jul 13 04:39:27 PM PDT 24 Jul 13 04:41:14 PM PDT 24 13858230587 ps
T111 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2610353252 Jul 13 04:39:16 PM PDT 24 Jul 13 04:39:42 PM PDT 24 1891136119 ps
T77 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1807037058 Jul 13 04:39:42 PM PDT 24 Jul 13 04:40:42 PM PDT 24 4288042119 ps
T121 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.219263695 Jul 13 04:39:41 PM PDT 24 Jul 13 04:41:09 PM PDT 24 1409292778 ps
T375 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4044771313 Jul 13 04:39:27 PM PDT 24 Jul 13 04:40:02 PM PDT 24 5078008183 ps
T376 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1134472869 Jul 13 04:39:48 PM PDT 24 Jul 13 04:40:11 PM PDT 24 13274068729 ps
T377 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1362605272 Jul 13 04:39:40 PM PDT 24 Jul 13 04:39:55 PM PDT 24 2108884496 ps
T78 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1732293424 Jul 13 04:39:26 PM PDT 24 Jul 13 04:42:31 PM PDT 24 93883875498 ps
T378 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3931672535 Jul 13 04:39:29 PM PDT 24 Jul 13 04:40:36 PM PDT 24 16487291565 ps
T379 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3338729870 Jul 13 04:39:29 PM PDT 24 Jul 13 04:41:15 PM PDT 24 13610043722 ps
T380 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.575538131 Jul 13 04:39:41 PM PDT 24 Jul 13 04:39:53 PM PDT 24 386053433 ps
T381 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3397862485 Jul 13 04:39:26 PM PDT 24 Jul 13 04:39:46 PM PDT 24 2799154558 ps
T79 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.129056362 Jul 13 04:39:26 PM PDT 24 Jul 13 04:41:01 PM PDT 24 29029911933 ps
T382 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1652820935 Jul 13 04:39:29 PM PDT 24 Jul 13 04:40:04 PM PDT 24 8366334949 ps
T383 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1829650120 Jul 13 04:39:26 PM PDT 24 Jul 13 04:39:41 PM PDT 24 2299273956 ps
T384 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3844312687 Jul 13 04:39:27 PM PDT 24 Jul 13 04:39:59 PM PDT 24 14339125381 ps
T80 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1227501894 Jul 13 04:39:24 PM PDT 24 Jul 13 04:39:55 PM PDT 24 33476895392 ps
T385 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2825524580 Jul 13 04:39:37 PM PDT 24 Jul 13 04:40:01 PM PDT 24 8918572496 ps
T386 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1005706642 Jul 13 04:39:26 PM PDT 24 Jul 13 04:39:56 PM PDT 24 3434629227 ps
T387 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.131648167 Jul 13 04:39:24 PM PDT 24 Jul 13 04:39:49 PM PDT 24 2058331942 ps
T81 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3835544716 Jul 13 04:39:40 PM PDT 24 Jul 13 04:40:00 PM PDT 24 3112564047 ps
T388 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.541421455 Jul 13 04:39:18 PM PDT 24 Jul 13 04:39:47 PM PDT 24 6164613492 ps
T389 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4288537573 Jul 13 04:39:25 PM PDT 24 Jul 13 04:39:47 PM PDT 24 3671985515 ps
T88 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2392942276 Jul 13 04:39:18 PM PDT 24 Jul 13 04:39:41 PM PDT 24 2221628806 ps
T390 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2007122647 Jul 13 04:39:26 PM PDT 24 Jul 13 04:40:06 PM PDT 24 17096239906 ps
T391 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1524846533 Jul 13 04:39:27 PM PDT 24 Jul 13 04:39:54 PM PDT 24 11542014916 ps
T392 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.119102324 Jul 13 04:39:36 PM PDT 24 Jul 13 04:39:59 PM PDT 24 21349712199 ps
T393 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3394145282 Jul 13 04:39:21 PM PDT 24 Jul 13 04:39:56 PM PDT 24 11547458440 ps
T394 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3097868076 Jul 13 04:39:28 PM PDT 24 Jul 13 04:39:55 PM PDT 24 9976603479 ps
T395 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.4263940073 Jul 13 04:39:41 PM PDT 24 Jul 13 04:42:19 PM PDT 24 1347532352 ps
T396 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3663251098 Jul 13 04:39:28 PM PDT 24 Jul 13 04:39:40 PM PDT 24 869459005 ps
T397 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2614427940 Jul 13 04:39:39 PM PDT 24 Jul 13 04:41:19 PM PDT 24 20829667822 ps
T120 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.100527825 Jul 13 04:39:35 PM PDT 24 Jul 13 04:42:16 PM PDT 24 8179566497 ps
T93 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1385131469 Jul 13 04:39:42 PM PDT 24 Jul 13 04:39:54 PM PDT 24 660462056 ps
T398 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2139417170 Jul 13 04:39:26 PM PDT 24 Jul 13 04:39:58 PM PDT 24 13967501187 ps
T399 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.883537589 Jul 13 04:39:35 PM PDT 24 Jul 13 04:40:07 PM PDT 24 14612476349 ps
T400 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.739972716 Jul 13 04:39:30 PM PDT 24 Jul 13 04:39:49 PM PDT 24 1302966385 ps
T401 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2875906687 Jul 13 04:39:24 PM PDT 24 Jul 13 04:40:54 PM PDT 24 1113724325 ps
T402 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2454165282 Jul 13 04:39:19 PM PDT 24 Jul 13 04:39:45 PM PDT 24 11192852735 ps
T125 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2822371949 Jul 13 04:39:20 PM PDT 24 Jul 13 04:42:24 PM PDT 24 18738889308 ps
T403 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3688902374 Jul 13 04:39:27 PM PDT 24 Jul 13 04:40:08 PM PDT 24 4246652675 ps
T404 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.706378088 Jul 13 04:39:36 PM PDT 24 Jul 13 04:39:48 PM PDT 24 346268880 ps
T405 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3939406883 Jul 13 04:39:37 PM PDT 24 Jul 13 04:40:06 PM PDT 24 23150047210 ps
T90 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3029065615 Jul 13 04:39:26 PM PDT 24 Jul 13 04:40:07 PM PDT 24 721303766 ps
T91 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1541244275 Jul 13 04:39:25 PM PDT 24 Jul 13 04:39:58 PM PDT 24 12452326696 ps
T406 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1983540636 Jul 13 04:39:27 PM PDT 24 Jul 13 04:41:34 PM PDT 24 28854794231 ps
T407 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.97865329 Jul 13 04:39:40 PM PDT 24 Jul 13 04:39:58 PM PDT 24 676393767 ps
T408 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2268515713 Jul 13 04:39:41 PM PDT 24 Jul 13 04:40:08 PM PDT 24 5701019517 ps
T409 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3280172091 Jul 13 04:39:27 PM PDT 24 Jul 13 04:39:55 PM PDT 24 2843945078 ps
T410 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2049335844 Jul 13 04:39:27 PM PDT 24 Jul 13 04:39:57 PM PDT 24 13378561428 ps
T123 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2390346814 Jul 13 04:39:27 PM PDT 24 Jul 13 04:42:18 PM PDT 24 3926086632 ps
T411 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3897997823 Jul 13 04:39:20 PM PDT 24 Jul 13 04:39:32 PM PDT 24 1914466579 ps
T412 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1214710471 Jul 13 04:39:25 PM PDT 24 Jul 13 04:41:27 PM PDT 24 19792588528 ps
T413 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1030612726 Jul 13 04:39:43 PM PDT 24 Jul 13 04:41:29 PM PDT 24 7070732373 ps
T414 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.4270616536 Jul 13 04:39:41 PM PDT 24 Jul 13 04:39:52 PM PDT 24 167697576 ps
T415 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.412150779 Jul 13 04:39:29 PM PDT 24 Jul 13 04:39:45 PM PDT 24 186581302 ps
T416 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1637511605 Jul 13 04:39:35 PM PDT 24 Jul 13 04:39:47 PM PDT 24 352020134 ps
T417 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2984598875 Jul 13 04:39:22 PM PDT 24 Jul 13 04:39:45 PM PDT 24 8843056772 ps
T418 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2254919762 Jul 13 04:39:36 PM PDT 24 Jul 13 04:39:46 PM PDT 24 688226636 ps
T419 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2474827219 Jul 13 04:39:39 PM PDT 24 Jul 13 04:39:49 PM PDT 24 171089648 ps
T420 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1387555834 Jul 13 04:39:41 PM PDT 24 Jul 13 04:40:14 PM PDT 24 3551011465 ps
T421 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1681558046 Jul 13 04:39:44 PM PDT 24 Jul 13 04:39:56 PM PDT 24 231482077 ps
T422 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2012791257 Jul 13 04:39:26 PM PDT 24 Jul 13 04:39:46 PM PDT 24 5363676667 ps
T423 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.609894870 Jul 13 04:39:40 PM PDT 24 Jul 13 04:39:59 PM PDT 24 682489860 ps
T122 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2745849661 Jul 13 04:39:42 PM PDT 24 Jul 13 04:42:27 PM PDT 24 10783813650 ps
T424 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3416472885 Jul 13 04:39:41 PM PDT 24 Jul 13 04:40:14 PM PDT 24 4776060736 ps
T425 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2286541694 Jul 13 04:39:26 PM PDT 24 Jul 13 04:40:50 PM PDT 24 244886115 ps
T426 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1820933845 Jul 13 04:39:39 PM PDT 24 Jul 13 04:41:16 PM PDT 24 4029648279 ps
T427 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.4032045879 Jul 13 04:39:24 PM PDT 24 Jul 13 04:40:05 PM PDT 24 53268866395 ps
T428 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.285644811 Jul 13 04:39:35 PM PDT 24 Jul 13 04:40:07 PM PDT 24 12152689208 ps
T429 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2133424547 Jul 13 04:39:28 PM PDT 24 Jul 13 04:39:53 PM PDT 24 849483218 ps
T430 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.34393585 Jul 13 04:39:39 PM PDT 24 Jul 13 04:40:32 PM PDT 24 4075691772 ps
T94 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.490200599 Jul 13 04:39:20 PM PDT 24 Jul 13 04:39:54 PM PDT 24 17055971645 ps
T431 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2657247794 Jul 13 04:39:43 PM PDT 24 Jul 13 04:40:10 PM PDT 24 9908371020 ps
T432 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.659668427 Jul 13 04:39:37 PM PDT 24 Jul 13 04:40:06 PM PDT 24 3362927421 ps
T433 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1054200052 Jul 13 04:39:43 PM PDT 24 Jul 13 04:40:11 PM PDT 24 2256201087 ps
T434 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.286489551 Jul 13 04:39:23 PM PDT 24 Jul 13 04:39:41 PM PDT 24 5961674664 ps
T435 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.282569561 Jul 13 04:39:38 PM PDT 24 Jul 13 04:40:11 PM PDT 24 8316700395 ps
T436 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1797176863 Jul 13 04:39:40 PM PDT 24 Jul 13 04:40:23 PM PDT 24 19360301441 ps
T437 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3235009154 Jul 13 04:39:27 PM PDT 24 Jul 13 04:39:48 PM PDT 24 1716244500 ps
T438 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1801282060 Jul 13 04:39:20 PM PDT 24 Jul 13 04:39:38 PM PDT 24 2803809180 ps
T439 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2413317019 Jul 13 04:39:31 PM PDT 24 Jul 13 04:40:00 PM PDT 24 11400815739 ps
T440 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1127242839 Jul 13 04:39:17 PM PDT 24 Jul 13 04:42:00 PM PDT 24 2808599115 ps
T441 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3676958267 Jul 13 04:39:43 PM PDT 24 Jul 13 04:40:09 PM PDT 24 2352017444 ps
T442 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3687289158 Jul 13 04:39:42 PM PDT 24 Jul 13 04:40:06 PM PDT 24 1888023086 ps
T89 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.4169979819 Jul 13 04:39:40 PM PDT 24 Jul 13 04:40:14 PM PDT 24 15937850706 ps
T443 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2297847720 Jul 13 04:39:34 PM PDT 24 Jul 13 04:39:55 PM PDT 24 1369636610 ps
T444 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3460262717 Jul 13 04:39:33 PM PDT 24 Jul 13 04:39:58 PM PDT 24 6573708048 ps
T445 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3334682240 Jul 13 04:39:24 PM PDT 24 Jul 13 04:42:48 PM PDT 24 51408742755 ps
T95 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3786478262 Jul 13 04:39:24 PM PDT 24 Jul 13 04:42:19 PM PDT 24 40949014990 ps
T446 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1532388290 Jul 13 04:39:20 PM PDT 24 Jul 13 04:39:30 PM PDT 24 719436555 ps
T447 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.4193533681 Jul 13 04:39:36 PM PDT 24 Jul 13 04:40:11 PM PDT 24 4268478435 ps
T448 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3164040878 Jul 13 04:39:21 PM PDT 24 Jul 13 04:41:37 PM PDT 24 16759054298 ps
T449 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3677828411 Jul 13 04:39:18 PM PDT 24 Jul 13 04:41:57 PM PDT 24 20542768654 ps
T450 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.426803756 Jul 13 04:39:39 PM PDT 24 Jul 13 04:39:53 PM PDT 24 493241904 ps
T451 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.34442350 Jul 13 04:39:25 PM PDT 24 Jul 13 04:39:56 PM PDT 24 6150916545 ps
T452 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2383931960 Jul 13 04:39:38 PM PDT 24 Jul 13 04:39:48 PM PDT 24 187301443 ps
T453 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3732626325 Jul 13 04:39:41 PM PDT 24 Jul 13 04:40:10 PM PDT 24 21238404074 ps
T92 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.811191395 Jul 13 04:39:42 PM PDT 24 Jul 13 04:40:41 PM PDT 24 4116798223 ps
T454 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.649308832 Jul 13 04:39:26 PM PDT 24 Jul 13 04:39:38 PM PDT 24 3482819060 ps

Test location /workspace/coverage/default/19.rom_ctrl_smoke.575965808
Short name T3
Test name
Test status
Simulation time 27067113287 ps
CPU time 68.66 seconds
Started Jul 13 04:43:42 PM PDT 24
Finished Jul 13 04:44:51 PM PDT 24
Peak memory 216508 kb
Host smart-53eb2f44-159c-4e4d-8b14-b6c5644188e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575965808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.575965808
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3478464355
Short name T24
Test name
Test status
Simulation time 45179799488 ps
CPU time 556.82 seconds
Started Jul 13 04:43:27 PM PDT 24
Finished Jul 13 04:52:47 PM PDT 24
Peak memory 238812 kb
Host smart-7bb1d62c-7f8e-4499-9899-0599fc12b5e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478464355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3478464355
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.2857061428
Short name T14
Test name
Test status
Simulation time 168044132447 ps
CPU time 5022.28 seconds
Started Jul 13 04:44:10 PM PDT 24
Finished Jul 13 06:07:53 PM PDT 24
Peak memory 236052 kb
Host smart-d6693619-f34d-4ddb-9c9c-9eaa22a912d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857061428 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.2857061428
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1040995674
Short name T34
Test name
Test status
Simulation time 10491597923 ps
CPU time 220.67 seconds
Started Jul 13 04:43:43 PM PDT 24
Finished Jul 13 04:47:24 PM PDT 24
Peak memory 225648 kb
Host smart-ece49162-9ff7-416b-bae9-3c7f376b0845
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040995674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1040995674
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2256751700
Short name T115
Test name
Test status
Simulation time 4541383135 ps
CPU time 174.96 seconds
Started Jul 13 04:39:52 PM PDT 24
Finished Jul 13 04:42:48 PM PDT 24
Peak memory 214056 kb
Host smart-40707e6a-ac28-4386-8e26-c621c9794ab2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256751700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2256751700
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.4245755554
Short name T36
Test name
Test status
Simulation time 21610814765 ps
CPU time 96.74 seconds
Started Jul 13 04:44:00 PM PDT 24
Finished Jul 13 04:45:39 PM PDT 24
Peak memory 219472 kb
Host smart-d0596c16-80e3-4a82-8810-8d092198c3d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245755554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.4245755554
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.4044495243
Short name T6
Test name
Test status
Simulation time 4135865467 ps
CPU time 22.64 seconds
Started Jul 13 04:44:00 PM PDT 24
Finished Jul 13 04:44:24 PM PDT 24
Peak memory 219324 kb
Host smart-c06091f3-5472-4b8f-ae01-1faebc9f71a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044495243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.4044495243
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.544748994
Short name T25
Test name
Test status
Simulation time 15364023354 ps
CPU time 128.4 seconds
Started Jul 13 04:44:50 PM PDT 24
Finished Jul 13 04:46:59 PM PDT 24
Peak memory 238420 kb
Host smart-3e1097c2-d6ef-4210-abea-6b0d4a77dd55
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544748994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.544748994
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3070124504
Short name T73
Test name
Test status
Simulation time 27816158711 ps
CPU time 51.14 seconds
Started Jul 13 04:39:39 PM PDT 24
Finished Jul 13 04:40:31 PM PDT 24
Peak memory 213808 kb
Host smart-00dccdc0-8071-4cb4-a9d3-86471799c9b2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070124504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3070124504
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.100527825
Short name T120
Test name
Test status
Simulation time 8179566497 ps
CPU time 158.97 seconds
Started Jul 13 04:39:35 PM PDT 24
Finished Jul 13 04:42:16 PM PDT 24
Peak memory 214060 kb
Host smart-96bf1fbe-3fb0-4c18-9db1-877b1ef83d81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100527825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.100527825
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1915018968
Short name T7
Test name
Test status
Simulation time 3303498894 ps
CPU time 25.27 seconds
Started Jul 13 04:43:29 PM PDT 24
Finished Jul 13 04:43:57 PM PDT 24
Peak memory 217236 kb
Host smart-74e1e4b7-ab8b-4271-8b11-90a2ac022162
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915018968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1915018968
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2907893675
Short name T9
Test name
Test status
Simulation time 1319724856 ps
CPU time 19.6 seconds
Started Jul 13 04:44:07 PM PDT 24
Finished Jul 13 04:44:27 PM PDT 24
Peak memory 219204 kb
Host smart-3ad941c4-05a3-4a1b-818d-74437508a095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907893675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2907893675
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1476455555
Short name T47
Test name
Test status
Simulation time 8335746819 ps
CPU time 63.29 seconds
Started Jul 13 04:43:59 PM PDT 24
Finished Jul 13 04:45:02 PM PDT 24
Peak memory 219292 kb
Host smart-9448c075-4019-4c47-a5f1-b545ac37d3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476455555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1476455555
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.755888967
Short name T54
Test name
Test status
Simulation time 13030167114 ps
CPU time 169.43 seconds
Started Jul 13 04:39:22 PM PDT 24
Finished Jul 13 04:42:13 PM PDT 24
Peak memory 214164 kb
Host smart-6e2451a1-f418-4937-9bea-9ab928ec289b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755888967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.755888967
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1550560285
Short name T13
Test name
Test status
Simulation time 14159837621 ps
CPU time 25.93 seconds
Started Jul 13 04:44:02 PM PDT 24
Finished Jul 13 04:44:30 PM PDT 24
Peak memory 214680 kb
Host smart-fe67bc47-67ac-4c3a-aa97-ea5ef41b3460
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550560285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1550560285
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1732293424
Short name T78
Test name
Test status
Simulation time 93883875498 ps
CPU time 182.4 seconds
Started Jul 13 04:39:26 PM PDT 24
Finished Jul 13 04:42:31 PM PDT 24
Peak memory 214708 kb
Host smart-fb1618ca-011e-4031-b0d9-b1f46d60918d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732293424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1732293424
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.668304337
Short name T163
Test name
Test status
Simulation time 1922709875 ps
CPU time 143.41 seconds
Started Jul 13 04:43:44 PM PDT 24
Finished Jul 13 04:46:09 PM PDT 24
Peak memory 238600 kb
Host smart-fc01b2e7-9e77-4fbf-8e11-685ebf2c9c9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668304337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.668304337
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2787791997
Short name T12
Test name
Test status
Simulation time 4943011005 ps
CPU time 23.97 seconds
Started Jul 13 04:43:28 PM PDT 24
Finished Jul 13 04:43:54 PM PDT 24
Peak memory 219292 kb
Host smart-50964744-40ba-4107-98d9-955f2e044655
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2787791997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2787791997
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3786478262
Short name T95
Test name
Test status
Simulation time 40949014990 ps
CPU time 173.25 seconds
Started Jul 13 04:39:24 PM PDT 24
Finished Jul 13 04:42:19 PM PDT 24
Peak memory 215072 kb
Host smart-ad9e8b7f-fd6f-4097-878d-55126425ceed
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786478262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3786478262
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.600698189
Short name T96
Test name
Test status
Simulation time 1381411542 ps
CPU time 14.86 seconds
Started Jul 13 04:43:44 PM PDT 24
Finished Jul 13 04:44:00 PM PDT 24
Peak memory 219024 kb
Host smart-af2771b0-95a4-402d-8ca7-028569dfbbe3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=600698189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.600698189
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.2586921800
Short name T18
Test name
Test status
Simulation time 252158191524 ps
CPU time 2464.32 seconds
Started Jul 13 04:43:39 PM PDT 24
Finished Jul 13 05:24:44 PM PDT 24
Peak memory 249888 kb
Host smart-c74aa6ed-62d8-414a-9fa5-1c065b9ea348
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586921800 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.2586921800
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2911361486
Short name T75
Test name
Test status
Simulation time 6495289902 ps
CPU time 27.14 seconds
Started Jul 13 04:39:26 PM PDT 24
Finished Jul 13 04:39:56 PM PDT 24
Peak memory 211652 kb
Host smart-acdfe4ae-48ca-4330-bd86-8f56078772ba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911361486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2911361486
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3900705089
Short name T367
Test name
Test status
Simulation time 7705509821 ps
CPU time 23.01 seconds
Started Jul 13 04:39:33 PM PDT 24
Finished Jul 13 04:39:57 PM PDT 24
Peak memory 211740 kb
Host smart-ae6865a1-a610-4d36-873e-86e6d61982bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900705089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3900705089
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3959347219
Short name T370
Test name
Test status
Simulation time 2895150646 ps
CPU time 32.56 seconds
Started Jul 13 04:39:30 PM PDT 24
Finished Jul 13 04:40:05 PM PDT 24
Peak memory 211324 kb
Host smart-b09f7bf4-cb1b-473f-8471-28fca67bec6c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959347219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3959347219
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.119102324
Short name T392
Test name
Test status
Simulation time 21349712199 ps
CPU time 22.18 seconds
Started Jul 13 04:39:36 PM PDT 24
Finished Jul 13 04:39:59 PM PDT 24
Peak memory 216684 kb
Host smart-4906f63b-6cf6-46da-97c2-3317c633af85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119102324 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.119102324
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.31435605
Short name T373
Test name
Test status
Simulation time 1709838688 ps
CPU time 13.65 seconds
Started Jul 13 04:39:31 PM PDT 24
Finished Jul 13 04:39:47 PM PDT 24
Peak memory 210992 kb
Host smart-f8724b57-191e-44f2-917f-05baccda79c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31435605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.31435605
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4044771313
Short name T375
Test name
Test status
Simulation time 5078008183 ps
CPU time 31.11 seconds
Started Jul 13 04:39:27 PM PDT 24
Finished Jul 13 04:40:02 PM PDT 24
Peak memory 210548 kb
Host smart-fba6bebc-161c-478b-8166-9d68f5ff3dd5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044771313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.4044771313
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3173593317
Short name T371
Test name
Test status
Simulation time 3091703302 ps
CPU time 26.6 seconds
Started Jul 13 04:39:25 PM PDT 24
Finished Jul 13 04:39:55 PM PDT 24
Peak memory 210492 kb
Host smart-6a15d6bd-e067-4b2d-82fe-d8b7145dda31
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173593317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3173593317
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2610353252
Short name T111
Test name
Test status
Simulation time 1891136119 ps
CPU time 23.05 seconds
Started Jul 13 04:39:16 PM PDT 24
Finished Jul 13 04:39:42 PM PDT 24
Peak memory 212248 kb
Host smart-0e9ad9f0-0edd-4530-810d-a3f276681027
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610353252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2610353252
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.706378088
Short name T404
Test name
Test status
Simulation time 346268880 ps
CPU time 10.95 seconds
Started Jul 13 04:39:36 PM PDT 24
Finished Jul 13 04:39:48 PM PDT 24
Peak memory 217128 kb
Host smart-733a4aa7-544e-4a85-9f8e-5556563a0ddb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706378088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.706378088
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2822371949
Short name T125
Test name
Test status
Simulation time 18738889308 ps
CPU time 182.31 seconds
Started Jul 13 04:39:20 PM PDT 24
Finished Jul 13 04:42:24 PM PDT 24
Peak memory 214096 kb
Host smart-b9f3db20-7f62-4952-9431-d65fd8c3be59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822371949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2822371949
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1541244275
Short name T91
Test name
Test status
Simulation time 12452326696 ps
CPU time 25.65 seconds
Started Jul 13 04:39:25 PM PDT 24
Finished Jul 13 04:39:58 PM PDT 24
Peak memory 212164 kb
Host smart-1aed5b91-1453-49e8-a72a-76c0690e7d8e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541244275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1541244275
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.198106818
Short name T372
Test name
Test status
Simulation time 19566432042 ps
CPU time 30.25 seconds
Started Jul 13 04:39:30 PM PDT 24
Finished Jul 13 04:40:03 PM PDT 24
Peak memory 211652 kb
Host smart-87d506de-a46f-441d-b5db-5ced6d0a2e2d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198106818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.198106818
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1005706642
Short name T386
Test name
Test status
Simulation time 3434629227 ps
CPU time 26.25 seconds
Started Jul 13 04:39:26 PM PDT 24
Finished Jul 13 04:39:56 PM PDT 24
Peak memory 211876 kb
Host smart-b3b3c51d-ac36-4915-83e4-9a56ac2e0237
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005706642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1005706642
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.993654827
Short name T363
Test name
Test status
Simulation time 8881867400 ps
CPU time 21.02 seconds
Started Jul 13 04:39:36 PM PDT 24
Finished Jul 13 04:39:58 PM PDT 24
Peak memory 215244 kb
Host smart-75305758-883e-40c1-96b8-454a2bf0a2a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993654827 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.993654827
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4288537573
Short name T389
Test name
Test status
Simulation time 3671985515 ps
CPU time 19.51 seconds
Started Jul 13 04:39:25 PM PDT 24
Finished Jul 13 04:39:47 PM PDT 24
Peak memory 210600 kb
Host smart-e30f3272-6817-40fa-b722-1a637c0bc1c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288537573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.4288537573
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1532388290
Short name T446
Test name
Test status
Simulation time 719436555 ps
CPU time 8.15 seconds
Started Jul 13 04:39:20 PM PDT 24
Finished Jul 13 04:39:30 PM PDT 24
Peak memory 210492 kb
Host smart-a7a29f11-3e89-4757-9967-854c74461b90
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532388290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1532388290
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.541421455
Short name T388
Test name
Test status
Simulation time 6164613492 ps
CPU time 27.34 seconds
Started Jul 13 04:39:18 PM PDT 24
Finished Jul 13 04:39:47 PM PDT 24
Peak memory 210524 kb
Host smart-c60b6c10-308e-4aee-839d-f0b51ec37a18
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541421455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
541421455
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3677828411
Short name T449
Test name
Test status
Simulation time 20542768654 ps
CPU time 156.98 seconds
Started Jul 13 04:39:18 PM PDT 24
Finished Jul 13 04:41:57 PM PDT 24
Peak memory 214144 kb
Host smart-9a352ea4-d51b-4490-8f93-9a8e8261f02d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677828411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3677828411
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2816829429
Short name T108
Test name
Test status
Simulation time 18935035982 ps
CPU time 26.2 seconds
Started Jul 13 04:39:13 PM PDT 24
Finished Jul 13 04:39:41 PM PDT 24
Peak memory 212296 kb
Host smart-c326a1a1-a7f5-4606-8c91-ce5be6baf775
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816829429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2816829429
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2413317019
Short name T439
Test name
Test status
Simulation time 11400815739 ps
CPU time 26.9 seconds
Started Jul 13 04:39:31 PM PDT 24
Finished Jul 13 04:40:00 PM PDT 24
Peak memory 218576 kb
Host smart-008bca9d-db04-474a-bf83-efb73a663329
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413317019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2413317019
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2750815881
Short name T118
Test name
Test status
Simulation time 2740563197 ps
CPU time 83.8 seconds
Started Jul 13 04:39:32 PM PDT 24
Finished Jul 13 04:40:58 PM PDT 24
Peak memory 213620 kb
Host smart-096e6f69-060b-4055-97b3-55debefe5cc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750815881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2750815881
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1801282060
Short name T438
Test name
Test status
Simulation time 2803809180 ps
CPU time 16.95 seconds
Started Jul 13 04:39:20 PM PDT 24
Finished Jul 13 04:39:38 PM PDT 24
Peak memory 214528 kb
Host smart-29c8f46c-436f-4578-acc9-162760153af0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801282060 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1801282060
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3751994947
Short name T110
Test name
Test status
Simulation time 6624943334 ps
CPU time 26.53 seconds
Started Jul 13 04:39:21 PM PDT 24
Finished Jul 13 04:39:50 PM PDT 24
Peak memory 211828 kb
Host smart-0045849e-7b24-4474-8aa8-9a8a25f96d57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751994947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3751994947
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.129056362
Short name T79
Test name
Test status
Simulation time 29029911933 ps
CPU time 92.21 seconds
Started Jul 13 04:39:26 PM PDT 24
Finished Jul 13 04:41:01 PM PDT 24
Peak memory 218672 kb
Host smart-261fcf96-fcbb-4aae-bd78-ce208cfb3dd8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129056362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.129056362
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.309104524
Short name T109
Test name
Test status
Simulation time 17894423190 ps
CPU time 25.69 seconds
Started Jul 13 04:39:39 PM PDT 24
Finished Jul 13 04:40:06 PM PDT 24
Peak memory 213064 kb
Host smart-dd443fa4-b170-42aa-9dfa-28a9c2578d94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309104524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.309104524
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.889925225
Short name T52
Test name
Test status
Simulation time 185669916 ps
CPU time 11.98 seconds
Started Jul 13 04:39:48 PM PDT 24
Finished Jul 13 04:40:01 PM PDT 24
Peak memory 218200 kb
Host smart-2d7e8448-30ef-4095-b753-f3fdaa713e14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889925225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.889925225
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3653849057
Short name T53
Test name
Test status
Simulation time 1485217728 ps
CPU time 155.01 seconds
Started Jul 13 04:39:38 PM PDT 24
Finished Jul 13 04:42:13 PM PDT 24
Peak memory 213896 kb
Host smart-6efddae3-dcdf-45bd-8104-8fd278fd737b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653849057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3653849057
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3688902374
Short name T403
Test name
Test status
Simulation time 4246652675 ps
CPU time 34.15 seconds
Started Jul 13 04:39:27 PM PDT 24
Finished Jul 13 04:40:08 PM PDT 24
Peak memory 218104 kb
Host smart-0cb165f1-39a6-459f-b648-416c3d95fd1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688902374 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3688902374
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2268515713
Short name T408
Test name
Test status
Simulation time 5701019517 ps
CPU time 24.14 seconds
Started Jul 13 04:39:41 PM PDT 24
Finished Jul 13 04:40:08 PM PDT 24
Peak memory 212208 kb
Host smart-4de4f190-fc06-4602-868c-a028f47b768a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268515713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2268515713
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1214710471
Short name T412
Test name
Test status
Simulation time 19792588528 ps
CPU time 119.39 seconds
Started Jul 13 04:39:25 PM PDT 24
Finished Jul 13 04:41:27 PM PDT 24
Peak memory 215180 kb
Host smart-abcd08aa-aa98-4ca8-a4f1-fdf941dde6b2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214710471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1214710471
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3732626325
Short name T453
Test name
Test status
Simulation time 21238404074 ps
CPU time 26.31 seconds
Started Jul 13 04:39:41 PM PDT 24
Finished Jul 13 04:40:10 PM PDT 24
Peak memory 212396 kb
Host smart-ebeed3f3-21f8-4454-888f-634d3fbd3f7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732626325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3732626325
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1134472869
Short name T376
Test name
Test status
Simulation time 13274068729 ps
CPU time 22.51 seconds
Started Jul 13 04:39:48 PM PDT 24
Finished Jul 13 04:40:11 PM PDT 24
Peak memory 218404 kb
Host smart-54a458af-61f6-4346-a0b0-89dd467462cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134472869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1134472869
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.4244190481
Short name T124
Test name
Test status
Simulation time 15919854399 ps
CPU time 176.1 seconds
Started Jul 13 04:39:25 PM PDT 24
Finished Jul 13 04:42:23 PM PDT 24
Peak memory 214180 kb
Host smart-5e0dd007-1604-4a65-826c-466cc1d37e54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244190481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.4244190481
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1362605272
Short name T377
Test name
Test status
Simulation time 2108884496 ps
CPU time 12.62 seconds
Started Jul 13 04:39:40 PM PDT 24
Finished Jul 13 04:39:55 PM PDT 24
Peak memory 216248 kb
Host smart-e52260d7-b825-4d22-a628-294f1217021f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362605272 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1362605272
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3897997823
Short name T411
Test name
Test status
Simulation time 1914466579 ps
CPU time 10.15 seconds
Started Jul 13 04:39:20 PM PDT 24
Finished Jul 13 04:39:32 PM PDT 24
Peak memory 210640 kb
Host smart-ccb831e9-c0cf-4f71-9489-fe2363aa082d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897997823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3897997823
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.412150779
Short name T415
Test name
Test status
Simulation time 186581302 ps
CPU time 12.69 seconds
Started Jul 13 04:39:29 PM PDT 24
Finished Jul 13 04:39:45 PM PDT 24
Peak memory 212400 kb
Host smart-006d82b6-b60f-4c5b-80bc-d6663f7c9f08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412150779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.412150779
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.4032045879
Short name T427
Test name
Test status
Simulation time 53268866395 ps
CPU time 39.61 seconds
Started Jul 13 04:39:24 PM PDT 24
Finished Jul 13 04:40:05 PM PDT 24
Peak memory 218900 kb
Host smart-aa87ee5b-c8fc-4a85-b2a3-936a9b94b6ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032045879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.4032045879
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1084323276
Short name T117
Test name
Test status
Simulation time 2742115965 ps
CPU time 166.9 seconds
Started Jul 13 04:39:18 PM PDT 24
Finished Jul 13 04:42:07 PM PDT 24
Peak memory 213760 kb
Host smart-1182e11e-78b0-4e13-bdb3-1a05783eee70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084323276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1084323276
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1686935434
Short name T357
Test name
Test status
Simulation time 7260403974 ps
CPU time 20.75 seconds
Started Jul 13 04:39:41 PM PDT 24
Finished Jul 13 04:40:09 PM PDT 24
Peak memory 217268 kb
Host smart-39b4143b-812f-44ad-87a3-6a830fbcdb18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686935434 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1686935434
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2125606442
Short name T65
Test name
Test status
Simulation time 11223329443 ps
CPU time 26.31 seconds
Started Jul 13 04:39:26 PM PDT 24
Finished Jul 13 04:40:00 PM PDT 24
Peak memory 212024 kb
Host smart-3075aca7-41d6-48ac-a0db-7df2b7b5d54c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125606442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2125606442
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3931672535
Short name T378
Test name
Test status
Simulation time 16487291565 ps
CPU time 63.99 seconds
Started Jul 13 04:39:29 PM PDT 24
Finished Jul 13 04:40:36 PM PDT 24
Peak memory 214784 kb
Host smart-b5881229-bf67-44e4-ab8e-e6410be2f988
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931672535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3931672535
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3663251098
Short name T396
Test name
Test status
Simulation time 869459005 ps
CPU time 8.22 seconds
Started Jul 13 04:39:28 PM PDT 24
Finished Jul 13 04:39:40 PM PDT 24
Peak memory 211288 kb
Host smart-d8df2893-9502-4d30-bf8f-6c1496860afc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663251098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3663251098
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.4262057295
Short name T365
Test name
Test status
Simulation time 27896824168 ps
CPU time 21.14 seconds
Started Jul 13 04:39:42 PM PDT 24
Finished Jul 13 04:40:06 PM PDT 24
Peak memory 218448 kb
Host smart-fbb00d1c-6325-4afd-8be8-824c7dd0be10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262057295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.4262057295
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2099956008
Short name T116
Test name
Test status
Simulation time 350845777 ps
CPU time 85.41 seconds
Started Jul 13 04:40:24 PM PDT 24
Finished Jul 13 04:41:51 PM PDT 24
Peak memory 213820 kb
Host smart-37d5fade-7917-48c5-9baa-782360741990
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099956008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2099956008
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.9725058
Short name T364
Test name
Test status
Simulation time 47483788468 ps
CPU time 32.95 seconds
Started Jul 13 04:39:36 PM PDT 24
Finished Jul 13 04:40:10 PM PDT 24
Peak memory 218492 kb
Host smart-e566670e-2c61-4f06-83ea-8c4bab73db33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9725058 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.9725058
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3844312687
Short name T384
Test name
Test status
Simulation time 14339125381 ps
CPU time 28.73 seconds
Started Jul 13 04:39:27 PM PDT 24
Finished Jul 13 04:39:59 PM PDT 24
Peak memory 211944 kb
Host smart-a99f36e3-77ea-45b4-afee-52cb83208ebe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844312687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3844312687
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1983540636
Short name T406
Test name
Test status
Simulation time 28854794231 ps
CPU time 123.33 seconds
Started Jul 13 04:39:27 PM PDT 24
Finished Jul 13 04:41:34 PM PDT 24
Peak memory 213760 kb
Host smart-6fbb985a-5fc9-485d-a200-fab4d9f23cbb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983540636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1983540636
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3835544716
Short name T81
Test name
Test status
Simulation time 3112564047 ps
CPU time 17.5 seconds
Started Jul 13 04:39:40 PM PDT 24
Finished Jul 13 04:40:00 PM PDT 24
Peak memory 212424 kb
Host smart-5859fd82-b4a3-4f5b-9ae3-a8e20fdd32a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835544716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3835544716
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3460262717
Short name T444
Test name
Test status
Simulation time 6573708048 ps
CPU time 23.74 seconds
Started Jul 13 04:39:33 PM PDT 24
Finished Jul 13 04:39:58 PM PDT 24
Peak memory 217652 kb
Host smart-ca750c09-4188-4441-8001-1514910e3cfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460262717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3460262717
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1624396901
Short name T63
Test name
Test status
Simulation time 3106129193 ps
CPU time 96.97 seconds
Started Jul 13 04:39:36 PM PDT 24
Finished Jul 13 04:41:14 PM PDT 24
Peak memory 213668 kb
Host smart-f6804df1-d50f-4bad-8f32-faca2b4ad5da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624396901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1624396901
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2825524580
Short name T385
Test name
Test status
Simulation time 8918572496 ps
CPU time 22.8 seconds
Started Jul 13 04:39:37 PM PDT 24
Finished Jul 13 04:40:01 PM PDT 24
Peak memory 218308 kb
Host smart-ba22f39c-e5a9-4351-8eba-a208c93b8d77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825524580 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2825524580
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.580398261
Short name T76
Test name
Test status
Simulation time 17102760900 ps
CPU time 29.89 seconds
Started Jul 13 04:39:27 PM PDT 24
Finished Jul 13 04:40:03 PM PDT 24
Peak memory 212284 kb
Host smart-07a53380-e57d-4d88-b149-abaee4284668
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580398261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.580398261
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.533074822
Short name T112
Test name
Test status
Simulation time 16447279695 ps
CPU time 99.3 seconds
Started Jul 13 04:39:43 PM PDT 24
Finished Jul 13 04:41:26 PM PDT 24
Peak memory 214052 kb
Host smart-4c0d5c85-ac15-4f1a-ad76-857ccb0817d3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533074822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.533074822
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.426803756
Short name T450
Test name
Test status
Simulation time 493241904 ps
CPU time 11.51 seconds
Started Jul 13 04:39:39 PM PDT 24
Finished Jul 13 04:39:53 PM PDT 24
Peak memory 211044 kb
Host smart-1f558b6b-b8b1-4acd-9d38-e552b2900269
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426803756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.426803756
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3939406883
Short name T405
Test name
Test status
Simulation time 23150047210 ps
CPU time 27.6 seconds
Started Jul 13 04:39:37 PM PDT 24
Finished Jul 13 04:40:06 PM PDT 24
Peak memory 217292 kb
Host smart-0ad5e4dd-c1a5-476b-9ac3-33b3df6aeee8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939406883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3939406883
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2390346814
Short name T123
Test name
Test status
Simulation time 3926086632 ps
CPU time 167.51 seconds
Started Jul 13 04:39:27 PM PDT 24
Finished Jul 13 04:42:18 PM PDT 24
Peak memory 213896 kb
Host smart-86e3881d-42f8-4bfe-a1d0-c851eca345ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390346814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2390346814
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1797176863
Short name T436
Test name
Test status
Simulation time 19360301441 ps
CPU time 32.9 seconds
Started Jul 13 04:39:40 PM PDT 24
Finished Jul 13 04:40:23 PM PDT 24
Peak memory 217792 kb
Host smart-ccc2edd3-988c-40af-96b0-e20b2077b499
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797176863 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1797176863
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1385131469
Short name T93
Test name
Test status
Simulation time 660462056 ps
CPU time 8.42 seconds
Started Jul 13 04:39:42 PM PDT 24
Finished Jul 13 04:39:54 PM PDT 24
Peak memory 210748 kb
Host smart-a0d6c169-fd24-46a6-8a98-ebe42fdfe210
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385131469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1385131469
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3164040878
Short name T448
Test name
Test status
Simulation time 16759054298 ps
CPU time 134.37 seconds
Started Jul 13 04:39:21 PM PDT 24
Finished Jul 13 04:41:37 PM PDT 24
Peak memory 214328 kb
Host smart-d382e694-1117-48df-9171-a931af53c066
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164040878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3164040878
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1681558046
Short name T421
Test name
Test status
Simulation time 231482077 ps
CPU time 8.77 seconds
Started Jul 13 04:39:44 PM PDT 24
Finished Jul 13 04:39:56 PM PDT 24
Peak memory 211332 kb
Host smart-9ddd78eb-c0f0-47bf-bd11-09e7ae71167d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681558046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1681558046
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2649823255
Short name T71
Test name
Test status
Simulation time 5578567943 ps
CPU time 28.32 seconds
Started Jul 13 04:39:21 PM PDT 24
Finished Jul 13 04:39:51 PM PDT 24
Peak memory 217456 kb
Host smart-76f44660-fc7f-4c9d-b217-350d331df7f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649823255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2649823255
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2875906687
Short name T401
Test name
Test status
Simulation time 1113724325 ps
CPU time 88.84 seconds
Started Jul 13 04:39:24 PM PDT 24
Finished Jul 13 04:40:54 PM PDT 24
Peak memory 213464 kb
Host smart-f75443f1-deed-4740-88ff-d13478470fd3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875906687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2875906687
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.649308832
Short name T454
Test name
Test status
Simulation time 3482819060 ps
CPU time 8.19 seconds
Started Jul 13 04:39:26 PM PDT 24
Finished Jul 13 04:39:38 PM PDT 24
Peak memory 218804 kb
Host smart-c84f89f8-3d1d-4d2f-bfc3-9d0a2335aee3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649308832 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.649308832
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.29945529
Short name T362
Test name
Test status
Simulation time 1166608692 ps
CPU time 15.66 seconds
Started Jul 13 04:39:38 PM PDT 24
Finished Jul 13 04:39:54 PM PDT 24
Peak memory 210512 kb
Host smart-b03d997a-5dd4-47df-8cf7-f23dedebe5f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29945529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.29945529
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1030612726
Short name T413
Test name
Test status
Simulation time 7070732373 ps
CPU time 103.08 seconds
Started Jul 13 04:39:43 PM PDT 24
Finished Jul 13 04:41:29 PM PDT 24
Peak memory 215128 kb
Host smart-a0e059f5-bbc2-422c-b171-83fb0dc40e43
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030612726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1030612726
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2049335844
Short name T410
Test name
Test status
Simulation time 13378561428 ps
CPU time 27.36 seconds
Started Jul 13 04:39:27 PM PDT 24
Finished Jul 13 04:39:57 PM PDT 24
Peak memory 212356 kb
Host smart-5de280b5-5e15-4142-a098-63cb969f438c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049335844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2049335844
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2133424547
Short name T429
Test name
Test status
Simulation time 849483218 ps
CPU time 18.27 seconds
Started Jul 13 04:39:28 PM PDT 24
Finished Jul 13 04:39:53 PM PDT 24
Peak memory 217224 kb
Host smart-3eaed32f-b4f7-4a70-84c1-fbbce95b2778
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133424547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2133424547
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2383931960
Short name T452
Test name
Test status
Simulation time 187301443 ps
CPU time 8.88 seconds
Started Jul 13 04:39:38 PM PDT 24
Finished Jul 13 04:39:48 PM PDT 24
Peak memory 215684 kb
Host smart-98115f31-8e5f-42bf-99aa-d0bbf392b7de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383931960 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2383931960
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2454165282
Short name T402
Test name
Test status
Simulation time 11192852735 ps
CPU time 24.64 seconds
Started Jul 13 04:39:19 PM PDT 24
Finished Jul 13 04:39:45 PM PDT 24
Peak memory 211844 kb
Host smart-38dd5533-aa78-407e-8710-b5dbe76c4051
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454165282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2454165282
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1807037058
Short name T77
Test name
Test status
Simulation time 4288042119 ps
CPU time 56.68 seconds
Started Jul 13 04:39:42 PM PDT 24
Finished Jul 13 04:40:42 PM PDT 24
Peak memory 215068 kb
Host smart-2d497088-8663-4504-be5f-8585382ae7fc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807037058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1807037058
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1829650120
Short name T383
Test name
Test status
Simulation time 2299273956 ps
CPU time 12.15 seconds
Started Jul 13 04:39:26 PM PDT 24
Finished Jul 13 04:39:41 PM PDT 24
Peak memory 211188 kb
Host smart-fc570fdc-bbc0-46c1-906b-e57acd647bf2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829650120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1829650120
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.285644811
Short name T428
Test name
Test status
Simulation time 12152689208 ps
CPU time 30.86 seconds
Started Jul 13 04:39:35 PM PDT 24
Finished Jul 13 04:40:07 PM PDT 24
Peak memory 218484 kb
Host smart-071003bf-7120-4768-84be-267cf8504f40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285644811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.285644811
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3878718773
Short name T119
Test name
Test status
Simulation time 13858230587 ps
CPU time 103.05 seconds
Started Jul 13 04:39:27 PM PDT 24
Finished Jul 13 04:41:14 PM PDT 24
Peak memory 213528 kb
Host smart-b8275dad-3515-4757-ac41-2403cb2dceac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878718773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3878718773
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3676958267
Short name T441
Test name
Test status
Simulation time 2352017444 ps
CPU time 22.56 seconds
Started Jul 13 04:39:43 PM PDT 24
Finished Jul 13 04:40:09 PM PDT 24
Peak memory 217184 kb
Host smart-412ade21-881f-464f-bec9-843531be52f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676958267 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3676958267
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1227501894
Short name T80
Test name
Test status
Simulation time 33476895392 ps
CPU time 29.39 seconds
Started Jul 13 04:39:24 PM PDT 24
Finished Jul 13 04:39:55 PM PDT 24
Peak memory 212252 kb
Host smart-39629a15-3d57-43d4-a185-d9567ffc77f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227501894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1227501894
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.811191395
Short name T92
Test name
Test status
Simulation time 4116798223 ps
CPU time 55.55 seconds
Started Jul 13 04:39:42 PM PDT 24
Finished Jul 13 04:40:41 PM PDT 24
Peak memory 211680 kb
Host smart-a9a9ac61-b19b-4911-a0b7-47030552d6e8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811191395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.811191395
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3280172091
Short name T409
Test name
Test status
Simulation time 2843945078 ps
CPU time 24.41 seconds
Started Jul 13 04:39:27 PM PDT 24
Finished Jul 13 04:39:55 PM PDT 24
Peak memory 212172 kb
Host smart-a76a2ca3-3bbd-460d-b548-6a25459bc97e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280172091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3280172091
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3416472885
Short name T424
Test name
Test status
Simulation time 4776060736 ps
CPU time 30.54 seconds
Started Jul 13 04:39:41 PM PDT 24
Finished Jul 13 04:40:14 PM PDT 24
Peak memory 217688 kb
Host smart-16d6904e-42d2-48bc-8906-e88be814d5e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416472885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3416472885
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.219263695
Short name T121
Test name
Test status
Simulation time 1409292778 ps
CPU time 85.21 seconds
Started Jul 13 04:39:41 PM PDT 24
Finished Jul 13 04:41:09 PM PDT 24
Peak memory 213544 kb
Host smart-24528f4c-d70e-4793-8621-5ad820c6ce3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219263695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.219263695
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2474827219
Short name T419
Test name
Test status
Simulation time 171089648 ps
CPU time 8.41 seconds
Started Jul 13 04:39:39 PM PDT 24
Finished Jul 13 04:39:49 PM PDT 24
Peak memory 210240 kb
Host smart-1a6d7ba3-119a-4778-8e00-1bf953dc9b57
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474827219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2474827219
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.63307894
Short name T374
Test name
Test status
Simulation time 194468399 ps
CPU time 8.37 seconds
Started Jul 13 04:39:34 PM PDT 24
Finished Jul 13 04:39:43 PM PDT 24
Peak memory 210592 kb
Host smart-c28a6501-ce64-4311-85aa-0dbb5a4db1e9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63307894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_ba
sh.63307894
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.721422072
Short name T369
Test name
Test status
Simulation time 6602744718 ps
CPU time 32.12 seconds
Started Jul 13 04:39:25 PM PDT 24
Finished Jul 13 04:39:59 PM PDT 24
Peak memory 211884 kb
Host smart-2ebb1d9e-1147-4876-b9b2-bd1b9cc05868
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721422072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.721422072
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1387555834
Short name T420
Test name
Test status
Simulation time 3551011465 ps
CPU time 29.66 seconds
Started Jul 13 04:39:41 PM PDT 24
Finished Jul 13 04:40:14 PM PDT 24
Peak memory 215744 kb
Host smart-9891d3ea-42e4-4912-920e-d0e1637d615b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387555834 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1387555834
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1653157312
Short name T113
Test name
Test status
Simulation time 2428128441 ps
CPU time 23.26 seconds
Started Jul 13 04:39:32 PM PDT 24
Finished Jul 13 04:39:57 PM PDT 24
Peak memory 211648 kb
Host smart-4fe9c6c5-d789-4bb2-a9b0-ffe8cd11c323
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653157312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1653157312
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1929460271
Short name T360
Test name
Test status
Simulation time 6534512872 ps
CPU time 19.28 seconds
Started Jul 13 04:39:21 PM PDT 24
Finished Jul 13 04:39:41 PM PDT 24
Peak memory 210820 kb
Host smart-b693b83d-6bc5-438c-9b19-0ead69cec2a2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929460271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1929460271
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2527661366
Short name T368
Test name
Test status
Simulation time 13030544428 ps
CPU time 27.95 seconds
Started Jul 13 04:39:24 PM PDT 24
Finished Jul 13 04:39:53 PM PDT 24
Peak memory 210764 kb
Host smart-29b4bb66-5384-4f34-91a5-61f37207f4ca
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527661366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2527661366
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.34393585
Short name T430
Test name
Test status
Simulation time 4075691772 ps
CPU time 51.17 seconds
Started Jul 13 04:39:39 PM PDT 24
Finished Jul 13 04:40:32 PM PDT 24
Peak memory 214796 kb
Host smart-7c8937f9-50fe-4025-9c8f-7cdff92f2dc6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34393585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pass
thru_mem_tl_intg_err.34393585
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.4193533681
Short name T447
Test name
Test status
Simulation time 4268478435 ps
CPU time 33.55 seconds
Started Jul 13 04:39:36 PM PDT 24
Finished Jul 13 04:40:11 PM PDT 24
Peak memory 212180 kb
Host smart-5928a7ce-93b0-498d-af43-d090b32c6f0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193533681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.4193533681
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1054200052
Short name T433
Test name
Test status
Simulation time 2256201087 ps
CPU time 24.5 seconds
Started Jul 13 04:39:43 PM PDT 24
Finished Jul 13 04:40:11 PM PDT 24
Peak memory 218280 kb
Host smart-edec482d-67ce-484f-b317-5f40bfcf313a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054200052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1054200052
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1127242839
Short name T440
Test name
Test status
Simulation time 2808599115 ps
CPU time 160.42 seconds
Started Jul 13 04:39:17 PM PDT 24
Finished Jul 13 04:42:00 PM PDT 24
Peak memory 214980 kb
Host smart-e18cfa2b-4d31-49aa-afc2-79164f4f7ef0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127242839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1127242839
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2012791257
Short name T422
Test name
Test status
Simulation time 5363676667 ps
CPU time 17.14 seconds
Started Jul 13 04:39:26 PM PDT 24
Finished Jul 13 04:39:46 PM PDT 24
Peak memory 210936 kb
Host smart-b97adca7-95d6-4ef7-945a-7100cdf93696
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012791257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2012791257
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3687289158
Short name T442
Test name
Test status
Simulation time 1888023086 ps
CPU time 20.18 seconds
Started Jul 13 04:39:42 PM PDT 24
Finished Jul 13 04:40:06 PM PDT 24
Peak memory 211180 kb
Host smart-092ead58-5a62-4344-9353-1a4aee91384a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687289158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3687289158
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.609894870
Short name T423
Test name
Test status
Simulation time 682489860 ps
CPU time 16.25 seconds
Started Jul 13 04:39:40 PM PDT 24
Finished Jul 13 04:39:59 PM PDT 24
Peak memory 211916 kb
Host smart-5125581b-7b0d-49c3-9abd-8a6e09be19ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609894870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.609894870
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2254919762
Short name T418
Test name
Test status
Simulation time 688226636 ps
CPU time 8.71 seconds
Started Jul 13 04:39:36 PM PDT 24
Finished Jul 13 04:39:46 PM PDT 24
Peak memory 215596 kb
Host smart-8fc103f4-62d5-44b6-8be8-78ae79138fb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254919762 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2254919762
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2984598875
Short name T417
Test name
Test status
Simulation time 8843056772 ps
CPU time 21.38 seconds
Started Jul 13 04:39:22 PM PDT 24
Finished Jul 13 04:39:45 PM PDT 24
Peak memory 212292 kb
Host smart-dfb751a0-b531-49da-8feb-ef4209bba54d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984598875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2984598875
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3235009154
Short name T437
Test name
Test status
Simulation time 1716244500 ps
CPU time 18.22 seconds
Started Jul 13 04:39:27 PM PDT 24
Finished Jul 13 04:39:48 PM PDT 24
Peak memory 210228 kb
Host smart-f2aef0fd-244e-47c4-8b51-3542fc6736ee
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235009154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3235009154
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.739972716
Short name T400
Test name
Test status
Simulation time 1302966385 ps
CPU time 16.45 seconds
Started Jul 13 04:39:30 PM PDT 24
Finished Jul 13 04:39:49 PM PDT 24
Peak memory 210472 kb
Host smart-15ccfadc-0785-4d84-872a-1beb81534c7d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739972716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
739972716
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2104208771
Short name T107
Test name
Test status
Simulation time 2170703712 ps
CPU time 20.75 seconds
Started Jul 13 04:39:40 PM PDT 24
Finished Jul 13 04:40:02 PM PDT 24
Peak memory 212120 kb
Host smart-f0ebb02c-6c06-4c17-bb12-1a9d95090c85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104208771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2104208771
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2007122647
Short name T390
Test name
Test status
Simulation time 17096239906 ps
CPU time 38.34 seconds
Started Jul 13 04:39:26 PM PDT 24
Finished Jul 13 04:40:06 PM PDT 24
Peak memory 218276 kb
Host smart-598934c1-4db1-4fa6-b93b-72a2d2832ec9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007122647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2007122647
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.575538131
Short name T380
Test name
Test status
Simulation time 386053433 ps
CPU time 8.22 seconds
Started Jul 13 04:39:41 PM PDT 24
Finished Jul 13 04:39:53 PM PDT 24
Peak memory 210500 kb
Host smart-1e68a407-ae82-4bf6-987e-4eec54ef5908
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575538131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.575538131
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.286489551
Short name T434
Test name
Test status
Simulation time 5961674664 ps
CPU time 16.32 seconds
Started Jul 13 04:39:23 PM PDT 24
Finished Jul 13 04:39:41 PM PDT 24
Peak memory 210988 kb
Host smart-a5e169e8-ab84-4885-b2bb-c36ea3bcaaa8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286489551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.286489551
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1637511605
Short name T416
Test name
Test status
Simulation time 352020134 ps
CPU time 11.71 seconds
Started Jul 13 04:39:35 PM PDT 24
Finished Jul 13 04:39:47 PM PDT 24
Peak memory 211260 kb
Host smart-d006b01a-3ac2-4b59-b963-809dd00ffa86
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637511605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1637511605
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2657247794
Short name T431
Test name
Test status
Simulation time 9908371020 ps
CPU time 23.68 seconds
Started Jul 13 04:39:43 PM PDT 24
Finished Jul 13 04:40:10 PM PDT 24
Peak memory 217552 kb
Host smart-49945f2e-a0a3-4945-aa7e-4b53ac1d0657
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657247794 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2657247794
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2392942276
Short name T88
Test name
Test status
Simulation time 2221628806 ps
CPU time 21.13 seconds
Started Jul 13 04:39:18 PM PDT 24
Finished Jul 13 04:39:41 PM PDT 24
Peak memory 211432 kb
Host smart-06125aa1-c1f8-4d03-9b32-df9035954917
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392942276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2392942276
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3382343819
Short name T355
Test name
Test status
Simulation time 1263982960 ps
CPU time 14.36 seconds
Started Jul 13 04:39:40 PM PDT 24
Finished Jul 13 04:39:56 PM PDT 24
Peak memory 210460 kb
Host smart-b90397a5-1f60-47eb-8839-e27e7302933b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382343819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3382343819
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.883537589
Short name T399
Test name
Test status
Simulation time 14612476349 ps
CPU time 31.39 seconds
Started Jul 13 04:39:35 PM PDT 24
Finished Jul 13 04:40:07 PM PDT 24
Peak memory 210708 kb
Host smart-ebbb1ca1-cf44-493c-a428-26fc69bcc300
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883537589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
883537589
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3334682240
Short name T445
Test name
Test status
Simulation time 51408742755 ps
CPU time 202.33 seconds
Started Jul 13 04:39:24 PM PDT 24
Finished Jul 13 04:42:48 PM PDT 24
Peak memory 215044 kb
Host smart-1653f19d-7974-4bf8-98fb-ca54565d6f9f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334682240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3334682240
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.34442350
Short name T451
Test name
Test status
Simulation time 6150916545 ps
CPU time 29.53 seconds
Started Jul 13 04:39:25 PM PDT 24
Finished Jul 13 04:39:56 PM PDT 24
Peak memory 212664 kb
Host smart-efe11d91-7fcd-487f-8872-e7bebdda7c99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34442350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_same_csr_outstanding.34442350
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3960892358
Short name T358
Test name
Test status
Simulation time 29990530253 ps
CPU time 26.07 seconds
Started Jul 13 04:39:25 PM PDT 24
Finished Jul 13 04:39:52 PM PDT 24
Peak memory 218760 kb
Host smart-da9c2be0-518d-4147-9c91-38953b72a93a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960892358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3960892358
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1524846533
Short name T391
Test name
Test status
Simulation time 11542014916 ps
CPU time 23.83 seconds
Started Jul 13 04:39:27 PM PDT 24
Finished Jul 13 04:39:54 PM PDT 24
Peak memory 218284 kb
Host smart-20aec70d-e50d-4fe3-8916-de0e1d65d0d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524846533 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1524846533
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.4169979819
Short name T89
Test name
Test status
Simulation time 15937850706 ps
CPU time 31.29 seconds
Started Jul 13 04:39:40 PM PDT 24
Finished Jul 13 04:40:14 PM PDT 24
Peak memory 211984 kb
Host smart-1c7343af-d302-4c42-bb57-f6271d60c6e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169979819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.4169979819
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2614427940
Short name T397
Test name
Test status
Simulation time 20829667822 ps
CPU time 99.6 seconds
Started Jul 13 04:39:39 PM PDT 24
Finished Jul 13 04:41:19 PM PDT 24
Peak memory 213752 kb
Host smart-f94a78b4-9e0a-417a-8f5a-08077fa442fc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614427940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2614427940
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2992219018
Short name T106
Test name
Test status
Simulation time 7866495629 ps
CPU time 21.55 seconds
Started Jul 13 04:39:41 PM PDT 24
Finished Jul 13 04:40:06 PM PDT 24
Peak memory 212616 kb
Host smart-5516c3b2-8263-4e71-acb6-a24a2971dee6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992219018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2992219018
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3394145282
Short name T393
Test name
Test status
Simulation time 11547458440 ps
CPU time 33.22 seconds
Started Jul 13 04:39:21 PM PDT 24
Finished Jul 13 04:39:56 PM PDT 24
Peak memory 218756 kb
Host smart-bf49c7af-8d4c-4c36-a4d1-2a7197207076
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394145282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3394145282
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2745849661
Short name T122
Test name
Test status
Simulation time 10783813650 ps
CPU time 162.05 seconds
Started Jul 13 04:39:42 PM PDT 24
Finished Jul 13 04:42:27 PM PDT 24
Peak memory 213996 kb
Host smart-13783cbe-b306-4bc0-a6dc-f48069377e07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745849661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2745849661
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3097868076
Short name T394
Test name
Test status
Simulation time 9976603479 ps
CPU time 23.22 seconds
Started Jul 13 04:39:28 PM PDT 24
Finished Jul 13 04:39:55 PM PDT 24
Peak memory 217408 kb
Host smart-92e44861-71c6-4e9d-8b48-660e95520451
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097868076 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3097868076
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1652820935
Short name T382
Test name
Test status
Simulation time 8366334949 ps
CPU time 31.61 seconds
Started Jul 13 04:39:29 PM PDT 24
Finished Jul 13 04:40:04 PM PDT 24
Peak memory 212164 kb
Host smart-7223ccdf-fc83-4bec-8e02-b0d5295fb108
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652820935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1652820935
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.97865329
Short name T407
Test name
Test status
Simulation time 676393767 ps
CPU time 16.88 seconds
Started Jul 13 04:39:40 PM PDT 24
Finished Jul 13 04:39:58 PM PDT 24
Peak memory 212476 kb
Host smart-c37e9108-63dc-4be4-bcd2-40f5dff874aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97865329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctr
l_same_csr_outstanding.97865329
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3520607392
Short name T70
Test name
Test status
Simulation time 9448531587 ps
CPU time 25.74 seconds
Started Jul 13 04:39:36 PM PDT 24
Finished Jul 13 04:40:03 PM PDT 24
Peak memory 218776 kb
Host smart-b78fbb9d-cb98-4232-9ed5-7eb43e3bd8a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520607392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3520607392
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.4263940073
Short name T395
Test name
Test status
Simulation time 1347532352 ps
CPU time 155.85 seconds
Started Jul 13 04:39:41 PM PDT 24
Finished Jul 13 04:42:19 PM PDT 24
Peak memory 213856 kb
Host smart-9ad8aeaa-1dac-4f6a-8d5c-e35ac1dfc829
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263940073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.4263940073
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1591485030
Short name T359
Test name
Test status
Simulation time 6472797474 ps
CPU time 13.73 seconds
Started Jul 13 04:39:45 PM PDT 24
Finished Jul 13 04:40:01 PM PDT 24
Peak memory 217604 kb
Host smart-e67c15b3-1371-4586-bd5a-ea55caa490d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591485030 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1591485030
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.490200599
Short name T94
Test name
Test status
Simulation time 17055971645 ps
CPU time 32.46 seconds
Started Jul 13 04:39:20 PM PDT 24
Finished Jul 13 04:39:54 PM PDT 24
Peak memory 212052 kb
Host smart-67cf04ae-efd1-4f33-b3c2-b28c0030dd32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490200599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.490200599
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2889158826
Short name T74
Test name
Test status
Simulation time 781149568 ps
CPU time 38.86 seconds
Started Jul 13 04:39:40 PM PDT 24
Finished Jul 13 04:40:20 PM PDT 24
Peak memory 213652 kb
Host smart-f68271c4-bc02-4184-8d5c-2c37eba342c3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889158826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2889158826
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.282569561
Short name T435
Test name
Test status
Simulation time 8316700395 ps
CPU time 32.36 seconds
Started Jul 13 04:39:38 PM PDT 24
Finished Jul 13 04:40:11 PM PDT 24
Peak memory 212496 kb
Host smart-684a864a-ce6d-4c54-9f90-2b6b7a0aa6e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282569561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.282569561
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1745252450
Short name T356
Test name
Test status
Simulation time 688859871 ps
CPU time 13.06 seconds
Started Jul 13 04:39:25 PM PDT 24
Finished Jul 13 04:39:41 PM PDT 24
Peak memory 217340 kb
Host smart-b8ba8e2b-e47c-42ff-a204-8134f95e426b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745252450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1745252450
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2286541694
Short name T425
Test name
Test status
Simulation time 244886115 ps
CPU time 81.3 seconds
Started Jul 13 04:39:26 PM PDT 24
Finished Jul 13 04:40:50 PM PDT 24
Peak memory 213692 kb
Host smart-3130d24b-87da-44bf-b195-48ebc0baa3dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286541694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2286541694
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1575103061
Short name T361
Test name
Test status
Simulation time 569438733 ps
CPU time 8.75 seconds
Started Jul 13 04:39:28 PM PDT 24
Finished Jul 13 04:39:40 PM PDT 24
Peak memory 214496 kb
Host smart-f0ef56e3-05b2-4cf8-b035-d0bc4aa9032e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575103061 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1575103061
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3397862485
Short name T381
Test name
Test status
Simulation time 2799154558 ps
CPU time 16.11 seconds
Started Jul 13 04:39:26 PM PDT 24
Finished Jul 13 04:39:46 PM PDT 24
Peak memory 210588 kb
Host smart-4c81c75f-45df-4754-b469-c236289450f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397862485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3397862485
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2505459812
Short name T72
Test name
Test status
Simulation time 2761809781 ps
CPU time 39.15 seconds
Started Jul 13 04:39:19 PM PDT 24
Finished Jul 13 04:40:00 PM PDT 24
Peak memory 212652 kb
Host smart-908f0a26-6a68-4acb-8841-ae66a7cb1111
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505459812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2505459812
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.659668427
Short name T432
Test name
Test status
Simulation time 3362927421 ps
CPU time 28.13 seconds
Started Jul 13 04:39:37 PM PDT 24
Finished Jul 13 04:40:06 PM PDT 24
Peak memory 212056 kb
Host smart-a0091c02-a232-4a95-bcf5-e075b3f661b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659668427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.659668427
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.131648167
Short name T387
Test name
Test status
Simulation time 2058331942 ps
CPU time 24.18 seconds
Started Jul 13 04:39:24 PM PDT 24
Finished Jul 13 04:39:49 PM PDT 24
Peak memory 218856 kb
Host smart-06840116-bbcb-4e2d-ace1-b74600d8adbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131648167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.131648167
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3338729870
Short name T379
Test name
Test status
Simulation time 13610043722 ps
CPU time 102.46 seconds
Started Jul 13 04:39:29 PM PDT 24
Finished Jul 13 04:41:15 PM PDT 24
Peak memory 213832 kb
Host smart-2f78d3d5-2c10-4451-a85b-eb9f8af8ca84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338729870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3338729870
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3507517748
Short name T366
Test name
Test status
Simulation time 6930828994 ps
CPU time 18.64 seconds
Started Jul 13 04:39:36 PM PDT 24
Finished Jul 13 04:39:56 PM PDT 24
Peak memory 215552 kb
Host smart-36ceef1a-611b-4e35-ac76-bd7fdae490c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507517748 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3507517748
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2139417170
Short name T398
Test name
Test status
Simulation time 13967501187 ps
CPU time 28.69 seconds
Started Jul 13 04:39:26 PM PDT 24
Finished Jul 13 04:39:58 PM PDT 24
Peak memory 211240 kb
Host smart-d2aa5016-d9c2-4c02-9991-a12ff6a55c03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139417170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2139417170
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3029065615
Short name T90
Test name
Test status
Simulation time 721303766 ps
CPU time 37.94 seconds
Started Jul 13 04:39:26 PM PDT 24
Finished Jul 13 04:40:07 PM PDT 24
Peak memory 213032 kb
Host smart-6cf12345-ceee-4716-8132-144e31a4e112
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029065615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3029065615
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.4270616536
Short name T414
Test name
Test status
Simulation time 167697576 ps
CPU time 8.43 seconds
Started Jul 13 04:39:41 PM PDT 24
Finished Jul 13 04:39:52 PM PDT 24
Peak memory 211404 kb
Host smart-6998c594-5177-4b38-ad4c-6f94c7c2db74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270616536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.4270616536
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2297847720
Short name T443
Test name
Test status
Simulation time 1369636610 ps
CPU time 19.59 seconds
Started Jul 13 04:39:34 PM PDT 24
Finished Jul 13 04:39:55 PM PDT 24
Peak memory 218224 kb
Host smart-6f333e65-81f3-44ab-86f1-27a6c656720d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297847720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2297847720
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1820933845
Short name T426
Test name
Test status
Simulation time 4029648279 ps
CPU time 95.5 seconds
Started Jul 13 04:39:39 PM PDT 24
Finished Jul 13 04:41:16 PM PDT 24
Peak memory 213564 kb
Host smart-26270c8d-741d-4199-873a-f38af5ea10d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820933845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1820933845
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2421696255
Short name T351
Test name
Test status
Simulation time 4469389171 ps
CPU time 35.19 seconds
Started Jul 13 04:43:27 PM PDT 24
Finished Jul 13 04:44:04 PM PDT 24
Peak memory 217516 kb
Host smart-5b48c12b-cb78-4c92-a208-130cc7c24c3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421696255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2421696255
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3698655297
Short name T97
Test name
Test status
Simulation time 15107679994 ps
CPU time 169 seconds
Started Jul 13 04:43:26 PM PDT 24
Finished Jul 13 04:46:17 PM PDT 24
Peak memory 239056 kb
Host smart-daf7a91d-57ca-40b1-97cd-17d432d7a235
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698655297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3698655297
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1438013567
Short name T200
Test name
Test status
Simulation time 77760204895 ps
CPU time 55.08 seconds
Started Jul 13 04:43:27 PM PDT 24
Finished Jul 13 04:44:24 PM PDT 24
Peak memory 219272 kb
Host smart-bd6af0f6-f44c-4d44-b3c4-0e145e030644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438013567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1438013567
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3050451827
Short name T26
Test name
Test status
Simulation time 1411951854 ps
CPU time 125.53 seconds
Started Jul 13 04:43:27 PM PDT 24
Finished Jul 13 04:45:35 PM PDT 24
Peak memory 237204 kb
Host smart-5bfe0952-ccaa-417a-99e6-6ea8d7be9084
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050451827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3050451827
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1085586012
Short name T35
Test name
Test status
Simulation time 1549633207 ps
CPU time 20.05 seconds
Started Jul 13 04:43:26 PM PDT 24
Finished Jul 13 04:43:47 PM PDT 24
Peak memory 216472 kb
Host smart-85289467-9119-407b-b8db-b02972774e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085586012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1085586012
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1200574775
Short name T136
Test name
Test status
Simulation time 60205274102 ps
CPU time 181.78 seconds
Started Jul 13 04:43:32 PM PDT 24
Finished Jul 13 04:46:35 PM PDT 24
Peak memory 227516 kb
Host smart-01500416-88c2-4694-9174-333ff6dc89ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200574775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1200574775
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.73887486
Short name T42
Test name
Test status
Simulation time 9132882388 ps
CPU time 236.31 seconds
Started Jul 13 04:43:27 PM PDT 24
Finished Jul 13 04:47:26 PM PDT 24
Peak memory 237420 kb
Host smart-4ecece51-218d-4bbe-bc54-0859cc95a468
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73887486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_cor
rupt_sig_fatal_chk.73887486
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3898204918
Short name T211
Test name
Test status
Simulation time 629117059 ps
CPU time 22.59 seconds
Started Jul 13 04:43:31 PM PDT 24
Finished Jul 13 04:43:55 PM PDT 24
Peak memory 219216 kb
Host smart-76e0903f-be2d-42eb-8f00-f86c741614ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898204918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3898204918
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3120558265
Short name T180
Test name
Test status
Simulation time 697189978 ps
CPU time 10.66 seconds
Started Jul 13 04:43:27 PM PDT 24
Finished Jul 13 04:43:41 PM PDT 24
Peak memory 219204 kb
Host smart-0eae3176-bc6c-4032-be54-0e5ff63ac1f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3120558265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3120558265
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.891099045
Short name T87
Test name
Test status
Simulation time 32238320657 ps
CPU time 77.17 seconds
Started Jul 13 04:43:26 PM PDT 24
Finished Jul 13 04:44:44 PM PDT 24
Peak memory 216080 kb
Host smart-e56b3568-7400-4d69-b02a-ab1af9330fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891099045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.891099045
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.389607825
Short name T198
Test name
Test status
Simulation time 28677305685 ps
CPU time 86.53 seconds
Started Jul 13 04:43:29 PM PDT 24
Finished Jul 13 04:44:58 PM PDT 24
Peak memory 220092 kb
Host smart-1526e26e-51e2-4337-9397-c80a34cf70dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389607825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.389607825
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3307147686
Short name T244
Test name
Test status
Simulation time 3667787953 ps
CPU time 30.58 seconds
Started Jul 13 04:43:41 PM PDT 24
Finished Jul 13 04:44:12 PM PDT 24
Peak memory 217080 kb
Host smart-2f437d67-84bd-4694-84f0-dc4e81e421ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307147686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3307147686
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.577040601
Short name T43
Test name
Test status
Simulation time 143096190895 ps
CPU time 637.92 seconds
Started Jul 13 04:43:35 PM PDT 24
Finished Jul 13 04:54:14 PM PDT 24
Peak memory 224304 kb
Host smart-2fde1cf4-6a24-4619-9336-e733aeb66fb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577040601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.577040601
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3548175058
Short name T294
Test name
Test status
Simulation time 3597188247 ps
CPU time 41.91 seconds
Started Jul 13 04:43:37 PM PDT 24
Finished Jul 13 04:44:20 PM PDT 24
Peak memory 219316 kb
Host smart-0bbc70e5-e10c-4556-bdcb-d7be3367e0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548175058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3548175058
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.367869960
Short name T21
Test name
Test status
Simulation time 763690848 ps
CPU time 10.72 seconds
Started Jul 13 04:43:36 PM PDT 24
Finished Jul 13 04:43:47 PM PDT 24
Peak memory 219268 kb
Host smart-32a72c19-e824-4f6b-a170-a69cb6f70d71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=367869960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.367869960
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3846488890
Short name T32
Test name
Test status
Simulation time 2656767129 ps
CPU time 20.94 seconds
Started Jul 13 04:43:38 PM PDT 24
Finished Jul 13 04:44:00 PM PDT 24
Peak memory 216536 kb
Host smart-6ae19b3e-86fe-4dad-8a12-9f0552c09c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846488890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3846488890
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1413168979
Short name T85
Test name
Test status
Simulation time 16931078499 ps
CPU time 110.55 seconds
Started Jul 13 04:43:34 PM PDT 24
Finished Jul 13 04:45:26 PM PDT 24
Peak memory 231616 kb
Host smart-29af7dd9-3f27-44d1-a478-625858978e2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413168979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1413168979
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3840038370
Short name T69
Test name
Test status
Simulation time 750649520 ps
CPU time 8.65 seconds
Started Jul 13 04:43:39 PM PDT 24
Finished Jul 13 04:43:49 PM PDT 24
Peak memory 217100 kb
Host smart-1cf0a124-4dd3-4711-81ca-eda9b4d6d884
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840038370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3840038370
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.338619347
Short name T307
Test name
Test status
Simulation time 78571007143 ps
CPU time 435.77 seconds
Started Jul 13 04:43:38 PM PDT 24
Finished Jul 13 04:50:54 PM PDT 24
Peak memory 234464 kb
Host smart-9ec919b2-7cab-4519-bef3-94f67927b484
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338619347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.338619347
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1413328090
Short name T251
Test name
Test status
Simulation time 3876962902 ps
CPU time 41.79 seconds
Started Jul 13 04:43:35 PM PDT 24
Finished Jul 13 04:44:17 PM PDT 24
Peak memory 218620 kb
Host smart-84d89a39-1af0-4d09-bf4c-36eb536cfc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413328090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1413328090
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1669429797
Short name T174
Test name
Test status
Simulation time 971010656 ps
CPU time 10.61 seconds
Started Jul 13 04:43:38 PM PDT 24
Finished Jul 13 04:43:50 PM PDT 24
Peak memory 219260 kb
Host smart-3101094f-b900-4c03-aa4b-ff1e5044580d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1669429797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1669429797
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.613999691
Short name T181
Test name
Test status
Simulation time 1959587551 ps
CPU time 23.3 seconds
Started Jul 13 04:43:38 PM PDT 24
Finished Jul 13 04:44:02 PM PDT 24
Peak memory 216072 kb
Host smart-225e640b-41c6-4c0a-b322-91a3b1d2cbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613999691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.613999691
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.280764904
Short name T324
Test name
Test status
Simulation time 19581723433 ps
CPU time 130.93 seconds
Started Jul 13 04:43:39 PM PDT 24
Finished Jul 13 04:45:51 PM PDT 24
Peak memory 222080 kb
Host smart-0f9de25d-167a-4321-b7a3-a3a2992d0b86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280764904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.280764904
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3289532190
Short name T104
Test name
Test status
Simulation time 751621936 ps
CPU time 8.37 seconds
Started Jul 13 04:43:34 PM PDT 24
Finished Jul 13 04:43:43 PM PDT 24
Peak memory 217116 kb
Host smart-629ceab5-229f-4937-a14a-9e92612f64e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289532190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3289532190
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3061694293
Short name T62
Test name
Test status
Simulation time 50040939287 ps
CPU time 522.97 seconds
Started Jul 13 04:43:41 PM PDT 24
Finished Jul 13 04:52:24 PM PDT 24
Peak memory 236168 kb
Host smart-aa48b7f1-b278-4e29-b09d-9108c8a8f8a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061694293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3061694293
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2125142208
Short name T184
Test name
Test status
Simulation time 25246378424 ps
CPU time 65.02 seconds
Started Jul 13 04:43:34 PM PDT 24
Finished Jul 13 04:44:39 PM PDT 24
Peak memory 219220 kb
Host smart-0183dbad-f4a1-4339-b0d9-694aeedac7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125142208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2125142208
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1917330185
Short name T297
Test name
Test status
Simulation time 177912341 ps
CPU time 10.6 seconds
Started Jul 13 04:43:34 PM PDT 24
Finished Jul 13 04:43:46 PM PDT 24
Peak memory 219216 kb
Host smart-916b8626-043e-4bc6-ae50-9d048318af6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1917330185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1917330185
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.692863797
Short name T305
Test name
Test status
Simulation time 28919304239 ps
CPU time 62.61 seconds
Started Jul 13 04:43:41 PM PDT 24
Finished Jul 13 04:44:44 PM PDT 24
Peak memory 217156 kb
Host smart-233b5080-b3a9-4280-8c8a-0a7a4a1078e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692863797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.692863797
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.661082858
Short name T17
Test name
Test status
Simulation time 7162449091 ps
CPU time 29.88 seconds
Started Jul 13 04:43:37 PM PDT 24
Finished Jul 13 04:44:07 PM PDT 24
Peak memory 219320 kb
Host smart-47b69024-93f2-4c98-beb7-12b52b3742c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661082858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.661082858
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2841449640
Short name T266
Test name
Test status
Simulation time 3428176213 ps
CPU time 14.34 seconds
Started Jul 13 04:43:33 PM PDT 24
Finished Jul 13 04:43:48 PM PDT 24
Peak memory 217148 kb
Host smart-aae9b28a-d32a-4a17-be76-423800220e8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841449640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2841449640
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.463713754
Short name T354
Test name
Test status
Simulation time 49898356107 ps
CPU time 223.54 seconds
Started Jul 13 04:43:38 PM PDT 24
Finished Jul 13 04:47:22 PM PDT 24
Peak memory 235040 kb
Host smart-2637cc28-768c-4b19-b6c1-9efbf5a5aeeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463713754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_c
orrupt_sig_fatal_chk.463713754
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2231641528
Short name T293
Test name
Test status
Simulation time 25362978854 ps
CPU time 53.93 seconds
Started Jul 13 04:43:38 PM PDT 24
Finished Jul 13 04:44:32 PM PDT 24
Peak memory 220632 kb
Host smart-6af6d883-0176-44f9-965c-a9c133bc04be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231641528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2231641528
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3450076480
Short name T270
Test name
Test status
Simulation time 1420991789 ps
CPU time 13.19 seconds
Started Jul 13 04:43:38 PM PDT 24
Finished Jul 13 04:43:52 PM PDT 24
Peak memory 218824 kb
Host smart-8df0d874-026c-43fe-a72c-0c13ee7272a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3450076480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3450076480
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1381636358
Short name T171
Test name
Test status
Simulation time 2362911781 ps
CPU time 30.86 seconds
Started Jul 13 04:43:34 PM PDT 24
Finished Jul 13 04:44:05 PM PDT 24
Peak memory 216748 kb
Host smart-5949ce32-7419-4851-8f45-823037203d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381636358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1381636358
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2916828949
Short name T218
Test name
Test status
Simulation time 43957241519 ps
CPU time 128.42 seconds
Started Jul 13 04:43:39 PM PDT 24
Finished Jul 13 04:45:48 PM PDT 24
Peak memory 219304 kb
Host smart-a2f84056-b3fc-4ecd-8e2e-948907572d2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916828949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2916828949
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2063697140
Short name T248
Test name
Test status
Simulation time 9840155496 ps
CPU time 23.22 seconds
Started Jul 13 04:43:43 PM PDT 24
Finished Jul 13 04:44:07 PM PDT 24
Peak memory 217420 kb
Host smart-0220eb5d-009c-4e84-8843-0808d969c567
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063697140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2063697140
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.359617634
Short name T222
Test name
Test status
Simulation time 95967586838 ps
CPU time 920.44 seconds
Started Jul 13 04:43:35 PM PDT 24
Finished Jul 13 04:58:57 PM PDT 24
Peak memory 219448 kb
Host smart-c7600267-e345-4607-8960-1d6727a24b4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359617634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.359617634
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3160378179
Short name T272
Test name
Test status
Simulation time 7744352952 ps
CPU time 64.27 seconds
Started Jul 13 04:43:46 PM PDT 24
Finished Jul 13 04:44:51 PM PDT 24
Peak memory 219132 kb
Host smart-0466a26f-1ecf-41fa-a1d8-173f3bc7c183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160378179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3160378179
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1115840827
Short name T243
Test name
Test status
Simulation time 12768929571 ps
CPU time 33.24 seconds
Started Jul 13 04:43:35 PM PDT 24
Finished Jul 13 04:44:09 PM PDT 24
Peak memory 211980 kb
Host smart-e3b4ec77-c7e3-4034-8052-98e2076be25c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1115840827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1115840827
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.895918676
Short name T299
Test name
Test status
Simulation time 358255913 ps
CPU time 21.31 seconds
Started Jul 13 04:43:40 PM PDT 24
Finished Jul 13 04:44:02 PM PDT 24
Peak memory 216700 kb
Host smart-552afdf6-947b-4e01-b269-4cf512a4df17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895918676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.895918676
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2888491325
Short name T150
Test name
Test status
Simulation time 17294016908 ps
CPU time 81.39 seconds
Started Jul 13 04:43:38 PM PDT 24
Finished Jul 13 04:45:01 PM PDT 24
Peak memory 219304 kb
Host smart-47e68098-4184-4de3-b3e0-b981f583c0e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888491325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2888491325
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1607708286
Short name T191
Test name
Test status
Simulation time 1614592610 ps
CPU time 18.54 seconds
Started Jul 13 04:43:45 PM PDT 24
Finished Jul 13 04:44:05 PM PDT 24
Peak memory 217120 kb
Host smart-05e68986-8f17-4f24-97f2-4b7e7d3b3ae8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607708286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1607708286
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3362035065
Short name T56
Test name
Test status
Simulation time 9410378043 ps
CPU time 46.78 seconds
Started Jul 13 04:43:42 PM PDT 24
Finished Jul 13 04:44:29 PM PDT 24
Peak memory 219212 kb
Host smart-810c086a-bbed-4548-9c67-86d3c02ecbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362035065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3362035065
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2095007309
Short name T301
Test name
Test status
Simulation time 15501490594 ps
CPU time 32.99 seconds
Started Jul 13 04:43:42 PM PDT 24
Finished Jul 13 04:44:15 PM PDT 24
Peak memory 211680 kb
Host smart-901ce62f-9c2a-45f3-b173-faeec27f29dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2095007309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2095007309
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.2517517491
Short name T286
Test name
Test status
Simulation time 22511081046 ps
CPU time 39.55 seconds
Started Jul 13 04:44:41 PM PDT 24
Finished Jul 13 04:45:22 PM PDT 24
Peak memory 215332 kb
Host smart-51144ad9-0d38-463f-8377-185230e6f813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517517491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2517517491
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.444821578
Short name T292
Test name
Test status
Simulation time 3451480728 ps
CPU time 29.59 seconds
Started Jul 13 04:43:45 PM PDT 24
Finished Jul 13 04:44:16 PM PDT 24
Peak memory 216840 kb
Host smart-8f2eee35-8e4d-4ac2-820a-a3fd070d7744
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444821578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.444821578
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.4152869576
Short name T346
Test name
Test status
Simulation time 4523561647 ps
CPU time 25.67 seconds
Started Jul 13 04:43:44 PM PDT 24
Finished Jul 13 04:44:11 PM PDT 24
Peak memory 216928 kb
Host smart-dbfd2259-5a50-448b-81f5-cd4b07e4291b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152869576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.4152869576
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2194623310
Short name T20
Test name
Test status
Simulation time 159960133365 ps
CPU time 297.31 seconds
Started Jul 13 04:43:45 PM PDT 24
Finished Jul 13 04:48:44 PM PDT 24
Peak memory 233620 kb
Host smart-57a406dd-c2c8-45c0-883b-c2cd94cd30a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194623310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2194623310
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1048343963
Short name T196
Test name
Test status
Simulation time 5635152343 ps
CPU time 52.18 seconds
Started Jul 13 04:43:42 PM PDT 24
Finished Jul 13 04:44:35 PM PDT 24
Peak memory 219272 kb
Host smart-44d9a936-cd22-4b47-9e69-8641fddb571b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048343963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1048343963
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1470135283
Short name T230
Test name
Test status
Simulation time 1685300651 ps
CPU time 18.64 seconds
Started Jul 13 04:43:44 PM PDT 24
Finished Jul 13 04:44:04 PM PDT 24
Peak memory 211480 kb
Host smart-08c24575-6cba-48f5-b5f9-664467968bcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1470135283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1470135283
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3822605212
Short name T348
Test name
Test status
Simulation time 722522390 ps
CPU time 19.6 seconds
Started Jul 13 04:43:49 PM PDT 24
Finished Jul 13 04:44:09 PM PDT 24
Peak memory 216508 kb
Host smart-cda6abcc-78b5-46d6-9d02-d30e08a0d61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822605212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3822605212
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1163467647
Short name T318
Test name
Test status
Simulation time 1154584124 ps
CPU time 31.66 seconds
Started Jul 13 04:43:49 PM PDT 24
Finished Jul 13 04:44:21 PM PDT 24
Peak memory 219268 kb
Host smart-c7259ea8-5b96-4989-90db-2d3708970aad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163467647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1163467647
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.597246218
Short name T153
Test name
Test status
Simulation time 58008290977 ps
CPU time 30.55 seconds
Started Jul 13 04:43:46 PM PDT 24
Finished Jul 13 04:44:17 PM PDT 24
Peak memory 217504 kb
Host smart-b3a15570-bed9-4721-8c46-763258e5afca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597246218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.597246218
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.188186737
Short name T259
Test name
Test status
Simulation time 53635581006 ps
CPU time 588.99 seconds
Started Jul 13 04:43:45 PM PDT 24
Finished Jul 13 04:53:35 PM PDT 24
Peak memory 233860 kb
Host smart-cbdef4ba-a69b-4f45-8d2b-a674e7e46191
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188186737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.188186737
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1621535784
Short name T221
Test name
Test status
Simulation time 6399530820 ps
CPU time 56.26 seconds
Started Jul 13 04:43:41 PM PDT 24
Finished Jul 13 04:44:38 PM PDT 24
Peak memory 219364 kb
Host smart-e58f5595-d252-4473-907c-6eb519872a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621535784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1621535784
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.960949327
Short name T325
Test name
Test status
Simulation time 4315149195 ps
CPU time 22.42 seconds
Started Jul 13 04:43:42 PM PDT 24
Finished Jul 13 04:44:05 PM PDT 24
Peak memory 219300 kb
Host smart-95faa6ec-598a-4b57-a3c2-c973a8215089
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=960949327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.960949327
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.939802430
Short name T343
Test name
Test status
Simulation time 68665667834 ps
CPU time 46.77 seconds
Started Jul 13 04:43:45 PM PDT 24
Finished Jul 13 04:44:32 PM PDT 24
Peak memory 216644 kb
Host smart-935667d6-8c6a-4712-be49-27656eb1452c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939802430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.939802430
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3155384569
Short name T84
Test name
Test status
Simulation time 18233553622 ps
CPU time 78.02 seconds
Started Jul 13 04:43:45 PM PDT 24
Finished Jul 13 04:45:04 PM PDT 24
Peak memory 218452 kb
Host smart-5466e22a-3223-4580-8441-e283da2c1bc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155384569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3155384569
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1427186173
Short name T333
Test name
Test status
Simulation time 2163031553 ps
CPU time 21.39 seconds
Started Jul 13 04:43:42 PM PDT 24
Finished Jul 13 04:44:04 PM PDT 24
Peak memory 216920 kb
Host smart-1eeda34a-7ea6-4ddc-b45d-8ff45b3edbb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427186173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1427186173
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2901787473
Short name T227
Test name
Test status
Simulation time 126613944460 ps
CPU time 593.22 seconds
Started Jul 13 04:43:40 PM PDT 24
Finished Jul 13 04:53:33 PM PDT 24
Peak memory 235816 kb
Host smart-c186d019-5c4f-46fe-8753-0d7d0f05c9e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901787473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2901787473
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3369198469
Short name T28
Test name
Test status
Simulation time 14046026020 ps
CPU time 43.99 seconds
Started Jul 13 04:43:43 PM PDT 24
Finished Jul 13 04:44:28 PM PDT 24
Peak memory 219296 kb
Host smart-503555c5-102a-411b-9fe3-98413afff7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369198469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3369198469
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3692713793
Short name T186
Test name
Test status
Simulation time 1871002356 ps
CPU time 21.46 seconds
Started Jul 13 04:43:42 PM PDT 24
Finished Jul 13 04:44:05 PM PDT 24
Peak memory 211340 kb
Host smart-f4fd274c-6c80-4877-a2ba-75d18749d4d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3692713793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3692713793
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2078609010
Short name T130
Test name
Test status
Simulation time 346640894 ps
CPU time 20.2 seconds
Started Jul 13 04:43:43 PM PDT 24
Finished Jul 13 04:44:04 PM PDT 24
Peak memory 215980 kb
Host smart-f38a9faf-2ee5-4959-bc85-bfc2afa792c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078609010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2078609010
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3600690122
Short name T306
Test name
Test status
Simulation time 83701699744 ps
CPU time 174.67 seconds
Started Jul 13 04:43:45 PM PDT 24
Finished Jul 13 04:46:40 PM PDT 24
Peak memory 227584 kb
Host smart-90c8c7e8-4d64-4e98-9fe3-140356ff079c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600690122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3600690122
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2213838737
Short name T328
Test name
Test status
Simulation time 2045055458 ps
CPU time 21.34 seconds
Started Jul 13 04:43:48 PM PDT 24
Finished Jul 13 04:44:09 PM PDT 24
Peak memory 217080 kb
Host smart-a5b6ab25-3040-4292-8390-c71282d7f3a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213838737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2213838737
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2591253721
Short name T103
Test name
Test status
Simulation time 8177020384 ps
CPU time 67.13 seconds
Started Jul 13 04:43:42 PM PDT 24
Finished Jul 13 04:44:50 PM PDT 24
Peak memory 219100 kb
Host smart-e5a1157a-de04-4621-a907-905fdd38dbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591253721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2591253721
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2033511241
Short name T148
Test name
Test status
Simulation time 3461288128 ps
CPU time 32.13 seconds
Started Jul 13 04:43:43 PM PDT 24
Finished Jul 13 04:44:16 PM PDT 24
Peak memory 217492 kb
Host smart-76f35196-446b-42bd-b5a1-10242585cc46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033511241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2033511241
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1672791456
Short name T188
Test name
Test status
Simulation time 1026724049 ps
CPU time 11.59 seconds
Started Jul 13 04:44:49 PM PDT 24
Finished Jul 13 04:45:02 PM PDT 24
Peak memory 213184 kb
Host smart-378285fe-b957-4da9-952a-061041161f0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672791456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1672791456
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1068399112
Short name T334
Test name
Test status
Simulation time 2178283415 ps
CPU time 154.44 seconds
Started Jul 13 04:43:28 PM PDT 24
Finished Jul 13 04:46:05 PM PDT 24
Peak memory 240620 kb
Host smart-16d906fc-610b-4c8a-a43b-46f27974c53c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068399112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1068399112
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2959288795
Short name T290
Test name
Test status
Simulation time 1319986910 ps
CPU time 19.21 seconds
Started Jul 13 04:43:29 PM PDT 24
Finished Jul 13 04:43:50 PM PDT 24
Peak memory 219216 kb
Host smart-25ff6d3c-841a-4bfe-b2c7-22ccc1f606d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959288795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2959288795
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1109836067
Short name T254
Test name
Test status
Simulation time 1349306101 ps
CPU time 12.59 seconds
Started Jul 13 04:43:27 PM PDT 24
Finished Jul 13 04:43:43 PM PDT 24
Peak memory 218740 kb
Host smart-8050ae12-55a9-484f-89f8-5681c9e1ba29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1109836067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1109836067
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2292882734
Short name T27
Test name
Test status
Simulation time 2812733921 ps
CPU time 243.29 seconds
Started Jul 13 04:43:26 PM PDT 24
Finished Jul 13 04:47:31 PM PDT 24
Peak memory 238068 kb
Host smart-1fdab032-6b93-490d-a588-2366a51fcb71
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292882734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2292882734
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1015908805
Short name T226
Test name
Test status
Simulation time 6327595948 ps
CPU time 67.52 seconds
Started Jul 13 04:43:29 PM PDT 24
Finished Jul 13 04:44:39 PM PDT 24
Peak memory 216988 kb
Host smart-7bc691b9-3274-46d6-be64-8083ce427e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015908805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1015908805
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3872540641
Short name T289
Test name
Test status
Simulation time 8273388744 ps
CPU time 50.6 seconds
Started Jul 13 04:44:49 PM PDT 24
Finished Jul 13 04:45:41 PM PDT 24
Peak memory 219332 kb
Host smart-34103598-9176-4528-877e-eacbc5d1c02c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872540641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3872540641
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1135948923
Short name T352
Test name
Test status
Simulation time 5960974935 ps
CPU time 31.09 seconds
Started Jul 13 04:43:48 PM PDT 24
Finished Jul 13 04:44:20 PM PDT 24
Peak memory 217404 kb
Host smart-bd6e27f5-2b8b-494e-93e9-a07c82240c39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135948923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1135948923
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2249242585
Short name T23
Test name
Test status
Simulation time 90343704165 ps
CPU time 966.32 seconds
Started Jul 13 04:43:45 PM PDT 24
Finished Jul 13 04:59:52 PM PDT 24
Peak memory 225916 kb
Host smart-999662e7-414b-441a-bbc4-e3799af845cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249242585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2249242585
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2925846827
Short name T60
Test name
Test status
Simulation time 5048229035 ps
CPU time 49.09 seconds
Started Jul 13 04:43:46 PM PDT 24
Finished Jul 13 04:44:36 PM PDT 24
Peak memory 219324 kb
Host smart-c959b6fa-2222-495a-85f8-753ef7a3927b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925846827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2925846827
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3127676702
Short name T229
Test name
Test status
Simulation time 1998018890 ps
CPU time 22.75 seconds
Started Jul 13 04:43:49 PM PDT 24
Finished Jul 13 04:44:12 PM PDT 24
Peak memory 219220 kb
Host smart-6c368130-23d7-4533-b156-cb2376a69aab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3127676702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3127676702
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.286378021
Short name T2
Test name
Test status
Simulation time 369084704 ps
CPU time 20.05 seconds
Started Jul 13 04:43:44 PM PDT 24
Finished Jul 13 04:44:05 PM PDT 24
Peak memory 216412 kb
Host smart-24360054-fe17-4e5d-82ff-1b30d73981bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286378021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.286378021
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.1367102791
Short name T224
Test name
Test status
Simulation time 17015452053 ps
CPU time 42.06 seconds
Started Jul 13 04:43:45 PM PDT 24
Finished Jul 13 04:44:28 PM PDT 24
Peak memory 217104 kb
Host smart-1bd7e672-cb1f-40f7-bb3d-84172c0ecac7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367102791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.1367102791
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.769273735
Short name T155
Test name
Test status
Simulation time 13248898017 ps
CPU time 28.92 seconds
Started Jul 13 04:43:44 PM PDT 24
Finished Jul 13 04:44:14 PM PDT 24
Peak memory 217500 kb
Host smart-bc8f2ba5-365f-4c76-822a-0543fc85384b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769273735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.769273735
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.479327105
Short name T41
Test name
Test status
Simulation time 261393654200 ps
CPU time 538.71 seconds
Started Jul 13 04:44:41 PM PDT 24
Finished Jul 13 04:53:41 PM PDT 24
Peak memory 215084 kb
Host smart-d64fceb1-a439-4d22-83de-34c081e2f755
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479327105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.479327105
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.46454955
Short name T332
Test name
Test status
Simulation time 5232047766 ps
CPU time 49.61 seconds
Started Jul 13 04:43:49 PM PDT 24
Finished Jul 13 04:44:39 PM PDT 24
Peak memory 219300 kb
Host smart-cb6d4cb7-f555-4981-9ee1-64682dbcab26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46454955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.46454955
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.909530995
Short name T199
Test name
Test status
Simulation time 16195126369 ps
CPU time 32.65 seconds
Started Jul 13 04:43:42 PM PDT 24
Finished Jul 13 04:44:16 PM PDT 24
Peak memory 219348 kb
Host smart-f8561dfd-71b1-4d23-9e34-0f18719c0d3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=909530995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.909530995
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3363935965
Short name T177
Test name
Test status
Simulation time 46224791213 ps
CPU time 63.09 seconds
Started Jul 13 04:43:45 PM PDT 24
Finished Jul 13 04:44:49 PM PDT 24
Peak memory 217264 kb
Host smart-5d08f96c-0b99-46d2-9216-688d6415927a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363935965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3363935965
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.425753457
Short name T323
Test name
Test status
Simulation time 3744553549 ps
CPU time 47.32 seconds
Started Jul 13 04:44:41 PM PDT 24
Finished Jul 13 04:45:30 PM PDT 24
Peak memory 216676 kb
Host smart-d1925829-c3b0-4b05-91b9-c5bb5526957f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425753457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.425753457
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1133847378
Short name T159
Test name
Test status
Simulation time 176122941 ps
CPU time 8.1 seconds
Started Jul 13 04:43:49 PM PDT 24
Finished Jul 13 04:43:58 PM PDT 24
Peak memory 218080 kb
Host smart-59514f8c-690d-4664-ac28-b65ef356b440
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133847378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1133847378
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1661121916
Short name T250
Test name
Test status
Simulation time 61508805359 ps
CPU time 246.9 seconds
Started Jul 13 04:43:44 PM PDT 24
Finished Jul 13 04:47:52 PM PDT 24
Peak memory 218060 kb
Host smart-28c81747-8230-4def-b4bf-4dc33df9f144
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661121916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1661121916
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3670276346
Short name T178
Test name
Test status
Simulation time 4790114509 ps
CPU time 43.07 seconds
Started Jul 13 04:43:46 PM PDT 24
Finished Jul 13 04:44:30 PM PDT 24
Peak memory 219320 kb
Host smart-47894e28-bf9f-4c77-b134-270d1a68a445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670276346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3670276346
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2739899976
Short name T233
Test name
Test status
Simulation time 7187940413 ps
CPU time 30.04 seconds
Started Jul 13 04:43:45 PM PDT 24
Finished Jul 13 04:44:16 PM PDT 24
Peak memory 217804 kb
Host smart-f88127e5-3ca2-48b8-8845-cbba97bf00a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2739899976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2739899976
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.551851384
Short name T341
Test name
Test status
Simulation time 1527085591 ps
CPU time 19.92 seconds
Started Jul 13 04:43:43 PM PDT 24
Finished Jul 13 04:44:04 PM PDT 24
Peak memory 217372 kb
Host smart-54b886b6-02ca-487e-a614-17eecf0a4f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551851384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.551851384
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.269296701
Short name T255
Test name
Test status
Simulation time 6721580535 ps
CPU time 66.18 seconds
Started Jul 13 04:43:49 PM PDT 24
Finished Jul 13 04:44:55 PM PDT 24
Peak memory 220960 kb
Host smart-872f4e7c-f534-4db9-9101-eaaf239b0eb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269296701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.269296701
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2395200149
Short name T144
Test name
Test status
Simulation time 2076621878 ps
CPU time 21.06 seconds
Started Jul 13 04:43:51 PM PDT 24
Finished Jul 13 04:44:12 PM PDT 24
Peak memory 217044 kb
Host smart-1c860227-ddce-484c-b06e-301e6c6dbcc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395200149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2395200149
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2272415980
Short name T151
Test name
Test status
Simulation time 2192725550 ps
CPU time 175.07 seconds
Started Jul 13 04:43:52 PM PDT 24
Finished Jul 13 04:46:47 PM PDT 24
Peak memory 228492 kb
Host smart-3066969a-f78f-4478-ad68-67514b66cd08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272415980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2272415980
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3111654586
Short name T228
Test name
Test status
Simulation time 21891931865 ps
CPU time 32.9 seconds
Started Jul 13 04:43:51 PM PDT 24
Finished Jul 13 04:44:24 PM PDT 24
Peak memory 219340 kb
Host smart-ef30fd37-bbde-434f-8792-958cda7e03ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3111654586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3111654586
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3927066908
Short name T183
Test name
Test status
Simulation time 1408218964 ps
CPU time 20.32 seconds
Started Jul 13 04:43:49 PM PDT 24
Finished Jul 13 04:44:10 PM PDT 24
Peak memory 216832 kb
Host smart-42f19af0-99e1-4c8d-b144-5dc39187634b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927066908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3927066908
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2513491756
Short name T282
Test name
Test status
Simulation time 86567205837 ps
CPU time 260.82 seconds
Started Jul 13 04:43:48 PM PDT 24
Finished Jul 13 04:48:10 PM PDT 24
Peak memory 221064 kb
Host smart-4171f259-52e5-4caa-94ff-ebddeffc7aa7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513491756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2513491756
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.212664237
Short name T15
Test name
Test status
Simulation time 41397359957 ps
CPU time 9301.33 seconds
Started Jul 13 04:43:53 PM PDT 24
Finished Jul 13 07:18:55 PM PDT 24
Peak memory 231724 kb
Host smart-5477c3c0-9514-4c4c-bb8a-97e822922383
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212664237 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.212664237
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2437008469
Short name T225
Test name
Test status
Simulation time 8824562574 ps
CPU time 21.02 seconds
Started Jul 13 04:43:50 PM PDT 24
Finished Jul 13 04:44:11 PM PDT 24
Peak memory 217400 kb
Host smart-e5f00721-4283-46a7-b114-3a7c80607634
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437008469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2437008469
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3220509885
Short name T44
Test name
Test status
Simulation time 136221770190 ps
CPU time 483.03 seconds
Started Jul 13 04:43:52 PM PDT 24
Finished Jul 13 04:51:55 PM PDT 24
Peak memory 225556 kb
Host smart-79ca7c67-4546-4307-a849-a25cfd076b9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220509885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3220509885
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2065471657
Short name T278
Test name
Test status
Simulation time 7561308583 ps
CPU time 26.44 seconds
Started Jul 13 04:43:53 PM PDT 24
Finished Jul 13 04:44:20 PM PDT 24
Peak memory 219316 kb
Host smart-07845f92-ef34-4f3e-a0b3-1fa7ce0b9fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065471657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2065471657
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.741169492
Short name T280
Test name
Test status
Simulation time 9527013231 ps
CPU time 14.79 seconds
Started Jul 13 04:43:54 PM PDT 24
Finished Jul 13 04:44:09 PM PDT 24
Peak memory 219164 kb
Host smart-c70c840b-145b-4996-a6f6-c0d827a94411
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=741169492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.741169492
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1793195903
Short name T102
Test name
Test status
Simulation time 5143957292 ps
CPU time 48.91 seconds
Started Jul 13 04:43:51 PM PDT 24
Finished Jul 13 04:44:41 PM PDT 24
Peak memory 216516 kb
Host smart-13b276e3-fb6d-4fbf-a4e7-31dddf55e1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793195903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1793195903
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3131799164
Short name T146
Test name
Test status
Simulation time 7487961732 ps
CPU time 74.52 seconds
Started Jul 13 04:43:58 PM PDT 24
Finished Jul 13 04:45:13 PM PDT 24
Peak memory 219284 kb
Host smart-b09fb297-a652-4f20-9e6b-d94bcb2af01f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131799164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3131799164
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3408203195
Short name T212
Test name
Test status
Simulation time 1007970736 ps
CPU time 14.44 seconds
Started Jul 13 04:43:54 PM PDT 24
Finished Jul 13 04:44:09 PM PDT 24
Peak memory 216996 kb
Host smart-0ebc578b-e3ba-4167-952a-8eff5bc79119
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408203195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3408203195
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1929973557
Short name T55
Test name
Test status
Simulation time 248370359767 ps
CPU time 798.06 seconds
Started Jul 13 04:43:55 PM PDT 24
Finished Jul 13 04:57:13 PM PDT 24
Peak memory 219476 kb
Host smart-a71f03a9-c3c7-4b5e-a038-fdfd345a2352
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929973557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1929973557
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2734403171
Short name T275
Test name
Test status
Simulation time 13400314625 ps
CPU time 58.18 seconds
Started Jul 13 04:43:58 PM PDT 24
Finished Jul 13 04:44:57 PM PDT 24
Peak memory 219092 kb
Host smart-d171039b-6d29-4c8d-b2a5-0808d84e896c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734403171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2734403171
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.743097315
Short name T126
Test name
Test status
Simulation time 1173685055 ps
CPU time 17.93 seconds
Started Jul 13 04:43:54 PM PDT 24
Finished Jul 13 04:44:12 PM PDT 24
Peak memory 219268 kb
Host smart-258b6ef0-5f2b-4fc3-9252-4e1912795b9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=743097315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.743097315
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.127640836
Short name T302
Test name
Test status
Simulation time 4131288298 ps
CPU time 38.17 seconds
Started Jul 13 04:43:53 PM PDT 24
Finished Jul 13 04:44:31 PM PDT 24
Peak memory 216396 kb
Host smart-31146083-5a55-4298-bca0-d8a9c0788019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127640836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.127640836
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.4294334303
Short name T284
Test name
Test status
Simulation time 451740535 ps
CPU time 24.79 seconds
Started Jul 13 04:43:53 PM PDT 24
Finished Jul 13 04:44:19 PM PDT 24
Peak memory 219248 kb
Host smart-6733f132-3c2e-43a5-a939-b19e03dc07d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294334303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.4294334303
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3831819134
Short name T264
Test name
Test status
Simulation time 1079711239 ps
CPU time 10.03 seconds
Started Jul 13 04:43:52 PM PDT 24
Finished Jul 13 04:44:03 PM PDT 24
Peak memory 217180 kb
Host smart-598f4752-9294-4c49-99e4-7e324850714b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831819134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3831819134
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1346236869
Short name T131
Test name
Test status
Simulation time 99485312983 ps
CPU time 333.85 seconds
Started Jul 13 04:43:53 PM PDT 24
Finished Jul 13 04:49:27 PM PDT 24
Peak memory 237232 kb
Host smart-78137ea4-3d2a-48b0-a4af-39e46f856e3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346236869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1346236869
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3270984467
Short name T135
Test name
Test status
Simulation time 661777157 ps
CPU time 19.58 seconds
Started Jul 13 04:43:53 PM PDT 24
Finished Jul 13 04:44:12 PM PDT 24
Peak memory 219260 kb
Host smart-4ec91d2c-bb9e-439c-a3cc-3cbd30c27848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270984467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3270984467
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2067662799
Short name T165
Test name
Test status
Simulation time 790739897 ps
CPU time 10.58 seconds
Started Jul 13 04:43:53 PM PDT 24
Finished Jul 13 04:44:04 PM PDT 24
Peak memory 219560 kb
Host smart-51a9ebec-6bbe-4a51-9290-78a0a317bf7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2067662799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2067662799
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3705684827
Short name T129
Test name
Test status
Simulation time 7291795177 ps
CPU time 58.47 seconds
Started Jul 13 04:43:58 PM PDT 24
Finished Jul 13 04:44:57 PM PDT 24
Peak memory 216508 kb
Host smart-2ab1988a-4d6f-4ded-b2b3-4172c2bc1076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705684827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3705684827
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3098006597
Short name T353
Test name
Test status
Simulation time 307844068 ps
CPU time 8.58 seconds
Started Jul 13 04:44:03 PM PDT 24
Finished Jul 13 04:44:13 PM PDT 24
Peak memory 216912 kb
Host smart-a1f515f0-1eac-4563-a0c8-5a0f907d82b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098006597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3098006597
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1447423286
Short name T58
Test name
Test status
Simulation time 142203417506 ps
CPU time 412.15 seconds
Started Jul 13 04:43:50 PM PDT 24
Finished Jul 13 04:50:43 PM PDT 24
Peak memory 237580 kb
Host smart-ef27b14c-abf2-4b91-9fcb-fddea648bd97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447423286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1447423286
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1545956638
Short name T203
Test name
Test status
Simulation time 332421043 ps
CPU time 19.74 seconds
Started Jul 13 04:43:54 PM PDT 24
Finished Jul 13 04:44:14 PM PDT 24
Peak memory 219252 kb
Host smart-20ebafbc-8bb4-4053-8d88-c302b8879d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545956638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1545956638
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3377091389
Short name T317
Test name
Test status
Simulation time 14920322253 ps
CPU time 29.87 seconds
Started Jul 13 04:43:55 PM PDT 24
Finished Jul 13 04:44:25 PM PDT 24
Peak memory 211536 kb
Host smart-b1b72e96-4122-4243-8661-0b8c40231360
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3377091389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3377091389
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2001779703
Short name T319
Test name
Test status
Simulation time 8940705948 ps
CPU time 48.07 seconds
Started Jul 13 04:43:52 PM PDT 24
Finished Jul 13 04:44:40 PM PDT 24
Peak memory 216920 kb
Host smart-e5f13e23-b3b1-4e27-9cef-f9b66b96df3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001779703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2001779703
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3489257980
Short name T86
Test name
Test status
Simulation time 6445350571 ps
CPU time 87.07 seconds
Started Jul 13 04:43:50 PM PDT 24
Finished Jul 13 04:45:18 PM PDT 24
Peak memory 219268 kb
Host smart-00ef5303-da68-46f0-b9c4-29980aa346a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489257980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3489257980
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1852580310
Short name T202
Test name
Test status
Simulation time 13040287822 ps
CPU time 28.09 seconds
Started Jul 13 04:44:01 PM PDT 24
Finished Jul 13 04:44:31 PM PDT 24
Peak memory 217452 kb
Host smart-9763a064-fde8-4428-a740-09ec01041240
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852580310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1852580310
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.924250440
Short name T210
Test name
Test status
Simulation time 7154556347 ps
CPU time 136.57 seconds
Started Jul 13 04:43:59 PM PDT 24
Finished Jul 13 04:46:17 PM PDT 24
Peak memory 233884 kb
Host smart-390d1e8d-9ece-4797-82ae-369060af61fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924250440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.924250440
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.4264381055
Short name T321
Test name
Test status
Simulation time 346195932 ps
CPU time 19.23 seconds
Started Jul 13 04:44:01 PM PDT 24
Finished Jul 13 04:44:23 PM PDT 24
Peak memory 219212 kb
Host smart-912eca3e-2aee-44ca-86fd-0decb69a9139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264381055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.4264381055
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.4164801767
Short name T258
Test name
Test status
Simulation time 7873084853 ps
CPU time 21.89 seconds
Started Jul 13 04:44:01 PM PDT 24
Finished Jul 13 04:44:25 PM PDT 24
Peak memory 219336 kb
Host smart-7f0b0762-e024-4b65-904d-39f5e35aad04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4164801767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.4164801767
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3844425222
Short name T336
Test name
Test status
Simulation time 5755002333 ps
CPU time 45.2 seconds
Started Jul 13 04:44:01 PM PDT 24
Finished Jul 13 04:44:49 PM PDT 24
Peak memory 216452 kb
Host smart-f7568c9a-d32d-424f-88c6-5d4529112712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844425222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3844425222
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1925312923
Short name T105
Test name
Test status
Simulation time 68202568678 ps
CPU time 104.84 seconds
Started Jul 13 04:44:00 PM PDT 24
Finished Jul 13 04:45:46 PM PDT 24
Peak memory 220824 kb
Host smart-371fb5ef-0b36-4525-8dfe-8f5847375016
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925312923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1925312923
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3474599542
Short name T156
Test name
Test status
Simulation time 7691044501 ps
CPU time 29.77 seconds
Started Jul 13 04:43:59 PM PDT 24
Finished Jul 13 04:44:30 PM PDT 24
Peak memory 217396 kb
Host smart-d72ecd69-ad5a-400c-9003-5eadee3f949c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474599542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3474599542
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1418844937
Short name T236
Test name
Test status
Simulation time 20691871180 ps
CPU time 145.24 seconds
Started Jul 13 04:44:00 PM PDT 24
Finished Jul 13 04:46:28 PM PDT 24
Peak memory 236776 kb
Host smart-c53855ab-9dfa-47c1-bb89-e6f47415c5aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418844937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1418844937
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3221426870
Short name T167
Test name
Test status
Simulation time 12446951259 ps
CPU time 40.31 seconds
Started Jul 13 04:43:59 PM PDT 24
Finished Jul 13 04:44:42 PM PDT 24
Peak memory 219320 kb
Host smart-08152d69-3dc2-4ce9-871c-95498e83ce98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221426870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3221426870
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2465802855
Short name T187
Test name
Test status
Simulation time 1019357625 ps
CPU time 11.93 seconds
Started Jul 13 04:44:00 PM PDT 24
Finished Jul 13 04:44:14 PM PDT 24
Peak memory 219220 kb
Host smart-7b6bce13-53cc-494c-be76-22c3c32d7c1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2465802855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2465802855
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.201304308
Short name T238
Test name
Test status
Simulation time 6685032729 ps
CPU time 57.2 seconds
Started Jul 13 04:44:01 PM PDT 24
Finished Jul 13 04:45:01 PM PDT 24
Peak memory 216772 kb
Host smart-da9a62c9-6d83-4af2-8d6b-1bd315fd61da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201304308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.201304308
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.516409014
Short name T347
Test name
Test status
Simulation time 15591046570 ps
CPU time 170.7 seconds
Started Jul 13 04:44:00 PM PDT 24
Finished Jul 13 04:46:52 PM PDT 24
Peak memory 222104 kb
Host smart-4c3a71b9-be69-47ae-9996-65fffaa8ed01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516409014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.516409014
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.968755444
Short name T190
Test name
Test status
Simulation time 9977563635 ps
CPU time 22.99 seconds
Started Jul 13 04:43:27 PM PDT 24
Finished Jul 13 04:43:52 PM PDT 24
Peak memory 217524 kb
Host smart-5ee6ec5d-9ac7-4773-b1f8-74ff6feed596
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968755444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.968755444
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2936765374
Short name T161
Test name
Test status
Simulation time 15060148867 ps
CPU time 66.72 seconds
Started Jul 13 04:43:28 PM PDT 24
Finished Jul 13 04:44:37 PM PDT 24
Peak memory 219276 kb
Host smart-37affb96-c81e-4484-af43-6d74985974a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936765374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2936765374
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1435689956
Short name T337
Test name
Test status
Simulation time 189857839 ps
CPU time 11.2 seconds
Started Jul 13 04:43:33 PM PDT 24
Finished Jul 13 04:43:44 PM PDT 24
Peak memory 219232 kb
Host smart-c7bc3e8e-0555-43c7-a4dd-2fd2e4fac15d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1435689956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1435689956
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1576118687
Short name T29
Test name
Test status
Simulation time 3095761525 ps
CPU time 130.32 seconds
Started Jul 13 04:44:32 PM PDT 24
Finished Jul 13 04:46:43 PM PDT 24
Peak memory 238240 kb
Host smart-431104cd-8db2-4974-a2a0-d12d15e4acff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576118687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1576118687
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1405782410
Short name T39
Test name
Test status
Simulation time 7492459087 ps
CPU time 34.5 seconds
Started Jul 13 04:43:26 PM PDT 24
Finished Jul 13 04:44:03 PM PDT 24
Peak memory 216528 kb
Host smart-7247bd64-f87a-484c-b00e-8879772fc6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405782410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1405782410
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.369189592
Short name T315
Test name
Test status
Simulation time 19040032204 ps
CPU time 49 seconds
Started Jul 13 04:43:28 PM PDT 24
Finished Jul 13 04:44:20 PM PDT 24
Peak memory 217004 kb
Host smart-167faa74-8e37-4d00-b608-104d9d3380c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369189592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.369189592
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.869283154
Short name T339
Test name
Test status
Simulation time 7847625606 ps
CPU time 20.66 seconds
Started Jul 13 04:43:59 PM PDT 24
Finished Jul 13 04:44:21 PM PDT 24
Peak memory 217512 kb
Host smart-5a8cfaac-23dc-48ac-94b3-03bcd1b72638
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869283154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.869283154
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1784700129
Short name T304
Test name
Test status
Simulation time 48484619919 ps
CPU time 457.37 seconds
Started Jul 13 04:44:03 PM PDT 24
Finished Jul 13 04:51:42 PM PDT 24
Peak memory 225700 kb
Host smart-de25d3c8-f451-47e3-979c-32fb9ac08895
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784700129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1784700129
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2499284745
Short name T162
Test name
Test status
Simulation time 32779328864 ps
CPU time 65.66 seconds
Started Jul 13 04:44:00 PM PDT 24
Finished Jul 13 04:45:08 PM PDT 24
Peak memory 219320 kb
Host smart-ddd2a6f7-e80b-4169-b26c-f2928a6dd6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499284745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2499284745
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3577075318
Short name T128
Test name
Test status
Simulation time 7503917864 ps
CPU time 21.07 seconds
Started Jul 13 04:44:00 PM PDT 24
Finished Jul 13 04:44:24 PM PDT 24
Peak memory 211880 kb
Host smart-c201aa4c-902e-4e57-92c4-e3e1ce43fe49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3577075318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3577075318
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3664654806
Short name T1
Test name
Test status
Simulation time 364218156 ps
CPU time 20.65 seconds
Started Jul 13 04:43:59 PM PDT 24
Finished Jul 13 04:44:21 PM PDT 24
Peak memory 216412 kb
Host smart-6d5da6b1-15fb-465e-b295-8fc24f8ce81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664654806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3664654806
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.877293951
Short name T185
Test name
Test status
Simulation time 16188467950 ps
CPU time 111.04 seconds
Started Jul 13 04:44:01 PM PDT 24
Finished Jul 13 04:45:55 PM PDT 24
Peak memory 220208 kb
Host smart-bd766125-d096-46f3-9488-bd02f3303063
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877293951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.877293951
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2712209981
Short name T195
Test name
Test status
Simulation time 6688259462 ps
CPU time 27.31 seconds
Started Jul 13 04:44:00 PM PDT 24
Finished Jul 13 04:44:29 PM PDT 24
Peak memory 217516 kb
Host smart-09178f3e-c338-4454-90ef-617f89fa54a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712209981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2712209981
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3504156361
Short name T253
Test name
Test status
Simulation time 83729275382 ps
CPU time 426.73 seconds
Started Jul 13 04:43:59 PM PDT 24
Finished Jul 13 04:51:06 PM PDT 24
Peak memory 218300 kb
Host smart-4993cc71-2508-42d8-87fd-ca6f366a55c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504156361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3504156361
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3083077329
Short name T5
Test name
Test status
Simulation time 32122607435 ps
CPU time 63.19 seconds
Started Jul 13 04:44:02 PM PDT 24
Finished Jul 13 04:45:07 PM PDT 24
Peak memory 219288 kb
Host smart-a3e02b3d-c029-4c3d-b6c8-f2b5a997a9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083077329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3083077329
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3631280062
Short name T160
Test name
Test status
Simulation time 15704085236 ps
CPU time 32.6 seconds
Started Jul 13 04:44:01 PM PDT 24
Finished Jul 13 04:44:36 PM PDT 24
Peak memory 211796 kb
Host smart-fd565a83-3fd7-4c66-bbae-0943a0733523
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3631280062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3631280062
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3258734273
Short name T344
Test name
Test status
Simulation time 16139282730 ps
CPU time 75.47 seconds
Started Jul 13 04:44:00 PM PDT 24
Finished Jul 13 04:45:17 PM PDT 24
Peak memory 218316 kb
Host smart-4658db2d-3193-4bdd-9057-9178a3d10e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258734273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3258734273
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1984656016
Short name T217
Test name
Test status
Simulation time 8025697939 ps
CPU time 65.42 seconds
Started Jul 13 04:44:00 PM PDT 24
Finished Jul 13 04:45:07 PM PDT 24
Peak memory 220028 kb
Host smart-37fc8198-0988-49bb-bdd2-77e6ffcd4b9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984656016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1984656016
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2604095667
Short name T49
Test name
Test status
Simulation time 94248341825 ps
CPU time 3842.43 seconds
Started Jul 13 04:44:01 PM PDT 24
Finished Jul 13 05:48:07 PM PDT 24
Peak memory 252136 kb
Host smart-181bb3d5-2dcf-4f06-ae17-cf192e794112
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604095667 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.2604095667
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3798536302
Short name T166
Test name
Test status
Simulation time 1571008248 ps
CPU time 11.03 seconds
Started Jul 13 04:43:59 PM PDT 24
Finished Jul 13 04:44:12 PM PDT 24
Peak memory 216608 kb
Host smart-de095539-97e3-48a2-b843-80f79ea2a8bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798536302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3798536302
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.898178882
Short name T133
Test name
Test status
Simulation time 233542604007 ps
CPU time 761.19 seconds
Started Jul 13 04:44:00 PM PDT 24
Finished Jul 13 04:56:44 PM PDT 24
Peak memory 225464 kb
Host smart-d0b93db9-bf11-433b-ac7d-ca1ccb786f7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898178882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.898178882
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3631697200
Short name T48
Test name
Test status
Simulation time 20267395692 ps
CPU time 53.14 seconds
Started Jul 13 04:44:01 PM PDT 24
Finished Jul 13 04:44:56 PM PDT 24
Peak memory 219272 kb
Host smart-f55fb111-6911-4656-a7ee-fc8d580e51ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631697200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3631697200
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2713462550
Short name T37
Test name
Test status
Simulation time 14472421645 ps
CPU time 21.15 seconds
Started Jul 13 04:44:00 PM PDT 24
Finished Jul 13 04:44:23 PM PDT 24
Peak memory 219268 kb
Host smart-37b09ddc-cbf1-4910-829d-ce08bc44dce0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2713462550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2713462550
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.47228922
Short name T214
Test name
Test status
Simulation time 8553900818 ps
CPU time 69.64 seconds
Started Jul 13 04:44:02 PM PDT 24
Finished Jul 13 04:45:14 PM PDT 24
Peak memory 217704 kb
Host smart-eb7297fe-e69e-42b7-9268-f830c660ca3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47228922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.47228922
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.1920086033
Short name T16
Test name
Test status
Simulation time 106106793293 ps
CPU time 1071.12 seconds
Started Jul 13 04:43:59 PM PDT 24
Finished Jul 13 05:01:51 PM PDT 24
Peak memory 235724 kb
Host smart-0f13cb3e-4dc6-4a53-8219-87a3da301408
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920086033 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.1920086033
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1468260684
Short name T67
Test name
Test status
Simulation time 3630532198 ps
CPU time 14.76 seconds
Started Jul 13 04:44:01 PM PDT 24
Finished Jul 13 04:44:18 PM PDT 24
Peak memory 217220 kb
Host smart-affdcafa-a03f-460f-ab4b-7aac10d616d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468260684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1468260684
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.491708322
Short name T281
Test name
Test status
Simulation time 41841259074 ps
CPU time 495.55 seconds
Started Jul 13 04:44:01 PM PDT 24
Finished Jul 13 04:52:19 PM PDT 24
Peak memory 225552 kb
Host smart-2d5ffbee-e0d9-4156-a779-6b3dacf8cead
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491708322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.491708322
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1657487386
Short name T33
Test name
Test status
Simulation time 333038546 ps
CPU time 19.19 seconds
Started Jul 13 04:44:01 PM PDT 24
Finished Jul 13 04:44:22 PM PDT 24
Peak memory 219260 kb
Host smart-67293951-ed5f-4d88-a2b9-8724573b89b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657487386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1657487386
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3643597248
Short name T283
Test name
Test status
Simulation time 699384132 ps
CPU time 10.49 seconds
Started Jul 13 04:44:00 PM PDT 24
Finished Jul 13 04:44:12 PM PDT 24
Peak memory 219216 kb
Host smart-cb942d89-b8dd-42e3-af95-b5f1c36e7078
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3643597248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3643597248
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3945220532
Short name T82
Test name
Test status
Simulation time 10827449082 ps
CPU time 59.02 seconds
Started Jul 13 04:44:02 PM PDT 24
Finished Jul 13 04:45:03 PM PDT 24
Peak memory 216856 kb
Host smart-7ad52086-9b2d-4c9a-8e28-22e9e9a5ff74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945220532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3945220532
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3742487434
Short name T209
Test name
Test status
Simulation time 6470864995 ps
CPU time 108.69 seconds
Started Jul 13 04:44:00 PM PDT 24
Finished Jul 13 04:45:50 PM PDT 24
Peak memory 221480 kb
Host smart-a2197b1b-78a7-4be0-859b-1f451d0b83ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742487434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3742487434
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2214418801
Short name T10
Test name
Test status
Simulation time 1172544171 ps
CPU time 15.94 seconds
Started Jul 13 04:44:01 PM PDT 24
Finished Jul 13 04:44:19 PM PDT 24
Peak memory 217168 kb
Host smart-98abf3ca-b1c3-4670-929c-fd5d11ef8b7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214418801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2214418801
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.4118773504
Short name T232
Test name
Test status
Simulation time 103553832894 ps
CPU time 1039.86 seconds
Started Jul 13 04:44:00 PM PDT 24
Finished Jul 13 05:01:22 PM PDT 24
Peak memory 233752 kb
Host smart-1c5ecd30-ba16-4641-afc3-29d755702e02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118773504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.4118773504
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1418055565
Short name T296
Test name
Test status
Simulation time 2813788593 ps
CPU time 18.02 seconds
Started Jul 13 04:44:01 PM PDT 24
Finished Jul 13 04:44:22 PM PDT 24
Peak memory 219328 kb
Host smart-940068ec-cb09-4a1b-963b-6a932f760bee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1418055565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1418055565
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3304656385
Short name T231
Test name
Test status
Simulation time 2501734388 ps
CPU time 25.71 seconds
Started Jul 13 04:44:01 PM PDT 24
Finished Jul 13 04:44:29 PM PDT 24
Peak memory 216728 kb
Host smart-3ddd0ed1-7114-4446-ae19-4477ecd053de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304656385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3304656385
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3619909041
Short name T237
Test name
Test status
Simulation time 18028150494 ps
CPU time 60.25 seconds
Started Jul 13 04:44:02 PM PDT 24
Finished Jul 13 04:45:04 PM PDT 24
Peak memory 219504 kb
Host smart-695af2fd-4519-4641-9283-9865cc9704c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619909041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3619909041
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3608066693
Short name T8
Test name
Test status
Simulation time 3433219524 ps
CPU time 14.06 seconds
Started Jul 13 04:44:15 PM PDT 24
Finished Jul 13 04:44:29 PM PDT 24
Peak memory 217112 kb
Host smart-5e0ab3bf-98df-4160-b5fa-de30756e7f25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608066693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3608066693
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3479592268
Short name T40
Test name
Test status
Simulation time 170286331460 ps
CPU time 512.97 seconds
Started Jul 13 04:43:58 PM PDT 24
Finished Jul 13 04:52:31 PM PDT 24
Peak memory 217696 kb
Host smart-34f76973-9b1d-406f-9862-afc4f52718ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479592268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3479592268
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.284261354
Short name T267
Test name
Test status
Simulation time 28656818920 ps
CPU time 61.13 seconds
Started Jul 13 04:44:01 PM PDT 24
Finished Jul 13 04:45:04 PM PDT 24
Peak memory 219252 kb
Host smart-4fd33034-f4fd-4cc3-a849-71ba2b8aea1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284261354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.284261354
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1026638945
Short name T219
Test name
Test status
Simulation time 2435487436 ps
CPU time 16.08 seconds
Started Jul 13 04:44:00 PM PDT 24
Finished Jul 13 04:44:17 PM PDT 24
Peak memory 211712 kb
Host smart-e371becf-0b66-4e5a-90f0-ced931746162
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1026638945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1026638945
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2323595115
Short name T279
Test name
Test status
Simulation time 8361618096 ps
CPU time 76.48 seconds
Started Jul 13 04:44:00 PM PDT 24
Finished Jul 13 04:45:19 PM PDT 24
Peak memory 216620 kb
Host smart-713015b4-5dfc-46d0-904b-26a622af964f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323595115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2323595115
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2331023518
Short name T285
Test name
Test status
Simulation time 559260916 ps
CPU time 31.86 seconds
Started Jul 13 04:44:01 PM PDT 24
Finished Jul 13 04:44:35 PM PDT 24
Peak memory 219272 kb
Host smart-bab97949-13db-4d53-be08-c61a99af384e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331023518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2331023518
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.4061921058
Short name T149
Test name
Test status
Simulation time 40807384800 ps
CPU time 32.72 seconds
Started Jul 13 04:44:09 PM PDT 24
Finished Jul 13 04:44:42 PM PDT 24
Peak memory 217312 kb
Host smart-12e6cbe8-8f12-40e5-a440-0784ac6ec593
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061921058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.4061921058
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3102981105
Short name T276
Test name
Test status
Simulation time 198576440970 ps
CPU time 484.05 seconds
Started Jul 13 04:44:12 PM PDT 24
Finished Jul 13 04:52:17 PM PDT 24
Peak memory 226388 kb
Host smart-ea14c4c7-a8e0-4be2-ac0f-544970d10645
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102981105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3102981105
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3017424703
Short name T173
Test name
Test status
Simulation time 32136705694 ps
CPU time 65.13 seconds
Started Jul 13 04:44:09 PM PDT 24
Finished Jul 13 04:45:15 PM PDT 24
Peak memory 219264 kb
Host smart-f41158e7-91d6-46a6-ac79-d265d3253b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017424703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3017424703
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1403276104
Short name T261
Test name
Test status
Simulation time 3154615708 ps
CPU time 15.07 seconds
Started Jul 13 04:44:08 PM PDT 24
Finished Jul 13 04:44:24 PM PDT 24
Peak memory 218852 kb
Host smart-da219307-8518-4886-a1f4-88ccf7a402d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1403276104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1403276104
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1540718258
Short name T310
Test name
Test status
Simulation time 25381951535 ps
CPU time 53.86 seconds
Started Jul 13 04:44:09 PM PDT 24
Finished Jul 13 04:45:03 PM PDT 24
Peak memory 216624 kb
Host smart-400f56eb-94fb-46db-8a61-3ed5edab7b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540718258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1540718258
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2508080005
Short name T322
Test name
Test status
Simulation time 2098349231 ps
CPU time 50.08 seconds
Started Jul 13 04:44:12 PM PDT 24
Finished Jul 13 04:45:02 PM PDT 24
Peak memory 219260 kb
Host smart-355bfb31-31af-49e1-9ac6-bfdb8483aa0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508080005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2508080005
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2867003366
Short name T66
Test name
Test status
Simulation time 6462455710 ps
CPU time 18.79 seconds
Started Jul 13 04:44:08 PM PDT 24
Finished Jul 13 04:44:28 PM PDT 24
Peak memory 217196 kb
Host smart-72c89253-dfc2-4bb9-a32d-a13f8b5f72d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867003366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2867003366
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1817740535
Short name T57
Test name
Test status
Simulation time 2219717611 ps
CPU time 157.95 seconds
Started Jul 13 04:44:08 PM PDT 24
Finished Jul 13 04:46:47 PM PDT 24
Peak memory 225076 kb
Host smart-3989f410-0255-4534-8177-0bd07e8f7de7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817740535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1817740535
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1348689836
Short name T154
Test name
Test status
Simulation time 5699856723 ps
CPU time 51.67 seconds
Started Jul 13 04:44:08 PM PDT 24
Finished Jul 13 04:45:00 PM PDT 24
Peak memory 219172 kb
Host smart-0e3dd56c-348c-4aaa-a188-7e70758b88cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348689836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1348689836
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3240372798
Short name T242
Test name
Test status
Simulation time 2826169502 ps
CPU time 27 seconds
Started Jul 13 04:44:11 PM PDT 24
Finished Jul 13 04:44:39 PM PDT 24
Peak memory 219368 kb
Host smart-14bcb3ba-fc30-48ae-9770-7cafbb8a8c09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3240372798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3240372798
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1424604319
Short name T265
Test name
Test status
Simulation time 17137651325 ps
CPU time 55.13 seconds
Started Jul 13 04:44:08 PM PDT 24
Finished Jul 13 04:45:04 PM PDT 24
Peak memory 216820 kb
Host smart-3c4df476-7795-4142-9616-f7d9ca76a195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424604319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1424604319
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2336815262
Short name T134
Test name
Test status
Simulation time 12491414113 ps
CPU time 117.48 seconds
Started Jul 13 04:44:08 PM PDT 24
Finished Jul 13 04:46:05 PM PDT 24
Peak memory 219868 kb
Host smart-6862f696-2f67-4f52-817e-b11c932bcf56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336815262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2336815262
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.415146744
Short name T172
Test name
Test status
Simulation time 1029690123 ps
CPU time 12.41 seconds
Started Jul 13 04:44:11 PM PDT 24
Finished Jul 13 04:44:24 PM PDT 24
Peak memory 217048 kb
Host smart-dbc0b85b-fbf6-4d4f-b658-8d4cc3fb3a5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415146744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.415146744
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3225544121
Short name T194
Test name
Test status
Simulation time 248824395688 ps
CPU time 493.54 seconds
Started Jul 13 04:44:09 PM PDT 24
Finished Jul 13 04:52:23 PM PDT 24
Peak memory 234336 kb
Host smart-bb37c386-0d76-4079-b6c5-7fa728839011
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225544121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3225544121
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3111257959
Short name T114
Test name
Test status
Simulation time 8531247021 ps
CPU time 65.7 seconds
Started Jul 13 04:44:09 PM PDT 24
Finished Jul 13 04:45:15 PM PDT 24
Peak memory 219320 kb
Host smart-f76e65d9-a4d8-445d-b3d8-2a2839667207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111257959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3111257959
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3590326894
Short name T11
Test name
Test status
Simulation time 3779461694 ps
CPU time 31.13 seconds
Started Jul 13 04:44:12 PM PDT 24
Finished Jul 13 04:44:43 PM PDT 24
Peak memory 219296 kb
Host smart-63554944-51e8-480d-bb40-dd4c4fb9dba1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3590326894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3590326894
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2593756491
Short name T132
Test name
Test status
Simulation time 30355694285 ps
CPU time 66.12 seconds
Started Jul 13 04:44:10 PM PDT 24
Finished Jul 13 04:45:16 PM PDT 24
Peak memory 218100 kb
Host smart-6ea92842-9445-4e24-ba86-bb3e5bdfd3c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593756491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2593756491
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2097789
Short name T249
Test name
Test status
Simulation time 170770827 ps
CPU time 8.54 seconds
Started Jul 13 04:44:19 PM PDT 24
Finished Jul 13 04:44:27 PM PDT 24
Peak memory 217196 kb
Host smart-d9aa8ad0-734a-4cf2-9364-1717c37673a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2097789
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1680484900
Short name T61
Test name
Test status
Simulation time 24363961301 ps
CPU time 297.02 seconds
Started Jul 13 04:44:08 PM PDT 24
Finished Jul 13 04:49:05 PM PDT 24
Peak memory 228276 kb
Host smart-a8a32c39-e780-40a2-a146-8a4cc842c1b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680484900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1680484900
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.616319046
Short name T300
Test name
Test status
Simulation time 7031370006 ps
CPU time 24.26 seconds
Started Jul 13 04:44:14 PM PDT 24
Finished Jul 13 04:44:39 PM PDT 24
Peak memory 219360 kb
Host smart-2bbceab3-bfa7-4614-aa1d-3b1aff5b6139
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=616319046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.616319046
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1762286438
Short name T83
Test name
Test status
Simulation time 5593506252 ps
CPU time 59.2 seconds
Started Jul 13 04:44:09 PM PDT 24
Finished Jul 13 04:45:09 PM PDT 24
Peak memory 216812 kb
Host smart-4cd81456-eb60-4da0-acc0-be8f21634b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762286438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1762286438
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.821903865
Short name T38
Test name
Test status
Simulation time 32318207338 ps
CPU time 164.17 seconds
Started Jul 13 04:44:14 PM PDT 24
Finished Jul 13 04:46:58 PM PDT 24
Peak memory 230336 kb
Host smart-6c627f2d-6950-4dce-b7bf-dc49e73753dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821903865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.821903865
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3453252310
Short name T46
Test name
Test status
Simulation time 1550807643 ps
CPU time 18.31 seconds
Started Jul 13 04:43:28 PM PDT 24
Finished Jul 13 04:43:48 PM PDT 24
Peak memory 217100 kb
Host smart-43c48125-a255-4e91-b6ab-43d9b3cf59a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453252310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3453252310
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.4243086023
Short name T207
Test name
Test status
Simulation time 7812364824 ps
CPU time 137.43 seconds
Started Jul 13 04:43:30 PM PDT 24
Finished Jul 13 04:45:49 PM PDT 24
Peak memory 235216 kb
Host smart-e2371f9a-0099-4d54-8354-d4641613f578
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243086023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.4243086023
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2388917405
Short name T326
Test name
Test status
Simulation time 8354416663 ps
CPU time 65.1 seconds
Started Jul 13 04:43:27 PM PDT 24
Finished Jul 13 04:44:35 PM PDT 24
Peak memory 219176 kb
Host smart-f9733181-2068-4e23-ba1f-b1ef507cd226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388917405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2388917405
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1889328218
Short name T257
Test name
Test status
Simulation time 5468546892 ps
CPU time 25.51 seconds
Started Jul 13 04:44:49 PM PDT 24
Finished Jul 13 04:45:16 PM PDT 24
Peak memory 219304 kb
Host smart-763d184f-7243-441b-8981-0a3cf4523e55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1889328218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1889328218
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1878673762
Short name T30
Test name
Test status
Simulation time 3522445921 ps
CPU time 139.43 seconds
Started Jul 13 04:43:31 PM PDT 24
Finished Jul 13 04:45:51 PM PDT 24
Peak memory 239600 kb
Host smart-764bc41e-f857-4495-a008-9a1a20153970
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878673762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1878673762
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.896996326
Short name T260
Test name
Test status
Simulation time 21037233453 ps
CPU time 56.4 seconds
Started Jul 13 04:43:27 PM PDT 24
Finished Jul 13 04:44:25 PM PDT 24
Peak memory 217020 kb
Host smart-364cd096-66b1-4a28-beec-f84ec614d0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896996326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.896996326
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1184613325
Short name T274
Test name
Test status
Simulation time 16790927154 ps
CPU time 184.86 seconds
Started Jul 13 04:43:28 PM PDT 24
Finished Jul 13 04:46:35 PM PDT 24
Peak memory 220760 kb
Host smart-4dc48095-86f4-4b80-b7e6-092c31439b9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184613325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1184613325
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1201167904
Short name T50
Test name
Test status
Simulation time 796577485354 ps
CPU time 2225.26 seconds
Started Jul 13 04:43:28 PM PDT 24
Finished Jul 13 05:20:36 PM PDT 24
Peak memory 248160 kb
Host smart-52790bf0-db8e-45b8-8e41-af3cf5ff4dcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201167904 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.1201167904
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3112597670
Short name T189
Test name
Test status
Simulation time 1941093441 ps
CPU time 20.61 seconds
Started Jul 13 04:44:17 PM PDT 24
Finished Jul 13 04:44:38 PM PDT 24
Peak memory 217080 kb
Host smart-6683742a-80bc-4b41-8161-e54219cd45b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112597670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3112597670
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1257304807
Short name T220
Test name
Test status
Simulation time 130344643526 ps
CPU time 439.14 seconds
Started Jul 13 04:44:16 PM PDT 24
Finished Jul 13 04:51:35 PM PDT 24
Peak memory 234124 kb
Host smart-d1d07345-69dc-4bca-a7a5-fe8ada3ecafb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257304807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1257304807
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1583527855
Short name T4
Test name
Test status
Simulation time 32782643484 ps
CPU time 65.87 seconds
Started Jul 13 04:44:15 PM PDT 24
Finished Jul 13 04:45:21 PM PDT 24
Peak memory 219324 kb
Host smart-85e76d38-f38a-4f82-ab4a-c0394af2a3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583527855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1583527855
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3115641430
Short name T22
Test name
Test status
Simulation time 3572446308 ps
CPU time 22.55 seconds
Started Jul 13 04:44:17 PM PDT 24
Finished Jul 13 04:44:40 PM PDT 24
Peak memory 219268 kb
Host smart-a25b319f-5256-464b-80b2-c02bbc88745a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3115641430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3115641430
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2017206043
Short name T340
Test name
Test status
Simulation time 9873699598 ps
CPU time 37.08 seconds
Started Jul 13 04:44:17 PM PDT 24
Finished Jul 13 04:44:54 PM PDT 24
Peak memory 216184 kb
Host smart-d1968b0a-2195-4b57-8568-609223fd081f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017206043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2017206043
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2550137099
Short name T139
Test name
Test status
Simulation time 3053625506 ps
CPU time 34.06 seconds
Started Jul 13 04:44:19 PM PDT 24
Finished Jul 13 04:44:53 PM PDT 24
Peak memory 219104 kb
Host smart-2757b366-5bcf-438f-a8b9-22bcca3d901c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550137099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2550137099
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3072035307
Short name T313
Test name
Test status
Simulation time 345516950 ps
CPU time 8.5 seconds
Started Jul 13 04:44:25 PM PDT 24
Finished Jul 13 04:44:34 PM PDT 24
Peak memory 217016 kb
Host smart-e18a7713-1087-4222-9c96-aeb98bd06715
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072035307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3072035307
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3741700697
Short name T100
Test name
Test status
Simulation time 97159763418 ps
CPU time 284.25 seconds
Started Jul 13 04:44:25 PM PDT 24
Finished Jul 13 04:49:10 PM PDT 24
Peak memory 238848 kb
Host smart-16d5714d-324e-44f8-b0e8-3e3ecbb6e325
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741700697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3741700697
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3883220421
Short name T350
Test name
Test status
Simulation time 7495770259 ps
CPU time 61.88 seconds
Started Jul 13 04:44:26 PM PDT 24
Finished Jul 13 04:45:28 PM PDT 24
Peak memory 219320 kb
Host smart-f5d3ce87-bf54-4bd8-ac99-661d92082aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883220421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3883220421
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3771732089
Short name T268
Test name
Test status
Simulation time 682208904 ps
CPU time 10.95 seconds
Started Jul 13 04:44:24 PM PDT 24
Finished Jul 13 04:44:35 PM PDT 24
Peak memory 219232 kb
Host smart-c243356b-fba3-4427-9682-98743f5d52a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3771732089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3771732089
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1737366812
Short name T175
Test name
Test status
Simulation time 690629727 ps
CPU time 19.66 seconds
Started Jul 13 04:44:27 PM PDT 24
Finished Jul 13 04:44:47 PM PDT 24
Peak memory 216504 kb
Host smart-d7068894-3ec0-41d9-a7c1-04865e023088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737366812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1737366812
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1055186613
Short name T239
Test name
Test status
Simulation time 27955633510 ps
CPU time 113.21 seconds
Started Jul 13 04:44:27 PM PDT 24
Finished Jul 13 04:46:20 PM PDT 24
Peak memory 227564 kb
Host smart-3c15e8ae-dff7-49ec-932b-20741c85f626
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055186613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1055186613
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2075544990
Short name T295
Test name
Test status
Simulation time 864408782 ps
CPU time 14.18 seconds
Started Jul 13 04:44:25 PM PDT 24
Finished Jul 13 04:44:40 PM PDT 24
Peak memory 217152 kb
Host smart-108e581b-7f71-4c46-ad79-310ddda59f13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075544990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2075544990
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2938953005
Short name T269
Test name
Test status
Simulation time 189241341962 ps
CPU time 548.95 seconds
Started Jul 13 04:44:26 PM PDT 24
Finished Jul 13 04:53:36 PM PDT 24
Peak memory 230404 kb
Host smart-c515a3f6-37cf-4edc-b42a-1a731cab77e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938953005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2938953005
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3675465476
Short name T59
Test name
Test status
Simulation time 516744250 ps
CPU time 22.57 seconds
Started Jul 13 04:44:25 PM PDT 24
Finished Jul 13 04:44:48 PM PDT 24
Peak memory 219260 kb
Host smart-c466297f-7e09-49b7-b892-4d448da206c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675465476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3675465476
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.913057930
Short name T311
Test name
Test status
Simulation time 15298833592 ps
CPU time 29.11 seconds
Started Jul 13 04:44:25 PM PDT 24
Finished Jul 13 04:44:55 PM PDT 24
Peak memory 211956 kb
Host smart-a62b0135-9d43-4d51-be04-12da8622290b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=913057930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.913057930
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.4148338790
Short name T141
Test name
Test status
Simulation time 8196522263 ps
CPU time 74.34 seconds
Started Jul 13 04:44:25 PM PDT 24
Finished Jul 13 04:45:40 PM PDT 24
Peak memory 216904 kb
Host smart-40929b71-75a1-458d-8829-d214679b7834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148338790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.4148338790
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3696182002
Short name T127
Test name
Test status
Simulation time 2732829760 ps
CPU time 22.33 seconds
Started Jul 13 04:44:25 PM PDT 24
Finished Jul 13 04:44:48 PM PDT 24
Peak memory 217988 kb
Host smart-03be7e0b-5d96-43c0-b40f-0d42fdfa4cc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696182002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3696182002
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2936700627
Short name T204
Test name
Test status
Simulation time 612333068 ps
CPU time 8.22 seconds
Started Jul 13 04:44:36 PM PDT 24
Finished Jul 13 04:44:46 PM PDT 24
Peak memory 217128 kb
Host smart-bb79dbd1-6ae9-43d9-8c08-0f614b370cfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936700627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2936700627
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2089267549
Short name T287
Test name
Test status
Simulation time 25192065994 ps
CPU time 257.02 seconds
Started Jul 13 04:44:36 PM PDT 24
Finished Jul 13 04:48:54 PM PDT 24
Peak memory 233792 kb
Host smart-73a760cb-0a2d-4698-951d-fe9a2f223dba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089267549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2089267549
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.4148668158
Short name T64
Test name
Test status
Simulation time 2318826071 ps
CPU time 35.28 seconds
Started Jul 13 04:44:36 PM PDT 24
Finished Jul 13 04:45:12 PM PDT 24
Peak memory 219328 kb
Host smart-7043b195-1dc8-4884-a2f9-932dc97a4f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148668158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.4148668158
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.4228104275
Short name T246
Test name
Test status
Simulation time 183107881 ps
CPU time 10.38 seconds
Started Jul 13 04:44:28 PM PDT 24
Finished Jul 13 04:44:39 PM PDT 24
Peak memory 219208 kb
Host smart-3fabb0ee-7e41-469f-a7fb-2b3f8118abc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4228104275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.4228104275
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3416919973
Short name T170
Test name
Test status
Simulation time 11221968636 ps
CPU time 37.79 seconds
Started Jul 13 04:44:26 PM PDT 24
Finished Jul 13 04:45:04 PM PDT 24
Peak memory 216004 kb
Host smart-0cfe4171-9458-48c2-8773-e5f80284f1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416919973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3416919973
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2175677490
Short name T256
Test name
Test status
Simulation time 26884791941 ps
CPU time 71.25 seconds
Started Jul 13 04:44:25 PM PDT 24
Finished Jul 13 04:45:37 PM PDT 24
Peak memory 219320 kb
Host smart-09260bb3-1c5d-43bd-a1eb-1a75f0ebddbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175677490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2175677490
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2886241256
Short name T164
Test name
Test status
Simulation time 824966591 ps
CPU time 8.32 seconds
Started Jul 13 04:44:36 PM PDT 24
Finished Jul 13 04:44:45 PM PDT 24
Peak memory 217112 kb
Host smart-6388d110-4f45-452e-8dd2-bbd22bf4bdbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886241256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2886241256
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.118015383
Short name T45
Test name
Test status
Simulation time 16902968246 ps
CPU time 219.7 seconds
Started Jul 13 04:44:36 PM PDT 24
Finished Jul 13 04:48:17 PM PDT 24
Peak memory 236884 kb
Host smart-c3379b9a-e752-4149-b00b-f9b72a222be0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118015383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.118015383
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1428247273
Short name T101
Test name
Test status
Simulation time 6898849926 ps
CPU time 59.09 seconds
Started Jul 13 04:44:36 PM PDT 24
Finished Jul 13 04:45:36 PM PDT 24
Peak memory 219328 kb
Host smart-8bf6663c-7da7-42a4-b37f-c8b2eb0db59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428247273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1428247273
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1677085024
Short name T309
Test name
Test status
Simulation time 1840735814 ps
CPU time 21.89 seconds
Started Jul 13 04:44:34 PM PDT 24
Finished Jul 13 04:44:57 PM PDT 24
Peak memory 211356 kb
Host smart-d12998b7-0281-4b24-987e-f5180b818e0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1677085024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1677085024
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1790406991
Short name T291
Test name
Test status
Simulation time 11757034124 ps
CPU time 49.68 seconds
Started Jul 13 04:44:36 PM PDT 24
Finished Jul 13 04:45:27 PM PDT 24
Peak memory 217212 kb
Host smart-59712266-f56f-41c6-92fb-aa36493af6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790406991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1790406991
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2926746736
Short name T205
Test name
Test status
Simulation time 19343816876 ps
CPU time 89.54 seconds
Started Jul 13 04:44:36 PM PDT 24
Finished Jul 13 04:46:07 PM PDT 24
Peak memory 220612 kb
Host smart-d86ab3b0-7664-4d00-8836-2ac706b0f131
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926746736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2926746736
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2699664640
Short name T252
Test name
Test status
Simulation time 3954140853 ps
CPU time 20.36 seconds
Started Jul 13 04:44:37 PM PDT 24
Finished Jul 13 04:44:58 PM PDT 24
Peak memory 217068 kb
Host smart-6a90f7a3-6d84-45c9-8164-a6cca93cd061
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699664640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2699664640
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2129644252
Short name T277
Test name
Test status
Simulation time 299935201830 ps
CPU time 467.89 seconds
Started Jul 13 04:44:35 PM PDT 24
Finished Jul 13 04:52:24 PM PDT 24
Peak memory 233564 kb
Host smart-4ddcfc31-fe97-4879-b60d-1878bac7a201
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129644252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2129644252
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1487820337
Short name T312
Test name
Test status
Simulation time 13347948692 ps
CPU time 57.2 seconds
Started Jul 13 04:44:34 PM PDT 24
Finished Jul 13 04:45:32 PM PDT 24
Peak memory 219320 kb
Host smart-a9385573-0b72-468e-a5cc-362cc3bf6148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487820337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1487820337
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2462181411
Short name T176
Test name
Test status
Simulation time 4931988521 ps
CPU time 24.4 seconds
Started Jul 13 04:44:35 PM PDT 24
Finished Jul 13 04:45:01 PM PDT 24
Peak memory 219288 kb
Host smart-7d6e5ca0-c39e-4199-95f8-405ad976ebaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2462181411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2462181411
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.4024149836
Short name T342
Test name
Test status
Simulation time 4961540837 ps
CPU time 35.98 seconds
Started Jul 13 04:44:37 PM PDT 24
Finished Jul 13 04:45:14 PM PDT 24
Peak memory 216788 kb
Host smart-8fcf37f6-084a-40d1-9e73-0f9de27edb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024149836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.4024149836
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.470464970
Short name T169
Test name
Test status
Simulation time 105397237945 ps
CPU time 114.13 seconds
Started Jul 13 04:44:35 PM PDT 24
Finished Jul 13 04:46:31 PM PDT 24
Peak memory 219272 kb
Host smart-5095c6f3-a2a2-4f56-ad45-7e0530b90369
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470464970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.470464970
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1941821946
Short name T157
Test name
Test status
Simulation time 786813742 ps
CPU time 8.22 seconds
Started Jul 13 04:44:36 PM PDT 24
Finished Jul 13 04:44:45 PM PDT 24
Peak memory 217184 kb
Host smart-b3a1c156-ce4a-48f7-bb13-b00063703f76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941821946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1941821946
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.319921153
Short name T247
Test name
Test status
Simulation time 149554087538 ps
CPU time 672.19 seconds
Started Jul 13 04:44:35 PM PDT 24
Finished Jul 13 04:55:48 PM PDT 24
Peak memory 225632 kb
Host smart-cac69e26-576d-401f-a5a9-10368da71031
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319921153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.319921153
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.502204330
Short name T145
Test name
Test status
Simulation time 3102326620 ps
CPU time 37.03 seconds
Started Jul 13 04:44:36 PM PDT 24
Finished Jul 13 04:45:14 PM PDT 24
Peak memory 218972 kb
Host smart-6873c8b2-8308-4466-b680-c6d780e02204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502204330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.502204330
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2397165795
Short name T137
Test name
Test status
Simulation time 1198724766 ps
CPU time 17.68 seconds
Started Jul 13 04:44:37 PM PDT 24
Finished Jul 13 04:44:55 PM PDT 24
Peak memory 218592 kb
Host smart-166e5a13-6890-4213-91d0-71f8cbfc8ccd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2397165795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2397165795
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2404274133
Short name T235
Test name
Test status
Simulation time 3270935142 ps
CPU time 47.85 seconds
Started Jul 13 04:44:35 PM PDT 24
Finished Jul 13 04:45:23 PM PDT 24
Peak memory 219388 kb
Host smart-7fdd5d21-401a-44be-b500-70fc7fe77d7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404274133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2404274133
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3509209427
Short name T234
Test name
Test status
Simulation time 3381586791 ps
CPU time 29.65 seconds
Started Jul 13 04:44:47 PM PDT 24
Finished Jul 13 04:45:18 PM PDT 24
Peak memory 217160 kb
Host smart-5a4069ce-6ae1-4611-b5ca-2ce3a8dfcb27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509209427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3509209427
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.385195190
Short name T192
Test name
Test status
Simulation time 186541343393 ps
CPU time 513.45 seconds
Started Jul 13 04:44:47 PM PDT 24
Finished Jul 13 04:53:21 PM PDT 24
Peak memory 237768 kb
Host smart-2aa96b64-c06f-4a53-8ea7-d1d2b1f9557e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385195190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.385195190
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.550145656
Short name T329
Test name
Test status
Simulation time 3023069392 ps
CPU time 38.41 seconds
Started Jul 13 04:44:47 PM PDT 24
Finished Jul 13 04:45:26 PM PDT 24
Peak memory 219296 kb
Host smart-559528a8-3b06-4a7b-9a2f-2798a721f6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550145656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.550145656
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1887827171
Short name T143
Test name
Test status
Simulation time 1024499315 ps
CPU time 10.59 seconds
Started Jul 13 04:44:35 PM PDT 24
Finished Jul 13 04:44:47 PM PDT 24
Peak memory 219244 kb
Host smart-f3d01460-e88a-4b7d-87e5-f6932766c543
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1887827171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1887827171
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.202572931
Short name T216
Test name
Test status
Simulation time 6598992793 ps
CPU time 73 seconds
Started Jul 13 04:44:35 PM PDT 24
Finished Jul 13 04:45:49 PM PDT 24
Peak memory 217068 kb
Host smart-3a96a793-681e-4b04-afb0-20dae36e08ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202572931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.202572931
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2088343374
Short name T338
Test name
Test status
Simulation time 5981715257 ps
CPU time 83.39 seconds
Started Jul 13 04:44:34 PM PDT 24
Finished Jul 13 04:45:58 PM PDT 24
Peak memory 220160 kb
Host smart-0ab1a250-8e4f-4454-8c81-541024faf68e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088343374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2088343374
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1096864559
Short name T213
Test name
Test status
Simulation time 688869827 ps
CPU time 8.35 seconds
Started Jul 13 04:44:49 PM PDT 24
Finished Jul 13 04:44:59 PM PDT 24
Peak memory 217032 kb
Host smart-25e712b0-acab-4bc6-97d4-60401c1a083f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096864559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1096864559
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3442108743
Short name T182
Test name
Test status
Simulation time 31436531138 ps
CPU time 375.16 seconds
Started Jul 13 04:44:44 PM PDT 24
Finished Jul 13 04:51:00 PM PDT 24
Peak memory 237980 kb
Host smart-78601b29-a792-46ef-ac76-96fdacb9cbda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442108743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3442108743
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3127640019
Short name T345
Test name
Test status
Simulation time 24569522069 ps
CPU time 57.3 seconds
Started Jul 13 04:44:43 PM PDT 24
Finished Jul 13 04:45:41 PM PDT 24
Peak memory 219352 kb
Host smart-02305f7c-fb2e-47b2-99be-78aa6ab2800d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127640019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3127640019
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2774451943
Short name T288
Test name
Test status
Simulation time 3679574656 ps
CPU time 30.76 seconds
Started Jul 13 04:44:45 PM PDT 24
Finished Jul 13 04:45:17 PM PDT 24
Peak memory 219356 kb
Host smart-1fc3f57c-7e3e-460d-8f39-5b18c1453e1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2774451943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2774451943
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2731396858
Short name T298
Test name
Test status
Simulation time 4702413090 ps
CPU time 56.12 seconds
Started Jul 13 04:44:47 PM PDT 24
Finished Jul 13 04:45:44 PM PDT 24
Peak memory 216476 kb
Host smart-2818097a-d34c-439f-b560-d1b1ff4ad397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731396858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2731396858
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3959503370
Short name T263
Test name
Test status
Simulation time 9914443630 ps
CPU time 50.2 seconds
Started Jul 13 04:44:46 PM PDT 24
Finished Jul 13 04:45:37 PM PDT 24
Peak memory 217724 kb
Host smart-a9d5cb21-6b33-4f80-834c-721b612199ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959503370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3959503370
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1939684906
Short name T68
Test name
Test status
Simulation time 718539580 ps
CPU time 8.48 seconds
Started Jul 13 04:44:46 PM PDT 24
Finished Jul 13 04:44:55 PM PDT 24
Peak memory 217096 kb
Host smart-14c1338f-8a4c-489a-a031-bb4cdb0a8d5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939684906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1939684906
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2028676117
Short name T327
Test name
Test status
Simulation time 36191163391 ps
CPU time 341.98 seconds
Started Jul 13 04:44:46 PM PDT 24
Finished Jul 13 04:50:30 PM PDT 24
Peak memory 225240 kb
Host smart-d95d02e2-a377-46a5-a7e4-155d5e80a2d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028676117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2028676117
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.160946286
Short name T320
Test name
Test status
Simulation time 1678195933 ps
CPU time 29.86 seconds
Started Jul 13 04:44:44 PM PDT 24
Finished Jul 13 04:45:15 PM PDT 24
Peak memory 219216 kb
Host smart-38a7db09-227e-42d2-bcdb-c639ccf98c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160946286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.160946286
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.756989301
Short name T138
Test name
Test status
Simulation time 345001538 ps
CPU time 10.37 seconds
Started Jul 13 04:44:44 PM PDT 24
Finished Jul 13 04:44:56 PM PDT 24
Peak memory 219220 kb
Host smart-843494b0-8f19-4d4c-b616-48a85ce3839a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=756989301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.756989301
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1995252961
Short name T303
Test name
Test status
Simulation time 3567143793 ps
CPU time 32 seconds
Started Jul 13 04:44:45 PM PDT 24
Finished Jul 13 04:45:17 PM PDT 24
Peak memory 216340 kb
Host smart-9efcf106-2b7d-4915-96a8-fa414cdf3d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995252961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1995252961
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.281985796
Short name T19
Test name
Test status
Simulation time 6608062531 ps
CPU time 65.51 seconds
Started Jul 13 04:44:43 PM PDT 24
Finished Jul 13 04:45:50 PM PDT 24
Peak memory 219344 kb
Host smart-cf98062b-de58-49d8-be1d-06baf5384ed9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281985796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.281985796
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.90507541
Short name T51
Test name
Test status
Simulation time 37328350578 ps
CPU time 752.21 seconds
Started Jul 13 04:44:44 PM PDT 24
Finished Jul 13 04:57:17 PM PDT 24
Peak memory 230872 kb
Host smart-39574487-d0c1-4058-a55d-b9f95a8ce156
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90507541 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.90507541
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.418575776
Short name T335
Test name
Test status
Simulation time 661576357 ps
CPU time 8.46 seconds
Started Jul 13 04:43:28 PM PDT 24
Finished Jul 13 04:43:39 PM PDT 24
Peak memory 216716 kb
Host smart-26030f11-8c21-4d2b-95d3-7af4d2044049
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418575776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.418575776
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.4217489984
Short name T316
Test name
Test status
Simulation time 252794239657 ps
CPU time 636.29 seconds
Started Jul 13 04:43:27 PM PDT 24
Finished Jul 13 04:54:06 PM PDT 24
Peak memory 234512 kb
Host smart-d7bad866-e8cf-4200-bd94-796f7f9171a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217489984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.4217489984
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.187775915
Short name T197
Test name
Test status
Simulation time 336039514 ps
CPU time 19.59 seconds
Started Jul 13 04:43:33 PM PDT 24
Finished Jul 13 04:43:53 PM PDT 24
Peak memory 219232 kb
Host smart-a2c7b639-3b50-4765-a56d-5d713c401198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187775915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.187775915
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.617026339
Short name T142
Test name
Test status
Simulation time 1618347640 ps
CPU time 18.89 seconds
Started Jul 13 04:44:49 PM PDT 24
Finished Jul 13 04:45:10 PM PDT 24
Peak memory 219236 kb
Host smart-92dbe763-043d-432d-b6b9-c79d6684b980
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=617026339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.617026339
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.705901728
Short name T240
Test name
Test status
Simulation time 9542754546 ps
CPU time 53.37 seconds
Started Jul 13 04:43:27 PM PDT 24
Finished Jul 13 04:44:23 PM PDT 24
Peak memory 217012 kb
Host smart-2ba201be-7fcc-40b2-9a2b-bae509db54d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705901728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.705901728
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3808218092
Short name T223
Test name
Test status
Simulation time 8474245857 ps
CPU time 118.14 seconds
Started Jul 13 04:43:27 PM PDT 24
Finished Jul 13 04:45:28 PM PDT 24
Peak memory 227524 kb
Host smart-161c3812-fb8a-48fa-a724-b2b158bae340
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808218092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3808218092
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2518765144
Short name T208
Test name
Test status
Simulation time 32633178232 ps
CPU time 19.92 seconds
Started Jul 13 04:44:50 PM PDT 24
Finished Jul 13 04:45:11 PM PDT 24
Peak memory 217052 kb
Host smart-1148c769-cef3-45d1-9b20-6bd62a6d2480
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518765144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2518765144
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2212085754
Short name T140
Test name
Test status
Simulation time 82188185811 ps
CPU time 738.68 seconds
Started Jul 13 04:43:30 PM PDT 24
Finished Jul 13 04:55:50 PM PDT 24
Peak memory 238644 kb
Host smart-b2ad4f3b-8c52-4678-b82c-9b4667f76838
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212085754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2212085754
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2131660534
Short name T99
Test name
Test status
Simulation time 1709966020 ps
CPU time 30.98 seconds
Started Jul 13 04:43:31 PM PDT 24
Finished Jul 13 04:44:03 PM PDT 24
Peak memory 219216 kb
Host smart-59067130-d53a-4c2f-89a7-a6c8154f5f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131660534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2131660534
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3114159563
Short name T31
Test name
Test status
Simulation time 12293424034 ps
CPU time 25.21 seconds
Started Jul 13 04:43:30 PM PDT 24
Finished Jul 13 04:43:57 PM PDT 24
Peak memory 219292 kb
Host smart-1c1f7eec-8b8e-4b73-84fd-77a43c3f4222
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3114159563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3114159563
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2238502364
Short name T168
Test name
Test status
Simulation time 8367452795 ps
CPU time 77.41 seconds
Started Jul 13 04:44:50 PM PDT 24
Finished Jul 13 04:46:09 PM PDT 24
Peak memory 216204 kb
Host smart-6504c288-f4c3-44e6-bedd-cd3bbb25f5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238502364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2238502364
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1857212469
Short name T193
Test name
Test status
Simulation time 12815867355 ps
CPU time 114.87 seconds
Started Jul 13 04:44:52 PM PDT 24
Finished Jul 13 04:46:47 PM PDT 24
Peak memory 220024 kb
Host smart-de4a5f16-8c23-4759-a4e0-6b7ca033be2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857212469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1857212469
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.921289301
Short name T314
Test name
Test status
Simulation time 10075342315 ps
CPU time 23.42 seconds
Started Jul 13 04:43:33 PM PDT 24
Finished Jul 13 04:43:57 PM PDT 24
Peak memory 213284 kb
Host smart-8b32457c-63b0-4f22-aa54-6a40fd9a3d20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921289301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.921289301
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1445011022
Short name T179
Test name
Test status
Simulation time 58639752453 ps
CPU time 731.61 seconds
Started Jul 13 04:43:28 PM PDT 24
Finished Jul 13 04:55:42 PM PDT 24
Peak memory 237996 kb
Host smart-492d3a5a-9e13-41a0-830f-b21135be2788
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445011022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1445011022
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3946598603
Short name T330
Test name
Test status
Simulation time 2299865930 ps
CPU time 26.93 seconds
Started Jul 13 04:43:30 PM PDT 24
Finished Jul 13 04:43:59 PM PDT 24
Peak memory 219312 kb
Host smart-72267c79-d57f-42c4-b345-5198526f3b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946598603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3946598603
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1391803585
Short name T262
Test name
Test status
Simulation time 693674343 ps
CPU time 10.35 seconds
Started Jul 13 04:43:30 PM PDT 24
Finished Jul 13 04:43:42 PM PDT 24
Peak memory 219244 kb
Host smart-a5f66a1c-329c-4e72-b3d2-bd47dd8b8eed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1391803585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1391803585
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.902520135
Short name T245
Test name
Test status
Simulation time 22973807743 ps
CPU time 79.54 seconds
Started Jul 13 04:44:49 PM PDT 24
Finished Jul 13 04:46:10 PM PDT 24
Peak memory 217364 kb
Host smart-8b8c3aa9-1f86-441c-a370-b45ca0d4fa75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902520135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.902520135
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1744330706
Short name T349
Test name
Test status
Simulation time 16113032440 ps
CPU time 148.93 seconds
Started Jul 13 04:44:50 PM PDT 24
Finished Jul 13 04:47:20 PM PDT 24
Peak memory 220724 kb
Host smart-a235184c-2dca-4a98-a3f3-3644c14c4127
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744330706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1744330706
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2762833567
Short name T98
Test name
Test status
Simulation time 570470191 ps
CPU time 8.35 seconds
Started Jul 13 04:43:35 PM PDT 24
Finished Jul 13 04:43:44 PM PDT 24
Peak memory 217020 kb
Host smart-6e9b8801-8674-4a6f-966b-2f83e74ba6cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762833567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2762833567
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1252221548
Short name T206
Test name
Test status
Simulation time 34151489790 ps
CPU time 413.6 seconds
Started Jul 13 04:43:33 PM PDT 24
Finished Jul 13 04:50:27 PM PDT 24
Peak memory 237080 kb
Host smart-607554b9-305e-4b9a-ae51-dde5a18af447
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252221548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1252221548
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.972402936
Short name T158
Test name
Test status
Simulation time 1013667123 ps
CPU time 23.01 seconds
Started Jul 13 04:43:38 PM PDT 24
Finished Jul 13 04:44:03 PM PDT 24
Peak memory 219264 kb
Host smart-a04317b4-8f2d-46b6-a3ef-2b3a96a59986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972402936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.972402936
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3676278064
Short name T331
Test name
Test status
Simulation time 11979508005 ps
CPU time 18.56 seconds
Started Jul 13 04:43:38 PM PDT 24
Finished Jul 13 04:43:58 PM PDT 24
Peak memory 219328 kb
Host smart-266e737f-4318-4062-bfe7-8194200532a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3676278064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3676278064
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1752565660
Short name T308
Test name
Test status
Simulation time 5595488903 ps
CPU time 51.63 seconds
Started Jul 13 04:43:38 PM PDT 24
Finished Jul 13 04:44:30 PM PDT 24
Peak memory 216212 kb
Host smart-fb1cc80a-9fa3-4a4a-b1f7-2a0c8b594a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752565660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1752565660
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3924622910
Short name T241
Test name
Test status
Simulation time 1489199074 ps
CPU time 19.82 seconds
Started Jul 13 04:43:37 PM PDT 24
Finished Jul 13 04:43:57 PM PDT 24
Peak memory 218732 kb
Host smart-c64e1eb0-522e-41b1-b54b-74339e0bf531
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924622910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3924622910
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.4011952515
Short name T152
Test name
Test status
Simulation time 2715211485 ps
CPU time 23.8 seconds
Started Jul 13 04:43:35 PM PDT 24
Finished Jul 13 04:43:59 PM PDT 24
Peak memory 217120 kb
Host smart-fe30b66e-0433-4cd8-a448-84629edae995
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011952515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.4011952515
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2321404456
Short name T201
Test name
Test status
Simulation time 92319363791 ps
CPU time 465.15 seconds
Started Jul 13 04:43:34 PM PDT 24
Finished Jul 13 04:51:20 PM PDT 24
Peak memory 239012 kb
Host smart-a75b6c4e-9421-4fa5-b880-5c611f164831
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321404456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2321404456
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.4263567574
Short name T147
Test name
Test status
Simulation time 1649181887 ps
CPU time 30.46 seconds
Started Jul 13 04:43:34 PM PDT 24
Finished Jul 13 04:44:05 PM PDT 24
Peak memory 219216 kb
Host smart-c535c02f-47a4-427b-95b8-07ffa0730f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263567574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.4263567574
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.36821338
Short name T271
Test name
Test status
Simulation time 176396323 ps
CPU time 10.58 seconds
Started Jul 13 04:43:39 PM PDT 24
Finished Jul 13 04:43:50 PM PDT 24
Peak memory 219244 kb
Host smart-1ecb27e8-67f2-4f92-9a2d-d8341b3c07c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=36821338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.36821338
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.730721695
Short name T215
Test name
Test status
Simulation time 5596512090 ps
CPU time 38.35 seconds
Started Jul 13 04:43:38 PM PDT 24
Finished Jul 13 04:44:18 PM PDT 24
Peak memory 217828 kb
Host smart-91ba004c-0c0c-479d-a54b-61010d02a6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730721695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.730721695
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3196234491
Short name T273
Test name
Test status
Simulation time 32539878439 ps
CPU time 76.83 seconds
Started Jul 13 04:43:38 PM PDT 24
Finished Jul 13 04:44:56 PM PDT 24
Peak memory 219160 kb
Host smart-6303b983-7db6-4b64-94d7-da01bbdb1443
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196234491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3196234491
Directory /workspace/9.rom_ctrl_stress_all/latest
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