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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.19 96.89 91.85 97.68 100.00 98.28 97.30 98.37


Total test records in report: 459
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T301 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.783337514 Jul 14 05:23:58 PM PDT 24 Jul 14 05:24:29 PM PDT 24 6582179566 ps
T302 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.119557382 Jul 14 05:24:04 PM PDT 24 Jul 14 05:27:46 PM PDT 24 13373530622 ps
T303 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3077466841 Jul 14 05:24:02 PM PDT 24 Jul 14 05:25:11 PM PDT 24 32146159783 ps
T304 /workspace/coverage/default/27.rom_ctrl_alert_test.3182068020 Jul 14 05:24:47 PM PDT 24 Jul 14 05:25:06 PM PDT 24 5917646515 ps
T305 /workspace/coverage/default/13.rom_ctrl_stress_all.1104257770 Jul 14 05:23:55 PM PDT 24 Jul 14 05:25:45 PM PDT 24 31809257894 ps
T306 /workspace/coverage/default/42.rom_ctrl_alert_test.1513621709 Jul 14 05:25:23 PM PDT 24 Jul 14 05:25:54 PM PDT 24 21200053270 ps
T46 /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.257880342 Jul 14 05:23:57 PM PDT 24 Jul 14 06:02:17 PM PDT 24 122943017227 ps
T307 /workspace/coverage/default/8.rom_ctrl_alert_test.2841708400 Jul 14 05:23:56 PM PDT 24 Jul 14 05:24:04 PM PDT 24 167319867 ps
T308 /workspace/coverage/default/5.rom_ctrl_stress_all.3410970166 Jul 14 05:23:46 PM PDT 24 Jul 14 05:26:13 PM PDT 24 16133316450 ps
T309 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3990184751 Jul 14 05:25:42 PM PDT 24 Jul 14 05:26:03 PM PDT 24 1807114448 ps
T310 /workspace/coverage/default/23.rom_ctrl_stress_all.4132916030 Jul 14 05:24:26 PM PDT 24 Jul 14 05:25:11 PM PDT 24 555975573 ps
T311 /workspace/coverage/default/15.rom_ctrl_smoke.46708566 Jul 14 05:24:05 PM PDT 24 Jul 14 05:24:59 PM PDT 24 15156002921 ps
T312 /workspace/coverage/default/14.rom_ctrl_stress_all.807041176 Jul 14 05:23:58 PM PDT 24 Jul 14 05:24:50 PM PDT 24 3870406904 ps
T313 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2026192383 Jul 14 05:24:02 PM PDT 24 Jul 14 05:32:02 PM PDT 24 34248373839 ps
T314 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2020226906 Jul 14 05:25:37 PM PDT 24 Jul 14 05:25:49 PM PDT 24 187289092 ps
T315 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3501025574 Jul 14 05:23:45 PM PDT 24 Jul 14 05:26:04 PM PDT 24 2638189695 ps
T316 /workspace/coverage/default/15.rom_ctrl_alert_test.4215397714 Jul 14 05:24:02 PM PDT 24 Jul 14 05:24:32 PM PDT 24 14565011208 ps
T317 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2250658023 Jul 14 05:23:43 PM PDT 24 Jul 14 05:23:59 PM PDT 24 705183810 ps
T318 /workspace/coverage/default/7.rom_ctrl_alert_test.3249727869 Jul 14 05:23:44 PM PDT 24 Jul 14 05:23:54 PM PDT 24 170753988 ps
T319 /workspace/coverage/default/33.rom_ctrl_alert_test.383674428 Jul 14 05:25:01 PM PDT 24 Jul 14 05:25:25 PM PDT 24 10199683467 ps
T320 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3206875730 Jul 14 05:23:58 PM PDT 24 Jul 14 05:28:08 PM PDT 24 5209995518 ps
T321 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1471990258 Jul 14 05:25:00 PM PDT 24 Jul 14 05:25:53 PM PDT 24 42273081534 ps
T322 /workspace/coverage/default/7.rom_ctrl_smoke.1126589322 Jul 14 05:23:43 PM PDT 24 Jul 14 05:25:00 PM PDT 24 7199403008 ps
T323 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2340163325 Jul 14 05:25:19 PM PDT 24 Jul 14 05:25:44 PM PDT 24 4153309546 ps
T324 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3747840677 Jul 14 05:23:40 PM PDT 24 Jul 14 05:30:36 PM PDT 24 32726022983 ps
T325 /workspace/coverage/default/47.rom_ctrl_alert_test.797047825 Jul 14 05:25:49 PM PDT 24 Jul 14 05:25:59 PM PDT 24 403964401 ps
T326 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3120026244 Jul 14 05:25:02 PM PDT 24 Jul 14 05:25:30 PM PDT 24 3234058563 ps
T327 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1152314072 Jul 14 05:25:13 PM PDT 24 Jul 14 05:25:33 PM PDT 24 1712637090 ps
T328 /workspace/coverage/default/4.rom_ctrl_smoke.3482315443 Jul 14 05:23:45 PM PDT 24 Jul 14 05:24:20 PM PDT 24 1748386979 ps
T329 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3762431532 Jul 14 05:23:52 PM PDT 24 Jul 14 05:24:20 PM PDT 24 3165722489 ps
T330 /workspace/coverage/default/36.rom_ctrl_alert_test.2104738619 Jul 14 05:25:06 PM PDT 24 Jul 14 05:25:35 PM PDT 24 11564775333 ps
T331 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2991803638 Jul 14 05:25:12 PM PDT 24 Jul 14 05:31:12 PM PDT 24 10241043416 ps
T332 /workspace/coverage/default/1.rom_ctrl_stress_all.2386572592 Jul 14 05:23:39 PM PDT 24 Jul 14 05:25:21 PM PDT 24 45347554081 ps
T333 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.270859162 Jul 14 05:24:35 PM PDT 24 Jul 14 05:24:58 PM PDT 24 1975401321 ps
T334 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.738998404 Jul 14 05:24:02 PM PDT 24 Jul 14 05:24:53 PM PDT 24 20519361899 ps
T335 /workspace/coverage/default/29.rom_ctrl_stress_all.2607053900 Jul 14 05:24:48 PM PDT 24 Jul 14 05:25:53 PM PDT 24 18473310280 ps
T336 /workspace/coverage/default/32.rom_ctrl_smoke.3307869702 Jul 14 05:24:58 PM PDT 24 Jul 14 05:26:01 PM PDT 24 29936398716 ps
T337 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3787774685 Jul 14 05:25:54 PM PDT 24 Jul 14 05:26:13 PM PDT 24 676177796 ps
T338 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.654338358 Jul 14 05:23:57 PM PDT 24 Jul 14 05:24:26 PM PDT 24 3186790353 ps
T101 /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.598051176 Jul 14 05:25:18 PM PDT 24 Jul 14 05:45:59 PM PDT 24 31411214930 ps
T339 /workspace/coverage/default/29.rom_ctrl_smoke.3050144330 Jul 14 05:24:47 PM PDT 24 Jul 14 05:25:47 PM PDT 24 26816056565 ps
T340 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3580787792 Jul 14 05:25:08 PM PDT 24 Jul 14 05:26:17 PM PDT 24 16789633100 ps
T341 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2692507763 Jul 14 05:24:06 PM PDT 24 Jul 14 05:24:34 PM PDT 24 12094684514 ps
T342 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2108330832 Jul 14 05:23:34 PM PDT 24 Jul 14 05:24:09 PM PDT 24 3827411522 ps
T343 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1279601890 Jul 14 05:23:56 PM PDT 24 Jul 14 05:24:16 PM PDT 24 2354683380 ps
T344 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1885724384 Jul 14 05:24:12 PM PDT 24 Jul 14 05:24:42 PM PDT 24 1539441347 ps
T345 /workspace/coverage/default/3.rom_ctrl_stress_all.1894832492 Jul 14 05:23:43 PM PDT 24 Jul 14 05:24:47 PM PDT 24 30082536246 ps
T346 /workspace/coverage/default/4.rom_ctrl_stress_all.1773297893 Jul 14 05:23:47 PM PDT 24 Jul 14 05:25:23 PM PDT 24 19598176004 ps
T347 /workspace/coverage/default/34.rom_ctrl_alert_test.3026528795 Jul 14 05:25:09 PM PDT 24 Jul 14 05:25:46 PM PDT 24 71402227837 ps
T348 /workspace/coverage/default/15.rom_ctrl_stress_all.797692707 Jul 14 05:24:02 PM PDT 24 Jul 14 05:24:17 PM PDT 24 4580429772 ps
T349 /workspace/coverage/default/41.rom_ctrl_alert_test.2792776275 Jul 14 05:25:24 PM PDT 24 Jul 14 05:25:42 PM PDT 24 1440656715 ps
T350 /workspace/coverage/default/30.rom_ctrl_alert_test.3280174132 Jul 14 05:25:00 PM PDT 24 Jul 14 05:25:23 PM PDT 24 4786981213 ps
T351 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1392767960 Jul 14 05:25:01 PM PDT 24 Jul 14 05:25:44 PM PDT 24 15714524401 ps
T352 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.357858699 Jul 14 05:24:45 PM PDT 24 Jul 14 05:32:17 PM PDT 24 154569528908 ps
T353 /workspace/coverage/default/0.rom_ctrl_stress_all.2138503934 Jul 14 05:23:32 PM PDT 24 Jul 14 05:24:48 PM PDT 24 17041724847 ps
T354 /workspace/coverage/default/2.rom_ctrl_smoke.580684562 Jul 14 05:23:37 PM PDT 24 Jul 14 05:24:12 PM PDT 24 2058710950 ps
T355 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.877817028 Jul 14 05:25:41 PM PDT 24 Jul 14 05:30:50 PM PDT 24 306403406287 ps
T356 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2521289010 Jul 14 05:25:00 PM PDT 24 Jul 14 05:25:11 PM PDT 24 349392059 ps
T357 /workspace/coverage/default/42.rom_ctrl_smoke.3466770873 Jul 14 05:25:26 PM PDT 24 Jul 14 05:26:03 PM PDT 24 11628060256 ps
T358 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.528824959 Jul 14 05:24:13 PM PDT 24 Jul 14 05:25:21 PM PDT 24 16984879088 ps
T359 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1246149181 Jul 14 05:23:49 PM PDT 24 Jul 14 05:38:00 PM PDT 24 191911281843 ps
T360 /workspace/coverage/default/35.rom_ctrl_alert_test.2969197925 Jul 14 05:25:08 PM PDT 24 Jul 14 05:25:38 PM PDT 24 3354990864 ps
T29 /workspace/coverage/default/0.rom_ctrl_sec_cm.2466399314 Jul 14 05:23:35 PM PDT 24 Jul 14 05:25:30 PM PDT 24 456577258 ps
T361 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3052321191 Jul 14 05:25:30 PM PDT 24 Jul 14 05:25:56 PM PDT 24 2737635286 ps
T362 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.4034147619 Jul 14 05:24:45 PM PDT 24 Jul 14 05:25:35 PM PDT 24 5656932622 ps
T59 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3885245553 Jul 14 05:26:33 PM PDT 24 Jul 14 05:26:55 PM PDT 24 4052369276 ps
T60 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2172013171 Jul 14 05:26:57 PM PDT 24 Jul 14 05:27:25 PM PDT 24 7197295794 ps
T61 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2062500887 Jul 14 05:27:03 PM PDT 24 Jul 14 05:30:22 PM PDT 24 48285556302 ps
T363 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1405051964 Jul 14 05:26:13 PM PDT 24 Jul 14 05:26:44 PM PDT 24 17375060717 ps
T364 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1136806142 Jul 14 05:26:36 PM PDT 24 Jul 14 05:26:47 PM PDT 24 710360637 ps
T66 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.466940475 Jul 14 05:26:09 PM PDT 24 Jul 14 05:26:30 PM PDT 24 2271932234 ps
T55 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1007406086 Jul 14 05:26:37 PM PDT 24 Jul 14 05:28:08 PM PDT 24 1783271551 ps
T67 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2014696359 Jul 14 05:26:12 PM PDT 24 Jul 14 05:26:31 PM PDT 24 1710958771 ps
T68 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.417209712 Jul 14 05:26:24 PM PDT 24 Jul 14 05:27:50 PM PDT 24 16422432265 ps
T90 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.25040044 Jul 14 05:26:01 PM PDT 24 Jul 14 05:26:27 PM PDT 24 11447820481 ps
T91 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3995524210 Jul 14 05:27:04 PM PDT 24 Jul 14 05:27:30 PM PDT 24 2970893186 ps
T365 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1170256847 Jul 14 05:26:15 PM PDT 24 Jul 14 05:26:49 PM PDT 24 34801153300 ps
T366 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.200507765 Jul 14 05:26:59 PM PDT 24 Jul 14 05:27:33 PM PDT 24 14650236407 ps
T367 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.102970728 Jul 14 05:26:45 PM PDT 24 Jul 14 05:27:22 PM PDT 24 73999031398 ps
T368 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3884597599 Jul 14 05:26:31 PM PDT 24 Jul 14 05:27:08 PM PDT 24 6383663758 ps
T369 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3499266066 Jul 14 05:26:20 PM PDT 24 Jul 14 05:26:46 PM PDT 24 5703753779 ps
T69 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1082685957 Jul 14 05:26:41 PM PDT 24 Jul 14 05:26:58 PM PDT 24 1169147572 ps
T95 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3813777208 Jul 14 05:27:00 PM PDT 24 Jul 14 05:29:22 PM PDT 24 68469049931 ps
T370 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1048568132 Jul 14 05:26:31 PM PDT 24 Jul 14 05:27:02 PM PDT 24 14427526948 ps
T96 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1881396782 Jul 14 05:26:18 PM PDT 24 Jul 14 05:26:37 PM PDT 24 604854853 ps
T92 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2855828227 Jul 14 05:26:52 PM PDT 24 Jul 14 05:27:13 PM PDT 24 2623249160 ps
T93 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.952371204 Jul 14 05:26:58 PM PDT 24 Jul 14 05:27:17 PM PDT 24 3252219704 ps
T371 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3196305809 Jul 14 05:27:02 PM PDT 24 Jul 14 05:27:26 PM PDT 24 2734275639 ps
T372 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2109921092 Jul 14 05:26:11 PM PDT 24 Jul 14 05:26:42 PM PDT 24 11777857453 ps
T373 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1420526346 Jul 14 05:26:57 PM PDT 24 Jul 14 05:27:32 PM PDT 24 17797515285 ps
T56 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.171431152 Jul 14 05:26:56 PM PDT 24 Jul 14 05:29:48 PM PDT 24 17507014224 ps
T70 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.887738133 Jul 14 05:26:51 PM PDT 24 Jul 14 05:29:22 PM PDT 24 61457475780 ps
T374 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1498931170 Jul 14 05:26:50 PM PDT 24 Jul 14 05:27:22 PM PDT 24 8297286806 ps
T375 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1647743671 Jul 14 05:26:36 PM PDT 24 Jul 14 05:26:48 PM PDT 24 447706155 ps
T57 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2504929732 Jul 14 05:26:01 PM PDT 24 Jul 14 05:28:37 PM PDT 24 1245400855 ps
T94 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3259003951 Jul 14 05:26:17 PM PDT 24 Jul 14 05:26:30 PM PDT 24 358126190 ps
T71 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3871193101 Jul 14 05:26:43 PM PDT 24 Jul 14 05:27:04 PM PDT 24 2062296440 ps
T72 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2717256073 Jul 14 05:25:55 PM PDT 24 Jul 14 05:26:33 PM PDT 24 2836496283 ps
T73 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.4057256898 Jul 14 05:26:56 PM PDT 24 Jul 14 05:27:04 PM PDT 24 688787441 ps
T376 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4000108149 Jul 14 05:27:00 PM PDT 24 Jul 14 05:27:22 PM PDT 24 8927488286 ps
T377 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3833632762 Jul 14 05:26:14 PM PDT 24 Jul 14 05:26:36 PM PDT 24 4987410869 ps
T378 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2496081596 Jul 14 05:26:58 PM PDT 24 Jul 14 05:28:18 PM PDT 24 31182454323 ps
T379 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1663001835 Jul 14 05:26:14 PM PDT 24 Jul 14 05:27:38 PM PDT 24 8822676421 ps
T74 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1022828686 Jul 14 05:26:32 PM PDT 24 Jul 14 05:26:57 PM PDT 24 11117738534 ps
T380 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.208680720 Jul 14 05:26:23 PM PDT 24 Jul 14 05:26:49 PM PDT 24 38614267863 ps
T381 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2654216801 Jul 14 05:26:43 PM PDT 24 Jul 14 05:27:15 PM PDT 24 5021008844 ps
T382 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3480973897 Jul 14 05:26:26 PM PDT 24 Jul 14 05:26:43 PM PDT 24 12294052260 ps
T112 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1488228820 Jul 14 05:26:06 PM PDT 24 Jul 14 05:27:41 PM PDT 24 4490334625 ps
T383 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3002259565 Jul 14 05:26:26 PM PDT 24 Jul 14 05:26:38 PM PDT 24 721750781 ps
T384 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.4227878997 Jul 14 05:26:00 PM PDT 24 Jul 14 05:26:18 PM PDT 24 1395721111 ps
T385 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2830008823 Jul 14 05:26:52 PM PDT 24 Jul 14 05:29:49 PM PDT 24 24539481326 ps
T386 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2729152972 Jul 14 05:26:31 PM PDT 24 Jul 14 05:26:42 PM PDT 24 254712085 ps
T387 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2919471475 Jul 14 05:26:07 PM PDT 24 Jul 14 05:26:28 PM PDT 24 7478500106 ps
T388 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1344483376 Jul 14 05:26:43 PM PDT 24 Jul 14 05:27:04 PM PDT 24 5369949495 ps
T389 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4244184873 Jul 14 05:26:12 PM PDT 24 Jul 14 05:26:21 PM PDT 24 438254657 ps
T105 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2003740020 Jul 14 05:26:32 PM PDT 24 Jul 14 05:29:08 PM PDT 24 1211546847 ps
T110 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3860637951 Jul 14 05:26:13 PM PDT 24 Jul 14 05:27:55 PM PDT 24 3975143573 ps
T390 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1984044984 Jul 14 05:26:42 PM PDT 24 Jul 14 05:27:00 PM PDT 24 7134122344 ps
T391 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2197460585 Jul 14 05:25:59 PM PDT 24 Jul 14 05:26:08 PM PDT 24 339300378 ps
T106 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.417134932 Jul 14 05:26:32 PM PDT 24 Jul 14 05:28:16 PM PDT 24 8844745318 ps
T392 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.438662615 Jul 14 05:25:59 PM PDT 24 Jul 14 05:26:14 PM PDT 24 3426423506 ps
T393 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.211497640 Jul 14 05:26:30 PM PDT 24 Jul 14 05:27:57 PM PDT 24 15903868322 ps
T394 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1397575365 Jul 14 05:26:57 PM PDT 24 Jul 14 05:27:09 PM PDT 24 1718664328 ps
T78 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1216446861 Jul 14 05:26:05 PM PDT 24 Jul 14 05:26:35 PM PDT 24 2063785127 ps
T395 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4074255796 Jul 14 05:26:58 PM PDT 24 Jul 14 05:27:20 PM PDT 24 15794935541 ps
T396 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1293401457 Jul 14 05:26:06 PM PDT 24 Jul 14 05:26:34 PM PDT 24 3129748588 ps
T397 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1145963607 Jul 14 05:26:26 PM PDT 24 Jul 14 05:27:02 PM PDT 24 3712943036 ps
T398 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1497652181 Jul 14 05:26:06 PM PDT 24 Jul 14 05:26:31 PM PDT 24 2863182736 ps
T399 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3350392579 Jul 14 05:26:30 PM PDT 24 Jul 14 05:26:59 PM PDT 24 2818662373 ps
T400 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2956871888 Jul 14 05:26:11 PM PDT 24 Jul 14 05:26:27 PM PDT 24 2059402837 ps
T401 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1417483355 Jul 14 05:26:20 PM PDT 24 Jul 14 05:26:46 PM PDT 24 2938733880 ps
T402 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1850628872 Jul 14 05:26:52 PM PDT 24 Jul 14 05:27:17 PM PDT 24 2593943021 ps
T403 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.393235245 Jul 14 05:26:19 PM PDT 24 Jul 14 05:26:27 PM PDT 24 473404833 ps
T404 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1523394451 Jul 14 05:26:14 PM PDT 24 Jul 14 05:26:22 PM PDT 24 717556125 ps
T405 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4249385581 Jul 14 05:26:01 PM PDT 24 Jul 14 05:26:37 PM PDT 24 8595325936 ps
T406 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.800826540 Jul 14 05:26:51 PM PDT 24 Jul 14 05:27:21 PM PDT 24 15086523647 ps
T407 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.44863439 Jul 14 05:26:07 PM PDT 24 Jul 14 05:26:40 PM PDT 24 3452648128 ps
T408 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2833424135 Jul 14 05:26:23 PM PDT 24 Jul 14 05:26:58 PM PDT 24 8146178124 ps
T409 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.492993218 Jul 14 05:26:20 PM PDT 24 Jul 14 05:26:35 PM PDT 24 899951948 ps
T410 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.345748086 Jul 14 05:26:13 PM PDT 24 Jul 14 05:26:34 PM PDT 24 2110590790 ps
T411 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2415622352 Jul 14 05:26:45 PM PDT 24 Jul 14 05:26:55 PM PDT 24 368802622 ps
T412 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2906514337 Jul 14 05:26:39 PM PDT 24 Jul 14 05:27:11 PM PDT 24 3694105518 ps
T413 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3713235360 Jul 14 05:26:41 PM PDT 24 Jul 14 05:27:10 PM PDT 24 14729163315 ps
T414 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2024573861 Jul 14 05:26:03 PM PDT 24 Jul 14 05:26:37 PM PDT 24 3856585888 ps
T79 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3809150133 Jul 14 05:26:07 PM PDT 24 Jul 14 05:26:58 PM PDT 24 1672996044 ps
T415 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.898100973 Jul 14 05:26:12 PM PDT 24 Jul 14 05:26:30 PM PDT 24 5320632913 ps
T108 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2583066184 Jul 14 05:26:50 PM PDT 24 Jul 14 05:29:37 PM PDT 24 2626817975 ps
T109 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.902194556 Jul 14 05:26:18 PM PDT 24 Jul 14 05:27:49 PM PDT 24 4438975869 ps
T107 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2525866608 Jul 14 05:26:24 PM PDT 24 Jul 14 05:27:56 PM PDT 24 7771721834 ps
T416 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.921708084 Jul 14 05:26:13 PM PDT 24 Jul 14 05:26:43 PM PDT 24 18056938653 ps
T417 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1305625701 Jul 14 05:26:50 PM PDT 24 Jul 14 05:27:03 PM PDT 24 170794466 ps
T418 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1064559593 Jul 14 05:26:57 PM PDT 24 Jul 14 05:27:21 PM PDT 24 2480773997 ps
T80 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3083873230 Jul 14 05:26:42 PM PDT 24 Jul 14 05:28:27 PM PDT 24 7980719280 ps
T419 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1842564409 Jul 14 05:26:17 PM PDT 24 Jul 14 05:26:32 PM PDT 24 2307745182 ps
T420 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3448017878 Jul 14 05:25:53 PM PDT 24 Jul 14 05:26:05 PM PDT 24 167367129 ps
T421 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2078474813 Jul 14 05:26:42 PM PDT 24 Jul 14 05:26:52 PM PDT 24 182735796 ps
T422 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2963058591 Jul 14 05:26:20 PM PDT 24 Jul 14 05:26:49 PM PDT 24 3457918234 ps
T423 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3956429820 Jul 14 05:26:18 PM PDT 24 Jul 14 05:26:35 PM PDT 24 4677941653 ps
T81 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3514222049 Jul 14 05:26:14 PM PDT 24 Jul 14 05:26:29 PM PDT 24 1042775708 ps
T424 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3675050225 Jul 14 05:26:24 PM PDT 24 Jul 14 05:26:43 PM PDT 24 1799068000 ps
T425 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2103920113 Jul 14 05:26:00 PM PDT 24 Jul 14 05:26:28 PM PDT 24 3462162070 ps
T426 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3763840032 Jul 14 05:26:27 PM PDT 24 Jul 14 05:26:56 PM PDT 24 6966619968 ps
T82 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1526437502 Jul 14 05:26:51 PM PDT 24 Jul 14 05:27:23 PM PDT 24 4052586824 ps
T427 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1587906530 Jul 14 05:26:57 PM PDT 24 Jul 14 05:27:07 PM PDT 24 187779831 ps
T428 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1547347625 Jul 14 05:27:07 PM PDT 24 Jul 14 05:27:33 PM PDT 24 2061587414 ps
T111 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1380927186 Jul 14 05:26:38 PM PDT 24 Jul 14 05:29:16 PM PDT 24 5540505162 ps
T429 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1119981772 Jul 14 05:26:32 PM PDT 24 Jul 14 05:29:18 PM PDT 24 18089924107 ps
T102 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.220330589 Jul 14 05:26:58 PM PDT 24 Jul 14 05:29:37 PM PDT 24 1039225099 ps
T83 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1160005609 Jul 14 05:27:04 PM PDT 24 Jul 14 05:27:17 PM PDT 24 2045088368 ps
T430 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3039379605 Jul 14 05:26:42 PM PDT 24 Jul 14 05:28:21 PM PDT 24 13430963301 ps
T113 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1945982428 Jul 14 05:26:51 PM PDT 24 Jul 14 05:28:15 PM PDT 24 1664829940 ps
T431 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3947201847 Jul 14 05:26:33 PM PDT 24 Jul 14 05:28:16 PM PDT 24 27012283292 ps
T84 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.4028232271 Jul 14 05:26:12 PM PDT 24 Jul 14 05:26:28 PM PDT 24 2273703349 ps
T432 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1966701805 Jul 14 05:26:20 PM PDT 24 Jul 14 05:26:40 PM PDT 24 7849586612 ps
T433 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.4211558598 Jul 14 05:26:32 PM PDT 24 Jul 14 05:26:44 PM PDT 24 1682677242 ps
T434 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3274996315 Jul 14 05:26:20 PM PDT 24 Jul 14 05:27:35 PM PDT 24 2588164149 ps
T435 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3864603037 Jul 14 05:26:58 PM PDT 24 Jul 14 05:27:22 PM PDT 24 8903924277 ps
T103 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.796852951 Jul 14 05:26:59 PM PDT 24 Jul 14 05:29:38 PM PDT 24 7135709873 ps
T436 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.948177139 Jul 14 05:26:38 PM PDT 24 Jul 14 05:26:55 PM PDT 24 1241787091 ps
T437 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1180588522 Jul 14 05:26:43 PM PDT 24 Jul 14 05:27:10 PM PDT 24 4646952491 ps
T438 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3181470678 Jul 14 05:26:09 PM PDT 24 Jul 14 05:26:20 PM PDT 24 496157825 ps
T439 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2010019205 Jul 14 05:26:12 PM PDT 24 Jul 14 05:26:32 PM PDT 24 5535924542 ps
T85 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1509506087 Jul 14 05:26:27 PM PDT 24 Jul 14 05:28:37 PM PDT 24 24153259547 ps
T440 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1663637349 Jul 14 05:26:52 PM PDT 24 Jul 14 05:27:22 PM PDT 24 38190515076 ps
T441 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1852110663 Jul 14 05:27:00 PM PDT 24 Jul 14 05:27:27 PM PDT 24 10494825550 ps
T442 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2998645344 Jul 14 05:26:00 PM PDT 24 Jul 14 05:27:54 PM PDT 24 37591461385 ps
T443 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3886868658 Jul 14 05:26:30 PM PDT 24 Jul 14 05:26:55 PM PDT 24 26329548601 ps
T114 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.578137997 Jul 14 05:26:24 PM PDT 24 Jul 14 05:29:22 PM PDT 24 4128107617 ps
T444 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3946201970 Jul 14 05:26:07 PM PDT 24 Jul 14 05:26:31 PM PDT 24 2700481696 ps
T445 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3404327190 Jul 14 05:26:53 PM PDT 24 Jul 14 05:27:07 PM PDT 24 907833047 ps
T446 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1756166555 Jul 14 05:25:59 PM PDT 24 Jul 14 05:26:11 PM PDT 24 510554633 ps
T104 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1453391223 Jul 14 05:26:00 PM PDT 24 Jul 14 05:28:52 PM PDT 24 7846441014 ps
T87 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3596177245 Jul 14 05:26:40 PM PDT 24 Jul 14 05:28:29 PM PDT 24 17164965842 ps
T447 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.127459365 Jul 14 05:26:52 PM PDT 24 Jul 14 05:27:21 PM PDT 24 8890202219 ps
T448 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2030430524 Jul 14 05:26:06 PM PDT 24 Jul 14 05:26:15 PM PDT 24 689472231 ps
T449 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3021765976 Jul 14 05:26:33 PM PDT 24 Jul 14 05:27:07 PM PDT 24 3543882153 ps
T450 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3020604345 Jul 14 05:26:12 PM PDT 24 Jul 14 05:26:28 PM PDT 24 704718862 ps
T451 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3131467821 Jul 14 05:26:20 PM PDT 24 Jul 14 05:26:38 PM PDT 24 2047428952 ps
T452 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3370705519 Jul 14 05:26:21 PM PDT 24 Jul 14 05:28:01 PM PDT 24 31168997685 ps
T88 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.156782251 Jul 14 05:27:00 PM PDT 24 Jul 14 05:28:31 PM PDT 24 9233352506 ps
T453 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3622037844 Jul 14 05:25:59 PM PDT 24 Jul 14 05:26:24 PM PDT 24 8115832496 ps
T86 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.888182165 Jul 14 05:26:37 PM PDT 24 Jul 14 05:27:15 PM PDT 24 2629123821 ps
T454 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.560399911 Jul 14 05:26:43 PM PDT 24 Jul 14 05:28:12 PM PDT 24 1406557730 ps
T455 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2542589525 Jul 14 05:26:23 PM PDT 24 Jul 14 05:26:42 PM PDT 24 7082092541 ps
T456 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3920368867 Jul 14 05:26:00 PM PDT 24 Jul 14 05:26:16 PM PDT 24 1916605246 ps
T457 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.720613020 Jul 14 05:26:15 PM PDT 24 Jul 14 05:26:40 PM PDT 24 10411159923 ps
T89 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.4157004230 Jul 14 05:26:13 PM PDT 24 Jul 14 05:26:41 PM PDT 24 3421845594 ps
T458 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4057207611 Jul 14 05:26:18 PM PDT 24 Jul 14 05:26:35 PM PDT 24 5486452781 ps
T459 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2835934132 Jul 14 05:27:03 PM PDT 24 Jul 14 05:29:56 PM PDT 24 13583620152 ps

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1748697470
Short name T7
Test name
Test status
Simulation time 12797924422 ps
CPU time 229.87 seconds
Started Jul 14 05:23:34 PM PDT 24
Finished Jul 14 05:27:25 PM PDT 24
Peak memory 229780 kb
Host smart-345900db-85ff-49bc-bf53-b53fc316e845
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748697470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1748697470
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.4071187653
Short name T11
Test name
Test status
Simulation time 195238332673 ps
CPU time 1703.29 seconds
Started Jul 14 05:25:56 PM PDT 24
Finished Jul 14 05:54:20 PM PDT 24
Peak memory 237772 kb
Host smart-16641b9d-4a8e-4c2b-beff-b2db4013f15c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071187653 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.4071187653
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1982942788
Short name T3
Test name
Test status
Simulation time 5277954597 ps
CPU time 46.2 seconds
Started Jul 14 05:25:43 PM PDT 24
Finished Jul 14 05:26:30 PM PDT 24
Peak memory 216632 kb
Host smart-9032cda8-3920-4362-94ab-d2f06d7445e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982942788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1982942788
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3166388231
Short name T31
Test name
Test status
Simulation time 8347782818 ps
CPU time 343.53 seconds
Started Jul 14 05:24:09 PM PDT 24
Finished Jul 14 05:29:53 PM PDT 24
Peak memory 235016 kb
Host smart-92bae34c-866c-44f0-ac61-5f52a66a8656
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166388231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3166388231
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2504929732
Short name T57
Test name
Test status
Simulation time 1245400855 ps
CPU time 155 seconds
Started Jul 14 05:26:01 PM PDT 24
Finished Jul 14 05:28:37 PM PDT 24
Peak memory 213896 kb
Host smart-e594c7ba-4e47-4095-ba0a-62725446958b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504929732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2504929732
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1435472667
Short name T23
Test name
Test status
Simulation time 941593522 ps
CPU time 229.42 seconds
Started Jul 14 05:23:47 PM PDT 24
Finished Jul 14 05:27:37 PM PDT 24
Peak memory 237924 kb
Host smart-329e8c5c-7061-4e21-86d1-8eba1bc82b06
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435472667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1435472667
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.417209712
Short name T68
Test name
Test status
Simulation time 16422432265 ps
CPU time 85.81 seconds
Started Jul 14 05:26:24 PM PDT 24
Finished Jul 14 05:27:50 PM PDT 24
Peak memory 213756 kb
Host smart-6418ebc5-b542-46b3-a719-8764d2cc24ac
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417209712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.417209712
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1453391223
Short name T104
Test name
Test status
Simulation time 7846441014 ps
CPU time 171.51 seconds
Started Jul 14 05:26:00 PM PDT 24
Finished Jul 14 05:28:52 PM PDT 24
Peak memory 214240 kb
Host smart-43ebe772-8862-4b8b-8530-c9dcf622723d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453391223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1453391223
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3090866336
Short name T48
Test name
Test status
Simulation time 42914517167 ps
CPU time 24.13 seconds
Started Jul 14 05:25:37 PM PDT 24
Finished Jul 14 05:26:02 PM PDT 24
Peak memory 217540 kb
Host smart-75eac192-9e0f-45ca-b930-c31c5958e8bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090866336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3090866336
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.796852951
Short name T103
Test name
Test status
Simulation time 7135709873 ps
CPU time 158.74 seconds
Started Jul 14 05:26:59 PM PDT 24
Finished Jul 14 05:29:38 PM PDT 24
Peak memory 214228 kb
Host smart-fb595725-7598-414b-8a0a-70262230c1ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796852951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.796852951
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3977686905
Short name T16
Test name
Test status
Simulation time 6197980706 ps
CPU time 77.9 seconds
Started Jul 14 05:25:44 PM PDT 24
Finished Jul 14 05:27:03 PM PDT 24
Peak memory 219292 kb
Host smart-0bff3032-e250-476b-a649-24711d08b03c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977686905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3977686905
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3071926872
Short name T38
Test name
Test status
Simulation time 4258602497 ps
CPU time 44.26 seconds
Started Jul 14 05:25:12 PM PDT 24
Finished Jul 14 05:25:57 PM PDT 24
Peak memory 219288 kb
Host smart-a83382e6-3f7e-4a3a-83b4-0aad7f050f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071926872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3071926872
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2773275788
Short name T27
Test name
Test status
Simulation time 4711252381 ps
CPU time 19.95 seconds
Started Jul 14 05:23:40 PM PDT 24
Finished Jul 14 05:24:01 PM PDT 24
Peak memory 219248 kb
Host smart-d77f5711-7901-4a8e-a825-171e6268f0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773275788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2773275788
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1914456247
Short name T18
Test name
Test status
Simulation time 4954038641 ps
CPU time 354.31 seconds
Started Jul 14 05:24:29 PM PDT 24
Finished Jul 14 05:30:23 PM PDT 24
Peak memory 241916 kb
Host smart-5b36a3c0-0cfe-4ce6-a9e1-838291b2c0d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914456247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1914456247
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2502824769
Short name T34
Test name
Test status
Simulation time 36386443552 ps
CPU time 275.96 seconds
Started Jul 14 05:23:36 PM PDT 24
Finished Jul 14 05:28:13 PM PDT 24
Peak memory 237896 kb
Host smart-378ca0b2-eb9e-40a4-95f0-d1e22711fc86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502824769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2502824769
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1119981772
Short name T429
Test name
Test status
Simulation time 18089924107 ps
CPU time 164.95 seconds
Started Jul 14 05:26:32 PM PDT 24
Finished Jul 14 05:29:18 PM PDT 24
Peak memory 215432 kb
Host smart-4d2ff1c8-d631-4d6e-83d5-68fadb80ad04
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119981772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1119981772
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1945982428
Short name T113
Test name
Test status
Simulation time 1664829940 ps
CPU time 83.69 seconds
Started Jul 14 05:26:51 PM PDT 24
Finished Jul 14 05:28:15 PM PDT 24
Peak memory 213632 kb
Host smart-9e52fce4-7853-474e-9676-afcba55034d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945982428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1945982428
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2492982805
Short name T165
Test name
Test status
Simulation time 12812618840 ps
CPU time 67.88 seconds
Started Jul 14 05:24:02 PM PDT 24
Finished Jul 14 05:25:10 PM PDT 24
Peak memory 216852 kb
Host smart-4fc55947-4f03-404f-a51c-93b7cebe84cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492982805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2492982805
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1756166555
Short name T446
Test name
Test status
Simulation time 510554633 ps
CPU time 11.85 seconds
Started Jul 14 05:25:59 PM PDT 24
Finished Jul 14 05:26:11 PM PDT 24
Peak memory 210716 kb
Host smart-24b35d98-dc79-47c8-a4fc-8213fe7881e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756166555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1756166555
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2197460585
Short name T391
Test name
Test status
Simulation time 339300378 ps
CPU time 8.73 seconds
Started Jul 14 05:25:59 PM PDT 24
Finished Jul 14 05:26:08 PM PDT 24
Peak memory 210880 kb
Host smart-047c80ee-9774-49a6-ab6c-e25f23db87b4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197460585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2197460585
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3622037844
Short name T453
Test name
Test status
Simulation time 8115832496 ps
CPU time 24.51 seconds
Started Jul 14 05:25:59 PM PDT 24
Finished Jul 14 05:26:24 PM PDT 24
Peak memory 211852 kb
Host smart-ec9845a4-66cf-4163-9b11-a466c4bcf69f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622037844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3622037844
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4249385581
Short name T405
Test name
Test status
Simulation time 8595325936 ps
CPU time 34.76 seconds
Started Jul 14 05:26:01 PM PDT 24
Finished Jul 14 05:26:37 PM PDT 24
Peak memory 217812 kb
Host smart-265e5ee9-d853-4ef5-876e-4b2ea6d47b5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249385581 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.4249385581
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.438662615
Short name T392
Test name
Test status
Simulation time 3426423506 ps
CPU time 14.2 seconds
Started Jul 14 05:25:59 PM PDT 24
Finished Jul 14 05:26:14 PM PDT 24
Peak memory 210720 kb
Host smart-ce458e7c-9014-4ec2-a8f4-32808479d221
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438662615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.438662615
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3920368867
Short name T456
Test name
Test status
Simulation time 1916605246 ps
CPU time 15.35 seconds
Started Jul 14 05:26:00 PM PDT 24
Finished Jul 14 05:26:16 PM PDT 24
Peak memory 210496 kb
Host smart-b3c770f0-3bcc-44f1-924e-7b9a1fcd9871
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920368867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3920368867
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.4227878997
Short name T384
Test name
Test status
Simulation time 1395721111 ps
CPU time 17.2 seconds
Started Jul 14 05:26:00 PM PDT 24
Finished Jul 14 05:26:18 PM PDT 24
Peak memory 210480 kb
Host smart-a82be0e3-9d1d-441c-82c0-c03068cd95fb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227878997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.4227878997
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2717256073
Short name T72
Test name
Test status
Simulation time 2836496283 ps
CPU time 37.56 seconds
Started Jul 14 05:25:55 PM PDT 24
Finished Jul 14 05:26:33 PM PDT 24
Peak memory 213708 kb
Host smart-bb922e2c-e9d4-4370-a2ef-99a038312d4a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717256073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2717256073
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.25040044
Short name T90
Test name
Test status
Simulation time 11447820481 ps
CPU time 24.92 seconds
Started Jul 14 05:26:01 PM PDT 24
Finished Jul 14 05:26:27 PM PDT 24
Peak memory 212572 kb
Host smart-42dcfe1c-918f-4758-9786-0d779df8676b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25040044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_same_csr_outstanding.25040044
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3448017878
Short name T420
Test name
Test status
Simulation time 167367129 ps
CPU time 11.15 seconds
Started Jul 14 05:25:53 PM PDT 24
Finished Jul 14 05:26:05 PM PDT 24
Peak memory 218968 kb
Host smart-47c2b57b-8376-4908-b2cb-c98eaeec07df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448017878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3448017878
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2919471475
Short name T387
Test name
Test status
Simulation time 7478500106 ps
CPU time 19.65 seconds
Started Jul 14 05:26:07 PM PDT 24
Finished Jul 14 05:26:28 PM PDT 24
Peak memory 211964 kb
Host smart-c5af0340-82d2-4103-9572-6343bff9df16
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919471475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2919471475
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1497652181
Short name T398
Test name
Test status
Simulation time 2863182736 ps
CPU time 24.96 seconds
Started Jul 14 05:26:06 PM PDT 24
Finished Jul 14 05:26:31 PM PDT 24
Peak memory 210776 kb
Host smart-5b220ef2-14dc-4b08-9dd1-ec3c22157aa1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497652181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1497652181
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1216446861
Short name T78
Test name
Test status
Simulation time 2063785127 ps
CPU time 29.08 seconds
Started Jul 14 05:26:05 PM PDT 24
Finished Jul 14 05:26:35 PM PDT 24
Peak memory 210716 kb
Host smart-dd8680b0-349e-4254-9144-ae743ae37e98
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216446861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1216446861
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3946201970
Short name T444
Test name
Test status
Simulation time 2700481696 ps
CPU time 23.35 seconds
Started Jul 14 05:26:07 PM PDT 24
Finished Jul 14 05:26:31 PM PDT 24
Peak memory 217788 kb
Host smart-b78796ac-e165-4c9d-9078-6a4e226c1cf0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946201970 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3946201970
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.466940475
Short name T66
Test name
Test status
Simulation time 2271932234 ps
CPU time 21.23 seconds
Started Jul 14 05:26:09 PM PDT 24
Finished Jul 14 05:26:30 PM PDT 24
Peak memory 211972 kb
Host smart-40945ba4-b58f-4835-9b88-1f754636c7ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466940475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.466940475
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3181470678
Short name T438
Test name
Test status
Simulation time 496157825 ps
CPU time 11.41 seconds
Started Jul 14 05:26:09 PM PDT 24
Finished Jul 14 05:26:20 PM PDT 24
Peak memory 210432 kb
Host smart-29bb576b-eb03-4a03-9b40-e51290658deb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181470678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3181470678
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2103920113
Short name T425
Test name
Test status
Simulation time 3462162070 ps
CPU time 28.4 seconds
Started Jul 14 05:26:00 PM PDT 24
Finished Jul 14 05:26:28 PM PDT 24
Peak memory 210520 kb
Host smart-b1293af5-c5f6-49b4-be2f-83b147125ae6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103920113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2103920113
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2998645344
Short name T442
Test name
Test status
Simulation time 37591461385 ps
CPU time 113.84 seconds
Started Jul 14 05:26:00 PM PDT 24
Finished Jul 14 05:27:54 PM PDT 24
Peak memory 213920 kb
Host smart-296b4d1c-18ed-4e5e-98cb-dd776acc5dc8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998645344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2998645344
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1293401457
Short name T396
Test name
Test status
Simulation time 3129748588 ps
CPU time 27.29 seconds
Started Jul 14 05:26:06 PM PDT 24
Finished Jul 14 05:26:34 PM PDT 24
Peak memory 212200 kb
Host smart-02626fb0-6264-4251-9cc7-c097bfaee579
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293401457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1293401457
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2024573861
Short name T414
Test name
Test status
Simulation time 3856585888 ps
CPU time 33.85 seconds
Started Jul 14 05:26:03 PM PDT 24
Finished Jul 14 05:26:37 PM PDT 24
Peak memory 218364 kb
Host smart-a587fbf3-71f4-46c7-ad83-d605482ac142
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024573861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2024573861
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1136806142
Short name T364
Test name
Test status
Simulation time 710360637 ps
CPU time 10.91 seconds
Started Jul 14 05:26:36 PM PDT 24
Finished Jul 14 05:26:47 PM PDT 24
Peak memory 216472 kb
Host smart-e748c8d9-b4f2-40f8-913b-d6db7938182e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136806142 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1136806142
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.948177139
Short name T436
Test name
Test status
Simulation time 1241787091 ps
CPU time 16.35 seconds
Started Jul 14 05:26:38 PM PDT 24
Finished Jul 14 05:26:55 PM PDT 24
Peak memory 211636 kb
Host smart-efb7924d-dddf-4a97-b086-cc7d42a44458
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948177139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.948177139
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1344483376
Short name T388
Test name
Test status
Simulation time 5369949495 ps
CPU time 20.69 seconds
Started Jul 14 05:26:43 PM PDT 24
Finished Jul 14 05:27:04 PM PDT 24
Peak memory 212704 kb
Host smart-7bcd5270-0a6a-4881-a928-5b7909063297
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344483376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1344483376
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3350392579
Short name T399
Test name
Test status
Simulation time 2818662373 ps
CPU time 28.58 seconds
Started Jul 14 05:26:30 PM PDT 24
Finished Jul 14 05:26:59 PM PDT 24
Peak memory 219248 kb
Host smart-79d78e1b-c5a3-455f-9d54-940523fe0a22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350392579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3350392579
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1007406086
Short name T55
Test name
Test status
Simulation time 1783271551 ps
CPU time 89.98 seconds
Started Jul 14 05:26:37 PM PDT 24
Finished Jul 14 05:28:08 PM PDT 24
Peak memory 213336 kb
Host smart-4409a397-c809-4259-af0c-df07e3e13ef6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007406086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1007406086
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2415622352
Short name T411
Test name
Test status
Simulation time 368802622 ps
CPU time 9.25 seconds
Started Jul 14 05:26:45 PM PDT 24
Finished Jul 14 05:26:55 PM PDT 24
Peak memory 216676 kb
Host smart-c2555e80-c87f-412e-9e7b-613c91c8858c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415622352 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2415622352
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2906514337
Short name T412
Test name
Test status
Simulation time 3694105518 ps
CPU time 31.66 seconds
Started Jul 14 05:26:39 PM PDT 24
Finished Jul 14 05:27:11 PM PDT 24
Peak memory 210692 kb
Host smart-633b4bc3-021a-45ac-b128-023c84350607
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906514337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2906514337
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3596177245
Short name T87
Test name
Test status
Simulation time 17164965842 ps
CPU time 108.83 seconds
Started Jul 14 05:26:40 PM PDT 24
Finished Jul 14 05:28:29 PM PDT 24
Peak memory 215336 kb
Host smart-d1aaa463-fea5-4be6-b5a5-5d24b9ddade4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596177245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3596177245
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2654216801
Short name T381
Test name
Test status
Simulation time 5021008844 ps
CPU time 31.42 seconds
Started Jul 14 05:26:43 PM PDT 24
Finished Jul 14 05:27:15 PM PDT 24
Peak memory 212152 kb
Host smart-edd77c65-8697-4e9f-b4a7-aa9f014e07d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654216801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2654216801
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1647743671
Short name T375
Test name
Test status
Simulation time 447706155 ps
CPU time 11.43 seconds
Started Jul 14 05:26:36 PM PDT 24
Finished Jul 14 05:26:48 PM PDT 24
Peak memory 218860 kb
Host smart-a915545e-d8fc-42fb-b6df-010c97510f49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647743671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1647743671
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1380927186
Short name T111
Test name
Test status
Simulation time 5540505162 ps
CPU time 157.71 seconds
Started Jul 14 05:26:38 PM PDT 24
Finished Jul 14 05:29:16 PM PDT 24
Peak memory 214276 kb
Host smart-cac88d8b-ea0f-4e11-9e33-59ce0a6ae605
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380927186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1380927186
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2078474813
Short name T421
Test name
Test status
Simulation time 182735796 ps
CPU time 9.11 seconds
Started Jul 14 05:26:42 PM PDT 24
Finished Jul 14 05:26:52 PM PDT 24
Peak memory 216076 kb
Host smart-6bf316e8-3084-4452-a6cc-f91fb6195be0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078474813 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2078474813
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3871193101
Short name T71
Test name
Test status
Simulation time 2062296440 ps
CPU time 20.93 seconds
Started Jul 14 05:26:43 PM PDT 24
Finished Jul 14 05:27:04 PM PDT 24
Peak memory 211496 kb
Host smart-96863072-f68c-4853-9c1c-f03a7885d249
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871193101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3871193101
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.888182165
Short name T86
Test name
Test status
Simulation time 2629123821 ps
CPU time 37.6 seconds
Started Jul 14 05:26:37 PM PDT 24
Finished Jul 14 05:27:15 PM PDT 24
Peak memory 213776 kb
Host smart-2d9499f8-d6e8-4dd6-9b2f-59d194b6f131
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888182165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.888182165
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3713235360
Short name T413
Test name
Test status
Simulation time 14729163315 ps
CPU time 28.66 seconds
Started Jul 14 05:26:41 PM PDT 24
Finished Jul 14 05:27:10 PM PDT 24
Peak memory 212212 kb
Host smart-e5904640-2a57-4e3d-bf47-32eed3e0394f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713235360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3713235360
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1180588522
Short name T437
Test name
Test status
Simulation time 4646952491 ps
CPU time 26.99 seconds
Started Jul 14 05:26:43 PM PDT 24
Finished Jul 14 05:27:10 PM PDT 24
Peak memory 217668 kb
Host smart-035c3d99-f39e-4856-9874-2e19faa653fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180588522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1180588522
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.560399911
Short name T454
Test name
Test status
Simulation time 1406557730 ps
CPU time 88.01 seconds
Started Jul 14 05:26:43 PM PDT 24
Finished Jul 14 05:28:12 PM PDT 24
Peak memory 213552 kb
Host smart-7ebedfdd-a508-4839-a939-55a5b9fb3c9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560399911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.560399911
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.800826540
Short name T406
Test name
Test status
Simulation time 15086523647 ps
CPU time 30.1 seconds
Started Jul 14 05:26:51 PM PDT 24
Finished Jul 14 05:27:21 PM PDT 24
Peak memory 218440 kb
Host smart-a9d9cad8-dc5c-45be-89f3-21559fc8dc23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800826540 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.800826540
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1984044984
Short name T390
Test name
Test status
Simulation time 7134122344 ps
CPU time 17.72 seconds
Started Jul 14 05:26:42 PM PDT 24
Finished Jul 14 05:27:00 PM PDT 24
Peak memory 212024 kb
Host smart-8113a8af-1286-47aa-8fd9-7a5453c43db5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984044984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1984044984
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3083873230
Short name T80
Test name
Test status
Simulation time 7980719280 ps
CPU time 104.26 seconds
Started Jul 14 05:26:42 PM PDT 24
Finished Jul 14 05:28:27 PM PDT 24
Peak memory 215292 kb
Host smart-24d5db87-ac3e-4f95-8d49-9bf27f4694cc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083873230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3083873230
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1082685957
Short name T69
Test name
Test status
Simulation time 1169147572 ps
CPU time 15.84 seconds
Started Jul 14 05:26:41 PM PDT 24
Finished Jul 14 05:26:58 PM PDT 24
Peak memory 211164 kb
Host smart-77d436d7-be0b-40ce-8acb-604a5d0bab9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082685957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1082685957
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.102970728
Short name T367
Test name
Test status
Simulation time 73999031398 ps
CPU time 36.82 seconds
Started Jul 14 05:26:45 PM PDT 24
Finished Jul 14 05:27:22 PM PDT 24
Peak memory 218660 kb
Host smart-b6d82da6-659b-4393-bad5-fd988e5d88cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102970728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.102970728
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3039379605
Short name T430
Test name
Test status
Simulation time 13430963301 ps
CPU time 99.41 seconds
Started Jul 14 05:26:42 PM PDT 24
Finished Jul 14 05:28:21 PM PDT 24
Peak memory 213748 kb
Host smart-f60f3ed9-72a6-4684-9393-044ac706ed57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039379605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3039379605
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1498931170
Short name T374
Test name
Test status
Simulation time 8297286806 ps
CPU time 32.11 seconds
Started Jul 14 05:26:50 PM PDT 24
Finished Jul 14 05:27:22 PM PDT 24
Peak memory 218068 kb
Host smart-7578c973-9aa1-4a94-97b2-3e232bf9ff5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498931170 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1498931170
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1526437502
Short name T82
Test name
Test status
Simulation time 4052586824 ps
CPU time 31.59 seconds
Started Jul 14 05:26:51 PM PDT 24
Finished Jul 14 05:27:23 PM PDT 24
Peak memory 211584 kb
Host smart-c5e451c3-fa83-45bb-a627-5959fb3b6687
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526437502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1526437502
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.887738133
Short name T70
Test name
Test status
Simulation time 61457475780 ps
CPU time 150.1 seconds
Started Jul 14 05:26:51 PM PDT 24
Finished Jul 14 05:29:22 PM PDT 24
Peak memory 218756 kb
Host smart-3ab4b4c7-0f5c-4ee1-b6c9-57e5612653c6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887738133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa
ssthru_mem_tl_intg_err.887738133
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1663637349
Short name T440
Test name
Test status
Simulation time 38190515076 ps
CPU time 29.03 seconds
Started Jul 14 05:26:52 PM PDT 24
Finished Jul 14 05:27:22 PM PDT 24
Peak memory 212780 kb
Host smart-83a8d78b-c49b-44ff-bb32-a61cf3600b39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663637349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1663637349
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1305625701
Short name T417
Test name
Test status
Simulation time 170794466 ps
CPU time 12.42 seconds
Started Jul 14 05:26:50 PM PDT 24
Finished Jul 14 05:27:03 PM PDT 24
Peak memory 217196 kb
Host smart-c99cf375-39cd-4660-9dbe-69389523b3a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305625701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1305625701
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1850628872
Short name T402
Test name
Test status
Simulation time 2593943021 ps
CPU time 24.71 seconds
Started Jul 14 05:26:52 PM PDT 24
Finished Jul 14 05:27:17 PM PDT 24
Peak memory 218804 kb
Host smart-325ba869-aef6-4e44-ab84-d1c57b16e40c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850628872 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1850628872
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3404327190
Short name T445
Test name
Test status
Simulation time 907833047 ps
CPU time 14.23 seconds
Started Jul 14 05:26:53 PM PDT 24
Finished Jul 14 05:27:07 PM PDT 24
Peak memory 211164 kb
Host smart-3c80be10-9d47-46fa-8cd1-02fe3c09afa1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404327190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3404327190
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2830008823
Short name T385
Test name
Test status
Simulation time 24539481326 ps
CPU time 176.59 seconds
Started Jul 14 05:26:52 PM PDT 24
Finished Jul 14 05:29:49 PM PDT 24
Peak memory 215276 kb
Host smart-e0f81ce0-ff10-42b1-ae1d-a1141a17f0a7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830008823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2830008823
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2855828227
Short name T92
Test name
Test status
Simulation time 2623249160 ps
CPU time 20.18 seconds
Started Jul 14 05:26:52 PM PDT 24
Finished Jul 14 05:27:13 PM PDT 24
Peak memory 212480 kb
Host smart-e9c317d4-a86e-470d-8353-05c28fffd740
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855828227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2855828227
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.127459365
Short name T447
Test name
Test status
Simulation time 8890202219 ps
CPU time 28.31 seconds
Started Jul 14 05:26:52 PM PDT 24
Finished Jul 14 05:27:21 PM PDT 24
Peak memory 218800 kb
Host smart-b7399f58-31a2-4372-9314-bbf5bff41a41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127459365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.127459365
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2583066184
Short name T108
Test name
Test status
Simulation time 2626817975 ps
CPU time 166.69 seconds
Started Jul 14 05:26:50 PM PDT 24
Finished Jul 14 05:29:37 PM PDT 24
Peak memory 213896 kb
Host smart-8a997aeb-2bc8-4ee4-848f-6460b2bede1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583066184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2583066184
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4074255796
Short name T395
Test name
Test status
Simulation time 15794935541 ps
CPU time 21.18 seconds
Started Jul 14 05:26:58 PM PDT 24
Finished Jul 14 05:27:20 PM PDT 24
Peak memory 216876 kb
Host smart-fad6a81b-3df2-47d0-8955-e2849be9f8b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074255796 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.4074255796
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2172013171
Short name T60
Test name
Test status
Simulation time 7197295794 ps
CPU time 27.55 seconds
Started Jul 14 05:26:57 PM PDT 24
Finished Jul 14 05:27:25 PM PDT 24
Peak memory 211944 kb
Host smart-6d3d4213-76dd-465a-8174-9a64651dd445
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172013171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2172013171
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3813777208
Short name T95
Test name
Test status
Simulation time 68469049931 ps
CPU time 141.84 seconds
Started Jul 14 05:27:00 PM PDT 24
Finished Jul 14 05:29:22 PM PDT 24
Peak memory 213824 kb
Host smart-ec0baa3b-85f6-4090-8141-d8d911dbf9aa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813777208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3813777208
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.4057256898
Short name T73
Test name
Test status
Simulation time 688787441 ps
CPU time 7.74 seconds
Started Jul 14 05:26:56 PM PDT 24
Finished Jul 14 05:27:04 PM PDT 24
Peak memory 211076 kb
Host smart-e1ff4c6c-963a-409c-859b-ec48cb2ff7bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057256898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.4057256898
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1852110663
Short name T441
Test name
Test status
Simulation time 10494825550 ps
CPU time 26.94 seconds
Started Jul 14 05:27:00 PM PDT 24
Finished Jul 14 05:27:27 PM PDT 24
Peak memory 217480 kb
Host smart-318996b0-04d5-4d8b-846c-f4c2b016489e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852110663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1852110663
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.171431152
Short name T56
Test name
Test status
Simulation time 17507014224 ps
CPU time 170.68 seconds
Started Jul 14 05:26:56 PM PDT 24
Finished Jul 14 05:29:48 PM PDT 24
Peak memory 214276 kb
Host smart-1ff9a34e-2492-4cd7-bf38-802b11070925
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171431152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.171431152
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1587906530
Short name T427
Test name
Test status
Simulation time 187779831 ps
CPU time 9.19 seconds
Started Jul 14 05:26:57 PM PDT 24
Finished Jul 14 05:27:07 PM PDT 24
Peak memory 216824 kb
Host smart-c518e730-b984-4c11-bda6-680fefe0bac0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587906530 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1587906530
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1420526346
Short name T373
Test name
Test status
Simulation time 17797515285 ps
CPU time 33.79 seconds
Started Jul 14 05:26:57 PM PDT 24
Finished Jul 14 05:27:32 PM PDT 24
Peak memory 212068 kb
Host smart-1cd800b5-7a25-4276-82b5-7e6f6c574381
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420526346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1420526346
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2496081596
Short name T378
Test name
Test status
Simulation time 31182454323 ps
CPU time 78.63 seconds
Started Jul 14 05:26:58 PM PDT 24
Finished Jul 14 05:28:18 PM PDT 24
Peak memory 213836 kb
Host smart-4cb34757-c690-4665-9041-018045fc4acb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496081596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2496081596
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.952371204
Short name T93
Test name
Test status
Simulation time 3252219704 ps
CPU time 18.03 seconds
Started Jul 14 05:26:58 PM PDT 24
Finished Jul 14 05:27:17 PM PDT 24
Peak memory 212076 kb
Host smart-81768d6c-8f75-4965-80e9-09ea8cb1a472
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952371204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.952371204
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3864603037
Short name T435
Test name
Test status
Simulation time 8903924277 ps
CPU time 23.15 seconds
Started Jul 14 05:26:58 PM PDT 24
Finished Jul 14 05:27:22 PM PDT 24
Peak memory 218560 kb
Host smart-7ba3c2e7-2333-4dc2-b586-c341dd9ec01b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864603037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3864603037
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4000108149
Short name T376
Test name
Test status
Simulation time 8927488286 ps
CPU time 21.44 seconds
Started Jul 14 05:27:00 PM PDT 24
Finished Jul 14 05:27:22 PM PDT 24
Peak memory 217192 kb
Host smart-f4530fe7-9b08-40eb-b8ef-ac4ba627bb90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000108149 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.4000108149
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1397575365
Short name T394
Test name
Test status
Simulation time 1718664328 ps
CPU time 11.2 seconds
Started Jul 14 05:26:57 PM PDT 24
Finished Jul 14 05:27:09 PM PDT 24
Peak memory 210608 kb
Host smart-c4439d82-6c6f-4927-ab35-85f99511ee47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397575365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1397575365
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.156782251
Short name T88
Test name
Test status
Simulation time 9233352506 ps
CPU time 89.8 seconds
Started Jul 14 05:27:00 PM PDT 24
Finished Jul 14 05:28:31 PM PDT 24
Peak memory 213820 kb
Host smart-2fe594ec-5a90-4d81-b71e-564f94449559
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156782251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pa
ssthru_mem_tl_intg_err.156782251
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1064559593
Short name T418
Test name
Test status
Simulation time 2480773997 ps
CPU time 23.22 seconds
Started Jul 14 05:26:57 PM PDT 24
Finished Jul 14 05:27:21 PM PDT 24
Peak memory 212420 kb
Host smart-99910d47-8ecd-482d-9c08-c0e1be70c9c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064559593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1064559593
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.200507765
Short name T366
Test name
Test status
Simulation time 14650236407 ps
CPU time 34.26 seconds
Started Jul 14 05:26:59 PM PDT 24
Finished Jul 14 05:27:33 PM PDT 24
Peak memory 217560 kb
Host smart-bfe12cf8-884d-4a52-b6ba-b5387bace3dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200507765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.200507765
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.220330589
Short name T102
Test name
Test status
Simulation time 1039225099 ps
CPU time 158.96 seconds
Started Jul 14 05:26:58 PM PDT 24
Finished Jul 14 05:29:37 PM PDT 24
Peak memory 213776 kb
Host smart-e5abec61-b3d5-4107-a623-2123c554fe3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220330589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.220330589
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3196305809
Short name T371
Test name
Test status
Simulation time 2734275639 ps
CPU time 23.77 seconds
Started Jul 14 05:27:02 PM PDT 24
Finished Jul 14 05:27:26 PM PDT 24
Peak memory 217468 kb
Host smart-9aa609db-572b-4860-98ca-a9fd36cfd8f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196305809 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3196305809
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1160005609
Short name T83
Test name
Test status
Simulation time 2045088368 ps
CPU time 11.91 seconds
Started Jul 14 05:27:04 PM PDT 24
Finished Jul 14 05:27:17 PM PDT 24
Peak memory 210664 kb
Host smart-1cad10ba-b77a-4608-aaf2-016ca8f43ba3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160005609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1160005609
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2062500887
Short name T61
Test name
Test status
Simulation time 48285556302 ps
CPU time 198.7 seconds
Started Jul 14 05:27:03 PM PDT 24
Finished Jul 14 05:30:22 PM PDT 24
Peak memory 214732 kb
Host smart-4f524f62-fe03-446b-b141-4f87d11a8d41
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062500887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2062500887
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3995524210
Short name T91
Test name
Test status
Simulation time 2970893186 ps
CPU time 25.6 seconds
Started Jul 14 05:27:04 PM PDT 24
Finished Jul 14 05:27:30 PM PDT 24
Peak memory 212052 kb
Host smart-1bbc2b1a-ff01-4fe5-a957-66df455c27dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995524210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3995524210
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1547347625
Short name T428
Test name
Test status
Simulation time 2061587414 ps
CPU time 26.08 seconds
Started Jul 14 05:27:07 PM PDT 24
Finished Jul 14 05:27:33 PM PDT 24
Peak memory 216164 kb
Host smart-6c482fd3-ea18-4574-b025-e3bc881d0432
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547347625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1547347625
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2835934132
Short name T459
Test name
Test status
Simulation time 13583620152 ps
CPU time 172.06 seconds
Started Jul 14 05:27:03 PM PDT 24
Finished Jul 14 05:29:56 PM PDT 24
Peak memory 214260 kb
Host smart-0a7643e2-5b42-4002-ae29-3e7c9e6b371c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835934132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2835934132
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3514222049
Short name T81
Test name
Test status
Simulation time 1042775708 ps
CPU time 14.35 seconds
Started Jul 14 05:26:14 PM PDT 24
Finished Jul 14 05:26:29 PM PDT 24
Peak memory 210688 kb
Host smart-f8352e3e-1916-4bbc-ac2e-9b40d3d65a3f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514222049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3514222049
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2010019205
Short name T439
Test name
Test status
Simulation time 5535924542 ps
CPU time 18.99 seconds
Started Jul 14 05:26:12 PM PDT 24
Finished Jul 14 05:26:32 PM PDT 24
Peak memory 210752 kb
Host smart-25eaa0c5-8e7b-4aaa-a0ce-b570e3a21014
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010019205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2010019205
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3020604345
Short name T450
Test name
Test status
Simulation time 704718862 ps
CPU time 15.63 seconds
Started Jul 14 05:26:12 PM PDT 24
Finished Jul 14 05:26:28 PM PDT 24
Peak memory 211932 kb
Host smart-23da347a-0bf2-48e6-9a57-4098d91d443d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020604345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3020604345
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4244184873
Short name T389
Test name
Test status
Simulation time 438254657 ps
CPU time 8.41 seconds
Started Jul 14 05:26:12 PM PDT 24
Finished Jul 14 05:26:21 PM PDT 24
Peak memory 213936 kb
Host smart-4916daf1-da14-4fb8-9e74-cb013cc4264e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244184873 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.4244184873
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.4157004230
Short name T89
Test name
Test status
Simulation time 3421845594 ps
CPU time 27.57 seconds
Started Jul 14 05:26:13 PM PDT 24
Finished Jul 14 05:26:41 PM PDT 24
Peak memory 211640 kb
Host smart-0814dc29-84fb-4402-bdd3-4ee17d0e7670
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157004230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.4157004230
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1170256847
Short name T365
Test name
Test status
Simulation time 34801153300 ps
CPU time 33.84 seconds
Started Jul 14 05:26:15 PM PDT 24
Finished Jul 14 05:26:49 PM PDT 24
Peak memory 210912 kb
Host smart-3c95faf2-e301-4e45-a610-483e5e521c36
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170256847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1170256847
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2030430524
Short name T448
Test name
Test status
Simulation time 689472231 ps
CPU time 8.12 seconds
Started Jul 14 05:26:06 PM PDT 24
Finished Jul 14 05:26:15 PM PDT 24
Peak memory 210556 kb
Host smart-ec0f05d8-611d-4570-bc8f-2805323f8360
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030430524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2030430524
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3809150133
Short name T79
Test name
Test status
Simulation time 1672996044 ps
CPU time 50.59 seconds
Started Jul 14 05:26:07 PM PDT 24
Finished Jul 14 05:26:58 PM PDT 24
Peak memory 213812 kb
Host smart-3092d971-53db-4def-90ef-6d900ebe16cc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809150133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3809150133
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3833632762
Short name T377
Test name
Test status
Simulation time 4987410869 ps
CPU time 21.63 seconds
Started Jul 14 05:26:14 PM PDT 24
Finished Jul 14 05:26:36 PM PDT 24
Peak memory 212268 kb
Host smart-91cbb84c-aae4-46cb-9dc9-1c89d888bb47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833632762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3833632762
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.44863439
Short name T407
Test name
Test status
Simulation time 3452648128 ps
CPU time 32.79 seconds
Started Jul 14 05:26:07 PM PDT 24
Finished Jul 14 05:26:40 PM PDT 24
Peak memory 218588 kb
Host smart-67ccc7c9-b207-4b41-b3aa-d4c2b992d9d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44863439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.44863439
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1488228820
Short name T112
Test name
Test status
Simulation time 4490334625 ps
CPU time 94.25 seconds
Started Jul 14 05:26:06 PM PDT 24
Finished Jul 14 05:27:41 PM PDT 24
Peak memory 213820 kb
Host smart-707373d9-dc78-491e-bb5c-6b08a84cb45a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488228820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1488228820
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2014696359
Short name T67
Test name
Test status
Simulation time 1710958771 ps
CPU time 18.65 seconds
Started Jul 14 05:26:12 PM PDT 24
Finished Jul 14 05:26:31 PM PDT 24
Peak memory 210940 kb
Host smart-45b01423-2543-44ff-bcb8-3bb5276bd65f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014696359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2014696359
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.4028232271
Short name T84
Test name
Test status
Simulation time 2273703349 ps
CPU time 16.19 seconds
Started Jul 14 05:26:12 PM PDT 24
Finished Jul 14 05:26:28 PM PDT 24
Peak memory 210704 kb
Host smart-37be39c9-0798-4040-a0bd-1deb5bfae002
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028232271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.4028232271
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2109921092
Short name T372
Test name
Test status
Simulation time 11777857453 ps
CPU time 30.79 seconds
Started Jul 14 05:26:11 PM PDT 24
Finished Jul 14 05:26:42 PM PDT 24
Peak memory 212208 kb
Host smart-decb3141-38ad-4c81-af6a-8225891f9428
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109921092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2109921092
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1405051964
Short name T363
Test name
Test status
Simulation time 17375060717 ps
CPU time 30.88 seconds
Started Jul 14 05:26:13 PM PDT 24
Finished Jul 14 05:26:44 PM PDT 24
Peak memory 218032 kb
Host smart-b290a41a-3857-459e-9218-b657b7e0ad76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405051964 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1405051964
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.345748086
Short name T410
Test name
Test status
Simulation time 2110590790 ps
CPU time 20.97 seconds
Started Jul 14 05:26:13 PM PDT 24
Finished Jul 14 05:26:34 PM PDT 24
Peak memory 211992 kb
Host smart-3530f558-251a-412c-ab94-911eee955861
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345748086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.345748086
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1523394451
Short name T404
Test name
Test status
Simulation time 717556125 ps
CPU time 8.18 seconds
Started Jul 14 05:26:14 PM PDT 24
Finished Jul 14 05:26:22 PM PDT 24
Peak memory 210536 kb
Host smart-7439c1ad-0091-49af-bf1c-b87683f69b6d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523394451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1523394451
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2956871888
Short name T400
Test name
Test status
Simulation time 2059402837 ps
CPU time 15.27 seconds
Started Jul 14 05:26:11 PM PDT 24
Finished Jul 14 05:26:27 PM PDT 24
Peak memory 210428 kb
Host smart-3efa545f-8b95-4db6-9a29-a3ff1055eaea
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956871888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2956871888
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1663001835
Short name T379
Test name
Test status
Simulation time 8822676421 ps
CPU time 82.97 seconds
Started Jul 14 05:26:14 PM PDT 24
Finished Jul 14 05:27:38 PM PDT 24
Peak memory 213720 kb
Host smart-a4bed54a-472f-4cf6-89f5-2a2ae677bfd0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663001835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1663001835
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.921708084
Short name T416
Test name
Test status
Simulation time 18056938653 ps
CPU time 29.4 seconds
Started Jul 14 05:26:13 PM PDT 24
Finished Jul 14 05:26:43 PM PDT 24
Peak memory 212264 kb
Host smart-a3d35409-984f-4081-ae76-063ac711e054
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921708084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.921708084
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.898100973
Short name T415
Test name
Test status
Simulation time 5320632913 ps
CPU time 18.14 seconds
Started Jul 14 05:26:12 PM PDT 24
Finished Jul 14 05:26:30 PM PDT 24
Peak memory 218788 kb
Host smart-74d708d8-6be4-4b34-8c59-5c26e31344d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898100973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.898100973
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3860637951
Short name T110
Test name
Test status
Simulation time 3975143573 ps
CPU time 101.22 seconds
Started Jul 14 05:26:13 PM PDT 24
Finished Jul 14 05:27:55 PM PDT 24
Peak memory 213468 kb
Host smart-d75226d6-7d7f-4a6e-aad6-b110bf12f487
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860637951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3860637951
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1966701805
Short name T432
Test name
Test status
Simulation time 7849586612 ps
CPU time 18.61 seconds
Started Jul 14 05:26:20 PM PDT 24
Finished Jul 14 05:26:40 PM PDT 24
Peak memory 211968 kb
Host smart-9553c8e5-ef2f-41b3-8307-eb877cbacc50
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966701805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1966701805
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.492993218
Short name T409
Test name
Test status
Simulation time 899951948 ps
CPU time 14.02 seconds
Started Jul 14 05:26:20 PM PDT 24
Finished Jul 14 05:26:35 PM PDT 24
Peak memory 210616 kb
Host smart-a21dbccd-f613-42e4-8162-6dd17fbcb3a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492993218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.492993218
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1881396782
Short name T96
Test name
Test status
Simulation time 604854853 ps
CPU time 19.18 seconds
Started Jul 14 05:26:18 PM PDT 24
Finished Jul 14 05:26:37 PM PDT 24
Peak memory 211500 kb
Host smart-66379164-b3e0-458c-abb8-75693509b7e8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881396782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1881396782
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3956429820
Short name T423
Test name
Test status
Simulation time 4677941653 ps
CPU time 16.6 seconds
Started Jul 14 05:26:18 PM PDT 24
Finished Jul 14 05:26:35 PM PDT 24
Peak memory 216836 kb
Host smart-0d03ebc2-736c-4db0-ada9-c8d2ec85ac14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956429820 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3956429820
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1842564409
Short name T419
Test name
Test status
Simulation time 2307745182 ps
CPU time 15.05 seconds
Started Jul 14 05:26:17 PM PDT 24
Finished Jul 14 05:26:32 PM PDT 24
Peak memory 210828 kb
Host smart-610cf211-3f72-4977-bf11-92cb3b60986c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842564409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1842564409
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3499266066
Short name T369
Test name
Test status
Simulation time 5703753779 ps
CPU time 25.52 seconds
Started Jul 14 05:26:20 PM PDT 24
Finished Jul 14 05:26:46 PM PDT 24
Peak memory 210548 kb
Host smart-39a4c6a7-6e70-41c7-a51a-7badbcfb9bdf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499266066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3499266066
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2963058591
Short name T422
Test name
Test status
Simulation time 3457918234 ps
CPU time 29.44 seconds
Started Jul 14 05:26:20 PM PDT 24
Finished Jul 14 05:26:49 PM PDT 24
Peak memory 210652 kb
Host smart-f8ea3f29-2376-498f-ba3b-9e1971e2644a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963058591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2963058591
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3259003951
Short name T94
Test name
Test status
Simulation time 358126190 ps
CPU time 12.27 seconds
Started Jul 14 05:26:17 PM PDT 24
Finished Jul 14 05:26:30 PM PDT 24
Peak memory 212424 kb
Host smart-2714f175-9bfd-449d-b276-9274f00b7114
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259003951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3259003951
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.720613020
Short name T457
Test name
Test status
Simulation time 10411159923 ps
CPU time 25.33 seconds
Started Jul 14 05:26:15 PM PDT 24
Finished Jul 14 05:26:40 PM PDT 24
Peak memory 218896 kb
Host smart-72767982-e8b4-4566-972d-0d8176965704
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720613020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.720613020
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3370705519
Short name T452
Test name
Test status
Simulation time 31168997685 ps
CPU time 99.7 seconds
Started Jul 14 05:26:21 PM PDT 24
Finished Jul 14 05:28:01 PM PDT 24
Peak memory 213952 kb
Host smart-ec978539-67b0-4951-b2b1-fcdb3d62af55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370705519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3370705519
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1417483355
Short name T401
Test name
Test status
Simulation time 2938733880 ps
CPU time 25.58 seconds
Started Jul 14 05:26:20 PM PDT 24
Finished Jul 14 05:26:46 PM PDT 24
Peak memory 218320 kb
Host smart-2eab6b1b-7571-4e40-b4f0-d7e87fcbc015
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417483355 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1417483355
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.393235245
Short name T403
Test name
Test status
Simulation time 473404833 ps
CPU time 8.23 seconds
Started Jul 14 05:26:19 PM PDT 24
Finished Jul 14 05:26:27 PM PDT 24
Peak memory 210860 kb
Host smart-aa43948d-abcc-48c2-9fca-2574e8cc7558
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393235245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.393235245
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3274996315
Short name T434
Test name
Test status
Simulation time 2588164149 ps
CPU time 73.74 seconds
Started Jul 14 05:26:20 PM PDT 24
Finished Jul 14 05:27:35 PM PDT 24
Peak memory 214828 kb
Host smart-c00f05eb-dbf9-4268-b49d-9dc5f60206d2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274996315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3274996315
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4057207611
Short name T458
Test name
Test status
Simulation time 5486452781 ps
CPU time 16.76 seconds
Started Jul 14 05:26:18 PM PDT 24
Finished Jul 14 05:26:35 PM PDT 24
Peak memory 212524 kb
Host smart-b48dc153-efe8-4c1b-88a4-cd63c6c49f60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057207611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.4057207611
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3131467821
Short name T451
Test name
Test status
Simulation time 2047428952 ps
CPU time 17.52 seconds
Started Jul 14 05:26:20 PM PDT 24
Finished Jul 14 05:26:38 PM PDT 24
Peak memory 218064 kb
Host smart-bdb3fd2f-cdf5-4226-958e-90f13250c813
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131467821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3131467821
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.902194556
Short name T109
Test name
Test status
Simulation time 4438975869 ps
CPU time 90.87 seconds
Started Jul 14 05:26:18 PM PDT 24
Finished Jul 14 05:27:49 PM PDT 24
Peak memory 213924 kb
Host smart-444dae18-6075-4a23-aa0a-6ff6d507d3ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902194556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.902194556
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3763840032
Short name T426
Test name
Test status
Simulation time 6966619968 ps
CPU time 28.56 seconds
Started Jul 14 05:26:27 PM PDT 24
Finished Jul 14 05:26:56 PM PDT 24
Peak memory 216804 kb
Host smart-75a7b003-0793-4f6c-9757-444a6c1e8d68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763840032 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3763840032
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3675050225
Short name T424
Test name
Test status
Simulation time 1799068000 ps
CPU time 19.22 seconds
Started Jul 14 05:26:24 PM PDT 24
Finished Jul 14 05:26:43 PM PDT 24
Peak memory 211540 kb
Host smart-b96b112d-d17f-4002-8c77-90a95034edcd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675050225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3675050225
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1509506087
Short name T85
Test name
Test status
Simulation time 24153259547 ps
CPU time 129.38 seconds
Started Jul 14 05:26:27 PM PDT 24
Finished Jul 14 05:28:37 PM PDT 24
Peak memory 215448 kb
Host smart-d0ce15ab-808b-4729-bc4f-507bdaea5b7d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509506087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1509506087
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2542589525
Short name T455
Test name
Test status
Simulation time 7082092541 ps
CPU time 17.92 seconds
Started Jul 14 05:26:23 PM PDT 24
Finished Jul 14 05:26:42 PM PDT 24
Peak memory 211688 kb
Host smart-92530da1-4647-4aa1-8bca-de6d3fc9fd85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542589525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2542589525
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2833424135
Short name T408
Test name
Test status
Simulation time 8146178124 ps
CPU time 34.76 seconds
Started Jul 14 05:26:23 PM PDT 24
Finished Jul 14 05:26:58 PM PDT 24
Peak memory 218344 kb
Host smart-f5ca86f0-e630-42f9-a7f4-cd461f4f6586
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833424135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2833424135
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.578137997
Short name T114
Test name
Test status
Simulation time 4128107617 ps
CPU time 177.52 seconds
Started Jul 14 05:26:24 PM PDT 24
Finished Jul 14 05:29:22 PM PDT 24
Peak memory 213868 kb
Host smart-68714a99-7521-48ee-92d2-d66db2e755c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578137997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.578137997
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.208680720
Short name T380
Test name
Test status
Simulation time 38614267863 ps
CPU time 25.56 seconds
Started Jul 14 05:26:23 PM PDT 24
Finished Jul 14 05:26:49 PM PDT 24
Peak memory 217260 kb
Host smart-ad1433d3-4385-4b43-8110-3f15c7d13147
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208680720 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.208680720
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3480973897
Short name T382
Test name
Test status
Simulation time 12294052260 ps
CPU time 16.54 seconds
Started Jul 14 05:26:26 PM PDT 24
Finished Jul 14 05:26:43 PM PDT 24
Peak memory 212164 kb
Host smart-b8a1be1f-04b0-49a7-b359-723767b2cd79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480973897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3480973897
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3002259565
Short name T383
Test name
Test status
Simulation time 721750781 ps
CPU time 12.02 seconds
Started Jul 14 05:26:26 PM PDT 24
Finished Jul 14 05:26:38 PM PDT 24
Peak memory 212664 kb
Host smart-7199b6bf-e92c-4eff-82e5-96c2847afc4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002259565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3002259565
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1145963607
Short name T397
Test name
Test status
Simulation time 3712943036 ps
CPU time 35.74 seconds
Started Jul 14 05:26:26 PM PDT 24
Finished Jul 14 05:27:02 PM PDT 24
Peak memory 218460 kb
Host smart-5cbff78b-239d-496f-85c4-0138d2035d5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145963607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1145963607
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2525866608
Short name T107
Test name
Test status
Simulation time 7771721834 ps
CPU time 91.54 seconds
Started Jul 14 05:26:24 PM PDT 24
Finished Jul 14 05:27:56 PM PDT 24
Peak memory 213872 kb
Host smart-b4c46d6b-35ce-41a9-a1de-23037c0d8a33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525866608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2525866608
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3885245553
Short name T59
Test name
Test status
Simulation time 4052369276 ps
CPU time 21.63 seconds
Started Jul 14 05:26:33 PM PDT 24
Finished Jul 14 05:26:55 PM PDT 24
Peak memory 217956 kb
Host smart-04ac0b92-b2bf-4378-aea2-fc3219a0c8f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885245553 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3885245553
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1022828686
Short name T74
Test name
Test status
Simulation time 11117738534 ps
CPU time 24.92 seconds
Started Jul 14 05:26:32 PM PDT 24
Finished Jul 14 05:26:57 PM PDT 24
Peak memory 211672 kb
Host smart-3858ef97-4820-48ae-8581-3266a099823f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022828686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1022828686
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3947201847
Short name T431
Test name
Test status
Simulation time 27012283292 ps
CPU time 102.55 seconds
Started Jul 14 05:26:33 PM PDT 24
Finished Jul 14 05:28:16 PM PDT 24
Peak memory 213836 kb
Host smart-bc422493-d42a-4884-89cd-555059ad2f5d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947201847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3947201847
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3886868658
Short name T443
Test name
Test status
Simulation time 26329548601 ps
CPU time 24.16 seconds
Started Jul 14 05:26:30 PM PDT 24
Finished Jul 14 05:26:55 PM PDT 24
Peak memory 212456 kb
Host smart-86c22f57-99dc-4240-9e89-3beef900b41b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886868658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3886868658
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3884597599
Short name T368
Test name
Test status
Simulation time 6383663758 ps
CPU time 36.23 seconds
Started Jul 14 05:26:31 PM PDT 24
Finished Jul 14 05:27:08 PM PDT 24
Peak memory 217576 kb
Host smart-94790171-988b-43c2-ba0f-72ea6f9ec8f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884597599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3884597599
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.417134932
Short name T106
Test name
Test status
Simulation time 8844745318 ps
CPU time 103.7 seconds
Started Jul 14 05:26:32 PM PDT 24
Finished Jul 14 05:28:16 PM PDT 24
Peak memory 213596 kb
Host smart-bc8e461f-38bc-4e9f-849c-7c834a773cfb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417134932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.417134932
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.4211558598
Short name T433
Test name
Test status
Simulation time 1682677242 ps
CPU time 11.97 seconds
Started Jul 14 05:26:32 PM PDT 24
Finished Jul 14 05:26:44 PM PDT 24
Peak memory 216916 kb
Host smart-eab6e26e-4de7-4df4-89b3-f3a6be355d98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211558598 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.4211558598
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1048568132
Short name T370
Test name
Test status
Simulation time 14427526948 ps
CPU time 30.66 seconds
Started Jul 14 05:26:31 PM PDT 24
Finished Jul 14 05:27:02 PM PDT 24
Peak memory 212176 kb
Host smart-83770f49-5598-476c-b367-f7c0acac8c12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048568132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1048568132
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.211497640
Short name T393
Test name
Test status
Simulation time 15903868322 ps
CPU time 86.59 seconds
Started Jul 14 05:26:30 PM PDT 24
Finished Jul 14 05:27:57 PM PDT 24
Peak memory 215132 kb
Host smart-e5f8b18a-e226-45a6-9fef-cc4c88126ebd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211497640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.211497640
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2729152972
Short name T386
Test name
Test status
Simulation time 254712085 ps
CPU time 10.05 seconds
Started Jul 14 05:26:31 PM PDT 24
Finished Jul 14 05:26:42 PM PDT 24
Peak memory 211044 kb
Host smart-eb04d071-3bf7-4b71-ac7e-16dfc9762d16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729152972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2729152972
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3021765976
Short name T449
Test name
Test status
Simulation time 3543882153 ps
CPU time 33.2 seconds
Started Jul 14 05:26:33 PM PDT 24
Finished Jul 14 05:27:07 PM PDT 24
Peak memory 218476 kb
Host smart-1e74eb12-cf56-43a6-bd3a-53ee2b3d1087
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021765976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3021765976
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2003740020
Short name T105
Test name
Test status
Simulation time 1211546847 ps
CPU time 155.09 seconds
Started Jul 14 05:26:32 PM PDT 24
Finished Jul 14 05:29:08 PM PDT 24
Peak memory 213956 kb
Host smart-c8b3b672-c569-4b82-bf34-29f95554a07c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003740020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2003740020
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3622987195
Short name T272
Test name
Test status
Simulation time 5539847525 ps
CPU time 17.06 seconds
Started Jul 14 05:23:37 PM PDT 24
Finished Jul 14 05:23:54 PM PDT 24
Peak memory 217184 kb
Host smart-c879f38f-460a-4f3d-9a28-4022d0baa46e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622987195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3622987195
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2108330832
Short name T342
Test name
Test status
Simulation time 3827411522 ps
CPU time 33.76 seconds
Started Jul 14 05:23:34 PM PDT 24
Finished Jul 14 05:24:09 PM PDT 24
Peak memory 219328 kb
Host smart-11fd1f68-ede2-437f-8b07-9280eb8f9a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108330832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2108330832
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2131110559
Short name T280
Test name
Test status
Simulation time 12250578804 ps
CPU time 25.86 seconds
Started Jul 14 05:23:35 PM PDT 24
Finished Jul 14 05:24:01 PM PDT 24
Peak memory 217684 kb
Host smart-f97d9803-a439-4095-b5de-991131e6dd16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2131110559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2131110559
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2466399314
Short name T29
Test name
Test status
Simulation time 456577258 ps
CPU time 114.46 seconds
Started Jul 14 05:23:35 PM PDT 24
Finished Jul 14 05:25:30 PM PDT 24
Peak memory 237360 kb
Host smart-ca0ee566-f828-46be-8b97-a5f7c1d023cd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466399314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2466399314
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.815448171
Short name T267
Test name
Test status
Simulation time 1406859859 ps
CPU time 20.84 seconds
Started Jul 14 05:23:35 PM PDT 24
Finished Jul 14 05:23:56 PM PDT 24
Peak memory 217428 kb
Host smart-1a77b485-2eae-4cea-9025-0f3dc24d879b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815448171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.815448171
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2138503934
Short name T353
Test name
Test status
Simulation time 17041724847 ps
CPU time 75.44 seconds
Started Jul 14 05:23:32 PM PDT 24
Finished Jul 14 05:24:48 PM PDT 24
Peak memory 217164 kb
Host smart-a52e5fa9-2cb5-410c-a594-ed2e5940e9bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138503934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2138503934
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2557402419
Short name T197
Test name
Test status
Simulation time 2628056968 ps
CPU time 24.08 seconds
Started Jul 14 05:23:39 PM PDT 24
Finished Jul 14 05:24:03 PM PDT 24
Peak memory 217052 kb
Host smart-7fa869d2-7e05-4421-84f0-516a2c352ca6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557402419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2557402419
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1727378184
Short name T265
Test name
Test status
Simulation time 260164912291 ps
CPU time 493.56 seconds
Started Jul 14 05:23:40 PM PDT 24
Finished Jul 14 05:31:54 PM PDT 24
Peak memory 232664 kb
Host smart-321f9216-b04c-4199-aac1-2ad4434c8adc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727378184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1727378184
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.295260680
Short name T21
Test name
Test status
Simulation time 2933780695 ps
CPU time 25.01 seconds
Started Jul 14 05:23:39 PM PDT 24
Finished Jul 14 05:24:05 PM PDT 24
Peak memory 211576 kb
Host smart-7027d6b0-2ae7-44f9-a9a8-546e3297e198
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=295260680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.295260680
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1509375766
Short name T28
Test name
Test status
Simulation time 703969417 ps
CPU time 229.3 seconds
Started Jul 14 05:23:37 PM PDT 24
Finished Jul 14 05:27:27 PM PDT 24
Peak memory 239704 kb
Host smart-cc1f06c7-1ea3-424e-8996-422b2669695e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509375766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1509375766
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1467108336
Short name T283
Test name
Test status
Simulation time 18537466248 ps
CPU time 39.48 seconds
Started Jul 14 05:23:38 PM PDT 24
Finished Jul 14 05:24:18 PM PDT 24
Peak memory 217096 kb
Host smart-91bffac1-13df-4639-8b82-89606a2fb3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467108336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1467108336
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2386572592
Short name T332
Test name
Test status
Simulation time 45347554081 ps
CPU time 101.71 seconds
Started Jul 14 05:23:39 PM PDT 24
Finished Jul 14 05:25:21 PM PDT 24
Peak memory 219244 kb
Host smart-96321934-215e-4db7-8eab-1894e789cc13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386572592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2386572592
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.763733109
Short name T285
Test name
Test status
Simulation time 7521488140 ps
CPU time 29.67 seconds
Started Jul 14 05:23:55 PM PDT 24
Finished Jul 14 05:24:25 PM PDT 24
Peak memory 217364 kb
Host smart-d32f1404-6217-4e98-8b64-e7b7d4332b99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763733109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.763733109
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.4011830199
Short name T127
Test name
Test status
Simulation time 224070188838 ps
CPU time 608.88 seconds
Started Jul 14 05:23:56 PM PDT 24
Finished Jul 14 05:34:05 PM PDT 24
Peak memory 235804 kb
Host smart-3a49263f-3a4a-44a8-a0f3-38d4272456cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011830199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.4011830199
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1279601890
Short name T343
Test name
Test status
Simulation time 2354683380 ps
CPU time 19.57 seconds
Started Jul 14 05:23:56 PM PDT 24
Finished Jul 14 05:24:16 PM PDT 24
Peak memory 219252 kb
Host smart-216951d4-d9cb-4ead-9697-7c5a2134096f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279601890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1279601890
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2607797888
Short name T149
Test name
Test status
Simulation time 10527300093 ps
CPU time 25.9 seconds
Started Jul 14 05:23:52 PM PDT 24
Finished Jul 14 05:24:18 PM PDT 24
Peak memory 217704 kb
Host smart-3c38d674-70da-451b-900b-5b6a154f482f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2607797888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2607797888
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3950929439
Short name T52
Test name
Test status
Simulation time 8895916443 ps
CPU time 79.22 seconds
Started Jul 14 05:23:51 PM PDT 24
Finished Jul 14 05:25:11 PM PDT 24
Peak memory 216968 kb
Host smart-ec18c021-0521-49a9-b16f-a2dda02635b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950929439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3950929439
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.249639841
Short name T119
Test name
Test status
Simulation time 16473899975 ps
CPU time 195.32 seconds
Started Jul 14 05:23:49 PM PDT 24
Finished Jul 14 05:27:05 PM PDT 24
Peak memory 221220 kb
Host smart-74e52f8d-25ee-4fde-9dab-3b533180faa6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249639841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.249639841
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3836238200
Short name T131
Test name
Test status
Simulation time 916919590 ps
CPU time 8.62 seconds
Started Jul 14 05:23:55 PM PDT 24
Finished Jul 14 05:24:04 PM PDT 24
Peak memory 217144 kb
Host smart-ac03ea7f-5114-4db9-b3ae-20db967cbafb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836238200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3836238200
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1246149181
Short name T359
Test name
Test status
Simulation time 191911281843 ps
CPU time 851.15 seconds
Started Jul 14 05:23:49 PM PDT 24
Finished Jul 14 05:38:00 PM PDT 24
Peak memory 219296 kb
Host smart-a963b842-3612-4998-9238-06fa0eabd520
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246149181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1246149181
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2729613022
Short name T205
Test name
Test status
Simulation time 30792936215 ps
CPU time 65.07 seconds
Started Jul 14 05:23:52 PM PDT 24
Finished Jul 14 05:24:57 PM PDT 24
Peak memory 219280 kb
Host smart-197826a7-d9df-48d7-bf36-371a3d1ff238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729613022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2729613022
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3762431532
Short name T329
Test name
Test status
Simulation time 3165722489 ps
CPU time 27.78 seconds
Started Jul 14 05:23:52 PM PDT 24
Finished Jul 14 05:24:20 PM PDT 24
Peak memory 219280 kb
Host smart-d5534a58-af29-423f-98e3-1f46a6fdd47a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3762431532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3762431532
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2372256823
Short name T161
Test name
Test status
Simulation time 3533004219 ps
CPU time 40.92 seconds
Started Jul 14 05:23:49 PM PDT 24
Finished Jul 14 05:24:31 PM PDT 24
Peak memory 216044 kb
Host smart-57fac25e-bca1-453c-96d4-03f6051d8044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372256823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2372256823
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3877231476
Short name T293
Test name
Test status
Simulation time 14342729696 ps
CPU time 152.05 seconds
Started Jul 14 05:23:49 PM PDT 24
Finished Jul 14 05:26:21 PM PDT 24
Peak memory 222500 kb
Host smart-fe0a4da5-996c-460d-b6a6-cdd825955434
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877231476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3877231476
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3399383377
Short name T58
Test name
Test status
Simulation time 609032764 ps
CPU time 12.75 seconds
Started Jul 14 05:23:57 PM PDT 24
Finished Jul 14 05:24:10 PM PDT 24
Peak memory 217100 kb
Host smart-6227c5fa-c03b-4384-9396-897899575e68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399383377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3399383377
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.4116493144
Short name T195
Test name
Test status
Simulation time 4745178158 ps
CPU time 216.98 seconds
Started Jul 14 05:23:54 PM PDT 24
Finished Jul 14 05:27:32 PM PDT 24
Peak memory 231220 kb
Host smart-616bdf5d-6eca-47cd-acfb-ecf50a70fa31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116493144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.4116493144
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.783337514
Short name T301
Test name
Test status
Simulation time 6582179566 ps
CPU time 30.32 seconds
Started Jul 14 05:23:58 PM PDT 24
Finished Jul 14 05:24:29 PM PDT 24
Peak memory 219296 kb
Host smart-0cd0b47e-d56e-4d0b-a9ab-f164ba09c86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783337514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.783337514
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1951648820
Short name T22
Test name
Test status
Simulation time 7569798607 ps
CPU time 22.01 seconds
Started Jul 14 05:23:58 PM PDT 24
Finished Jul 14 05:24:20 PM PDT 24
Peak memory 219252 kb
Host smart-19e8ed9b-098e-462d-acd7-c17003db9afc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1951648820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1951648820
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1298962431
Short name T278
Test name
Test status
Simulation time 48014260598 ps
CPU time 61.96 seconds
Started Jul 14 05:24:05 PM PDT 24
Finished Jul 14 05:25:08 PM PDT 24
Peak memory 217600 kb
Host smart-418d9eeb-5aa5-4487-9a0a-f2f2ece676db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298962431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1298962431
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2091023527
Short name T175
Test name
Test status
Simulation time 776504836 ps
CPU time 24.29 seconds
Started Jul 14 05:23:58 PM PDT 24
Finished Jul 14 05:24:23 PM PDT 24
Peak memory 217156 kb
Host smart-855b7c1f-7db2-44a9-8b71-8b2640ff84ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091023527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2091023527
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2018521809
Short name T248
Test name
Test status
Simulation time 250301270 ps
CPU time 9.88 seconds
Started Jul 14 05:23:57 PM PDT 24
Finished Jul 14 05:24:08 PM PDT 24
Peak memory 217100 kb
Host smart-ce218e29-ead9-44d0-a237-4280e1a7afdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018521809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2018521809
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3206875730
Short name T320
Test name
Test status
Simulation time 5209995518 ps
CPU time 249.07 seconds
Started Jul 14 05:23:58 PM PDT 24
Finished Jul 14 05:28:08 PM PDT 24
Peak memory 225784 kb
Host smart-6558e017-30ba-46d8-af91-e1e6cb0dc510
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206875730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3206875730
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1583528953
Short name T199
Test name
Test status
Simulation time 1320477202 ps
CPU time 19.41 seconds
Started Jul 14 05:23:58 PM PDT 24
Finished Jul 14 05:24:18 PM PDT 24
Peak memory 219284 kb
Host smart-c6367ff7-ddc6-4238-8701-c5f836555c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583528953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1583528953
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.654338358
Short name T338
Test name
Test status
Simulation time 3186790353 ps
CPU time 28.37 seconds
Started Jul 14 05:23:57 PM PDT 24
Finished Jul 14 05:24:26 PM PDT 24
Peak memory 211468 kb
Host smart-ef71c3a5-ee21-470f-8e36-28a46e4d205c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=654338358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.654338358
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1624716044
Short name T130
Test name
Test status
Simulation time 20211231878 ps
CPU time 48.42 seconds
Started Jul 14 05:23:57 PM PDT 24
Finished Jul 14 05:24:46 PM PDT 24
Peak memory 217216 kb
Host smart-45b6629f-58f8-412f-92d7-f4114acc317c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624716044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1624716044
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1104257770
Short name T305
Test name
Test status
Simulation time 31809257894 ps
CPU time 109.94 seconds
Started Jul 14 05:23:55 PM PDT 24
Finished Jul 14 05:25:45 PM PDT 24
Peak memory 220948 kb
Host smart-7d948273-5249-42d7-9d94-5c69918f5583
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104257770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1104257770
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.257880342
Short name T46
Test name
Test status
Simulation time 122943017227 ps
CPU time 2298.86 seconds
Started Jul 14 05:23:57 PM PDT 24
Finished Jul 14 06:02:17 PM PDT 24
Peak memory 241240 kb
Host smart-6baa4ce0-462e-4c1d-bee0-c4da96aaa532
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257880342 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.257880342
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2745065136
Short name T184
Test name
Test status
Simulation time 2727638754 ps
CPU time 16.65 seconds
Started Jul 14 05:23:58 PM PDT 24
Finished Jul 14 05:24:16 PM PDT 24
Peak memory 213140 kb
Host smart-43eb6194-56c9-499c-8a69-ad212ae502b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745065136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2745065136
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1503082147
Short name T125
Test name
Test status
Simulation time 33313961907 ps
CPU time 220.24 seconds
Started Jul 14 05:23:57 PM PDT 24
Finished Jul 14 05:27:38 PM PDT 24
Peak memory 238352 kb
Host smart-6bcca236-c00c-496b-bacd-4c483578aa7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503082147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1503082147
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1864936844
Short name T10
Test name
Test status
Simulation time 1738161145 ps
CPU time 19.29 seconds
Started Jul 14 05:24:05 PM PDT 24
Finished Jul 14 05:24:25 PM PDT 24
Peak memory 219200 kb
Host smart-8f5dfd82-e8dd-47aa-a086-d6ba07f15946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864936844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1864936844
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.454788554
Short name T19
Test name
Test status
Simulation time 1243337172 ps
CPU time 17.56 seconds
Started Jul 14 05:23:58 PM PDT 24
Finished Jul 14 05:24:16 PM PDT 24
Peak memory 211340 kb
Host smart-501d66b8-4b48-4bf7-8005-84965a4fc448
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=454788554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.454788554
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1547089566
Short name T49
Test name
Test status
Simulation time 653317607 ps
CPU time 19.81 seconds
Started Jul 14 05:24:05 PM PDT 24
Finished Jul 14 05:24:26 PM PDT 24
Peak memory 216548 kb
Host smart-35b130e5-e3ab-4db5-a7f6-f11b9872e559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547089566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1547089566
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.807041176
Short name T312
Test name
Test status
Simulation time 3870406904 ps
CPU time 52.03 seconds
Started Jul 14 05:23:58 PM PDT 24
Finished Jul 14 05:24:50 PM PDT 24
Peak memory 217768 kb
Host smart-4422631a-c6bc-4f30-8dcb-7cdb971eee8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807041176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.807041176
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1769480599
Short name T43
Test name
Test status
Simulation time 52544124005 ps
CPU time 1016.28 seconds
Started Jul 14 05:24:05 PM PDT 24
Finished Jul 14 05:41:02 PM PDT 24
Peak memory 235680 kb
Host smart-663ac112-7957-4de3-8d2a-b4743a389da4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769480599 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.1769480599
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.4215397714
Short name T316
Test name
Test status
Simulation time 14565011208 ps
CPU time 29.44 seconds
Started Jul 14 05:24:02 PM PDT 24
Finished Jul 14 05:24:32 PM PDT 24
Peak memory 213312 kb
Host smart-217a26ea-ce41-4824-be23-59b5732fe455
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215397714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.4215397714
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3222227743
Short name T266
Test name
Test status
Simulation time 51741942297 ps
CPU time 434.25 seconds
Started Jul 14 05:24:04 PM PDT 24
Finished Jul 14 05:31:20 PM PDT 24
Peak memory 228068 kb
Host smart-4fe23797-6a5f-4f3d-9cf7-544778205587
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222227743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3222227743
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.410677671
Short name T268
Test name
Test status
Simulation time 662314234 ps
CPU time 18.75 seconds
Started Jul 14 05:24:05 PM PDT 24
Finished Jul 14 05:24:25 PM PDT 24
Peak memory 219300 kb
Host smart-2f967c50-d40e-4191-80c4-4ef30e9e2874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410677671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.410677671
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.19496160
Short name T99
Test name
Test status
Simulation time 1569610147 ps
CPU time 13.51 seconds
Started Jul 14 05:24:03 PM PDT 24
Finished Jul 14 05:24:17 PM PDT 24
Peak memory 218824 kb
Host smart-02aa5413-64ab-4159-8d2e-a1b12f9af283
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=19496160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.19496160
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.46708566
Short name T311
Test name
Test status
Simulation time 15156002921 ps
CPU time 53.16 seconds
Started Jul 14 05:24:05 PM PDT 24
Finished Jul 14 05:24:59 PM PDT 24
Peak memory 216980 kb
Host smart-131cce79-1916-44bd-8a95-dc0f643cad3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46708566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.46708566
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.797692707
Short name T348
Test name
Test status
Simulation time 4580429772 ps
CPU time 15.05 seconds
Started Jul 14 05:24:02 PM PDT 24
Finished Jul 14 05:24:17 PM PDT 24
Peak memory 218788 kb
Host smart-c8641fe9-680f-4b2e-a1b7-f74a89683dcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797692707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.797692707
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.4209157432
Short name T169
Test name
Test status
Simulation time 1332545226 ps
CPU time 17.36 seconds
Started Jul 14 05:24:06 PM PDT 24
Finished Jul 14 05:24:24 PM PDT 24
Peak memory 217032 kb
Host smart-35a8fde9-4217-43fc-a53c-2fd15ff877cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209157432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.4209157432
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.297398724
Short name T221
Test name
Test status
Simulation time 195421726016 ps
CPU time 557.52 seconds
Started Jul 14 05:24:05 PM PDT 24
Finished Jul 14 05:33:23 PM PDT 24
Peak memory 236100 kb
Host smart-31dc83b4-4c59-451d-8682-f971da68fa48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297398724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.297398724
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3077466841
Short name T303
Test name
Test status
Simulation time 32146159783 ps
CPU time 67.99 seconds
Started Jul 14 05:24:02 PM PDT 24
Finished Jul 14 05:25:11 PM PDT 24
Peak memory 219180 kb
Host smart-b7d762e7-9da0-4052-8ac3-bb07718b6ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077466841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3077466841
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2692507763
Short name T341
Test name
Test status
Simulation time 12094684514 ps
CPU time 27.88 seconds
Started Jul 14 05:24:06 PM PDT 24
Finished Jul 14 05:24:34 PM PDT 24
Peak memory 219244 kb
Host smart-030e5cca-e033-4045-99d7-117ac993dd31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2692507763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2692507763
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3952252545
Short name T188
Test name
Test status
Simulation time 10611038286 ps
CPU time 59.55 seconds
Started Jul 14 05:24:04 PM PDT 24
Finished Jul 14 05:25:05 PM PDT 24
Peak memory 217860 kb
Host smart-24f6ffab-1b09-442e-9a77-d97cab9a3752
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952252545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3952252545
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1269964010
Short name T2
Test name
Test status
Simulation time 14612783905 ps
CPU time 21.82 seconds
Started Jul 14 05:24:04 PM PDT 24
Finished Jul 14 05:24:26 PM PDT 24
Peak memory 217576 kb
Host smart-5862b130-2247-4e05-a8bc-854f14cd7e22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269964010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1269964010
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.119557382
Short name T302
Test name
Test status
Simulation time 13373530622 ps
CPU time 220.62 seconds
Started Jul 14 05:24:04 PM PDT 24
Finished Jul 14 05:27:46 PM PDT 24
Peak memory 240236 kb
Host smart-057df6ba-3d2c-4be0-8024-91966ae02306
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119557382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.119557382
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3223202000
Short name T150
Test name
Test status
Simulation time 3763933724 ps
CPU time 41.84 seconds
Started Jul 14 05:24:01 PM PDT 24
Finished Jul 14 05:24:44 PM PDT 24
Peak memory 219244 kb
Host smart-8c43d5ba-bf57-4e1b-9e64-2ef3e11eeca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223202000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3223202000
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2204186293
Short name T274
Test name
Test status
Simulation time 19312182848 ps
CPU time 17.71 seconds
Started Jul 14 05:24:03 PM PDT 24
Finished Jul 14 05:24:21 PM PDT 24
Peak memory 211920 kb
Host smart-f439799a-c951-4d7e-bfd4-1c22213db4bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2204186293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2204186293
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.701671739
Short name T237
Test name
Test status
Simulation time 4111347079 ps
CPU time 42.51 seconds
Started Jul 14 05:24:04 PM PDT 24
Finished Jul 14 05:24:47 PM PDT 24
Peak memory 215864 kb
Host smart-a0c0c15f-c1ab-4554-bb44-dbc303ac08e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701671739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.701671739
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.508539788
Short name T208
Test name
Test status
Simulation time 11282845280 ps
CPU time 82.21 seconds
Started Jul 14 05:24:05 PM PDT 24
Finished Jul 14 05:25:28 PM PDT 24
Peak memory 219844 kb
Host smart-01b62526-9e93-45ae-be2d-5ae97bcbbfc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508539788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.508539788
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.1673799176
Short name T41
Test name
Test status
Simulation time 122844397105 ps
CPU time 1424.04 seconds
Started Jul 14 05:24:01 PM PDT 24
Finished Jul 14 05:47:46 PM PDT 24
Peak memory 238252 kb
Host smart-1c3e7e24-6623-4a8b-8441-f63e857cfb3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673799176 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.1673799176
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3628693956
Short name T62
Test name
Test status
Simulation time 2327583892 ps
CPU time 15.65 seconds
Started Jul 14 05:24:02 PM PDT 24
Finished Jul 14 05:24:18 PM PDT 24
Peak memory 213312 kb
Host smart-10099e37-832a-43b5-b575-20da1d620add
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628693956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3628693956
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1688088967
Short name T257
Test name
Test status
Simulation time 31274068716 ps
CPU time 268.59 seconds
Started Jul 14 05:24:04 PM PDT 24
Finished Jul 14 05:28:34 PM PDT 24
Peak memory 219528 kb
Host smart-f551bed1-9133-4d8b-a94a-42327dc42c35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688088967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1688088967
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1655166540
Short name T262
Test name
Test status
Simulation time 704439401 ps
CPU time 19.73 seconds
Started Jul 14 05:24:07 PM PDT 24
Finished Jul 14 05:24:27 PM PDT 24
Peak memory 219184 kb
Host smart-bcdcf191-1389-474c-ab66-c95bb398ea5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655166540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1655166540
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1944619875
Short name T271
Test name
Test status
Simulation time 17740253851 ps
CPU time 35.45 seconds
Started Jul 14 05:24:03 PM PDT 24
Finished Jul 14 05:24:39 PM PDT 24
Peak memory 211916 kb
Host smart-3d10cc28-f1e8-4118-81e9-7b0ca2c6c574
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1944619875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1944619875
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.3119394000
Short name T279
Test name
Test status
Simulation time 690921052 ps
CPU time 19.76 seconds
Started Jul 14 05:24:03 PM PDT 24
Finished Jul 14 05:24:23 PM PDT 24
Peak memory 217364 kb
Host smart-57219f84-0c46-4bc0-ae5c-35b2380a6bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119394000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.3119394000
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1801983005
Short name T256
Test name
Test status
Simulation time 389024974 ps
CPU time 24.3 seconds
Started Jul 14 05:24:00 PM PDT 24
Finished Jul 14 05:24:25 PM PDT 24
Peak memory 217668 kb
Host smart-afc4e4fd-2ba4-4e71-a039-016387a0a472
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801983005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1801983005
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.3802753489
Short name T40
Test name
Test status
Simulation time 301227930865 ps
CPU time 2968.13 seconds
Started Jul 14 05:24:05 PM PDT 24
Finished Jul 14 06:13:35 PM PDT 24
Peak memory 244932 kb
Host smart-7b9b53b3-824f-4c5c-84f7-4616fb88a324
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802753489 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.3802753489
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.4227524945
Short name T231
Test name
Test status
Simulation time 9502144153 ps
CPU time 23.01 seconds
Started Jul 14 05:24:09 PM PDT 24
Finished Jul 14 05:24:32 PM PDT 24
Peak memory 213284 kb
Host smart-79267ed2-6d22-454c-8015-cb42f9dff2b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227524945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.4227524945
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2026192383
Short name T313
Test name
Test status
Simulation time 34248373839 ps
CPU time 479.03 seconds
Started Jul 14 05:24:02 PM PDT 24
Finished Jul 14 05:32:02 PM PDT 24
Peak memory 225424 kb
Host smart-30c9a7db-96d5-4b5f-8b2b-eb22a360d657
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026192383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2026192383
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.738998404
Short name T334
Test name
Test status
Simulation time 20519361899 ps
CPU time 50.93 seconds
Started Jul 14 05:24:02 PM PDT 24
Finished Jul 14 05:24:53 PM PDT 24
Peak memory 219332 kb
Host smart-e68130ef-0a3d-4ad5-b38f-270df07ac394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738998404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.738998404
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3253131500
Short name T235
Test name
Test status
Simulation time 4158547337 ps
CPU time 16.3 seconds
Started Jul 14 05:24:03 PM PDT 24
Finished Jul 14 05:24:20 PM PDT 24
Peak memory 218576 kb
Host smart-608f67c8-aea2-45cf-adaf-19d722968625
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3253131500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3253131500
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.900063363
Short name T264
Test name
Test status
Simulation time 5737209561 ps
CPU time 37.44 seconds
Started Jul 14 05:24:04 PM PDT 24
Finished Jul 14 05:24:42 PM PDT 24
Peak memory 216956 kb
Host smart-e5e1c5b9-0235-4e63-a855-f30ddee30957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900063363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.900063363
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3584586952
Short name T122
Test name
Test status
Simulation time 1041120200 ps
CPU time 35.03 seconds
Started Jul 14 05:24:05 PM PDT 24
Finished Jul 14 05:24:41 PM PDT 24
Peak memory 219220 kb
Host smart-2ba66d08-6497-4d27-8df3-c564dfe4c3bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584586952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3584586952
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.4286346218
Short name T249
Test name
Test status
Simulation time 169158287 ps
CPU time 8.23 seconds
Started Jul 14 05:23:37 PM PDT 24
Finished Jul 14 05:23:45 PM PDT 24
Peak memory 217160 kb
Host smart-cc6eb28c-9692-40c6-b9fc-88ac9b241fff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286346218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.4286346218
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3747840677
Short name T324
Test name
Test status
Simulation time 32726022983 ps
CPU time 415.14 seconds
Started Jul 14 05:23:40 PM PDT 24
Finished Jul 14 05:30:36 PM PDT 24
Peak memory 240072 kb
Host smart-5d13ab4a-9731-40ac-8bfc-6ed30158dff4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747840677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3747840677
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.320718249
Short name T47
Test name
Test status
Simulation time 7868323324 ps
CPU time 66.1 seconds
Started Jul 14 05:23:43 PM PDT 24
Finished Jul 14 05:24:50 PM PDT 24
Peak memory 219164 kb
Host smart-dfe6fd65-3886-4e8c-a19b-49e14dd60edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320718249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.320718249
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2952692281
Short name T98
Test name
Test status
Simulation time 592121469 ps
CPU time 14.59 seconds
Started Jul 14 05:23:41 PM PDT 24
Finished Jul 14 05:23:56 PM PDT 24
Peak memory 219220 kb
Host smart-69be8200-66bc-40d5-bf5d-a46a47e8dee8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2952692281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2952692281
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.416751802
Short name T5
Test name
Test status
Simulation time 2856376055 ps
CPU time 135.82 seconds
Started Jul 14 05:23:35 PM PDT 24
Finished Jul 14 05:25:51 PM PDT 24
Peak memory 237960 kb
Host smart-ab164131-fe1b-490b-9058-4bca5dfb7c39
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416751802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.416751802
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.580684562
Short name T354
Test name
Test status
Simulation time 2058710950 ps
CPU time 34.63 seconds
Started Jul 14 05:23:37 PM PDT 24
Finished Jul 14 05:24:12 PM PDT 24
Peak memory 215880 kb
Host smart-2323815f-a55f-499a-8c79-0f2a4097190f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580684562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.580684562
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2405049298
Short name T190
Test name
Test status
Simulation time 10429840649 ps
CPU time 118.22 seconds
Started Jul 14 05:23:37 PM PDT 24
Finished Jul 14 05:25:36 PM PDT 24
Peak memory 219732 kb
Host smart-e69c997d-8551-4ca7-bba0-bf26d3dfcfbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405049298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2405049298
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.2673397335
Short name T13
Test name
Test status
Simulation time 14370781866 ps
CPU time 591.13 seconds
Started Jul 14 05:23:43 PM PDT 24
Finished Jul 14 05:33:35 PM PDT 24
Peak memory 235720 kb
Host smart-9534ced1-e837-4162-9b19-86c64714e875
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673397335 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.2673397335
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.276672171
Short name T186
Test name
Test status
Simulation time 7691822253 ps
CPU time 31.52 seconds
Started Jul 14 05:24:07 PM PDT 24
Finished Jul 14 05:24:39 PM PDT 24
Peak memory 217468 kb
Host smart-64743504-176a-4dd8-8287-7570b5541df2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276672171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.276672171
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1885724384
Short name T344
Test name
Test status
Simulation time 1539441347 ps
CPU time 29.42 seconds
Started Jul 14 05:24:12 PM PDT 24
Finished Jul 14 05:24:42 PM PDT 24
Peak memory 219260 kb
Host smart-aaedfd18-35ce-4dcd-96fb-e3862a8e2e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885724384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1885724384
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1558894032
Short name T254
Test name
Test status
Simulation time 3719901468 ps
CPU time 30.52 seconds
Started Jul 14 05:24:10 PM PDT 24
Finished Jul 14 05:24:41 PM PDT 24
Peak memory 219316 kb
Host smart-00c552ed-2f04-441f-a288-006e74e59c59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1558894032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1558894032
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2703372148
Short name T158
Test name
Test status
Simulation time 362543910 ps
CPU time 19.61 seconds
Started Jul 14 05:24:08 PM PDT 24
Finished Jul 14 05:24:29 PM PDT 24
Peak memory 216172 kb
Host smart-0a191801-8467-4029-aeb7-36699fddba5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703372148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2703372148
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.806183833
Short name T297
Test name
Test status
Simulation time 12804827703 ps
CPU time 106.94 seconds
Started Jul 14 05:24:08 PM PDT 24
Finished Jul 14 05:25:56 PM PDT 24
Peak memory 219360 kb
Host smart-b3166c88-72f4-4a66-8009-3e46c3d49255
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806183833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.806183833
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.422075560
Short name T294
Test name
Test status
Simulation time 12644823282 ps
CPU time 27.54 seconds
Started Jul 14 05:24:08 PM PDT 24
Finished Jul 14 05:24:36 PM PDT 24
Peak memory 217568 kb
Host smart-9231cd87-a61a-44d1-bd46-6a445e2e531b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422075560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.422075560
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.74188147
Short name T239
Test name
Test status
Simulation time 17489111042 ps
CPU time 207.95 seconds
Started Jul 14 05:24:08 PM PDT 24
Finished Jul 14 05:27:37 PM PDT 24
Peak memory 233948 kb
Host smart-2ce25b47-1595-4594-8ac5-52762d473018
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74188147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_co
rrupt_sig_fatal_chk.74188147
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2556295212
Short name T146
Test name
Test status
Simulation time 2242423308 ps
CPU time 28.29 seconds
Started Jul 14 05:24:08 PM PDT 24
Finished Jul 14 05:24:37 PM PDT 24
Peak memory 219324 kb
Host smart-66f703a8-bbae-440f-bad1-d2cdfb48393b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556295212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2556295212
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.161229145
Short name T286
Test name
Test status
Simulation time 736395461 ps
CPU time 10.61 seconds
Started Jul 14 05:24:08 PM PDT 24
Finished Jul 14 05:24:19 PM PDT 24
Peak memory 219196 kb
Host smart-f9f20624-23b1-47fd-81f8-c3a947822dad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=161229145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.161229145
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.65510031
Short name T174
Test name
Test status
Simulation time 3839335653 ps
CPU time 19.93 seconds
Started Jul 14 05:24:08 PM PDT 24
Finished Jul 14 05:24:29 PM PDT 24
Peak memory 216384 kb
Host smart-97bcca9d-eed7-4d01-bdd9-837b99e1a78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65510031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.65510031
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.529574618
Short name T236
Test name
Test status
Simulation time 10949480104 ps
CPU time 54.42 seconds
Started Jul 14 05:24:10 PM PDT 24
Finished Jul 14 05:25:05 PM PDT 24
Peak memory 219340 kb
Host smart-f87c2556-c028-462c-bfaa-d387784e0a40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529574618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.529574618
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3900711376
Short name T230
Test name
Test status
Simulation time 14517785601 ps
CPU time 19.52 seconds
Started Jul 14 05:24:21 PM PDT 24
Finished Jul 14 05:24:41 PM PDT 24
Peak memory 217960 kb
Host smart-f07b92d1-610c-4226-9294-e5b49bf0c23e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900711376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3900711376
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1487243883
Short name T35
Test name
Test status
Simulation time 38992736285 ps
CPU time 463.62 seconds
Started Jul 14 05:24:14 PM PDT 24
Finished Jul 14 05:31:58 PM PDT 24
Peak memory 232752 kb
Host smart-b81974a4-2713-471b-a80f-6767d15f0014
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487243883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1487243883
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.528824959
Short name T358
Test name
Test status
Simulation time 16984879088 ps
CPU time 67.29 seconds
Started Jul 14 05:24:13 PM PDT 24
Finished Jul 14 05:25:21 PM PDT 24
Peak memory 219244 kb
Host smart-19b1a598-e2eb-43b6-af5c-4128d0605304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528824959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.528824959
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2701040448
Short name T246
Test name
Test status
Simulation time 3648103769 ps
CPU time 16.42 seconds
Started Jul 14 05:24:13 PM PDT 24
Finished Jul 14 05:24:30 PM PDT 24
Peak memory 219372 kb
Host smart-bec9c452-963a-430f-bab7-980cb9fbaded
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2701040448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2701040448
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.578583082
Short name T14
Test name
Test status
Simulation time 2917253676 ps
CPU time 24.14 seconds
Started Jul 14 05:24:14 PM PDT 24
Finished Jul 14 05:24:39 PM PDT 24
Peak memory 216032 kb
Host smart-43b3dbde-4113-446b-9143-fc61782dd925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578583082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.578583082
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3444811075
Short name T255
Test name
Test status
Simulation time 6781129570 ps
CPU time 34.26 seconds
Started Jul 14 05:24:13 PM PDT 24
Finished Jul 14 05:24:47 PM PDT 24
Peak memory 219112 kb
Host smart-6f38f41d-17f2-4121-9c60-305d64cfba8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444811075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3444811075
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.166700093
Short name T212
Test name
Test status
Simulation time 2736402489 ps
CPU time 12.28 seconds
Started Jul 14 05:24:33 PM PDT 24
Finished Jul 14 05:24:46 PM PDT 24
Peak memory 217056 kb
Host smart-543b98c7-24e0-4323-8115-5d0ab9dd0d88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166700093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.166700093
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2769663079
Short name T287
Test name
Test status
Simulation time 7882151889 ps
CPU time 32.71 seconds
Started Jul 14 05:24:31 PM PDT 24
Finished Jul 14 05:25:04 PM PDT 24
Peak memory 219264 kb
Host smart-5723d536-8f7f-47f7-ad8f-0eb2122bd385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769663079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2769663079
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.4222565692
Short name T8
Test name
Test status
Simulation time 14021071921 ps
CPU time 28.72 seconds
Started Jul 14 05:24:27 PM PDT 24
Finished Jul 14 05:24:57 PM PDT 24
Peak memory 211712 kb
Host smart-a5698def-8c2c-477c-bbc9-ac56fec2507e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4222565692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.4222565692
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.4069405539
Short name T121
Test name
Test status
Simulation time 1110144423 ps
CPU time 20.38 seconds
Started Jul 14 05:24:25 PM PDT 24
Finished Jul 14 05:24:46 PM PDT 24
Peak memory 216724 kb
Host smart-8ad85728-1d9e-4db7-98f7-10bc98e8315b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069405539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.4069405539
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.4132916030
Short name T310
Test name
Test status
Simulation time 555975573 ps
CPU time 44.26 seconds
Started Jul 14 05:24:26 PM PDT 24
Finished Jul 14 05:25:11 PM PDT 24
Peak memory 219252 kb
Host smart-7799bafd-207a-4f74-a594-a70b4a3566e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132916030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.4132916030
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.4233924635
Short name T228
Test name
Test status
Simulation time 22455787236 ps
CPU time 32 seconds
Started Jul 14 05:24:35 PM PDT 24
Finished Jul 14 05:25:08 PM PDT 24
Peak memory 217572 kb
Host smart-7d36537b-c0cc-43ca-8165-b172972e8324
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233924635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.4233924635
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3679945187
Short name T288
Test name
Test status
Simulation time 102756158599 ps
CPU time 261.59 seconds
Started Jul 14 05:24:33 PM PDT 24
Finished Jul 14 05:28:55 PM PDT 24
Peak memory 240524 kb
Host smart-fd55ca88-012b-41fc-877d-24fe053bd225
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679945187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3679945187
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.117909795
Short name T160
Test name
Test status
Simulation time 8037528586 ps
CPU time 43.54 seconds
Started Jul 14 05:24:33 PM PDT 24
Finished Jul 14 05:25:17 PM PDT 24
Peak memory 219316 kb
Host smart-4232b3ff-6892-40a5-9ea8-a151aa97a6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117909795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.117909795
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.270859162
Short name T333
Test name
Test status
Simulation time 1975401321 ps
CPU time 22.38 seconds
Started Jul 14 05:24:35 PM PDT 24
Finished Jul 14 05:24:58 PM PDT 24
Peak memory 219288 kb
Host smart-7cca9253-0537-4d47-9055-a7a4722927b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=270859162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.270859162
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1991610632
Short name T217
Test name
Test status
Simulation time 34109122050 ps
CPU time 71.25 seconds
Started Jul 14 05:24:35 PM PDT 24
Finished Jul 14 05:25:46 PM PDT 24
Peak memory 216236 kb
Host smart-81e92cec-097b-4162-ae9e-93792da1e04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991610632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1991610632
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2570141579
Short name T172
Test name
Test status
Simulation time 30772452005 ps
CPU time 59.38 seconds
Started Jul 14 05:24:33 PM PDT 24
Finished Jul 14 05:25:32 PM PDT 24
Peak memory 220584 kb
Host smart-f5771587-0694-4c75-b76e-de6f522c5d74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570141579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2570141579
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.517484004
Short name T164
Test name
Test status
Simulation time 4024086897 ps
CPU time 29.93 seconds
Started Jul 14 05:24:38 PM PDT 24
Finished Jul 14 05:25:09 PM PDT 24
Peak memory 216640 kb
Host smart-15f36482-38fb-406d-b7f2-90359e3d6c2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517484004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.517484004
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3402434630
Short name T120
Test name
Test status
Simulation time 111959911848 ps
CPU time 322.4 seconds
Started Jul 14 05:24:39 PM PDT 24
Finished Jul 14 05:30:03 PM PDT 24
Peak memory 224760 kb
Host smart-d1a92fc7-cf1b-439b-9533-c25e660902d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402434630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3402434630
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.508597404
Short name T182
Test name
Test status
Simulation time 12508297187 ps
CPU time 40.09 seconds
Started Jul 14 05:24:41 PM PDT 24
Finished Jul 14 05:25:22 PM PDT 24
Peak memory 219328 kb
Host smart-5f304572-3279-4f18-a900-705ea141cdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508597404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.508597404
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.562069283
Short name T115
Test name
Test status
Simulation time 185449490 ps
CPU time 10.46 seconds
Started Jul 14 05:24:38 PM PDT 24
Finished Jul 14 05:24:49 PM PDT 24
Peak memory 219220 kb
Host smart-f31e5495-e78b-4893-bf70-675e7b4fae4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=562069283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.562069283
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3336853744
Short name T258
Test name
Test status
Simulation time 20962706222 ps
CPU time 71.01 seconds
Started Jul 14 05:24:33 PM PDT 24
Finished Jul 14 05:25:44 PM PDT 24
Peak memory 215668 kb
Host smart-a00d8e59-ef06-4849-8ddc-4763c01b7d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336853744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3336853744
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3118817710
Short name T17
Test name
Test status
Simulation time 4636435413 ps
CPU time 58.61 seconds
Started Jul 14 05:24:40 PM PDT 24
Finished Jul 14 05:25:40 PM PDT 24
Peak memory 217708 kb
Host smart-383c3928-cd6d-4f49-bbba-6fac79d5e663
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118817710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3118817710
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.122743735
Short name T126
Test name
Test status
Simulation time 42857891649 ps
CPU time 31.73 seconds
Started Jul 14 05:24:41 PM PDT 24
Finished Jul 14 05:25:14 PM PDT 24
Peak memory 217456 kb
Host smart-66949bd1-bf0c-414b-915c-ae871c264098
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122743735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.122743735
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3751255808
Short name T159
Test name
Test status
Simulation time 38737859441 ps
CPU time 418.84 seconds
Started Jul 14 05:24:41 PM PDT 24
Finished Jul 14 05:31:41 PM PDT 24
Peak memory 234312 kb
Host smart-5943f011-c5ec-42e2-bfb3-b6df4a8752d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751255808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3751255808
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2565271785
Short name T144
Test name
Test status
Simulation time 332628911 ps
CPU time 19.67 seconds
Started Jul 14 05:24:38 PM PDT 24
Finished Jul 14 05:24:59 PM PDT 24
Peak memory 219276 kb
Host smart-2ce943ac-bed8-4337-be81-53e2cea6d4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565271785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2565271785
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3836214363
Short name T116
Test name
Test status
Simulation time 344812781 ps
CPU time 10.25 seconds
Started Jul 14 05:24:38 PM PDT 24
Finished Jul 14 05:24:48 PM PDT 24
Peak memory 219308 kb
Host smart-f3954537-4372-4702-8ec1-d5d6549b614c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3836214363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3836214363
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3793477467
Short name T128
Test name
Test status
Simulation time 24418751402 ps
CPU time 66.31 seconds
Started Jul 14 05:24:41 PM PDT 24
Finished Jul 14 05:25:48 PM PDT 24
Peak memory 216140 kb
Host smart-a2635e4b-8fe4-48df-a1fe-d3e3b3a8fdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793477467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3793477467
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2456536417
Short name T50
Test name
Test status
Simulation time 14808240949 ps
CPU time 85.99 seconds
Started Jul 14 05:24:39 PM PDT 24
Finished Jul 14 05:26:06 PM PDT 24
Peak memory 220004 kb
Host smart-bf732f1e-4b74-4143-84bf-c6fbe5d0390e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456536417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2456536417
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3182068020
Short name T304
Test name
Test status
Simulation time 5917646515 ps
CPU time 18.28 seconds
Started Jul 14 05:24:47 PM PDT 24
Finished Jul 14 05:25:06 PM PDT 24
Peak memory 217308 kb
Host smart-6f4cc9ce-5e1c-4581-af37-b9c1026c0588
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182068020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3182068020
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.357858699
Short name T352
Test name
Test status
Simulation time 154569528908 ps
CPU time 451.75 seconds
Started Jul 14 05:24:45 PM PDT 24
Finished Jul 14 05:32:17 PM PDT 24
Peak memory 232068 kb
Host smart-d3c12ee3-6992-4685-be77-00bc88591783
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357858699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.357858699
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.316146082
Short name T299
Test name
Test status
Simulation time 7888254029 ps
CPU time 23.17 seconds
Started Jul 14 05:24:46 PM PDT 24
Finished Jul 14 05:25:10 PM PDT 24
Peak memory 212020 kb
Host smart-b4892baa-8af7-4855-9457-371b6c401a8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=316146082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.316146082
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2331394537
Short name T194
Test name
Test status
Simulation time 2119546169 ps
CPU time 32.5 seconds
Started Jul 14 05:24:39 PM PDT 24
Finished Jul 14 05:25:12 PM PDT 24
Peak memory 215976 kb
Host smart-f1f119d9-f33a-4c38-b61e-92902e0aec88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331394537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2331394537
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1731948598
Short name T207
Test name
Test status
Simulation time 16739069512 ps
CPU time 37.58 seconds
Started Jul 14 05:24:46 PM PDT 24
Finished Jul 14 05:25:25 PM PDT 24
Peak memory 219320 kb
Host smart-d2a5566f-67a5-4aae-86ce-eb6acea5e493
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731948598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1731948598
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1500737783
Short name T155
Test name
Test status
Simulation time 750224729 ps
CPU time 8.24 seconds
Started Jul 14 05:24:46 PM PDT 24
Finished Jul 14 05:24:55 PM PDT 24
Peak memory 216360 kb
Host smart-2a7bd76c-ed6a-47bf-a490-3fbb55e470c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500737783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1500737783
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3657492578
Short name T177
Test name
Test status
Simulation time 14730730042 ps
CPU time 223.15 seconds
Started Jul 14 05:24:46 PM PDT 24
Finished Jul 14 05:28:30 PM PDT 24
Peak memory 234940 kb
Host smart-7af95b4d-e8a3-4202-8557-7714c7e03c4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657492578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3657492578
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.4034147619
Short name T362
Test name
Test status
Simulation time 5656932622 ps
CPU time 49.65 seconds
Started Jul 14 05:24:45 PM PDT 24
Finished Jul 14 05:25:35 PM PDT 24
Peak memory 219340 kb
Host smart-8531c113-d3d2-4417-a8cc-0048c049ca71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034147619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.4034147619
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1255571383
Short name T219
Test name
Test status
Simulation time 3189730390 ps
CPU time 19.32 seconds
Started Jul 14 05:24:44 PM PDT 24
Finished Jul 14 05:25:04 PM PDT 24
Peak memory 219340 kb
Host smart-590b7668-2b3e-4086-85d9-aabdd307e198
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1255571383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1255571383
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1424782786
Short name T234
Test name
Test status
Simulation time 26435302944 ps
CPU time 43.05 seconds
Started Jul 14 05:24:47 PM PDT 24
Finished Jul 14 05:25:31 PM PDT 24
Peak memory 217020 kb
Host smart-02902c1b-41eb-4fe4-ae04-a8e1dc3fae51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424782786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1424782786
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3033155110
Short name T229
Test name
Test status
Simulation time 19065432049 ps
CPU time 38.12 seconds
Started Jul 14 05:24:46 PM PDT 24
Finished Jul 14 05:25:25 PM PDT 24
Peak memory 214624 kb
Host smart-6f86a826-3ef3-4a86-847d-2b1428426b86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033155110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3033155110
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.946292391
Short name T147
Test name
Test status
Simulation time 6818361754 ps
CPU time 18.91 seconds
Started Jul 14 05:24:53 PM PDT 24
Finished Jul 14 05:25:12 PM PDT 24
Peak memory 217872 kb
Host smart-66799f28-244c-4851-9296-0b604676ef9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946292391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.946292391
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1942530162
Short name T295
Test name
Test status
Simulation time 61105492184 ps
CPU time 578.72 seconds
Started Jul 14 05:24:51 PM PDT 24
Finished Jul 14 05:34:30 PM PDT 24
Peak memory 238824 kb
Host smart-053e5fe0-e4d3-488a-bce0-e6113e84b84d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942530162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1942530162
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2179697938
Short name T51
Test name
Test status
Simulation time 648124372 ps
CPU time 19.29 seconds
Started Jul 14 05:24:50 PM PDT 24
Finished Jul 14 05:25:10 PM PDT 24
Peak memory 219272 kb
Host smart-377190fe-ff8a-4a96-9dd5-f920f967766a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179697938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2179697938
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3857615524
Short name T167
Test name
Test status
Simulation time 676227043 ps
CPU time 12.43 seconds
Started Jul 14 05:24:52 PM PDT 24
Finished Jul 14 05:25:05 PM PDT 24
Peak memory 218804 kb
Host smart-3be1343e-8e22-4d12-ab06-59c5fed94e27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3857615524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3857615524
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3050144330
Short name T339
Test name
Test status
Simulation time 26816056565 ps
CPU time 59.83 seconds
Started Jul 14 05:24:47 PM PDT 24
Finished Jul 14 05:25:47 PM PDT 24
Peak memory 216032 kb
Host smart-6b66215b-1434-4d82-9232-8d079c11e150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050144330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3050144330
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2607053900
Short name T335
Test name
Test status
Simulation time 18473310280 ps
CPU time 64.37 seconds
Started Jul 14 05:24:48 PM PDT 24
Finished Jul 14 05:25:53 PM PDT 24
Peak memory 218944 kb
Host smart-c7b0bc96-ef2d-48bb-baad-c952f77fcca4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607053900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2607053900
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.4146781419
Short name T251
Test name
Test status
Simulation time 20790290460 ps
CPU time 28.67 seconds
Started Jul 14 05:23:45 PM PDT 24
Finished Jul 14 05:24:15 PM PDT 24
Peak memory 217564 kb
Host smart-7312f8f8-f72d-4f9d-a86b-088249ca2546
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146781419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.4146781419
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2194202487
Short name T180
Test name
Test status
Simulation time 11008332270 ps
CPU time 60.35 seconds
Started Jul 14 05:23:37 PM PDT 24
Finished Jul 14 05:24:38 PM PDT 24
Peak memory 219320 kb
Host smart-4a600383-b051-42d7-9dd6-49ba6147bb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194202487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2194202487
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1528346866
Short name T136
Test name
Test status
Simulation time 532711368 ps
CPU time 10.7 seconds
Started Jul 14 05:23:38 PM PDT 24
Finished Jul 14 05:23:50 PM PDT 24
Peak memory 219280 kb
Host smart-9e58f40d-e8de-4ca2-ae54-e39a050c199d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1528346866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1528346866
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.4087727829
Short name T24
Test name
Test status
Simulation time 16907159126 ps
CPU time 144.38 seconds
Started Jul 14 05:23:44 PM PDT 24
Finished Jul 14 05:26:10 PM PDT 24
Peak memory 235384 kb
Host smart-ccbc0d0f-a457-4a8a-b31a-0aaafdae0c51
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087727829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.4087727829
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1779617735
Short name T132
Test name
Test status
Simulation time 8378084089 ps
CPU time 70.4 seconds
Started Jul 14 05:23:37 PM PDT 24
Finished Jul 14 05:24:48 PM PDT 24
Peak memory 217096 kb
Host smart-57175155-8590-49ae-9c8c-56822b3d0ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779617735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1779617735
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1894832492
Short name T345
Test name
Test status
Simulation time 30082536246 ps
CPU time 63.36 seconds
Started Jul 14 05:23:43 PM PDT 24
Finished Jul 14 05:24:47 PM PDT 24
Peak memory 219272 kb
Host smart-7e651f7b-0387-4053-8efb-82e80812f65a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894832492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1894832492
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3280174132
Short name T350
Test name
Test status
Simulation time 4786981213 ps
CPU time 22.23 seconds
Started Jul 14 05:25:00 PM PDT 24
Finished Jul 14 05:25:23 PM PDT 24
Peak memory 217376 kb
Host smart-5113f2a2-543b-4697-a11c-bafdf44401f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280174132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3280174132
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3141363887
Short name T277
Test name
Test status
Simulation time 254235114039 ps
CPU time 722.4 seconds
Started Jul 14 05:24:52 PM PDT 24
Finished Jul 14 05:36:55 PM PDT 24
Peak memory 239304 kb
Host smart-cd904ac5-b45a-4ff7-bf79-c4d5417e38e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141363887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3141363887
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.4060215022
Short name T134
Test name
Test status
Simulation time 332822461 ps
CPU time 19.57 seconds
Started Jul 14 05:25:02 PM PDT 24
Finished Jul 14 05:25:22 PM PDT 24
Peak memory 219192 kb
Host smart-d2045d61-0033-47a4-b4ea-a5d22620b0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060215022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.4060215022
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.4193787451
Short name T241
Test name
Test status
Simulation time 16186490612 ps
CPU time 33.11 seconds
Started Jul 14 05:24:51 PM PDT 24
Finished Jul 14 05:25:25 PM PDT 24
Peak memory 211576 kb
Host smart-c5720381-65ff-4e23-9883-7cd91d33cd61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4193787451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.4193787451
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1161658995
Short name T156
Test name
Test status
Simulation time 36251992645 ps
CPU time 62.84 seconds
Started Jul 14 05:24:51 PM PDT 24
Finished Jul 14 05:25:55 PM PDT 24
Peak memory 216112 kb
Host smart-3ec0ff2e-fdf1-42a3-9711-798ef14e67f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161658995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1161658995
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.948616418
Short name T53
Test name
Test status
Simulation time 13121181574 ps
CPU time 132.54 seconds
Started Jul 14 05:24:54 PM PDT 24
Finished Jul 14 05:27:07 PM PDT 24
Peak memory 219272 kb
Host smart-fcf5fb9a-c285-4aca-838e-01c0ac6f31db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948616418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.948616418
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2371486020
Short name T45
Test name
Test status
Simulation time 100691907425 ps
CPU time 1049.22 seconds
Started Jul 14 05:24:59 PM PDT 24
Finished Jul 14 05:42:29 PM PDT 24
Peak memory 233440 kb
Host smart-9933928d-bf4a-415c-8c5d-cf2b413205af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371486020 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.2371486020
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2362350416
Short name T223
Test name
Test status
Simulation time 688936318 ps
CPU time 7.95 seconds
Started Jul 14 05:24:59 PM PDT 24
Finished Jul 14 05:25:08 PM PDT 24
Peak memory 216428 kb
Host smart-efd57474-2934-4257-b5e7-ea5b9c393619
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362350416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2362350416
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1048445873
Short name T296
Test name
Test status
Simulation time 297145487181 ps
CPU time 537.38 seconds
Started Jul 14 05:25:01 PM PDT 24
Finished Jul 14 05:33:59 PM PDT 24
Peak memory 239276 kb
Host smart-56504a67-a542-414e-a319-7e2ee72d3211
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048445873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1048445873
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1392767960
Short name T351
Test name
Test status
Simulation time 15714524401 ps
CPU time 42.56 seconds
Started Jul 14 05:25:01 PM PDT 24
Finished Jul 14 05:25:44 PM PDT 24
Peak memory 219288 kb
Host smart-c8f376b3-3db6-48da-9f40-3883681b04aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392767960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1392767960
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2521289010
Short name T356
Test name
Test status
Simulation time 349392059 ps
CPU time 10.23 seconds
Started Jul 14 05:25:00 PM PDT 24
Finished Jul 14 05:25:11 PM PDT 24
Peak memory 219260 kb
Host smart-f28e270a-f508-4fe2-902d-56135df0b717
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2521289010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2521289010
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2344287994
Short name T291
Test name
Test status
Simulation time 8967220354 ps
CPU time 68.29 seconds
Started Jul 14 05:24:58 PM PDT 24
Finished Jul 14 05:26:07 PM PDT 24
Peak memory 216368 kb
Host smart-f1c5aa8d-ea3d-4fa2-87b7-243a4a29de96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344287994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2344287994
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.4115413006
Short name T118
Test name
Test status
Simulation time 47231342923 ps
CPU time 268.27 seconds
Started Jul 14 05:25:01 PM PDT 24
Finished Jul 14 05:29:30 PM PDT 24
Peak memory 220624 kb
Host smart-a7642fb1-254f-4370-8e47-ecff200452e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115413006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.4115413006
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1405683578
Short name T300
Test name
Test status
Simulation time 4101759920 ps
CPU time 32.72 seconds
Started Jul 14 05:25:00 PM PDT 24
Finished Jul 14 05:25:33 PM PDT 24
Peak memory 216556 kb
Host smart-34c8c0ba-50f7-4247-8c69-3ff71492c36f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405683578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1405683578
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2115761986
Short name T168
Test name
Test status
Simulation time 187365670508 ps
CPU time 630.07 seconds
Started Jul 14 05:24:59 PM PDT 24
Finished Jul 14 05:35:30 PM PDT 24
Peak memory 235844 kb
Host smart-66b0773a-af9a-4812-a8b7-568ccaf01616
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115761986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2115761986
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.103147757
Short name T141
Test name
Test status
Simulation time 5244102565 ps
CPU time 45.74 seconds
Started Jul 14 05:25:02 PM PDT 24
Finished Jul 14 05:25:48 PM PDT 24
Peak memory 219264 kb
Host smart-10f6dad3-7f82-48d6-8c01-182c0e976358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103147757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.103147757
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.612977382
Short name T220
Test name
Test status
Simulation time 2861222648 ps
CPU time 26.69 seconds
Started Jul 14 05:25:04 PM PDT 24
Finished Jul 14 05:25:31 PM PDT 24
Peak memory 211340 kb
Host smart-ba647995-452d-40c4-9da5-9ca7258acbcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=612977382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.612977382
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3307869702
Short name T336
Test name
Test status
Simulation time 29936398716 ps
CPU time 62.5 seconds
Started Jul 14 05:24:58 PM PDT 24
Finished Jul 14 05:26:01 PM PDT 24
Peak memory 217456 kb
Host smart-033b5b68-5977-4b49-8471-f025236ba91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307869702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3307869702
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2181389182
Short name T276
Test name
Test status
Simulation time 57500863984 ps
CPU time 128.94 seconds
Started Jul 14 05:24:59 PM PDT 24
Finished Jul 14 05:27:09 PM PDT 24
Peak memory 220636 kb
Host smart-803395aa-cd14-4da0-a94b-71c180403cec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181389182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2181389182
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.383674428
Short name T319
Test name
Test status
Simulation time 10199683467 ps
CPU time 23.03 seconds
Started Jul 14 05:25:01 PM PDT 24
Finished Jul 14 05:25:25 PM PDT 24
Peak memory 217364 kb
Host smart-6b5ec49d-ea23-46e3-bb28-1ed4e15a5033
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383674428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.383674428
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.4195249804
Short name T260
Test name
Test status
Simulation time 260346742177 ps
CPU time 666.86 seconds
Started Jul 14 05:25:04 PM PDT 24
Finished Jul 14 05:36:12 PM PDT 24
Peak memory 215672 kb
Host smart-a2d3e4b0-f9da-4444-a560-a3ae1e75a9bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195249804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.4195249804
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1471990258
Short name T321
Test name
Test status
Simulation time 42273081534 ps
CPU time 51.5 seconds
Started Jul 14 05:25:00 PM PDT 24
Finished Jul 14 05:25:53 PM PDT 24
Peak memory 219236 kb
Host smart-f8522282-5198-4e38-879f-c419ba9df041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471990258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1471990258
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3120026244
Short name T326
Test name
Test status
Simulation time 3234058563 ps
CPU time 27.66 seconds
Started Jul 14 05:25:02 PM PDT 24
Finished Jul 14 05:25:30 PM PDT 24
Peak memory 219348 kb
Host smart-43a34944-367b-4809-bf1e-0577820de09a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3120026244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3120026244
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1574222215
Short name T145
Test name
Test status
Simulation time 4275711475 ps
CPU time 48.41 seconds
Started Jul 14 05:24:59 PM PDT 24
Finished Jul 14 05:25:48 PM PDT 24
Peak memory 215988 kb
Host smart-e6b13965-3ef8-4393-8a3b-d8fca847476a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574222215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1574222215
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.235777387
Short name T206
Test name
Test status
Simulation time 15737008680 ps
CPU time 130.25 seconds
Started Jul 14 05:25:00 PM PDT 24
Finished Jul 14 05:27:12 PM PDT 24
Peak memory 219864 kb
Host smart-41ccdb57-434a-4cf8-93e1-d8dfb441949b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235777387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.235777387
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3026528795
Short name T347
Test name
Test status
Simulation time 71402227837 ps
CPU time 36.39 seconds
Started Jul 14 05:25:09 PM PDT 24
Finished Jul 14 05:25:46 PM PDT 24
Peak memory 217496 kb
Host smart-a4022439-8e16-4bb0-a5df-9da2d666c074
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026528795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3026528795
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1261898407
Short name T181
Test name
Test status
Simulation time 94271323323 ps
CPU time 584.54 seconds
Started Jul 14 05:25:10 PM PDT 24
Finished Jul 14 05:34:55 PM PDT 24
Peak memory 234948 kb
Host smart-363c2875-2cc3-4294-8d72-5abd9c958b3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261898407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1261898407
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.867786204
Short name T275
Test name
Test status
Simulation time 8503046231 ps
CPU time 33.31 seconds
Started Jul 14 05:25:11 PM PDT 24
Finished Jul 14 05:25:45 PM PDT 24
Peak memory 219248 kb
Host smart-02158227-9c74-489d-8eb3-2d2e8410faf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867786204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.867786204
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1393424171
Short name T213
Test name
Test status
Simulation time 181038632 ps
CPU time 10.1 seconds
Started Jul 14 05:25:06 PM PDT 24
Finished Jul 14 05:25:18 PM PDT 24
Peak memory 219212 kb
Host smart-a336f484-fbe6-47d0-8994-fdeba7fe699a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1393424171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1393424171
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2923127865
Short name T178
Test name
Test status
Simulation time 2926475810 ps
CPU time 24.77 seconds
Started Jul 14 05:25:01 PM PDT 24
Finished Jul 14 05:25:26 PM PDT 24
Peak memory 216252 kb
Host smart-371dd369-65b3-4960-ba29-c3f7c2997a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923127865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2923127865
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.4217292445
Short name T245
Test name
Test status
Simulation time 12323364003 ps
CPU time 115.79 seconds
Started Jul 14 05:25:00 PM PDT 24
Finished Jul 14 05:26:57 PM PDT 24
Peak memory 219264 kb
Host smart-0401b15c-6f0f-406d-aa68-f4dcbaa4a142
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217292445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.4217292445
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2969197925
Short name T360
Test name
Test status
Simulation time 3354990864 ps
CPU time 29.14 seconds
Started Jul 14 05:25:08 PM PDT 24
Finished Jul 14 05:25:38 PM PDT 24
Peak memory 217296 kb
Host smart-8990ad00-6a6e-4a23-9b43-0affe238a07d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969197925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2969197925
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3323732910
Short name T133
Test name
Test status
Simulation time 36013625743 ps
CPU time 503.33 seconds
Started Jul 14 05:25:07 PM PDT 24
Finished Jul 14 05:33:32 PM PDT 24
Peak memory 229688 kb
Host smart-8e68c0b8-c442-47c2-93bc-1d34b904cc43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323732910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3323732910
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3901582366
Short name T209
Test name
Test status
Simulation time 13421793321 ps
CPU time 59.86 seconds
Started Jul 14 05:25:06 PM PDT 24
Finished Jul 14 05:26:08 PM PDT 24
Peak memory 219196 kb
Host smart-96593d3e-2be9-43e5-a62a-1a9cc949cb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901582366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3901582366
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3636719148
Short name T140
Test name
Test status
Simulation time 10372818999 ps
CPU time 29.44 seconds
Started Jul 14 05:25:04 PM PDT 24
Finished Jul 14 05:25:34 PM PDT 24
Peak memory 219240 kb
Host smart-e6f99d1b-4ef2-40ef-9f1d-b8f989f691d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3636719148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3636719148
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3741467765
Short name T242
Test name
Test status
Simulation time 3492896922 ps
CPU time 27.57 seconds
Started Jul 14 05:25:05 PM PDT 24
Finished Jul 14 05:25:33 PM PDT 24
Peak memory 216676 kb
Host smart-6ed29b0c-dfc9-40ea-91c4-f8d832fa908b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741467765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3741467765
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1227102118
Short name T281
Test name
Test status
Simulation time 16288188660 ps
CPU time 168.52 seconds
Started Jul 14 05:25:05 PM PDT 24
Finished Jul 14 05:27:54 PM PDT 24
Peak memory 221192 kb
Host smart-30f49ba0-857c-4dcc-8c8d-729ceefcd137
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227102118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1227102118
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2104738619
Short name T330
Test name
Test status
Simulation time 11564775333 ps
CPU time 26.79 seconds
Started Jul 14 05:25:06 PM PDT 24
Finished Jul 14 05:25:35 PM PDT 24
Peak memory 217352 kb
Host smart-0b2ec14f-8614-44d2-9b28-f71ee1694c47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104738619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2104738619
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2169397774
Short name T173
Test name
Test status
Simulation time 91187681347 ps
CPU time 287.57 seconds
Started Jul 14 05:25:06 PM PDT 24
Finished Jul 14 05:29:54 PM PDT 24
Peak memory 237316 kb
Host smart-213336bd-ff30-4337-be30-3ab978daf1a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169397774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2169397774
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3580787792
Short name T340
Test name
Test status
Simulation time 16789633100 ps
CPU time 68.23 seconds
Started Jul 14 05:25:08 PM PDT 24
Finished Jul 14 05:26:17 PM PDT 24
Peak memory 219256 kb
Host smart-504cbe43-a08f-4783-8f5b-d34a6a029258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580787792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3580787792
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.545859004
Short name T1
Test name
Test status
Simulation time 3942896523 ps
CPU time 20.55 seconds
Started Jul 14 05:25:06 PM PDT 24
Finished Jul 14 05:25:29 PM PDT 24
Peak memory 211640 kb
Host smart-1219a879-d6ca-4959-8a62-ebc8402aac2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=545859004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.545859004
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3750755052
Short name T193
Test name
Test status
Simulation time 7538118390 ps
CPU time 77.35 seconds
Started Jul 14 05:25:06 PM PDT 24
Finished Jul 14 05:26:25 PM PDT 24
Peak memory 217096 kb
Host smart-b5175623-b78c-4a5e-8501-8bcd57587d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750755052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3750755052
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1408792120
Short name T227
Test name
Test status
Simulation time 29959475440 ps
CPU time 271.46 seconds
Started Jul 14 05:25:06 PM PDT 24
Finished Jul 14 05:29:38 PM PDT 24
Peak memory 220648 kb
Host smart-88d0a1ae-9f37-45a6-b66b-c3b9953d2be8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408792120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1408792120
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3391220276
Short name T225
Test name
Test status
Simulation time 6546903407 ps
CPU time 19.75 seconds
Started Jul 14 05:25:15 PM PDT 24
Finished Jul 14 05:25:36 PM PDT 24
Peak memory 213220 kb
Host smart-eceaa9f5-23c9-4ef2-ae31-0892c31b591b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391220276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3391220276
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1509567586
Short name T292
Test name
Test status
Simulation time 250808359612 ps
CPU time 676.11 seconds
Started Jul 14 05:25:15 PM PDT 24
Finished Jul 14 05:36:32 PM PDT 24
Peak memory 236608 kb
Host smart-1efa524d-c1c0-43b0-8f63-1f84c2096548
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509567586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1509567586
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2799279317
Short name T192
Test name
Test status
Simulation time 8205811413 ps
CPU time 67.93 seconds
Started Jul 14 05:25:13 PM PDT 24
Finished Jul 14 05:26:21 PM PDT 24
Peak memory 219252 kb
Host smart-d4a7b38e-0c8a-4738-920b-95f92a5d6e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799279317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2799279317
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1994337314
Short name T269
Test name
Test status
Simulation time 4413021069 ps
CPU time 28.8 seconds
Started Jul 14 05:25:12 PM PDT 24
Finished Jul 14 05:25:41 PM PDT 24
Peak memory 217892 kb
Host smart-6b17c620-2648-4a14-b318-d54a52620f68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1994337314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1994337314
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3307543647
Short name T211
Test name
Test status
Simulation time 6437270088 ps
CPU time 54.86 seconds
Started Jul 14 05:25:11 PM PDT 24
Finished Jul 14 05:26:06 PM PDT 24
Peak memory 217184 kb
Host smart-af466faf-a80a-424c-afc3-808d5e3c584f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307543647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3307543647
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1851175545
Short name T148
Test name
Test status
Simulation time 16467133350 ps
CPU time 48.39 seconds
Started Jul 14 05:25:14 PM PDT 24
Finished Jul 14 05:26:02 PM PDT 24
Peak memory 219268 kb
Host smart-10e0384d-5b0c-46ee-9bf6-8c21d14feec0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851175545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1851175545
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.620662865
Short name T44
Test name
Test status
Simulation time 72182879913 ps
CPU time 2741.65 seconds
Started Jul 14 05:25:13 PM PDT 24
Finished Jul 14 06:10:55 PM PDT 24
Peak memory 232252 kb
Host smart-95950d91-ae5c-4ece-b9af-ff507caa48d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620662865 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.620662865
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3631926241
Short name T215
Test name
Test status
Simulation time 23602516852 ps
CPU time 23.94 seconds
Started Jul 14 05:25:16 PM PDT 24
Finished Jul 14 05:25:41 PM PDT 24
Peak memory 217376 kb
Host smart-95ad243a-5b15-492c-9410-d9453556a2cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631926241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3631926241
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2991803638
Short name T331
Test name
Test status
Simulation time 10241043416 ps
CPU time 359.75 seconds
Started Jul 14 05:25:12 PM PDT 24
Finished Jul 14 05:31:12 PM PDT 24
Peak memory 238396 kb
Host smart-9628c67c-40e0-4d9f-a2d8-09cf79e397a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991803638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2991803638
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1152314072
Short name T327
Test name
Test status
Simulation time 1712637090 ps
CPU time 19.83 seconds
Started Jul 14 05:25:13 PM PDT 24
Finished Jul 14 05:25:33 PM PDT 24
Peak memory 219224 kb
Host smart-8bcc886a-f57f-4d50-8c63-1c83a6492706
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1152314072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1152314072
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2996940120
Short name T270
Test name
Test status
Simulation time 27259040426 ps
CPU time 81.89 seconds
Started Jul 14 05:25:11 PM PDT 24
Finished Jul 14 05:26:33 PM PDT 24
Peak memory 216024 kb
Host smart-c93a1ae5-ca6a-4676-a9ca-26b33fd7b386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996940120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2996940120
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1128165904
Short name T142
Test name
Test status
Simulation time 70818706132 ps
CPU time 74.84 seconds
Started Jul 14 05:25:14 PM PDT 24
Finished Jul 14 05:26:29 PM PDT 24
Peak memory 219272 kb
Host smart-18fc0479-645d-4604-80d9-1c7ce81aa6ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128165904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1128165904
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.598051176
Short name T101
Test name
Test status
Simulation time 31411214930 ps
CPU time 1240.18 seconds
Started Jul 14 05:25:18 PM PDT 24
Finished Jul 14 05:45:59 PM PDT 24
Peak memory 233388 kb
Host smart-69b057ff-1872-4826-8d37-146e559b68bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598051176 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.598051176
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.4110755224
Short name T64
Test name
Test status
Simulation time 2057843993 ps
CPU time 21.04 seconds
Started Jul 14 05:25:16 PM PDT 24
Finished Jul 14 05:25:38 PM PDT 24
Peak memory 217276 kb
Host smart-26587aa9-be9e-4371-9b46-5b12de235eb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110755224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.4110755224
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2487503182
Short name T224
Test name
Test status
Simulation time 4954037188 ps
CPU time 151.9 seconds
Started Jul 14 05:25:17 PM PDT 24
Finished Jul 14 05:27:49 PM PDT 24
Peak memory 227660 kb
Host smart-4ca62ee1-8184-4591-af38-03dcf4e0c8a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487503182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2487503182
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.4082763289
Short name T238
Test name
Test status
Simulation time 7022202149 ps
CPU time 60.55 seconds
Started Jul 14 05:25:19 PM PDT 24
Finished Jul 14 05:26:20 PM PDT 24
Peak memory 219340 kb
Host smart-e8b13cf9-4cd6-41b8-9f42-0cf720d39f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082763289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.4082763289
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1906538464
Short name T263
Test name
Test status
Simulation time 767156155 ps
CPU time 10.62 seconds
Started Jul 14 05:25:18 PM PDT 24
Finished Jul 14 05:25:30 PM PDT 24
Peak memory 219192 kb
Host smart-f25c2a05-3de8-4260-be07-51474170672a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1906538464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1906538464
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.570009807
Short name T226
Test name
Test status
Simulation time 32693533932 ps
CPU time 93.3 seconds
Started Jul 14 05:25:19 PM PDT 24
Finished Jul 14 05:26:53 PM PDT 24
Peak memory 217488 kb
Host smart-ab2d600d-a846-473e-8d8b-60be36784113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570009807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.570009807
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2115154435
Short name T153
Test name
Test status
Simulation time 1384874970 ps
CPU time 21.71 seconds
Started Jul 14 05:25:19 PM PDT 24
Finished Jul 14 05:25:41 PM PDT 24
Peak memory 219100 kb
Host smart-956a0b80-a625-4112-a53c-43d91262360a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115154435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2115154435
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1539935184
Short name T9
Test name
Test status
Simulation time 3843282920 ps
CPU time 30.71 seconds
Started Jul 14 05:23:47 PM PDT 24
Finished Jul 14 05:24:19 PM PDT 24
Peak memory 217104 kb
Host smart-1062f057-04de-48d3-865b-c82eb3922b6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539935184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1539935184
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3501025574
Short name T315
Test name
Test status
Simulation time 2638189695 ps
CPU time 138.09 seconds
Started Jul 14 05:23:45 PM PDT 24
Finished Jul 14 05:26:04 PM PDT 24
Peak memory 219476 kb
Host smart-7dbf6131-7b66-4b81-be3f-88d0120a24e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501025574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3501025574
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1564673730
Short name T240
Test name
Test status
Simulation time 4013261882 ps
CPU time 44.01 seconds
Started Jul 14 05:23:44 PM PDT 24
Finished Jul 14 05:24:29 PM PDT 24
Peak memory 219360 kb
Host smart-907f44ec-4768-48bf-8b54-e80791872052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564673730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1564673730
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.250878919
Short name T170
Test name
Test status
Simulation time 3052112382 ps
CPU time 15.24 seconds
Started Jul 14 05:23:44 PM PDT 24
Finished Jul 14 05:24:01 PM PDT 24
Peak memory 218764 kb
Host smart-e466bfea-a723-47c0-b815-bdf3aba2fb89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=250878919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.250878919
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3482315443
Short name T328
Test name
Test status
Simulation time 1748386979 ps
CPU time 34.04 seconds
Started Jul 14 05:23:45 PM PDT 24
Finished Jul 14 05:24:20 PM PDT 24
Peak memory 216920 kb
Host smart-725b875b-9324-4d83-b775-1e7aee5b9d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482315443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3482315443
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1773297893
Short name T346
Test name
Test status
Simulation time 19598176004 ps
CPU time 95.89 seconds
Started Jul 14 05:23:47 PM PDT 24
Finished Jul 14 05:25:23 PM PDT 24
Peak memory 220028 kb
Host smart-00ec52d6-0068-4902-a356-341fe5880d0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773297893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1773297893
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3092220367
Short name T250
Test name
Test status
Simulation time 3511536947 ps
CPU time 28.17 seconds
Started Jul 14 05:25:26 PM PDT 24
Finished Jul 14 05:25:55 PM PDT 24
Peak memory 217244 kb
Host smart-3a6e72b2-c002-4f8f-8ad7-6ec77a30a154
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092220367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3092220367
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3069193311
Short name T4
Test name
Test status
Simulation time 27725223038 ps
CPU time 179.36 seconds
Started Jul 14 05:25:18 PM PDT 24
Finished Jul 14 05:28:18 PM PDT 24
Peak memory 239244 kb
Host smart-7bdce911-c4ec-4c80-86d0-fce4cd73d3e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069193311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3069193311
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1172523985
Short name T204
Test name
Test status
Simulation time 689206469 ps
CPU time 19.01 seconds
Started Jul 14 05:25:19 PM PDT 24
Finished Jul 14 05:25:39 PM PDT 24
Peak memory 219280 kb
Host smart-6abbb551-9f5c-4d50-bf6e-a7cbef5a1e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172523985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1172523985
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2340163325
Short name T323
Test name
Test status
Simulation time 4153309546 ps
CPU time 23.31 seconds
Started Jul 14 05:25:19 PM PDT 24
Finished Jul 14 05:25:44 PM PDT 24
Peak memory 219364 kb
Host smart-f449baef-d7c5-41a3-a402-4b4c120b98a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2340163325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2340163325
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2890370995
Short name T100
Test name
Test status
Simulation time 35356326523 ps
CPU time 62.51 seconds
Started Jul 14 05:25:18 PM PDT 24
Finished Jul 14 05:26:21 PM PDT 24
Peak memory 217060 kb
Host smart-ecd82499-9598-4936-ab64-09271e18ff91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890370995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2890370995
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3463560968
Short name T138
Test name
Test status
Simulation time 10034874933 ps
CPU time 38.7 seconds
Started Jul 14 05:25:17 PM PDT 24
Finished Jul 14 05:25:57 PM PDT 24
Peak memory 214756 kb
Host smart-164a7f9c-59a4-478a-9aee-4445860f9748
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463560968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3463560968
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2792776275
Short name T349
Test name
Test status
Simulation time 1440656715 ps
CPU time 17.29 seconds
Started Jul 14 05:25:24 PM PDT 24
Finished Jul 14 05:25:42 PM PDT 24
Peak memory 217224 kb
Host smart-3814c80a-5039-49a7-963f-ffda2d2fd1be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792776275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2792776275
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2627905400
Short name T187
Test name
Test status
Simulation time 26658303617 ps
CPU time 270.01 seconds
Started Jul 14 05:25:22 PM PDT 24
Finished Jul 14 05:29:53 PM PDT 24
Peak memory 224768 kb
Host smart-8b6db8cf-7d10-4a23-96f0-fd0581b65423
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627905400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2627905400
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.787627579
Short name T135
Test name
Test status
Simulation time 14236163804 ps
CPU time 40.72 seconds
Started Jul 14 05:25:23 PM PDT 24
Finished Jul 14 05:26:04 PM PDT 24
Peak memory 219268 kb
Host smart-80d34207-f980-4444-87f2-165ba9415a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787627579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.787627579
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2309433353
Short name T189
Test name
Test status
Simulation time 329348437 ps
CPU time 10.76 seconds
Started Jul 14 05:25:24 PM PDT 24
Finished Jul 14 05:25:36 PM PDT 24
Peak memory 219232 kb
Host smart-25b160da-42b4-48e8-84a6-08b03c65cb8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2309433353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2309433353
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2070245676
Short name T191
Test name
Test status
Simulation time 15413055168 ps
CPU time 80.79 seconds
Started Jul 14 05:25:24 PM PDT 24
Finished Jul 14 05:26:45 PM PDT 24
Peak memory 217712 kb
Host smart-4bc98550-c732-44d2-a313-655af300573f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070245676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2070245676
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.237689895
Short name T54
Test name
Test status
Simulation time 6539268581 ps
CPU time 65.77 seconds
Started Jul 14 05:25:25 PM PDT 24
Finished Jul 14 05:26:32 PM PDT 24
Peak memory 218200 kb
Host smart-ac25eb78-1d00-492c-a133-a606bbfec2ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237689895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.237689895
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1513621709
Short name T306
Test name
Test status
Simulation time 21200053270 ps
CPU time 29.68 seconds
Started Jul 14 05:25:23 PM PDT 24
Finished Jul 14 05:25:54 PM PDT 24
Peak memory 217296 kb
Host smart-d302dd25-b6c9-422a-81c0-484a0f0986d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513621709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1513621709
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1126895853
Short name T37
Test name
Test status
Simulation time 29467385641 ps
CPU time 305.16 seconds
Started Jul 14 05:25:25 PM PDT 24
Finished Jul 14 05:30:31 PM PDT 24
Peak memory 235272 kb
Host smart-eacf4f11-63ed-41f7-b414-3e4600151603
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126895853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1126895853
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1049769127
Short name T244
Test name
Test status
Simulation time 31737821562 ps
CPU time 55.92 seconds
Started Jul 14 05:25:27 PM PDT 24
Finished Jul 14 05:26:23 PM PDT 24
Peak memory 219232 kb
Host smart-4fb01af8-c143-4772-9cf2-d3a22cfdf00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049769127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1049769127
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1975876404
Short name T273
Test name
Test status
Simulation time 1272663132 ps
CPU time 18.22 seconds
Started Jul 14 05:25:25 PM PDT 24
Finished Jul 14 05:25:43 PM PDT 24
Peak memory 219308 kb
Host smart-8cf901f0-33f2-4477-aa7f-caeb01c6e9f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1975876404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1975876404
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3466770873
Short name T357
Test name
Test status
Simulation time 11628060256 ps
CPU time 36.84 seconds
Started Jul 14 05:25:26 PM PDT 24
Finished Jul 14 05:26:03 PM PDT 24
Peak memory 217420 kb
Host smart-aef94a6b-0f4d-4e56-bdbf-f363c4a21be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466770873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3466770873
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.4188343383
Short name T214
Test name
Test status
Simulation time 1319387499 ps
CPU time 21.28 seconds
Started Jul 14 05:25:26 PM PDT 24
Finished Jul 14 05:25:48 PM PDT 24
Peak memory 219124 kb
Host smart-623fbb4a-5d6c-4822-8649-c66e0f5a2e32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188343383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.4188343383
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.4176797900
Short name T42
Test name
Test status
Simulation time 322846821981 ps
CPU time 3253.54 seconds
Started Jul 14 05:25:22 PM PDT 24
Finished Jul 14 06:19:37 PM PDT 24
Peak memory 246316 kb
Host smart-6df96238-0365-4939-81c8-3b0e781960b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176797900 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.4176797900
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3645200753
Short name T202
Test name
Test status
Simulation time 9118153225 ps
CPU time 18.32 seconds
Started Jul 14 05:25:35 PM PDT 24
Finished Jul 14 05:25:54 PM PDT 24
Peak memory 217400 kb
Host smart-6fd4d9d1-74a0-44b1-9a44-1bdf7746be34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645200753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3645200753
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1163634697
Short name T196
Test name
Test status
Simulation time 9523812956 ps
CPU time 229.63 seconds
Started Jul 14 05:25:28 PM PDT 24
Finished Jul 14 05:29:18 PM PDT 24
Peak memory 219156 kb
Host smart-ccbaf1e1-4953-4725-89e4-0bdfc02e4aba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163634697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1163634697
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1850971444
Short name T26
Test name
Test status
Simulation time 21886498667 ps
CPU time 51.39 seconds
Started Jul 14 05:25:29 PM PDT 24
Finished Jul 14 05:26:21 PM PDT 24
Peak memory 219260 kb
Host smart-737b187d-7eb8-4b84-95f5-4107c66fade6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850971444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1850971444
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3052321191
Short name T361
Test name
Test status
Simulation time 2737635286 ps
CPU time 25.13 seconds
Started Jul 14 05:25:30 PM PDT 24
Finished Jul 14 05:25:56 PM PDT 24
Peak memory 211556 kb
Host smart-52946000-ad0c-482d-8944-0fc801dff1ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3052321191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3052321191
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3809912961
Short name T253
Test name
Test status
Simulation time 1423974615 ps
CPU time 19.94 seconds
Started Jul 14 05:25:30 PM PDT 24
Finished Jul 14 05:25:51 PM PDT 24
Peak memory 216532 kb
Host smart-15ecdf51-d501-41c9-bc59-60c6df73d109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809912961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3809912961
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2327026358
Short name T123
Test name
Test status
Simulation time 13103983581 ps
CPU time 67.44 seconds
Started Jul 14 05:25:30 PM PDT 24
Finished Jul 14 05:26:38 PM PDT 24
Peak memory 219364 kb
Host smart-047e5411-9557-42db-9323-530be907f5c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327026358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2327026358
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3869137408
Short name T203
Test name
Test status
Simulation time 113437860340 ps
CPU time 394.12 seconds
Started Jul 14 05:25:34 PM PDT 24
Finished Jul 14 05:32:09 PM PDT 24
Peak memory 219240 kb
Host smart-eef53488-eadb-4a99-9e08-21e7c62c446d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869137408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3869137408
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.167632095
Short name T36
Test name
Test status
Simulation time 342724778 ps
CPU time 18.96 seconds
Started Jul 14 05:25:37 PM PDT 24
Finished Jul 14 05:25:57 PM PDT 24
Peak memory 219248 kb
Host smart-773def95-b8c2-46dc-ae17-a700edf0f88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167632095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.167632095
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2020226906
Short name T314
Test name
Test status
Simulation time 187289092 ps
CPU time 10.48 seconds
Started Jul 14 05:25:37 PM PDT 24
Finished Jul 14 05:25:49 PM PDT 24
Peak memory 219308 kb
Host smart-97cc4611-92fd-43e3-9c9f-9defcb6cf29e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2020226906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2020226906
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2761488092
Short name T75
Test name
Test status
Simulation time 1420985743 ps
CPU time 20.46 seconds
Started Jul 14 05:25:36 PM PDT 24
Finished Jul 14 05:25:57 PM PDT 24
Peak memory 216276 kb
Host smart-057a17fc-4af9-4086-85ca-0a9d2d09eee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761488092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2761488092
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1670711438
Short name T166
Test name
Test status
Simulation time 42461490027 ps
CPU time 132.02 seconds
Started Jul 14 05:25:38 PM PDT 24
Finished Jul 14 05:27:50 PM PDT 24
Peak memory 219360 kb
Host smart-225e90f0-7957-474d-8533-5fe555be63a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670711438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1670711438
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.673022798
Short name T63
Test name
Test status
Simulation time 3410714827 ps
CPU time 28.64 seconds
Started Jul 14 05:25:43 PM PDT 24
Finished Jul 14 05:26:12 PM PDT 24
Peak memory 217188 kb
Host smart-920c4041-8c10-496a-8d17-18c451568ca7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673022798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.673022798
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.877817028
Short name T355
Test name
Test status
Simulation time 306403406287 ps
CPU time 308.14 seconds
Started Jul 14 05:25:41 PM PDT 24
Finished Jul 14 05:30:50 PM PDT 24
Peak memory 216848 kb
Host smart-271b476f-dd96-4c99-9bcc-e688e093ddaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877817028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.877817028
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.43876935
Short name T171
Test name
Test status
Simulation time 7336805176 ps
CPU time 65.4 seconds
Started Jul 14 05:25:40 PM PDT 24
Finished Jul 14 05:26:45 PM PDT 24
Peak memory 219296 kb
Host smart-3cea119a-943b-4d81-9eaa-2d1432fb76ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43876935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.43876935
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3990184751
Short name T309
Test name
Test status
Simulation time 1807114448 ps
CPU time 21.02 seconds
Started Jul 14 05:25:42 PM PDT 24
Finished Jul 14 05:26:03 PM PDT 24
Peak memory 219276 kb
Host smart-98431198-3fbd-4499-b311-1b36473a1d5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3990184751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3990184751
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2061072636
Short name T198
Test name
Test status
Simulation time 69141213879 ps
CPU time 58.45 seconds
Started Jul 14 05:25:48 PM PDT 24
Finished Jul 14 05:26:48 PM PDT 24
Peak memory 216648 kb
Host smart-71d195f8-8228-4138-95b3-939bfd531d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061072636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2061072636
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.715747542
Short name T243
Test name
Test status
Simulation time 12070224747 ps
CPU time 27.53 seconds
Started Jul 14 05:25:42 PM PDT 24
Finished Jul 14 05:26:10 PM PDT 24
Peak memory 217516 kb
Host smart-a8ca86b1-043e-4ca2-8a5d-d0b063025b70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715747542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.715747542
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.324502613
Short name T232
Test name
Test status
Simulation time 151137578231 ps
CPU time 568.38 seconds
Started Jul 14 05:25:42 PM PDT 24
Finished Jul 14 05:35:11 PM PDT 24
Peak memory 226140 kb
Host smart-380a700e-ccfe-4a89-9b45-edf992e45ecc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324502613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.324502613
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3936790609
Short name T183
Test name
Test status
Simulation time 10914001405 ps
CPU time 52.19 seconds
Started Jul 14 05:25:43 PM PDT 24
Finished Jul 14 05:26:35 PM PDT 24
Peak memory 219236 kb
Host smart-033167ab-605f-43f6-b442-00b4b32b2fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936790609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3936790609
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2927098238
Short name T201
Test name
Test status
Simulation time 174925966 ps
CPU time 10.29 seconds
Started Jul 14 05:25:44 PM PDT 24
Finished Jul 14 05:25:55 PM PDT 24
Peak memory 219212 kb
Host smart-d383b419-4c7f-47b9-9421-4ac6fd87744b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2927098238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2927098238
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3335302385
Short name T6
Test name
Test status
Simulation time 62520350348 ps
CPU time 44.44 seconds
Started Jul 14 05:25:48 PM PDT 24
Finished Jul 14 05:26:34 PM PDT 24
Peak memory 215376 kb
Host smart-f6046c4a-e9e3-4af0-a5ab-84efc2993628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335302385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3335302385
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1493016638
Short name T200
Test name
Test status
Simulation time 53499419265 ps
CPU time 142.18 seconds
Started Jul 14 05:25:44 PM PDT 24
Finished Jul 14 05:28:07 PM PDT 24
Peak memory 220500 kb
Host smart-84c37e93-8bdb-4260-89f1-9be1b6f60dab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493016638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1493016638
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.797047825
Short name T325
Test name
Test status
Simulation time 403964401 ps
CPU time 8.48 seconds
Started Jul 14 05:25:49 PM PDT 24
Finished Jul 14 05:25:59 PM PDT 24
Peak memory 217064 kb
Host smart-5fbaefe6-4e17-475d-a051-b5d19cbc79a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797047825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.797047825
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1345140858
Short name T290
Test name
Test status
Simulation time 53707811803 ps
CPU time 652.24 seconds
Started Jul 14 05:25:46 PM PDT 24
Finished Jul 14 05:36:38 PM PDT 24
Peak memory 237904 kb
Host smart-3d9b4765-a3e5-4f9c-83d4-faf9da6ff0ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345140858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1345140858
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.536645576
Short name T154
Test name
Test status
Simulation time 332756738 ps
CPU time 19.04 seconds
Started Jul 14 05:25:49 PM PDT 24
Finished Jul 14 05:26:09 PM PDT 24
Peak memory 219284 kb
Host smart-897e220f-0963-4792-9fc3-02b156d75d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536645576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.536645576
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.973254286
Short name T139
Test name
Test status
Simulation time 5814787494 ps
CPU time 26.7 seconds
Started Jul 14 05:25:46 PM PDT 24
Finished Jul 14 05:26:13 PM PDT 24
Peak memory 211924 kb
Host smart-217083b4-c188-4261-acd8-1faf0dccb1cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=973254286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.973254286
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.588509520
Short name T162
Test name
Test status
Simulation time 71925646153 ps
CPU time 69.9 seconds
Started Jul 14 05:25:48 PM PDT 24
Finished Jul 14 05:26:59 PM PDT 24
Peak memory 218040 kb
Host smart-96a1c47a-2f54-4002-a20b-a4110a551d95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588509520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.588509520
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.430030280
Short name T222
Test name
Test status
Simulation time 943856202 ps
CPU time 14.83 seconds
Started Jul 14 05:25:48 PM PDT 24
Finished Jul 14 05:26:04 PM PDT 24
Peak memory 213236 kb
Host smart-50ada00c-8c8a-464a-b4a0-fd7914486ae5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430030280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.430030280
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1920621156
Short name T289
Test name
Test status
Simulation time 25230781195 ps
CPU time 206.39 seconds
Started Jul 14 05:25:48 PM PDT 24
Finished Jul 14 05:29:16 PM PDT 24
Peak memory 224664 kb
Host smart-7a0ffb9d-f415-47ba-9bf1-5d938d3668ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920621156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1920621156
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2861254672
Short name T210
Test name
Test status
Simulation time 7584889873 ps
CPU time 66.71 seconds
Started Jul 14 05:25:49 PM PDT 24
Finished Jul 14 05:26:57 PM PDT 24
Peak memory 219348 kb
Host smart-80717c77-ce89-465b-a334-1e67d997e91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861254672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2861254672
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3385871874
Short name T97
Test name
Test status
Simulation time 8592942555 ps
CPU time 29.36 seconds
Started Jul 14 05:25:47 PM PDT 24
Finished Jul 14 05:26:17 PM PDT 24
Peak memory 211904 kb
Host smart-3109eb10-3caf-4aa4-9933-dff5c4bdbe2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3385871874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3385871874
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2936349686
Short name T216
Test name
Test status
Simulation time 24257767026 ps
CPU time 68.05 seconds
Started Jul 14 05:25:47 PM PDT 24
Finished Jul 14 05:26:56 PM PDT 24
Peak memory 217312 kb
Host smart-1ed213b9-68cd-47e0-8fe3-8561f573bdca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936349686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2936349686
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3194390666
Short name T117
Test name
Test status
Simulation time 18127563258 ps
CPU time 95.66 seconds
Started Jul 14 05:25:49 PM PDT 24
Finished Jul 14 05:27:26 PM PDT 24
Peak memory 219784 kb
Host smart-7a313d8c-32ff-46b8-9e9d-a029ea03fe7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194390666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3194390666
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1027571152
Short name T65
Test name
Test status
Simulation time 167780111 ps
CPU time 8.7 seconds
Started Jul 14 05:25:53 PM PDT 24
Finished Jul 14 05:26:02 PM PDT 24
Peak memory 217024 kb
Host smart-d1460566-6231-4adc-bbc6-f05506467022
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027571152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1027571152
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.829958389
Short name T30
Test name
Test status
Simulation time 288004561994 ps
CPU time 787.58 seconds
Started Jul 14 05:25:55 PM PDT 24
Finished Jul 14 05:39:03 PM PDT 24
Peak memory 224040 kb
Host smart-81ae9c02-55bd-44b2-a95b-19b4353673e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829958389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.829958389
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3787774685
Short name T337
Test name
Test status
Simulation time 676177796 ps
CPU time 19.51 seconds
Started Jul 14 05:25:54 PM PDT 24
Finished Jul 14 05:26:13 PM PDT 24
Peak memory 219240 kb
Host smart-9ee40fc4-8186-4362-9a37-851559da310c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787774685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3787774685
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2332463884
Short name T282
Test name
Test status
Simulation time 266297265 ps
CPU time 12.56 seconds
Started Jul 14 05:25:47 PM PDT 24
Finished Jul 14 05:26:00 PM PDT 24
Peak memory 219204 kb
Host smart-0cdb0fe0-547e-4cf6-af5d-0c94333493a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2332463884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2332463884
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3490311000
Short name T77
Test name
Test status
Simulation time 5529244463 ps
CPU time 30.14 seconds
Started Jul 14 05:25:50 PM PDT 24
Finished Jul 14 05:26:21 PM PDT 24
Peak memory 217208 kb
Host smart-72ec3f9d-9f04-4d9d-8a38-e95184ca6711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490311000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3490311000
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.4070836922
Short name T157
Test name
Test status
Simulation time 93380078302 ps
CPU time 230.3 seconds
Started Jul 14 05:25:48 PM PDT 24
Finished Jul 14 05:29:40 PM PDT 24
Peak memory 221372 kb
Host smart-96446592-ee5a-405c-9501-978ba545cb58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070836922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.4070836922
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3750301842
Short name T25
Test name
Test status
Simulation time 25741117182 ps
CPU time 33.78 seconds
Started Jul 14 05:23:44 PM PDT 24
Finished Jul 14 05:24:19 PM PDT 24
Peak memory 217352 kb
Host smart-c49d8f30-927c-4701-96bc-80684bf5d6db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750301842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3750301842
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3563935965
Short name T284
Test name
Test status
Simulation time 56741922131 ps
CPU time 643.83 seconds
Started Jul 14 05:23:43 PM PDT 24
Finished Jul 14 05:34:27 PM PDT 24
Peak memory 216704 kb
Host smart-f8de884c-6303-45fd-b783-9d0c603716a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563935965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3563935965
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.4084078406
Short name T39
Test name
Test status
Simulation time 28933248637 ps
CPU time 61.92 seconds
Started Jul 14 05:23:46 PM PDT 24
Finished Jul 14 05:24:49 PM PDT 24
Peak memory 219224 kb
Host smart-2efb6d41-0879-4cf3-a3e2-5f23715add73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084078406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.4084078406
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2250658023
Short name T317
Test name
Test status
Simulation time 705183810 ps
CPU time 14.7 seconds
Started Jul 14 05:23:43 PM PDT 24
Finished Jul 14 05:23:59 PM PDT 24
Peak memory 218384 kb
Host smart-eb858140-60e7-4623-bfec-d5d1a83fb903
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2250658023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2250658023
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3214955650
Short name T233
Test name
Test status
Simulation time 346569205 ps
CPU time 19.92 seconds
Started Jul 14 05:23:47 PM PDT 24
Finished Jul 14 05:24:08 PM PDT 24
Peak memory 216456 kb
Host smart-f723d541-fa14-4559-bb94-f8e45c150e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214955650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3214955650
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3410970166
Short name T308
Test name
Test status
Simulation time 16133316450 ps
CPU time 145.73 seconds
Started Jul 14 05:23:46 PM PDT 24
Finished Jul 14 05:26:13 PM PDT 24
Peak memory 221140 kb
Host smart-3d1c3bd2-3938-4202-8959-4fab624f272b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410970166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3410970166
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3398394900
Short name T129
Test name
Test status
Simulation time 12755481040 ps
CPU time 28.34 seconds
Started Jul 14 05:23:46 PM PDT 24
Finished Jul 14 05:24:15 PM PDT 24
Peak memory 217400 kb
Host smart-5ad6dbf1-d151-429c-96e7-6548eaf97f0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398394900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3398394900
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1730792428
Short name T179
Test name
Test status
Simulation time 15798979799 ps
CPU time 141.59 seconds
Started Jul 14 05:23:42 PM PDT 24
Finished Jul 14 05:26:04 PM PDT 24
Peak memory 227352 kb
Host smart-b45c4681-f5ce-4eb0-bd6b-0e697e697dff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730792428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1730792428
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1369672317
Short name T185
Test name
Test status
Simulation time 332373786 ps
CPU time 19.12 seconds
Started Jul 14 05:23:45 PM PDT 24
Finished Jul 14 05:24:05 PM PDT 24
Peak memory 219280 kb
Host smart-7b462518-67d6-4ffd-8461-1d4088d98b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369672317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1369672317
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2201130426
Short name T298
Test name
Test status
Simulation time 4808961208 ps
CPU time 23.34 seconds
Started Jul 14 05:23:42 PM PDT 24
Finished Jul 14 05:24:06 PM PDT 24
Peak memory 219336 kb
Host smart-c518bf44-eb91-4a0a-8def-75afebce8711
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2201130426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2201130426
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3787693092
Short name T218
Test name
Test status
Simulation time 35744195031 ps
CPU time 64.33 seconds
Started Jul 14 05:23:44 PM PDT 24
Finished Jul 14 05:24:50 PM PDT 24
Peak memory 215468 kb
Host smart-3539bc09-bbc7-4227-bd80-0ba723275976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787693092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3787693092
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2063232764
Short name T124
Test name
Test status
Simulation time 34369563917 ps
CPU time 77.78 seconds
Started Jul 14 05:23:46 PM PDT 24
Finished Jul 14 05:25:05 PM PDT 24
Peak memory 219264 kb
Host smart-1dcbd075-ad42-4b96-9585-4c480f2578c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063232764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2063232764
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.154569281
Short name T12
Test name
Test status
Simulation time 56380034751 ps
CPU time 1116.19 seconds
Started Jul 14 05:23:44 PM PDT 24
Finished Jul 14 05:42:22 PM PDT 24
Peak memory 235884 kb
Host smart-6bab9e52-45dc-4e9a-b8e3-f6acf42de12d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154569281 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.154569281
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3249727869
Short name T318
Test name
Test status
Simulation time 170753988 ps
CPU time 8.55 seconds
Started Jul 14 05:23:44 PM PDT 24
Finished Jul 14 05:23:54 PM PDT 24
Peak memory 217076 kb
Host smart-1c4aeb23-4bf4-4aa4-aefd-aff03079bcea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249727869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3249727869
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.4294416577
Short name T33
Test name
Test status
Simulation time 164412219313 ps
CPU time 368.68 seconds
Started Jul 14 05:23:47 PM PDT 24
Finished Jul 14 05:29:57 PM PDT 24
Peak memory 236000 kb
Host smart-2fc65e35-d92f-4003-9578-2497736b8145
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294416577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.4294416577
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.99995108
Short name T143
Test name
Test status
Simulation time 28125039865 ps
CPU time 50.19 seconds
Started Jul 14 05:23:48 PM PDT 24
Finished Jul 14 05:24:39 PM PDT 24
Peak memory 219256 kb
Host smart-ea63a40f-4cfa-473f-b75d-3b897395a36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99995108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.99995108
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2136768555
Short name T20
Test name
Test status
Simulation time 4531807577 ps
CPU time 15.74 seconds
Started Jul 14 05:23:44 PM PDT 24
Finished Jul 14 05:24:01 PM PDT 24
Peak memory 217632 kb
Host smart-bbae16f6-6f32-4ced-b461-9b01134608ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2136768555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2136768555
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1126589322
Short name T322
Test name
Test status
Simulation time 7199403008 ps
CPU time 75.34 seconds
Started Jul 14 05:23:43 PM PDT 24
Finished Jul 14 05:25:00 PM PDT 24
Peak memory 216664 kb
Host smart-83652e48-b2d2-432b-a176-e8310fc3ead3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126589322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1126589322
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.6178856
Short name T151
Test name
Test status
Simulation time 3957613342 ps
CPU time 54.54 seconds
Started Jul 14 05:23:48 PM PDT 24
Finished Jul 14 05:24:43 PM PDT 24
Peak memory 229624 kb
Host smart-3024394a-5c55-4ddf-adab-7a6c97c645d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6178856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.rom_ctrl_stress_all.6178856
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2841708400
Short name T307
Test name
Test status
Simulation time 167319867 ps
CPU time 8.08 seconds
Started Jul 14 05:23:56 PM PDT 24
Finished Jul 14 05:24:04 PM PDT 24
Peak memory 217040 kb
Host smart-ccac9c9a-429e-43ba-86f5-da5152eb1aae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841708400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2841708400
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1861613360
Short name T32
Test name
Test status
Simulation time 8513132856 ps
CPU time 152.48 seconds
Started Jul 14 05:23:49 PM PDT 24
Finished Jul 14 05:26:22 PM PDT 24
Peak memory 225468 kb
Host smart-ef8936eb-6c7c-43b9-8195-52339619f027
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861613360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1861613360
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3708430374
Short name T163
Test name
Test status
Simulation time 16056579864 ps
CPU time 65.42 seconds
Started Jul 14 05:23:50 PM PDT 24
Finished Jul 14 05:24:56 PM PDT 24
Peak memory 219340 kb
Host smart-64d2128e-e08c-440d-ad84-d65dd2f9f5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708430374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3708430374
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3591824293
Short name T259
Test name
Test status
Simulation time 7515152059 ps
CPU time 31.93 seconds
Started Jul 14 05:23:49 PM PDT 24
Finished Jul 14 05:24:21 PM PDT 24
Peak memory 211932 kb
Host smart-cda37a33-88d9-468a-a2b7-d21cf99490e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3591824293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3591824293
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1405339192
Short name T76
Test name
Test status
Simulation time 3398137580 ps
CPU time 23.73 seconds
Started Jul 14 05:23:46 PM PDT 24
Finished Jul 14 05:24:10 PM PDT 24
Peak memory 215604 kb
Host smart-ee93757c-21e4-4c70-8f76-234edf0611b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405339192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1405339192
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2048423094
Short name T247
Test name
Test status
Simulation time 45394928000 ps
CPU time 80.18 seconds
Started Jul 14 05:23:51 PM PDT 24
Finished Jul 14 05:25:12 PM PDT 24
Peak memory 219340 kb
Host smart-67b4518e-27bb-48a6-a264-e02e041de45e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048423094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2048423094
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1234837348
Short name T252
Test name
Test status
Simulation time 6952152207 ps
CPU time 17.97 seconds
Started Jul 14 05:23:49 PM PDT 24
Finished Jul 14 05:24:08 PM PDT 24
Peak memory 217540 kb
Host smart-4b22f2d7-6c34-4460-aa3d-f1a2d8c47556
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234837348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1234837348
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1344437917
Short name T137
Test name
Test status
Simulation time 46089023124 ps
CPU time 245.74 seconds
Started Jul 14 05:23:51 PM PDT 24
Finished Jul 14 05:27:57 PM PDT 24
Peak memory 238900 kb
Host smart-249df492-5fc1-4820-b07a-773e08bd5907
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344437917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1344437917
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2842646885
Short name T261
Test name
Test status
Simulation time 688371888 ps
CPU time 19.16 seconds
Started Jul 14 05:23:51 PM PDT 24
Finished Jul 14 05:24:11 PM PDT 24
Peak memory 219228 kb
Host smart-d337698e-5c1a-4362-a621-8d9a3d475f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842646885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2842646885
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1483121996
Short name T152
Test name
Test status
Simulation time 928735658 ps
CPU time 10.6 seconds
Started Jul 14 05:23:50 PM PDT 24
Finished Jul 14 05:24:01 PM PDT 24
Peak memory 219184 kb
Host smart-8ca53026-89c6-4152-ac07-a5f59da9cf01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1483121996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1483121996
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3227893
Short name T15
Test name
Test status
Simulation time 366199931 ps
CPU time 19.84 seconds
Started Jul 14 05:23:55 PM PDT 24
Finished Jul 14 05:24:16 PM PDT 24
Peak memory 216372 kb
Host smart-cc726a7b-e241-44a3-891e-4bafdab198f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3227893
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1763968679
Short name T176
Test name
Test status
Simulation time 24230208183 ps
CPU time 106.12 seconds
Started Jul 14 05:23:51 PM PDT 24
Finished Jul 14 05:25:38 PM PDT 24
Peak memory 220428 kb
Host smart-4813fd8a-083e-4a67-90ac-747c07877e1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763968679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1763968679
Directory /workspace/9.rom_ctrl_stress_all/latest
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