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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.31 96.89 92.13 97.68 100.00 98.62 97.45 98.37


Total test records in report: 461
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T308 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1387608374 Jul 15 05:23:36 PM PDT 24 Jul 15 05:24:13 PM PDT 24 4796347428 ps
T309 /workspace/coverage/default/14.rom_ctrl_stress_all.3412642676 Jul 15 05:21:31 PM PDT 24 Jul 15 05:22:19 PM PDT 24 32639557402 ps
T310 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.372820477 Jul 15 05:24:43 PM PDT 24 Jul 15 05:25:26 PM PDT 24 7723329185 ps
T311 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2495820630 Jul 15 05:20:09 PM PDT 24 Jul 15 05:20:49 PM PDT 24 3119057872 ps
T312 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.946766702 Jul 15 05:23:50 PM PDT 24 Jul 15 05:24:03 PM PDT 24 272426984 ps
T30 /workspace/coverage/default/2.rom_ctrl_sec_cm.4102630447 Jul 15 05:20:04 PM PDT 24 Jul 15 05:23:57 PM PDT 24 12453547976 ps
T313 /workspace/coverage/default/2.rom_ctrl_smoke.515943691 Jul 15 05:20:01 PM PDT 24 Jul 15 05:21:01 PM PDT 24 26796537978 ps
T314 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1949768506 Jul 15 05:23:36 PM PDT 24 Jul 15 05:24:09 PM PDT 24 12094858099 ps
T315 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2468671220 Jul 15 05:23:35 PM PDT 24 Jul 15 05:29:28 PM PDT 24 26589487038 ps
T316 /workspace/coverage/default/38.rom_ctrl_stress_all.202159728 Jul 15 05:23:59 PM PDT 24 Jul 15 05:24:35 PM PDT 24 1324856524 ps
T317 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3041349035 Jul 15 05:22:03 PM PDT 24 Jul 15 05:22:36 PM PDT 24 3875017553 ps
T318 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.4199156855 Jul 15 05:22:36 PM PDT 24 Jul 15 05:22:56 PM PDT 24 346569516 ps
T319 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.736075165 Jul 15 05:23:51 PM PDT 24 Jul 15 05:33:58 PM PDT 24 188885499758 ps
T320 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2887134088 Jul 15 05:24:06 PM PDT 24 Jul 15 05:24:18 PM PDT 24 186117610 ps
T321 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.20528738 Jul 15 05:23:51 PM PDT 24 Jul 15 05:24:11 PM PDT 24 1500881115 ps
T322 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1074516741 Jul 15 05:23:19 PM PDT 24 Jul 15 05:31:53 PM PDT 24 91192861908 ps
T323 /workspace/coverage/default/34.rom_ctrl_stress_all.224252113 Jul 15 05:23:35 PM PDT 24 Jul 15 05:24:40 PM PDT 24 37169393039 ps
T324 /workspace/coverage/default/49.rom_ctrl_alert_test.3599642810 Jul 15 05:24:58 PM PDT 24 Jul 15 05:25:28 PM PDT 24 13733168655 ps
T325 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2421469274 Jul 15 05:23:59 PM PDT 24 Jul 15 05:29:18 PM PDT 24 72865665041 ps
T48 /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1100512441 Jul 15 05:23:50 PM PDT 24 Jul 15 05:40:56 PM PDT 24 26649252348 ps
T326 /workspace/coverage/default/0.rom_ctrl_smoke.3189925320 Jul 15 05:19:39 PM PDT 24 Jul 15 05:20:09 PM PDT 24 2361137407 ps
T327 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2585660555 Jul 15 05:21:01 PM PDT 24 Jul 15 05:21:56 PM PDT 24 47430885158 ps
T328 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.845131623 Jul 15 05:22:44 PM PDT 24 Jul 15 05:22:59 PM PDT 24 1215837111 ps
T329 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3455119131 Jul 15 05:24:23 PM PDT 24 Jul 15 05:28:34 PM PDT 24 12318807257 ps
T330 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1481867556 Jul 15 05:24:06 PM PDT 24 Jul 15 05:34:05 PM PDT 24 56951753057 ps
T331 /workspace/coverage/default/37.rom_ctrl_alert_test.2225972206 Jul 15 05:23:49 PM PDT 24 Jul 15 05:24:24 PM PDT 24 4283786710 ps
T332 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2819088819 Jul 15 05:24:49 PM PDT 24 Jul 15 05:31:32 PM PDT 24 107961041123 ps
T333 /workspace/coverage/default/30.rom_ctrl_alert_test.1559540196 Jul 15 05:23:20 PM PDT 24 Jul 15 05:23:45 PM PDT 24 11868160068 ps
T334 /workspace/coverage/default/15.rom_ctrl_stress_all.170786761 Jul 15 05:21:32 PM PDT 24 Jul 15 05:21:50 PM PDT 24 427237240 ps
T335 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.194430118 Jul 15 05:20:16 PM PDT 24 Jul 15 05:20:40 PM PDT 24 8615072972 ps
T336 /workspace/coverage/default/37.rom_ctrl_stress_all.3394216675 Jul 15 05:23:49 PM PDT 24 Jul 15 05:24:21 PM PDT 24 2270844661 ps
T337 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2073677922 Jul 15 05:22:34 PM PDT 24 Jul 15 05:30:55 PM PDT 24 40208681009 ps
T338 /workspace/coverage/default/13.rom_ctrl_smoke.1842056046 Jul 15 05:21:25 PM PDT 24 Jul 15 05:22:05 PM PDT 24 31340156351 ps
T339 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3144522171 Jul 15 05:22:26 PM PDT 24 Jul 15 05:22:58 PM PDT 24 8200774591 ps
T340 /workspace/coverage/default/36.rom_ctrl_smoke.2932549778 Jul 15 05:23:44 PM PDT 24 Jul 15 05:24:13 PM PDT 24 2583548135 ps
T341 /workspace/coverage/default/42.rom_ctrl_alert_test.3335904505 Jul 15 05:24:29 PM PDT 24 Jul 15 05:24:46 PM PDT 24 4590639923 ps
T342 /workspace/coverage/default/40.rom_ctrl_smoke.1098597832 Jul 15 05:24:06 PM PDT 24 Jul 15 05:24:33 PM PDT 24 684941987 ps
T343 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.4024002448 Jul 15 05:24:42 PM PDT 24 Jul 15 05:25:05 PM PDT 24 11244472774 ps
T344 /workspace/coverage/default/48.rom_ctrl_alert_test.511206927 Jul 15 05:24:59 PM PDT 24 Jul 15 05:25:07 PM PDT 24 346299929 ps
T345 /workspace/coverage/default/5.rom_ctrl_stress_all.2961485260 Jul 15 05:20:24 PM PDT 24 Jul 15 05:21:48 PM PDT 24 5629040436 ps
T346 /workspace/coverage/default/38.rom_ctrl_smoke.737499171 Jul 15 05:23:58 PM PDT 24 Jul 15 05:24:31 PM PDT 24 1904254603 ps
T92 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3108149945 Jul 15 05:24:37 PM PDT 24 Jul 15 05:25:05 PM PDT 24 10370116340 ps
T93 /workspace/coverage/default/37.rom_ctrl_smoke.1379825931 Jul 15 05:23:50 PM PDT 24 Jul 15 05:25:02 PM PDT 24 17993661464 ps
T94 /workspace/coverage/default/7.rom_ctrl_stress_all.2106835386 Jul 15 05:20:48 PM PDT 24 Jul 15 05:23:03 PM PDT 24 61609353106 ps
T95 /workspace/coverage/default/17.rom_ctrl_alert_test.271898891 Jul 15 05:21:56 PM PDT 24 Jul 15 05:22:24 PM PDT 24 8479443382 ps
T96 /workspace/coverage/default/30.rom_ctrl_stress_all.3918769681 Jul 15 05:23:15 PM PDT 24 Jul 15 05:24:06 PM PDT 24 2333529714 ps
T97 /workspace/coverage/default/2.rom_ctrl_alert_test.617023530 Jul 15 05:20:02 PM PDT 24 Jul 15 05:20:25 PM PDT 24 2121915093 ps
T98 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1093786279 Jul 15 05:24:15 PM PDT 24 Jul 15 05:24:27 PM PDT 24 369184803 ps
T99 /workspace/coverage/default/34.rom_ctrl_smoke.1978426776 Jul 15 05:23:35 PM PDT 24 Jul 15 05:23:56 PM PDT 24 351484740 ps
T100 /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3992937670 Jul 15 05:23:13 PM PDT 24 Jul 15 05:42:52 PM PDT 24 58395537057 ps
T101 /workspace/coverage/default/3.rom_ctrl_alert_test.2592282172 Jul 15 05:20:10 PM PDT 24 Jul 15 05:20:19 PM PDT 24 169269052 ps
T347 /workspace/coverage/default/23.rom_ctrl_stress_all.1631621009 Jul 15 05:22:34 PM PDT 24 Jul 15 05:25:39 PM PDT 24 16911926392 ps
T348 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3069755101 Jul 15 05:23:07 PM PDT 24 Jul 15 05:23:35 PM PDT 24 4798775827 ps
T349 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2009826508 Jul 15 05:23:50 PM PDT 24 Jul 15 05:24:50 PM PDT 24 6537239788 ps
T350 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2369485266 Jul 15 05:20:16 PM PDT 24 Jul 15 05:21:23 PM PDT 24 8732975212 ps
T351 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2576426373 Jul 15 05:19:47 PM PDT 24 Jul 15 05:20:20 PM PDT 24 15301142910 ps
T352 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2384672453 Jul 15 05:21:32 PM PDT 24 Jul 15 05:22:08 PM PDT 24 4346826130 ps
T353 /workspace/coverage/default/30.rom_ctrl_smoke.1135177106 Jul 15 05:23:14 PM PDT 24 Jul 15 05:23:59 PM PDT 24 3460165306 ps
T354 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3923117778 Jul 15 05:22:41 PM PDT 24 Jul 15 05:32:49 PM PDT 24 64367200441 ps
T355 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2865483038 Jul 15 05:22:22 PM PDT 24 Jul 15 05:22:41 PM PDT 24 1542243601 ps
T356 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.765765763 Jul 15 05:24:50 PM PDT 24 Jul 15 05:25:10 PM PDT 24 1374890275 ps
T357 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.652708439 Jul 15 05:23:58 PM PDT 24 Jul 15 05:24:10 PM PDT 24 3508224354 ps
T358 /workspace/coverage/default/11.rom_ctrl_stress_all.3289880243 Jul 15 05:21:09 PM PDT 24 Jul 15 05:22:03 PM PDT 24 3469125825 ps
T359 /workspace/coverage/default/32.rom_ctrl_alert_test.2952814702 Jul 15 05:23:35 PM PDT 24 Jul 15 05:24:04 PM PDT 24 13316853132 ps
T360 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2308686027 Jul 15 05:24:51 PM PDT 24 Jul 15 05:25:17 PM PDT 24 8708915958 ps
T361 /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.2587238126 Jul 15 05:21:40 PM PDT 24 Jul 15 06:16:18 PM PDT 24 86690166577 ps
T59 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2955405523 Jul 15 05:09:09 PM PDT 24 Jul 15 05:09:19 PM PDT 24 345651574 ps
T60 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3262710387 Jul 15 05:10:04 PM PDT 24 Jul 15 05:10:19 PM PDT 24 792239478 ps
T61 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1300804532 Jul 15 05:08:34 PM PDT 24 Jul 15 05:08:52 PM PDT 24 12037916803 ps
T102 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2145709557 Jul 15 05:10:28 PM PDT 24 Jul 15 05:11:10 PM PDT 24 4139117302 ps
T64 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1418604667 Jul 15 05:10:13 PM PDT 24 Jul 15 05:11:50 PM PDT 24 39632248489 ps
T65 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1286565018 Jul 15 05:08:28 PM PDT 24 Jul 15 05:08:59 PM PDT 24 6164035073 ps
T56 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2817957021 Jul 15 05:09:41 PM PDT 24 Jul 15 05:12:34 PM PDT 24 1916088238 ps
T362 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.431481079 Jul 15 05:08:55 PM PDT 24 Jul 15 05:09:26 PM PDT 24 3158749703 ps
T363 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1616194394 Jul 15 05:09:29 PM PDT 24 Jul 15 05:09:57 PM PDT 24 4983189278 ps
T66 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.393528822 Jul 15 05:08:22 PM PDT 24 Jul 15 05:09:03 PM PDT 24 14850233845 ps
T103 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.611180151 Jul 15 05:10:44 PM PDT 24 Jul 15 05:11:11 PM PDT 24 1562309195 ps
T57 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3772544810 Jul 15 05:10:20 PM PDT 24 Jul 15 05:13:16 PM PDT 24 2702519444 ps
T364 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2226430238 Jul 15 05:09:55 PM PDT 24 Jul 15 05:10:36 PM PDT 24 6727687243 ps
T365 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3328348503 Jul 15 05:10:36 PM PDT 24 Jul 15 05:10:57 PM PDT 24 661516459 ps
T67 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1477219375 Jul 15 05:09:15 PM PDT 24 Jul 15 05:09:25 PM PDT 24 171106492 ps
T106 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2547322283 Jul 15 05:10:06 PM PDT 24 Jul 15 05:10:35 PM PDT 24 2815118353 ps
T58 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2010512189 Jul 15 05:10:43 PM PDT 24 Jul 15 05:13:27 PM PDT 24 629010804 ps
T366 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.232151410 Jul 15 05:09:15 PM PDT 24 Jul 15 05:09:24 PM PDT 24 718506030 ps
T68 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2427389565 Jul 15 05:09:22 PM PDT 24 Jul 15 05:09:57 PM PDT 24 2671045683 ps
T112 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3947736177 Jul 15 05:10:35 PM PDT 24 Jul 15 05:13:27 PM PDT 24 16159660260 ps
T367 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2518343254 Jul 15 05:08:51 PM PDT 24 Jul 15 05:09:12 PM PDT 24 1621159409 ps
T368 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2757240926 Jul 15 05:09:38 PM PDT 24 Jul 15 05:12:42 PM PDT 24 147282345176 ps
T104 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3067608593 Jul 15 05:09:29 PM PDT 24 Jul 15 05:10:16 PM PDT 24 4433269545 ps
T69 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2153235428 Jul 15 05:09:53 PM PDT 24 Jul 15 05:10:13 PM PDT 24 2740890062 ps
T369 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3671143040 Jul 15 05:10:20 PM PDT 24 Jul 15 05:11:05 PM PDT 24 3168158151 ps
T370 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2108495301 Jul 15 05:09:55 PM PDT 24 Jul 15 05:12:07 PM PDT 24 16704987733 ps
T105 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1508980816 Jul 15 05:09:35 PM PDT 24 Jul 15 05:09:55 PM PDT 24 718267407 ps
T70 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1586920776 Jul 15 05:10:20 PM PDT 24 Jul 15 05:10:43 PM PDT 24 660774655 ps
T371 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3436482314 Jul 15 05:09:55 PM PDT 24 Jul 15 05:10:33 PM PDT 24 8565288845 ps
T372 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2187084320 Jul 15 05:09:29 PM PDT 24 Jul 15 05:10:18 PM PDT 24 66040992049 ps
T71 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3414403614 Jul 15 05:08:51 PM PDT 24 Jul 15 05:09:01 PM PDT 24 168975280 ps
T373 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2658196560 Jul 15 05:08:28 PM PDT 24 Jul 15 05:08:59 PM PDT 24 22380959918 ps
T109 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2133675933 Jul 15 05:09:27 PM PDT 24 Jul 15 05:12:26 PM PDT 24 10432613650 ps
T374 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1795603481 Jul 15 05:10:05 PM PDT 24 Jul 15 05:10:38 PM PDT 24 14200608407 ps
T72 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.129622958 Jul 15 05:10:19 PM PDT 24 Jul 15 05:11:25 PM PDT 24 9386830190 ps
T116 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2252537525 Jul 15 05:09:44 PM PDT 24 Jul 15 05:11:22 PM PDT 24 6367808487 ps
T375 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2599102368 Jul 15 05:10:51 PM PDT 24 Jul 15 05:11:19 PM PDT 24 2333826351 ps
T376 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.549222029 Jul 15 05:10:37 PM PDT 24 Jul 15 05:11:06 PM PDT 24 4560682764 ps
T377 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2003944109 Jul 15 05:10:50 PM PDT 24 Jul 15 05:11:22 PM PDT 24 5390384175 ps
T378 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.332857982 Jul 15 05:10:13 PM PDT 24 Jul 15 05:10:23 PM PDT 24 688254644 ps
T379 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3793986412 Jul 15 05:09:30 PM PDT 24 Jul 15 05:12:19 PM PDT 24 391707527 ps
T73 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1864940103 Jul 15 05:10:43 PM PDT 24 Jul 15 05:11:48 PM PDT 24 1496390288 ps
T380 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.4210200512 Jul 15 05:10:19 PM PDT 24 Jul 15 05:10:41 PM PDT 24 172654795 ps
T381 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3693227128 Jul 15 05:10:06 PM PDT 24 Jul 15 05:10:40 PM PDT 24 3883439676 ps
T382 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.4112787270 Jul 15 05:09:38 PM PDT 24 Jul 15 05:09:55 PM PDT 24 688290894 ps
T81 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1415817206 Jul 15 05:09:30 PM PDT 24 Jul 15 05:11:13 PM PDT 24 5498520262 ps
T383 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2350088614 Jul 15 05:09:14 PM PDT 24 Jul 15 05:09:23 PM PDT 24 718827013 ps
T82 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1845957654 Jul 15 05:09:30 PM PDT 24 Jul 15 05:09:52 PM PDT 24 662076477 ps
T384 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1305541979 Jul 15 05:10:29 PM PDT 24 Jul 15 05:11:02 PM PDT 24 2434368295 ps
T385 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3559157678 Jul 15 05:09:09 PM PDT 24 Jul 15 05:09:39 PM PDT 24 14921352618 ps
T386 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.94846562 Jul 15 05:09:55 PM PDT 24 Jul 15 05:10:21 PM PDT 24 8504874359 ps
T110 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3047673496 Jul 15 05:10:19 PM PDT 24 Jul 15 05:12:10 PM PDT 24 6330400218 ps
T387 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1269322861 Jul 15 05:09:21 PM PDT 24 Jul 15 05:10:02 PM PDT 24 14547175041 ps
T388 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3463222138 Jul 15 05:09:06 PM PDT 24 Jul 15 05:09:32 PM PDT 24 10875210666 ps
T389 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3703229061 Jul 15 05:10:04 PM PDT 24 Jul 15 05:13:27 PM PDT 24 92628717439 ps
T390 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.4268640278 Jul 15 05:10:35 PM PDT 24 Jul 15 05:11:22 PM PDT 24 2860967611 ps
T391 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2059519695 Jul 15 05:09:21 PM PDT 24 Jul 15 05:09:59 PM PDT 24 6883091334 ps
T392 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1361475543 Jul 15 05:10:29 PM PDT 24 Jul 15 05:11:00 PM PDT 24 7540218573 ps
T393 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.915468543 Jul 15 05:08:28 PM PDT 24 Jul 15 05:08:59 PM PDT 24 9464912740 ps
T83 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2617750194 Jul 15 05:08:22 PM PDT 24 Jul 15 05:10:26 PM PDT 24 14042845860 ps
T394 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3538925882 Jul 15 05:10:47 PM PDT 24 Jul 15 05:11:24 PM PDT 24 11645927821 ps
T395 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1044846488 Jul 15 05:09:53 PM PDT 24 Jul 15 05:10:23 PM PDT 24 12974669660 ps
T396 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3664208760 Jul 15 05:08:43 PM PDT 24 Jul 15 05:09:19 PM PDT 24 12802242108 ps
T119 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3608880578 Jul 15 05:10:05 PM PDT 24 Jul 15 05:11:53 PM PDT 24 4489852085 ps
T397 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3504729577 Jul 15 05:08:48 PM PDT 24 Jul 15 05:09:22 PM PDT 24 3857930106 ps
T108 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.218932962 Jul 15 05:10:12 PM PDT 24 Jul 15 05:11:58 PM PDT 24 4171962299 ps
T398 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2580964293 Jul 15 05:09:21 PM PDT 24 Jul 15 05:09:54 PM PDT 24 7852527840 ps
T399 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.257594644 Jul 15 05:10:43 PM PDT 24 Jul 15 05:11:00 PM PDT 24 338711563 ps
T400 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3511899409 Jul 15 05:10:11 PM PDT 24 Jul 15 05:10:24 PM PDT 24 1422332407 ps
T84 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3379535446 Jul 15 05:09:27 PM PDT 24 Jul 15 05:10:16 PM PDT 24 8176668370 ps
T401 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.520788012 Jul 15 05:10:12 PM PDT 24 Jul 15 05:10:42 PM PDT 24 17500564828 ps
T402 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2461181939 Jul 15 05:08:54 PM PDT 24 Jul 15 05:10:27 PM PDT 24 9911171237 ps
T403 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2575103547 Jul 15 05:09:13 PM PDT 24 Jul 15 05:09:45 PM PDT 24 5762854481 ps
T404 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.217046888 Jul 15 05:09:29 PM PDT 24 Jul 15 05:10:00 PM PDT 24 2748426081 ps
T405 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.985936436 Jul 15 05:10:28 PM PDT 24 Jul 15 05:11:00 PM PDT 24 5804349069 ps
T85 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2854843211 Jul 15 05:10:37 PM PDT 24 Jul 15 05:11:40 PM PDT 24 4560579602 ps
T406 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2967731879 Jul 15 05:10:04 PM PDT 24 Jul 15 05:10:46 PM PDT 24 1817766194 ps
T407 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2257040348 Jul 15 05:10:43 PM PDT 24 Jul 15 05:11:06 PM PDT 24 1070091849 ps
T120 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3780791583 Jul 15 05:10:04 PM PDT 24 Jul 15 05:11:47 PM PDT 24 3793123748 ps
T408 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1210775559 Jul 15 05:10:37 PM PDT 24 Jul 15 05:10:59 PM PDT 24 172536639 ps
T409 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2481723991 Jul 15 05:10:03 PM PDT 24 Jul 15 05:10:26 PM PDT 24 839939788 ps
T410 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3125993581 Jul 15 05:09:28 PM PDT 24 Jul 15 05:09:58 PM PDT 24 2468129613 ps
T411 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.268740261 Jul 15 05:09:06 PM PDT 24 Jul 15 05:10:28 PM PDT 24 18222108725 ps
T111 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1777952824 Jul 15 05:08:20 PM PDT 24 Jul 15 05:10:03 PM PDT 24 3529417098 ps
T412 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3897913020 Jul 15 05:09:41 PM PDT 24 Jul 15 05:09:58 PM PDT 24 179596125 ps
T413 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2333852592 Jul 15 05:09:04 PM PDT 24 Jul 15 05:09:24 PM PDT 24 3624393138 ps
T414 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1425456877 Jul 15 05:09:36 PM PDT 24 Jul 15 05:10:07 PM PDT 24 5844264689 ps
T415 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.4292541764 Jul 15 05:09:49 PM PDT 24 Jul 15 05:10:02 PM PDT 24 719541282 ps
T416 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3084237931 Jul 15 05:09:07 PM PDT 24 Jul 15 05:09:33 PM PDT 24 2465241326 ps
T417 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1378123814 Jul 15 05:10:11 PM PDT 24 Jul 15 05:10:49 PM PDT 24 15761682324 ps
T418 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.875326482 Jul 15 05:10:38 PM PDT 24 Jul 15 05:10:58 PM PDT 24 659595432 ps
T419 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.4062413069 Jul 15 05:09:05 PM PDT 24 Jul 15 05:09:33 PM PDT 24 14092656609 ps
T420 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3990475208 Jul 15 05:10:11 PM PDT 24 Jul 15 05:10:46 PM PDT 24 20563801899 ps
T421 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1875430386 Jul 15 05:08:49 PM PDT 24 Jul 15 05:09:26 PM PDT 24 29178830004 ps
T86 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.4149267539 Jul 15 05:08:35 PM PDT 24 Jul 15 05:09:32 PM PDT 24 14785126970 ps
T113 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.38982983 Jul 15 05:09:59 PM PDT 24 Jul 15 05:12:43 PM PDT 24 3619791988 ps
T114 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.736055334 Jul 15 05:09:14 PM PDT 24 Jul 15 05:12:11 PM PDT 24 16522909226 ps
T422 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1133465446 Jul 15 05:08:22 PM PDT 24 Jul 15 05:08:37 PM PDT 24 338607994 ps
T423 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3504677738 Jul 15 05:10:38 PM PDT 24 Jul 15 05:12:27 PM PDT 24 7319775183 ps
T424 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.764532159 Jul 15 05:09:44 PM PDT 24 Jul 15 05:12:47 PM PDT 24 21104865431 ps
T425 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3591761175 Jul 15 05:10:36 PM PDT 24 Jul 15 05:11:18 PM PDT 24 15422770663 ps
T87 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4287855176 Jul 15 05:10:35 PM PDT 24 Jul 15 05:10:52 PM PDT 24 345277099 ps
T115 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1209925369 Jul 15 05:10:43 PM PDT 24 Jul 15 05:13:26 PM PDT 24 1635229526 ps
T426 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3616198197 Jul 15 05:10:37 PM PDT 24 Jul 15 05:11:05 PM PDT 24 6604434665 ps
T427 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1151329217 Jul 15 05:08:51 PM PDT 24 Jul 15 05:09:03 PM PDT 24 228606355 ps
T88 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.142452541 Jul 15 05:09:20 PM PDT 24 Jul 15 05:10:18 PM PDT 24 16630683413 ps
T428 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3819896165 Jul 15 05:10:44 PM PDT 24 Jul 15 05:11:19 PM PDT 24 26730760937 ps
T429 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2600747972 Jul 15 05:09:16 PM PDT 24 Jul 15 05:09:29 PM PDT 24 175865737 ps
T430 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1329509961 Jul 15 05:10:52 PM PDT 24 Jul 15 05:11:29 PM PDT 24 17755704756 ps
T89 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.930054133 Jul 15 05:10:28 PM PDT 24 Jul 15 05:13:22 PM PDT 24 118352368518 ps
T431 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3020110681 Jul 15 05:09:44 PM PDT 24 Jul 15 05:10:13 PM PDT 24 2870163742 ps
T118 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3355170383 Jul 15 05:09:00 PM PDT 24 Jul 15 05:11:57 PM PDT 24 8142071926 ps
T432 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2521865555 Jul 15 05:08:21 PM PDT 24 Jul 15 05:08:33 PM PDT 24 385256491 ps
T433 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2121843808 Jul 15 05:09:47 PM PDT 24 Jul 15 05:10:04 PM PDT 24 345756240 ps
T91 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3584342142 Jul 15 05:09:55 PM PDT 24 Jul 15 05:12:10 PM PDT 24 34808537203 ps
T434 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.278152764 Jul 15 05:10:11 PM PDT 24 Jul 15 05:11:48 PM PDT 24 10305511920 ps
T90 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1918635413 Jul 15 05:09:07 PM PDT 24 Jul 15 05:09:33 PM PDT 24 1787294466 ps
T435 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.594124313 Jul 15 05:09:56 PM PDT 24 Jul 15 05:10:16 PM PDT 24 1516528114 ps
T436 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3745201770 Jul 15 05:08:21 PM PDT 24 Jul 15 05:08:33 PM PDT 24 345937854 ps
T437 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2150330772 Jul 15 05:10:36 PM PDT 24 Jul 15 05:11:12 PM PDT 24 12181575115 ps
T438 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.262366603 Jul 15 05:09:13 PM PDT 24 Jul 15 05:09:41 PM PDT 24 3156406357 ps
T117 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3217427944 Jul 15 05:10:38 PM PDT 24 Jul 15 05:12:09 PM PDT 24 1001537160 ps
T439 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2484905749 Jul 15 05:10:45 PM PDT 24 Jul 15 05:11:44 PM PDT 24 1677579806 ps
T440 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.527396331 Jul 15 05:10:11 PM PDT 24 Jul 15 05:10:22 PM PDT 24 193139613 ps
T441 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1530592096 Jul 15 05:09:09 PM PDT 24 Jul 15 05:09:42 PM PDT 24 16085987575 ps
T442 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.930944099 Jul 15 05:08:52 PM PDT 24 Jul 15 05:09:19 PM PDT 24 11840860405 ps
T443 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.905341346 Jul 15 05:10:14 PM PDT 24 Jul 15 05:12:46 PM PDT 24 16302066394 ps
T444 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2288559373 Jul 15 05:10:12 PM PDT 24 Jul 15 05:10:42 PM PDT 24 4888617874 ps
T445 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1781192685 Jul 15 05:09:48 PM PDT 24 Jul 15 05:10:12 PM PDT 24 9508776090 ps
T446 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3697624380 Jul 15 05:08:44 PM PDT 24 Jul 15 05:09:01 PM PDT 24 352244192 ps
T447 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3728630724 Jul 15 05:10:19 PM PDT 24 Jul 15 05:10:46 PM PDT 24 6374293849 ps
T448 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.404825696 Jul 15 05:09:16 PM PDT 24 Jul 15 05:09:42 PM PDT 24 4221095411 ps
T449 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2418514592 Jul 15 05:10:12 PM PDT 24 Jul 15 05:10:45 PM PDT 24 3941821701 ps
T450 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2130488795 Jul 15 05:09:55 PM PDT 24 Jul 15 05:10:22 PM PDT 24 2439638272 ps
T451 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2564573546 Jul 15 05:10:47 PM PDT 24 Jul 15 05:11:24 PM PDT 24 4492331756 ps
T452 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.886309786 Jul 15 05:10:43 PM PDT 24 Jul 15 05:11:25 PM PDT 24 65584814770 ps
T453 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3707156351 Jul 15 05:08:43 PM PDT 24 Jul 15 05:11:21 PM PDT 24 346574773 ps
T454 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3948791863 Jul 15 05:10:04 PM PDT 24 Jul 15 05:10:42 PM PDT 24 15022951501 ps
T455 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1896653919 Jul 15 05:08:44 PM PDT 24 Jul 15 05:09:10 PM PDT 24 2348421805 ps
T456 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2133512956 Jul 15 05:10:20 PM PDT 24 Jul 15 05:11:03 PM PDT 24 6661591427 ps
T457 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.4284302499 Jul 15 05:09:21 PM PDT 24 Jul 15 05:09:50 PM PDT 24 4886079551 ps
T458 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1990892942 Jul 15 05:08:29 PM PDT 24 Jul 15 05:09:02 PM PDT 24 16178177062 ps
T459 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2888082736 Jul 15 05:10:02 PM PDT 24 Jul 15 05:10:28 PM PDT 24 8553749774 ps
T460 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.608947470 Jul 15 05:09:28 PM PDT 24 Jul 15 05:10:11 PM PDT 24 3402932051 ps
T461 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3092527468 Jul 15 05:10:35 PM PDT 24 Jul 15 05:10:53 PM PDT 24 174144641 ps

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1706385466
Short name T9
Test name
Test status
Simulation time 16667117127 ps
CPU time 81.9 seconds
Started Jul 15 05:21:18 PM PDT 24
Finished Jul 15 05:22:41 PM PDT 24
Peak memory 227544 kb
Host smart-f964d2bd-7394-46ad-96aa-35996b76a758
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706385466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1706385466
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.3615214459
Short name T12
Test name
Test status
Simulation time 107574179302 ps
CPU time 2248.97 seconds
Started Jul 15 05:21:18 PM PDT 24
Finished Jul 15 05:58:48 PM PDT 24
Peak memory 244924 kb
Host smart-7b285854-80df-4f81-afad-c65d458bac3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615214459 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.3615214459
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1685042058
Short name T31
Test name
Test status
Simulation time 55184751526 ps
CPU time 589.75 seconds
Started Jul 15 05:23:58 PM PDT 24
Finished Jul 15 05:33:49 PM PDT 24
Peak memory 227660 kb
Host smart-8b939f29-e082-4149-84d7-30a5a26e0e95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685042058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1685042058
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2817957021
Short name T56
Test name
Test status
Simulation time 1916088238 ps
CPU time 165.06 seconds
Started Jul 15 05:09:41 PM PDT 24
Finished Jul 15 05:12:34 PM PDT 24
Peak memory 218808 kb
Host smart-cc74981a-9af5-4bb9-a8d4-fa225b4d2d48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817957021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2817957021
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.340403684
Short name T2
Test name
Test status
Simulation time 4773327134 ps
CPU time 43.51 seconds
Started Jul 15 05:24:15 PM PDT 24
Finished Jul 15 05:24:59 PM PDT 24
Peak memory 216716 kb
Host smart-fb505045-a26f-43e3-b101-28960f79d428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340403684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.340403684
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3014177918
Short name T6
Test name
Test status
Simulation time 2669297265 ps
CPU time 224.97 seconds
Started Jul 15 05:20:09 PM PDT 24
Finished Jul 15 05:23:55 PM PDT 24
Peak memory 238200 kb
Host smart-380e61ab-69f2-4bc3-b6ba-e960d3ade20b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014177918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3014177918
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.129622958
Short name T72
Test name
Test status
Simulation time 9386830190 ps
CPU time 56.44 seconds
Started Jul 15 05:10:19 PM PDT 24
Finished Jul 15 05:11:25 PM PDT 24
Peak memory 215668 kb
Host smart-095404da-555c-4500-8cbe-816ed8bb0433
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129622958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa
ssthru_mem_tl_intg_err.129622958
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3047673496
Short name T110
Test name
Test status
Simulation time 6330400218 ps
CPU time 100.25 seconds
Started Jul 15 05:10:19 PM PDT 24
Finished Jul 15 05:12:10 PM PDT 24
Peak memory 213676 kb
Host smart-c6196fa7-e359-4a1a-b228-9d961c614109
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047673496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3047673496
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.778485730
Short name T5
Test name
Test status
Simulation time 85906602872 ps
CPU time 59.53 seconds
Started Jul 15 05:23:58 PM PDT 24
Finished Jul 15 05:24:58 PM PDT 24
Peak memory 219276 kb
Host smart-fc8b4f42-73b2-4ac4-824a-6a98587e8ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778485730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.778485730
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1085588836
Short name T131
Test name
Test status
Simulation time 3007134119 ps
CPU time 25.89 seconds
Started Jul 15 05:20:02 PM PDT 24
Finished Jul 15 05:20:29 PM PDT 24
Peak memory 217132 kb
Host smart-eaa5562f-7821-43b3-8fb0-f4ba5b4de12e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085588836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1085588836
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2576426373
Short name T351
Test name
Test status
Simulation time 15301142910 ps
CPU time 32.91 seconds
Started Jul 15 05:19:47 PM PDT 24
Finished Jul 15 05:20:20 PM PDT 24
Peak memory 215556 kb
Host smart-38d52df4-2b17-41ec-a2f6-6ab71466ef06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576426373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2576426373
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3954920783
Short name T40
Test name
Test status
Simulation time 3766651109 ps
CPU time 42.98 seconds
Started Jul 15 05:21:34 PM PDT 24
Finished Jul 15 05:22:17 PM PDT 24
Peak memory 219352 kb
Host smart-1b122f9c-feb7-4aa2-a69f-9f04582f0a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954920783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3954920783
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2927879839
Short name T34
Test name
Test status
Simulation time 85808740486 ps
CPU time 274.57 seconds
Started Jul 15 05:20:17 PM PDT 24
Finished Jul 15 05:24:53 PM PDT 24
Peak memory 237756 kb
Host smart-56663f42-4a74-40d7-a831-bc0f0bcacb12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927879839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2927879839
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2834412592
Short name T1
Test name
Test status
Simulation time 18509323178 ps
CPU time 95.52 seconds
Started Jul 15 05:23:14 PM PDT 24
Finished Jul 15 05:24:50 PM PDT 24
Peak memory 219324 kb
Host smart-d329c899-d374-40cd-9809-caa39aedae21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834412592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2834412592
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1777952824
Short name T111
Test name
Test status
Simulation time 3529417098 ps
CPU time 98.62 seconds
Started Jul 15 05:08:20 PM PDT 24
Finished Jul 15 05:10:03 PM PDT 24
Peak memory 213528 kb
Host smart-c4885f84-f61e-4b61-9bd1-228e73b1010e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777952824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1777952824
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.218932962
Short name T108
Test name
Test status
Simulation time 4171962299 ps
CPU time 104.97 seconds
Started Jul 15 05:10:12 PM PDT 24
Finished Jul 15 05:11:58 PM PDT 24
Peak memory 213580 kb
Host smart-a64a3f4f-57bb-4b79-acf4-afb4a3063ff3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218932962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.218932962
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3947736177
Short name T112
Test name
Test status
Simulation time 16159660260 ps
CPU time 163.59 seconds
Started Jul 15 05:10:35 PM PDT 24
Finished Jul 15 05:13:27 PM PDT 24
Peak memory 214148 kb
Host smart-b709ca64-b6e3-4c59-9e8c-0d4c8133837d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947736177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3947736177
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.393528822
Short name T66
Test name
Test status
Simulation time 14850233845 ps
CPU time 37.79 seconds
Started Jul 15 05:08:22 PM PDT 24
Finished Jul 15 05:09:03 PM PDT 24
Peak memory 211888 kb
Host smart-a4271e7d-594c-44f8-b687-30a8a8aab8a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393528822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.393528822
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3108149945
Short name T92
Test name
Test status
Simulation time 10370116340 ps
CPU time 27.75 seconds
Started Jul 15 05:24:37 PM PDT 24
Finished Jul 15 05:25:05 PM PDT 24
Peak memory 212068 kb
Host smart-03f1fb37-0086-4f86-9fa5-2a8067146b0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3108149945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3108149945
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.3209625713
Short name T16
Test name
Test status
Simulation time 118284990972 ps
CPU time 4527.78 seconds
Started Jul 15 05:22:03 PM PDT 24
Finished Jul 15 06:37:31 PM PDT 24
Peak memory 253496 kb
Host smart-55d197eb-f937-4bcb-948b-dae471d04a22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209625713 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.3209625713
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2156550572
Short name T219
Test name
Test status
Simulation time 23309310581 ps
CPU time 421.54 seconds
Started Jul 15 05:23:02 PM PDT 24
Finished Jul 15 05:30:04 PM PDT 24
Peak memory 235820 kb
Host smart-686c6a61-047f-4627-9b4a-ac72b21e6e6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156550572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2156550572
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2328895071
Short name T179
Test name
Test status
Simulation time 1992032135 ps
CPU time 39.89 seconds
Started Jul 15 05:19:41 PM PDT 24
Finished Jul 15 05:20:21 PM PDT 24
Peak memory 216456 kb
Host smart-1ecd9a85-370f-4ae2-8785-353c0338a57b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328895071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2328895071
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2658196560
Short name T373
Test name
Test status
Simulation time 22380959918 ps
CPU time 29.44 seconds
Started Jul 15 05:08:28 PM PDT 24
Finished Jul 15 05:08:59 PM PDT 24
Peak memory 211620 kb
Host smart-29f04b80-0eba-40cc-9392-3cad66c86fec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658196560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2658196560
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.915468543
Short name T393
Test name
Test status
Simulation time 9464912740 ps
CPU time 29.4 seconds
Started Jul 15 05:08:28 PM PDT 24
Finished Jul 15 05:08:59 PM PDT 24
Peak memory 212120 kb
Host smart-40216132-57f8-4f3a-b2b6-1754d68441c3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915468543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.915468543
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1300804532
Short name T61
Test name
Test status
Simulation time 12037916803 ps
CPU time 16.7 seconds
Started Jul 15 05:08:34 PM PDT 24
Finished Jul 15 05:08:52 PM PDT 24
Peak memory 215356 kb
Host smart-3ab60be1-c363-4378-a0ef-6ac5e38d8d1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300804532 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1300804532
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1990892942
Short name T458
Test name
Test status
Simulation time 16178177062 ps
CPU time 31.8 seconds
Started Jul 15 05:08:29 PM PDT 24
Finished Jul 15 05:09:02 PM PDT 24
Peak memory 212428 kb
Host smart-9c2635d9-5626-41c9-b411-53121f7794cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990892942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1990892942
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2521865555
Short name T432
Test name
Test status
Simulation time 385256491 ps
CPU time 8.15 seconds
Started Jul 15 05:08:21 PM PDT 24
Finished Jul 15 05:08:33 PM PDT 24
Peak memory 210416 kb
Host smart-99a4110f-d922-4c17-8b4a-f282474665a4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521865555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2521865555
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3745201770
Short name T436
Test name
Test status
Simulation time 345937854 ps
CPU time 8 seconds
Started Jul 15 05:08:21 PM PDT 24
Finished Jul 15 05:08:33 PM PDT 24
Peak memory 210492 kb
Host smart-347843b1-b23c-4690-91c8-e11f5ba6ed83
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745201770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3745201770
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2617750194
Short name T83
Test name
Test status
Simulation time 14042845860 ps
CPU time 120.54 seconds
Started Jul 15 05:08:22 PM PDT 24
Finished Jul 15 05:10:26 PM PDT 24
Peak memory 213948 kb
Host smart-56e48ff0-00a9-42ad-a8fe-c567d7243e99
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617750194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2617750194
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1286565018
Short name T65
Test name
Test status
Simulation time 6164035073 ps
CPU time 29 seconds
Started Jul 15 05:08:28 PM PDT 24
Finished Jul 15 05:08:59 PM PDT 24
Peak memory 212840 kb
Host smart-4582154c-8665-4b50-9834-4719cb623fbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286565018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1286565018
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1133465446
Short name T422
Test name
Test status
Simulation time 338607994 ps
CPU time 11.8 seconds
Started Jul 15 05:08:22 PM PDT 24
Finished Jul 15 05:08:37 PM PDT 24
Peak memory 216948 kb
Host smart-96cd7933-2c9d-4e91-b88e-24f714da4c96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133465446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1133465446
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1875430386
Short name T421
Test name
Test status
Simulation time 29178830004 ps
CPU time 33.34 seconds
Started Jul 15 05:08:49 PM PDT 24
Finished Jul 15 05:09:26 PM PDT 24
Peak memory 211872 kb
Host smart-d573e763-71d9-41da-8b1c-a9102395fc09
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875430386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1875430386
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2518343254
Short name T367
Test name
Test status
Simulation time 1621159409 ps
CPU time 18.64 seconds
Started Jul 15 05:08:51 PM PDT 24
Finished Jul 15 05:09:12 PM PDT 24
Peak memory 210576 kb
Host smart-2619b100-1b4c-46d8-b496-a2a4833cc3b4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518343254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2518343254
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3697624380
Short name T446
Test name
Test status
Simulation time 352244192 ps
CPU time 11.9 seconds
Started Jul 15 05:08:44 PM PDT 24
Finished Jul 15 05:09:01 PM PDT 24
Peak memory 210572 kb
Host smart-4203eb00-d610-4570-9d13-0f2d243160e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697624380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3697624380
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1151329217
Short name T427
Test name
Test status
Simulation time 228606355 ps
CPU time 10.13 seconds
Started Jul 15 05:08:51 PM PDT 24
Finished Jul 15 05:09:03 PM PDT 24
Peak memory 217196 kb
Host smart-51cbe287-3b4d-47ac-9de0-a50273975a0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151329217 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1151329217
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3414403614
Short name T71
Test name
Test status
Simulation time 168975280 ps
CPU time 8.15 seconds
Started Jul 15 05:08:51 PM PDT 24
Finished Jul 15 05:09:01 PM PDT 24
Peak memory 210672 kb
Host smart-fa6d0514-464d-4d91-aada-9aef5e1fdcf9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414403614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3414403614
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1896653919
Short name T455
Test name
Test status
Simulation time 2348421805 ps
CPU time 21.79 seconds
Started Jul 15 05:08:44 PM PDT 24
Finished Jul 15 05:09:10 PM PDT 24
Peak memory 210500 kb
Host smart-8c20db68-5f2b-4323-8d3c-997f06f99b90
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896653919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1896653919
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3504729577
Short name T397
Test name
Test status
Simulation time 3857930106 ps
CPU time 29.66 seconds
Started Jul 15 05:08:48 PM PDT 24
Finished Jul 15 05:09:22 PM PDT 24
Peak memory 210588 kb
Host smart-47f681ca-1a35-4c05-ab95-ff712993695f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504729577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3504729577
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.4149267539
Short name T86
Test name
Test status
Simulation time 14785126970 ps
CPU time 55.44 seconds
Started Jul 15 05:08:35 PM PDT 24
Finished Jul 15 05:09:32 PM PDT 24
Peak memory 215304 kb
Host smart-0b50ffd9-e047-4a90-8f6d-83ac5ead5dd2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149267539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.4149267539
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.930944099
Short name T442
Test name
Test status
Simulation time 11840860405 ps
CPU time 25.52 seconds
Started Jul 15 05:08:52 PM PDT 24
Finished Jul 15 05:09:19 PM PDT 24
Peak memory 212240 kb
Host smart-53c17b7d-b75b-44a0-9113-7fe1d7210338
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930944099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.930944099
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3664208760
Short name T396
Test name
Test status
Simulation time 12802242108 ps
CPU time 31.61 seconds
Started Jul 15 05:08:43 PM PDT 24
Finished Jul 15 05:09:19 PM PDT 24
Peak memory 218720 kb
Host smart-9cb31060-09a9-4b1e-8654-aff00fb50480
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664208760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3664208760
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3707156351
Short name T453
Test name
Test status
Simulation time 346574773 ps
CPU time 153.48 seconds
Started Jul 15 05:08:43 PM PDT 24
Finished Jul 15 05:11:21 PM PDT 24
Peak memory 213936 kb
Host smart-90d598c1-ca6d-4f53-8f17-2fe5b3469efb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707156351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3707156351
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3693227128
Short name T381
Test name
Test status
Simulation time 3883439676 ps
CPU time 31.16 seconds
Started Jul 15 05:10:06 PM PDT 24
Finished Jul 15 05:10:40 PM PDT 24
Peak memory 217784 kb
Host smart-484a3393-133e-43c8-a9f5-e02d873ca550
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693227128 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3693227128
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2547322283
Short name T106
Test name
Test status
Simulation time 2815118353 ps
CPU time 25.88 seconds
Started Jul 15 05:10:06 PM PDT 24
Finished Jul 15 05:10:35 PM PDT 24
Peak memory 211436 kb
Host smart-d1ea9b55-c97e-44f0-936e-38058cbe110f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547322283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2547322283
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2967731879
Short name T406
Test name
Test status
Simulation time 1817766194 ps
CPU time 37.89 seconds
Started Jul 15 05:10:04 PM PDT 24
Finished Jul 15 05:10:46 PM PDT 24
Peak memory 213784 kb
Host smart-77527d2d-4d4b-4cf8-8cbb-29f7cc83ec42
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967731879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2967731879
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3262710387
Short name T60
Test name
Test status
Simulation time 792239478 ps
CPU time 12.04 seconds
Started Jul 15 05:10:04 PM PDT 24
Finished Jul 15 05:10:19 PM PDT 24
Peak memory 212408 kb
Host smart-362b49df-7db1-41b4-9696-cbf601d6f982
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262710387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3262710387
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2481723991
Short name T409
Test name
Test status
Simulation time 839939788 ps
CPU time 18.65 seconds
Started Jul 15 05:10:03 PM PDT 24
Finished Jul 15 05:10:26 PM PDT 24
Peak memory 218532 kb
Host smart-26754f54-30da-4c4f-ada8-7684cb95c997
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481723991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2481723991
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3608880578
Short name T119
Test name
Test status
Simulation time 4489852085 ps
CPU time 105.08 seconds
Started Jul 15 05:10:05 PM PDT 24
Finished Jul 15 05:11:53 PM PDT 24
Peak memory 213924 kb
Host smart-df5c5dc2-f7df-40a5-9cea-87973c2a7ab0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608880578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3608880578
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3990475208
Short name T420
Test name
Test status
Simulation time 20563801899 ps
CPU time 33.04 seconds
Started Jul 15 05:10:11 PM PDT 24
Finished Jul 15 05:10:46 PM PDT 24
Peak memory 216568 kb
Host smart-ebe9b8b5-424b-401f-8b1a-9613de0b506e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990475208 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3990475208
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2418514592
Short name T449
Test name
Test status
Simulation time 3941821701 ps
CPU time 31.24 seconds
Started Jul 15 05:10:12 PM PDT 24
Finished Jul 15 05:10:45 PM PDT 24
Peak memory 211980 kb
Host smart-e27dcc73-e9ed-4887-b054-f148753269f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418514592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2418514592
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3703229061
Short name T389
Test name
Test status
Simulation time 92628717439 ps
CPU time 199.3 seconds
Started Jul 15 05:10:04 PM PDT 24
Finished Jul 15 05:13:27 PM PDT 24
Peak memory 214892 kb
Host smart-503794e7-d856-499a-9f31-c024a0c6fac7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703229061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3703229061
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2288559373
Short name T444
Test name
Test status
Simulation time 4888617874 ps
CPU time 28.12 seconds
Started Jul 15 05:10:12 PM PDT 24
Finished Jul 15 05:10:42 PM PDT 24
Peak memory 212564 kb
Host smart-4e16f6ba-908a-4613-8ee2-7465007c1465
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288559373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2288559373
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1378123814
Short name T417
Test name
Test status
Simulation time 15761682324 ps
CPU time 37.12 seconds
Started Jul 15 05:10:11 PM PDT 24
Finished Jul 15 05:10:49 PM PDT 24
Peak memory 218644 kb
Host smart-ece3645f-81d8-4997-bb60-6c07831e5b46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378123814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1378123814
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.278152764
Short name T434
Test name
Test status
Simulation time 10305511920 ps
CPU time 95.44 seconds
Started Jul 15 05:10:11 PM PDT 24
Finished Jul 15 05:11:48 PM PDT 24
Peak memory 214028 kb
Host smart-17be5493-0a8b-4f37-bfd4-413d6e720fc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278152764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.278152764
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.527396331
Short name T440
Test name
Test status
Simulation time 193139613 ps
CPU time 9.25 seconds
Started Jul 15 05:10:11 PM PDT 24
Finished Jul 15 05:10:22 PM PDT 24
Peak memory 216264 kb
Host smart-d7e4253d-4ca2-4d73-863d-bfdcb1f527b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527396331 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.527396331
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.332857982
Short name T378
Test name
Test status
Simulation time 688254644 ps
CPU time 8.46 seconds
Started Jul 15 05:10:13 PM PDT 24
Finished Jul 15 05:10:23 PM PDT 24
Peak memory 211004 kb
Host smart-41fdaaf7-df44-407a-85f9-0d48dcb60df0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332857982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.332857982
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1418604667
Short name T64
Test name
Test status
Simulation time 39632248489 ps
CPU time 95.78 seconds
Started Jul 15 05:10:13 PM PDT 24
Finished Jul 15 05:11:50 PM PDT 24
Peak memory 213912 kb
Host smart-4a11ec24-268c-4aa2-b37a-4bca6ff28cda
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418604667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1418604667
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3511899409
Short name T400
Test name
Test status
Simulation time 1422332407 ps
CPU time 11.15 seconds
Started Jul 15 05:10:11 PM PDT 24
Finished Jul 15 05:10:24 PM PDT 24
Peak memory 211280 kb
Host smart-fb9c6434-4601-45dc-b515-bfdffdb639f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511899409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3511899409
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.520788012
Short name T401
Test name
Test status
Simulation time 17500564828 ps
CPU time 28.8 seconds
Started Jul 15 05:10:12 PM PDT 24
Finished Jul 15 05:10:42 PM PDT 24
Peak memory 217688 kb
Host smart-59aaf574-c79b-41e9-8924-249f714da027
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520788012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.520788012
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2133512956
Short name T456
Test name
Test status
Simulation time 6661591427 ps
CPU time 31.89 seconds
Started Jul 15 05:10:20 PM PDT 24
Finished Jul 15 05:11:03 PM PDT 24
Peak memory 217104 kb
Host smart-a6dd2f84-d752-44dc-be58-6c3d702e262f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133512956 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2133512956
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1586920776
Short name T70
Test name
Test status
Simulation time 660774655 ps
CPU time 12.46 seconds
Started Jul 15 05:10:20 PM PDT 24
Finished Jul 15 05:10:43 PM PDT 24
Peak memory 210692 kb
Host smart-df8db157-e1ba-4535-93c3-d6daef17eeba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586920776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1586920776
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.905341346
Short name T443
Test name
Test status
Simulation time 16302066394 ps
CPU time 151.32 seconds
Started Jul 15 05:10:14 PM PDT 24
Finished Jul 15 05:12:46 PM PDT 24
Peak memory 215312 kb
Host smart-fae7b20d-7871-432b-af46-e82a850b1853
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905341346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.905341346
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3728630724
Short name T447
Test name
Test status
Simulation time 6374293849 ps
CPU time 15.82 seconds
Started Jul 15 05:10:19 PM PDT 24
Finished Jul 15 05:10:46 PM PDT 24
Peak memory 211448 kb
Host smart-d1b8bfa2-9025-4ee3-a0fb-68851ed68de8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728630724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3728630724
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3671143040
Short name T369
Test name
Test status
Simulation time 3168158151 ps
CPU time 33.24 seconds
Started Jul 15 05:10:20 PM PDT 24
Finished Jul 15 05:11:05 PM PDT 24
Peak memory 218448 kb
Host smart-2b4cf548-df5f-4b64-bcdf-0d19a619ab65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671143040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3671143040
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3772544810
Short name T57
Test name
Test status
Simulation time 2702519444 ps
CPU time 164.54 seconds
Started Jul 15 05:10:20 PM PDT 24
Finished Jul 15 05:13:16 PM PDT 24
Peak memory 213964 kb
Host smart-d2045324-7280-4a75-8536-e6838ca6563f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772544810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3772544810
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1305541979
Short name T384
Test name
Test status
Simulation time 2434368295 ps
CPU time 22.78 seconds
Started Jul 15 05:10:29 PM PDT 24
Finished Jul 15 05:11:02 PM PDT 24
Peak memory 217884 kb
Host smart-540bd2a9-0ac1-4ad7-a531-4ad4a252f7b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305541979 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1305541979
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1361475543
Short name T392
Test name
Test status
Simulation time 7540218573 ps
CPU time 20.45 seconds
Started Jul 15 05:10:29 PM PDT 24
Finished Jul 15 05:11:00 PM PDT 24
Peak memory 212408 kb
Host smart-77495050-b328-4889-879c-15dd585e6c14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361475543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1361475543
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2145709557
Short name T102
Test name
Test status
Simulation time 4139117302 ps
CPU time 32.4 seconds
Started Jul 15 05:10:28 PM PDT 24
Finished Jul 15 05:11:10 PM PDT 24
Peak memory 212292 kb
Host smart-eecdcae2-0bae-4cb2-8f24-bf6b188e5e34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145709557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2145709557
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.4210200512
Short name T380
Test name
Test status
Simulation time 172654795 ps
CPU time 11.96 seconds
Started Jul 15 05:10:19 PM PDT 24
Finished Jul 15 05:10:41 PM PDT 24
Peak memory 217240 kb
Host smart-00b314f7-f616-415f-896d-81d7bdc0fe27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210200512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.4210200512
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3092527468
Short name T461
Test name
Test status
Simulation time 174144641 ps
CPU time 8.58 seconds
Started Jul 15 05:10:35 PM PDT 24
Finished Jul 15 05:10:53 PM PDT 24
Peak memory 213452 kb
Host smart-474b2359-7b47-4c87-a496-de8320727c47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092527468 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3092527468
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3616198197
Short name T426
Test name
Test status
Simulation time 6604434665 ps
CPU time 19.05 seconds
Started Jul 15 05:10:37 PM PDT 24
Finished Jul 15 05:11:05 PM PDT 24
Peak memory 212144 kb
Host smart-acb8a0e2-936a-4483-906a-07b6cf9636f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616198197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3616198197
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.930054133
Short name T89
Test name
Test status
Simulation time 118352368518 ps
CPU time 163.83 seconds
Started Jul 15 05:10:28 PM PDT 24
Finished Jul 15 05:13:22 PM PDT 24
Peak memory 214692 kb
Host smart-541d289f-3e32-4ef9-aaa1-ea46a3452f68
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930054133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.930054133
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.549222029
Short name T376
Test name
Test status
Simulation time 4560682764 ps
CPU time 20.16 seconds
Started Jul 15 05:10:37 PM PDT 24
Finished Jul 15 05:11:06 PM PDT 24
Peak memory 212512 kb
Host smart-39fe2c05-3a8b-4e8f-b81c-2441a53f30bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549222029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.549222029
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.985936436
Short name T405
Test name
Test status
Simulation time 5804349069 ps
CPU time 21.83 seconds
Started Jul 15 05:10:28 PM PDT 24
Finished Jul 15 05:11:00 PM PDT 24
Peak memory 218684 kb
Host smart-91581aa1-113b-4029-8f5c-7f272d3c95a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985936436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.985936436
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2150330772
Short name T437
Test name
Test status
Simulation time 12181575115 ps
CPU time 26.31 seconds
Started Jul 15 05:10:36 PM PDT 24
Finished Jul 15 05:11:12 PM PDT 24
Peak memory 217256 kb
Host smart-72bf4d20-0d35-410a-a4d4-79f6947ec4ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150330772 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2150330772
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4287855176
Short name T87
Test name
Test status
Simulation time 345277099 ps
CPU time 8.23 seconds
Started Jul 15 05:10:35 PM PDT 24
Finished Jul 15 05:10:52 PM PDT 24
Peak memory 210756 kb
Host smart-91a07bc8-711c-4035-82f6-52a0a5b23ee5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287855176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.4287855176
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.4268640278
Short name T390
Test name
Test status
Simulation time 2860967611 ps
CPU time 37.46 seconds
Started Jul 15 05:10:35 PM PDT 24
Finished Jul 15 05:11:22 PM PDT 24
Peak memory 213676 kb
Host smart-b237a2fd-16ac-4173-938d-02de282fdc61
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268640278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.4268640278
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.875326482
Short name T418
Test name
Test status
Simulation time 659595432 ps
CPU time 10.52 seconds
Started Jul 15 05:10:38 PM PDT 24
Finished Jul 15 05:10:58 PM PDT 24
Peak memory 211048 kb
Host smart-df080801-9fcd-4259-9703-31769a453018
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875326482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.875326482
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3328348503
Short name T365
Test name
Test status
Simulation time 661516459 ps
CPU time 11.23 seconds
Started Jul 15 05:10:36 PM PDT 24
Finished Jul 15 05:10:57 PM PDT 24
Peak memory 217012 kb
Host smart-dd33af58-e391-41be-88f6-80bf04c03796
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328348503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3328348503
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3504677738
Short name T423
Test name
Test status
Simulation time 7319775183 ps
CPU time 99.42 seconds
Started Jul 15 05:10:38 PM PDT 24
Finished Jul 15 05:12:27 PM PDT 24
Peak memory 213460 kb
Host smart-b769b061-cee0-4b68-95aa-6a008642cd9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504677738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3504677738
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3819896165
Short name T428
Test name
Test status
Simulation time 26730760937 ps
CPU time 26.8 seconds
Started Jul 15 05:10:44 PM PDT 24
Finished Jul 15 05:11:19 PM PDT 24
Peak memory 216840 kb
Host smart-66e8e222-e9ac-4b0f-a946-1b164b06d06f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819896165 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3819896165
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3591761175
Short name T425
Test name
Test status
Simulation time 15422770663 ps
CPU time 32.94 seconds
Started Jul 15 05:10:36 PM PDT 24
Finished Jul 15 05:11:18 PM PDT 24
Peak memory 211744 kb
Host smart-9e1c4a1c-76b0-4bec-9c9b-4f7fd42d951d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591761175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3591761175
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2854843211
Short name T85
Test name
Test status
Simulation time 4560579602 ps
CPU time 53.07 seconds
Started Jul 15 05:10:37 PM PDT 24
Finished Jul 15 05:11:40 PM PDT 24
Peak memory 214040 kb
Host smart-aef1438e-7650-4d2d-849e-18d79bb66887
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854843211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2854843211
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2257040348
Short name T407
Test name
Test status
Simulation time 1070091849 ps
CPU time 14.91 seconds
Started Jul 15 05:10:43 PM PDT 24
Finished Jul 15 05:11:06 PM PDT 24
Peak memory 210812 kb
Host smart-08001cad-1381-4011-8ddc-62d57fc5e09c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257040348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2257040348
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1210775559
Short name T408
Test name
Test status
Simulation time 172536639 ps
CPU time 12.28 seconds
Started Jul 15 05:10:37 PM PDT 24
Finished Jul 15 05:10:59 PM PDT 24
Peak memory 217252 kb
Host smart-a074a9de-a7e2-4bed-abd2-5d8140580d03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210775559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1210775559
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3217427944
Short name T117
Test name
Test status
Simulation time 1001537160 ps
CPU time 81.74 seconds
Started Jul 15 05:10:38 PM PDT 24
Finished Jul 15 05:12:09 PM PDT 24
Peak memory 213344 kb
Host smart-b055ecd2-f65d-43c4-8265-e98740bd602d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217427944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3217427944
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2564573546
Short name T451
Test name
Test status
Simulation time 4492331756 ps
CPU time 28.9 seconds
Started Jul 15 05:10:47 PM PDT 24
Finished Jul 15 05:11:24 PM PDT 24
Peak memory 217856 kb
Host smart-1f39e563-d4fd-44c0-92bc-9c36222de779
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564573546 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2564573546
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.257594644
Short name T399
Test name
Test status
Simulation time 338711563 ps
CPU time 8.26 seconds
Started Jul 15 05:10:43 PM PDT 24
Finished Jul 15 05:11:00 PM PDT 24
Peak memory 210576 kb
Host smart-bb3ae363-bc42-453a-ba0a-9562a850af4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257594644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.257594644
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1864940103
Short name T73
Test name
Test status
Simulation time 1496390288 ps
CPU time 55.86 seconds
Started Jul 15 05:10:43 PM PDT 24
Finished Jul 15 05:11:48 PM PDT 24
Peak memory 214860 kb
Host smart-cfc19a53-e779-4faf-a5d7-26ce8ea0c823
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864940103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1864940103
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.611180151
Short name T103
Test name
Test status
Simulation time 1562309195 ps
CPU time 18.22 seconds
Started Jul 15 05:10:44 PM PDT 24
Finished Jul 15 05:11:11 PM PDT 24
Peak memory 211096 kb
Host smart-58a2ded6-93ff-4f42-8c63-6a957ffbf102
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611180151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.611180151
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.886309786
Short name T452
Test name
Test status
Simulation time 65584814770 ps
CPU time 33.29 seconds
Started Jul 15 05:10:43 PM PDT 24
Finished Jul 15 05:11:25 PM PDT 24
Peak memory 218736 kb
Host smart-65df7311-93d8-4580-97b1-d4849752def8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886309786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.886309786
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1209925369
Short name T115
Test name
Test status
Simulation time 1635229526 ps
CPU time 153.75 seconds
Started Jul 15 05:10:43 PM PDT 24
Finished Jul 15 05:13:26 PM PDT 24
Peak memory 214004 kb
Host smart-2492aed7-93c8-49a1-af8a-ef6f10703511
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209925369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1209925369
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2003944109
Short name T377
Test name
Test status
Simulation time 5390384175 ps
CPU time 25.2 seconds
Started Jul 15 05:10:50 PM PDT 24
Finished Jul 15 05:11:22 PM PDT 24
Peak memory 215780 kb
Host smart-c015e087-6cd6-4827-b421-1272d59a5151
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003944109 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2003944109
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2599102368
Short name T375
Test name
Test status
Simulation time 2333826351 ps
CPU time 22.6 seconds
Started Jul 15 05:10:51 PM PDT 24
Finished Jul 15 05:11:19 PM PDT 24
Peak memory 211708 kb
Host smart-da90c73c-cd4d-4e91-b928-4d853ea339db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599102368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2599102368
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2484905749
Short name T439
Test name
Test status
Simulation time 1677579806 ps
CPU time 50.32 seconds
Started Jul 15 05:10:45 PM PDT 24
Finished Jul 15 05:11:44 PM PDT 24
Peak memory 213596 kb
Host smart-7e10ee52-9640-4cc4-b08d-ee6d4ab88e3e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484905749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2484905749
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1329509961
Short name T430
Test name
Test status
Simulation time 17755704756 ps
CPU time 31.97 seconds
Started Jul 15 05:10:52 PM PDT 24
Finished Jul 15 05:11:29 PM PDT 24
Peak memory 212684 kb
Host smart-4df9fac2-14d2-4bc2-ac99-ec05372f298c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329509961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1329509961
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3538925882
Short name T394
Test name
Test status
Simulation time 11645927821 ps
CPU time 28.98 seconds
Started Jul 15 05:10:47 PM PDT 24
Finished Jul 15 05:11:24 PM PDT 24
Peak memory 216444 kb
Host smart-3be9eff2-4df0-4bed-aa05-039fb1d5965d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538925882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3538925882
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2010512189
Short name T58
Test name
Test status
Simulation time 629010804 ps
CPU time 155.2 seconds
Started Jul 15 05:10:43 PM PDT 24
Finished Jul 15 05:13:27 PM PDT 24
Peak memory 214048 kb
Host smart-4c06240f-4ddf-43e0-8fa3-0b5342f1ad5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010512189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2010512189
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3463222138
Short name T388
Test name
Test status
Simulation time 10875210666 ps
CPU time 25.1 seconds
Started Jul 15 05:09:06 PM PDT 24
Finished Jul 15 05:09:32 PM PDT 24
Peak memory 211820 kb
Host smart-32a3e8cd-bc04-482c-9215-3dfcac4e978d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463222138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3463222138
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2955405523
Short name T59
Test name
Test status
Simulation time 345651574 ps
CPU time 8.55 seconds
Started Jul 15 05:09:09 PM PDT 24
Finished Jul 15 05:09:19 PM PDT 24
Peak memory 210636 kb
Host smart-0dc3538b-e82a-4584-ab46-84d8d73fd52b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955405523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2955405523
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1918635413
Short name T90
Test name
Test status
Simulation time 1787294466 ps
CPU time 25.62 seconds
Started Jul 15 05:09:07 PM PDT 24
Finished Jul 15 05:09:33 PM PDT 24
Peak memory 211844 kb
Host smart-20d3f1c6-beff-4658-96dd-d8ab81f47989
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918635413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1918635413
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3084237931
Short name T416
Test name
Test status
Simulation time 2465241326 ps
CPU time 24.56 seconds
Started Jul 15 05:09:07 PM PDT 24
Finished Jul 15 05:09:33 PM PDT 24
Peak memory 216932 kb
Host smart-ae1c9d78-b910-4fbc-bfd8-e1353bab7e36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084237931 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3084237931
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3559157678
Short name T385
Test name
Test status
Simulation time 14921352618 ps
CPU time 29.3 seconds
Started Jul 15 05:09:09 PM PDT 24
Finished Jul 15 05:09:39 PM PDT 24
Peak memory 212032 kb
Host smart-597f670a-032a-4d68-866a-76453969e493
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559157678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3559157678
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.4062413069
Short name T419
Test name
Test status
Simulation time 14092656609 ps
CPU time 26.83 seconds
Started Jul 15 05:09:05 PM PDT 24
Finished Jul 15 05:09:33 PM PDT 24
Peak memory 210524 kb
Host smart-9515f821-b976-46c7-bacc-17c6b37e587c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062413069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.4062413069
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2333852592
Short name T413
Test name
Test status
Simulation time 3624393138 ps
CPU time 19.14 seconds
Started Jul 15 05:09:04 PM PDT 24
Finished Jul 15 05:09:24 PM PDT 24
Peak memory 210536 kb
Host smart-0467d34e-9259-450d-a0f0-6483bf3c896a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333852592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2333852592
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2461181939
Short name T402
Test name
Test status
Simulation time 9911171237 ps
CPU time 92.11 seconds
Started Jul 15 05:08:54 PM PDT 24
Finished Jul 15 05:10:27 PM PDT 24
Peak memory 218896 kb
Host smart-a805d923-2331-4edf-9952-388736121c5c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461181939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2461181939
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1530592096
Short name T441
Test name
Test status
Simulation time 16085987575 ps
CPU time 31.61 seconds
Started Jul 15 05:09:09 PM PDT 24
Finished Jul 15 05:09:42 PM PDT 24
Peak memory 212584 kb
Host smart-87c419c1-c8bc-40c3-a969-6dfcd929d6ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530592096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1530592096
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.431481079
Short name T362
Test name
Test status
Simulation time 3158749703 ps
CPU time 28.99 seconds
Started Jul 15 05:08:55 PM PDT 24
Finished Jul 15 05:09:26 PM PDT 24
Peak memory 218224 kb
Host smart-95be2d34-3bfd-4ed8-841a-80bfe05caf04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431481079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.431481079
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3355170383
Short name T118
Test name
Test status
Simulation time 8142071926 ps
CPU time 175.91 seconds
Started Jul 15 05:09:00 PM PDT 24
Finished Jul 15 05:11:57 PM PDT 24
Peak memory 214196 kb
Host smart-e98d2b90-e923-4b6c-88a3-d9155def5ede
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355170383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3355170383
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2350088614
Short name T383
Test name
Test status
Simulation time 718827013 ps
CPU time 8.41 seconds
Started Jul 15 05:09:14 PM PDT 24
Finished Jul 15 05:09:23 PM PDT 24
Peak memory 210548 kb
Host smart-5dcfc311-098e-4cf8-90bd-145c4bfa1458
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350088614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2350088614
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.262366603
Short name T438
Test name
Test status
Simulation time 3156406357 ps
CPU time 26.92 seconds
Started Jul 15 05:09:13 PM PDT 24
Finished Jul 15 05:09:41 PM PDT 24
Peak memory 211372 kb
Host smart-05c87cd0-4b9b-4b33-9510-c22950939c3e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262366603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.262366603
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2600747972
Short name T429
Test name
Test status
Simulation time 175865737 ps
CPU time 11.88 seconds
Started Jul 15 05:09:16 PM PDT 24
Finished Jul 15 05:09:29 PM PDT 24
Peak memory 211752 kb
Host smart-29e6e34d-7ab1-48c9-83b3-74427d6d0cf5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600747972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2600747972
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2059519695
Short name T391
Test name
Test status
Simulation time 6883091334 ps
CPU time 29.26 seconds
Started Jul 15 05:09:21 PM PDT 24
Finished Jul 15 05:09:59 PM PDT 24
Peak memory 215036 kb
Host smart-1bd0470e-62f7-4961-b4fd-0ac1147d9f69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059519695 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2059519695
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1477219375
Short name T67
Test name
Test status
Simulation time 171106492 ps
CPU time 8.32 seconds
Started Jul 15 05:09:15 PM PDT 24
Finished Jul 15 05:09:25 PM PDT 24
Peak memory 210620 kb
Host smart-d9d8a6c1-75ac-41f4-b135-1c1ed83ef063
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477219375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1477219375
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.232151410
Short name T366
Test name
Test status
Simulation time 718506030 ps
CPU time 8.11 seconds
Started Jul 15 05:09:15 PM PDT 24
Finished Jul 15 05:09:24 PM PDT 24
Peak memory 210532 kb
Host smart-245b67c3-c7c7-4035-bd43-69261198c6af
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232151410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.232151410
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.404825696
Short name T448
Test name
Test status
Simulation time 4221095411 ps
CPU time 25.18 seconds
Started Jul 15 05:09:16 PM PDT 24
Finished Jul 15 05:09:42 PM PDT 24
Peak memory 210556 kb
Host smart-5c8eaba0-903b-451c-9f44-f098d5e0fd37
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404825696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
404825696
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.268740261
Short name T411
Test name
Test status
Simulation time 18222108725 ps
CPU time 81.7 seconds
Started Jul 15 05:09:06 PM PDT 24
Finished Jul 15 05:10:28 PM PDT 24
Peak memory 213852 kb
Host smart-b9e11b4d-2dac-44c5-8af9-b6bef0e5a90b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268740261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.268740261
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2427389565
Short name T68
Test name
Test status
Simulation time 2671045683 ps
CPU time 25.51 seconds
Started Jul 15 05:09:22 PM PDT 24
Finished Jul 15 05:09:57 PM PDT 24
Peak memory 212320 kb
Host smart-6ec0ffa8-7964-4bc0-a378-79b9465024b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427389565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2427389565
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2575103547
Short name T403
Test name
Test status
Simulation time 5762854481 ps
CPU time 30.44 seconds
Started Jul 15 05:09:13 PM PDT 24
Finished Jul 15 05:09:45 PM PDT 24
Peak memory 217472 kb
Host smart-24479303-1fb2-4f6c-a0c6-310ddd43f43a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575103547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2575103547
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.736055334
Short name T114
Test name
Test status
Simulation time 16522909226 ps
CPU time 175.79 seconds
Started Jul 15 05:09:14 PM PDT 24
Finished Jul 15 05:12:11 PM PDT 24
Peak memory 214184 kb
Host smart-6ab15813-abe2-4f9d-bbbe-097cca00b5cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736055334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.736055334
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1845957654
Short name T82
Test name
Test status
Simulation time 662076477 ps
CPU time 8.16 seconds
Started Jul 15 05:09:30 PM PDT 24
Finished Jul 15 05:09:52 PM PDT 24
Peak memory 210660 kb
Host smart-43602582-7ec3-4d8f-bb56-012dee1e358e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845957654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1845957654
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3125993581
Short name T410
Test name
Test status
Simulation time 2468129613 ps
CPU time 16.47 seconds
Started Jul 15 05:09:28 PM PDT 24
Finished Jul 15 05:09:58 PM PDT 24
Peak memory 210640 kb
Host smart-1aabe742-85fc-403f-b135-8e2f88a23171
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125993581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3125993581
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3379535446
Short name T84
Test name
Test status
Simulation time 8176668370 ps
CPU time 34.19 seconds
Started Jul 15 05:09:27 PM PDT 24
Finished Jul 15 05:10:16 PM PDT 24
Peak memory 211712 kb
Host smart-07a07a66-72c9-4c03-8f49-bbebc6b34e30
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379535446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3379535446
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1616194394
Short name T363
Test name
Test status
Simulation time 4983189278 ps
CPU time 13.14 seconds
Started Jul 15 05:09:29 PM PDT 24
Finished Jul 15 05:09:57 PM PDT 24
Peak memory 217180 kb
Host smart-0938acc2-3ee9-40f4-8d8a-385ec03a7279
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616194394 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1616194394
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.4284302499
Short name T457
Test name
Test status
Simulation time 4886079551 ps
CPU time 22.62 seconds
Started Jul 15 05:09:21 PM PDT 24
Finished Jul 15 05:09:50 PM PDT 24
Peak memory 211668 kb
Host smart-71b98141-6a82-4a97-a872-8321452caefe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284302499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.4284302499
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.608947470
Short name T460
Test name
Test status
Simulation time 3402932051 ps
CPU time 28.98 seconds
Started Jul 15 05:09:28 PM PDT 24
Finished Jul 15 05:10:11 PM PDT 24
Peak memory 210508 kb
Host smart-75d75730-6411-4dbc-9c96-a94c13d482a5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608947470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.608947470
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1269322861
Short name T387
Test name
Test status
Simulation time 14547175041 ps
CPU time 31.34 seconds
Started Jul 15 05:09:21 PM PDT 24
Finished Jul 15 05:10:02 PM PDT 24
Peak memory 210516 kb
Host smart-8428cd26-cc4b-4cb0-bed5-0313421a4807
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269322861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1269322861
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.142452541
Short name T88
Test name
Test status
Simulation time 16630683413 ps
CPU time 53.47 seconds
Started Jul 15 05:09:20 PM PDT 24
Finished Jul 15 05:10:18 PM PDT 24
Peak memory 213684 kb
Host smart-f35d095b-aca3-474d-8ea8-eb919702ba78
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142452541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.142452541
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3067608593
Short name T104
Test name
Test status
Simulation time 4433269545 ps
CPU time 32.68 seconds
Started Jul 15 05:09:29 PM PDT 24
Finished Jul 15 05:10:16 PM PDT 24
Peak memory 212584 kb
Host smart-68797fc8-750b-454e-8c3b-c8d771026983
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067608593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3067608593
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2580964293
Short name T398
Test name
Test status
Simulation time 7852527840 ps
CPU time 24.27 seconds
Started Jul 15 05:09:21 PM PDT 24
Finished Jul 15 05:09:54 PM PDT 24
Peak memory 217816 kb
Host smart-2c0ab472-4d46-47b7-a0cb-35284dcbc924
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580964293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2580964293
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2133675933
Short name T109
Test name
Test status
Simulation time 10432613650 ps
CPU time 163.8 seconds
Started Jul 15 05:09:27 PM PDT 24
Finished Jul 15 05:12:26 PM PDT 24
Peak memory 214072 kb
Host smart-19f86aa5-8b20-4e97-9499-2164713ca13b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133675933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2133675933
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3897913020
Short name T412
Test name
Test status
Simulation time 179596125 ps
CPU time 8.8 seconds
Started Jul 15 05:09:41 PM PDT 24
Finished Jul 15 05:09:58 PM PDT 24
Peak memory 215932 kb
Host smart-5e0ec5ef-2a12-4ef9-8b4c-2776d521e6c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897913020 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3897913020
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2187084320
Short name T372
Test name
Test status
Simulation time 66040992049 ps
CPU time 34.47 seconds
Started Jul 15 05:09:29 PM PDT 24
Finished Jul 15 05:10:18 PM PDT 24
Peak memory 211860 kb
Host smart-d2c67218-2980-4d09-b600-0f9dc58ca3fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187084320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2187084320
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1415817206
Short name T81
Test name
Test status
Simulation time 5498520262 ps
CPU time 88.75 seconds
Started Jul 15 05:09:30 PM PDT 24
Finished Jul 15 05:11:13 PM PDT 24
Peak memory 215032 kb
Host smart-ebcbea04-4236-4247-bb93-18bede833204
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415817206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1415817206
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1508980816
Short name T105
Test name
Test status
Simulation time 718267407 ps
CPU time 8.57 seconds
Started Jul 15 05:09:35 PM PDT 24
Finished Jul 15 05:09:55 PM PDT 24
Peak memory 211348 kb
Host smart-db396858-3910-46b1-be95-b56c0a0219b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508980816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1508980816
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.217046888
Short name T404
Test name
Test status
Simulation time 2748426081 ps
CPU time 17.6 seconds
Started Jul 15 05:09:29 PM PDT 24
Finished Jul 15 05:10:00 PM PDT 24
Peak memory 217336 kb
Host smart-8f4b2704-fd13-40fa-9e4b-143f0472f33d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217046888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.217046888
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3793986412
Short name T379
Test name
Test status
Simulation time 391707527 ps
CPU time 155.46 seconds
Started Jul 15 05:09:30 PM PDT 24
Finished Jul 15 05:12:19 PM PDT 24
Peak memory 213952 kb
Host smart-048586a2-1746-469c-a621-bf2d2c4b3ac4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793986412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3793986412
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.4292541764
Short name T415
Test name
Test status
Simulation time 719541282 ps
CPU time 9.57 seconds
Started Jul 15 05:09:49 PM PDT 24
Finished Jul 15 05:10:02 PM PDT 24
Peak memory 216676 kb
Host smart-5f4aa855-dfbf-44be-a85e-41ce4990cfbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292541764 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.4292541764
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.4112787270
Short name T382
Test name
Test status
Simulation time 688290894 ps
CPU time 8.23 seconds
Started Jul 15 05:09:38 PM PDT 24
Finished Jul 15 05:09:55 PM PDT 24
Peak memory 210784 kb
Host smart-6eb1f194-3dd4-428c-8092-be34f60842c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112787270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.4112787270
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2757240926
Short name T368
Test name
Test status
Simulation time 147282345176 ps
CPU time 174.67 seconds
Started Jul 15 05:09:38 PM PDT 24
Finished Jul 15 05:12:42 PM PDT 24
Peak memory 214820 kb
Host smart-b2a8329d-cd52-41f7-a37e-419c3c1e69e9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757240926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2757240926
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1781192685
Short name T445
Test name
Test status
Simulation time 9508776090 ps
CPU time 19.72 seconds
Started Jul 15 05:09:48 PM PDT 24
Finished Jul 15 05:10:12 PM PDT 24
Peak memory 212392 kb
Host smart-90d56ba9-7a0a-4f81-8dbb-3506ac9aa488
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781192685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1781192685
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1425456877
Short name T414
Test name
Test status
Simulation time 5844264689 ps
CPU time 20.78 seconds
Started Jul 15 05:09:36 PM PDT 24
Finished Jul 15 05:10:07 PM PDT 24
Peak memory 217704 kb
Host smart-3250a657-c5f2-496a-9360-153b73a71545
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425456877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1425456877
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.94846562
Short name T386
Test name
Test status
Simulation time 8504874359 ps
CPU time 22.74 seconds
Started Jul 15 05:09:55 PM PDT 24
Finished Jul 15 05:10:21 PM PDT 24
Peak memory 217604 kb
Host smart-c3f8268d-5f76-41be-b8a4-a7d0c2649982
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94846562 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.94846562
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3020110681
Short name T431
Test name
Test status
Simulation time 2870163742 ps
CPU time 22.3 seconds
Started Jul 15 05:09:44 PM PDT 24
Finished Jul 15 05:10:13 PM PDT 24
Peak memory 211672 kb
Host smart-41ef8023-3765-44f3-9852-c8b14606b57f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020110681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3020110681
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.764532159
Short name T424
Test name
Test status
Simulation time 21104865431 ps
CPU time 176.02 seconds
Started Jul 15 05:09:44 PM PDT 24
Finished Jul 15 05:12:47 PM PDT 24
Peak memory 214996 kb
Host smart-e7b006f4-b170-40a6-adbe-17f0ab89619a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764532159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.764532159
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2153235428
Short name T69
Test name
Test status
Simulation time 2740890062 ps
CPU time 17.38 seconds
Started Jul 15 05:09:53 PM PDT 24
Finished Jul 15 05:10:13 PM PDT 24
Peak memory 211024 kb
Host smart-1c3f1481-5c8a-45cc-8d9f-621bc482a6f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153235428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2153235428
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2121843808
Short name T433
Test name
Test status
Simulation time 345756240 ps
CPU time 12.07 seconds
Started Jul 15 05:09:47 PM PDT 24
Finished Jul 15 05:10:04 PM PDT 24
Peak memory 217236 kb
Host smart-202f2298-8ded-4263-83d2-3ac7e720da14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121843808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2121843808
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2252537525
Short name T116
Test name
Test status
Simulation time 6367808487 ps
CPU time 90.66 seconds
Started Jul 15 05:09:44 PM PDT 24
Finished Jul 15 05:11:22 PM PDT 24
Peak memory 213812 kb
Host smart-ebfd26dd-ec79-48a2-b344-5b69ac306074
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252537525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2252537525
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2130488795
Short name T450
Test name
Test status
Simulation time 2439638272 ps
CPU time 22.74 seconds
Started Jul 15 05:09:55 PM PDT 24
Finished Jul 15 05:10:22 PM PDT 24
Peak memory 214612 kb
Host smart-43e82193-03c5-4ff6-a87c-3f77ff9c048d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130488795 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2130488795
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.594124313
Short name T435
Test name
Test status
Simulation time 1516528114 ps
CPU time 16.87 seconds
Started Jul 15 05:09:56 PM PDT 24
Finished Jul 15 05:10:16 PM PDT 24
Peak memory 211872 kb
Host smart-96d0eefc-02db-4dd8-be6b-be61604128ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594124313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.594124313
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2108495301
Short name T370
Test name
Test status
Simulation time 16704987733 ps
CPU time 128.11 seconds
Started Jul 15 05:09:55 PM PDT 24
Finished Jul 15 05:12:07 PM PDT 24
Peak memory 214028 kb
Host smart-5c9fc2df-c3ee-46c1-b46b-c60ca35c7ce3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108495301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2108495301
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1044846488
Short name T395
Test name
Test status
Simulation time 12974669660 ps
CPU time 27.22 seconds
Started Jul 15 05:09:53 PM PDT 24
Finished Jul 15 05:10:23 PM PDT 24
Peak memory 212768 kb
Host smart-8260a059-e60a-4224-a6b7-015307ee01cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044846488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1044846488
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3436482314
Short name T371
Test name
Test status
Simulation time 8565288845 ps
CPU time 34.36 seconds
Started Jul 15 05:09:55 PM PDT 24
Finished Jul 15 05:10:33 PM PDT 24
Peak memory 218904 kb
Host smart-f0bd564f-ffd0-4d4a-ba21-4baf6583c670
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436482314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3436482314
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.38982983
Short name T113
Test name
Test status
Simulation time 3619791988 ps
CPU time 160.52 seconds
Started Jul 15 05:09:59 PM PDT 24
Finished Jul 15 05:12:43 PM PDT 24
Peak memory 213912 kb
Host smart-c67e2a00-be0a-4b87-8234-907c639559f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38982983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_intg
_err.38982983
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1795603481
Short name T374
Test name
Test status
Simulation time 14200608407 ps
CPU time 29.81 seconds
Started Jul 15 05:10:05 PM PDT 24
Finished Jul 15 05:10:38 PM PDT 24
Peak memory 217004 kb
Host smart-ccc78914-37b4-443e-9591-effeadb895e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795603481 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1795603481
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2888082736
Short name T459
Test name
Test status
Simulation time 8553749774 ps
CPU time 21.93 seconds
Started Jul 15 05:10:02 PM PDT 24
Finished Jul 15 05:10:28 PM PDT 24
Peak memory 212268 kb
Host smart-6e20bbfd-c427-4656-8b92-1037160e21fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888082736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2888082736
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3584342142
Short name T91
Test name
Test status
Simulation time 34808537203 ps
CPU time 131.46 seconds
Started Jul 15 05:09:55 PM PDT 24
Finished Jul 15 05:12:10 PM PDT 24
Peak memory 214068 kb
Host smart-80914780-588e-45c4-af8e-223b2f20883b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584342142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3584342142
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3948791863
Short name T454
Test name
Test status
Simulation time 15022951501 ps
CPU time 34.85 seconds
Started Jul 15 05:10:04 PM PDT 24
Finished Jul 15 05:10:42 PM PDT 24
Peak memory 212408 kb
Host smart-68b2af75-3b00-44e6-ae2a-ba1a675d237d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948791863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3948791863
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2226430238
Short name T364
Test name
Test status
Simulation time 6727687243 ps
CPU time 37.77 seconds
Started Jul 15 05:09:55 PM PDT 24
Finished Jul 15 05:10:36 PM PDT 24
Peak memory 218688 kb
Host smart-85d36fd9-613c-4ab6-8a86-2d9d755e9fef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226430238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2226430238
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3780791583
Short name T120
Test name
Test status
Simulation time 3793123748 ps
CPU time 100.14 seconds
Started Jul 15 05:10:04 PM PDT 24
Finished Jul 15 05:11:47 PM PDT 24
Peak memory 213508 kb
Host smart-ffd35147-929e-43ea-8e40-c6d8e1ffe93d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780791583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3780791583
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2655833679
Short name T283
Test name
Test status
Simulation time 332123238 ps
CPU time 8.23 seconds
Started Jul 15 05:19:55 PM PDT 24
Finished Jul 15 05:20:04 PM PDT 24
Peak memory 217188 kb
Host smart-97b03d13-8085-470e-b060-0b25d265e6d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655833679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2655833679
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1287646085
Short name T32
Test name
Test status
Simulation time 183461141239 ps
CPU time 509.91 seconds
Started Jul 15 05:19:48 PM PDT 24
Finished Jul 15 05:28:19 PM PDT 24
Peak memory 227784 kb
Host smart-c71c13d9-020a-449f-952e-efb3706b7379
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287646085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1287646085
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1041480588
Short name T205
Test name
Test status
Simulation time 1831366768 ps
CPU time 19.73 seconds
Started Jul 15 05:19:40 PM PDT 24
Finished Jul 15 05:20:01 PM PDT 24
Peak memory 219212 kb
Host smart-fd4e17cf-fa7a-4584-9219-25645c9eaefa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1041480588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1041480588
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2970153363
Short name T29
Test name
Test status
Simulation time 4501089730 ps
CPU time 236.67 seconds
Started Jul 15 05:19:46 PM PDT 24
Finished Jul 15 05:23:43 PM PDT 24
Peak memory 238340 kb
Host smart-555e5624-615d-4784-a454-07efbd43059e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970153363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2970153363
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3189925320
Short name T326
Test name
Test status
Simulation time 2361137407 ps
CPU time 29.43 seconds
Started Jul 15 05:19:39 PM PDT 24
Finished Jul 15 05:20:09 PM PDT 24
Peak memory 216760 kb
Host smart-40f57076-e8e6-452f-9ae5-e8b67a43cf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189925320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3189925320
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.788506874
Short name T36
Test name
Test status
Simulation time 55181387735 ps
CPU time 562.79 seconds
Started Jul 15 05:19:54 PM PDT 24
Finished Jul 15 05:29:18 PM PDT 24
Peak memory 239648 kb
Host smart-03945f35-3848-4df7-9acc-c2e47d7243a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788506874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.788506874
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3580831131
Short name T243
Test name
Test status
Simulation time 11234463832 ps
CPU time 51.33 seconds
Started Jul 15 05:19:55 PM PDT 24
Finished Jul 15 05:20:47 PM PDT 24
Peak memory 219328 kb
Host smart-b387c946-7fac-4b8c-bb5e-06b49cfe31e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580831131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3580831131
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.351005732
Short name T121
Test name
Test status
Simulation time 15860574115 ps
CPU time 31.83 seconds
Started Jul 15 05:19:57 PM PDT 24
Finished Jul 15 05:20:29 PM PDT 24
Peak memory 219244 kb
Host smart-3ea844c1-d030-4367-8535-234c0af8d0d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=351005732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.351005732
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2044696576
Short name T21
Test name
Test status
Simulation time 264673148 ps
CPU time 118.86 seconds
Started Jul 15 05:20:02 PM PDT 24
Finished Jul 15 05:22:02 PM PDT 24
Peak memory 237352 kb
Host smart-0537dbd0-5dc7-4a9d-b6ff-9581ad4e2023
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044696576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2044696576
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.539876316
Short name T17
Test name
Test status
Simulation time 7678443829 ps
CPU time 68.86 seconds
Started Jul 15 05:19:55 PM PDT 24
Finished Jul 15 05:21:05 PM PDT 24
Peak memory 217604 kb
Host smart-eb5327c0-b915-489c-b05b-4cd84b3dee77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539876316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.539876316
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3192698745
Short name T4
Test name
Test status
Simulation time 24891022273 ps
CPU time 42.49 seconds
Started Jul 15 05:19:55 PM PDT 24
Finished Jul 15 05:20:38 PM PDT 24
Peak memory 219256 kb
Host smart-2c7ad1db-c8c1-4af4-a918-0e5d0707020a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192698745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3192698745
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1267202009
Short name T305
Test name
Test status
Simulation time 494342578 ps
CPU time 11.97 seconds
Started Jul 15 05:21:09 PM PDT 24
Finished Jul 15 05:21:22 PM PDT 24
Peak memory 216544 kb
Host smart-63f91261-62c4-4e4e-81b3-065049b4f832
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267202009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1267202009
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.880406491
Short name T42
Test name
Test status
Simulation time 71182335686 ps
CPU time 654.44 seconds
Started Jul 15 05:21:09 PM PDT 24
Finished Jul 15 05:32:04 PM PDT 24
Peak memory 240076 kb
Host smart-0a9001ee-8ce0-491f-8124-68fc001c46ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880406491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.880406491
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3784677194
Short name T215
Test name
Test status
Simulation time 7755668930 ps
CPU time 68.34 seconds
Started Jul 15 05:21:10 PM PDT 24
Finished Jul 15 05:22:19 PM PDT 24
Peak memory 219236 kb
Host smart-2dc973f9-d89b-4712-934d-4b6d05a8fd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784677194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3784677194
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1119865416
Short name T122
Test name
Test status
Simulation time 12625181196 ps
CPU time 28.32 seconds
Started Jul 15 05:21:07 PM PDT 24
Finished Jul 15 05:21:36 PM PDT 24
Peak memory 219284 kb
Host smart-207b97d5-c40f-4840-9ae0-7f1f13a7f94c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1119865416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1119865416
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1434643056
Short name T297
Test name
Test status
Simulation time 6998105980 ps
CPU time 64.87 seconds
Started Jul 15 05:21:09 PM PDT 24
Finished Jul 15 05:22:15 PM PDT 24
Peak memory 216852 kb
Host smart-c8c6a118-47de-4588-97a0-1f7c24d67254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434643056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1434643056
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3496059142
Short name T268
Test name
Test status
Simulation time 6225068097 ps
CPU time 67.51 seconds
Started Jul 15 05:21:08 PM PDT 24
Finished Jul 15 05:22:16 PM PDT 24
Peak memory 219336 kb
Host smart-efb75c65-e797-4428-9c4b-29fc789e0c55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496059142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3496059142
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3408972542
Short name T233
Test name
Test status
Simulation time 4064228647 ps
CPU time 30.86 seconds
Started Jul 15 05:21:16 PM PDT 24
Finished Jul 15 05:21:48 PM PDT 24
Peak memory 217252 kb
Host smart-258217ab-9938-4056-9c2b-641433451e77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408972542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3408972542
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2147878678
Short name T184
Test name
Test status
Simulation time 391979442850 ps
CPU time 949.56 seconds
Started Jul 15 05:21:10 PM PDT 24
Finished Jul 15 05:37:00 PM PDT 24
Peak memory 237284 kb
Host smart-c91ad356-2dbd-4a06-8207-67b0f580b58f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147878678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2147878678
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3060684764
Short name T208
Test name
Test status
Simulation time 92880003328 ps
CPU time 56.91 seconds
Started Jul 15 05:21:08 PM PDT 24
Finished Jul 15 05:22:06 PM PDT 24
Peak memory 219252 kb
Host smart-0afcd522-9631-4cda-a00d-b73292cabbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060684764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3060684764
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2156316549
Short name T156
Test name
Test status
Simulation time 184901009 ps
CPU time 10.52 seconds
Started Jul 15 05:21:09 PM PDT 24
Finished Jul 15 05:21:20 PM PDT 24
Peak memory 219264 kb
Host smart-18fb95e8-a729-4800-be3b-f09283450aed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2156316549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2156316549
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.1096180026
Short name T273
Test name
Test status
Simulation time 8383275175 ps
CPU time 68.26 seconds
Started Jul 15 05:21:07 PM PDT 24
Finished Jul 15 05:22:16 PM PDT 24
Peak memory 216584 kb
Host smart-27e4189e-fcf2-4eab-875c-3437053fd289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096180026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1096180026
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3289880243
Short name T358
Test name
Test status
Simulation time 3469125825 ps
CPU time 53.66 seconds
Started Jul 15 05:21:09 PM PDT 24
Finished Jul 15 05:22:03 PM PDT 24
Peak memory 219340 kb
Host smart-b8b2e9b9-3ebe-4f24-bee3-ef245b9856c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289880243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3289880243
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1721611770
Short name T230
Test name
Test status
Simulation time 1362399531 ps
CPU time 10.79 seconds
Started Jul 15 05:21:24 PM PDT 24
Finished Jul 15 05:21:35 PM PDT 24
Peak memory 217196 kb
Host smart-0aa5d667-6b43-4ae9-81b1-d23265a72088
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721611770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1721611770
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2591734775
Short name T249
Test name
Test status
Simulation time 68169806039 ps
CPU time 727.57 seconds
Started Jul 15 05:21:18 PM PDT 24
Finished Jul 15 05:33:27 PM PDT 24
Peak memory 234544 kb
Host smart-d6cd5d6c-893e-45b5-bdbb-5747603be2af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591734775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2591734775
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.989077852
Short name T299
Test name
Test status
Simulation time 676109121 ps
CPU time 18.74 seconds
Started Jul 15 05:21:16 PM PDT 24
Finished Jul 15 05:21:35 PM PDT 24
Peak memory 219264 kb
Host smart-e6182cc4-38a5-43ac-a789-a2830626e058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989077852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.989077852
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2421648354
Short name T172
Test name
Test status
Simulation time 263642971 ps
CPU time 12.06 seconds
Started Jul 15 05:21:17 PM PDT 24
Finished Jul 15 05:21:29 PM PDT 24
Peak memory 219292 kb
Host smart-324f8a02-3e6c-4329-9a52-b657b96c6f3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2421648354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2421648354
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1919768123
Short name T79
Test name
Test status
Simulation time 721112450 ps
CPU time 20.88 seconds
Started Jul 15 05:21:18 PM PDT 24
Finished Jul 15 05:21:40 PM PDT 24
Peak memory 215936 kb
Host smart-7f8e9dee-efa9-4ff0-b018-9c357fe4377b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919768123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1919768123
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2694935891
Short name T45
Test name
Test status
Simulation time 166089213503 ps
CPU time 1629.31 seconds
Started Jul 15 05:21:25 PM PDT 24
Finished Jul 15 05:48:35 PM PDT 24
Peak memory 239016 kb
Host smart-70f857e6-59f9-4f6b-b96f-32cbff2e3b8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694935891 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.2694935891
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2405702707
Short name T170
Test name
Test status
Simulation time 18505250826 ps
CPU time 32.16 seconds
Started Jul 15 05:21:33 PM PDT 24
Finished Jul 15 05:22:06 PM PDT 24
Peak memory 217396 kb
Host smart-51713f90-8f37-414e-bd21-1b73d98ac5eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405702707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2405702707
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2813557551
Short name T293
Test name
Test status
Simulation time 266607845838 ps
CPU time 662.6 seconds
Started Jul 15 05:21:26 PM PDT 24
Finished Jul 15 05:32:29 PM PDT 24
Peak memory 238324 kb
Host smart-b0cafb80-dacb-4208-a696-b7a051d896fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813557551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2813557551
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3307498614
Short name T199
Test name
Test status
Simulation time 16392274690 ps
CPU time 42.8 seconds
Started Jul 15 05:21:26 PM PDT 24
Finished Jul 15 05:22:09 PM PDT 24
Peak memory 219300 kb
Host smart-58501c97-e8e6-4f11-a8ea-50831b80caec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307498614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3307498614
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3408316285
Short name T124
Test name
Test status
Simulation time 1576771643 ps
CPU time 20.48 seconds
Started Jul 15 05:21:24 PM PDT 24
Finished Jul 15 05:21:46 PM PDT 24
Peak memory 219280 kb
Host smart-00f14a19-c666-4283-8afc-44364e75f154
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3408316285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3408316285
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1842056046
Short name T338
Test name
Test status
Simulation time 31340156351 ps
CPU time 38.78 seconds
Started Jul 15 05:21:25 PM PDT 24
Finished Jul 15 05:22:05 PM PDT 24
Peak memory 216700 kb
Host smart-9f576679-6d99-4a7f-a4ea-26aabc104244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842056046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1842056046
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3231556358
Short name T143
Test name
Test status
Simulation time 2425211488 ps
CPU time 35.01 seconds
Started Jul 15 05:21:25 PM PDT 24
Finished Jul 15 05:22:00 PM PDT 24
Peak memory 215600 kb
Host smart-689253cb-3552-4088-9cf6-3de1659d4613
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231556358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3231556358
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1480611710
Short name T54
Test name
Test status
Simulation time 33069597555 ps
CPU time 31.63 seconds
Started Jul 15 05:21:32 PM PDT 24
Finished Jul 15 05:22:04 PM PDT 24
Peak memory 217520 kb
Host smart-17b4eb3b-1937-460e-b5e9-f3988dec5b5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480611710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1480611710
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2970566298
Short name T130
Test name
Test status
Simulation time 311476986537 ps
CPU time 889.9 seconds
Started Jul 15 05:21:32 PM PDT 24
Finished Jul 15 05:36:23 PM PDT 24
Peak memory 237276 kb
Host smart-3436b182-3bf8-44fd-b4c5-7fdfdc659606
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970566298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2970566298
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2384672453
Short name T352
Test name
Test status
Simulation time 4346826130 ps
CPU time 35.53 seconds
Started Jul 15 05:21:32 PM PDT 24
Finished Jul 15 05:22:08 PM PDT 24
Peak memory 211980 kb
Host smart-d7033f86-e22b-49af-afdb-14b7e771a1de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2384672453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2384672453
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2055665317
Short name T160
Test name
Test status
Simulation time 7789882979 ps
CPU time 29.75 seconds
Started Jul 15 05:21:32 PM PDT 24
Finished Jul 15 05:22:02 PM PDT 24
Peak memory 216564 kb
Host smart-50fc289b-f00e-4a34-a525-3a768b155dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055665317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2055665317
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3412642676
Short name T309
Test name
Test status
Simulation time 32639557402 ps
CPU time 46.98 seconds
Started Jul 15 05:21:31 PM PDT 24
Finished Jul 15 05:22:19 PM PDT 24
Peak memory 219500 kb
Host smart-bfa1e260-c1ee-4754-a316-df015688a7bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412642676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3412642676
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.491360842
Short name T46
Test name
Test status
Simulation time 106549290539 ps
CPU time 1031.97 seconds
Started Jul 15 05:21:32 PM PDT 24
Finished Jul 15 05:38:45 PM PDT 24
Peak memory 235740 kb
Host smart-e8e3df9b-3923-4256-a5c6-a8ed59cf44e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491360842 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.491360842
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2887142844
Short name T261
Test name
Test status
Simulation time 174501076 ps
CPU time 8.54 seconds
Started Jul 15 05:21:50 PM PDT 24
Finished Jul 15 05:22:00 PM PDT 24
Peak memory 213232 kb
Host smart-d1e8e5de-e2c6-4e33-91a7-fee9228e17c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887142844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2887142844
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1673084475
Short name T171
Test name
Test status
Simulation time 168189111166 ps
CPU time 427.29 seconds
Started Jul 15 05:21:42 PM PDT 24
Finished Jul 15 05:28:50 PM PDT 24
Peak memory 219500 kb
Host smart-2471c18d-1946-4a2f-81a4-1d1c2a3f9e88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673084475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1673084475
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1513699067
Short name T287
Test name
Test status
Simulation time 1687271265 ps
CPU time 25.76 seconds
Started Jul 15 05:21:41 PM PDT 24
Finished Jul 15 05:22:07 PM PDT 24
Peak memory 219240 kb
Host smart-e2e357f4-9ac9-4977-bdbd-57ca1f3e5eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513699067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1513699067
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3294478139
Short name T178
Test name
Test status
Simulation time 179762457 ps
CPU time 10.57 seconds
Started Jul 15 05:21:40 PM PDT 24
Finished Jul 15 05:21:51 PM PDT 24
Peak memory 219180 kb
Host smart-fe081b73-ceba-40a1-81da-d8cf9a70f5fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3294478139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3294478139
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1709940142
Short name T77
Test name
Test status
Simulation time 787909563 ps
CPU time 20.3 seconds
Started Jul 15 05:21:32 PM PDT 24
Finished Jul 15 05:21:53 PM PDT 24
Peak memory 216292 kb
Host smart-0fe6be56-50e4-4fb5-9aba-dd3a45b0722c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709940142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1709940142
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.170786761
Short name T334
Test name
Test status
Simulation time 427237240 ps
CPU time 17.75 seconds
Started Jul 15 05:21:32 PM PDT 24
Finished Jul 15 05:21:50 PM PDT 24
Peak memory 219308 kb
Host smart-a460bd99-51ac-4018-993d-aae7e74a12a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170786761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.170786761
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.2587238126
Short name T361
Test name
Test status
Simulation time 86690166577 ps
CPU time 3276.7 seconds
Started Jul 15 05:21:40 PM PDT 24
Finished Jul 15 06:16:18 PM PDT 24
Peak memory 252192 kb
Host smart-403f5467-bdc6-4068-81ba-3b43dfb81678
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587238126 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.2587238126
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.444745812
Short name T195
Test name
Test status
Simulation time 2002571709 ps
CPU time 20.18 seconds
Started Jul 15 05:21:51 PM PDT 24
Finished Jul 15 05:22:12 PM PDT 24
Peak memory 217188 kb
Host smart-dd5401f0-9f58-48c3-9cc6-dc8a737bbc9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444745812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.444745812
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3381364235
Short name T218
Test name
Test status
Simulation time 3712473631 ps
CPU time 239.58 seconds
Started Jul 15 05:21:49 PM PDT 24
Finished Jul 15 05:25:49 PM PDT 24
Peak memory 238728 kb
Host smart-0409905d-9aa8-427e-ae8b-838bd68dbb31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381364235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3381364235
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.435503136
Short name T290
Test name
Test status
Simulation time 5157183508 ps
CPU time 52.53 seconds
Started Jul 15 05:21:50 PM PDT 24
Finished Jul 15 05:22:43 PM PDT 24
Peak memory 219144 kb
Host smart-fadd23fe-01ad-4bfd-bd8a-ec05b029a9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435503136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.435503136
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.102404461
Short name T270
Test name
Test status
Simulation time 776193165 ps
CPU time 15.28 seconds
Started Jul 15 05:21:50 PM PDT 24
Finished Jul 15 05:22:06 PM PDT 24
Peak memory 219220 kb
Host smart-214b4add-e9ca-4c85-a7f8-f142dbaf8c06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=102404461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.102404461
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3718470908
Short name T176
Test name
Test status
Simulation time 14721130317 ps
CPU time 63.71 seconds
Started Jul 15 05:21:51 PM PDT 24
Finished Jul 15 05:22:55 PM PDT 24
Peak memory 216416 kb
Host smart-f2744464-4b2f-423a-a4d4-e22a8650bd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718470908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3718470908
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2027906636
Short name T144
Test name
Test status
Simulation time 1915524656 ps
CPU time 21.97 seconds
Started Jul 15 05:21:50 PM PDT 24
Finished Jul 15 05:22:12 PM PDT 24
Peak memory 218636 kb
Host smart-4eaedd04-7fd1-41b0-bb7c-1eef0b168fa1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027906636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2027906636
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.271898891
Short name T95
Test name
Test status
Simulation time 8479443382 ps
CPU time 26.81 seconds
Started Jul 15 05:21:56 PM PDT 24
Finished Jul 15 05:22:24 PM PDT 24
Peak memory 217532 kb
Host smart-85db45a8-88fe-452c-af5f-13688e77ea96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271898891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.271898891
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2164775705
Short name T265
Test name
Test status
Simulation time 2954637210 ps
CPU time 189.71 seconds
Started Jul 15 05:21:58 PM PDT 24
Finished Jul 15 05:25:08 PM PDT 24
Peak memory 237924 kb
Host smart-64ca6ab4-5fd0-49d1-9603-b6a4a650b60e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164775705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2164775705
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1300656281
Short name T175
Test name
Test status
Simulation time 16481633872 ps
CPU time 37.95 seconds
Started Jul 15 05:21:54 PM PDT 24
Finished Jul 15 05:22:33 PM PDT 24
Peak memory 219272 kb
Host smart-5d26cd36-e495-43d0-a6d7-8f03d67ec728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300656281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1300656281
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3939172687
Short name T306
Test name
Test status
Simulation time 723515344 ps
CPU time 10.65 seconds
Started Jul 15 05:21:58 PM PDT 24
Finished Jul 15 05:22:09 PM PDT 24
Peak memory 219284 kb
Host smart-c943f185-3eb4-426c-8a4d-ccda07f3208b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3939172687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3939172687
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1775416070
Short name T136
Test name
Test status
Simulation time 18711283434 ps
CPU time 49.17 seconds
Started Jul 15 05:21:50 PM PDT 24
Finished Jul 15 05:22:41 PM PDT 24
Peak memory 217072 kb
Host smart-3bd5b6b5-18d7-4560-a595-b6e6396feea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775416070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1775416070
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3650118208
Short name T244
Test name
Test status
Simulation time 853655693 ps
CPU time 18.59 seconds
Started Jul 15 05:21:50 PM PDT 24
Finished Jul 15 05:22:10 PM PDT 24
Peak memory 219304 kb
Host smart-1ea4b25c-4183-4094-8e86-aff0f63b3f1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650118208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3650118208
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3168101274
Short name T180
Test name
Test status
Simulation time 8534362453 ps
CPU time 31.28 seconds
Started Jul 15 05:22:12 PM PDT 24
Finished Jul 15 05:22:44 PM PDT 24
Peak memory 217476 kb
Host smart-2db775d4-dc2d-42a8-9006-8e0b528954b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168101274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3168101274
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3257632139
Short name T181
Test name
Test status
Simulation time 124250017094 ps
CPU time 557.91 seconds
Started Jul 15 05:22:03 PM PDT 24
Finished Jul 15 05:31:22 PM PDT 24
Peak memory 238748 kb
Host smart-2f6e41d7-83f7-476f-8643-5d8649c217da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257632139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3257632139
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1399294760
Short name T134
Test name
Test status
Simulation time 4176772651 ps
CPU time 44.39 seconds
Started Jul 15 05:22:03 PM PDT 24
Finished Jul 15 05:22:48 PM PDT 24
Peak memory 219264 kb
Host smart-e0153869-4dd5-4d5d-a626-7fd116a5dab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399294760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1399294760
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3041349035
Short name T317
Test name
Test status
Simulation time 3875017553 ps
CPU time 32.44 seconds
Started Jul 15 05:22:03 PM PDT 24
Finished Jul 15 05:22:36 PM PDT 24
Peak memory 211260 kb
Host smart-88d16f91-c3f4-440a-b1d9-872c1878dda9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3041349035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3041349035
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.368292177
Short name T190
Test name
Test status
Simulation time 32979503687 ps
CPU time 63.16 seconds
Started Jul 15 05:22:02 PM PDT 24
Finished Jul 15 05:23:05 PM PDT 24
Peak memory 217372 kb
Host smart-9208a9ed-f4e3-4e6b-beba-06d3bab071f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368292177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.368292177
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2058802922
Short name T10
Test name
Test status
Simulation time 18975352965 ps
CPU time 85.11 seconds
Started Jul 15 05:22:02 PM PDT 24
Finished Jul 15 05:23:28 PM PDT 24
Peak memory 218628 kb
Host smart-0f6cf920-14bf-40c3-8697-977226617196
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058802922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2058802922
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1494326250
Short name T228
Test name
Test status
Simulation time 499276710 ps
CPU time 11.87 seconds
Started Jul 15 05:22:19 PM PDT 24
Finished Jul 15 05:22:32 PM PDT 24
Peak memory 218176 kb
Host smart-d9ad6600-cdfc-4080-a08f-e932208071c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494326250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1494326250
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.4140117135
Short name T216
Test name
Test status
Simulation time 151649025809 ps
CPU time 388.63 seconds
Started Jul 15 05:22:18 PM PDT 24
Finished Jul 15 05:28:48 PM PDT 24
Peak memory 219448 kb
Host smart-cd915b94-ac53-48bb-9ab1-9166caaa8b23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140117135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.4140117135
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2335659618
Short name T53
Test name
Test status
Simulation time 22274156899 ps
CPU time 54.37 seconds
Started Jul 15 05:22:18 PM PDT 24
Finished Jul 15 05:23:13 PM PDT 24
Peak memory 219356 kb
Host smart-e9512022-bbec-4dc7-aaa8-18e814c90f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335659618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2335659618
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3774545005
Short name T141
Test name
Test status
Simulation time 16776353690 ps
CPU time 34.9 seconds
Started Jul 15 05:22:19 PM PDT 24
Finished Jul 15 05:22:54 PM PDT 24
Peak memory 211956 kb
Host smart-5e31a0ca-af28-49da-9ecc-3fc443df5428
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3774545005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3774545005
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.2237756447
Short name T148
Test name
Test status
Simulation time 3483116944 ps
CPU time 26.19 seconds
Started Jul 15 05:22:10 PM PDT 24
Finished Jul 15 05:22:36 PM PDT 24
Peak memory 216348 kb
Host smart-c2af983b-e646-4afa-b8d7-2736efa38d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237756447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.2237756447
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1602081336
Short name T237
Test name
Test status
Simulation time 4614415958 ps
CPU time 64.88 seconds
Started Jul 15 05:22:11 PM PDT 24
Finished Jul 15 05:23:16 PM PDT 24
Peak memory 219308 kb
Host smart-81e97e71-097a-4c93-b5ac-284e4f6e18ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602081336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1602081336
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.617023530
Short name T97
Test name
Test status
Simulation time 2121915093 ps
CPU time 22.6 seconds
Started Jul 15 05:20:02 PM PDT 24
Finished Jul 15 05:20:25 PM PDT 24
Peak memory 217032 kb
Host smart-a514b7ff-fd6c-4ca8-8fe2-41bf56c92896
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617023530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.617023530
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.4261446484
Short name T162
Test name
Test status
Simulation time 54827625142 ps
CPU time 597.02 seconds
Started Jul 15 05:20:05 PM PDT 24
Finished Jul 15 05:30:02 PM PDT 24
Peak memory 229596 kb
Host smart-d723691f-f74b-4aef-9a89-26761f68b78e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261446484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.4261446484
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2473710212
Short name T159
Test name
Test status
Simulation time 9543522048 ps
CPU time 47.7 seconds
Started Jul 15 05:20:03 PM PDT 24
Finished Jul 15 05:20:51 PM PDT 24
Peak memory 219316 kb
Host smart-bbe375f4-57e1-4214-b2ad-a233863dd9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473710212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2473710212
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3334351022
Short name T232
Test name
Test status
Simulation time 364986863 ps
CPU time 10.77 seconds
Started Jul 15 05:20:02 PM PDT 24
Finished Jul 15 05:20:14 PM PDT 24
Peak memory 219276 kb
Host smart-995aa836-39d4-4a88-bc8c-9cb68b133e93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3334351022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3334351022
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.4102630447
Short name T30
Test name
Test status
Simulation time 12453547976 ps
CPU time 232.09 seconds
Started Jul 15 05:20:04 PM PDT 24
Finished Jul 15 05:23:57 PM PDT 24
Peak memory 237980 kb
Host smart-77ce1065-92e6-4866-b9fa-718d0282bf07
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102630447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.4102630447
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.515943691
Short name T313
Test name
Test status
Simulation time 26796537978 ps
CPU time 58.98 seconds
Started Jul 15 05:20:01 PM PDT 24
Finished Jul 15 05:21:01 PM PDT 24
Peak memory 215576 kb
Host smart-57bfa2a4-add2-499f-9467-dfc646f8d01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515943691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.515943691
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.640930622
Short name T204
Test name
Test status
Simulation time 128339271552 ps
CPU time 113.06 seconds
Started Jul 15 05:20:03 PM PDT 24
Finished Jul 15 05:21:57 PM PDT 24
Peak memory 220524 kb
Host smart-ae682755-e509-4e78-9a4b-1144d4995563
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640930622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.640930622
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3374488593
Short name T307
Test name
Test status
Simulation time 4916782218 ps
CPU time 15.97 seconds
Started Jul 15 05:22:27 PM PDT 24
Finished Jul 15 05:22:44 PM PDT 24
Peak memory 217336 kb
Host smart-dd896395-daaf-49f0-97dc-0c9eb22a9c2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374488593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3374488593
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3574882866
Short name T35
Test name
Test status
Simulation time 64052544787 ps
CPU time 573.78 seconds
Started Jul 15 05:22:26 PM PDT 24
Finished Jul 15 05:32:01 PM PDT 24
Peak memory 237892 kb
Host smart-e6e32391-1967-422b-b773-0195b41d9bcd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574882866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3574882866
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.495513306
Short name T28
Test name
Test status
Simulation time 55817968198 ps
CPU time 38.03 seconds
Started Jul 15 05:22:25 PM PDT 24
Finished Jul 15 05:23:03 PM PDT 24
Peak memory 219212 kb
Host smart-74d78ec4-71db-4858-87b5-6fb7207b1180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495513306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.495513306
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2865483038
Short name T355
Test name
Test status
Simulation time 1542243601 ps
CPU time 19.22 seconds
Started Jul 15 05:22:22 PM PDT 24
Finished Jul 15 05:22:41 PM PDT 24
Peak memory 219324 kb
Host smart-366a8c5c-45a7-42c3-9862-2e141304eb4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2865483038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2865483038
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2010458573
Short name T272
Test name
Test status
Simulation time 1002046013 ps
CPU time 27.09 seconds
Started Jul 15 05:22:19 PM PDT 24
Finished Jul 15 05:22:47 PM PDT 24
Peak memory 216824 kb
Host smart-36340eb4-37d8-49e6-a9d0-cb464179ba5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010458573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2010458573
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2500739819
Short name T126
Test name
Test status
Simulation time 1020230495 ps
CPU time 38.27 seconds
Started Jul 15 05:22:19 PM PDT 24
Finished Jul 15 05:22:57 PM PDT 24
Peak memory 219216 kb
Host smart-38ee314f-7931-4084-9b27-a98cf9a3a704
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500739819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2500739819
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3314261468
Short name T224
Test name
Test status
Simulation time 4030936523 ps
CPU time 31.5 seconds
Started Jul 15 05:22:27 PM PDT 24
Finished Jul 15 05:22:59 PM PDT 24
Peak memory 217084 kb
Host smart-b0f5b673-fee3-4e69-ab63-bc4337e8775c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314261468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3314261468
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3045488342
Short name T254
Test name
Test status
Simulation time 30673047037 ps
CPU time 407.58 seconds
Started Jul 15 05:22:26 PM PDT 24
Finished Jul 15 05:29:15 PM PDT 24
Peak memory 241512 kb
Host smart-badd705e-5877-44ad-950c-0fa87b87560e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045488342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3045488342
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3144522171
Short name T339
Test name
Test status
Simulation time 8200774591 ps
CPU time 31.4 seconds
Started Jul 15 05:22:26 PM PDT 24
Finished Jul 15 05:22:58 PM PDT 24
Peak memory 219336 kb
Host smart-09f87c8a-c8cf-45bd-8f74-d4e81627173c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144522171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3144522171
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3179180408
Short name T203
Test name
Test status
Simulation time 46220656197 ps
CPU time 31.15 seconds
Started Jul 15 05:22:26 PM PDT 24
Finished Jul 15 05:22:57 PM PDT 24
Peak memory 219328 kb
Host smart-153bca12-6da1-4e8a-9e99-146675f863a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3179180408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3179180408
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2764982323
Short name T49
Test name
Test status
Simulation time 8027828300 ps
CPU time 72.2 seconds
Started Jul 15 05:22:27 PM PDT 24
Finished Jul 15 05:23:40 PM PDT 24
Peak memory 217384 kb
Host smart-f9201435-6b67-4731-965a-0310cc1eca26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764982323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2764982323
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3469422128
Short name T197
Test name
Test status
Simulation time 74020169370 ps
CPU time 166.59 seconds
Started Jul 15 05:22:26 PM PDT 24
Finished Jul 15 05:25:13 PM PDT 24
Peak memory 222060 kb
Host smart-e274c072-c246-4a35-bde3-d8dcd807dac1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469422128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3469422128
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.4029519941
Short name T210
Test name
Test status
Simulation time 3305607603 ps
CPU time 28.64 seconds
Started Jul 15 05:22:36 PM PDT 24
Finished Jul 15 05:23:05 PM PDT 24
Peak memory 217144 kb
Host smart-dc74ead3-f5e7-4482-9abf-a73fc9cfaceb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029519941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.4029519941
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2073677922
Short name T337
Test name
Test status
Simulation time 40208681009 ps
CPU time 500.6 seconds
Started Jul 15 05:22:34 PM PDT 24
Finished Jul 15 05:30:55 PM PDT 24
Peak memory 236104 kb
Host smart-7f055161-689c-4c94-a331-3c0621301c62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073677922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2073677922
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.4199156855
Short name T318
Test name
Test status
Simulation time 346569516 ps
CPU time 19.34 seconds
Started Jul 15 05:22:36 PM PDT 24
Finished Jul 15 05:22:56 PM PDT 24
Peak memory 219244 kb
Host smart-faef64f2-a03e-4ac8-a6f7-4e4b472e0f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199156855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.4199156855
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2816033007
Short name T135
Test name
Test status
Simulation time 10322960530 ps
CPU time 24.77 seconds
Started Jul 15 05:22:33 PM PDT 24
Finished Jul 15 05:22:58 PM PDT 24
Peak memory 211824 kb
Host smart-13f49caf-4c00-484a-8678-3d4dfe09036a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2816033007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2816033007
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.590581782
Short name T292
Test name
Test status
Simulation time 3021879654 ps
CPU time 41.24 seconds
Started Jul 15 05:22:35 PM PDT 24
Finished Jul 15 05:23:17 PM PDT 24
Peak memory 215896 kb
Host smart-81252df4-d5a5-4a15-a8bd-b0fda37365e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590581782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.590581782
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.782450319
Short name T163
Test name
Test status
Simulation time 8926337139 ps
CPU time 74.18 seconds
Started Jul 15 05:22:34 PM PDT 24
Finished Jul 15 05:23:49 PM PDT 24
Peak memory 216916 kb
Host smart-0a3111a9-337c-4e8b-8f5d-6ae3904d0939
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782450319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.782450319
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2901823050
Short name T150
Test name
Test status
Simulation time 3933869249 ps
CPU time 31.28 seconds
Started Jul 15 05:22:43 PM PDT 24
Finished Jul 15 05:23:15 PM PDT 24
Peak memory 217236 kb
Host smart-391e5304-899d-4a4c-9412-35fa4864cad4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901823050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2901823050
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2597981644
Short name T183
Test name
Test status
Simulation time 595181790562 ps
CPU time 778.68 seconds
Started Jul 15 05:22:43 PM PDT 24
Finished Jul 15 05:35:42 PM PDT 24
Peak memory 234820 kb
Host smart-d4767cab-861c-49fb-a646-5fee2a98312c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597981644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2597981644
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.4063011155
Short name T142
Test name
Test status
Simulation time 19028540616 ps
CPU time 47.5 seconds
Started Jul 15 05:22:42 PM PDT 24
Finished Jul 15 05:23:30 PM PDT 24
Peak memory 219332 kb
Host smart-aafb40d1-59ec-4039-9827-c184c72b8d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063011155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.4063011155
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1765733091
Short name T55
Test name
Test status
Simulation time 14137497313 ps
CPU time 19.5 seconds
Started Jul 15 05:22:42 PM PDT 24
Finished Jul 15 05:23:02 PM PDT 24
Peak memory 219228 kb
Host smart-eaa8969e-dcef-440d-8834-d6b3d7e25213
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1765733091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1765733091
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.950130228
Short name T291
Test name
Test status
Simulation time 681132474 ps
CPU time 20.72 seconds
Started Jul 15 05:22:35 PM PDT 24
Finished Jul 15 05:22:56 PM PDT 24
Peak memory 215948 kb
Host smart-12773b95-b324-45b9-a473-538213e0dfe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950130228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.950130228
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1631621009
Short name T347
Test name
Test status
Simulation time 16911926392 ps
CPU time 183.85 seconds
Started Jul 15 05:22:34 PM PDT 24
Finished Jul 15 05:25:39 PM PDT 24
Peak memory 221376 kb
Host smart-1452bb07-5209-4762-9214-cea670efc33c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631621009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1631621009
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2170013628
Short name T26
Test name
Test status
Simulation time 590938097 ps
CPU time 12.05 seconds
Started Jul 15 05:22:43 PM PDT 24
Finished Jul 15 05:22:56 PM PDT 24
Peak memory 217020 kb
Host smart-7fb1544d-43b9-4f34-b633-2002288b0a0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170013628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2170013628
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3923117778
Short name T354
Test name
Test status
Simulation time 64367200441 ps
CPU time 607.78 seconds
Started Jul 15 05:22:41 PM PDT 24
Finished Jul 15 05:32:49 PM PDT 24
Peak memory 233780 kb
Host smart-7d3f0b43-95f7-4fd0-82e4-2195136067c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923117778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3923117778
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1448273178
Short name T274
Test name
Test status
Simulation time 7216971125 ps
CPU time 32.08 seconds
Started Jul 15 05:22:43 PM PDT 24
Finished Jul 15 05:23:16 PM PDT 24
Peak memory 219344 kb
Host smart-cfb37e4e-ae13-4204-bf34-c69185438df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448273178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1448273178
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.845131623
Short name T328
Test name
Test status
Simulation time 1215837111 ps
CPU time 14.36 seconds
Started Jul 15 05:22:44 PM PDT 24
Finished Jul 15 05:22:59 PM PDT 24
Peak memory 219304 kb
Host smart-edb8aadd-1b3a-4dae-bef6-05c524c57a0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=845131623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.845131623
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.25337280
Short name T240
Test name
Test status
Simulation time 1622078049 ps
CPU time 31.78 seconds
Started Jul 15 05:22:42 PM PDT 24
Finished Jul 15 05:23:14 PM PDT 24
Peak memory 215612 kb
Host smart-a3e8da02-379f-4888-a934-54d6f12fa1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25337280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.25337280
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3784594397
Short name T78
Test name
Test status
Simulation time 6593174117 ps
CPU time 60.45 seconds
Started Jul 15 05:22:43 PM PDT 24
Finished Jul 15 05:23:44 PM PDT 24
Peak memory 227460 kb
Host smart-38312482-516e-49e4-be40-21d5b7e9bea8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784594397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3784594397
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3003065037
Short name T248
Test name
Test status
Simulation time 1024414854 ps
CPU time 14.79 seconds
Started Jul 15 05:22:50 PM PDT 24
Finished Jul 15 05:23:06 PM PDT 24
Peak memory 213152 kb
Host smart-b6813387-fe00-4a7a-9314-a3b21fc11da4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003065037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3003065037
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3139818386
Short name T246
Test name
Test status
Simulation time 230735016507 ps
CPU time 651.01 seconds
Started Jul 15 05:22:50 PM PDT 24
Finished Jul 15 05:33:41 PM PDT 24
Peak memory 236100 kb
Host smart-ee724af4-21c5-4780-977c-dcc3fec08d8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139818386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3139818386
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1600881494
Short name T39
Test name
Test status
Simulation time 2749469526 ps
CPU time 19.43 seconds
Started Jul 15 05:22:51 PM PDT 24
Finished Jul 15 05:23:11 PM PDT 24
Peak memory 219292 kb
Host smart-7a1e341b-4a86-4e48-b240-d2f78b21fe29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600881494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1600881494
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1262863148
Short name T133
Test name
Test status
Simulation time 181912076 ps
CPU time 10.12 seconds
Started Jul 15 05:22:51 PM PDT 24
Finished Jul 15 05:23:02 PM PDT 24
Peak memory 219188 kb
Host smart-bc382e98-b074-4cc9-8740-bc7213fdca6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1262863148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1262863148
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2335691049
Short name T296
Test name
Test status
Simulation time 696437943 ps
CPU time 26.11 seconds
Started Jul 15 05:22:43 PM PDT 24
Finished Jul 15 05:23:09 PM PDT 24
Peak memory 216084 kb
Host smart-b2fa76f4-12d5-4aaf-88a4-c217475b909d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335691049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2335691049
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1045491653
Short name T201
Test name
Test status
Simulation time 2119643378 ps
CPU time 29.3 seconds
Started Jul 15 05:22:51 PM PDT 24
Finished Jul 15 05:23:21 PM PDT 24
Peak memory 219172 kb
Host smart-23173b11-ee12-4029-97b8-67696ed9229f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045491653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1045491653
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1778080671
Short name T229
Test name
Test status
Simulation time 170697447 ps
CPU time 8.5 seconds
Started Jul 15 05:22:51 PM PDT 24
Finished Jul 15 05:23:00 PM PDT 24
Peak memory 218200 kb
Host smart-8ac1630a-8be7-459c-8622-271a64372770
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778080671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1778080671
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1638389413
Short name T140
Test name
Test status
Simulation time 951674490508 ps
CPU time 513.33 seconds
Started Jul 15 05:22:50 PM PDT 24
Finished Jul 15 05:31:24 PM PDT 24
Peak memory 239312 kb
Host smart-be13e04f-07fe-46eb-8799-8032eb078a88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638389413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1638389413
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.352449869
Short name T217
Test name
Test status
Simulation time 1315864311 ps
CPU time 29.43 seconds
Started Jul 15 05:22:51 PM PDT 24
Finished Jul 15 05:23:21 PM PDT 24
Peak memory 218668 kb
Host smart-df84299a-9c9d-41d4-96d0-270c5a662c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352449869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.352449869
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1850974985
Short name T227
Test name
Test status
Simulation time 5310459660 ps
CPU time 14.18 seconds
Started Jul 15 05:22:50 PM PDT 24
Finished Jul 15 05:23:05 PM PDT 24
Peak memory 219324 kb
Host smart-99240678-2a36-4f33-ab0b-943a1b028fd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1850974985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1850974985
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2735421143
Short name T200
Test name
Test status
Simulation time 13048721832 ps
CPU time 43 seconds
Started Jul 15 05:22:50 PM PDT 24
Finished Jul 15 05:23:34 PM PDT 24
Peak memory 216004 kb
Host smart-8ad854d7-4fea-4b80-96f4-1c6eeb80db5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735421143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2735421143
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1520257432
Short name T286
Test name
Test status
Simulation time 1497658812 ps
CPU time 11 seconds
Started Jul 15 05:22:51 PM PDT 24
Finished Jul 15 05:23:02 PM PDT 24
Peak memory 214472 kb
Host smart-5f37eb33-f487-46af-8f13-8948b6dafd2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520257432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1520257432
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1131740605
Short name T43
Test name
Test status
Simulation time 101236767685 ps
CPU time 1012.02 seconds
Started Jul 15 05:22:51 PM PDT 24
Finished Jul 15 05:39:44 PM PDT 24
Peak memory 238312 kb
Host smart-71eed3bb-e731-4e76-bba2-f2fc68964b58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131740605 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.1131740605
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2321050250
Short name T284
Test name
Test status
Simulation time 11599423087 ps
CPU time 24.71 seconds
Started Jul 15 05:23:02 PM PDT 24
Finished Jul 15 05:23:27 PM PDT 24
Peak memory 217404 kb
Host smart-a1deeb1a-3648-4c43-9f01-2a965bda7b03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321050250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2321050250
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.48500328
Short name T37
Test name
Test status
Simulation time 675273825 ps
CPU time 19.03 seconds
Started Jul 15 05:22:59 PM PDT 24
Finished Jul 15 05:23:19 PM PDT 24
Peak memory 219268 kb
Host smart-5d6f9175-c6af-4b2f-9df7-7474e376d7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48500328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.48500328
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1307003146
Short name T153
Test name
Test status
Simulation time 11442153952 ps
CPU time 27.49 seconds
Started Jul 15 05:22:58 PM PDT 24
Finished Jul 15 05:23:26 PM PDT 24
Peak memory 211856 kb
Host smart-06ec0da5-f7a3-470b-b9b0-078aec3b274f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1307003146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1307003146
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2717139205
Short name T276
Test name
Test status
Simulation time 352794449 ps
CPU time 20.24 seconds
Started Jul 15 05:22:50 PM PDT 24
Finished Jul 15 05:23:11 PM PDT 24
Peak memory 216400 kb
Host smart-36be6063-f074-4292-840b-4d8f1bd1fe36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717139205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2717139205
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.117887563
Short name T128
Test name
Test status
Simulation time 19331594850 ps
CPU time 166.65 seconds
Started Jul 15 05:22:58 PM PDT 24
Finished Jul 15 05:25:46 PM PDT 24
Peak memory 221968 kb
Host smart-64eb60c1-7071-4850-a8e8-03a155a8fc4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117887563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.117887563
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3376087505
Short name T193
Test name
Test status
Simulation time 12938424857 ps
CPU time 28.9 seconds
Started Jul 15 05:23:07 PM PDT 24
Finished Jul 15 05:23:36 PM PDT 24
Peak memory 217508 kb
Host smart-fc096c1e-7ac6-4454-8316-8070c2c45049
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376087505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3376087505
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.4230049761
Short name T146
Test name
Test status
Simulation time 187734674250 ps
CPU time 453.61 seconds
Started Jul 15 05:22:59 PM PDT 24
Finished Jul 15 05:30:33 PM PDT 24
Peak memory 239716 kb
Host smart-2224d2a8-dc0c-4efa-ad48-d82ab50f9a9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230049761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.4230049761
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3069755101
Short name T348
Test name
Test status
Simulation time 4798775827 ps
CPU time 27.52 seconds
Started Jul 15 05:23:07 PM PDT 24
Finished Jul 15 05:23:35 PM PDT 24
Peak memory 215720 kb
Host smart-e243a1d6-7c0f-4206-9ce0-579d2e685017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069755101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3069755101
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2459031174
Short name T255
Test name
Test status
Simulation time 690147213 ps
CPU time 10.08 seconds
Started Jul 15 05:22:58 PM PDT 24
Finished Jul 15 05:23:09 PM PDT 24
Peak memory 219240 kb
Host smart-7cb40311-a168-4c1d-a1d5-1bb51c196da3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2459031174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2459031174
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.279736919
Short name T263
Test name
Test status
Simulation time 7699570803 ps
CPU time 66.56 seconds
Started Jul 15 05:22:58 PM PDT 24
Finished Jul 15 05:24:05 PM PDT 24
Peak memory 216380 kb
Host smart-0bd3b4ab-05c3-43b8-a7f1-f084b067f1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279736919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.279736919
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3749980064
Short name T302
Test name
Test status
Simulation time 4268970775 ps
CPU time 27.08 seconds
Started Jul 15 05:22:57 PM PDT 24
Finished Jul 15 05:23:25 PM PDT 24
Peak memory 217700 kb
Host smart-724575f1-72e6-4efc-ac73-cad221fda0c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749980064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3749980064
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3649062695
Short name T279
Test name
Test status
Simulation time 751695269 ps
CPU time 8.18 seconds
Started Jul 15 05:23:14 PM PDT 24
Finished Jul 15 05:23:22 PM PDT 24
Peak memory 217112 kb
Host smart-efad42ae-c81d-4385-8fdf-fdae28a161cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649062695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3649062695
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1290706614
Short name T173
Test name
Test status
Simulation time 18060998761 ps
CPU time 201.79 seconds
Started Jul 15 05:23:14 PM PDT 24
Finished Jul 15 05:26:36 PM PDT 24
Peak memory 232860 kb
Host smart-dd853af4-bfa9-4ae6-87f1-cd05be7655ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290706614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1290706614
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2243536112
Short name T185
Test name
Test status
Simulation time 12986476014 ps
CPU time 52.52 seconds
Started Jul 15 05:23:13 PM PDT 24
Finished Jul 15 05:24:06 PM PDT 24
Peak memory 219104 kb
Host smart-ffe99bd7-6a09-4d56-8017-450c23399cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243536112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2243536112
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3020741422
Short name T262
Test name
Test status
Simulation time 9291988065 ps
CPU time 30.61 seconds
Started Jul 15 05:23:16 PM PDT 24
Finished Jul 15 05:23:47 PM PDT 24
Peak memory 211956 kb
Host smart-06d16c7b-1a8c-4c35-b0ae-4bf4bb0ba4df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3020741422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3020741422
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.4136175022
Short name T165
Test name
Test status
Simulation time 13370245729 ps
CPU time 58.01 seconds
Started Jul 15 05:23:07 PM PDT 24
Finished Jul 15 05:24:05 PM PDT 24
Peak memory 216792 kb
Host smart-56046d91-9d6a-45d7-ad38-9a26b3ee8cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136175022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.4136175022
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3992937670
Short name T100
Test name
Test status
Simulation time 58395537057 ps
CPU time 1178.45 seconds
Started Jul 15 05:23:13 PM PDT 24
Finished Jul 15 05:42:52 PM PDT 24
Peak memory 232996 kb
Host smart-ab5820c5-cd22-45c0-ad54-272e0aa7a9e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992937670 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3992937670
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2592282172
Short name T101
Test name
Test status
Simulation time 169269052 ps
CPU time 8.35 seconds
Started Jul 15 05:20:10 PM PDT 24
Finished Jul 15 05:20:19 PM PDT 24
Peak memory 217208 kb
Host smart-fb201b0b-1447-4b35-8d22-f249001fc704
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592282172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2592282172
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3146182171
Short name T41
Test name
Test status
Simulation time 30967638086 ps
CPU time 141.86 seconds
Started Jul 15 05:20:09 PM PDT 24
Finished Jul 15 05:22:32 PM PDT 24
Peak memory 229648 kb
Host smart-a361d02b-90c7-451d-9bef-ba0ec8d04b69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146182171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3146182171
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2495820630
Short name T311
Test name
Test status
Simulation time 3119057872 ps
CPU time 40.17 seconds
Started Jul 15 05:20:09 PM PDT 24
Finished Jul 15 05:20:49 PM PDT 24
Peak memory 219312 kb
Host smart-bd324919-6d3a-4685-a478-1326f96da3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495820630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2495820630
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2622241191
Short name T145
Test name
Test status
Simulation time 2784831950 ps
CPU time 14.78 seconds
Started Jul 15 05:20:12 PM PDT 24
Finished Jul 15 05:20:27 PM PDT 24
Peak memory 218592 kb
Host smart-56f4cf10-e203-4ae3-9334-6d5fdc6c1ab0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2622241191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2622241191
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3407495186
Short name T76
Test name
Test status
Simulation time 1492441574 ps
CPU time 20.43 seconds
Started Jul 15 05:20:05 PM PDT 24
Finished Jul 15 05:20:26 PM PDT 24
Peak memory 216484 kb
Host smart-51d122d5-de06-4387-a83b-08a29bbef07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407495186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3407495186
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2922354879
Short name T252
Test name
Test status
Simulation time 6068847951 ps
CPU time 60.27 seconds
Started Jul 15 05:20:11 PM PDT 24
Finished Jul 15 05:21:12 PM PDT 24
Peak memory 216900 kb
Host smart-81276fd5-00a2-4b4e-ac5e-edf507a376d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922354879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2922354879
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1559540196
Short name T333
Test name
Test status
Simulation time 11868160068 ps
CPU time 25.35 seconds
Started Jul 15 05:23:20 PM PDT 24
Finished Jul 15 05:23:45 PM PDT 24
Peak memory 217484 kb
Host smart-bb8cb01d-90d5-46cb-bee9-845e6805350b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559540196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1559540196
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1074516741
Short name T322
Test name
Test status
Simulation time 91192861908 ps
CPU time 512.84 seconds
Started Jul 15 05:23:19 PM PDT 24
Finished Jul 15 05:31:53 PM PDT 24
Peak memory 225436 kb
Host smart-4398ac61-8dfa-438b-af21-25e9fd24b7bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074516741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1074516741
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1959711186
Short name T38
Test name
Test status
Simulation time 346238691 ps
CPU time 19.34 seconds
Started Jul 15 05:23:21 PM PDT 24
Finished Jul 15 05:23:40 PM PDT 24
Peak memory 219296 kb
Host smart-9bc169b7-7114-4b75-8f13-58ca5bdca982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959711186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1959711186
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3961416805
Short name T234
Test name
Test status
Simulation time 187066437 ps
CPU time 10.93 seconds
Started Jul 15 05:23:13 PM PDT 24
Finished Jul 15 05:23:24 PM PDT 24
Peak memory 219280 kb
Host smart-7d1d6a80-7808-48fe-98a9-82297f44bdf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3961416805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3961416805
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1135177106
Short name T353
Test name
Test status
Simulation time 3460165306 ps
CPU time 44.71 seconds
Started Jul 15 05:23:14 PM PDT 24
Finished Jul 15 05:23:59 PM PDT 24
Peak memory 215148 kb
Host smart-62ce2be8-bc7d-4b07-9c59-ec6350fc869c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135177106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1135177106
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3918769681
Short name T96
Test name
Test status
Simulation time 2333529714 ps
CPU time 49.96 seconds
Started Jul 15 05:23:15 PM PDT 24
Finished Jul 15 05:24:06 PM PDT 24
Peak memory 219288 kb
Host smart-882b5070-2c8a-4a89-82b1-87cacf2f73eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918769681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3918769681
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2284672469
Short name T298
Test name
Test status
Simulation time 3487683851 ps
CPU time 30.05 seconds
Started Jul 15 05:23:30 PM PDT 24
Finished Jul 15 05:24:00 PM PDT 24
Peak memory 217228 kb
Host smart-9ceab3e0-42cc-418a-a2fe-8cb62e934418
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284672469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2284672469
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3660201823
Short name T152
Test name
Test status
Simulation time 466039384737 ps
CPU time 1126.47 seconds
Started Jul 15 05:23:20 PM PDT 24
Finished Jul 15 05:42:07 PM PDT 24
Peak memory 216668 kb
Host smart-68f551a7-b677-4c4b-92e8-8da663ff45f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660201823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3660201823
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2125779345
Short name T223
Test name
Test status
Simulation time 28590567581 ps
CPU time 60.34 seconds
Started Jul 15 05:23:32 PM PDT 24
Finished Jul 15 05:24:33 PM PDT 24
Peak memory 219380 kb
Host smart-58cc1088-b4b2-4b55-9538-c1dadccc9ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125779345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2125779345
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3070481676
Short name T220
Test name
Test status
Simulation time 2899467690 ps
CPU time 27.13 seconds
Started Jul 15 05:23:22 PM PDT 24
Finished Jul 15 05:23:49 PM PDT 24
Peak memory 219256 kb
Host smart-ec82eda6-3efa-44d6-b2d5-d3a624aa660e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3070481676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3070481676
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3249309834
Short name T294
Test name
Test status
Simulation time 33963182446 ps
CPU time 87.11 seconds
Started Jul 15 05:23:22 PM PDT 24
Finished Jul 15 05:24:50 PM PDT 24
Peak memory 216308 kb
Host smart-5be75a6a-e0ef-416e-8819-f5bf6cfddb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249309834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3249309834
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1301549299
Short name T11
Test name
Test status
Simulation time 3991657803 ps
CPU time 51.61 seconds
Started Jul 15 05:23:19 PM PDT 24
Finished Jul 15 05:24:11 PM PDT 24
Peak memory 219284 kb
Host smart-aad65d37-899c-42ae-b88d-9fa83ce5fed6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301549299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1301549299
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2952814702
Short name T359
Test name
Test status
Simulation time 13316853132 ps
CPU time 27.65 seconds
Started Jul 15 05:23:35 PM PDT 24
Finished Jul 15 05:24:04 PM PDT 24
Peak memory 217468 kb
Host smart-8d0c7353-e378-40da-af81-7509216efdc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952814702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2952814702
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2468671220
Short name T315
Test name
Test status
Simulation time 26589487038 ps
CPU time 352.63 seconds
Started Jul 15 05:23:35 PM PDT 24
Finished Jul 15 05:29:28 PM PDT 24
Peak memory 228532 kb
Host smart-f15d990d-9ce3-4642-ae3c-458c89ed1518
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468671220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2468671220
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1387608374
Short name T308
Test name
Test status
Simulation time 4796347428 ps
CPU time 35.6 seconds
Started Jul 15 05:23:36 PM PDT 24
Finished Jul 15 05:24:13 PM PDT 24
Peak memory 219228 kb
Host smart-4892f843-edb2-453e-9ec1-f6b252b9acbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387608374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1387608374
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1870206284
Short name T14
Test name
Test status
Simulation time 11713564251 ps
CPU time 26.21 seconds
Started Jul 15 05:23:36 PM PDT 24
Finished Jul 15 05:24:03 PM PDT 24
Peak memory 217696 kb
Host smart-85f51253-9f85-4ea7-ab20-cf861598e2a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1870206284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1870206284
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1196214187
Short name T295
Test name
Test status
Simulation time 1662554112 ps
CPU time 31.66 seconds
Started Jul 15 05:23:37 PM PDT 24
Finished Jul 15 05:24:10 PM PDT 24
Peak memory 216948 kb
Host smart-2410346c-fe27-49f5-96fe-6b83bc4db13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196214187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1196214187
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3358328665
Short name T213
Test name
Test status
Simulation time 136899410111 ps
CPU time 95.01 seconds
Started Jul 15 05:23:35 PM PDT 24
Finished Jul 15 05:25:11 PM PDT 24
Peak memory 219336 kb
Host smart-03bb54eb-f812-4410-b410-983b3654171a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358328665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3358328665
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3418157004
Short name T282
Test name
Test status
Simulation time 413901737 ps
CPU time 11.39 seconds
Started Jul 15 05:23:36 PM PDT 24
Finished Jul 15 05:23:49 PM PDT 24
Peak memory 217124 kb
Host smart-c7d3d135-32d1-4205-96d3-d7364fb92fc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418157004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3418157004
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.258558033
Short name T187
Test name
Test status
Simulation time 8524485745 ps
CPU time 165.86 seconds
Started Jul 15 05:23:36 PM PDT 24
Finished Jul 15 05:26:24 PM PDT 24
Peak memory 240868 kb
Host smart-42dbc4e3-f260-4360-b0bb-3d874b97db1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258558033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.258558033
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1949768506
Short name T314
Test name
Test status
Simulation time 12094858099 ps
CPU time 31.08 seconds
Started Jul 15 05:23:36 PM PDT 24
Finished Jul 15 05:24:09 PM PDT 24
Peak memory 219280 kb
Host smart-7406f732-ecbe-4643-8f22-c2c569c5d594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949768506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1949768506
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2726654750
Short name T161
Test name
Test status
Simulation time 4017289873 ps
CPU time 32.31 seconds
Started Jul 15 05:23:35 PM PDT 24
Finished Jul 15 05:24:08 PM PDT 24
Peak memory 219256 kb
Host smart-3c38cb61-24be-4845-be87-2ef016ad76e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2726654750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2726654750
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.402520980
Short name T245
Test name
Test status
Simulation time 4668215673 ps
CPU time 50.64 seconds
Started Jul 15 05:23:37 PM PDT 24
Finished Jul 15 05:24:29 PM PDT 24
Peak memory 216392 kb
Host smart-7269dc17-74e3-476f-9c86-d1c335f58abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402520980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.402520980
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2700830798
Short name T191
Test name
Test status
Simulation time 23448960493 ps
CPU time 89.03 seconds
Started Jul 15 05:23:34 PM PDT 24
Finished Jul 15 05:25:04 PM PDT 24
Peak memory 219352 kb
Host smart-24263404-054a-4c13-bfc5-b9d30d6358e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700830798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2700830798
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2725462376
Short name T149
Test name
Test status
Simulation time 339137886 ps
CPU time 8.35 seconds
Started Jul 15 05:23:46 PM PDT 24
Finished Jul 15 05:23:55 PM PDT 24
Peak memory 213212 kb
Host smart-556c7210-bacd-4348-bb26-cf1645855985
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725462376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2725462376
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3374431968
Short name T129
Test name
Test status
Simulation time 10177423468 ps
CPU time 223.01 seconds
Started Jul 15 05:23:44 PM PDT 24
Finished Jul 15 05:27:28 PM PDT 24
Peak memory 236900 kb
Host smart-e75972ac-de9a-4fd8-8c11-a84a21892acc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374431968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3374431968
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.478352840
Short name T188
Test name
Test status
Simulation time 16405575392 ps
CPU time 45.9 seconds
Started Jul 15 05:23:43 PM PDT 24
Finished Jul 15 05:24:30 PM PDT 24
Peak memory 219332 kb
Host smart-86ea64cb-bbf6-4fd1-852e-c54ea3c3a422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478352840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.478352840
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.386356810
Short name T289
Test name
Test status
Simulation time 8384449983 ps
CPU time 33.43 seconds
Started Jul 15 05:23:37 PM PDT 24
Finished Jul 15 05:24:12 PM PDT 24
Peak memory 219264 kb
Host smart-2dddc4d7-3080-4cf1-8205-3164b55d728f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=386356810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.386356810
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1978426776
Short name T99
Test name
Test status
Simulation time 351484740 ps
CPU time 20.55 seconds
Started Jul 15 05:23:35 PM PDT 24
Finished Jul 15 05:23:56 PM PDT 24
Peak memory 216032 kb
Host smart-13cf7d71-9a74-4094-b874-2b1cdeb0a569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978426776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1978426776
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.224252113
Short name T323
Test name
Test status
Simulation time 37169393039 ps
CPU time 63.5 seconds
Started Jul 15 05:23:35 PM PDT 24
Finished Jul 15 05:24:40 PM PDT 24
Peak memory 219316 kb
Host smart-77eafef5-9464-4007-9ee1-9b734269a3ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224252113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.224252113
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.1962251017
Short name T44
Test name
Test status
Simulation time 275158167884 ps
CPU time 2365.74 seconds
Started Jul 15 05:23:46 PM PDT 24
Finished Jul 15 06:03:12 PM PDT 24
Peak memory 243952 kb
Host smart-f8555da5-c5f9-4eb9-beae-ef4c86a60d7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962251017 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.1962251017
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3665279128
Short name T281
Test name
Test status
Simulation time 2961043304 ps
CPU time 13.56 seconds
Started Jul 15 05:23:44 PM PDT 24
Finished Jul 15 05:23:58 PM PDT 24
Peak memory 217028 kb
Host smart-64407cae-1438-4fea-8aab-3d1d9990b8a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665279128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3665279128
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1246556789
Short name T285
Test name
Test status
Simulation time 31837715290 ps
CPU time 424.28 seconds
Started Jul 15 05:23:44 PM PDT 24
Finished Jul 15 05:30:49 PM PDT 24
Peak memory 217076 kb
Host smart-d5d2f69c-827e-4e12-a6d5-db6357f161b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246556789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1246556789
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.402800529
Short name T236
Test name
Test status
Simulation time 1645340427 ps
CPU time 31.87 seconds
Started Jul 15 05:23:44 PM PDT 24
Finished Jul 15 05:24:17 PM PDT 24
Peak memory 219264 kb
Host smart-c74454f5-687e-4eb3-9a24-f8570fcee974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402800529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.402800529
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1630824401
Short name T138
Test name
Test status
Simulation time 3684089298 ps
CPU time 32.33 seconds
Started Jul 15 05:23:46 PM PDT 24
Finished Jul 15 05:24:19 PM PDT 24
Peak memory 211692 kb
Host smart-c35ee6ef-1a42-4352-95ff-2827b1f96f07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1630824401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1630824401
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1878951466
Short name T259
Test name
Test status
Simulation time 59004242894 ps
CPU time 79.6 seconds
Started Jul 15 05:23:46 PM PDT 24
Finished Jul 15 05:25:07 PM PDT 24
Peak memory 216756 kb
Host smart-0ec7bac7-44ae-416b-b46f-7871e7bd33bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878951466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1878951466
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.49749169
Short name T275
Test name
Test status
Simulation time 9954186050 ps
CPU time 83.02 seconds
Started Jul 15 05:23:44 PM PDT 24
Finished Jul 15 05:25:08 PM PDT 24
Peak memory 220584 kb
Host smart-dbc34307-2c1c-4ee8-a5c7-3589ebd00d7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49749169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 35.rom_ctrl_stress_all.49749169
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3663461593
Short name T221
Test name
Test status
Simulation time 814771952 ps
CPU time 13.91 seconds
Started Jul 15 05:23:52 PM PDT 24
Finished Jul 15 05:24:06 PM PDT 24
Peak memory 217108 kb
Host smart-0fe1d16b-78bb-4fd2-84c5-f041e05ff247
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663461593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3663461593
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.736075165
Short name T319
Test name
Test status
Simulation time 188885499758 ps
CPU time 606.44 seconds
Started Jul 15 05:23:51 PM PDT 24
Finished Jul 15 05:33:58 PM PDT 24
Peak memory 241928 kb
Host smart-5536f0d7-dcb4-4282-aa54-5d828b6334cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736075165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.736075165
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2009826508
Short name T349
Test name
Test status
Simulation time 6537239788 ps
CPU time 59.36 seconds
Started Jul 15 05:23:50 PM PDT 24
Finished Jul 15 05:24:50 PM PDT 24
Peak memory 219356 kb
Host smart-cb50957f-313a-4511-b3b5-34087f9a2683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009826508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2009826508
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2861546400
Short name T212
Test name
Test status
Simulation time 699085000 ps
CPU time 10.3 seconds
Started Jul 15 05:23:46 PM PDT 24
Finished Jul 15 05:23:57 PM PDT 24
Peak memory 219224 kb
Host smart-08383484-fdd0-420f-a1b5-bcdb445995dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2861546400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2861546400
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2932549778
Short name T340
Test name
Test status
Simulation time 2583548135 ps
CPU time 28.69 seconds
Started Jul 15 05:23:44 PM PDT 24
Finished Jul 15 05:24:13 PM PDT 24
Peak memory 215892 kb
Host smart-c47eef67-79a1-40e9-bc78-06718376356c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932549778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2932549778
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1338669870
Short name T151
Test name
Test status
Simulation time 2923268474 ps
CPU time 27.91 seconds
Started Jul 15 05:23:43 PM PDT 24
Finished Jul 15 05:24:12 PM PDT 24
Peak memory 214536 kb
Host smart-09488fd6-8c38-4b4d-99fc-e991c1c5ce66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338669870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1338669870
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2225972206
Short name T331
Test name
Test status
Simulation time 4283786710 ps
CPU time 33.93 seconds
Started Jul 15 05:23:49 PM PDT 24
Finished Jul 15 05:24:24 PM PDT 24
Peak memory 217220 kb
Host smart-d5cff04f-553f-42d3-9bc6-3e29832e7adf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225972206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2225972206
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.884639373
Short name T247
Test name
Test status
Simulation time 4880378310 ps
CPU time 172.22 seconds
Started Jul 15 05:23:50 PM PDT 24
Finished Jul 15 05:26:42 PM PDT 24
Peak memory 237816 kb
Host smart-a7ceeb26-c6bb-4983-ab74-c5e024dd5d81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884639373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.884639373
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.20528738
Short name T321
Test name
Test status
Simulation time 1500881115 ps
CPU time 19.44 seconds
Started Jul 15 05:23:51 PM PDT 24
Finished Jul 15 05:24:11 PM PDT 24
Peak memory 219316 kb
Host smart-f7e74e5d-e387-43f6-a717-b48c720354a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20528738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.20528738
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.946766702
Short name T312
Test name
Test status
Simulation time 272426984 ps
CPU time 12.22 seconds
Started Jul 15 05:23:50 PM PDT 24
Finished Jul 15 05:24:03 PM PDT 24
Peak memory 219244 kb
Host smart-72bae6e4-42c6-42cd-a102-fb9e6c3453b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=946766702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.946766702
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1379825931
Short name T93
Test name
Test status
Simulation time 17993661464 ps
CPU time 71.8 seconds
Started Jul 15 05:23:50 PM PDT 24
Finished Jul 15 05:25:02 PM PDT 24
Peak memory 217480 kb
Host smart-09d90879-4a51-490f-9596-55796d8dd0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379825931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1379825931
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3394216675
Short name T336
Test name
Test status
Simulation time 2270844661 ps
CPU time 31.27 seconds
Started Jul 15 05:23:49 PM PDT 24
Finished Jul 15 05:24:21 PM PDT 24
Peak memory 219340 kb
Host smart-4a90257c-88aa-41cd-ae95-c6815e8cc5c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394216675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3394216675
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1100512441
Short name T48
Test name
Test status
Simulation time 26649252348 ps
CPU time 1025.54 seconds
Started Jul 15 05:23:50 PM PDT 24
Finished Jul 15 05:40:56 PM PDT 24
Peak memory 230948 kb
Host smart-aac21049-eb74-49db-9e17-8f71a1b97ed7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100512441 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.1100512441
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.378952711
Short name T154
Test name
Test status
Simulation time 2225228144 ps
CPU time 21.19 seconds
Started Jul 15 05:23:59 PM PDT 24
Finished Jul 15 05:24:21 PM PDT 24
Peak memory 217284 kb
Host smart-97a0ac29-12cc-43f7-ba82-826993cb7d10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378952711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.378952711
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2421469274
Short name T325
Test name
Test status
Simulation time 72865665041 ps
CPU time 317.7 seconds
Started Jul 15 05:23:59 PM PDT 24
Finished Jul 15 05:29:18 PM PDT 24
Peak memory 232728 kb
Host smart-f91bcff1-f864-4e27-bf2b-2019ad3d881e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421469274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2421469274
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.652708439
Short name T357
Test name
Test status
Simulation time 3508224354 ps
CPU time 10.74 seconds
Started Jul 15 05:23:58 PM PDT 24
Finished Jul 15 05:24:10 PM PDT 24
Peak memory 219336 kb
Host smart-37425ed6-2084-4d95-82f3-83208743333f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=652708439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.652708439
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.737499171
Short name T346
Test name
Test status
Simulation time 1904254603 ps
CPU time 31.83 seconds
Started Jul 15 05:23:58 PM PDT 24
Finished Jul 15 05:24:31 PM PDT 24
Peak memory 216052 kb
Host smart-15802e07-cb0d-4044-a967-0d73d7e4a63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737499171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.737499171
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.202159728
Short name T316
Test name
Test status
Simulation time 1324856524 ps
CPU time 34.3 seconds
Started Jul 15 05:23:59 PM PDT 24
Finished Jul 15 05:24:35 PM PDT 24
Peak memory 219228 kb
Host smart-ed067508-856e-425e-b569-8d081ed6e58c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202159728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.202159728
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2760407971
Short name T182
Test name
Test status
Simulation time 1220145110 ps
CPU time 10.85 seconds
Started Jul 15 05:24:06 PM PDT 24
Finished Jul 15 05:24:18 PM PDT 24
Peak memory 217032 kb
Host smart-97e2f3c4-b2d5-4ed7-8ef9-c0933bd7434b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760407971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2760407971
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.4188596413
Short name T303
Test name
Test status
Simulation time 2997447296 ps
CPU time 19.45 seconds
Started Jul 15 05:24:06 PM PDT 24
Finished Jul 15 05:24:27 PM PDT 24
Peak memory 219280 kb
Host smart-fa46a73b-ed3c-4565-a3b9-17bba492911e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188596413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.4188596413
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2184892627
Short name T264
Test name
Test status
Simulation time 23398719195 ps
CPU time 31.56 seconds
Started Jul 15 05:24:00 PM PDT 24
Finished Jul 15 05:24:32 PM PDT 24
Peak memory 211932 kb
Host smart-d97192ef-e87e-4270-8311-0ad8fc50f26c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2184892627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2184892627
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.840793773
Short name T192
Test name
Test status
Simulation time 15107709385 ps
CPU time 50.82 seconds
Started Jul 15 05:24:00 PM PDT 24
Finished Jul 15 05:24:51 PM PDT 24
Peak memory 217108 kb
Host smart-376ea82f-06c2-47da-8eed-ae23c487170c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840793773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.840793773
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2414702300
Short name T235
Test name
Test status
Simulation time 9497449763 ps
CPU time 95.95 seconds
Started Jul 15 05:23:59 PM PDT 24
Finished Jul 15 05:25:36 PM PDT 24
Peak memory 219324 kb
Host smart-aa361c82-00ca-4826-8a40-4aa620886bb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414702300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2414702300
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2475358470
Short name T222
Test name
Test status
Simulation time 10293476564 ps
CPU time 25.94 seconds
Started Jul 15 05:20:24 PM PDT 24
Finished Jul 15 05:20:50 PM PDT 24
Peak memory 217448 kb
Host smart-d35137d9-c103-45bc-825b-dadad1734e16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475358470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2475358470
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2369485266
Short name T350
Test name
Test status
Simulation time 8732975212 ps
CPU time 67.02 seconds
Started Jul 15 05:20:16 PM PDT 24
Finished Jul 15 05:21:23 PM PDT 24
Peak memory 219308 kb
Host smart-9e4f3f3a-983d-49de-8d4d-8fcf6152b45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369485266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2369485266
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.194430118
Short name T335
Test name
Test status
Simulation time 8615072972 ps
CPU time 22.65 seconds
Started Jul 15 05:20:16 PM PDT 24
Finished Jul 15 05:20:40 PM PDT 24
Peak memory 211676 kb
Host smart-d28484f9-292c-47ed-a179-23de8d20d958
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=194430118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.194430118
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2320667163
Short name T22
Test name
Test status
Simulation time 14199867108 ps
CPU time 244.49 seconds
Started Jul 15 05:20:23 PM PDT 24
Finished Jul 15 05:24:28 PM PDT 24
Peak memory 237944 kb
Host smart-f05ead6d-7ff5-4e6f-9c06-f13ed603bc6a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320667163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2320667163
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1683068473
Short name T177
Test name
Test status
Simulation time 349490128 ps
CPU time 20.08 seconds
Started Jul 15 05:20:10 PM PDT 24
Finished Jul 15 05:20:31 PM PDT 24
Peak memory 216552 kb
Host smart-d0885c26-62d6-40a7-a397-4578327f25a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683068473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1683068473
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1010653868
Short name T260
Test name
Test status
Simulation time 9262011780 ps
CPU time 91.5 seconds
Started Jul 15 05:20:11 PM PDT 24
Finished Jul 15 05:21:43 PM PDT 24
Peak memory 219412 kb
Host smart-2879eae8-bbf2-4121-a247-58ca59797996
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010653868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1010653868
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3995232372
Short name T196
Test name
Test status
Simulation time 339192552 ps
CPU time 8.44 seconds
Started Jul 15 05:24:15 PM PDT 24
Finished Jul 15 05:24:25 PM PDT 24
Peak memory 216612 kb
Host smart-25f56da7-7b09-47b4-84ab-6be5505d0e72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995232372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3995232372
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1481867556
Short name T330
Test name
Test status
Simulation time 56951753057 ps
CPU time 598.2 seconds
Started Jul 15 05:24:06 PM PDT 24
Finished Jul 15 05:34:05 PM PDT 24
Peak memory 237840 kb
Host smart-d7a3b480-462e-432a-ba63-2b827abcb1fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481867556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1481867556
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.4058158676
Short name T147
Test name
Test status
Simulation time 5493014410 ps
CPU time 28.79 seconds
Started Jul 15 05:24:15 PM PDT 24
Finished Jul 15 05:24:44 PM PDT 24
Peak memory 218796 kb
Host smart-4c6cfc65-d7c3-497a-9e32-a96b805954ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058158676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.4058158676
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2887134088
Short name T320
Test name
Test status
Simulation time 186117610 ps
CPU time 10.42 seconds
Started Jul 15 05:24:06 PM PDT 24
Finished Jul 15 05:24:18 PM PDT 24
Peak memory 219252 kb
Host smart-2f296d94-b857-4862-996e-3b22611fa2ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2887134088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2887134088
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1098597832
Short name T342
Test name
Test status
Simulation time 684941987 ps
CPU time 25.63 seconds
Started Jul 15 05:24:06 PM PDT 24
Finished Jul 15 05:24:33 PM PDT 24
Peak memory 215972 kb
Host smart-09fdc3a1-0a64-4984-a40c-c8bc49aecf4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098597832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1098597832
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2069820721
Short name T75
Test name
Test status
Simulation time 22676679145 ps
CPU time 111.97 seconds
Started Jul 15 05:24:07 PM PDT 24
Finished Jul 15 05:26:00 PM PDT 24
Peak memory 219312 kb
Host smart-0b88e95f-f6fa-4c47-bb44-4b2e676960e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069820721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2069820721
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2564935239
Short name T62
Test name
Test status
Simulation time 10947033778 ps
CPU time 24.98 seconds
Started Jul 15 05:24:22 PM PDT 24
Finished Jul 15 05:24:47 PM PDT 24
Peak memory 217392 kb
Host smart-dbcd9453-6065-4665-ae36-e610a388ea74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564935239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2564935239
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1819402173
Short name T269
Test name
Test status
Simulation time 2103172195 ps
CPU time 172.66 seconds
Started Jul 15 05:24:14 PM PDT 24
Finished Jul 15 05:27:08 PM PDT 24
Peak memory 237652 kb
Host smart-3458c48c-c516-4bb1-bdf5-c37177157a78
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819402173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1819402173
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2421182679
Short name T206
Test name
Test status
Simulation time 5476180834 ps
CPU time 50.84 seconds
Started Jul 15 05:24:21 PM PDT 24
Finished Jul 15 05:25:12 PM PDT 24
Peak memory 219320 kb
Host smart-18bc540f-dea8-468f-99c4-a89446c10512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421182679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2421182679
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1093786279
Short name T98
Test name
Test status
Simulation time 369184803 ps
CPU time 10.65 seconds
Started Jul 15 05:24:15 PM PDT 24
Finished Jul 15 05:24:27 PM PDT 24
Peak memory 219220 kb
Host smart-82562a92-71d0-46cc-a027-6d70f1ed03b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1093786279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1093786279
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.225651297
Short name T301
Test name
Test status
Simulation time 14145295830 ps
CPU time 86.23 seconds
Started Jul 15 05:24:14 PM PDT 24
Finished Jul 15 05:25:41 PM PDT 24
Peak memory 219936 kb
Host smart-37f10963-bbf2-42c4-a4a3-0ed8607cd0b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225651297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.225651297
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3335904505
Short name T341
Test name
Test status
Simulation time 4590639923 ps
CPU time 16.62 seconds
Started Jul 15 05:24:29 PM PDT 24
Finished Jul 15 05:24:46 PM PDT 24
Peak memory 217488 kb
Host smart-edd7556d-3898-415e-bc1c-4db502f20bb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335904505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3335904505
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3455119131
Short name T329
Test name
Test status
Simulation time 12318807257 ps
CPU time 250.5 seconds
Started Jul 15 05:24:23 PM PDT 24
Finished Jul 15 05:28:34 PM PDT 24
Peak memory 235860 kb
Host smart-e3e1250a-576c-404e-bd24-c0298041f160
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455119131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3455119131
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3619167566
Short name T166
Test name
Test status
Simulation time 4340300443 ps
CPU time 32.2 seconds
Started Jul 15 05:24:23 PM PDT 24
Finished Jul 15 05:24:56 PM PDT 24
Peak memory 219320 kb
Host smart-4839dda8-79df-4b79-ada9-ed56e659f006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619167566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3619167566
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1426800896
Short name T226
Test name
Test status
Simulation time 4004232697 ps
CPU time 32.11 seconds
Started Jul 15 05:24:21 PM PDT 24
Finished Jul 15 05:24:53 PM PDT 24
Peak memory 211332 kb
Host smart-22a4d6b7-67cb-45bd-87f7-f070dcf46ed1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1426800896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1426800896
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3614232923
Short name T127
Test name
Test status
Simulation time 7686254567 ps
CPU time 62.78 seconds
Started Jul 15 05:24:22 PM PDT 24
Finished Jul 15 05:25:26 PM PDT 24
Peak memory 217468 kb
Host smart-8a79e303-f8e4-4388-b71e-87a57007148b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614232923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3614232923
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.517076017
Short name T132
Test name
Test status
Simulation time 5975294899 ps
CPU time 20.02 seconds
Started Jul 15 05:24:23 PM PDT 24
Finished Jul 15 05:24:44 PM PDT 24
Peak memory 219344 kb
Host smart-2327c9de-31e7-4961-a5ac-cec4965bd6a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517076017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.517076017
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2227735487
Short name T214
Test name
Test status
Simulation time 21191347487 ps
CPU time 24.2 seconds
Started Jul 15 05:24:38 PM PDT 24
Finished Jul 15 05:25:02 PM PDT 24
Peak memory 217368 kb
Host smart-1fa6be72-44e4-4cb9-abc8-c0e4af5a3df4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227735487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2227735487
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3688049125
Short name T19
Test name
Test status
Simulation time 46514485907 ps
CPU time 484.44 seconds
Started Jul 15 05:24:31 PM PDT 24
Finished Jul 15 05:32:36 PM PDT 24
Peak memory 219564 kb
Host smart-c4d254cd-96e0-4c46-88fc-1f3cee386b8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688049125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3688049125
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2376266382
Short name T168
Test name
Test status
Simulation time 17030960509 ps
CPU time 52.54 seconds
Started Jul 15 05:24:36 PM PDT 24
Finished Jul 15 05:25:29 PM PDT 24
Peak memory 219376 kb
Host smart-8ee10363-33e3-4e6b-896a-d921ed7a2fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376266382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2376266382
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3878409720
Short name T107
Test name
Test status
Simulation time 3529137531 ps
CPU time 31.52 seconds
Started Jul 15 05:24:29 PM PDT 24
Finished Jul 15 05:25:01 PM PDT 24
Peak memory 219284 kb
Host smart-b48c9eff-b582-4186-b373-406d0151e018
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3878409720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3878409720
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3253249564
Short name T186
Test name
Test status
Simulation time 17438079207 ps
CPU time 75.17 seconds
Started Jul 15 05:24:31 PM PDT 24
Finished Jul 15 05:25:47 PM PDT 24
Peak memory 217508 kb
Host smart-c414674c-cdd2-4ed6-abca-173c742617a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253249564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3253249564
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.4221495433
Short name T266
Test name
Test status
Simulation time 6895727908 ps
CPU time 46.9 seconds
Started Jul 15 05:24:28 PM PDT 24
Finished Jul 15 05:25:15 PM PDT 24
Peak memory 218028 kb
Host smart-6dac53f2-2e51-4c1b-8f3d-697388db38f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221495433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.4221495433
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.1832501268
Short name T13
Test name
Test status
Simulation time 112253414126 ps
CPU time 6754.94 seconds
Started Jul 15 05:24:36 PM PDT 24
Finished Jul 15 07:17:12 PM PDT 24
Peak memory 236752 kb
Host smart-c8740ea4-f8fa-42bf-bb16-53e31c604623
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832501268 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.1832501268
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3954884923
Short name T25
Test name
Test status
Simulation time 1250738085 ps
CPU time 15.9 seconds
Started Jul 15 05:24:36 PM PDT 24
Finished Jul 15 05:24:52 PM PDT 24
Peak memory 217108 kb
Host smart-81056818-25b2-4fc8-83ce-1c68d18661dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954884923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3954884923
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.242351529
Short name T267
Test name
Test status
Simulation time 247002702124 ps
CPU time 337.94 seconds
Started Jul 15 05:24:36 PM PDT 24
Finished Jul 15 05:30:14 PM PDT 24
Peak memory 235096 kb
Host smart-0b535007-704f-4893-a78b-a4ca2f08f7c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242351529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.242351529
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3768943150
Short name T198
Test name
Test status
Simulation time 7461200752 ps
CPU time 44.1 seconds
Started Jul 15 05:24:37 PM PDT 24
Finished Jul 15 05:25:21 PM PDT 24
Peak memory 219252 kb
Host smart-06001ae8-4c2d-4f64-a161-d16831322845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768943150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3768943150
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3930168083
Short name T139
Test name
Test status
Simulation time 1410873037 ps
CPU time 19.35 seconds
Started Jul 15 05:24:36 PM PDT 24
Finished Jul 15 05:24:56 PM PDT 24
Peak memory 216708 kb
Host smart-6c77aa54-84b5-4ebc-8cb8-263a6cfa444c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930168083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3930168083
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.175518253
Short name T123
Test name
Test status
Simulation time 1974680458 ps
CPU time 17.12 seconds
Started Jul 15 05:24:36 PM PDT 24
Finished Jul 15 05:24:54 PM PDT 24
Peak memory 219288 kb
Host smart-3b46108c-d7a4-42ce-ab90-389bd2e333d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175518253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.175518253
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.139888731
Short name T202
Test name
Test status
Simulation time 11152244620 ps
CPU time 24.26 seconds
Started Jul 15 05:24:42 PM PDT 24
Finished Jul 15 05:25:07 PM PDT 24
Peak memory 217528 kb
Host smart-8cbe7b94-ec35-484c-8a39-6a04eaf9845c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139888731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.139888731
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.904828398
Short name T8
Test name
Test status
Simulation time 30499028846 ps
CPU time 293.66 seconds
Started Jul 15 05:24:43 PM PDT 24
Finished Jul 15 05:29:37 PM PDT 24
Peak memory 242920 kb
Host smart-076ab937-aef8-4b97-be78-369e4cb42db4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904828398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.904828398
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2723099274
Short name T231
Test name
Test status
Simulation time 332773242 ps
CPU time 19.1 seconds
Started Jul 15 05:24:45 PM PDT 24
Finished Jul 15 05:25:04 PM PDT 24
Peak memory 219196 kb
Host smart-aeb974fd-d57f-41fd-b4ea-5a50ae251263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723099274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2723099274
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3418979551
Short name T271
Test name
Test status
Simulation time 11679872328 ps
CPU time 27.33 seconds
Started Jul 15 05:24:42 PM PDT 24
Finished Jul 15 05:25:10 PM PDT 24
Peak memory 219328 kb
Host smart-0479c650-f119-4ac7-a8fb-e4215f6b3109
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3418979551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3418979551
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1647928817
Short name T74
Test name
Test status
Simulation time 1000401846 ps
CPU time 28.22 seconds
Started Jul 15 05:24:35 PM PDT 24
Finished Jul 15 05:25:04 PM PDT 24
Peak memory 216596 kb
Host smart-68f99daf-9375-42a7-831b-543ac3fc0e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647928817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1647928817
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.4097382474
Short name T164
Test name
Test status
Simulation time 796086367 ps
CPU time 49.05 seconds
Started Jul 15 05:24:36 PM PDT 24
Finished Jul 15 05:25:26 PM PDT 24
Peak memory 219228 kb
Host smart-cbcd98b5-db93-4dca-a62e-7a05a74f119c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097382474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.4097382474
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.174330537
Short name T225
Test name
Test status
Simulation time 15763279530 ps
CPU time 21.61 seconds
Started Jul 15 05:24:47 PM PDT 24
Finished Jul 15 05:25:09 PM PDT 24
Peak memory 217504 kb
Host smart-6fad9e53-0212-4910-bb0e-e5268ace79af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174330537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.174330537
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.75558553
Short name T239
Test name
Test status
Simulation time 247712339462 ps
CPU time 606.48 seconds
Started Jul 15 05:24:45 PM PDT 24
Finished Jul 15 05:34:52 PM PDT 24
Peak memory 235940 kb
Host smart-06e47099-2a08-4d32-954e-46fe7bd0fd8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75558553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_co
rrupt_sig_fatal_chk.75558553
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.372820477
Short name T310
Test name
Test status
Simulation time 7723329185 ps
CPU time 42.52 seconds
Started Jul 15 05:24:43 PM PDT 24
Finished Jul 15 05:25:26 PM PDT 24
Peak memory 219320 kb
Host smart-755b14b6-8314-48c3-9c05-e022754315fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372820477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.372820477
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.4024002448
Short name T343
Test name
Test status
Simulation time 11244472774 ps
CPU time 22.7 seconds
Started Jul 15 05:24:42 PM PDT 24
Finished Jul 15 05:25:05 PM PDT 24
Peak memory 219336 kb
Host smart-09d266a2-2557-4d00-a890-bbffb2cb66c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4024002448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.4024002448
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.2346298843
Short name T277
Test name
Test status
Simulation time 12536622284 ps
CPU time 40.41 seconds
Started Jul 15 05:24:43 PM PDT 24
Finished Jul 15 05:25:23 PM PDT 24
Peak memory 216936 kb
Host smart-bdfb0cce-7b3d-4f3a-98cc-5bee3e95e9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346298843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2346298843
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2419632979
Short name T174
Test name
Test status
Simulation time 23902873643 ps
CPU time 82.84 seconds
Started Jul 15 05:24:44 PM PDT 24
Finished Jul 15 05:26:07 PM PDT 24
Peak memory 217756 kb
Host smart-660057b7-2f40-455a-9e68-8e053b598f30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419632979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2419632979
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2922910631
Short name T3
Test name
Test status
Simulation time 7761159851 ps
CPU time 24.89 seconds
Started Jul 15 05:24:50 PM PDT 24
Finished Jul 15 05:25:16 PM PDT 24
Peak memory 217400 kb
Host smart-e4d36970-4876-472c-a04b-b41fdb3ff28f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922910631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2922910631
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2819088819
Short name T332
Test name
Test status
Simulation time 107961041123 ps
CPU time 401.97 seconds
Started Jul 15 05:24:49 PM PDT 24
Finished Jul 15 05:31:32 PM PDT 24
Peak memory 232300 kb
Host smart-176bf42a-d62f-42b2-886b-013c3ea41121
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819088819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2819088819
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.765765763
Short name T356
Test name
Test status
Simulation time 1374890275 ps
CPU time 19.52 seconds
Started Jul 15 05:24:50 PM PDT 24
Finished Jul 15 05:25:10 PM PDT 24
Peak memory 219196 kb
Host smart-9a09bc7f-c84b-4ec3-b483-0f8db5c6fc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765765763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.765765763
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2308686027
Short name T360
Test name
Test status
Simulation time 8708915958 ps
CPU time 25.54 seconds
Started Jul 15 05:24:51 PM PDT 24
Finished Jul 15 05:25:17 PM PDT 24
Peak memory 219328 kb
Host smart-0eca91ff-d572-4c2a-9735-6a929d4015ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2308686027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2308686027
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1594552479
Short name T51
Test name
Test status
Simulation time 7075533485 ps
CPU time 62.89 seconds
Started Jul 15 05:24:44 PM PDT 24
Finished Jul 15 05:25:48 PM PDT 24
Peak memory 217256 kb
Host smart-b2a9d11d-6a8a-447e-a777-5532fb71c6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594552479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1594552479
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2971112460
Short name T52
Test name
Test status
Simulation time 12811201982 ps
CPU time 39.14 seconds
Started Jul 15 05:24:51 PM PDT 24
Finished Jul 15 05:25:30 PM PDT 24
Peak memory 219196 kb
Host smart-196aaa90-9834-4a8d-ac14-a919f7b39254
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971112460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2971112460
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.511206927
Short name T344
Test name
Test status
Simulation time 346299929 ps
CPU time 8.32 seconds
Started Jul 15 05:24:59 PM PDT 24
Finished Jul 15 05:25:07 PM PDT 24
Peak memory 216840 kb
Host smart-c6c4b84d-03c7-4b57-895b-ed41b9e166f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511206927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.511206927
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3764971448
Short name T158
Test name
Test status
Simulation time 15611644380 ps
CPU time 176.7 seconds
Started Jul 15 05:24:50 PM PDT 24
Finished Jul 15 05:27:47 PM PDT 24
Peak memory 234348 kb
Host smart-4f2a7089-84c0-4c62-adf0-72fb36e69eb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764971448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3764971448
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3268719341
Short name T207
Test name
Test status
Simulation time 6087140685 ps
CPU time 55.34 seconds
Started Jul 15 05:24:50 PM PDT 24
Finished Jul 15 05:25:45 PM PDT 24
Peak memory 219280 kb
Host smart-abb0cf6c-c4ae-482f-93ee-5d9e4190ed0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268719341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3268719341
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2157763825
Short name T256
Test name
Test status
Simulation time 13353872311 ps
CPU time 30.96 seconds
Started Jul 15 05:24:51 PM PDT 24
Finished Jul 15 05:25:22 PM PDT 24
Peak memory 211992 kb
Host smart-c6c3093c-b76f-4b0b-8425-d1d9fee40c98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2157763825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2157763825
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2831972430
Short name T242
Test name
Test status
Simulation time 2707185895 ps
CPU time 30.67 seconds
Started Jul 15 05:24:49 PM PDT 24
Finished Jul 15 05:25:20 PM PDT 24
Peak memory 216044 kb
Host smart-dc89e80a-f479-4602-8697-bcaca35af414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831972430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2831972430
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1349847065
Short name T169
Test name
Test status
Simulation time 5763143337 ps
CPU time 83.54 seconds
Started Jul 15 05:24:53 PM PDT 24
Finished Jul 15 05:26:17 PM PDT 24
Peak memory 220196 kb
Host smart-c6212a07-d406-4af1-9e01-49ddef79b687
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349847065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1349847065
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3599642810
Short name T324
Test name
Test status
Simulation time 13733168655 ps
CPU time 30.34 seconds
Started Jul 15 05:24:58 PM PDT 24
Finished Jul 15 05:25:28 PM PDT 24
Peak memory 217220 kb
Host smart-0de34b7e-8047-47db-a196-da8397e4a970
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599642810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3599642810
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3247227101
Short name T33
Test name
Test status
Simulation time 29163337782 ps
CPU time 356.05 seconds
Started Jul 15 05:24:57 PM PDT 24
Finished Jul 15 05:30:53 PM PDT 24
Peak memory 233340 kb
Host smart-36005a25-e5e7-4c19-8c3e-99182fa3febc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247227101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3247227101
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1958050685
Short name T27
Test name
Test status
Simulation time 13900241086 ps
CPU time 32.3 seconds
Started Jul 15 05:24:59 PM PDT 24
Finished Jul 15 05:25:31 PM PDT 24
Peak memory 219256 kb
Host smart-004a9f39-d58e-4365-a713-4499c9058e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958050685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1958050685
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2990085756
Short name T211
Test name
Test status
Simulation time 844096489 ps
CPU time 15.73 seconds
Started Jul 15 05:24:57 PM PDT 24
Finished Jul 15 05:25:14 PM PDT 24
Peak memory 219276 kb
Host smart-bfa6428c-8551-4f90-accd-cbff4a3e54b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2990085756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2990085756
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.4081613418
Short name T18
Test name
Test status
Simulation time 659260425 ps
CPU time 20.13 seconds
Started Jul 15 05:24:57 PM PDT 24
Finished Jul 15 05:25:18 PM PDT 24
Peak memory 216428 kb
Host smart-9ac83e39-9fd7-47ac-9e5d-2e7596c7cb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081613418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.4081613418
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.476730986
Short name T157
Test name
Test status
Simulation time 11966725332 ps
CPU time 101.27 seconds
Started Jul 15 05:24:58 PM PDT 24
Finished Jul 15 05:26:40 PM PDT 24
Peak memory 230460 kb
Host smart-ec98fbb6-eba5-4bf6-972e-dfe79ac2d528
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476730986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.476730986
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1675371661
Short name T63
Test name
Test status
Simulation time 9037215885 ps
CPU time 25.91 seconds
Started Jul 15 05:20:30 PM PDT 24
Finished Jul 15 05:20:57 PM PDT 24
Peak memory 217532 kb
Host smart-017562cb-4dc1-4b24-a20a-12dfe332912f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675371661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1675371661
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.4014934138
Short name T278
Test name
Test status
Simulation time 73425710491 ps
CPU time 803.17 seconds
Started Jul 15 05:20:34 PM PDT 24
Finished Jul 15 05:33:58 PM PDT 24
Peak memory 238632 kb
Host smart-16d613f4-8862-4ad5-8d08-80c4205083c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014934138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.4014934138
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2035739452
Short name T250
Test name
Test status
Simulation time 30818985000 ps
CPU time 59.68 seconds
Started Jul 15 05:20:34 PM PDT 24
Finished Jul 15 05:21:34 PM PDT 24
Peak memory 219308 kb
Host smart-a9848336-122a-4840-8e88-663cedf9e8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035739452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2035739452
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3852242566
Short name T238
Test name
Test status
Simulation time 6229085274 ps
CPU time 19.3 seconds
Started Jul 15 05:20:24 PM PDT 24
Finished Jul 15 05:20:44 PM PDT 24
Peak memory 219244 kb
Host smart-49c0eeae-cd97-41d4-8974-9e0ea79ef389
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3852242566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3852242566
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3719441615
Short name T155
Test name
Test status
Simulation time 1347418869 ps
CPU time 19.9 seconds
Started Jul 15 05:20:25 PM PDT 24
Finished Jul 15 05:20:46 PM PDT 24
Peak memory 216604 kb
Host smart-1013322d-9319-417c-946a-7de3b6747e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719441615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3719441615
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2961485260
Short name T345
Test name
Test status
Simulation time 5629040436 ps
CPU time 83.23 seconds
Started Jul 15 05:20:24 PM PDT 24
Finished Jul 15 05:21:48 PM PDT 24
Peak memory 221196 kb
Host smart-bc03c7bf-26fb-432c-beb8-fb2faa2441d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961485260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2961485260
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.981532212
Short name T47
Test name
Test status
Simulation time 133289336089 ps
CPU time 1422 seconds
Started Jul 15 05:20:34 PM PDT 24
Finished Jul 15 05:44:16 PM PDT 24
Peak memory 234608 kb
Host smart-5e3b062d-c8c8-4899-84ce-0da5ebd9fd46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981532212 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.981532212
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2618753942
Short name T167
Test name
Test status
Simulation time 5858141739 ps
CPU time 28.01 seconds
Started Jul 15 05:20:40 PM PDT 24
Finished Jul 15 05:21:08 PM PDT 24
Peak memory 217528 kb
Host smart-e5d447e9-f659-421f-929f-776a4510af11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618753942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2618753942
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2177581859
Short name T20
Test name
Test status
Simulation time 180290895336 ps
CPU time 545.48 seconds
Started Jul 15 05:20:40 PM PDT 24
Finished Jul 15 05:29:46 PM PDT 24
Peak memory 234624 kb
Host smart-79dab3dd-6df1-499a-a84e-e827084a1e08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177581859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2177581859
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.964213439
Short name T241
Test name
Test status
Simulation time 7769237390 ps
CPU time 63.03 seconds
Started Jul 15 05:20:41 PM PDT 24
Finished Jul 15 05:21:44 PM PDT 24
Peak memory 219324 kb
Host smart-d91eb20e-c9d5-4d1b-9222-90e295191d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964213439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.964213439
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.457872750
Short name T7
Test name
Test status
Simulation time 13991053316 ps
CPU time 27.31 seconds
Started Jul 15 05:20:32 PM PDT 24
Finished Jul 15 05:21:00 PM PDT 24
Peak memory 211876 kb
Host smart-7e1ec0cb-c9dc-42f6-a60a-7f5d76dcde2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=457872750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.457872750
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3214246229
Short name T80
Test name
Test status
Simulation time 21825702797 ps
CPU time 75.47 seconds
Started Jul 15 05:20:31 PM PDT 24
Finished Jul 15 05:21:47 PM PDT 24
Peak memory 217012 kb
Host smart-8d9d5f4c-0d22-474e-a00a-ab6625bd82d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214246229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3214246229
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2592994487
Short name T257
Test name
Test status
Simulation time 18734317654 ps
CPU time 176.82 seconds
Started Jul 15 05:20:33 PM PDT 24
Finished Jul 15 05:23:30 PM PDT 24
Peak memory 221456 kb
Host smart-dce78704-736c-4acd-b4cc-b65780f2100e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592994487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2592994487
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1264308412
Short name T304
Test name
Test status
Simulation time 14925651092 ps
CPU time 31.85 seconds
Started Jul 15 05:20:54 PM PDT 24
Finished Jul 15 05:21:26 PM PDT 24
Peak memory 217388 kb
Host smart-e7426661-33ed-4239-9639-ff02da720c59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264308412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1264308412
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3607508763
Short name T288
Test name
Test status
Simulation time 11391591300 ps
CPU time 196.27 seconds
Started Jul 15 05:20:46 PM PDT 24
Finished Jul 15 05:24:03 PM PDT 24
Peak memory 240980 kb
Host smart-bc029a69-e6b5-4736-afa8-d7816b4c3d7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607508763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3607508763
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1903847847
Short name T300
Test name
Test status
Simulation time 13169852184 ps
CPU time 29.51 seconds
Started Jul 15 05:20:50 PM PDT 24
Finished Jul 15 05:21:20 PM PDT 24
Peak memory 219000 kb
Host smart-b67ae671-de9d-464b-88a4-c7e0258359fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903847847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1903847847
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.650262032
Short name T189
Test name
Test status
Simulation time 4119795401 ps
CPU time 21.7 seconds
Started Jul 15 05:20:50 PM PDT 24
Finished Jul 15 05:21:12 PM PDT 24
Peak memory 219348 kb
Host smart-6a7efbc0-613c-4242-b936-e5e4d83a5acc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=650262032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.650262032
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.102550389
Short name T209
Test name
Test status
Simulation time 5833913022 ps
CPU time 40.92 seconds
Started Jul 15 05:20:40 PM PDT 24
Finished Jul 15 05:21:21 PM PDT 24
Peak memory 216116 kb
Host smart-f42ce97a-1c5b-46b2-b5c7-0e11490a45a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102550389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.102550389
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2106835386
Short name T94
Test name
Test status
Simulation time 61609353106 ps
CPU time 134.24 seconds
Started Jul 15 05:20:48 PM PDT 24
Finished Jul 15 05:23:03 PM PDT 24
Peak memory 220908 kb
Host smart-6b30762b-30b6-4f03-b073-101d6daec70f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106835386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2106835386
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1422738465
Short name T24
Test name
Test status
Simulation time 8360731870 ps
CPU time 34.18 seconds
Started Jul 15 05:21:01 PM PDT 24
Finished Jul 15 05:21:36 PM PDT 24
Peak memory 217588 kb
Host smart-20ce38af-d334-4506-b7e6-51685dc2e1c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422738465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1422738465
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1965098442
Short name T253
Test name
Test status
Simulation time 111756891402 ps
CPU time 612.34 seconds
Started Jul 15 05:20:54 PM PDT 24
Finished Jul 15 05:31:07 PM PDT 24
Peak memory 225048 kb
Host smart-6883daa5-6125-455a-a40f-220d0927c72a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965098442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1965098442
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2585660555
Short name T327
Test name
Test status
Simulation time 47430885158 ps
CPU time 54.32 seconds
Started Jul 15 05:21:01 PM PDT 24
Finished Jul 15 05:21:56 PM PDT 24
Peak memory 219368 kb
Host smart-632be6c0-28ad-46f8-987f-d85cb388c8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585660555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2585660555
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1464049616
Short name T125
Test name
Test status
Simulation time 269442495 ps
CPU time 12.51 seconds
Started Jul 15 05:20:53 PM PDT 24
Finished Jul 15 05:21:06 PM PDT 24
Peak memory 217624 kb
Host smart-31766ca3-b571-47e3-a1a5-7940a6ec7a30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1464049616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1464049616
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2086457589
Short name T194
Test name
Test status
Simulation time 954497981 ps
CPU time 27.04 seconds
Started Jul 15 05:20:53 PM PDT 24
Finished Jul 15 05:21:21 PM PDT 24
Peak memory 216752 kb
Host smart-1ac3c918-5a31-4762-8946-1e8e1ef3b7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086457589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2086457589
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.705579759
Short name T137
Test name
Test status
Simulation time 12656041306 ps
CPU time 72.67 seconds
Started Jul 15 05:20:54 PM PDT 24
Finished Jul 15 05:22:07 PM PDT 24
Peak memory 219064 kb
Host smart-8f6922d8-4c05-43e2-9c3d-4ffd4f02a55b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705579759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.705579759
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3577336174
Short name T23
Test name
Test status
Simulation time 3542959712 ps
CPU time 25.54 seconds
Started Jul 15 05:21:09 PM PDT 24
Finished Jul 15 05:21:35 PM PDT 24
Peak memory 217132 kb
Host smart-253f4602-22dc-4bbc-b096-443674934ca1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577336174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3577336174
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1797122509
Short name T280
Test name
Test status
Simulation time 262112541468 ps
CPU time 448.29 seconds
Started Jul 15 05:21:01 PM PDT 24
Finished Jul 15 05:28:30 PM PDT 24
Peak memory 237864 kb
Host smart-a2a2b049-0347-48c5-a062-4df91dbd9d43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797122509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1797122509
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1262691839
Short name T50
Test name
Test status
Simulation time 16407042196 ps
CPU time 45.2 seconds
Started Jul 15 05:21:10 PM PDT 24
Finished Jul 15 05:21:55 PM PDT 24
Peak memory 219280 kb
Host smart-2633bfbc-9774-4fb0-a1ca-bf581c1ec3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262691839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1262691839
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3033502428
Short name T251
Test name
Test status
Simulation time 4159578659 ps
CPU time 34.78 seconds
Started Jul 15 05:21:01 PM PDT 24
Finished Jul 15 05:21:37 PM PDT 24
Peak memory 211588 kb
Host smart-2eec0cbb-3725-4144-9403-13d037eeb783
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3033502428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3033502428
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3285112393
Short name T258
Test name
Test status
Simulation time 15096035260 ps
CPU time 43.47 seconds
Started Jul 15 05:21:01 PM PDT 24
Finished Jul 15 05:21:45 PM PDT 24
Peak memory 217192 kb
Host smart-274892b3-05ce-43a9-870c-e8a54b7b941f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285112393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3285112393
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.1894589706
Short name T15
Test name
Test status
Simulation time 128602455410 ps
CPU time 2049.15 seconds
Started Jul 15 05:21:08 PM PDT 24
Finished Jul 15 05:55:18 PM PDT 24
Peak memory 235740 kb
Host smart-13f8571e-be69-4a7c-bf75-4e37ee246c74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894589706 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.1894589706
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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