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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.29 96.89 91.99 97.68 100.00 98.62 97.45 98.37


Total test records in report: 456
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T297 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3531325370 Jul 16 05:02:15 PM PDT 24 Jul 16 05:10:48 PM PDT 24 59182103378 ps
T298 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.4127332648 Jul 16 05:02:16 PM PDT 24 Jul 16 05:02:37 PM PDT 24 332521711 ps
T299 /workspace/coverage/default/49.rom_ctrl_smoke.4078617600 Jul 16 05:02:42 PM PDT 24 Jul 16 05:03:29 PM PDT 24 3517384543 ps
T300 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.725215979 Jul 16 05:01:54 PM PDT 24 Jul 16 05:02:32 PM PDT 24 2951483218 ps
T301 /workspace/coverage/default/21.rom_ctrl_smoke.17523351 Jul 16 05:01:29 PM PDT 24 Jul 16 05:02:01 PM PDT 24 1173817669 ps
T302 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1768496402 Jul 16 05:01:40 PM PDT 24 Jul 16 05:02:12 PM PDT 24 7051601481 ps
T303 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1898097510 Jul 16 05:01:26 PM PDT 24 Jul 16 05:01:57 PM PDT 24 17276368878 ps
T304 /workspace/coverage/default/25.rom_ctrl_alert_test.2075637402 Jul 16 05:01:56 PM PDT 24 Jul 16 05:02:06 PM PDT 24 169137858 ps
T305 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3095684956 Jul 16 05:01:29 PM PDT 24 Jul 16 05:02:40 PM PDT 24 61213259687 ps
T306 /workspace/coverage/default/14.rom_ctrl_stress_all.666089894 Jul 16 05:01:19 PM PDT 24 Jul 16 05:02:46 PM PDT 24 6949236154 ps
T307 /workspace/coverage/default/44.rom_ctrl_smoke.3093302012 Jul 16 05:02:30 PM PDT 24 Jul 16 05:03:02 PM PDT 24 3028877596 ps
T308 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1351144184 Jul 16 05:00:59 PM PDT 24 Jul 16 05:01:27 PM PDT 24 3127031079 ps
T309 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3054912172 Jul 16 05:01:02 PM PDT 24 Jul 16 05:01:29 PM PDT 24 12302900909 ps
T310 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1852011336 Jul 16 05:02:31 PM PDT 24 Jul 16 05:03:20 PM PDT 24 9697968303 ps
T311 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.187002006 Jul 16 05:00:43 PM PDT 24 Jul 16 05:01:00 PM PDT 24 1081307539 ps
T312 /workspace/coverage/default/8.rom_ctrl_smoke.4170100013 Jul 16 05:01:01 PM PDT 24 Jul 16 05:02:12 PM PDT 24 33401457389 ps
T313 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.544311711 Jul 16 05:02:15 PM PDT 24 Jul 16 05:02:35 PM PDT 24 1222463662 ps
T314 /workspace/coverage/default/30.rom_ctrl_alert_test.204797435 Jul 16 05:02:07 PM PDT 24 Jul 16 05:02:29 PM PDT 24 2212325303 ps
T315 /workspace/coverage/default/30.rom_ctrl_stress_all.4083553910 Jul 16 05:02:02 PM PDT 24 Jul 16 05:03:06 PM PDT 24 7555165412 ps
T316 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2407897910 Jul 16 05:02:06 PM PDT 24 Jul 16 05:02:34 PM PDT 24 1194086365 ps
T317 /workspace/coverage/default/17.rom_ctrl_smoke.2009385177 Jul 16 05:01:26 PM PDT 24 Jul 16 05:02:25 PM PDT 24 23173511391 ps
T318 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2501958561 Jul 16 05:01:30 PM PDT 24 Jul 16 05:02:13 PM PDT 24 3771929071 ps
T319 /workspace/coverage/default/36.rom_ctrl_stress_all.246706573 Jul 16 05:02:03 PM PDT 24 Jul 16 05:03:25 PM PDT 24 8703053493 ps
T320 /workspace/coverage/default/12.rom_ctrl_stress_all.3789779784 Jul 16 05:01:17 PM PDT 24 Jul 16 05:02:54 PM PDT 24 22147316576 ps
T321 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1867250904 Jul 16 05:01:15 PM PDT 24 Jul 16 05:01:28 PM PDT 24 181802997 ps
T322 /workspace/coverage/default/3.rom_ctrl_alert_test.3257689580 Jul 16 05:01:03 PM PDT 24 Jul 16 05:01:15 PM PDT 24 1713961564 ps
T323 /workspace/coverage/default/12.rom_ctrl_smoke.3148398014 Jul 16 05:01:18 PM PDT 24 Jul 16 05:02:00 PM PDT 24 4972663547 ps
T324 /workspace/coverage/default/40.rom_ctrl_smoke.1129900897 Jul 16 05:02:19 PM PDT 24 Jul 16 05:02:39 PM PDT 24 1424051953 ps
T325 /workspace/coverage/default/3.rom_ctrl_smoke.1542438619 Jul 16 05:00:59 PM PDT 24 Jul 16 05:01:33 PM PDT 24 9177026790 ps
T326 /workspace/coverage/default/6.rom_ctrl_stress_all.2645010641 Jul 16 05:01:02 PM PDT 24 Jul 16 05:01:29 PM PDT 24 3651188986 ps
T327 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.618258131 Jul 16 05:01:19 PM PDT 24 Jul 16 05:01:51 PM PDT 24 12296641254 ps
T328 /workspace/coverage/default/5.rom_ctrl_alert_test.4086032905 Jul 16 05:01:04 PM PDT 24 Jul 16 05:01:28 PM PDT 24 2466353979 ps
T329 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1961012507 Jul 16 05:02:16 PM PDT 24 Jul 16 05:02:40 PM PDT 24 4123062271 ps
T330 /workspace/coverage/default/24.rom_ctrl_stress_all.3890246804 Jul 16 05:01:39 PM PDT 24 Jul 16 05:02:28 PM PDT 24 8401979425 ps
T331 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2803680974 Jul 16 05:01:31 PM PDT 24 Jul 16 05:02:35 PM PDT 24 25160171927 ps
T332 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3466422212 Jul 16 05:01:26 PM PDT 24 Jul 16 05:02:32 PM PDT 24 25743882715 ps
T333 /workspace/coverage/default/29.rom_ctrl_stress_all.1867907317 Jul 16 05:01:58 PM PDT 24 Jul 16 05:02:55 PM PDT 24 18580641848 ps
T334 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2779531098 Jul 16 05:00:45 PM PDT 24 Jul 16 05:01:38 PM PDT 24 8330558028 ps
T335 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1952212097 Jul 16 05:02:43 PM PDT 24 Jul 16 05:02:54 PM PDT 24 177129483 ps
T336 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2568597595 Jul 16 05:01:04 PM PDT 24 Jul 16 05:06:34 PM PDT 24 20113616441 ps
T337 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.97681625 Jul 16 05:01:02 PM PDT 24 Jul 16 05:01:42 PM PDT 24 3552880852 ps
T338 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.327245898 Jul 16 05:02:02 PM PDT 24 Jul 16 05:04:26 PM PDT 24 2133934043 ps
T339 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2352962759 Jul 16 05:02:31 PM PDT 24 Jul 16 05:11:48 PM PDT 24 51999068667 ps
T340 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2768412079 Jul 16 05:01:04 PM PDT 24 Jul 16 05:01:15 PM PDT 24 863329136 ps
T341 /workspace/coverage/default/17.rom_ctrl_stress_all.4158179073 Jul 16 05:01:31 PM PDT 24 Jul 16 05:02:32 PM PDT 24 9905633086 ps
T342 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2994515362 Jul 16 05:01:24 PM PDT 24 Jul 16 05:01:58 PM PDT 24 16644728954 ps
T343 /workspace/coverage/default/39.rom_ctrl_stress_all.1565728019 Jul 16 05:02:16 PM PDT 24 Jul 16 05:04:05 PM PDT 24 12337512147 ps
T344 /workspace/coverage/default/33.rom_ctrl_smoke.1262513516 Jul 16 05:02:05 PM PDT 24 Jul 16 05:02:38 PM PDT 24 1731014322 ps
T28 /workspace/coverage/default/2.rom_ctrl_sec_cm.2094543454 Jul 16 05:01:01 PM PDT 24 Jul 16 05:03:17 PM PDT 24 6422796513 ps
T345 /workspace/coverage/default/15.rom_ctrl_stress_all.2841954024 Jul 16 05:01:19 PM PDT 24 Jul 16 05:02:14 PM PDT 24 4291418394 ps
T346 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3674634939 Jul 16 05:03:12 PM PDT 24 Jul 16 05:03:46 PM PDT 24 13312590499 ps
T347 /workspace/coverage/default/16.rom_ctrl_smoke.1093045494 Jul 16 05:01:27 PM PDT 24 Jul 16 05:02:14 PM PDT 24 7897982958 ps
T348 /workspace/coverage/default/31.rom_ctrl_stress_all.3698564823 Jul 16 05:02:05 PM PDT 24 Jul 16 05:03:12 PM PDT 24 23759928113 ps
T349 /workspace/coverage/default/7.rom_ctrl_stress_all.3026416475 Jul 16 05:01:00 PM PDT 24 Jul 16 05:02:56 PM PDT 24 21885844716 ps
T350 /workspace/coverage/default/48.rom_ctrl_stress_all.3914214950 Jul 16 05:02:43 PM PDT 24 Jul 16 05:04:42 PM PDT 24 11283347955 ps
T351 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.458389938 Jul 16 05:02:31 PM PDT 24 Jul 16 05:03:09 PM PDT 24 6142636592 ps
T352 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.4038788982 Jul 16 05:02:15 PM PDT 24 Jul 16 05:02:46 PM PDT 24 6177311729 ps
T353 /workspace/coverage/default/38.rom_ctrl_stress_all.1515878047 Jul 16 05:02:17 PM PDT 24 Jul 16 05:03:36 PM PDT 24 18571448316 ps
T354 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2147443528 Jul 16 05:01:26 PM PDT 24 Jul 16 05:01:51 PM PDT 24 8614815139 ps
T355 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.4129469079 Jul 16 05:02:06 PM PDT 24 Jul 16 05:03:13 PM PDT 24 33393661513 ps
T356 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.994841608 Jul 16 05:01:00 PM PDT 24 Jul 16 05:03:22 PM PDT 24 4487215671 ps
T357 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3268371709 Jul 16 05:02:04 PM PDT 24 Jul 16 05:02:41 PM PDT 24 7241496712 ps
T64 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1005875746 Jul 16 05:03:22 PM PDT 24 Jul 16 05:04:46 PM PDT 24 17212405911 ps
T55 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3081299117 Jul 16 05:03:29 PM PDT 24 Jul 16 05:03:52 PM PDT 24 9600901127 ps
T65 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.4057679878 Jul 16 05:03:29 PM PDT 24 Jul 16 05:04:17 PM PDT 24 1405690076 ps
T68 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2752727498 Jul 16 05:03:28 PM PDT 24 Jul 16 05:03:59 PM PDT 24 4046955825 ps
T358 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3492766683 Jul 16 05:02:53 PM PDT 24 Jul 16 05:03:16 PM PDT 24 2409021984 ps
T104 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.4183984849 Jul 16 05:03:18 PM PDT 24 Jul 16 05:03:30 PM PDT 24 835507460 ps
T359 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1756684899 Jul 16 05:03:29 PM PDT 24 Jul 16 05:03:54 PM PDT 24 4940764455 ps
T360 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1363607325 Jul 16 05:03:30 PM PDT 24 Jul 16 05:04:07 PM PDT 24 4043686408 ps
T361 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3202340218 Jul 16 05:02:55 PM PDT 24 Jul 16 05:03:26 PM PDT 24 16467401395 ps
T362 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1077353148 Jul 16 05:03:30 PM PDT 24 Jul 16 05:03:53 PM PDT 24 6484867851 ps
T60 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1226110264 Jul 16 05:02:57 PM PDT 24 Jul 16 05:05:50 PM PDT 24 34725140765 ps
T108 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.6497820 Jul 16 05:03:28 PM PDT 24 Jul 16 05:04:34 PM PDT 24 19466254979 ps
T363 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.501430814 Jul 16 05:03:25 PM PDT 24 Jul 16 05:03:57 PM PDT 24 3844374881 ps
T69 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3530272303 Jul 16 05:02:42 PM PDT 24 Jul 16 05:02:51 PM PDT 24 167771879 ps
T70 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1243072849 Jul 16 05:02:55 PM PDT 24 Jul 16 05:03:07 PM PDT 24 437560551 ps
T364 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3684185301 Jul 16 05:02:55 PM PDT 24 Jul 16 05:03:19 PM PDT 24 17485716836 ps
T365 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3276738813 Jul 16 05:02:57 PM PDT 24 Jul 16 05:03:06 PM PDT 24 339042172 ps
T366 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.545299119 Jul 16 05:03:27 PM PDT 24 Jul 16 05:03:37 PM PDT 24 386957035 ps
T61 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2550156766 Jul 16 05:03:29 PM PDT 24 Jul 16 05:06:09 PM PDT 24 1039123591 ps
T367 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2615300118 Jul 16 05:02:44 PM PDT 24 Jul 16 05:03:13 PM PDT 24 2942672522 ps
T62 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1652482351 Jul 16 05:03:19 PM PDT 24 Jul 16 05:04:59 PM PDT 24 5387126428 ps
T71 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1512800049 Jul 16 05:02:55 PM PDT 24 Jul 16 05:05:10 PM PDT 24 100534174851 ps
T368 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2942695536 Jul 16 05:02:44 PM PDT 24 Jul 16 05:02:54 PM PDT 24 173926136 ps
T109 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3808087894 Jul 16 05:03:26 PM PDT 24 Jul 16 05:06:01 PM PDT 24 1089067652 ps
T105 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.472201661 Jul 16 05:03:31 PM PDT 24 Jul 16 05:03:41 PM PDT 24 719069330 ps
T113 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2464978778 Jul 16 05:03:28 PM PDT 24 Jul 16 05:06:19 PM PDT 24 15552834771 ps
T114 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3825141555 Jul 16 05:03:20 PM PDT 24 Jul 16 05:06:07 PM PDT 24 10009666745 ps
T101 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3901646766 Jul 16 05:03:29 PM PDT 24 Jul 16 05:03:44 PM PDT 24 2420351570 ps
T106 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.488509305 Jul 16 05:03:25 PM PDT 24 Jul 16 05:05:07 PM PDT 24 21469539015 ps
T369 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2130889889 Jul 16 05:03:30 PM PDT 24 Jul 16 05:03:56 PM PDT 24 10840412411 ps
T370 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1446283114 Jul 16 05:02:52 PM PDT 24 Jul 16 05:03:13 PM PDT 24 1987905074 ps
T371 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3214499431 Jul 16 05:03:31 PM PDT 24 Jul 16 05:04:03 PM PDT 24 19480641433 ps
T112 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3680518732 Jul 16 05:02:45 PM PDT 24 Jul 16 05:05:28 PM PDT 24 7722554903 ps
T72 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2815151374 Jul 16 05:02:53 PM PDT 24 Jul 16 05:03:11 PM PDT 24 2521882186 ps
T73 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2952192807 Jul 16 05:03:32 PM PDT 24 Jul 16 05:05:03 PM PDT 24 31690583496 ps
T372 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1497833381 Jul 16 05:03:20 PM PDT 24 Jul 16 05:03:46 PM PDT 24 11827180805 ps
T373 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2511413097 Jul 16 05:02:52 PM PDT 24 Jul 16 05:03:05 PM PDT 24 2389484032 ps
T74 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3785567831 Jul 16 05:03:30 PM PDT 24 Jul 16 05:04:27 PM PDT 24 2138761991 ps
T374 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.394142510 Jul 16 05:02:55 PM PDT 24 Jul 16 05:03:19 PM PDT 24 23858651811 ps
T117 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3781350218 Jul 16 05:03:31 PM PDT 24 Jul 16 05:04:55 PM PDT 24 816364259 ps
T375 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3234843143 Jul 16 05:02:54 PM PDT 24 Jul 16 05:03:10 PM PDT 24 4473838188 ps
T376 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1957725905 Jul 16 05:03:25 PM PDT 24 Jul 16 05:03:34 PM PDT 24 173405168 ps
T75 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3749419297 Jul 16 05:03:00 PM PDT 24 Jul 16 05:03:12 PM PDT 24 1081200977 ps
T377 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2442018292 Jul 16 05:02:45 PM PDT 24 Jul 16 05:02:54 PM PDT 24 175992746 ps
T378 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2330691254 Jul 16 05:03:26 PM PDT 24 Jul 16 05:03:36 PM PDT 24 1504662759 ps
T379 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3179550042 Jul 16 05:02:54 PM PDT 24 Jul 16 05:03:03 PM PDT 24 710292824 ps
T380 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3943213551 Jul 16 05:03:20 PM PDT 24 Jul 16 05:03:55 PM PDT 24 4744660884 ps
T381 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1605626894 Jul 16 05:03:31 PM PDT 24 Jul 16 05:03:48 PM PDT 24 3084938688 ps
T382 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1650288529 Jul 16 05:03:26 PM PDT 24 Jul 16 05:03:39 PM PDT 24 687871625 ps
T383 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.465410990 Jul 16 05:03:29 PM PDT 24 Jul 16 05:04:01 PM PDT 24 4121660996 ps
T384 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2969757187 Jul 16 05:03:31 PM PDT 24 Jul 16 05:04:09 PM PDT 24 4249721695 ps
T385 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1974422357 Jul 16 05:03:20 PM PDT 24 Jul 16 05:03:29 PM PDT 24 847289548 ps
T386 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1917136467 Jul 16 05:03:30 PM PDT 24 Jul 16 05:03:44 PM PDT 24 231438716 ps
T387 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2876364611 Jul 16 05:03:27 PM PDT 24 Jul 16 05:03:57 PM PDT 24 18668727850 ps
T102 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2998912038 Jul 16 05:03:31 PM PDT 24 Jul 16 05:03:41 PM PDT 24 178093076 ps
T76 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.378643255 Jul 16 05:03:18 PM PDT 24 Jul 16 05:05:14 PM PDT 24 48634331577 ps
T103 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.92189239 Jul 16 05:03:28 PM PDT 24 Jul 16 05:03:48 PM PDT 24 2026576666 ps
T82 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1338504754 Jul 16 05:03:22 PM PDT 24 Jul 16 05:05:22 PM PDT 24 28808920286 ps
T388 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.498925985 Jul 16 05:02:42 PM PDT 24 Jul 16 05:02:57 PM PDT 24 980434867 ps
T389 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2245030542 Jul 16 05:03:29 PM PDT 24 Jul 16 05:03:41 PM PDT 24 1372723304 ps
T390 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.278269927 Jul 16 05:03:30 PM PDT 24 Jul 16 05:03:47 PM PDT 24 2297428451 ps
T391 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3800456796 Jul 16 05:03:19 PM PDT 24 Jul 16 05:03:32 PM PDT 24 339239707 ps
T392 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2479791936 Jul 16 05:03:31 PM PDT 24 Jul 16 05:03:45 PM PDT 24 177455994 ps
T110 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3293078281 Jul 16 05:03:25 PM PDT 24 Jul 16 05:06:09 PM PDT 24 1584912430 ps
T393 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3302195038 Jul 16 05:02:54 PM PDT 24 Jul 16 05:03:05 PM PDT 24 615602198 ps
T115 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2488043796 Jul 16 05:03:28 PM PDT 24 Jul 16 05:05:01 PM PDT 24 4768854863 ps
T83 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.554861834 Jul 16 05:02:56 PM PDT 24 Jul 16 05:03:40 PM PDT 24 2118041182 ps
T394 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3036978459 Jul 16 05:03:20 PM PDT 24 Jul 16 05:03:32 PM PDT 24 338398633 ps
T395 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2333386425 Jul 16 05:03:31 PM PDT 24 Jul 16 05:04:03 PM PDT 24 8171976659 ps
T84 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.424983066 Jul 16 05:02:41 PM PDT 24 Jul 16 05:05:56 PM PDT 24 26384019890 ps
T396 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.531533396 Jul 16 05:03:30 PM PDT 24 Jul 16 05:03:41 PM PDT 24 195207692 ps
T397 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1180681209 Jul 16 05:02:57 PM PDT 24 Jul 16 05:03:06 PM PDT 24 353378399 ps
T398 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2750788891 Jul 16 05:02:55 PM PDT 24 Jul 16 05:04:26 PM PDT 24 5519542002 ps
T399 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3489142487 Jul 16 05:03:19 PM PDT 24 Jul 16 05:03:58 PM PDT 24 2863874805 ps
T400 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.617214094 Jul 16 05:03:30 PM PDT 24 Jul 16 05:04:00 PM PDT 24 14036478596 ps
T401 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1253960122 Jul 16 05:02:42 PM PDT 24 Jul 16 05:05:22 PM PDT 24 17227649145 ps
T402 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1040625212 Jul 16 05:03:27 PM PDT 24 Jul 16 05:03:56 PM PDT 24 6806719866 ps
T403 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3752496669 Jul 16 05:02:55 PM PDT 24 Jul 16 05:03:29 PM PDT 24 16708084437 ps
T404 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1767137607 Jul 16 05:02:54 PM PDT 24 Jul 16 05:03:09 PM PDT 24 1843964601 ps
T405 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3515803575 Jul 16 05:03:19 PM PDT 24 Jul 16 05:03:42 PM PDT 24 2651046158 ps
T406 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3231952549 Jul 16 05:02:55 PM PDT 24 Jul 16 05:03:07 PM PDT 24 689297470 ps
T407 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1159035182 Jul 16 05:03:22 PM PDT 24 Jul 16 05:03:37 PM PDT 24 1082593200 ps
T408 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3149618330 Jul 16 05:02:44 PM PDT 24 Jul 16 05:05:24 PM PDT 24 2224116479 ps
T409 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1963161856 Jul 16 05:03:28 PM PDT 24 Jul 16 05:05:42 PM PDT 24 68314344989 ps
T410 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.88707243 Jul 16 05:02:56 PM PDT 24 Jul 16 05:03:05 PM PDT 24 750500170 ps
T411 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.887385298 Jul 16 05:03:21 PM PDT 24 Jul 16 05:03:46 PM PDT 24 2914678123 ps
T412 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3060423651 Jul 16 05:03:29 PM PDT 24 Jul 16 05:03:47 PM PDT 24 3075193584 ps
T413 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3671203001 Jul 16 05:03:21 PM PDT 24 Jul 16 05:03:48 PM PDT 24 13721334763 ps
T86 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2975889889 Jul 16 05:02:54 PM PDT 24 Jul 16 05:04:17 PM PDT 24 18066192790 ps
T414 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.957637012 Jul 16 05:02:52 PM PDT 24 Jul 16 05:03:21 PM PDT 24 11946719560 ps
T415 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1441969025 Jul 16 05:03:20 PM PDT 24 Jul 16 05:03:46 PM PDT 24 5804039541 ps
T116 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.929783684 Jul 16 05:03:19 PM PDT 24 Jul 16 05:04:57 PM PDT 24 2484390836 ps
T87 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3328144 Jul 16 05:03:28 PM PDT 24 Jul 16 05:03:50 PM PDT 24 4253004956 ps
T416 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2433490081 Jul 16 05:03:41 PM PDT 24 Jul 16 05:05:26 PM PDT 24 16552607081 ps
T417 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1234534532 Jul 16 05:02:57 PM PDT 24 Jul 16 05:03:31 PM PDT 24 3857284092 ps
T418 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.742767535 Jul 16 05:03:20 PM PDT 24 Jul 16 05:03:29 PM PDT 24 183720653 ps
T111 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2249744590 Jul 16 05:03:27 PM PDT 24 Jul 16 05:06:18 PM PDT 24 6972543092 ps
T419 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2821961952 Jul 16 05:03:20 PM PDT 24 Jul 16 05:03:45 PM PDT 24 2903961224 ps
T420 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2886870206 Jul 16 05:02:55 PM PDT 24 Jul 16 05:03:25 PM PDT 24 3835306035 ps
T421 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2064332427 Jul 16 05:03:28 PM PDT 24 Jul 16 05:03:37 PM PDT 24 688292460 ps
T422 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.93445989 Jul 16 05:02:55 PM PDT 24 Jul 16 05:03:08 PM PDT 24 760885175 ps
T88 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3235496853 Jul 16 05:03:19 PM PDT 24 Jul 16 05:03:43 PM PDT 24 4160541544 ps
T423 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2857421168 Jul 16 05:02:53 PM PDT 24 Jul 16 05:03:02 PM PDT 24 338597053 ps
T424 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3165968462 Jul 16 05:03:29 PM PDT 24 Jul 16 05:04:00 PM PDT 24 8190953396 ps
T425 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1428872950 Jul 16 05:03:19 PM PDT 24 Jul 16 05:03:43 PM PDT 24 9735855640 ps
T426 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4252834245 Jul 16 05:02:56 PM PDT 24 Jul 16 05:03:27 PM PDT 24 4339436124 ps
T427 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.883766472 Jul 16 05:02:54 PM PDT 24 Jul 16 05:03:30 PM PDT 24 7784139376 ps
T428 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1167478176 Jul 16 05:03:31 PM PDT 24 Jul 16 05:03:59 PM PDT 24 3178315952 ps
T89 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3280882754 Jul 16 05:02:42 PM PDT 24 Jul 16 05:02:51 PM PDT 24 174543992 ps
T118 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4139223473 Jul 16 05:02:54 PM PDT 24 Jul 16 05:05:44 PM PDT 24 48028602340 ps
T429 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.85143765 Jul 16 05:03:27 PM PDT 24 Jul 16 05:03:56 PM PDT 24 15398435185 ps
T430 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.817368178 Jul 16 05:03:27 PM PDT 24 Jul 16 05:03:53 PM PDT 24 29127453033 ps
T90 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4134854504 Jul 16 05:03:22 PM PDT 24 Jul 16 05:03:35 PM PDT 24 3390154620 ps
T431 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2889629771 Jul 16 05:03:31 PM PDT 24 Jul 16 05:05:12 PM PDT 24 11751966990 ps
T119 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1951391331 Jul 16 05:03:22 PM PDT 24 Jul 16 05:05:06 PM PDT 24 54850488247 ps
T432 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1387555576 Jul 16 05:03:21 PM PDT 24 Jul 16 05:03:48 PM PDT 24 22743568032 ps
T433 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3258541561 Jul 16 05:03:32 PM PDT 24 Jul 16 05:03:57 PM PDT 24 2552548646 ps
T434 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2038342280 Jul 16 05:02:43 PM PDT 24 Jul 16 05:03:08 PM PDT 24 5958308339 ps
T435 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3965370995 Jul 16 05:03:27 PM PDT 24 Jul 16 05:03:47 PM PDT 24 1806224180 ps
T436 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.693740024 Jul 16 05:03:18 PM PDT 24 Jul 16 05:03:42 PM PDT 24 12260882722 ps
T437 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.494392843 Jul 16 05:03:26 PM PDT 24 Jul 16 05:06:27 PM PDT 24 24890003340 ps
T438 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2786244371 Jul 16 05:02:45 PM PDT 24 Jul 16 05:03:05 PM PDT 24 3749138355 ps
T439 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3682741876 Jul 16 05:03:20 PM PDT 24 Jul 16 05:05:55 PM PDT 24 16293174448 ps
T440 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.575733525 Jul 16 05:02:56 PM PDT 24 Jul 16 05:03:27 PM PDT 24 3784189929 ps
T441 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.941307015 Jul 16 05:02:44 PM PDT 24 Jul 16 05:03:10 PM PDT 24 8235911967 ps
T442 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.114274132 Jul 16 05:02:56 PM PDT 24 Jul 16 05:03:09 PM PDT 24 717736348 ps
T120 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.201663815 Jul 16 05:03:27 PM PDT 24 Jul 16 05:06:19 PM PDT 24 11926767232 ps
T443 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4185518763 Jul 16 05:02:54 PM PDT 24 Jul 16 05:03:26 PM PDT 24 3986781516 ps
T444 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3222520434 Jul 16 05:03:19 PM PDT 24 Jul 16 05:03:36 PM PDT 24 2168606576 ps
T445 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.4016680585 Jul 16 05:02:54 PM PDT 24 Jul 16 05:03:07 PM PDT 24 185685622 ps
T446 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3649857951 Jul 16 05:02:54 PM PDT 24 Jul 16 05:03:25 PM PDT 24 15656434832 ps
T447 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3548225783 Jul 16 05:03:30 PM PDT 24 Jul 16 05:04:09 PM PDT 24 2355256780 ps
T448 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.819240312 Jul 16 05:02:41 PM PDT 24 Jul 16 05:03:11 PM PDT 24 11420784478 ps
T449 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.508892401 Jul 16 05:03:19 PM PDT 24 Jul 16 05:03:40 PM PDT 24 5470905364 ps
T450 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2760316902 Jul 16 05:02:58 PM PDT 24 Jul 16 05:03:07 PM PDT 24 352922524 ps
T451 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2093997452 Jul 16 05:02:56 PM PDT 24 Jul 16 05:03:13 PM PDT 24 2892424392 ps
T452 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1987661817 Jul 16 05:03:27 PM PDT 24 Jul 16 05:04:05 PM PDT 24 9844447851 ps
T91 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.376701546 Jul 16 05:03:18 PM PDT 24 Jul 16 05:06:19 PM PDT 24 43620668042 ps
T453 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3980709139 Jul 16 05:03:26 PM PDT 24 Jul 16 05:03:35 PM PDT 24 533853649 ps
T454 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2112291435 Jul 16 05:02:55 PM PDT 24 Jul 16 05:03:06 PM PDT 24 1323847936 ps
T92 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.176211457 Jul 16 05:02:55 PM PDT 24 Jul 16 05:03:26 PM PDT 24 4313631421 ps
T455 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2316396804 Jul 16 05:02:56 PM PDT 24 Jul 16 05:03:25 PM PDT 24 18734956583 ps
T456 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.750034278 Jul 16 05:03:31 PM PDT 24 Jul 16 05:05:13 PM PDT 24 3550757396 ps
T85 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2011210423 Jul 16 05:03:28 PM PDT 24 Jul 16 05:03:50 PM PDT 24 31818336469 ps

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.309810651
Short name T2
Test name
Test status
Simulation time 31366930197 ps
CPU time 426.28 seconds
Started Jul 16 05:01:29 PM PDT 24
Finished Jul 16 05:08:37 PM PDT 24
Peak memory 236760 kb
Host smart-623b7164-f1a1-469c-840a-e51d7e7fd4e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309810651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.309810651
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.1973871580
Short name T12
Test name
Test status
Simulation time 51607371688 ps
CPU time 984.44 seconds
Started Jul 16 05:02:21 PM PDT 24
Finished Jul 16 05:18:46 PM PDT 24
Peak memory 234328 kb
Host smart-5b61e83f-9749-47d5-a1a0-1dd6e3886d7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973871580 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.1973871580
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.4005441985
Short name T18
Test name
Test status
Simulation time 4114651348 ps
CPU time 31.32 seconds
Started Jul 16 05:01:54 PM PDT 24
Finished Jul 16 05:02:26 PM PDT 24
Peak memory 211448 kb
Host smart-8fc51d20-103c-4061-8be9-b6b0448a45e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4005441985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.4005441985
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2911031124
Short name T140
Test name
Test status
Simulation time 624076290544 ps
CPU time 497.56 seconds
Started Jul 16 05:02:30 PM PDT 24
Finished Jul 16 05:10:48 PM PDT 24
Peak memory 238732 kb
Host smart-3fc8d52c-c4bc-4381-b438-c61831704f20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911031124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2911031124
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3808087894
Short name T109
Test name
Test status
Simulation time 1089067652 ps
CPU time 154.02 seconds
Started Jul 16 05:03:26 PM PDT 24
Finished Jul 16 05:06:01 PM PDT 24
Peak memory 214132 kb
Host smart-ceb5524c-879f-4fc0-9d49-731757db7e65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808087894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3808087894
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.695285908
Short name T78
Test name
Test status
Simulation time 10596927408 ps
CPU time 49.87 seconds
Started Jul 16 05:01:20 PM PDT 24
Finished Jul 16 05:02:13 PM PDT 24
Peak memory 220884 kb
Host smart-ac8ed17a-d919-4563-85e3-300906428c30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695285908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.695285908
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.3973863504
Short name T13
Test name
Test status
Simulation time 25441963484 ps
CPU time 953.93 seconds
Started Jul 16 05:01:53 PM PDT 24
Finished Jul 16 05:17:47 PM PDT 24
Peak memory 230500 kb
Host smart-7ea612d0-a4cc-4e87-949e-b7cef3634ec1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973863504 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.3973863504
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.237418820
Short name T19
Test name
Test status
Simulation time 904255497 ps
CPU time 117.37 seconds
Started Jul 16 05:00:46 PM PDT 24
Finished Jul 16 05:02:44 PM PDT 24
Peak memory 238440 kb
Host smart-ada8431b-c65c-46a6-9629-e633c15099ac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237418820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.237418820
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.4057679878
Short name T65
Test name
Test status
Simulation time 1405690076 ps
CPU time 46.85 seconds
Started Jul 16 05:03:29 PM PDT 24
Finished Jul 16 05:04:17 PM PDT 24
Peak memory 213620 kb
Host smart-bb5ced5a-0398-4659-9ea7-6c25c07a67b4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057679878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.4057679878
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.698257261
Short name T22
Test name
Test status
Simulation time 970594211 ps
CPU time 8.45 seconds
Started Jul 16 05:01:00 PM PDT 24
Finished Jul 16 05:01:09 PM PDT 24
Peak memory 217028 kb
Host smart-e9481389-e488-456c-94bb-e634fb2ebf87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698257261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.698257261
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3680518732
Short name T112
Test name
Test status
Simulation time 7722554903 ps
CPU time 162.24 seconds
Started Jul 16 05:02:45 PM PDT 24
Finished Jul 16 05:05:28 PM PDT 24
Peak memory 213148 kb
Host smart-607288c8-4ce3-4e6f-ace0-d4954661a785
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680518732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3680518732
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1807098151
Short name T57
Test name
Test status
Simulation time 517888789 ps
CPU time 22.43 seconds
Started Jul 16 05:00:44 PM PDT 24
Finished Jul 16 05:01:07 PM PDT 24
Peak memory 219260 kb
Host smart-a44f9a60-a2af-458f-bfcf-bda4f48b0887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807098151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1807098151
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1991844854
Short name T227
Test name
Test status
Simulation time 16979648994 ps
CPU time 65.33 seconds
Started Jul 16 05:01:18 PM PDT 24
Finished Jul 16 05:02:26 PM PDT 24
Peak memory 219144 kb
Host smart-efa88981-d296-4f51-88fd-dc4d26f79e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991844854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1991844854
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3238488541
Short name T46
Test name
Test status
Simulation time 6234802335 ps
CPU time 36.07 seconds
Started Jul 16 05:01:57 PM PDT 24
Finished Jul 16 05:02:33 PM PDT 24
Peak memory 219356 kb
Host smart-4ae60911-c26e-4949-a630-d3bc952ee333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238488541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3238488541
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3293078281
Short name T110
Test name
Test status
Simulation time 1584912430 ps
CPU time 163.47 seconds
Started Jul 16 05:03:25 PM PDT 24
Finished Jul 16 05:06:09 PM PDT 24
Peak memory 214000 kb
Host smart-ba361434-7f9a-4ea9-921a-d4748e91da98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293078281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3293078281
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3811020609
Short name T126
Test name
Test status
Simulation time 25979328423 ps
CPU time 145.19 seconds
Started Jul 16 05:01:16 PM PDT 24
Finished Jul 16 05:03:44 PM PDT 24
Peak memory 235236 kb
Host smart-21256190-0628-4285-9459-8a6786eeaad9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811020609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3811020609
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.376701546
Short name T91
Test name
Test status
Simulation time 43620668042 ps
CPU time 180.66 seconds
Started Jul 16 05:03:18 PM PDT 24
Finished Jul 16 05:06:19 PM PDT 24
Peak memory 215028 kb
Host smart-74f30a15-90c1-4b2e-9928-0220d64a0410
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376701546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.376701546
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.201663815
Short name T120
Test name
Test status
Simulation time 11926767232 ps
CPU time 171.08 seconds
Started Jul 16 05:03:27 PM PDT 24
Finished Jul 16 05:06:19 PM PDT 24
Peak memory 215120 kb
Host smart-88585082-588d-41d4-825a-b0b6deed487e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201663815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.201663815
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2969722237
Short name T93
Test name
Test status
Simulation time 442389619 ps
CPU time 13.36 seconds
Started Jul 16 05:02:31 PM PDT 24
Finished Jul 16 05:02:45 PM PDT 24
Peak memory 218516 kb
Host smart-e97a77fd-d848-4560-8c3e-3e46b1042c50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2969722237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2969722237
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3280882754
Short name T89
Test name
Test status
Simulation time 174543992 ps
CPU time 8.14 seconds
Started Jul 16 05:02:42 PM PDT 24
Finished Jul 16 05:02:51 PM PDT 24
Peak memory 210548 kb
Host smart-901e1645-a61c-490f-8ac5-a6020a716fa3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280882754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3280882754
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.498925985
Short name T388
Test name
Test status
Simulation time 980434867 ps
CPU time 14.51 seconds
Started Jul 16 05:02:42 PM PDT 24
Finished Jul 16 05:02:57 PM PDT 24
Peak memory 210720 kb
Host smart-246ff09c-3468-4895-9ab2-f3c4df3fff8f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498925985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.498925985
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2038342280
Short name T434
Test name
Test status
Simulation time 5958308339 ps
CPU time 24.01 seconds
Started Jul 16 05:02:43 PM PDT 24
Finished Jul 16 05:03:08 PM PDT 24
Peak memory 211776 kb
Host smart-0f09c6b6-c6ad-4c62-9133-ea8e34fd3db7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038342280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2038342280
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2942695536
Short name T368
Test name
Test status
Simulation time 173926136 ps
CPU time 8.28 seconds
Started Jul 16 05:02:44 PM PDT 24
Finished Jul 16 05:02:54 PM PDT 24
Peak memory 213580 kb
Host smart-c8f0b2ec-16e8-49a6-b52d-263670403161
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942695536 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2942695536
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3530272303
Short name T69
Test name
Test status
Simulation time 167771879 ps
CPU time 8.31 seconds
Started Jul 16 05:02:42 PM PDT 24
Finished Jul 16 05:02:51 PM PDT 24
Peak memory 210704 kb
Host smart-3d63d366-43ef-452a-8a3b-17a0f488a119
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530272303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3530272303
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2442018292
Short name T377
Test name
Test status
Simulation time 175992746 ps
CPU time 8.19 seconds
Started Jul 16 05:02:45 PM PDT 24
Finished Jul 16 05:02:54 PM PDT 24
Peak memory 210592 kb
Host smart-42f0b1f0-8065-4e10-b493-7691375bcb0f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442018292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2442018292
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.941307015
Short name T441
Test name
Test status
Simulation time 8235911967 ps
CPU time 24.99 seconds
Started Jul 16 05:02:44 PM PDT 24
Finished Jul 16 05:03:10 PM PDT 24
Peak memory 210860 kb
Host smart-d0baff2e-96a8-4e01-987e-b8c9373f9609
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941307015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
941307015
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1253960122
Short name T401
Test name
Test status
Simulation time 17227649145 ps
CPU time 159.1 seconds
Started Jul 16 05:02:42 PM PDT 24
Finished Jul 16 05:05:22 PM PDT 24
Peak memory 214912 kb
Host smart-0c2de24a-eeed-4a3d-91f0-3b5548b9cedf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253960122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1253960122
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.819240312
Short name T448
Test name
Test status
Simulation time 11420784478 ps
CPU time 28.77 seconds
Started Jul 16 05:02:41 PM PDT 24
Finished Jul 16 05:03:11 PM PDT 24
Peak memory 212820 kb
Host smart-40635145-0c1c-4855-8592-1b05f46f89fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819240312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.819240312
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2615300118
Short name T367
Test name
Test status
Simulation time 2942672522 ps
CPU time 28.15 seconds
Started Jul 16 05:02:44 PM PDT 24
Finished Jul 16 05:03:13 PM PDT 24
Peak memory 218264 kb
Host smart-0823d8ac-f5de-43bd-a97b-2ae775a0a45f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615300118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2615300118
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3149618330
Short name T408
Test name
Test status
Simulation time 2224116479 ps
CPU time 159.17 seconds
Started Jul 16 05:02:44 PM PDT 24
Finished Jul 16 05:05:24 PM PDT 24
Peak memory 213668 kb
Host smart-d73c1ce8-c6f4-47a6-af15-6793c9d72c70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149618330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3149618330
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2760316902
Short name T450
Test name
Test status
Simulation time 352922524 ps
CPU time 8.35 seconds
Started Jul 16 05:02:58 PM PDT 24
Finished Jul 16 05:03:07 PM PDT 24
Peak memory 210660 kb
Host smart-1a27902f-27d4-41d3-aa70-6a18846feb5d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760316902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2760316902
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4185518763
Short name T443
Test name
Test status
Simulation time 3986781516 ps
CPU time 30.91 seconds
Started Jul 16 05:02:54 PM PDT 24
Finished Jul 16 05:03:26 PM PDT 24
Peak memory 211264 kb
Host smart-32451908-78b9-417c-8508-23a173c065a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185518763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.4185518763
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3752496669
Short name T403
Test name
Test status
Simulation time 16708084437 ps
CPU time 33.28 seconds
Started Jul 16 05:02:55 PM PDT 24
Finished Jul 16 05:03:29 PM PDT 24
Peak memory 212136 kb
Host smart-de5113e0-f1b6-4289-9866-0423bd18e190
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752496669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3752496669
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3202340218
Short name T361
Test name
Test status
Simulation time 16467401395 ps
CPU time 30.15 seconds
Started Jul 16 05:02:55 PM PDT 24
Finished Jul 16 05:03:26 PM PDT 24
Peak memory 217732 kb
Host smart-97472f85-3afb-4410-95f9-1597ca33e6a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202340218 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3202340218
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2857421168
Short name T423
Test name
Test status
Simulation time 338597053 ps
CPU time 8.19 seconds
Started Jul 16 05:02:53 PM PDT 24
Finished Jul 16 05:03:02 PM PDT 24
Peak memory 210644 kb
Host smart-67b7cfb9-b36a-4cad-94b4-76dacb255ef2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857421168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2857421168
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2316396804
Short name T455
Test name
Test status
Simulation time 18734956583 ps
CPU time 28.43 seconds
Started Jul 16 05:02:56 PM PDT 24
Finished Jul 16 05:03:25 PM PDT 24
Peak memory 210896 kb
Host smart-23e666ac-e598-4aa9-b96a-1fc387161eb7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316396804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2316396804
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3492766683
Short name T358
Test name
Test status
Simulation time 2409021984 ps
CPU time 22.35 seconds
Started Jul 16 05:02:53 PM PDT 24
Finished Jul 16 05:03:16 PM PDT 24
Peak memory 210468 kb
Host smart-3147ca23-602e-4ee4-a0f9-b62e6fbd00fd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492766683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3492766683
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.424983066
Short name T84
Test name
Test status
Simulation time 26384019890 ps
CPU time 194.04 seconds
Started Jul 16 05:02:41 PM PDT 24
Finished Jul 16 05:05:56 PM PDT 24
Peak memory 216024 kb
Host smart-fa31c131-0a78-4b9b-adca-893d93e98747
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424983066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.424983066
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.88707243
Short name T410
Test name
Test status
Simulation time 750500170 ps
CPU time 8.16 seconds
Started Jul 16 05:02:56 PM PDT 24
Finished Jul 16 05:03:05 PM PDT 24
Peak memory 211076 kb
Host smart-a1e89fc8-3fa0-4639-8773-7ab08e242d30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88707243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_same_csr_outstanding.88707243
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2786244371
Short name T438
Test name
Test status
Simulation time 3749138355 ps
CPU time 18.98 seconds
Started Jul 16 05:02:45 PM PDT 24
Finished Jul 16 05:03:05 PM PDT 24
Peak memory 218900 kb
Host smart-9155d80f-6bbb-4cea-921d-d8e0e17eba3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786244371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2786244371
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2330691254
Short name T378
Test name
Test status
Simulation time 1504662759 ps
CPU time 9.06 seconds
Started Jul 16 05:03:26 PM PDT 24
Finished Jul 16 05:03:36 PM PDT 24
Peak memory 216380 kb
Host smart-44219980-5f78-4773-8f65-49d875c843b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330691254 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2330691254
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2752727498
Short name T68
Test name
Test status
Simulation time 4046955825 ps
CPU time 31.18 seconds
Started Jul 16 05:03:28 PM PDT 24
Finished Jul 16 05:03:59 PM PDT 24
Peak memory 211852 kb
Host smart-7523fe79-c79c-4401-94f8-828a68f91d58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752727498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2752727498
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1167478176
Short name T428
Test name
Test status
Simulation time 3178315952 ps
CPU time 26.26 seconds
Started Jul 16 05:03:31 PM PDT 24
Finished Jul 16 05:03:59 PM PDT 24
Peak memory 212084 kb
Host smart-5d16b896-7f1e-4a25-bcb9-a4a44dcd3884
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167478176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1167478176
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3943213551
Short name T380
Test name
Test status
Simulation time 4744660884 ps
CPU time 33.41 seconds
Started Jul 16 05:03:20 PM PDT 24
Finished Jul 16 05:03:55 PM PDT 24
Peak memory 218812 kb
Host smart-8f6300c8-e84d-4760-af88-d99265423a0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943213551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3943213551
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.817368178
Short name T430
Test name
Test status
Simulation time 29127453033 ps
CPU time 25.03 seconds
Started Jul 16 05:03:27 PM PDT 24
Finished Jul 16 05:03:53 PM PDT 24
Peak memory 216784 kb
Host smart-3e4f3a85-b45c-4cf4-8b51-57e6615f3c2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817368178 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.817368178
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1040625212
Short name T402
Test name
Test status
Simulation time 6806719866 ps
CPU time 28.62 seconds
Started Jul 16 05:03:27 PM PDT 24
Finished Jul 16 05:03:56 PM PDT 24
Peak memory 212276 kb
Host smart-35a62a64-b721-47b6-be11-310c39154d63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040625212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1040625212
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.488509305
Short name T106
Test name
Test status
Simulation time 21469539015 ps
CPU time 101.25 seconds
Started Jul 16 05:03:25 PM PDT 24
Finished Jul 16 05:05:07 PM PDT 24
Peak memory 213920 kb
Host smart-b18a242b-0ea4-4ac1-ad27-6a3ceb3f570c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488509305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.488509305
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2064332427
Short name T421
Test name
Test status
Simulation time 688292460 ps
CPU time 8.07 seconds
Started Jul 16 05:03:28 PM PDT 24
Finished Jul 16 05:03:37 PM PDT 24
Peak memory 211476 kb
Host smart-8a9bf34b-7553-4ea1-8f18-362467ac7ca5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064332427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2064332427
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1650288529
Short name T382
Test name
Test status
Simulation time 687871625 ps
CPU time 11.86 seconds
Started Jul 16 05:03:26 PM PDT 24
Finished Jul 16 05:03:39 PM PDT 24
Peak memory 217384 kb
Host smart-fb0cdf28-155d-4be5-a6a4-5f3aed12a9f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650288529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1650288529
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2550156766
Short name T61
Test name
Test status
Simulation time 1039123591 ps
CPU time 159.23 seconds
Started Jul 16 05:03:29 PM PDT 24
Finished Jul 16 05:06:09 PM PDT 24
Peak memory 213804 kb
Host smart-414e9eaa-4eb6-4d9f-8383-86d74d7c80a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550156766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2550156766
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1957725905
Short name T376
Test name
Test status
Simulation time 173405168 ps
CPU time 8.55 seconds
Started Jul 16 05:03:25 PM PDT 24
Finished Jul 16 05:03:34 PM PDT 24
Peak memory 214192 kb
Host smart-a611ae56-9e81-4ed6-8e13-2cb4e6b9d1b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957725905 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1957725905
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2876364611
Short name T387
Test name
Test status
Simulation time 18668727850 ps
CPU time 30.04 seconds
Started Jul 16 05:03:27 PM PDT 24
Finished Jul 16 05:03:57 PM PDT 24
Peak memory 211948 kb
Host smart-cac84e29-5f07-4841-9774-1cde6aeecc71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876364611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2876364611
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.494392843
Short name T437
Test name
Test status
Simulation time 24890003340 ps
CPU time 180.3 seconds
Started Jul 16 05:03:26 PM PDT 24
Finished Jul 16 05:06:27 PM PDT 24
Peak memory 214780 kb
Host smart-7e4062be-31cc-43e2-ad9f-46eb4fb53c39
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494392843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.494392843
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2998912038
Short name T102
Test name
Test status
Simulation time 178093076 ps
CPU time 8.13 seconds
Started Jul 16 05:03:31 PM PDT 24
Finished Jul 16 05:03:41 PM PDT 24
Peak memory 211132 kb
Host smart-ad37802d-d473-4317-9a92-165e9cb0cc60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998912038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2998912038
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1917136467
Short name T386
Test name
Test status
Simulation time 231438716 ps
CPU time 12.52 seconds
Started Jul 16 05:03:30 PM PDT 24
Finished Jul 16 05:03:44 PM PDT 24
Peak memory 217260 kb
Host smart-c06bba4c-1108-401b-977e-3d1f3292bce7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917136467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1917136467
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2249744590
Short name T111
Test name
Test status
Simulation time 6972543092 ps
CPU time 170.24 seconds
Started Jul 16 05:03:27 PM PDT 24
Finished Jul 16 05:06:18 PM PDT 24
Peak memory 214092 kb
Host smart-b92d0864-18c8-4807-a78f-3ac4e6d7a536
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249744590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2249744590
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.617214094
Short name T400
Test name
Test status
Simulation time 14036478596 ps
CPU time 28.36 seconds
Started Jul 16 05:03:30 PM PDT 24
Finished Jul 16 05:04:00 PM PDT 24
Peak memory 218316 kb
Host smart-66f39bf8-bb9e-4bf3-a6aa-5c5515634956
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617214094 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.617214094
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.501430814
Short name T363
Test name
Test status
Simulation time 3844374881 ps
CPU time 30.88 seconds
Started Jul 16 05:03:25 PM PDT 24
Finished Jul 16 05:03:57 PM PDT 24
Peak memory 210608 kb
Host smart-87ebbe35-7260-4d79-bdd5-dca5bd4e784a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501430814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.501430814
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.6497820
Short name T108
Test name
Test status
Simulation time 19466254979 ps
CPU time 65.27 seconds
Started Jul 16 05:03:28 PM PDT 24
Finished Jul 16 05:04:34 PM PDT 24
Peak memory 213936 kb
Host smart-1c990a37-985d-43a1-8bfa-5f56592bcd75
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6497820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pass
thru_mem_tl_intg_err.6497820
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.92189239
Short name T103
Test name
Test status
Simulation time 2026576666 ps
CPU time 18.78 seconds
Started Jul 16 05:03:28 PM PDT 24
Finished Jul 16 05:03:48 PM PDT 24
Peak memory 212420 kb
Host smart-8682654a-b371-4683-862d-d76143843f4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92189239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ct
rl_same_csr_outstanding.92189239
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1077353148
Short name T362
Test name
Test status
Simulation time 6484867851 ps
CPU time 21.14 seconds
Started Jul 16 05:03:30 PM PDT 24
Finished Jul 16 05:03:53 PM PDT 24
Peak memory 218724 kb
Host smart-4b353e3d-d5eb-412f-9fab-c817b63400d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077353148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1077353148
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2889629771
Short name T431
Test name
Test status
Simulation time 11751966990 ps
CPU time 98.98 seconds
Started Jul 16 05:03:31 PM PDT 24
Finished Jul 16 05:05:12 PM PDT 24
Peak memory 213988 kb
Host smart-00956ff9-a2e7-4f82-ac0b-9ff963893630
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889629771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2889629771
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.465410990
Short name T383
Test name
Test status
Simulation time 4121660996 ps
CPU time 30.39 seconds
Started Jul 16 05:03:29 PM PDT 24
Finished Jul 16 05:04:01 PM PDT 24
Peak memory 217892 kb
Host smart-0c358146-ae00-4b14-afbd-608672beb3fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465410990 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.465410990
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.472201661
Short name T105
Test name
Test status
Simulation time 719069330 ps
CPU time 8.36 seconds
Started Jul 16 05:03:31 PM PDT 24
Finished Jul 16 05:03:41 PM PDT 24
Peak memory 210544 kb
Host smart-4d99ff7f-92ff-45df-ba83-67299a958d3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472201661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.472201661
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3548225783
Short name T447
Test name
Test status
Simulation time 2355256780 ps
CPU time 37.63 seconds
Started Jul 16 05:03:30 PM PDT 24
Finished Jul 16 05:04:09 PM PDT 24
Peak memory 213896 kb
Host smart-240b2215-6e96-4684-8759-023a4f8f8b5a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548225783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3548225783
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3901646766
Short name T101
Test name
Test status
Simulation time 2420351570 ps
CPU time 14.13 seconds
Started Jul 16 05:03:29 PM PDT 24
Finished Jul 16 05:03:44 PM PDT 24
Peak memory 211196 kb
Host smart-4ca087a2-0b02-4427-8859-97e434bc8929
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901646766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3901646766
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2245030542
Short name T389
Test name
Test status
Simulation time 1372723304 ps
CPU time 10.97 seconds
Started Jul 16 05:03:29 PM PDT 24
Finished Jul 16 05:03:41 PM PDT 24
Peak memory 217164 kb
Host smart-efe24b33-98ca-4d29-9c03-9e87775f62a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245030542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2245030542
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.545299119
Short name T366
Test name
Test status
Simulation time 386957035 ps
CPU time 9.26 seconds
Started Jul 16 05:03:27 PM PDT 24
Finished Jul 16 05:03:37 PM PDT 24
Peak memory 216464 kb
Host smart-57e1afef-f2df-4056-b70b-7bc537150cc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545299119 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.545299119
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3328144
Short name T87
Test name
Test status
Simulation time 4253004956 ps
CPU time 21.06 seconds
Started Jul 16 05:03:28 PM PDT 24
Finished Jul 16 05:03:50 PM PDT 24
Peak memory 211952 kb
Host smart-a87ad519-e4f8-4430-a957-ef188cfb95cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3328144
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2952192807
Short name T73
Test name
Test status
Simulation time 31690583496 ps
CPU time 90.3 seconds
Started Jul 16 05:03:32 PM PDT 24
Finished Jul 16 05:05:03 PM PDT 24
Peak memory 218936 kb
Host smart-f9c69ceb-8596-4b3d-871f-308caf4a407d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952192807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2952192807
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3965370995
Short name T435
Test name
Test status
Simulation time 1806224180 ps
CPU time 19.17 seconds
Started Jul 16 05:03:27 PM PDT 24
Finished Jul 16 05:03:47 PM PDT 24
Peak memory 212344 kb
Host smart-5e34a67a-02b3-4e4b-9627-c83bab1dcd7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965370995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3965370995
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1363607325
Short name T360
Test name
Test status
Simulation time 4043686408 ps
CPU time 34.99 seconds
Started Jul 16 05:03:30 PM PDT 24
Finished Jul 16 05:04:07 PM PDT 24
Peak memory 217176 kb
Host smart-4dc00245-6255-4628-a477-0774bf0e68ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363607325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1363607325
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2464978778
Short name T113
Test name
Test status
Simulation time 15552834771 ps
CPU time 170.06 seconds
Started Jul 16 05:03:28 PM PDT 24
Finished Jul 16 05:06:19 PM PDT 24
Peak memory 214300 kb
Host smart-91316b2f-6c63-4f39-a3bc-2244e31b0e20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464978778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2464978778
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.85143765
Short name T429
Test name
Test status
Simulation time 15398435185 ps
CPU time 28.35 seconds
Started Jul 16 05:03:27 PM PDT 24
Finished Jul 16 05:03:56 PM PDT 24
Peak memory 218484 kb
Host smart-6bbf3070-b287-45f7-9724-8c91f54b74bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85143765 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.85143765
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3165968462
Short name T424
Test name
Test status
Simulation time 8190953396 ps
CPU time 30.04 seconds
Started Jul 16 05:03:29 PM PDT 24
Finished Jul 16 05:04:00 PM PDT 24
Peak memory 212140 kb
Host smart-4413fead-c235-416b-8312-7b9649fcf6f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165968462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3165968462
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1963161856
Short name T409
Test name
Test status
Simulation time 68314344989 ps
CPU time 132.24 seconds
Started Jul 16 05:03:28 PM PDT 24
Finished Jul 16 05:05:42 PM PDT 24
Peak memory 213848 kb
Host smart-609f50ad-d2ad-49d6-be05-3165658ec326
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963161856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1963161856
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.278269927
Short name T390
Test name
Test status
Simulation time 2297428451 ps
CPU time 15.51 seconds
Started Jul 16 05:03:30 PM PDT 24
Finished Jul 16 05:03:47 PM PDT 24
Peak memory 212212 kb
Host smart-b7075129-4a9a-45d5-8e97-6ffce2f44fe9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278269927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.278269927
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2969757187
Short name T384
Test name
Test status
Simulation time 4249721695 ps
CPU time 36.94 seconds
Started Jul 16 05:03:31 PM PDT 24
Finished Jul 16 05:04:09 PM PDT 24
Peak memory 218480 kb
Host smart-d3c5a26a-b00c-41b6-b0e7-69b62eadfe0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969757187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2969757187
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2130889889
Short name T369
Test name
Test status
Simulation time 10840412411 ps
CPU time 24.89 seconds
Started Jul 16 05:03:30 PM PDT 24
Finished Jul 16 05:03:56 PM PDT 24
Peak memory 217708 kb
Host smart-262cddfa-dae1-493b-a50e-f2a9c519d748
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130889889 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2130889889
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2011210423
Short name T85
Test name
Test status
Simulation time 31818336469 ps
CPU time 20.84 seconds
Started Jul 16 05:03:28 PM PDT 24
Finished Jul 16 05:03:50 PM PDT 24
Peak memory 212004 kb
Host smart-b30f50c7-484c-408d-b0b7-a9bacb95f0bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011210423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2011210423
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3785567831
Short name T74
Test name
Test status
Simulation time 2138761991 ps
CPU time 55.24 seconds
Started Jul 16 05:03:30 PM PDT 24
Finished Jul 16 05:04:27 PM PDT 24
Peak memory 214812 kb
Host smart-9b90cf2a-26ac-4669-a82c-94027b8169a2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785567831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3785567831
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3980709139
Short name T453
Test name
Test status
Simulation time 533853649 ps
CPU time 8.34 seconds
Started Jul 16 05:03:26 PM PDT 24
Finished Jul 16 05:03:35 PM PDT 24
Peak memory 211248 kb
Host smart-8db4a95e-6b33-4a78-86fd-37d69d8976b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980709139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3980709139
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1756684899
Short name T359
Test name
Test status
Simulation time 4940764455 ps
CPU time 23.75 seconds
Started Jul 16 05:03:29 PM PDT 24
Finished Jul 16 05:03:54 PM PDT 24
Peak memory 219008 kb
Host smart-a83b9fd3-139c-4f62-9310-817fe59ef5ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756684899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1756684899
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.750034278
Short name T456
Test name
Test status
Simulation time 3550757396 ps
CPU time 100.42 seconds
Started Jul 16 05:03:31 PM PDT 24
Finished Jul 16 05:05:13 PM PDT 24
Peak memory 213696 kb
Host smart-d67bce13-ac86-4e3d-a5b9-1593362c5687
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750034278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.750034278
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3081299117
Short name T55
Test name
Test status
Simulation time 9600901127 ps
CPU time 22.26 seconds
Started Jul 16 05:03:29 PM PDT 24
Finished Jul 16 05:03:52 PM PDT 24
Peak memory 216872 kb
Host smart-5246bf3f-2967-4732-83a1-1be46e8379eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081299117 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3081299117
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3060423651
Short name T412
Test name
Test status
Simulation time 3075193584 ps
CPU time 16.97 seconds
Started Jul 16 05:03:29 PM PDT 24
Finished Jul 16 05:03:47 PM PDT 24
Peak memory 212064 kb
Host smart-420a7868-7b14-46b5-a8bf-d4ab23624836
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060423651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3060423651
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2333386425
Short name T395
Test name
Test status
Simulation time 8171976659 ps
CPU time 30.12 seconds
Started Jul 16 05:03:31 PM PDT 24
Finished Jul 16 05:04:03 PM PDT 24
Peak memory 212656 kb
Host smart-60385883-9149-4f7a-9b68-917a8fa8a3cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333386425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2333386425
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1605626894
Short name T381
Test name
Test status
Simulation time 3084938688 ps
CPU time 16.23 seconds
Started Jul 16 05:03:31 PM PDT 24
Finished Jul 16 05:03:48 PM PDT 24
Peak memory 217496 kb
Host smart-dd8b4175-4d50-4b75-b673-10b09b92fa0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605626894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1605626894
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2488043796
Short name T115
Test name
Test status
Simulation time 4768854863 ps
CPU time 92.06 seconds
Started Jul 16 05:03:28 PM PDT 24
Finished Jul 16 05:05:01 PM PDT 24
Peak memory 214720 kb
Host smart-1ce3bac6-5dbf-4e54-b8cf-4f535f9765b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488043796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2488043796
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.531533396
Short name T396
Test name
Test status
Simulation time 195207692 ps
CPU time 9.54 seconds
Started Jul 16 05:03:30 PM PDT 24
Finished Jul 16 05:03:41 PM PDT 24
Peak memory 217272 kb
Host smart-97c4c9af-0953-4f3c-bbdb-9f3bf916bed6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531533396 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.531533396
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3258541561
Short name T433
Test name
Test status
Simulation time 2552548646 ps
CPU time 23.4 seconds
Started Jul 16 05:03:32 PM PDT 24
Finished Jul 16 05:03:57 PM PDT 24
Peak memory 212156 kb
Host smart-5dabe809-6bc2-4c75-9a1d-1a481117eec4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258541561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3258541561
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1987661817
Short name T452
Test name
Test status
Simulation time 9844447851 ps
CPU time 37.54 seconds
Started Jul 16 05:03:27 PM PDT 24
Finished Jul 16 05:04:05 PM PDT 24
Peak memory 218808 kb
Host smart-7c668ae0-1ec6-43b8-a978-da80c2016f78
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987661817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1987661817
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2479791936
Short name T392
Test name
Test status
Simulation time 177455994 ps
CPU time 12.02 seconds
Started Jul 16 05:03:31 PM PDT 24
Finished Jul 16 05:03:45 PM PDT 24
Peak memory 212296 kb
Host smart-569215d1-e655-4447-aad2-3ac7a3f3f87c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479791936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2479791936
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3214499431
Short name T371
Test name
Test status
Simulation time 19480641433 ps
CPU time 30.98 seconds
Started Jul 16 05:03:31 PM PDT 24
Finished Jul 16 05:04:03 PM PDT 24
Peak memory 218640 kb
Host smart-f4ee3097-fdad-4ad2-8f5a-f2569c4176b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214499431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3214499431
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3781350218
Short name T117
Test name
Test status
Simulation time 816364259 ps
CPU time 82.38 seconds
Started Jul 16 05:03:31 PM PDT 24
Finished Jul 16 05:04:55 PM PDT 24
Peak memory 213332 kb
Host smart-5d9aafde-375f-4069-8a8b-e6766122992b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781350218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3781350218
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2093997452
Short name T451
Test name
Test status
Simulation time 2892424392 ps
CPU time 16.64 seconds
Started Jul 16 05:02:56 PM PDT 24
Finished Jul 16 05:03:13 PM PDT 24
Peak memory 211444 kb
Host smart-1e2c426b-b142-4516-b4cf-bb4802b68d6f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093997452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2093997452
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2112291435
Short name T454
Test name
Test status
Simulation time 1323847936 ps
CPU time 10.93 seconds
Started Jul 16 05:02:55 PM PDT 24
Finished Jul 16 05:03:06 PM PDT 24
Peak memory 210672 kb
Host smart-2d2a03e6-7a5c-4114-868f-550dbec7ac9a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112291435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2112291435
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.93445989
Short name T422
Test name
Test status
Simulation time 760885175 ps
CPU time 11.86 seconds
Started Jul 16 05:02:55 PM PDT 24
Finished Jul 16 05:03:08 PM PDT 24
Peak memory 210652 kb
Host smart-4ac1c5ae-5e82-43ab-b6ca-2500bfd558c8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93445989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_res
et.93445989
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3179550042
Short name T379
Test name
Test status
Simulation time 710292824 ps
CPU time 8.29 seconds
Started Jul 16 05:02:54 PM PDT 24
Finished Jul 16 05:03:03 PM PDT 24
Peak memory 214032 kb
Host smart-d9bcf40a-b0c7-40c0-95b7-25bc097c6374
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179550042 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3179550042
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.176211457
Short name T92
Test name
Test status
Simulation time 4313631421 ps
CPU time 30.32 seconds
Started Jul 16 05:02:55 PM PDT 24
Finished Jul 16 05:03:26 PM PDT 24
Peak memory 211836 kb
Host smart-b7102487-40ae-41a4-bce2-be17443be4b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176211457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.176211457
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3276738813
Short name T365
Test name
Test status
Simulation time 339042172 ps
CPU time 8.09 seconds
Started Jul 16 05:02:57 PM PDT 24
Finished Jul 16 05:03:06 PM PDT 24
Peak memory 210584 kb
Host smart-158de475-3c97-40d5-b633-b8a2b784252c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276738813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3276738813
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2886870206
Short name T420
Test name
Test status
Simulation time 3835306035 ps
CPU time 29.41 seconds
Started Jul 16 05:02:55 PM PDT 24
Finished Jul 16 05:03:25 PM PDT 24
Peak memory 210648 kb
Host smart-94a0f643-25af-4520-8e85-6efb7795bb51
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886870206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2886870206
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1512800049
Short name T71
Test name
Test status
Simulation time 100534174851 ps
CPU time 133.77 seconds
Started Jul 16 05:02:55 PM PDT 24
Finished Jul 16 05:05:10 PM PDT 24
Peak memory 214772 kb
Host smart-101b26dd-4624-4a09-bd2e-662c5d18269b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512800049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1512800049
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.4016680585
Short name T445
Test name
Test status
Simulation time 185685622 ps
CPU time 12.01 seconds
Started Jul 16 05:02:54 PM PDT 24
Finished Jul 16 05:03:07 PM PDT 24
Peak memory 212172 kb
Host smart-5667c73b-8459-44d3-bcc6-1c846ddb8b47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016680585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.4016680585
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3231952549
Short name T406
Test name
Test status
Simulation time 689297470 ps
CPU time 11.04 seconds
Started Jul 16 05:02:55 PM PDT 24
Finished Jul 16 05:03:07 PM PDT 24
Peak memory 217948 kb
Host smart-7a6906be-094c-4bb0-ab02-86452399fecb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231952549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3231952549
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2750788891
Short name T398
Test name
Test status
Simulation time 5519542002 ps
CPU time 89.93 seconds
Started Jul 16 05:02:55 PM PDT 24
Finished Jul 16 05:04:26 PM PDT 24
Peak memory 213836 kb
Host smart-7e6b7e2d-02d1-4b8b-9585-3225d637708e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750788891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2750788891
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1767137607
Short name T404
Test name
Test status
Simulation time 1843964601 ps
CPU time 14.14 seconds
Started Jul 16 05:02:54 PM PDT 24
Finished Jul 16 05:03:09 PM PDT 24
Peak memory 211360 kb
Host smart-63421e3e-889f-4fd6-b48a-0ccc0c43edb2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767137607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1767137607
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3234843143
Short name T375
Test name
Test status
Simulation time 4473838188 ps
CPU time 15.15 seconds
Started Jul 16 05:02:54 PM PDT 24
Finished Jul 16 05:03:10 PM PDT 24
Peak memory 211316 kb
Host smart-dbc195e9-02d5-404a-836f-2457549a7a5c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234843143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3234843143
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1234534532
Short name T417
Test name
Test status
Simulation time 3857284092 ps
CPU time 33.53 seconds
Started Jul 16 05:02:57 PM PDT 24
Finished Jul 16 05:03:31 PM PDT 24
Peak memory 211524 kb
Host smart-636205e4-4cbb-4747-993f-f9f1b70f09e7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234534532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1234534532
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3684185301
Short name T364
Test name
Test status
Simulation time 17485716836 ps
CPU time 23.97 seconds
Started Jul 16 05:02:55 PM PDT 24
Finished Jul 16 05:03:19 PM PDT 24
Peak memory 217240 kb
Host smart-dc1ad769-e946-4303-afc0-14ef8a8897f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684185301 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3684185301
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3302195038
Short name T393
Test name
Test status
Simulation time 615602198 ps
CPU time 11.02 seconds
Started Jul 16 05:02:54 PM PDT 24
Finished Jul 16 05:03:05 PM PDT 24
Peak memory 210636 kb
Host smart-d3bf7a0a-53a3-4d67-8edc-87b9b6db1b5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302195038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3302195038
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4252834245
Short name T426
Test name
Test status
Simulation time 4339436124 ps
CPU time 29.88 seconds
Started Jul 16 05:02:56 PM PDT 24
Finished Jul 16 05:03:27 PM PDT 24
Peak memory 210504 kb
Host smart-ad3dbdfb-c02d-47e2-8b29-f3ea5b238083
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252834245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.4252834245
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.394142510
Short name T374
Test name
Test status
Simulation time 23858651811 ps
CPU time 22.84 seconds
Started Jul 16 05:02:55 PM PDT 24
Finished Jul 16 05:03:19 PM PDT 24
Peak memory 210880 kb
Host smart-c87148b9-e9e4-4893-8d26-f16538564f52
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394142510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
394142510
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2975889889
Short name T86
Test name
Test status
Simulation time 18066192790 ps
CPU time 82.96 seconds
Started Jul 16 05:02:54 PM PDT 24
Finished Jul 16 05:04:17 PM PDT 24
Peak memory 214916 kb
Host smart-ac46311b-10ae-429e-922c-7c8d3af5247a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975889889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2975889889
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3749419297
Short name T75
Test name
Test status
Simulation time 1081200977 ps
CPU time 12.18 seconds
Started Jul 16 05:03:00 PM PDT 24
Finished Jul 16 05:03:12 PM PDT 24
Peak memory 212200 kb
Host smart-26dbe99e-4036-464c-8d13-3fc44899cb36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749419297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3749419297
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.114274132
Short name T442
Test name
Test status
Simulation time 717736348 ps
CPU time 11.81 seconds
Started Jul 16 05:02:56 PM PDT 24
Finished Jul 16 05:03:09 PM PDT 24
Peak memory 217116 kb
Host smart-c655ce10-4d68-4949-9857-814325873807
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114274132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.114274132
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4139223473
Short name T118
Test name
Test status
Simulation time 48028602340 ps
CPU time 169.66 seconds
Started Jul 16 05:02:54 PM PDT 24
Finished Jul 16 05:05:44 PM PDT 24
Peak memory 213952 kb
Host smart-7aafc2c0-b502-439d-9814-88333b5379da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139223473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.4139223473
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2815151374
Short name T72
Test name
Test status
Simulation time 2521882186 ps
CPU time 16.43 seconds
Started Jul 16 05:02:53 PM PDT 24
Finished Jul 16 05:03:11 PM PDT 24
Peak memory 210612 kb
Host smart-58e01f1d-38d3-4b58-b29e-09eca3d609f2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815151374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2815151374
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1446283114
Short name T370
Test name
Test status
Simulation time 1987905074 ps
CPU time 20.48 seconds
Started Jul 16 05:02:52 PM PDT 24
Finished Jul 16 05:03:13 PM PDT 24
Peak memory 211632 kb
Host smart-3d7a8a38-71cb-4120-829b-b48d8fe11e17
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446283114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1446283114
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.957637012
Short name T414
Test name
Test status
Simulation time 11946719560 ps
CPU time 27.67 seconds
Started Jul 16 05:02:52 PM PDT 24
Finished Jul 16 05:03:21 PM PDT 24
Peak memory 211852 kb
Host smart-80d3387d-45ab-4b35-a737-8cefd04cc607
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957637012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.957637012
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.575733525
Short name T440
Test name
Test status
Simulation time 3784189929 ps
CPU time 29.52 seconds
Started Jul 16 05:02:56 PM PDT 24
Finished Jul 16 05:03:27 PM PDT 24
Peak memory 216792 kb
Host smart-e3674b9b-1ff5-4780-b58d-3ba79df229af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575733525 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.575733525
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1243072849
Short name T70
Test name
Test status
Simulation time 437560551 ps
CPU time 10.8 seconds
Started Jul 16 05:02:55 PM PDT 24
Finished Jul 16 05:03:07 PM PDT 24
Peak memory 210544 kb
Host smart-f842f775-3995-47d9-93f5-aa9abd3e2760
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243072849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1243072849
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2511413097
Short name T373
Test name
Test status
Simulation time 2389484032 ps
CPU time 12.22 seconds
Started Jul 16 05:02:52 PM PDT 24
Finished Jul 16 05:03:05 PM PDT 24
Peak memory 210544 kb
Host smart-abbfd718-e0e6-49b4-b29d-cfea5cc640f8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511413097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2511413097
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3649857951
Short name T446
Test name
Test status
Simulation time 15656434832 ps
CPU time 30.85 seconds
Started Jul 16 05:02:54 PM PDT 24
Finished Jul 16 05:03:25 PM PDT 24
Peak memory 210852 kb
Host smart-f6abb4e2-820b-4ea8-853b-05e1cfd43f73
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649857951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3649857951
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.554861834
Short name T83
Test name
Test status
Simulation time 2118041182 ps
CPU time 43.63 seconds
Started Jul 16 05:02:56 PM PDT 24
Finished Jul 16 05:03:40 PM PDT 24
Peak memory 213780 kb
Host smart-c9dab21e-1a47-4189-bade-b006a2c365e5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554861834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.554861834
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1180681209
Short name T397
Test name
Test status
Simulation time 353378399 ps
CPU time 8.53 seconds
Started Jul 16 05:02:57 PM PDT 24
Finished Jul 16 05:03:06 PM PDT 24
Peak memory 210808 kb
Host smart-2eff8250-289d-43bb-b9dc-313f8a86ad5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180681209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1180681209
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.883766472
Short name T427
Test name
Test status
Simulation time 7784139376 ps
CPU time 35.36 seconds
Started Jul 16 05:02:54 PM PDT 24
Finished Jul 16 05:03:30 PM PDT 24
Peak memory 218896 kb
Host smart-6db8bdd8-a3d6-47d8-9bba-6b51fa6dd2ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883766472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.883766472
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1226110264
Short name T60
Test name
Test status
Simulation time 34725140765 ps
CPU time 172.43 seconds
Started Jul 16 05:02:57 PM PDT 24
Finished Jul 16 05:05:50 PM PDT 24
Peak memory 214376 kb
Host smart-ef0770a8-a329-42f6-88e9-8cfb4a6f325f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226110264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1226110264
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3671203001
Short name T413
Test name
Test status
Simulation time 13721334763 ps
CPU time 26.43 seconds
Started Jul 16 05:03:21 PM PDT 24
Finished Jul 16 05:03:48 PM PDT 24
Peak memory 217960 kb
Host smart-e7f24f71-fe9a-4dcc-b8dd-36545a42137b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671203001 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3671203001
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.4183984849
Short name T104
Test name
Test status
Simulation time 835507460 ps
CPU time 11.26 seconds
Started Jul 16 05:03:18 PM PDT 24
Finished Jul 16 05:03:30 PM PDT 24
Peak memory 210748 kb
Host smart-0a111a4d-1bce-44ec-8b4a-f435cdad46b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183984849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.4183984849
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.378643255
Short name T76
Test name
Test status
Simulation time 48634331577 ps
CPU time 115.33 seconds
Started Jul 16 05:03:18 PM PDT 24
Finished Jul 16 05:05:14 PM PDT 24
Peak memory 214772 kb
Host smart-d0ba482e-dfdb-4c2d-bf1d-6775685fbe85
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378643255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.378643255
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.693740024
Short name T436
Test name
Test status
Simulation time 12260882722 ps
CPU time 23.51 seconds
Started Jul 16 05:03:18 PM PDT 24
Finished Jul 16 05:03:42 PM PDT 24
Peak memory 212712 kb
Host smart-9210367d-df92-44ec-b1e4-1675ed03bdce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693740024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.693740024
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3222520434
Short name T444
Test name
Test status
Simulation time 2168606576 ps
CPU time 15.77 seconds
Started Jul 16 05:03:19 PM PDT 24
Finished Jul 16 05:03:36 PM PDT 24
Peak memory 216436 kb
Host smart-9f000a46-30c9-4cfe-822a-07f541cb807f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222520434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3222520434
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2433490081
Short name T416
Test name
Test status
Simulation time 16552607081 ps
CPU time 104.53 seconds
Started Jul 16 05:03:41 PM PDT 24
Finished Jul 16 05:05:26 PM PDT 24
Peak memory 214080 kb
Host smart-7d31639d-0fae-4c80-aaca-ea2df58f00b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433490081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2433490081
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1974422357
Short name T385
Test name
Test status
Simulation time 847289548 ps
CPU time 8.46 seconds
Started Jul 16 05:03:20 PM PDT 24
Finished Jul 16 05:03:29 PM PDT 24
Peak memory 213976 kb
Host smart-923107c2-9819-4501-a642-41aa45d2056d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974422357 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1974422357
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3235496853
Short name T88
Test name
Test status
Simulation time 4160541544 ps
CPU time 23.55 seconds
Started Jul 16 05:03:19 PM PDT 24
Finished Jul 16 05:03:43 PM PDT 24
Peak memory 211596 kb
Host smart-af77e9db-9b5d-4a97-8633-879fc35b4464
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235496853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3235496853
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1005875746
Short name T64
Test name
Test status
Simulation time 17212405911 ps
CPU time 83.38 seconds
Started Jul 16 05:03:22 PM PDT 24
Finished Jul 16 05:04:46 PM PDT 24
Peak memory 214476 kb
Host smart-335e2895-486d-4973-8ecb-8dbc9c366ff4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005875746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1005875746
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.508892401
Short name T449
Test name
Test status
Simulation time 5470905364 ps
CPU time 19.99 seconds
Started Jul 16 05:03:19 PM PDT 24
Finished Jul 16 05:03:40 PM PDT 24
Peak memory 212804 kb
Host smart-2342d5f7-f0dd-4e4b-a95d-0be44dbc9df9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508892401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.508892401
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3036978459
Short name T394
Test name
Test status
Simulation time 338398633 ps
CPU time 11.82 seconds
Started Jul 16 05:03:20 PM PDT 24
Finished Jul 16 05:03:32 PM PDT 24
Peak memory 217132 kb
Host smart-e368d100-2faf-47be-8b93-46f7a9b4d105
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036978459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3036978459
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1951391331
Short name T119
Test name
Test status
Simulation time 54850488247 ps
CPU time 103.31 seconds
Started Jul 16 05:03:22 PM PDT 24
Finished Jul 16 05:05:06 PM PDT 24
Peak memory 213784 kb
Host smart-01cab59c-af86-47a1-907b-eb17e0921729
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951391331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1951391331
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3515803575
Short name T405
Test name
Test status
Simulation time 2651046158 ps
CPU time 23.43 seconds
Started Jul 16 05:03:19 PM PDT 24
Finished Jul 16 05:03:42 PM PDT 24
Peak memory 219060 kb
Host smart-da1c9432-48ef-4c35-bc76-8e75cc30dff2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515803575 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3515803575
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1428872950
Short name T425
Test name
Test status
Simulation time 9735855640 ps
CPU time 23.7 seconds
Started Jul 16 05:03:19 PM PDT 24
Finished Jul 16 05:03:43 PM PDT 24
Peak memory 211888 kb
Host smart-59306654-37ca-4f23-b8d1-81bb192b8dba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428872950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1428872950
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1338504754
Short name T82
Test name
Test status
Simulation time 28808920286 ps
CPU time 119.83 seconds
Started Jul 16 05:03:22 PM PDT 24
Finished Jul 16 05:05:22 PM PDT 24
Peak memory 213820 kb
Host smart-f5edbffc-5ee7-4d7c-8f7d-cab8a7ead777
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338504754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1338504754
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1387555576
Short name T432
Test name
Test status
Simulation time 22743568032 ps
CPU time 25.95 seconds
Started Jul 16 05:03:21 PM PDT 24
Finished Jul 16 05:03:48 PM PDT 24
Peak memory 212308 kb
Host smart-2f4b59ac-4a2b-48d8-85c8-1db8aff4fe5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387555576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1387555576
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3800456796
Short name T391
Test name
Test status
Simulation time 339239707 ps
CPU time 11.42 seconds
Started Jul 16 05:03:19 PM PDT 24
Finished Jul 16 05:03:32 PM PDT 24
Peak memory 216140 kb
Host smart-9f038d18-11d0-4e83-ae32-060f6dbf6e4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800456796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3800456796
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1652482351
Short name T62
Test name
Test status
Simulation time 5387126428 ps
CPU time 99.4 seconds
Started Jul 16 05:03:19 PM PDT 24
Finished Jul 16 05:04:59 PM PDT 24
Peak memory 213644 kb
Host smart-efc6817b-ab4a-49a2-ab7d-bdb1a63bc415
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652482351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1652482351
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.887385298
Short name T411
Test name
Test status
Simulation time 2914678123 ps
CPU time 24.59 seconds
Started Jul 16 05:03:21 PM PDT 24
Finished Jul 16 05:03:46 PM PDT 24
Peak memory 217056 kb
Host smart-a772bb6d-1a74-4df0-90e8-fe06be1b3324
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887385298 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.887385298
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4134854504
Short name T90
Test name
Test status
Simulation time 3390154620 ps
CPU time 12.29 seconds
Started Jul 16 05:03:22 PM PDT 24
Finished Jul 16 05:03:35 PM PDT 24
Peak memory 211076 kb
Host smart-c8a18278-fcf1-420c-a036-3a8829304800
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134854504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.4134854504
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3682741876
Short name T439
Test name
Test status
Simulation time 16293174448 ps
CPU time 154.12 seconds
Started Jul 16 05:03:20 PM PDT 24
Finished Jul 16 05:05:55 PM PDT 24
Peak memory 215292 kb
Host smart-6844363c-c9f0-4e94-879b-c57eb7300aa5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682741876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3682741876
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1159035182
Short name T407
Test name
Test status
Simulation time 1082593200 ps
CPU time 14.69 seconds
Started Jul 16 05:03:22 PM PDT 24
Finished Jul 16 05:03:37 PM PDT 24
Peak memory 211076 kb
Host smart-e742d613-0c40-453d-8998-120eca422f5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159035182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1159035182
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1497833381
Short name T372
Test name
Test status
Simulation time 11827180805 ps
CPU time 25.04 seconds
Started Jul 16 05:03:20 PM PDT 24
Finished Jul 16 05:03:46 PM PDT 24
Peak memory 218748 kb
Host smart-18f5f5d2-35d9-4f29-898f-c115eb13fc22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497833381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1497833381
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3825141555
Short name T114
Test name
Test status
Simulation time 10009666745 ps
CPU time 166.2 seconds
Started Jul 16 05:03:20 PM PDT 24
Finished Jul 16 05:06:07 PM PDT 24
Peak memory 214180 kb
Host smart-b366c2bf-1c48-4750-85a9-90cc8a01d36e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825141555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3825141555
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2821961952
Short name T419
Test name
Test status
Simulation time 2903961224 ps
CPU time 24.6 seconds
Started Jul 16 05:03:20 PM PDT 24
Finished Jul 16 05:03:45 PM PDT 24
Peak memory 214604 kb
Host smart-591842bf-0593-40a7-bc1b-52216fed1fc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821961952 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2821961952
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1441969025
Short name T415
Test name
Test status
Simulation time 5804039541 ps
CPU time 24.68 seconds
Started Jul 16 05:03:20 PM PDT 24
Finished Jul 16 05:03:46 PM PDT 24
Peak memory 211872 kb
Host smart-67c7f425-e562-4e43-9598-54b31807684c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441969025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1441969025
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3489142487
Short name T399
Test name
Test status
Simulation time 2863874805 ps
CPU time 37.9 seconds
Started Jul 16 05:03:19 PM PDT 24
Finished Jul 16 05:03:58 PM PDT 24
Peak memory 213724 kb
Host smart-d84840a4-f71b-4856-b903-ee357aeaa046
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489142487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3489142487
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.742767535
Short name T418
Test name
Test status
Simulation time 183720653 ps
CPU time 8.33 seconds
Started Jul 16 05:03:20 PM PDT 24
Finished Jul 16 05:03:29 PM PDT 24
Peak memory 211256 kb
Host smart-406ecf9f-7c0a-4bdc-bc17-3f539bfc29fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742767535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.742767535
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.929783684
Short name T116
Test name
Test status
Simulation time 2484390836 ps
CPU time 96.6 seconds
Started Jul 16 05:03:19 PM PDT 24
Finished Jul 16 05:04:57 PM PDT 24
Peak memory 213612 kb
Host smart-b38e79e2-ab22-49fa-bee6-6fbfc1ad4b62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929783684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.929783684
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3821357998
Short name T34
Test name
Test status
Simulation time 24012012285 ps
CPU time 30.17 seconds
Started Jul 16 05:00:45 PM PDT 24
Finished Jul 16 05:01:16 PM PDT 24
Peak memory 217144 kb
Host smart-22733137-f9d4-4b4d-85c9-434a50c11635
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821357998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3821357998
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1436682512
Short name T17
Test name
Test status
Simulation time 255238160048 ps
CPU time 511.51 seconds
Started Jul 16 05:00:44 PM PDT 24
Finished Jul 16 05:09:17 PM PDT 24
Peak memory 226808 kb
Host smart-0f80d5fb-e555-441e-b237-7300805d1355
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436682512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1436682512
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.187002006
Short name T311
Test name
Test status
Simulation time 1081307539 ps
CPU time 17.1 seconds
Started Jul 16 05:00:43 PM PDT 24
Finished Jul 16 05:01:00 PM PDT 24
Peak memory 219168 kb
Host smart-e77111fd-ccbe-459f-8eea-029a13d6b4f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=187002006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.187002006
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.4261643402
Short name T20
Test name
Test status
Simulation time 11187643195 ps
CPU time 133.56 seconds
Started Jul 16 05:00:45 PM PDT 24
Finished Jul 16 05:02:59 PM PDT 24
Peak memory 237520 kb
Host smart-2b2dfb9d-de34-4886-9d95-2acd66e82d2f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261643402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.4261643402
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2741836510
Short name T59
Test name
Test status
Simulation time 6578431930 ps
CPU time 61.86 seconds
Started Jul 16 05:00:45 PM PDT 24
Finished Jul 16 05:01:48 PM PDT 24
Peak memory 216568 kb
Host smart-5d611fa8-ab49-4e50-a01d-21a7eb85670e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741836510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2741836510
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2545511933
Short name T177
Test name
Test status
Simulation time 8327580426 ps
CPU time 85.99 seconds
Started Jul 16 05:00:44 PM PDT 24
Finished Jul 16 05:02:10 PM PDT 24
Peak memory 219428 kb
Host smart-25411ad0-b633-4aca-88fe-fd1d6d4feb06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545511933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2545511933
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1321755149
Short name T284
Test name
Test status
Simulation time 867805291 ps
CPU time 8.35 seconds
Started Jul 16 05:00:45 PM PDT 24
Finished Jul 16 05:00:54 PM PDT 24
Peak memory 217004 kb
Host smart-045a7cef-170d-4fa4-8a6a-b7edf1169b94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321755149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1321755149
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3907242853
Short name T152
Test name
Test status
Simulation time 107566474692 ps
CPU time 292.3 seconds
Started Jul 16 05:00:44 PM PDT 24
Finished Jul 16 05:05:37 PM PDT 24
Peak memory 235812 kb
Host smart-c7399a18-c174-4bdf-80bf-8cd42ff88e7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907242853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3907242853
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2779531098
Short name T334
Test name
Test status
Simulation time 8330558028 ps
CPU time 52.69 seconds
Started Jul 16 05:00:45 PM PDT 24
Finished Jul 16 05:01:38 PM PDT 24
Peak memory 219256 kb
Host smart-877bc990-9c0c-4db4-9055-0a0610054099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779531098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2779531098
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.4217574810
Short name T184
Test name
Test status
Simulation time 364281365 ps
CPU time 10.57 seconds
Started Jul 16 05:00:44 PM PDT 24
Finished Jul 16 05:00:55 PM PDT 24
Peak memory 219208 kb
Host smart-5dd406c4-0b83-452a-9813-b041cd47740a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4217574810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.4217574810
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2748331342
Short name T239
Test name
Test status
Simulation time 1381514359 ps
CPU time 19.83 seconds
Started Jul 16 05:00:47 PM PDT 24
Finished Jul 16 05:01:08 PM PDT 24
Peak memory 216844 kb
Host smart-699bc9f7-22eb-4804-a22c-30885f55d0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748331342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2748331342
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2552305800
Short name T148
Test name
Test status
Simulation time 39458196121 ps
CPU time 85.59 seconds
Started Jul 16 05:00:44 PM PDT 24
Finished Jul 16 05:02:10 PM PDT 24
Peak memory 219276 kb
Host smart-876dda72-9a73-4a1f-8cdc-7b895106d53d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552305800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2552305800
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3946780944
Short name T32
Test name
Test status
Simulation time 4701798486 ps
CPU time 15.05 seconds
Started Jul 16 05:01:16 PM PDT 24
Finished Jul 16 05:01:33 PM PDT 24
Peak memory 213216 kb
Host smart-33cbceb4-2ba9-4e7c-b120-287dabdecc05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946780944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3946780944
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.627149532
Short name T37
Test name
Test status
Simulation time 77937052679 ps
CPU time 701.53 seconds
Started Jul 16 05:01:17 PM PDT 24
Finished Jul 16 05:13:01 PM PDT 24
Peak memory 236576 kb
Host smart-3ba5fbb9-1848-4f04-a72e-e834a581173b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627149532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.627149532
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1867250904
Short name T321
Test name
Test status
Simulation time 181802997 ps
CPU time 10.5 seconds
Started Jul 16 05:01:15 PM PDT 24
Finished Jul 16 05:01:28 PM PDT 24
Peak memory 219240 kb
Host smart-5d120abb-d0d9-4025-965e-047c68820b4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1867250904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1867250904
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2950835180
Short name T127
Test name
Test status
Simulation time 4415349033 ps
CPU time 38.23 seconds
Started Jul 16 05:01:14 PM PDT 24
Finished Jul 16 05:01:54 PM PDT 24
Peak memory 216156 kb
Host smart-7d114d8b-49cc-4f8e-9a3e-f01a0019d664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950835180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2950835180
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3848383863
Short name T125
Test name
Test status
Simulation time 584764870 ps
CPU time 31.99 seconds
Started Jul 16 05:01:18 PM PDT 24
Finished Jul 16 05:01:53 PM PDT 24
Peak memory 219184 kb
Host smart-d0d59a56-1284-488a-8925-50a1eb2e3b14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848383863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3848383863
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.336644299
Short name T250
Test name
Test status
Simulation time 6838393003 ps
CPU time 30.76 seconds
Started Jul 16 05:01:18 PM PDT 24
Finished Jul 16 05:01:52 PM PDT 24
Peak memory 217480 kb
Host smart-40bbd984-45b4-4977-922a-f58750802269
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336644299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.336644299
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.618478894
Short name T207
Test name
Test status
Simulation time 42758856756 ps
CPU time 62.06 seconds
Started Jul 16 05:01:17 PM PDT 24
Finished Jul 16 05:02:22 PM PDT 24
Peak memory 219256 kb
Host smart-06a123af-1cb4-4d5c-ad4b-4d006e6f408b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618478894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.618478894
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1956947312
Short name T145
Test name
Test status
Simulation time 3695225389 ps
CPU time 19.33 seconds
Started Jul 16 05:01:18 PM PDT 24
Finished Jul 16 05:01:40 PM PDT 24
Peak memory 211204 kb
Host smart-f5486bef-a637-4da7-8521-72c5da092253
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1956947312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1956947312
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2355655553
Short name T256
Test name
Test status
Simulation time 1807367236 ps
CPU time 20.32 seconds
Started Jul 16 05:01:17 PM PDT 24
Finished Jul 16 05:01:40 PM PDT 24
Peak memory 216492 kb
Host smart-e7b556b6-e2d4-4c16-9740-75b7d195f8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355655553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2355655553
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1330045464
Short name T181
Test name
Test status
Simulation time 7648142626 ps
CPU time 39.97 seconds
Started Jul 16 05:01:16 PM PDT 24
Finished Jul 16 05:01:58 PM PDT 24
Peak memory 218948 kb
Host smart-ca9d165c-459a-4e33-88c6-3c98ed71b433
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330045464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1330045464
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.4174306526
Short name T261
Test name
Test status
Simulation time 259470871 ps
CPU time 9.99 seconds
Started Jul 16 05:01:18 PM PDT 24
Finished Jul 16 05:01:31 PM PDT 24
Peak memory 217092 kb
Host smart-13d70458-e4e3-40aa-8b6c-420b1dfd3d2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174306526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.4174306526
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1884596903
Short name T139
Test name
Test status
Simulation time 29330227686 ps
CPU time 417.7 seconds
Started Jul 16 05:01:16 PM PDT 24
Finished Jul 16 05:08:15 PM PDT 24
Peak memory 236468 kb
Host smart-3ac62003-9a25-4cb9-87b6-71c67045fa2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884596903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1884596903
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3750109340
Short name T25
Test name
Test status
Simulation time 14269531885 ps
CPU time 40.94 seconds
Started Jul 16 05:01:15 PM PDT 24
Finished Jul 16 05:01:58 PM PDT 24
Peak memory 219080 kb
Host smart-4c3de3fb-dca1-4096-b8e8-b9d9af8d1c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750109340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3750109340
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1839366331
Short name T199
Test name
Test status
Simulation time 3574767240 ps
CPU time 29.52 seconds
Started Jul 16 05:01:17 PM PDT 24
Finished Jul 16 05:01:49 PM PDT 24
Peak memory 211352 kb
Host smart-5a361cc9-28f1-49e0-8290-642d6108d353
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1839366331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1839366331
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3148398014
Short name T323
Test name
Test status
Simulation time 4972663547 ps
CPU time 39.72 seconds
Started Jul 16 05:01:18 PM PDT 24
Finished Jul 16 05:02:00 PM PDT 24
Peak memory 215240 kb
Host smart-fc54f00b-7efa-4399-81dc-602a0f58e014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148398014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3148398014
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3789779784
Short name T320
Test name
Test status
Simulation time 22147316576 ps
CPU time 94.3 seconds
Started Jul 16 05:01:17 PM PDT 24
Finished Jul 16 05:02:54 PM PDT 24
Peak memory 219348 kb
Host smart-cbc9082c-cbc0-4793-a287-ede6e717bd2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789779784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3789779784
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.674584527
Short name T196
Test name
Test status
Simulation time 24042102581 ps
CPU time 28.54 seconds
Started Jul 16 05:01:18 PM PDT 24
Finished Jul 16 05:01:49 PM PDT 24
Peak memory 217492 kb
Host smart-885bdda7-72c5-4b02-b6a5-ed232f53a9d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674584527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.674584527
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2170317273
Short name T156
Test name
Test status
Simulation time 42509593657 ps
CPU time 452.71 seconds
Started Jul 16 05:01:21 PM PDT 24
Finished Jul 16 05:08:57 PM PDT 24
Peak memory 224940 kb
Host smart-699c001c-c5c9-4145-93a8-340b0d48feec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170317273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2170317273
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.618258131
Short name T327
Test name
Test status
Simulation time 12296641254 ps
CPU time 28.09 seconds
Started Jul 16 05:01:19 PM PDT 24
Finished Jul 16 05:01:51 PM PDT 24
Peak memory 212040 kb
Host smart-ff850c3e-c275-4139-b4c2-ab653d417349
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=618258131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.618258131
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2282140116
Short name T226
Test name
Test status
Simulation time 356803245 ps
CPU time 20.66 seconds
Started Jul 16 05:01:17 PM PDT 24
Finished Jul 16 05:01:40 PM PDT 24
Peak memory 216696 kb
Host smart-e25dbd5c-be39-4c9c-9646-1048bac7cee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282140116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2282140116
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1988799554
Short name T205
Test name
Test status
Simulation time 16559457605 ps
CPU time 33.26 seconds
Started Jul 16 05:01:20 PM PDT 24
Finished Jul 16 05:01:56 PM PDT 24
Peak memory 217116 kb
Host smart-b1e7abc9-506a-45c8-b768-14ef2cbc9cdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988799554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1988799554
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.4286310523
Short name T1
Test name
Test status
Simulation time 13496943177 ps
CPU time 186.89 seconds
Started Jul 16 05:01:17 PM PDT 24
Finished Jul 16 05:04:27 PM PDT 24
Peak memory 234916 kb
Host smart-3fbacc76-a4db-4d01-bdf5-052d705f13b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286310523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.4286310523
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1935867792
Short name T214
Test name
Test status
Simulation time 349639544 ps
CPU time 19.42 seconds
Started Jul 16 05:01:19 PM PDT 24
Finished Jul 16 05:01:41 PM PDT 24
Peak memory 219128 kb
Host smart-1a59032b-657c-48ce-aac1-f990b2f38a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935867792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1935867792
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2925358819
Short name T209
Test name
Test status
Simulation time 8671363881 ps
CPU time 21.97 seconds
Started Jul 16 05:01:19 PM PDT 24
Finished Jul 16 05:01:44 PM PDT 24
Peak memory 219208 kb
Host smart-66c107b3-b193-4e6f-8fa7-259c3c16258d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2925358819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2925358819
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3447072626
Short name T187
Test name
Test status
Simulation time 24920621823 ps
CPU time 53.93 seconds
Started Jul 16 05:01:19 PM PDT 24
Finished Jul 16 05:02:15 PM PDT 24
Peak memory 216816 kb
Host smart-5217ae41-d7ee-4be9-b2eb-8c74fe5c565d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447072626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3447072626
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.666089894
Short name T306
Test name
Test status
Simulation time 6949236154 ps
CPU time 84.26 seconds
Started Jul 16 05:01:19 PM PDT 24
Finished Jul 16 05:02:46 PM PDT 24
Peak memory 220216 kb
Host smart-0289f671-5ae6-461d-af33-59e36fff6801
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666089894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.666089894
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.540341189
Short name T36
Test name
Test status
Simulation time 750205548 ps
CPU time 8.24 seconds
Started Jul 16 05:01:24 PM PDT 24
Finished Jul 16 05:01:35 PM PDT 24
Peak memory 217152 kb
Host smart-22fd7d27-5ed6-41fc-8e15-0e9a8730788a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540341189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.540341189
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1978304480
Short name T258
Test name
Test status
Simulation time 52815681278 ps
CPU time 442.01 seconds
Started Jul 16 05:01:27 PM PDT 24
Finished Jul 16 05:08:52 PM PDT 24
Peak memory 236452 kb
Host smart-9d08295c-b371-4c7b-ac22-8543af9635f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978304480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1978304480
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.30503142
Short name T129
Test name
Test status
Simulation time 19219707359 ps
CPU time 46.17 seconds
Started Jul 16 05:01:31 PM PDT 24
Finished Jul 16 05:02:19 PM PDT 24
Peak memory 219280 kb
Host smart-05463de0-5f5f-4102-99b8-4746b73ac78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30503142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.30503142
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1898097510
Short name T303
Test name
Test status
Simulation time 17276368878 ps
CPU time 28.55 seconds
Started Jul 16 05:01:26 PM PDT 24
Finished Jul 16 05:01:57 PM PDT 24
Peak memory 217764 kb
Host smart-5ec7d9a9-fb3f-4b08-a5b0-3c0d28716d47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1898097510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1898097510
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.510333181
Short name T244
Test name
Test status
Simulation time 7209801352 ps
CPU time 68.2 seconds
Started Jul 16 05:01:19 PM PDT 24
Finished Jul 16 05:02:30 PM PDT 24
Peak memory 216448 kb
Host smart-9d9bb0b9-e6af-45fd-a6dc-48e5fed1e430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510333181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.510333181
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2841954024
Short name T345
Test name
Test status
Simulation time 4291418394 ps
CPU time 52.16 seconds
Started Jul 16 05:01:19 PM PDT 24
Finished Jul 16 05:02:14 PM PDT 24
Peak memory 216916 kb
Host smart-f308c4cf-48e3-41fa-b3c9-fb9488f844f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841954024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2841954024
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3635908729
Short name T273
Test name
Test status
Simulation time 17344004153 ps
CPU time 20.34 seconds
Started Jul 16 05:01:25 PM PDT 24
Finished Jul 16 05:01:49 PM PDT 24
Peak memory 217372 kb
Host smart-995f3503-b262-4221-b226-722db8931716
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635908729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3635908729
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2314468534
Short name T206
Test name
Test status
Simulation time 121751986374 ps
CPU time 295.77 seconds
Started Jul 16 05:01:30 PM PDT 24
Finished Jul 16 05:06:28 PM PDT 24
Peak memory 235204 kb
Host smart-a6261769-ff5a-4f29-b03e-1956765cae34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314468534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2314468534
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3095684956
Short name T305
Test name
Test status
Simulation time 61213259687 ps
CPU time 68.62 seconds
Started Jul 16 05:01:29 PM PDT 24
Finished Jul 16 05:02:40 PM PDT 24
Peak memory 219268 kb
Host smart-11783bdb-8362-44f5-82c1-266b716ddd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095684956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3095684956
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2994515362
Short name T342
Test name
Test status
Simulation time 16644728954 ps
CPU time 32.51 seconds
Started Jul 16 05:01:24 PM PDT 24
Finished Jul 16 05:01:58 PM PDT 24
Peak memory 211524 kb
Host smart-994fa5dd-a914-4bfa-b1a1-189189cdef16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2994515362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2994515362
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1093045494
Short name T347
Test name
Test status
Simulation time 7897982958 ps
CPU time 44.16 seconds
Started Jul 16 05:01:27 PM PDT 24
Finished Jul 16 05:02:14 PM PDT 24
Peak memory 216340 kb
Host smart-3831c6a4-7e37-4576-948d-fae80c323dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093045494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1093045494
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.4260375661
Short name T201
Test name
Test status
Simulation time 6653946379 ps
CPU time 39.24 seconds
Started Jul 16 05:01:27 PM PDT 24
Finished Jul 16 05:02:09 PM PDT 24
Peak memory 219244 kb
Host smart-74a691e0-6053-483e-a8b0-a2b8673490ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260375661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.4260375661
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.4214858422
Short name T204
Test name
Test status
Simulation time 17496703160 ps
CPU time 30.58 seconds
Started Jul 16 05:01:27 PM PDT 24
Finished Jul 16 05:02:00 PM PDT 24
Peak memory 217356 kb
Host smart-417d0915-7805-42e0-931b-0c14f55935d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214858422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.4214858422
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1761763301
Short name T285
Test name
Test status
Simulation time 88580943487 ps
CPU time 900.34 seconds
Started Jul 16 05:01:30 PM PDT 24
Finished Jul 16 05:16:32 PM PDT 24
Peak memory 225824 kb
Host smart-4c9a2583-5979-4859-9029-7209249ed72b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761763301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1761763301
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2803680974
Short name T331
Test name
Test status
Simulation time 25160171927 ps
CPU time 61.68 seconds
Started Jul 16 05:01:31 PM PDT 24
Finished Jul 16 05:02:35 PM PDT 24
Peak memory 219240 kb
Host smart-ae6cd805-f04b-4076-a2e3-445b3614c9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803680974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2803680974
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.4194862653
Short name T67
Test name
Test status
Simulation time 930683276 ps
CPU time 16.05 seconds
Started Jul 16 05:01:34 PM PDT 24
Finished Jul 16 05:01:52 PM PDT 24
Peak memory 219168 kb
Host smart-e67610df-26e5-415e-892a-52dd28aaf1b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4194862653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.4194862653
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2009385177
Short name T317
Test name
Test status
Simulation time 23173511391 ps
CPU time 55.81 seconds
Started Jul 16 05:01:26 PM PDT 24
Finished Jul 16 05:02:25 PM PDT 24
Peak memory 216256 kb
Host smart-ff542d53-ce2b-4ea0-9d83-7168d9b3ba19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009385177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2009385177
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.4158179073
Short name T341
Test name
Test status
Simulation time 9905633086 ps
CPU time 58.85 seconds
Started Jul 16 05:01:31 PM PDT 24
Finished Jul 16 05:02:32 PM PDT 24
Peak memory 215760 kb
Host smart-3240d554-8852-4e08-a941-1638b47308d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158179073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.4158179073
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.729466116
Short name T66
Test name
Test status
Simulation time 1500984699 ps
CPU time 8.31 seconds
Started Jul 16 05:01:25 PM PDT 24
Finished Jul 16 05:01:35 PM PDT 24
Peak memory 217060 kb
Host smart-a7d77c42-9a93-4422-80d9-208e41390245
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729466116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.729466116
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2346258711
Short name T123
Test name
Test status
Simulation time 4827243758 ps
CPU time 216.29 seconds
Started Jul 16 05:01:32 PM PDT 24
Finished Jul 16 05:05:11 PM PDT 24
Peak memory 239528 kb
Host smart-e02b8e0b-b677-4d8d-8544-6bef300ab14c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346258711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2346258711
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3466422212
Short name T332
Test name
Test status
Simulation time 25743882715 ps
CPU time 63.5 seconds
Started Jul 16 05:01:26 PM PDT 24
Finished Jul 16 05:02:32 PM PDT 24
Peak memory 219296 kb
Host smart-0ed7a0fd-15d7-47f1-a41e-0bf72dc035ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466422212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3466422212
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3008546021
Short name T144
Test name
Test status
Simulation time 55407065253 ps
CPU time 31.51 seconds
Started Jul 16 05:01:27 PM PDT 24
Finished Jul 16 05:02:01 PM PDT 24
Peak memory 211904 kb
Host smart-044450a7-3dc9-4167-98f7-ba723113f263
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3008546021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3008546021
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.3893146307
Short name T77
Test name
Test status
Simulation time 10541168910 ps
CPU time 59.63 seconds
Started Jul 16 05:01:25 PM PDT 24
Finished Jul 16 05:02:27 PM PDT 24
Peak memory 216384 kb
Host smart-db76507b-9eb0-4152-a8ef-275ea4fb642a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893146307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.3893146307
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1202527231
Short name T99
Test name
Test status
Simulation time 2705973992 ps
CPU time 35.43 seconds
Started Jul 16 05:01:30 PM PDT 24
Finished Jul 16 05:02:07 PM PDT 24
Peak memory 214512 kb
Host smart-3728eb88-9e4e-4c91-a767-52ad08485cdc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202527231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1202527231
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1853204633
Short name T197
Test name
Test status
Simulation time 2992540839 ps
CPU time 25.49 seconds
Started Jul 16 05:01:26 PM PDT 24
Finished Jul 16 05:01:54 PM PDT 24
Peak memory 217096 kb
Host smart-d64e0d05-7614-434b-a03d-142378d047e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853204633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1853204633
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.766146595
Short name T255
Test name
Test status
Simulation time 14332185288 ps
CPU time 59.64 seconds
Started Jul 16 05:01:29 PM PDT 24
Finished Jul 16 05:02:30 PM PDT 24
Peak memory 219232 kb
Host smart-90e41e38-f96d-4188-bc96-1f2f438b0f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766146595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.766146595
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2147443528
Short name T354
Test name
Test status
Simulation time 8614815139 ps
CPU time 21.66 seconds
Started Jul 16 05:01:26 PM PDT 24
Finished Jul 16 05:01:51 PM PDT 24
Peak memory 211472 kb
Host smart-dfa1257b-603c-41a9-9d7e-4aff09951b9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2147443528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2147443528
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3906676108
Short name T16
Test name
Test status
Simulation time 3812002512 ps
CPU time 20.11 seconds
Started Jul 16 05:01:30 PM PDT 24
Finished Jul 16 05:01:52 PM PDT 24
Peak memory 216752 kb
Host smart-de5b6b65-ce82-4feb-aedd-13a89bd1233d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906676108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3906676108
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.601861927
Short name T95
Test name
Test status
Simulation time 3748951110 ps
CPU time 29.36 seconds
Started Jul 16 05:01:26 PM PDT 24
Finished Jul 16 05:01:58 PM PDT 24
Peak memory 219208 kb
Host smart-f2d1e42e-63a2-4c7a-b4d7-3f8968964a1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601861927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.601861927
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.4284767538
Short name T290
Test name
Test status
Simulation time 360722241 ps
CPU time 8.36 seconds
Started Jul 16 05:01:04 PM PDT 24
Finished Jul 16 05:01:13 PM PDT 24
Peak memory 215712 kb
Host smart-196d94f6-31b6-40c9-8ab2-3ff0a5896631
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284767538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.4284767538
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.428239606
Short name T147
Test name
Test status
Simulation time 94615937015 ps
CPU time 466.03 seconds
Started Jul 16 05:00:46 PM PDT 24
Finished Jul 16 05:08:32 PM PDT 24
Peak memory 233856 kb
Host smart-ca7c8968-27ee-4d14-b17c-222ec194a3ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428239606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.428239606
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3653387253
Short name T245
Test name
Test status
Simulation time 33432106596 ps
CPU time 66.84 seconds
Started Jul 16 05:00:59 PM PDT 24
Finished Jul 16 05:02:07 PM PDT 24
Peak memory 220520 kb
Host smart-e42bb5db-2fd4-4ee9-b9df-bd9a3ce634bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653387253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3653387253
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3124434857
Short name T293
Test name
Test status
Simulation time 3604249910 ps
CPU time 20.59 seconds
Started Jul 16 05:00:44 PM PDT 24
Finished Jul 16 05:01:06 PM PDT 24
Peak memory 219228 kb
Host smart-e17d11c8-b7eb-406d-80a7-41f9d189fe09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3124434857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3124434857
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2094543454
Short name T28
Test name
Test status
Simulation time 6422796513 ps
CPU time 135.06 seconds
Started Jul 16 05:01:01 PM PDT 24
Finished Jul 16 05:03:17 PM PDT 24
Peak memory 238196 kb
Host smart-b7bf37b9-100a-4c0b-a7d2-c195081ab7ad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094543454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2094543454
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3668841392
Short name T281
Test name
Test status
Simulation time 371161031 ps
CPU time 20.23 seconds
Started Jul 16 05:00:42 PM PDT 24
Finished Jul 16 05:01:02 PM PDT 24
Peak memory 216100 kb
Host smart-f016159e-8bd5-47ec-a73f-6a1567d3c928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668841392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3668841392
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.354148600
Short name T3
Test name
Test status
Simulation time 4829051649 ps
CPU time 26.54 seconds
Started Jul 16 05:00:44 PM PDT 24
Finished Jul 16 05:01:11 PM PDT 24
Peak memory 214672 kb
Host smart-8ec2aa56-19a1-4242-8dd7-eb55ea5205e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354148600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.354148600
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3535990181
Short name T23
Test name
Test status
Simulation time 5226647074 ps
CPU time 16.82 seconds
Started Jul 16 05:01:30 PM PDT 24
Finished Jul 16 05:01:49 PM PDT 24
Peak memory 217192 kb
Host smart-8f945b16-ba53-4cde-b7f2-50706a5a3c6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535990181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3535990181
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3245079322
Short name T237
Test name
Test status
Simulation time 12600605572 ps
CPU time 207.08 seconds
Started Jul 16 05:01:25 PM PDT 24
Finished Jul 16 05:04:54 PM PDT 24
Peak memory 234784 kb
Host smart-ed95b379-3c05-4e10-9735-81c6d33d008d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245079322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3245079322
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2501958561
Short name T318
Test name
Test status
Simulation time 3771929071 ps
CPU time 42.18 seconds
Started Jul 16 05:01:30 PM PDT 24
Finished Jul 16 05:02:13 PM PDT 24
Peak memory 219180 kb
Host smart-66190143-3c30-4a4a-bf04-fadefc23f023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501958561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2501958561
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2988594762
Short name T135
Test name
Test status
Simulation time 15824731503 ps
CPU time 31.89 seconds
Started Jul 16 05:01:30 PM PDT 24
Finished Jul 16 05:02:04 PM PDT 24
Peak memory 217688 kb
Host smart-053601e7-8f73-4ae1-b7e9-c5dc7719cbe5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2988594762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2988594762
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3469599903
Short name T133
Test name
Test status
Simulation time 8710644896 ps
CPU time 50.39 seconds
Started Jul 16 05:01:30 PM PDT 24
Finished Jul 16 05:02:22 PM PDT 24
Peak memory 216980 kb
Host smart-29848242-a172-4584-9df2-7a676ef5fb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469599903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3469599903
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.472836497
Short name T292
Test name
Test status
Simulation time 193813350 ps
CPU time 14.07 seconds
Started Jul 16 05:01:27 PM PDT 24
Finished Jul 16 05:01:44 PM PDT 24
Peak memory 219220 kb
Host smart-1f157d6b-3bba-41d5-9502-e5fb1627a22f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472836497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.472836497
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3189554206
Short name T198
Test name
Test status
Simulation time 8911963778 ps
CPU time 21.48 seconds
Started Jul 16 05:01:39 PM PDT 24
Finished Jul 16 05:02:04 PM PDT 24
Peak memory 217472 kb
Host smart-9b61fa25-0ee0-4d96-b851-b6f56802dba0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189554206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3189554206
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.4240065772
Short name T134
Test name
Test status
Simulation time 6314331342 ps
CPU time 132.46 seconds
Started Jul 16 05:01:41 PM PDT 24
Finished Jul 16 05:03:56 PM PDT 24
Peak memory 237856 kb
Host smart-b1560c48-7571-4a3b-86ff-0abaf7b8f4fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240065772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.4240065772
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3411636873
Short name T174
Test name
Test status
Simulation time 2747835633 ps
CPU time 19.19 seconds
Started Jul 16 05:01:38 PM PDT 24
Finished Jul 16 05:01:58 PM PDT 24
Peak memory 219280 kb
Host smart-07b29485-0094-451e-8d7e-beebba9374c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411636873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3411636873
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2879623018
Short name T11
Test name
Test status
Simulation time 2336360954 ps
CPU time 14.2 seconds
Started Jul 16 05:01:40 PM PDT 24
Finished Jul 16 05:01:57 PM PDT 24
Peak memory 211676 kb
Host smart-d55b6f77-b9a6-456f-bdaa-f7b663c016ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2879623018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2879623018
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.17523351
Short name T301
Test name
Test status
Simulation time 1173817669 ps
CPU time 29.71 seconds
Started Jul 16 05:01:29 PM PDT 24
Finished Jul 16 05:02:01 PM PDT 24
Peak memory 215888 kb
Host smart-e03d1e06-71dc-4a5d-9bcf-4b6363ecda68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17523351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.17523351
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.81790288
Short name T4
Test name
Test status
Simulation time 8838834856 ps
CPU time 101.44 seconds
Started Jul 16 05:01:37 PM PDT 24
Finished Jul 16 05:03:20 PM PDT 24
Peak memory 219368 kb
Host smart-6168ef0f-7ce8-41a0-9cbc-1227ae7c1154
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81790288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 21.rom_ctrl_stress_all.81790288
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1785128341
Short name T146
Test name
Test status
Simulation time 7545558372 ps
CPU time 28.95 seconds
Started Jul 16 05:01:39 PM PDT 24
Finished Jul 16 05:02:10 PM PDT 24
Peak memory 217388 kb
Host smart-8408aae7-3a44-4d88-945a-f8ddc6b58361
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785128341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1785128341
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3085333500
Short name T218
Test name
Test status
Simulation time 6426971135 ps
CPU time 173.47 seconds
Started Jul 16 05:01:38 PM PDT 24
Finished Jul 16 05:04:33 PM PDT 24
Peak memory 236148 kb
Host smart-a2ab63bf-621b-46d2-bd54-69622d2301c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085333500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3085333500
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.21261059
Short name T276
Test name
Test status
Simulation time 15019538677 ps
CPU time 41.45 seconds
Started Jul 16 05:01:39 PM PDT 24
Finished Jul 16 05:02:24 PM PDT 24
Peak memory 219308 kb
Host smart-bf7dab00-6abd-44ae-8178-5b226e16bbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21261059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.21261059
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.621320642
Short name T246
Test name
Test status
Simulation time 2738088675 ps
CPU time 25.01 seconds
Started Jul 16 05:01:40 PM PDT 24
Finished Jul 16 05:02:08 PM PDT 24
Peak memory 219280 kb
Host smart-8ae18c74-701a-44e9-b4bb-0ef86c421c22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=621320642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.621320642
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1894143072
Short name T161
Test name
Test status
Simulation time 9243440436 ps
CPU time 26.72 seconds
Started Jul 16 05:01:42 PM PDT 24
Finished Jul 16 05:02:11 PM PDT 24
Peak memory 216612 kb
Host smart-5117a8ce-c9b0-41d8-8c4d-16137fc9b61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894143072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1894143072
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.413623677
Short name T7
Test name
Test status
Simulation time 9131631802 ps
CPU time 39.14 seconds
Started Jul 16 05:01:38 PM PDT 24
Finished Jul 16 05:02:20 PM PDT 24
Peak memory 217048 kb
Host smart-d1f25ef1-3276-4c74-9344-405d75344f18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413623677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.413623677
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2458390184
Short name T220
Test name
Test status
Simulation time 1874605133 ps
CPU time 19.53 seconds
Started Jul 16 05:01:40 PM PDT 24
Finished Jul 16 05:02:02 PM PDT 24
Peak memory 217020 kb
Host smart-b38f7a12-e0a2-4424-80e3-db18d922561c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458390184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2458390184
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.985380960
Short name T98
Test name
Test status
Simulation time 46617072397 ps
CPU time 495.42 seconds
Started Jul 16 05:01:41 PM PDT 24
Finished Jul 16 05:10:00 PM PDT 24
Peak memory 240176 kb
Host smart-4b0d952a-4027-4438-b0c9-eddde81cc05c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985380960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.985380960
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3597031448
Short name T128
Test name
Test status
Simulation time 67502211574 ps
CPU time 53.7 seconds
Started Jul 16 05:01:38 PM PDT 24
Finished Jul 16 05:02:35 PM PDT 24
Peak memory 219040 kb
Host smart-1c402442-36b8-473b-a73d-7a347769d079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597031448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3597031448
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1768496402
Short name T302
Test name
Test status
Simulation time 7051601481 ps
CPU time 29.52 seconds
Started Jul 16 05:01:40 PM PDT 24
Finished Jul 16 05:02:12 PM PDT 24
Peak memory 219280 kb
Host smart-a9bbe659-3008-4d7f-b116-66da116e1ecf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1768496402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1768496402
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2102511537
Short name T216
Test name
Test status
Simulation time 15674437247 ps
CPU time 73.96 seconds
Started Jul 16 05:01:39 PM PDT 24
Finished Jul 16 05:02:55 PM PDT 24
Peak memory 216068 kb
Host smart-fa6732a8-e91c-4438-a768-57bb21c5a24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102511537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2102511537
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.126950545
Short name T136
Test name
Test status
Simulation time 10591353625 ps
CPU time 91.78 seconds
Started Jul 16 05:01:38 PM PDT 24
Finished Jul 16 05:03:11 PM PDT 24
Peak memory 219344 kb
Host smart-605ca6bb-04d0-4688-9d57-05a5286b2240
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126950545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.126950545
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1911776036
Short name T200
Test name
Test status
Simulation time 21762174330 ps
CPU time 29.51 seconds
Started Jul 16 05:01:40 PM PDT 24
Finished Jul 16 05:02:13 PM PDT 24
Peak memory 217368 kb
Host smart-74945e89-6f86-4028-9e2e-831d6d1b5f2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911776036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1911776036
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.254036445
Short name T158
Test name
Test status
Simulation time 275863410036 ps
CPU time 362.87 seconds
Started Jul 16 05:01:41 PM PDT 24
Finished Jul 16 05:07:47 PM PDT 24
Peak memory 235008 kb
Host smart-dbc409ce-b46e-496c-be99-ad31210e2d76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254036445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.254036445
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1368979722
Short name T291
Test name
Test status
Simulation time 2535479692 ps
CPU time 19.24 seconds
Started Jul 16 05:01:39 PM PDT 24
Finished Jul 16 05:02:02 PM PDT 24
Peak memory 219296 kb
Host smart-bfb5d8ef-fbf0-4645-9ad3-da1e3972a865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368979722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1368979722
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.896049595
Short name T29
Test name
Test status
Simulation time 992177277 ps
CPU time 16.41 seconds
Started Jul 16 05:01:39 PM PDT 24
Finished Jul 16 05:01:58 PM PDT 24
Peak memory 218388 kb
Host smart-e074c0d0-8108-4ca5-a742-5bcda4a5892c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=896049595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.896049595
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.139648231
Short name T240
Test name
Test status
Simulation time 4228807135 ps
CPU time 44.56 seconds
Started Jul 16 05:01:40 PM PDT 24
Finished Jul 16 05:02:28 PM PDT 24
Peak memory 216468 kb
Host smart-7bed7aa6-e759-4de3-8e12-c1e717584d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139648231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.139648231
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3890246804
Short name T330
Test name
Test status
Simulation time 8401979425 ps
CPU time 47.16 seconds
Started Jul 16 05:01:39 PM PDT 24
Finished Jul 16 05:02:28 PM PDT 24
Peak memory 219384 kb
Host smart-81638683-a7d0-44c2-a749-3ad869c79a71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890246804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3890246804
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2075637402
Short name T304
Test name
Test status
Simulation time 169137858 ps
CPU time 8.47 seconds
Started Jul 16 05:01:56 PM PDT 24
Finished Jul 16 05:02:06 PM PDT 24
Peak memory 217172 kb
Host smart-50cd804e-d4f1-4afb-9a41-383d2d9eccc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075637402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2075637402
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1867507794
Short name T38
Test name
Test status
Simulation time 6377940714 ps
CPU time 190.03 seconds
Started Jul 16 05:01:53 PM PDT 24
Finished Jul 16 05:05:03 PM PDT 24
Peak memory 241272 kb
Host smart-44f3add6-0857-4693-aed3-cdff41f6aa1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867507794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1867507794
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.725215979
Short name T300
Test name
Test status
Simulation time 2951483218 ps
CPU time 37.66 seconds
Started Jul 16 05:01:54 PM PDT 24
Finished Jul 16 05:02:32 PM PDT 24
Peak memory 219252 kb
Host smart-2a75c566-1f90-492f-b0e3-45ef3fc87c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725215979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.725215979
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1026292801
Short name T178
Test name
Test status
Simulation time 11554494419 ps
CPU time 26.29 seconds
Started Jul 16 05:01:55 PM PDT 24
Finished Jul 16 05:02:22 PM PDT 24
Peak memory 219220 kb
Host smart-a56432c3-cfc4-4114-a4ca-21cbd3d3d390
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1026292801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1026292801
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.45342875
Short name T172
Test name
Test status
Simulation time 7272059780 ps
CPU time 82.24 seconds
Started Jul 16 05:01:40 PM PDT 24
Finished Jul 16 05:03:05 PM PDT 24
Peak memory 217408 kb
Host smart-7da420b9-fee0-42fd-a9ef-99235f929f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45342875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.45342875
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3245610369
Short name T279
Test name
Test status
Simulation time 854198734 ps
CPU time 26.63 seconds
Started Jul 16 05:01:40 PM PDT 24
Finished Jul 16 05:02:09 PM PDT 24
Peak memory 217316 kb
Host smart-d4d41e7a-f93b-43f8-87b1-05dcf3a67de3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245610369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3245610369
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1702402303
Short name T185
Test name
Test status
Simulation time 661955208 ps
CPU time 8.72 seconds
Started Jul 16 05:01:53 PM PDT 24
Finished Jul 16 05:02:02 PM PDT 24
Peak memory 213124 kb
Host smart-aa8093a2-4f02-4b12-9b48-17ec65f379c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702402303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1702402303
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2025239965
Short name T48
Test name
Test status
Simulation time 3472638266 ps
CPU time 145.35 seconds
Started Jul 16 05:01:56 PM PDT 24
Finished Jul 16 05:04:22 PM PDT 24
Peak memory 241268 kb
Host smart-a70a1ffd-2069-42cc-9902-d96d1a350b6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025239965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2025239965
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3610536433
Short name T31
Test name
Test status
Simulation time 2693411051 ps
CPU time 35.35 seconds
Started Jul 16 05:01:56 PM PDT 24
Finished Jul 16 05:02:32 PM PDT 24
Peak memory 216168 kb
Host smart-2c5d41ad-a945-4aa8-b1c9-66db36851191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610536433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3610536433
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.810281885
Short name T222
Test name
Test status
Simulation time 1086719515 ps
CPU time 31.6 seconds
Started Jul 16 05:01:54 PM PDT 24
Finished Jul 16 05:02:26 PM PDT 24
Peak memory 219292 kb
Host smart-c81debc7-e905-464e-9893-1c13ff1e29e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810281885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.810281885
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.420380715
Short name T96
Test name
Test status
Simulation time 172424924 ps
CPU time 8.39 seconds
Started Jul 16 05:01:54 PM PDT 24
Finished Jul 16 05:02:04 PM PDT 24
Peak memory 217120 kb
Host smart-c3ee76f1-c3c2-4a15-a2af-7d2fdc78093c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420380715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.420380715
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.76482813
Short name T265
Test name
Test status
Simulation time 204461746091 ps
CPU time 571.38 seconds
Started Jul 16 05:01:54 PM PDT 24
Finished Jul 16 05:11:26 PM PDT 24
Peak memory 234308 kb
Host smart-9a557c52-5e74-4c74-8172-43e7de1e9580
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76482813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_co
rrupt_sig_fatal_chk.76482813
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2371375756
Short name T213
Test name
Test status
Simulation time 38368514482 ps
CPU time 41.61 seconds
Started Jul 16 05:01:54 PM PDT 24
Finished Jul 16 05:02:36 PM PDT 24
Peak memory 219140 kb
Host smart-63cb80fe-c7bb-4524-9813-602588c76f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371375756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2371375756
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1226720632
Short name T63
Test name
Test status
Simulation time 4015980209 ps
CPU time 31.99 seconds
Started Jul 16 05:01:56 PM PDT 24
Finished Jul 16 05:02:29 PM PDT 24
Peak memory 219280 kb
Host smart-b5ed13f4-689c-4a90-9a9f-60315d2a227f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1226720632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1226720632
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.350543972
Short name T9
Test name
Test status
Simulation time 1409159647 ps
CPU time 23.84 seconds
Started Jul 16 05:01:53 PM PDT 24
Finished Jul 16 05:02:17 PM PDT 24
Peak memory 216068 kb
Host smart-a4b470ac-1bf8-4922-8236-714d5e896f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350543972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.350543972
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3717245421
Short name T80
Test name
Test status
Simulation time 1689483463 ps
CPU time 29.17 seconds
Started Jul 16 05:01:55 PM PDT 24
Finished Jul 16 05:02:25 PM PDT 24
Peak memory 219208 kb
Host smart-5916c7e2-cfc6-4d2d-8d88-00be22b64c41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717245421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3717245421
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3514112946
Short name T189
Test name
Test status
Simulation time 176123904 ps
CPU time 8.45 seconds
Started Jul 16 05:02:01 PM PDT 24
Finished Jul 16 05:02:10 PM PDT 24
Peak memory 217176 kb
Host smart-64ba2a9e-bfc6-4994-abf0-dd4981ae9498
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514112946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3514112946
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.938343367
Short name T39
Test name
Test status
Simulation time 86244264606 ps
CPU time 828.2 seconds
Started Jul 16 05:01:59 PM PDT 24
Finished Jul 16 05:15:47 PM PDT 24
Peak memory 219532 kb
Host smart-56149030-0d19-4fd3-81eb-350389fc4906
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938343367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.938343367
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2972083236
Short name T47
Test name
Test status
Simulation time 16473903065 ps
CPU time 63.63 seconds
Started Jul 16 05:01:57 PM PDT 24
Finished Jul 16 05:03:02 PM PDT 24
Peak memory 219260 kb
Host smart-d7ee4441-00ee-4216-9808-e0913e8d9e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972083236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2972083236
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3081884557
Short name T271
Test name
Test status
Simulation time 2324494108 ps
CPU time 23.34 seconds
Started Jul 16 05:01:57 PM PDT 24
Finished Jul 16 05:02:22 PM PDT 24
Peak memory 219320 kb
Host smart-08687aa3-e135-4328-bb39-b774884358e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3081884557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3081884557
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2614011866
Short name T162
Test name
Test status
Simulation time 7565544830 ps
CPU time 77.77 seconds
Started Jul 16 05:01:58 PM PDT 24
Finished Jul 16 05:03:16 PM PDT 24
Peak memory 217972 kb
Host smart-f6061158-6556-4502-b2bf-f039db99edd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614011866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2614011866
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.293018256
Short name T229
Test name
Test status
Simulation time 1307618955 ps
CPU time 38.87 seconds
Started Jul 16 05:01:58 PM PDT 24
Finished Jul 16 05:02:38 PM PDT 24
Peak memory 219256 kb
Host smart-5bc8eb99-988d-418d-b8d4-763ca9502fc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293018256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.rom_ctrl_stress_all.293018256
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.738409892
Short name T54
Test name
Test status
Simulation time 81366756398 ps
CPU time 9522.07 seconds
Started Jul 16 05:01:56 PM PDT 24
Finished Jul 16 07:40:39 PM PDT 24
Peak memory 246460 kb
Host smart-88a210bf-89da-42bd-80fc-0efcf188a350
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738409892 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.738409892
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1083886236
Short name T277
Test name
Test status
Simulation time 170782035 ps
CPU time 8.47 seconds
Started Jul 16 05:01:56 PM PDT 24
Finished Jul 16 05:02:05 PM PDT 24
Peak memory 217216 kb
Host smart-2d4ed97d-6061-40b5-87ff-7480079b5a8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083886236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1083886236
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2543095115
Short name T45
Test name
Test status
Simulation time 68074816728 ps
CPU time 660.66 seconds
Started Jul 16 05:01:55 PM PDT 24
Finished Jul 16 05:12:56 PM PDT 24
Peak memory 240092 kb
Host smart-0d97be77-d697-45f2-a1a6-ad4b749e27c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543095115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2543095115
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3268371709
Short name T357
Test name
Test status
Simulation time 7241496712 ps
CPU time 36.1 seconds
Started Jul 16 05:02:04 PM PDT 24
Finished Jul 16 05:02:41 PM PDT 24
Peak memory 219208 kb
Host smart-67ce39d4-c8fc-4ed3-ab9e-471bf5051de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268371709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3268371709
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1604057477
Short name T294
Test name
Test status
Simulation time 1763407422 ps
CPU time 13.25 seconds
Started Jul 16 05:01:56 PM PDT 24
Finished Jul 16 05:02:10 PM PDT 24
Peak memory 218592 kb
Host smart-3bb73f2f-3249-4f0a-85e1-1f62b9b82fcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1604057477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1604057477
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3743281518
Short name T270
Test name
Test status
Simulation time 8517431765 ps
CPU time 51.97 seconds
Started Jul 16 05:01:55 PM PDT 24
Finished Jul 16 05:02:48 PM PDT 24
Peak memory 216596 kb
Host smart-69899c41-75e5-4b5e-b3a8-eab0a57051aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743281518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3743281518
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1867907317
Short name T333
Test name
Test status
Simulation time 18580641848 ps
CPU time 55.85 seconds
Started Jul 16 05:01:58 PM PDT 24
Finished Jul 16 05:02:55 PM PDT 24
Peak memory 218212 kb
Host smart-11a19039-dea6-4a87-be09-d5c3e8957fb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867907317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1867907317
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3257689580
Short name T322
Test name
Test status
Simulation time 1713961564 ps
CPU time 11.16 seconds
Started Jul 16 05:01:03 PM PDT 24
Finished Jul 16 05:01:15 PM PDT 24
Peak memory 217188 kb
Host smart-d7f556e4-3051-43ec-8e02-ffadad16e581
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257689580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3257689580
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.994841608
Short name T356
Test name
Test status
Simulation time 4487215671 ps
CPU time 140.45 seconds
Started Jul 16 05:01:00 PM PDT 24
Finished Jul 16 05:03:22 PM PDT 24
Peak memory 219480 kb
Host smart-dd88df9e-221a-409b-ad34-03d97a67b325
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994841608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.994841608
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3054912172
Short name T309
Test name
Test status
Simulation time 12302900909 ps
CPU time 26.95 seconds
Started Jul 16 05:01:02 PM PDT 24
Finished Jul 16 05:01:29 PM PDT 24
Peak memory 219288 kb
Host smart-7f594f96-74d5-462c-ac3f-db3c0ebe3230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054912172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3054912172
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2326095265
Short name T160
Test name
Test status
Simulation time 3014113428 ps
CPU time 15.46 seconds
Started Jul 16 05:00:59 PM PDT 24
Finished Jul 16 05:01:16 PM PDT 24
Peak memory 219188 kb
Host smart-6a737f3f-8bc5-4f58-a05d-9deb8483772f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2326095265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2326095265
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3491821739
Short name T21
Test name
Test status
Simulation time 31015992419 ps
CPU time 246.67 seconds
Started Jul 16 05:00:59 PM PDT 24
Finished Jul 16 05:05:07 PM PDT 24
Peak memory 238304 kb
Host smart-4fc364a6-147f-4326-91ff-1565c9d2fc6c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491821739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3491821739
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1542438619
Short name T325
Test name
Test status
Simulation time 9177026790 ps
CPU time 32.71 seconds
Started Jul 16 05:00:59 PM PDT 24
Finished Jul 16 05:01:33 PM PDT 24
Peak memory 217444 kb
Host smart-7d40cc80-b7e6-4985-a061-2b77056ee353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542438619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1542438619
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1203372399
Short name T263
Test name
Test status
Simulation time 10923217536 ps
CPU time 74.36 seconds
Started Jul 16 05:01:00 PM PDT 24
Finished Jul 16 05:02:16 PM PDT 24
Peak memory 219380 kb
Host smart-d2e654b5-e468-4388-9dd6-9b57707e4e06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203372399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1203372399
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.204797435
Short name T314
Test name
Test status
Simulation time 2212325303 ps
CPU time 21.29 seconds
Started Jul 16 05:02:07 PM PDT 24
Finished Jul 16 05:02:29 PM PDT 24
Peak memory 217128 kb
Host smart-af3ffbd4-4fe0-4204-b112-d9b51c48c5bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204797435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.204797435
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.327245898
Short name T338
Test name
Test status
Simulation time 2133934043 ps
CPU time 143.24 seconds
Started Jul 16 05:02:02 PM PDT 24
Finished Jul 16 05:04:26 PM PDT 24
Peak memory 219364 kb
Host smart-2db820b0-9202-4fc0-8c91-1f33db83a4b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327245898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.327245898
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2779395887
Short name T41
Test name
Test status
Simulation time 1375123520 ps
CPU time 18.89 seconds
Started Jul 16 05:02:04 PM PDT 24
Finished Jul 16 05:02:23 PM PDT 24
Peak memory 219216 kb
Host smart-86edcd5d-50a2-46f1-998c-5d98940b596c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779395887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2779395887
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1263797741
Short name T107
Test name
Test status
Simulation time 199185899 ps
CPU time 10.38 seconds
Started Jul 16 05:02:05 PM PDT 24
Finished Jul 16 05:02:17 PM PDT 24
Peak memory 219272 kb
Host smart-ac379d38-df7a-4855-b81e-beb9c261f91b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1263797741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1263797741
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.73249524
Short name T266
Test name
Test status
Simulation time 26589025478 ps
CPU time 45.8 seconds
Started Jul 16 05:01:57 PM PDT 24
Finished Jul 16 05:02:44 PM PDT 24
Peak memory 216128 kb
Host smart-5e20b685-830c-465e-abe8-4fc5d827ea9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73249524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.73249524
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.4083553910
Short name T315
Test name
Test status
Simulation time 7555165412 ps
CPU time 63.46 seconds
Started Jul 16 05:02:02 PM PDT 24
Finished Jul 16 05:03:06 PM PDT 24
Peak memory 219268 kb
Host smart-1325450c-1e62-4ca6-a673-1b92b7315d81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083553910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.4083553910
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1323422203
Short name T157
Test name
Test status
Simulation time 2965264590 ps
CPU time 13.25 seconds
Started Jul 16 05:02:09 PM PDT 24
Finished Jul 16 05:02:23 PM PDT 24
Peak memory 217036 kb
Host smart-311928b2-0d45-4cf1-b718-0a4b0d7285ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323422203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1323422203
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.915322291
Short name T257
Test name
Test status
Simulation time 82140501146 ps
CPU time 342.65 seconds
Started Jul 16 05:02:01 PM PDT 24
Finished Jul 16 05:07:44 PM PDT 24
Peak memory 216952 kb
Host smart-7d272039-91e0-407b-b7dd-07f57a9e0f98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915322291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.915322291
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.504429105
Short name T242
Test name
Test status
Simulation time 13630735997 ps
CPU time 55.17 seconds
Started Jul 16 05:02:04 PM PDT 24
Finished Jul 16 05:03:00 PM PDT 24
Peak memory 219244 kb
Host smart-444948ee-8d65-42df-b978-84e850e04aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504429105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.504429105
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1815559246
Short name T282
Test name
Test status
Simulation time 4322109494 ps
CPU time 33.76 seconds
Started Jul 16 05:02:05 PM PDT 24
Finished Jul 16 05:02:40 PM PDT 24
Peak memory 211720 kb
Host smart-59d08a09-e2d5-40f6-926e-f0d75798638b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1815559246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1815559246
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2430199927
Short name T224
Test name
Test status
Simulation time 1045466983 ps
CPU time 23.77 seconds
Started Jul 16 05:02:08 PM PDT 24
Finished Jul 16 05:02:32 PM PDT 24
Peak memory 216632 kb
Host smart-7304fefe-38ec-41fb-8a38-8303f04d87db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430199927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2430199927
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3698564823
Short name T348
Test name
Test status
Simulation time 23759928113 ps
CPU time 64.99 seconds
Started Jul 16 05:02:05 PM PDT 24
Finished Jul 16 05:03:12 PM PDT 24
Peak memory 219064 kb
Host smart-319108fc-2350-43f1-b56a-3516abb82f02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698564823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3698564823
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3361736967
Short name T165
Test name
Test status
Simulation time 13885692681 ps
CPU time 29.71 seconds
Started Jul 16 05:02:04 PM PDT 24
Finished Jul 16 05:02:35 PM PDT 24
Peak memory 217200 kb
Host smart-f75a846c-1790-47c2-9144-7019f8ba0241
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361736967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3361736967
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2310233957
Short name T155
Test name
Test status
Simulation time 174870432706 ps
CPU time 360.56 seconds
Started Jul 16 05:02:05 PM PDT 24
Finished Jul 16 05:08:06 PM PDT 24
Peak memory 219472 kb
Host smart-e11ce6e3-8b6b-4cd6-a304-34b4598f7231
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310233957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2310233957
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.4129469079
Short name T355
Test name
Test status
Simulation time 33393661513 ps
CPU time 65.97 seconds
Started Jul 16 05:02:06 PM PDT 24
Finished Jul 16 05:03:13 PM PDT 24
Peak memory 219188 kb
Host smart-43a7bccc-2d1b-4fb2-a7df-1375b0325b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129469079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.4129469079
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.402039091
Short name T269
Test name
Test status
Simulation time 2229888885 ps
CPU time 22.66 seconds
Started Jul 16 05:02:09 PM PDT 24
Finished Jul 16 05:02:32 PM PDT 24
Peak memory 211360 kb
Host smart-cb849f5e-c645-4949-aee9-abb87276ebcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=402039091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.402039091
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.973861981
Short name T132
Test name
Test status
Simulation time 43216416968 ps
CPU time 45.04 seconds
Started Jul 16 05:02:03 PM PDT 24
Finished Jul 16 05:02:49 PM PDT 24
Peak memory 217116 kb
Host smart-97dfe0d2-788d-497e-b340-ee73366ee14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973861981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.973861981
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.4149835238
Short name T275
Test name
Test status
Simulation time 40116823870 ps
CPU time 63.66 seconds
Started Jul 16 05:02:07 PM PDT 24
Finished Jul 16 05:03:11 PM PDT 24
Peak memory 217708 kb
Host smart-d7a5bfd6-0ed1-4cce-8fb6-d1491a3dea6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149835238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.4149835238
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.875297183
Short name T121
Test name
Test status
Simulation time 574966661 ps
CPU time 11.95 seconds
Started Jul 16 05:02:06 PM PDT 24
Finished Jul 16 05:02:19 PM PDT 24
Peak memory 216984 kb
Host smart-90f56611-a605-49ca-a1ce-739624934b37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875297183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.875297183
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.800744923
Short name T221
Test name
Test status
Simulation time 203055536918 ps
CPU time 498.56 seconds
Started Jul 16 05:02:03 PM PDT 24
Finished Jul 16 05:10:22 PM PDT 24
Peak memory 234628 kb
Host smart-65fda4cb-6833-4caf-8f0c-8bac99c5569d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800744923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.800744923
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2407897910
Short name T316
Test name
Test status
Simulation time 1194086365 ps
CPU time 26.9 seconds
Started Jul 16 05:02:06 PM PDT 24
Finished Jul 16 05:02:34 PM PDT 24
Peak memory 219296 kb
Host smart-682cebfd-1b14-4042-9e3d-30b7f7862175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407897910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2407897910
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2589702102
Short name T150
Test name
Test status
Simulation time 4055037737 ps
CPU time 31.78 seconds
Started Jul 16 05:02:05 PM PDT 24
Finished Jul 16 05:02:37 PM PDT 24
Peak memory 219280 kb
Host smart-260e5de3-c2f8-45f3-8f70-af0df1d1c12a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2589702102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2589702102
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1262513516
Short name T344
Test name
Test status
Simulation time 1731014322 ps
CPU time 31.94 seconds
Started Jul 16 05:02:05 PM PDT 24
Finished Jul 16 05:02:38 PM PDT 24
Peak memory 215664 kb
Host smart-4fe90237-28d4-4cdf-8811-1f851efbee15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262513516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1262513516
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2902677156
Short name T6
Test name
Test status
Simulation time 14353229484 ps
CPU time 47.73 seconds
Started Jul 16 05:02:02 PM PDT 24
Finished Jul 16 05:02:51 PM PDT 24
Peak memory 221124 kb
Host smart-03bb5357-db27-42a4-8650-faf1486df3f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902677156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2902677156
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.535366101
Short name T14
Test name
Test status
Simulation time 903684848013 ps
CPU time 4107.5 seconds
Started Jul 16 05:02:04 PM PDT 24
Finished Jul 16 06:10:32 PM PDT 24
Peak memory 250264 kb
Host smart-d6d5f47c-0104-4f91-b339-f79a227c65a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535366101 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.535366101
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1868009244
Short name T253
Test name
Test status
Simulation time 3470975416 ps
CPU time 27.22 seconds
Started Jul 16 05:02:07 PM PDT 24
Finished Jul 16 05:02:35 PM PDT 24
Peak memory 217104 kb
Host smart-d8a1f024-2525-4974-992a-2923effc03e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868009244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1868009244
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.35397586
Short name T262
Test name
Test status
Simulation time 52889590806 ps
CPU time 510.85 seconds
Started Jul 16 05:02:03 PM PDT 24
Finished Jul 16 05:10:35 PM PDT 24
Peak memory 233776 kb
Host smart-d7c8f549-c18f-4737-b09e-d7f0d1d03be3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35397586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_co
rrupt_sig_fatal_chk.35397586
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3419306014
Short name T202
Test name
Test status
Simulation time 35924702352 ps
CPU time 61.57 seconds
Started Jul 16 05:02:07 PM PDT 24
Finished Jul 16 05:03:09 PM PDT 24
Peak memory 219264 kb
Host smart-7d396306-1ad7-4947-a005-3c118c638b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419306014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3419306014
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.4072971133
Short name T232
Test name
Test status
Simulation time 8246292663 ps
CPU time 23.86 seconds
Started Jul 16 05:02:05 PM PDT 24
Finished Jul 16 05:02:30 PM PDT 24
Peak memory 211120 kb
Host smart-631e458a-8fdb-4853-a07b-c46f1dcf4a7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4072971133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.4072971133
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3331830509
Short name T272
Test name
Test status
Simulation time 5297062577 ps
CPU time 43.01 seconds
Started Jul 16 05:02:05 PM PDT 24
Finished Jul 16 05:02:49 PM PDT 24
Peak memory 216356 kb
Host smart-5bd4737a-465d-473f-8548-65cb8e677f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331830509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3331830509
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.261378077
Short name T8
Test name
Test status
Simulation time 2177966858 ps
CPU time 29.44 seconds
Started Jul 16 05:02:05 PM PDT 24
Finished Jul 16 05:02:36 PM PDT 24
Peak memory 219252 kb
Host smart-b6e5b47b-88b8-4afe-869a-9d2070874475
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261378077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.261378077
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.3329725419
Short name T49
Test name
Test status
Simulation time 327195174397 ps
CPU time 1029.04 seconds
Started Jul 16 05:02:08 PM PDT 24
Finished Jul 16 05:19:18 PM PDT 24
Peak memory 235816 kb
Host smart-40d971ca-c724-4cf7-90b2-53d275021852
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329725419 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.3329725419
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1240073995
Short name T153
Test name
Test status
Simulation time 3410657138 ps
CPU time 26.83 seconds
Started Jul 16 05:02:09 PM PDT 24
Finished Jul 16 05:02:37 PM PDT 24
Peak memory 217068 kb
Host smart-115c0fd5-6b5c-4c94-a38a-9771f9afa64d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240073995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1240073995
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3952585151
Short name T33
Test name
Test status
Simulation time 196629259330 ps
CPU time 654.42 seconds
Started Jul 16 05:02:04 PM PDT 24
Finished Jul 16 05:13:00 PM PDT 24
Peak memory 224804 kb
Host smart-c30809bd-71dd-46fc-b452-5229a06a3ac0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952585151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3952585151
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.691444806
Short name T42
Test name
Test status
Simulation time 346341747 ps
CPU time 18.71 seconds
Started Jul 16 05:02:03 PM PDT 24
Finished Jul 16 05:02:23 PM PDT 24
Peak memory 219252 kb
Host smart-bbc3dd62-397a-4934-a7b4-d3880eef0dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691444806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.691444806
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2457316314
Short name T260
Test name
Test status
Simulation time 2668235728 ps
CPU time 14.76 seconds
Started Jul 16 05:02:04 PM PDT 24
Finished Jul 16 05:02:19 PM PDT 24
Peak memory 219360 kb
Host smart-1adbc4d4-d0c1-4a4c-bc24-81164635fdd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2457316314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2457316314
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.926664768
Short name T154
Test name
Test status
Simulation time 8310080917 ps
CPU time 34.25 seconds
Started Jul 16 05:02:06 PM PDT 24
Finished Jul 16 05:02:41 PM PDT 24
Peak memory 217684 kb
Host smart-35047445-8f08-40a1-a510-7c932ae6b840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926664768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.926664768
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.402227674
Short name T44
Test name
Test status
Simulation time 65940466823 ps
CPU time 62.18 seconds
Started Jul 16 05:02:06 PM PDT 24
Finished Jul 16 05:03:09 PM PDT 24
Peak memory 218228 kb
Host smart-46821a7c-480e-4979-91d8-3485f881d6b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402227674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.402227674
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1690620309
Short name T10
Test name
Test status
Simulation time 10968151928 ps
CPU time 32.83 seconds
Started Jul 16 05:02:14 PM PDT 24
Finished Jul 16 05:02:48 PM PDT 24
Peak memory 217368 kb
Host smart-e0d7ce59-610f-4ee7-b4ec-d91b38de3e15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690620309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1690620309
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.4268035052
Short name T40
Test name
Test status
Simulation time 19258042429 ps
CPU time 275.86 seconds
Started Jul 16 05:02:18 PM PDT 24
Finished Jul 16 05:06:55 PM PDT 24
Peak memory 217268 kb
Host smart-94d63eb3-0a94-4280-8d33-13d1b9c608d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268035052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.4268035052
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.4127332648
Short name T298
Test name
Test status
Simulation time 332521711 ps
CPU time 19.28 seconds
Started Jul 16 05:02:16 PM PDT 24
Finished Jul 16 05:02:37 PM PDT 24
Peak memory 219232 kb
Host smart-20952378-51ba-42af-99fa-d1d340fc906c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127332648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.4127332648
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1777766985
Short name T274
Test name
Test status
Simulation time 8286694243 ps
CPU time 18.86 seconds
Started Jul 16 05:02:19 PM PDT 24
Finished Jul 16 05:02:39 PM PDT 24
Peak memory 211752 kb
Host smart-d0c4b029-bb33-461f-ad29-433cad1ef387
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1777766985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1777766985
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.229871037
Short name T15
Test name
Test status
Simulation time 7705272455 ps
CPU time 63.23 seconds
Started Jul 16 05:02:05 PM PDT 24
Finished Jul 16 05:03:10 PM PDT 24
Peak memory 217104 kb
Host smart-c02b7dbd-0c87-4531-98c2-e6c15ed87046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229871037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.229871037
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.246706573
Short name T319
Test name
Test status
Simulation time 8703053493 ps
CPU time 80.83 seconds
Started Jul 16 05:02:03 PM PDT 24
Finished Jul 16 05:03:25 PM PDT 24
Peak memory 220708 kb
Host smart-08103644-e349-4a64-a8ec-a9720de9edbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246706573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.246706573
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3469843106
Short name T24
Test name
Test status
Simulation time 3701492639 ps
CPU time 27 seconds
Started Jul 16 05:02:20 PM PDT 24
Finished Jul 16 05:02:48 PM PDT 24
Peak memory 217192 kb
Host smart-5df5b35a-5fcb-4131-8667-fdc3906a05ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469843106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3469843106
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1659524590
Short name T234
Test name
Test status
Simulation time 1959328777 ps
CPU time 122.48 seconds
Started Jul 16 05:02:16 PM PDT 24
Finished Jul 16 05:04:20 PM PDT 24
Peak memory 219368 kb
Host smart-694a1590-d4f7-4daa-b3eb-d66f24a22f00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659524590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1659524590
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.843774582
Short name T5
Test name
Test status
Simulation time 1516460652 ps
CPU time 29.8 seconds
Started Jul 16 05:02:15 PM PDT 24
Finished Jul 16 05:02:46 PM PDT 24
Peak memory 219224 kb
Host smart-576e9af2-78c9-46b8-a6d6-cc351f2772af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843774582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.843774582
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.643018371
Short name T267
Test name
Test status
Simulation time 6726594624 ps
CPU time 16.83 seconds
Started Jul 16 05:02:21 PM PDT 24
Finished Jul 16 05:02:38 PM PDT 24
Peak memory 211464 kb
Host smart-11e9f104-9590-4549-8d25-440d51f06c02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=643018371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.643018371
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1807304121
Short name T122
Test name
Test status
Simulation time 1815048555 ps
CPU time 20.62 seconds
Started Jul 16 05:02:14 PM PDT 24
Finished Jul 16 05:02:36 PM PDT 24
Peak memory 216936 kb
Host smart-bfeabbef-7217-4fec-abf3-1791b87e6aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807304121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1807304121
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1903880031
Short name T142
Test name
Test status
Simulation time 38096815141 ps
CPU time 42.15 seconds
Started Jul 16 05:02:18 PM PDT 24
Finished Jul 16 05:03:01 PM PDT 24
Peak memory 214660 kb
Host smart-25dfdbdf-6b0a-4b17-b049-a1dd76012503
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903880031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1903880031
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.4106370411
Short name T138
Test name
Test status
Simulation time 6422836954 ps
CPU time 24.04 seconds
Started Jul 16 05:02:16 PM PDT 24
Finished Jul 16 05:02:41 PM PDT 24
Peak memory 217372 kb
Host smart-e48632f5-d51d-4080-9a90-560b7187709c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106370411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.4106370411
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1179666465
Short name T241
Test name
Test status
Simulation time 33468151565 ps
CPU time 299.43 seconds
Started Jul 16 05:02:21 PM PDT 24
Finished Jul 16 05:07:21 PM PDT 24
Peak memory 229288 kb
Host smart-79184631-6db0-4ce4-b197-6653ad04c0b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179666465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1179666465
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3599119281
Short name T278
Test name
Test status
Simulation time 1102175664 ps
CPU time 19.2 seconds
Started Jul 16 05:02:16 PM PDT 24
Finished Jul 16 05:02:36 PM PDT 24
Peak memory 219176 kb
Host smart-90442242-2c5e-4f7c-94f6-8c0662eed71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599119281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3599119281
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3200159216
Short name T183
Test name
Test status
Simulation time 696809712 ps
CPU time 10.12 seconds
Started Jul 16 05:02:16 PM PDT 24
Finished Jul 16 05:02:28 PM PDT 24
Peak memory 219208 kb
Host smart-f664f987-a262-4d66-a76e-05d7847db13c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3200159216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3200159216
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2522306533
Short name T124
Test name
Test status
Simulation time 1383642215 ps
CPU time 20.11 seconds
Started Jul 16 05:02:16 PM PDT 24
Finished Jul 16 05:02:38 PM PDT 24
Peak memory 216440 kb
Host smart-6736738d-11ac-4925-9173-51411f308bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522306533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2522306533
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1515878047
Short name T353
Test name
Test status
Simulation time 18571448316 ps
CPU time 78.1 seconds
Started Jul 16 05:02:17 PM PDT 24
Finished Jul 16 05:03:36 PM PDT 24
Peak memory 219276 kb
Host smart-6c7c94f8-cbd9-4fcf-8024-e597338002dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515878047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1515878047
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.273508813
Short name T217
Test name
Test status
Simulation time 2682002903 ps
CPU time 24.01 seconds
Started Jul 16 05:02:20 PM PDT 24
Finished Jul 16 05:02:44 PM PDT 24
Peak memory 217024 kb
Host smart-fd48bd36-0788-419f-ab26-4fa6176310ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273508813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.273508813
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3358597560
Short name T195
Test name
Test status
Simulation time 4301771823 ps
CPU time 154.99 seconds
Started Jul 16 05:02:25 PM PDT 24
Finished Jul 16 05:05:00 PM PDT 24
Peak memory 239980 kb
Host smart-c5ecdcf8-41c2-476a-a05d-fe62fb4957d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358597560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3358597560
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.4038788982
Short name T352
Test name
Test status
Simulation time 6177311729 ps
CPU time 29.54 seconds
Started Jul 16 05:02:15 PM PDT 24
Finished Jul 16 05:02:46 PM PDT 24
Peak memory 219332 kb
Host smart-195ebd90-324e-4009-ac1b-31c4e7331a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038788982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.4038788982
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1961012507
Short name T329
Test name
Test status
Simulation time 4123062271 ps
CPU time 21.84 seconds
Started Jul 16 05:02:16 PM PDT 24
Finished Jul 16 05:02:40 PM PDT 24
Peak memory 219276 kb
Host smart-b3f66228-fbc9-4654-8bc7-78c7d5d7d3b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1961012507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1961012507
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.3185911361
Short name T58
Test name
Test status
Simulation time 426587562 ps
CPU time 20.37 seconds
Started Jul 16 05:02:18 PM PDT 24
Finished Jul 16 05:02:39 PM PDT 24
Peak memory 216128 kb
Host smart-2a31ff43-ed60-4bf8-b360-6b7b4ae99b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185911361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.3185911361
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1565728019
Short name T343
Test name
Test status
Simulation time 12337512147 ps
CPU time 108.32 seconds
Started Jul 16 05:02:16 PM PDT 24
Finished Jul 16 05:04:05 PM PDT 24
Peak memory 219336 kb
Host smart-566e34e9-753e-41cd-b6ba-ef8089317dc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565728019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1565728019
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2568578992
Short name T208
Test name
Test status
Simulation time 172836384 ps
CPU time 8.32 seconds
Started Jul 16 05:01:03 PM PDT 24
Finished Jul 16 05:01:12 PM PDT 24
Peak memory 213112 kb
Host smart-b6476eea-2e88-4b14-b089-26c1f417d257
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568578992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2568578992
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2767363461
Short name T254
Test name
Test status
Simulation time 2539065672 ps
CPU time 162.08 seconds
Started Jul 16 05:01:04 PM PDT 24
Finished Jul 16 05:03:47 PM PDT 24
Peak memory 219016 kb
Host smart-4df4ec53-8a57-41fb-ad9c-cbcb9930eaf6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767363461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2767363461
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3659579572
Short name T249
Test name
Test status
Simulation time 16339107530 ps
CPU time 63.63 seconds
Started Jul 16 05:01:02 PM PDT 24
Finished Jul 16 05:02:07 PM PDT 24
Peak memory 219280 kb
Host smart-9d3d7af2-0d56-4ed1-b964-7c79d834ae9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659579572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3659579572
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2768412079
Short name T340
Test name
Test status
Simulation time 863329136 ps
CPU time 10.19 seconds
Started Jul 16 05:01:04 PM PDT 24
Finished Jul 16 05:01:15 PM PDT 24
Peak memory 219264 kb
Host smart-c2d00eb4-6f0d-4d99-95db-399018157e3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2768412079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2768412079
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.522459600
Short name T27
Test name
Test status
Simulation time 1568551752 ps
CPU time 234.98 seconds
Started Jul 16 05:01:02 PM PDT 24
Finished Jul 16 05:04:58 PM PDT 24
Peak memory 237132 kb
Host smart-3b620589-ec98-4b05-9d72-8f5ebd9ba9c9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522459600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.522459600
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2015712242
Short name T151
Test name
Test status
Simulation time 22562253598 ps
CPU time 63.55 seconds
Started Jul 16 05:01:02 PM PDT 24
Finished Jul 16 05:02:07 PM PDT 24
Peak memory 217240 kb
Host smart-502929cc-fa65-4b0b-a117-afcbe59e5933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015712242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2015712242
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.810482462
Short name T168
Test name
Test status
Simulation time 800693135 ps
CPU time 17.92 seconds
Started Jul 16 05:01:03 PM PDT 24
Finished Jul 16 05:01:21 PM PDT 24
Peak memory 219168 kb
Host smart-901dfbd9-38c1-46a7-b291-37fcd35cff8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810482462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.810482462
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2342686218
Short name T51
Test name
Test status
Simulation time 23128789211 ps
CPU time 916.46 seconds
Started Jul 16 05:01:01 PM PDT 24
Finished Jul 16 05:16:18 PM PDT 24
Peak memory 233788 kb
Host smart-4aafcdf3-de95-4f2b-95bf-20427e126181
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342686218 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.2342686218
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.192213513
Short name T210
Test name
Test status
Simulation time 688118754 ps
CPU time 8.61 seconds
Started Jul 16 05:02:18 PM PDT 24
Finished Jul 16 05:02:27 PM PDT 24
Peak memory 217080 kb
Host smart-b43e7c6e-ef4f-4c54-a388-222da73deb59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192213513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.192213513
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1420567572
Short name T167
Test name
Test status
Simulation time 496574859671 ps
CPU time 451.63 seconds
Started Jul 16 05:02:21 PM PDT 24
Finished Jul 16 05:09:53 PM PDT 24
Peak memory 233920 kb
Host smart-52537b59-1455-4e9c-888d-493450064427
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420567572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1420567572
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.544311711
Short name T313
Test name
Test status
Simulation time 1222463662 ps
CPU time 18.75 seconds
Started Jul 16 05:02:15 PM PDT 24
Finished Jul 16 05:02:35 PM PDT 24
Peak memory 219252 kb
Host smart-c11a7d28-f7fc-4042-8aac-0fa1d8fd8d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544311711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.544311711
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.918228742
Short name T211
Test name
Test status
Simulation time 8163857715 ps
CPU time 34.44 seconds
Started Jul 16 05:02:15 PM PDT 24
Finished Jul 16 05:02:50 PM PDT 24
Peak memory 219236 kb
Host smart-6cfbb11d-19d2-41ae-92f9-6f51d3904a72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=918228742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.918228742
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1129900897
Short name T324
Test name
Test status
Simulation time 1424051953 ps
CPU time 19.69 seconds
Started Jul 16 05:02:19 PM PDT 24
Finished Jul 16 05:02:39 PM PDT 24
Peak memory 215856 kb
Host smart-f5e2cae8-b761-4313-8a27-942d8916409c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129900897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1129900897
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1353416426
Short name T190
Test name
Test status
Simulation time 21076523626 ps
CPU time 44.99 seconds
Started Jul 16 05:02:20 PM PDT 24
Finished Jul 16 05:03:05 PM PDT 24
Peak memory 212092 kb
Host smart-49fa29c1-fb43-4d0e-a83b-cd41404933f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353416426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1353416426
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.3783135705
Short name T52
Test name
Test status
Simulation time 40422692523 ps
CPU time 1484.77 seconds
Started Jul 16 05:02:20 PM PDT 24
Finished Jul 16 05:27:06 PM PDT 24
Peak memory 235772 kb
Host smart-c25c453c-187a-42a5-b402-6ca33f1c092f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783135705 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.3783135705
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2062992681
Short name T268
Test name
Test status
Simulation time 4088271402 ps
CPU time 19.84 seconds
Started Jul 16 05:02:32 PM PDT 24
Finished Jul 16 05:02:52 PM PDT 24
Peak memory 217184 kb
Host smart-291891fa-0173-44e9-9e5d-53c476307df5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062992681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2062992681
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3531325370
Short name T297
Test name
Test status
Simulation time 59182103378 ps
CPU time 512.15 seconds
Started Jul 16 05:02:15 PM PDT 24
Finished Jul 16 05:10:48 PM PDT 24
Peak memory 219720 kb
Host smart-425f90c1-9658-4c50-bd8e-e0799528dfd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531325370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3531325370
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1852011336
Short name T310
Test name
Test status
Simulation time 9697968303 ps
CPU time 48.49 seconds
Started Jul 16 05:02:31 PM PDT 24
Finished Jul 16 05:03:20 PM PDT 24
Peak memory 219276 kb
Host smart-045170f1-8213-4ad5-8031-61bdd6d3d344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852011336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1852011336
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2157645460
Short name T247
Test name
Test status
Simulation time 304766799 ps
CPU time 9.86 seconds
Started Jul 16 05:02:15 PM PDT 24
Finished Jul 16 05:02:27 PM PDT 24
Peak memory 219260 kb
Host smart-2c377163-615c-47c3-aadb-df4b6bf0c07d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2157645460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2157645460
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.610152351
Short name T252
Test name
Test status
Simulation time 19151150281 ps
CPU time 53.63 seconds
Started Jul 16 05:02:17 PM PDT 24
Finished Jul 16 05:03:12 PM PDT 24
Peak memory 216740 kb
Host smart-23e9fc8b-2c77-4c95-b804-d616f7890b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610152351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.610152351
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2760359363
Short name T289
Test name
Test status
Simulation time 3431580320 ps
CPU time 52.53 seconds
Started Jul 16 05:02:17 PM PDT 24
Finished Jul 16 05:03:11 PM PDT 24
Peak memory 219320 kb
Host smart-1ac6904e-b088-40e7-9b6d-d608c17abdd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760359363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2760359363
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.237049968
Short name T180
Test name
Test status
Simulation time 2790394874 ps
CPU time 24.73 seconds
Started Jul 16 05:02:30 PM PDT 24
Finished Jul 16 05:02:55 PM PDT 24
Peak memory 217184 kb
Host smart-92ea820e-9ea4-4862-8fa4-23fe4053279e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237049968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.237049968
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2651565067
Short name T219
Test name
Test status
Simulation time 19871207455 ps
CPU time 252.06 seconds
Started Jul 16 05:02:30 PM PDT 24
Finished Jul 16 05:06:43 PM PDT 24
Peak memory 239060 kb
Host smart-8f6a7822-03ba-4426-820d-f8dc0b0e4921
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651565067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2651565067
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1471668774
Short name T176
Test name
Test status
Simulation time 44831714896 ps
CPU time 68.72 seconds
Started Jul 16 05:02:31 PM PDT 24
Finished Jul 16 05:03:40 PM PDT 24
Peak memory 219144 kb
Host smart-dd8887e1-b76d-457e-8091-8a93c1878068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471668774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1471668774
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.7686856
Short name T164
Test name
Test status
Simulation time 14986726080 ps
CPU time 30.58 seconds
Started Jul 16 05:02:34 PM PDT 24
Finished Jul 16 05:03:05 PM PDT 24
Peak memory 219412 kb
Host smart-dbabcfe9-8941-4633-8ac5-0fb0c462090b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=7686856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.7686856
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2937929458
Short name T79
Test name
Test status
Simulation time 1268252170 ps
CPU time 20.41 seconds
Started Jul 16 05:02:28 PM PDT 24
Finished Jul 16 05:02:49 PM PDT 24
Peak memory 216632 kb
Host smart-f5510b7c-77dd-4120-bb24-cabb66423960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937929458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2937929458
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1588666012
Short name T233
Test name
Test status
Simulation time 12875567419 ps
CPU time 130.44 seconds
Started Jul 16 05:02:29 PM PDT 24
Finished Jul 16 05:04:39 PM PDT 24
Peak memory 219548 kb
Host smart-02f35338-4c81-4f24-830d-8c3a81c65985
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588666012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1588666012
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.943153182
Short name T286
Test name
Test status
Simulation time 662125316 ps
CPU time 8.05 seconds
Started Jul 16 05:02:30 PM PDT 24
Finished Jul 16 05:02:39 PM PDT 24
Peak memory 217092 kb
Host smart-350a6212-ee39-4caf-b09e-f7b32c3fa553
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943153182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.943153182
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2531368744
Short name T175
Test name
Test status
Simulation time 133644133295 ps
CPU time 1258.79 seconds
Started Jul 16 05:02:28 PM PDT 24
Finished Jul 16 05:23:27 PM PDT 24
Peak memory 236000 kb
Host smart-03886f7e-ef44-4be6-92a7-00f4b3aa866a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531368744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2531368744
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3819553069
Short name T191
Test name
Test status
Simulation time 12583826043 ps
CPU time 56.12 seconds
Started Jul 16 05:02:32 PM PDT 24
Finished Jul 16 05:03:29 PM PDT 24
Peak memory 219088 kb
Host smart-99125e0c-d619-4868-b891-f691bf79931d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819553069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3819553069
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.746591311
Short name T225
Test name
Test status
Simulation time 719170102 ps
CPU time 10.31 seconds
Started Jul 16 05:02:32 PM PDT 24
Finished Jul 16 05:02:43 PM PDT 24
Peak memory 219252 kb
Host smart-2918c1e2-cb74-4d45-9375-cb8e02e6fd58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=746591311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.746591311
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3769506345
Short name T170
Test name
Test status
Simulation time 1168939831 ps
CPU time 27.95 seconds
Started Jul 16 05:02:33 PM PDT 24
Finished Jul 16 05:03:02 PM PDT 24
Peak memory 216540 kb
Host smart-394da9e0-0577-4b44-95ff-72d4d5a3f008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769506345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3769506345
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2204124924
Short name T235
Test name
Test status
Simulation time 3729256592 ps
CPU time 49.59 seconds
Started Jul 16 05:02:29 PM PDT 24
Finished Jul 16 05:03:19 PM PDT 24
Peak memory 219236 kb
Host smart-9bcfc47f-72e9-4e0b-8c32-90dcc8cbbb88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204124924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2204124924
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.300912917
Short name T212
Test name
Test status
Simulation time 590468554 ps
CPU time 8.45 seconds
Started Jul 16 05:02:29 PM PDT 24
Finished Jul 16 05:02:38 PM PDT 24
Peak memory 217156 kb
Host smart-e31b2b1e-e96d-4fc5-8bd6-d802561c953c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300912917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.300912917
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2352962759
Short name T339
Test name
Test status
Simulation time 51999068667 ps
CPU time 556.41 seconds
Started Jul 16 05:02:31 PM PDT 24
Finished Jul 16 05:11:48 PM PDT 24
Peak memory 219500 kb
Host smart-a0bed5da-280f-4a7f-a3e4-9f7c836152fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352962759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2352962759
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3699111932
Short name T131
Test name
Test status
Simulation time 3588065847 ps
CPU time 41.89 seconds
Started Jul 16 05:02:32 PM PDT 24
Finished Jul 16 05:03:15 PM PDT 24
Peak memory 219248 kb
Host smart-9cc3df8b-c4a1-4b8f-84d2-bc901f097feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699111932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3699111932
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2704245085
Short name T171
Test name
Test status
Simulation time 2834742138 ps
CPU time 25.62 seconds
Started Jul 16 05:02:30 PM PDT 24
Finished Jul 16 05:02:56 PM PDT 24
Peak memory 219328 kb
Host smart-0bb97ee1-3130-46e7-9eab-aea7c19d6f52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2704245085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2704245085
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3093302012
Short name T307
Test name
Test status
Simulation time 3028877596 ps
CPU time 31.68 seconds
Started Jul 16 05:02:30 PM PDT 24
Finished Jul 16 05:03:02 PM PDT 24
Peak memory 217432 kb
Host smart-6a07cd32-d9d6-445c-be15-8d05d04d2923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093302012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3093302012
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1768537818
Short name T215
Test name
Test status
Simulation time 7557626036 ps
CPU time 103.28 seconds
Started Jul 16 05:02:33 PM PDT 24
Finished Jul 16 05:04:17 PM PDT 24
Peak memory 219384 kb
Host smart-e7a3e157-e7a5-40b9-b2d1-0c5b2b3df5c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768537818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1768537818
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.1628080782
Short name T50
Test name
Test status
Simulation time 225896673733 ps
CPU time 2118.96 seconds
Started Jul 16 05:02:27 PM PDT 24
Finished Jul 16 05:37:47 PM PDT 24
Peak memory 243876 kb
Host smart-31059753-10f2-441e-81ef-7985fbd7bb1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628080782 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.1628080782
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1762437122
Short name T188
Test name
Test status
Simulation time 508119270 ps
CPU time 9.78 seconds
Started Jul 16 05:02:31 PM PDT 24
Finished Jul 16 05:02:42 PM PDT 24
Peak memory 217104 kb
Host smart-ebf26cd8-d6fa-4538-80c6-1d731c8e9fe9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762437122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1762437122
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2543746477
Short name T130
Test name
Test status
Simulation time 28587773819 ps
CPU time 60.91 seconds
Started Jul 16 05:02:27 PM PDT 24
Finished Jul 16 05:03:28 PM PDT 24
Peak memory 219280 kb
Host smart-381d364a-057a-484d-8259-685366f605ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543746477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2543746477
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.365389475
Short name T30
Test name
Test status
Simulation time 6832745755 ps
CPU time 28.9 seconds
Started Jul 16 05:02:27 PM PDT 24
Finished Jul 16 05:02:57 PM PDT 24
Peak memory 219252 kb
Host smart-ae58298e-af2f-4d75-a9ef-15143d6fbd14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=365389475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.365389475
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2353778092
Short name T194
Test name
Test status
Simulation time 12530485950 ps
CPU time 43.43 seconds
Started Jul 16 05:02:27 PM PDT 24
Finished Jul 16 05:03:10 PM PDT 24
Peak memory 216852 kb
Host smart-2a6bfb3d-b3f8-493f-abea-449307c53b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353778092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2353778092
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1946906461
Short name T81
Test name
Test status
Simulation time 701373038 ps
CPU time 47.06 seconds
Started Jul 16 05:02:26 PM PDT 24
Finished Jul 16 05:03:14 PM PDT 24
Peak memory 219892 kb
Host smart-b2b61887-1542-44ea-8e76-70d6a7301238
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946906461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1946906461
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3971741637
Short name T163
Test name
Test status
Simulation time 1514911985 ps
CPU time 17.27 seconds
Started Jul 16 05:02:42 PM PDT 24
Finished Jul 16 05:03:00 PM PDT 24
Peak memory 217052 kb
Host smart-bec94126-86c3-4f16-8780-c2e26c09d510
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971741637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3971741637
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.4174768370
Short name T193
Test name
Test status
Simulation time 36461704595 ps
CPU time 521.16 seconds
Started Jul 16 05:02:32 PM PDT 24
Finished Jul 16 05:11:14 PM PDT 24
Peak memory 225820 kb
Host smart-04a31619-d47a-4275-9b9d-2a9b68311d79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174768370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.4174768370
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.458389938
Short name T351
Test name
Test status
Simulation time 6142636592 ps
CPU time 37.72 seconds
Started Jul 16 05:02:31 PM PDT 24
Finished Jul 16 05:03:09 PM PDT 24
Peak memory 219252 kb
Host smart-cb5c8277-cbf5-4ec2-a7c7-f62a67453233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458389938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.458389938
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.4102815965
Short name T243
Test name
Test status
Simulation time 8386730457 ps
CPU time 67.2 seconds
Started Jul 16 05:02:32 PM PDT 24
Finished Jul 16 05:03:40 PM PDT 24
Peak memory 216328 kb
Host smart-42890379-bb0b-4e4e-877e-0d298bf096a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102815965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.4102815965
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.4031460421
Short name T264
Test name
Test status
Simulation time 4187362622 ps
CPU time 73.33 seconds
Started Jul 16 05:02:29 PM PDT 24
Finished Jul 16 05:03:42 PM PDT 24
Peak memory 219272 kb
Host smart-88b9bd80-4ff4-4eac-a3e2-7c4a7266a9bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031460421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.4031460421
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3005848945
Short name T149
Test name
Test status
Simulation time 4406088230 ps
CPU time 12.7 seconds
Started Jul 16 05:02:42 PM PDT 24
Finished Jul 16 05:02:56 PM PDT 24
Peak memory 217428 kb
Host smart-c6a22454-f1c2-40e3-a80c-c8162cdee29c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005848945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3005848945
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.221717860
Short name T236
Test name
Test status
Simulation time 61936922441 ps
CPU time 783.71 seconds
Started Jul 16 05:02:44 PM PDT 24
Finished Jul 16 05:15:49 PM PDT 24
Peak memory 237136 kb
Host smart-221970eb-821a-4e92-b28c-c02297ab59be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221717860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.221717860
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2014207733
Short name T100
Test name
Test status
Simulation time 8176925098 ps
CPU time 30.87 seconds
Started Jul 16 05:02:41 PM PDT 24
Finished Jul 16 05:03:12 PM PDT 24
Peak memory 219268 kb
Host smart-576250e4-1eaa-43ed-b825-bfe0a9548028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014207733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2014207733
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2029236999
Short name T203
Test name
Test status
Simulation time 718846449 ps
CPU time 10.09 seconds
Started Jul 16 05:02:42 PM PDT 24
Finished Jul 16 05:02:54 PM PDT 24
Peak memory 219272 kb
Host smart-e46f1b41-45a2-44e6-8148-39d394eb15bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2029236999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2029236999
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1551045373
Short name T288
Test name
Test status
Simulation time 6195603647 ps
CPU time 43.17 seconds
Started Jul 16 05:02:40 PM PDT 24
Finished Jul 16 05:03:23 PM PDT 24
Peak memory 217252 kb
Host smart-849cb251-1d7d-4deb-92d4-c2e9c798236a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551045373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1551045373
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.232678393
Short name T296
Test name
Test status
Simulation time 29198552234 ps
CPU time 72.54 seconds
Started Jul 16 05:02:41 PM PDT 24
Finished Jul 16 05:03:54 PM PDT 24
Peak memory 220404 kb
Host smart-23ac36d3-c6e4-4d67-99ec-824a33341441
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232678393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.232678393
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.3812289417
Short name T53
Test name
Test status
Simulation time 114400151883 ps
CPU time 1979.15 seconds
Started Jul 16 05:02:46 PM PDT 24
Finished Jul 16 05:35:45 PM PDT 24
Peak memory 237460 kb
Host smart-8f88420e-5078-47ca-b399-3295c90fe59f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812289417 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.3812289417
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.684748412
Short name T166
Test name
Test status
Simulation time 1980979992 ps
CPU time 20.81 seconds
Started Jul 16 05:02:44 PM PDT 24
Finished Jul 16 05:03:06 PM PDT 24
Peak memory 217148 kb
Host smart-dfe9cecf-20c5-41d4-9cd9-4cffa34085f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684748412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.684748412
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1724840372
Short name T280
Test name
Test status
Simulation time 15682897660 ps
CPU time 197.81 seconds
Started Jul 16 05:02:40 PM PDT 24
Finished Jul 16 05:05:59 PM PDT 24
Peak memory 238320 kb
Host smart-05e49987-0032-45fc-99b2-72f263a4541d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724840372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1724840372
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3346231858
Short name T26
Test name
Test status
Simulation time 1320511497 ps
CPU time 19.06 seconds
Started Jul 16 05:02:42 PM PDT 24
Finished Jul 16 05:03:02 PM PDT 24
Peak memory 219120 kb
Host smart-b47f8a57-e211-42b9-a126-dcdbc6571768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346231858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3346231858
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1952212097
Short name T335
Test name
Test status
Simulation time 177129483 ps
CPU time 10.3 seconds
Started Jul 16 05:02:43 PM PDT 24
Finished Jul 16 05:02:54 PM PDT 24
Peak memory 219156 kb
Host smart-7dbb48d3-0088-47b9-b06f-08e93d3771a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1952212097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1952212097
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1363559723
Short name T173
Test name
Test status
Simulation time 18486484575 ps
CPU time 45.21 seconds
Started Jul 16 05:02:42 PM PDT 24
Finished Jul 16 05:03:28 PM PDT 24
Peak memory 215388 kb
Host smart-bdf3fd9d-c40a-45e1-8cb4-c72a5b2aa9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363559723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1363559723
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3914214950
Short name T350
Test name
Test status
Simulation time 11283347955 ps
CPU time 117.54 seconds
Started Jul 16 05:02:43 PM PDT 24
Finished Jul 16 05:04:42 PM PDT 24
Peak memory 220388 kb
Host smart-4342d932-ab57-448c-8ac1-e798bf1418b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914214950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3914214950
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1557703813
Short name T179
Test name
Test status
Simulation time 1548075326 ps
CPU time 17.7 seconds
Started Jul 16 05:02:44 PM PDT 24
Finished Jul 16 05:03:02 PM PDT 24
Peak memory 213284 kb
Host smart-92b82196-36e3-4885-877f-3398ea632965
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557703813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1557703813
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3674634939
Short name T346
Test name
Test status
Simulation time 13312590499 ps
CPU time 33.62 seconds
Started Jul 16 05:03:12 PM PDT 24
Finished Jul 16 05:03:46 PM PDT 24
Peak memory 215492 kb
Host smart-6e52dac7-4d92-4110-afa3-a988810c6b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674634939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3674634939
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1449256869
Short name T56
Test name
Test status
Simulation time 4674000694 ps
CPU time 23.76 seconds
Started Jul 16 05:02:45 PM PDT 24
Finished Jul 16 05:03:09 PM PDT 24
Peak memory 219104 kb
Host smart-1aa216b6-1d46-4cb7-9d12-c4cb38632c12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1449256869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1449256869
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.4078617600
Short name T299
Test name
Test status
Simulation time 3517384543 ps
CPU time 46.11 seconds
Started Jul 16 05:02:42 PM PDT 24
Finished Jul 16 05:03:29 PM PDT 24
Peak memory 215680 kb
Host smart-dd7929ea-9149-443a-b6b6-fb8918b901bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078617600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.4078617600
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2902128136
Short name T192
Test name
Test status
Simulation time 60393690267 ps
CPU time 148.71 seconds
Started Jul 16 05:02:45 PM PDT 24
Finished Jul 16 05:05:14 PM PDT 24
Peak memory 220624 kb
Host smart-254be9ab-6cf7-4c27-ade1-6e61266bbc01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902128136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2902128136
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.4086032905
Short name T328
Test name
Test status
Simulation time 2466353979 ps
CPU time 22.99 seconds
Started Jul 16 05:01:04 PM PDT 24
Finished Jul 16 05:01:28 PM PDT 24
Peak memory 215816 kb
Host smart-640c79c3-b0a2-4e47-9303-1c59e9d09edd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086032905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.4086032905
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3169074222
Short name T137
Test name
Test status
Simulation time 10935411944 ps
CPU time 198.18 seconds
Started Jul 16 05:01:01 PM PDT 24
Finished Jul 16 05:04:20 PM PDT 24
Peak memory 242224 kb
Host smart-68c69756-8706-4f6f-8c4b-0a70100dd483
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169074222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3169074222
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1180154588
Short name T259
Test name
Test status
Simulation time 689399615 ps
CPU time 18.76 seconds
Started Jul 16 05:01:02 PM PDT 24
Finished Jul 16 05:01:22 PM PDT 24
Peak memory 219216 kb
Host smart-0f2bb5c8-f4f2-4a85-bb5c-f63f68fc7319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180154588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1180154588
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2521313059
Short name T182
Test name
Test status
Simulation time 3964681700 ps
CPU time 21.73 seconds
Started Jul 16 05:01:00 PM PDT 24
Finished Jul 16 05:01:23 PM PDT 24
Peak memory 211360 kb
Host smart-72dda88c-21ed-49fa-8ac6-83e6ad021c9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2521313059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2521313059
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3622490345
Short name T159
Test name
Test status
Simulation time 5133922281 ps
CPU time 34.54 seconds
Started Jul 16 05:01:00 PM PDT 24
Finished Jul 16 05:01:35 PM PDT 24
Peak memory 217636 kb
Host smart-4251f271-0cdd-4299-8888-9297ffa9f174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622490345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3622490345
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3135405293
Short name T231
Test name
Test status
Simulation time 874833054 ps
CPU time 59.62 seconds
Started Jul 16 05:01:02 PM PDT 24
Finished Jul 16 05:02:02 PM PDT 24
Peak memory 219316 kb
Host smart-af3f38ae-7213-4bd9-8cc9-1b4506f76cdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135405293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3135405293
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3057216748
Short name T223
Test name
Test status
Simulation time 2597642143 ps
CPU time 12.47 seconds
Started Jul 16 05:01:01 PM PDT 24
Finished Jul 16 05:01:14 PM PDT 24
Peak memory 217152 kb
Host smart-b877c7aa-f8dd-484d-9959-a6b798b1a8c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057216748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3057216748
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.144544298
Short name T295
Test name
Test status
Simulation time 91562644839 ps
CPU time 451.46 seconds
Started Jul 16 05:01:01 PM PDT 24
Finished Jul 16 05:08:33 PM PDT 24
Peak memory 217764 kb
Host smart-6868688f-b5e0-4366-b228-aa75830e7643
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144544298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.144544298
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.510741317
Short name T248
Test name
Test status
Simulation time 1678050950 ps
CPU time 25.27 seconds
Started Jul 16 05:01:00 PM PDT 24
Finished Jul 16 05:01:26 PM PDT 24
Peak memory 218416 kb
Host smart-8b78f0fe-57ea-4cd8-9128-f0e4ced43815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510741317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.510741317
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1351144184
Short name T308
Test name
Test status
Simulation time 3127031079 ps
CPU time 27.32 seconds
Started Jul 16 05:00:59 PM PDT 24
Finished Jul 16 05:01:27 PM PDT 24
Peak memory 219232 kb
Host smart-f6470c15-f46f-4483-85fb-f2009daf521e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1351144184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1351144184
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1067247509
Short name T43
Test name
Test status
Simulation time 866580949 ps
CPU time 24.71 seconds
Started Jul 16 05:00:59 PM PDT 24
Finished Jul 16 05:01:25 PM PDT 24
Peak memory 216380 kb
Host smart-7d63d1e6-90f0-46a0-aabf-9a6969b02fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067247509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1067247509
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2645010641
Short name T326
Test name
Test status
Simulation time 3651188986 ps
CPU time 26.41 seconds
Started Jul 16 05:01:02 PM PDT 24
Finished Jul 16 05:01:29 PM PDT 24
Peak memory 216872 kb
Host smart-dde636e9-7724-43dc-98e8-bc0d559ceace
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645010641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2645010641
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3525154111
Short name T228
Test name
Test status
Simulation time 162323100801 ps
CPU time 482.54 seconds
Started Jul 16 05:01:33 PM PDT 24
Finished Jul 16 05:09:38 PM PDT 24
Peak memory 233732 kb
Host smart-2cedbdfc-8bda-456a-8e3b-38ad91c7199e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525154111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3525154111
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.97681625
Short name T337
Test name
Test status
Simulation time 3552880852 ps
CPU time 38.76 seconds
Started Jul 16 05:01:02 PM PDT 24
Finished Jul 16 05:01:42 PM PDT 24
Peak memory 219280 kb
Host smart-8875b521-9802-4c9a-b689-0769a63fb7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97681625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.97681625
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3401650621
Short name T186
Test name
Test status
Simulation time 8598479782 ps
CPU time 22.34 seconds
Started Jul 16 05:01:00 PM PDT 24
Finished Jul 16 05:01:23 PM PDT 24
Peak memory 217608 kb
Host smart-e909511a-b55d-42e4-8f22-53c339a5e8f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3401650621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3401650621
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3071859208
Short name T287
Test name
Test status
Simulation time 6668856048 ps
CPU time 64.21 seconds
Started Jul 16 05:01:03 PM PDT 24
Finished Jul 16 05:02:08 PM PDT 24
Peak memory 216972 kb
Host smart-e6ae5e2e-d3fa-4b60-9300-d861fd026647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071859208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3071859208
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3026416475
Short name T349
Test name
Test status
Simulation time 21885844716 ps
CPU time 115.07 seconds
Started Jul 16 05:01:00 PM PDT 24
Finished Jul 16 05:02:56 PM PDT 24
Peak memory 220460 kb
Host smart-d16f3038-22b7-4c3f-b3b9-0a55f34d0cc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026416475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3026416475
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2493687817
Short name T238
Test name
Test status
Simulation time 4747833564 ps
CPU time 23.88 seconds
Started Jul 16 05:01:00 PM PDT 24
Finished Jul 16 05:01:25 PM PDT 24
Peak memory 217372 kb
Host smart-8a22791d-8b94-4ad7-b314-dc314b4c5117
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493687817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2493687817
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2568597595
Short name T336
Test name
Test status
Simulation time 20113616441 ps
CPU time 329.11 seconds
Started Jul 16 05:01:04 PM PDT 24
Finished Jul 16 05:06:34 PM PDT 24
Peak memory 233736 kb
Host smart-3fd1ae27-c5fd-4bae-b017-be4df75246e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568597595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2568597595
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.654978485
Short name T143
Test name
Test status
Simulation time 14101973336 ps
CPU time 59.75 seconds
Started Jul 16 05:01:02 PM PDT 24
Finished Jul 16 05:02:03 PM PDT 24
Peak memory 219356 kb
Host smart-bcbad2fb-8459-4b19-8c0a-a14e77c3b11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654978485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.654978485
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1179071261
Short name T251
Test name
Test status
Simulation time 1353113698 ps
CPU time 10.44 seconds
Started Jul 16 05:01:02 PM PDT 24
Finished Jul 16 05:01:13 PM PDT 24
Peak memory 219220 kb
Host smart-eb7f4ab6-7e67-4751-8743-8f785a04a89e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1179071261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1179071261
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.4170100013
Short name T312
Test name
Test status
Simulation time 33401457389 ps
CPU time 70.2 seconds
Started Jul 16 05:01:01 PM PDT 24
Finished Jul 16 05:02:12 PM PDT 24
Peak memory 217012 kb
Host smart-ebaff672-4c25-4a79-a3da-23d4656f5ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170100013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.4170100013
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.65141821
Short name T169
Test name
Test status
Simulation time 103274647480 ps
CPU time 126.55 seconds
Started Jul 16 05:01:04 PM PDT 24
Finished Jul 16 05:03:11 PM PDT 24
Peak memory 219264 kb
Host smart-ad5ee636-4398-4602-8290-65fb4dacd1b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65141821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 8.rom_ctrl_stress_all.65141821
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1133797752
Short name T283
Test name
Test status
Simulation time 33630472120 ps
CPU time 30.74 seconds
Started Jul 16 05:01:14 PM PDT 24
Finished Jul 16 05:01:47 PM PDT 24
Peak memory 217464 kb
Host smart-49a2f8c9-f07a-4970-a117-c4952f176f08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133797752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1133797752
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2787709291
Short name T97
Test name
Test status
Simulation time 9954054747 ps
CPU time 323.98 seconds
Started Jul 16 05:01:17 PM PDT 24
Finished Jul 16 05:06:44 PM PDT 24
Peak memory 240056 kb
Host smart-aefa5b65-c17e-442e-9c87-6152d569f48e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787709291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2787709291
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2582586095
Short name T141
Test name
Test status
Simulation time 10131593970 ps
CPU time 38.41 seconds
Started Jul 16 05:01:18 PM PDT 24
Finished Jul 16 05:01:59 PM PDT 24
Peak memory 219352 kb
Host smart-e7bd83ff-ea9e-46de-938c-256687a58a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582586095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2582586095
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2332423935
Short name T35
Test name
Test status
Simulation time 682443932 ps
CPU time 10.75 seconds
Started Jul 16 05:01:16 PM PDT 24
Finished Jul 16 05:01:28 PM PDT 24
Peak memory 219216 kb
Host smart-a346c297-d9f1-4799-8dd3-89f61bb9fa44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2332423935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2332423935
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2723053041
Short name T94
Test name
Test status
Simulation time 11842420875 ps
CPU time 36.75 seconds
Started Jul 16 05:01:04 PM PDT 24
Finished Jul 16 05:01:41 PM PDT 24
Peak memory 215828 kb
Host smart-e9a85ce0-5c9a-4c04-b045-078d53dce89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723053041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2723053041
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1407294107
Short name T230
Test name
Test status
Simulation time 2339510890 ps
CPU time 30.64 seconds
Started Jul 16 05:01:16 PM PDT 24
Finished Jul 16 05:01:48 PM PDT 24
Peak memory 219280 kb
Host smart-18531204-e47f-42ac-ba4b-a1d4c2cf298a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407294107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1407294107
Directory /workspace/9.rom_ctrl_stress_all/latest
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