Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.33 96.89 92.28 97.68 100.00 98.62 97.45 98.37


Total test records in report: 458
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T300 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1445371962 Jul 17 05:04:15 PM PDT 24 Jul 17 05:09:45 PM PDT 24 106460426750 ps
T301 /workspace/coverage/default/49.rom_ctrl_stress_all.2593420067 Jul 17 05:04:48 PM PDT 24 Jul 17 05:05:37 PM PDT 24 3297403200 ps
T302 /workspace/coverage/default/8.rom_ctrl_alert_test.2313333167 Jul 17 05:03:22 PM PDT 24 Jul 17 05:03:42 PM PDT 24 1806666541 ps
T303 /workspace/coverage/default/36.rom_ctrl_stress_all.11298381 Jul 17 05:04:14 PM PDT 24 Jul 17 05:06:09 PM PDT 24 10309775655 ps
T304 /workspace/coverage/default/7.rom_ctrl_alert_test.655225362 Jul 17 05:03:17 PM PDT 24 Jul 17 05:03:42 PM PDT 24 10510445390 ps
T305 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3374543252 Jul 17 05:03:42 PM PDT 24 Jul 17 05:17:12 PM PDT 24 75904830585 ps
T306 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.370507940 Jul 17 05:03:06 PM PDT 24 Jul 17 05:03:20 PM PDT 24 724190569 ps
T307 /workspace/coverage/default/31.rom_ctrl_smoke.3167583828 Jul 17 05:03:55 PM PDT 24 Jul 17 05:04:53 PM PDT 24 27797341821 ps
T308 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3637668087 Jul 17 05:03:44 PM PDT 24 Jul 17 05:04:06 PM PDT 24 1436336429 ps
T309 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2020094253 Jul 17 05:03:32 PM PDT 24 Jul 17 05:09:49 PM PDT 24 6863768088 ps
T310 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3049430811 Jul 17 05:03:07 PM PDT 24 Jul 17 05:15:21 PM PDT 24 279649586895 ps
T311 /workspace/coverage/default/14.rom_ctrl_alert_test.723602590 Jul 17 05:03:30 PM PDT 24 Jul 17 05:03:45 PM PDT 24 2421012305 ps
T312 /workspace/coverage/default/41.rom_ctrl_alert_test.2168354205 Jul 17 05:04:23 PM PDT 24 Jul 17 05:04:56 PM PDT 24 17378147035 ps
T313 /workspace/coverage/default/47.rom_ctrl_alert_test.2689274312 Jul 17 05:04:48 PM PDT 24 Jul 17 05:05:04 PM PDT 24 3736195935 ps
T314 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1544703176 Jul 17 05:03:04 PM PDT 24 Jul 17 05:16:09 PM PDT 24 680376614076 ps
T315 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1548775944 Jul 17 05:03:54 PM PDT 24 Jul 17 05:07:22 PM PDT 24 2847485040 ps
T316 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.921525841 Jul 17 05:03:42 PM PDT 24 Jul 17 05:04:44 PM PDT 24 25603116445 ps
T317 /workspace/coverage/default/1.rom_ctrl_alert_test.1741243806 Jul 17 05:03:05 PM PDT 24 Jul 17 05:03:28 PM PDT 24 9068347909 ps
T318 /workspace/coverage/default/35.rom_ctrl_stress_all.2925225088 Jul 17 05:04:12 PM PDT 24 Jul 17 05:04:49 PM PDT 24 1837791756 ps
T319 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2689217389 Jul 17 05:03:58 PM PDT 24 Jul 17 05:07:58 PM PDT 24 24166181147 ps
T320 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2616409836 Jul 17 05:03:30 PM PDT 24 Jul 17 05:04:28 PM PDT 24 6281709963 ps
T321 /workspace/coverage/default/38.rom_ctrl_smoke.1525275629 Jul 17 05:04:25 PM PDT 24 Jul 17 05:04:46 PM PDT 24 714062338 ps
T322 /workspace/coverage/default/33.rom_ctrl_smoke.2465537379 Jul 17 05:04:19 PM PDT 24 Jul 17 05:04:56 PM PDT 24 2440932143 ps
T323 /workspace/coverage/default/44.rom_ctrl_smoke.849682311 Jul 17 05:04:27 PM PDT 24 Jul 17 05:04:50 PM PDT 24 350983595 ps
T324 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.438458869 Jul 17 05:04:18 PM PDT 24 Jul 17 05:04:38 PM PDT 24 1374467884 ps
T325 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1921165212 Jul 17 05:03:20 PM PDT 24 Jul 17 05:06:05 PM PDT 24 2494474201 ps
T326 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.832033950 Jul 17 05:04:15 PM PDT 24 Jul 17 05:09:01 PM PDT 24 135630837913 ps
T327 /workspace/coverage/default/11.rom_ctrl_alert_test.3001270020 Jul 17 05:03:17 PM PDT 24 Jul 17 05:03:39 PM PDT 24 1981086144 ps
T328 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3513345184 Jul 17 05:04:38 PM PDT 24 Jul 17 05:05:21 PM PDT 24 14291800785 ps
T329 /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.472183765 Jul 17 05:04:24 PM PDT 24 Jul 17 05:07:48 PM PDT 24 2754608492 ps
T330 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3997003162 Jul 17 05:03:19 PM PDT 24 Jul 17 05:03:54 PM PDT 24 4087611466 ps
T331 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1509782159 Jul 17 05:04:24 PM PDT 24 Jul 17 05:05:04 PM PDT 24 2795812091 ps
T332 /workspace/coverage/default/9.rom_ctrl_stress_all.1531316064 Jul 17 05:03:20 PM PDT 24 Jul 17 05:04:25 PM PDT 24 14338509285 ps
T333 /workspace/coverage/default/1.rom_ctrl_smoke.2413081460 Jul 17 05:03:05 PM PDT 24 Jul 17 05:04:15 PM PDT 24 8418304083 ps
T334 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3063251549 Jul 17 05:04:27 PM PDT 24 Jul 17 05:04:53 PM PDT 24 1685176401 ps
T335 /workspace/coverage/default/29.rom_ctrl_smoke.920024637 Jul 17 05:03:56 PM PDT 24 Jul 17 05:04:54 PM PDT 24 13559157425 ps
T336 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2926162796 Jul 17 05:03:54 PM PDT 24 Jul 17 05:04:06 PM PDT 24 723919703 ps
T337 /workspace/coverage/default/30.rom_ctrl_stress_all.1328851560 Jul 17 05:03:58 PM PDT 24 Jul 17 05:05:49 PM PDT 24 48343698753 ps
T42 /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.4175827297 Jul 17 05:04:17 PM PDT 24 Jul 17 05:47:09 PM PDT 24 280379345343 ps
T43 /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.924884231 Jul 17 05:03:58 PM PDT 24 Jul 17 05:34:23 PM PDT 24 48421383643 ps
T338 /workspace/coverage/default/5.rom_ctrl_stress_all.707543936 Jul 17 05:03:16 PM PDT 24 Jul 17 05:03:57 PM PDT 24 5411331812 ps
T339 /workspace/coverage/default/28.rom_ctrl_stress_all.4113749658 Jul 17 05:03:58 PM PDT 24 Jul 17 05:05:56 PM PDT 24 152598311945 ps
T340 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1168662137 Jul 17 05:03:19 PM PDT 24 Jul 17 05:11:57 PM PDT 24 107418072378 ps
T341 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2245680382 Jul 17 05:04:20 PM PDT 24 Jul 17 05:04:43 PM PDT 24 4224953475 ps
T342 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1006628948 Jul 17 05:03:32 PM PDT 24 Jul 17 05:04:33 PM PDT 24 6796381791 ps
T343 /workspace/coverage/default/45.rom_ctrl_smoke.1210216415 Jul 17 05:04:27 PM PDT 24 Jul 17 05:05:49 PM PDT 24 8069717929 ps
T344 /workspace/coverage/default/36.rom_ctrl_alert_test.2588786292 Jul 17 05:04:24 PM PDT 24 Jul 17 05:04:55 PM PDT 24 6896618691 ps
T345 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1696671542 Jul 17 05:04:28 PM PDT 24 Jul 17 05:05:22 PM PDT 24 21819343890 ps
T346 /workspace/coverage/default/37.rom_ctrl_stress_all.735978175 Jul 17 05:04:22 PM PDT 24 Jul 17 05:08:00 PM PDT 24 52380280978 ps
T347 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1373722972 Jul 17 05:04:24 PM PDT 24 Jul 17 05:09:17 PM PDT 24 79646495708 ps
T348 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3447989130 Jul 17 05:03:39 PM PDT 24 Jul 17 05:11:06 PM PDT 24 186766896667 ps
T349 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2000332462 Jul 17 05:03:43 PM PDT 24 Jul 17 05:11:26 PM PDT 24 78068908621 ps
T350 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.188409682 Jul 17 05:03:22 PM PDT 24 Jul 17 05:04:32 PM PDT 24 33621785192 ps
T351 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2555843018 Jul 17 05:04:18 PM PDT 24 Jul 17 05:05:03 PM PDT 24 3945040480 ps
T352 /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.2148682079 Jul 17 05:03:06 PM PDT 24 Jul 17 05:32:50 PM PDT 24 200495216053 ps
T353 /workspace/coverage/default/19.rom_ctrl_stress_all.2115121268 Jul 17 05:03:30 PM PDT 24 Jul 17 05:06:22 PM PDT 24 36170823484 ps
T354 /workspace/coverage/default/13.rom_ctrl_stress_all.1683141561 Jul 17 05:03:19 PM PDT 24 Jul 17 05:06:10 PM PDT 24 67450038109 ps
T355 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.4287647884 Jul 17 05:03:39 PM PDT 24 Jul 17 05:03:55 PM PDT 24 670683608 ps
T356 /workspace/coverage/default/3.rom_ctrl_alert_test.4231768298 Jul 17 05:03:07 PM PDT 24 Jul 17 05:03:42 PM PDT 24 4109610721 ps
T357 /workspace/coverage/default/24.rom_ctrl_smoke.4082955762 Jul 17 05:03:45 PM PDT 24 Jul 17 05:04:36 PM PDT 24 20622255477 ps
T358 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1333561108 Jul 17 05:03:21 PM PDT 24 Jul 17 05:13:02 PM PDT 24 215656892512 ps
T359 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2401429563 Jul 17 05:04:26 PM PDT 24 Jul 17 05:04:40 PM PDT 24 274598801 ps
T360 /workspace/coverage/default/16.rom_ctrl_stress_all.39242881 Jul 17 05:03:28 PM PDT 24 Jul 17 05:05:00 PM PDT 24 14188405062 ps
T361 /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1702002441 Jul 17 05:03:55 PM PDT 24 Jul 17 05:42:10 PM PDT 24 68282964621 ps
T362 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2524257411 Jul 17 05:02:55 PM PDT 24 Jul 17 05:03:11 PM PDT 24 611679851 ps
T47 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3341482613 Jul 17 05:02:41 PM PDT 24 Jul 17 05:03:13 PM PDT 24 2577352676 ps
T48 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.751401293 Jul 17 05:02:53 PM PDT 24 Jul 17 05:03:05 PM PDT 24 345748616 ps
T44 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2929377773 Jul 17 05:02:52 PM PDT 24 Jul 17 05:04:18 PM PDT 24 477720195 ps
T45 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.730577779 Jul 17 05:02:53 PM PDT 24 Jul 17 05:05:44 PM PDT 24 9618571232 ps
T93 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.4884495 Jul 17 05:02:51 PM PDT 24 Jul 17 05:03:27 PM PDT 24 8202827877 ps
T46 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2571675322 Jul 17 05:03:03 PM PDT 24 Jul 17 05:05:40 PM PDT 24 1174545476 ps
T94 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3883105856 Jul 17 05:03:02 PM PDT 24 Jul 17 05:04:37 PM PDT 24 8988765532 ps
T95 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2103708312 Jul 17 05:02:42 PM PDT 24 Jul 17 05:03:01 PM PDT 24 1645546878 ps
T55 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.322074030 Jul 17 05:02:43 PM PDT 24 Jul 17 05:03:00 PM PDT 24 1152141698 ps
T97 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1800891578 Jul 17 05:03:06 PM PDT 24 Jul 17 05:04:31 PM PDT 24 251145974 ps
T56 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.965069352 Jul 17 05:02:53 PM PDT 24 Jul 17 05:03:53 PM PDT 24 2460550103 ps
T57 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.471762826 Jul 17 05:02:53 PM PDT 24 Jul 17 05:05:07 PM PDT 24 13230428542 ps
T363 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2267724663 Jul 17 05:02:40 PM PDT 24 Jul 17 05:03:08 PM PDT 24 6062578409 ps
T364 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1884498333 Jul 17 05:03:04 PM PDT 24 Jul 17 05:03:40 PM PDT 24 4271970513 ps
T365 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.141830544 Jul 17 05:03:03 PM PDT 24 Jul 17 05:03:15 PM PDT 24 378142137 ps
T87 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.665696397 Jul 17 05:02:51 PM PDT 24 Jul 17 05:03:13 PM PDT 24 8832977016 ps
T58 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3382214651 Jul 17 05:02:52 PM PDT 24 Jul 17 05:03:04 PM PDT 24 688594930 ps
T366 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1827101857 Jul 17 05:02:42 PM PDT 24 Jul 17 05:02:51 PM PDT 24 170932765 ps
T59 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.304125479 Jul 17 05:02:50 PM PDT 24 Jul 17 05:02:58 PM PDT 24 687930211 ps
T102 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1950015393 Jul 17 05:02:54 PM PDT 24 Jul 17 05:04:26 PM PDT 24 5924155980 ps
T367 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1527882886 Jul 17 05:02:43 PM PDT 24 Jul 17 05:03:16 PM PDT 24 4225145548 ps
T60 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2537722808 Jul 17 05:03:03 PM PDT 24 Jul 17 05:03:30 PM PDT 24 11794024785 ps
T368 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3248295560 Jul 17 05:03:02 PM PDT 24 Jul 17 05:03:29 PM PDT 24 18729147817 ps
T369 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2520009509 Jul 17 05:02:43 PM PDT 24 Jul 17 05:03:20 PM PDT 24 7523962877 ps
T88 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2802250059 Jul 17 05:02:36 PM PDT 24 Jul 17 05:03:34 PM PDT 24 2163348987 ps
T61 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.4151554668 Jul 17 05:02:53 PM PDT 24 Jul 17 05:03:12 PM PDT 24 4597318540 ps
T370 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.587596599 Jul 17 05:03:06 PM PDT 24 Jul 17 05:03:33 PM PDT 24 1413886818 ps
T62 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2742748197 Jul 17 05:02:50 PM PDT 24 Jul 17 05:03:08 PM PDT 24 8678495377 ps
T63 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1194472713 Jul 17 05:03:05 PM PDT 24 Jul 17 05:05:02 PM PDT 24 62759092356 ps
T371 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.716708950 Jul 17 05:02:52 PM PDT 24 Jul 17 05:03:13 PM PDT 24 1564167646 ps
T98 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1702741856 Jul 17 05:02:54 PM PDT 24 Jul 17 05:05:31 PM PDT 24 430138921 ps
T101 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.987969992 Jul 17 05:02:41 PM PDT 24 Jul 17 05:05:19 PM PDT 24 429777045 ps
T372 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1907090267 Jul 17 05:03:04 PM PDT 24 Jul 17 05:03:35 PM PDT 24 2777968066 ps
T99 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.380745890 Jul 17 05:03:05 PM PDT 24 Jul 17 05:05:47 PM PDT 24 3485968671 ps
T373 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3176198257 Jul 17 05:02:53 PM PDT 24 Jul 17 05:03:14 PM PDT 24 3102514454 ps
T89 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3561369506 Jul 17 05:02:50 PM PDT 24 Jul 17 05:03:00 PM PDT 24 689438154 ps
T72 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2022915833 Jul 17 05:02:53 PM PDT 24 Jul 17 05:06:20 PM PDT 24 50439225388 ps
T374 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1026809605 Jul 17 05:03:06 PM PDT 24 Jul 17 05:03:43 PM PDT 24 14589763351 ps
T375 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4265827553 Jul 17 05:02:51 PM PDT 24 Jul 17 05:03:27 PM PDT 24 6057839361 ps
T106 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.392690049 Jul 17 05:03:05 PM PDT 24 Jul 17 05:04:51 PM PDT 24 3812920321 ps
T376 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3135373370 Jul 17 05:03:04 PM PDT 24 Jul 17 05:05:17 PM PDT 24 35573630816 ps
T90 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.216743312 Jul 17 05:02:52 PM PDT 24 Jul 17 05:03:08 PM PDT 24 1518237638 ps
T377 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1640947816 Jul 17 05:02:53 PM PDT 24 Jul 17 05:03:29 PM PDT 24 3135650638 ps
T378 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2446099988 Jul 17 05:03:04 PM PDT 24 Jul 17 05:03:35 PM PDT 24 9096148270 ps
T379 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3590686420 Jul 17 05:03:04 PM PDT 24 Jul 17 05:03:30 PM PDT 24 4328317867 ps
T91 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1454372167 Jul 17 05:02:39 PM PDT 24 Jul 17 05:03:14 PM PDT 24 8022262815 ps
T380 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3730088432 Jul 17 05:03:05 PM PDT 24 Jul 17 05:03:22 PM PDT 24 6302113963 ps
T381 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1895641179 Jul 17 05:02:53 PM PDT 24 Jul 17 05:04:39 PM PDT 24 4157728181 ps
T107 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2228121141 Jul 17 05:03:05 PM PDT 24 Jul 17 05:06:00 PM PDT 24 18261488601 ps
T92 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3154890941 Jul 17 05:03:05 PM PDT 24 Jul 17 05:03:34 PM PDT 24 2393229804 ps
T382 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1074098939 Jul 17 05:02:51 PM PDT 24 Jul 17 05:05:13 PM PDT 24 59604561907 ps
T383 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3523316237 Jul 17 05:02:37 PM PDT 24 Jul 17 05:03:00 PM PDT 24 13356522434 ps
T384 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1657855267 Jul 17 05:03:04 PM PDT 24 Jul 17 05:03:15 PM PDT 24 1650536770 ps
T385 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1871981356 Jul 17 05:03:05 PM PDT 24 Jul 17 05:03:42 PM PDT 24 15582265458 ps
T386 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.4178990218 Jul 17 05:03:04 PM PDT 24 Jul 17 05:03:14 PM PDT 24 578270197 ps
T387 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2362979622 Jul 17 05:03:04 PM PDT 24 Jul 17 05:04:34 PM PDT 24 7419549498 ps
T73 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3581883815 Jul 17 05:02:44 PM PDT 24 Jul 17 05:04:56 PM PDT 24 53422497394 ps
T74 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3728821597 Jul 17 05:02:52 PM PDT 24 Jul 17 05:05:38 PM PDT 24 76929546583 ps
T388 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.230561877 Jul 17 05:02:52 PM PDT 24 Jul 17 05:03:33 PM PDT 24 5280991100 ps
T389 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2271693506 Jul 17 05:02:38 PM PDT 24 Jul 17 05:04:14 PM PDT 24 12643873038 ps
T390 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3602060614 Jul 17 05:02:53 PM PDT 24 Jul 17 05:03:33 PM PDT 24 9158146186 ps
T391 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3849511806 Jul 17 05:02:53 PM PDT 24 Jul 17 05:03:15 PM PDT 24 868192190 ps
T392 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.410162170 Jul 17 05:02:51 PM PDT 24 Jul 17 05:03:29 PM PDT 24 6793691067 ps
T393 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3143349230 Jul 17 05:02:52 PM PDT 24 Jul 17 05:03:22 PM PDT 24 6858902406 ps
T394 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2561954029 Jul 17 05:02:36 PM PDT 24 Jul 17 05:03:09 PM PDT 24 7833175308 ps
T395 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.424710992 Jul 17 05:03:02 PM PDT 24 Jul 17 05:03:14 PM PDT 24 1373028103 ps
T396 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1736984832 Jul 17 05:03:04 PM PDT 24 Jul 17 05:03:39 PM PDT 24 11880743909 ps
T397 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.230482075 Jul 17 05:02:50 PM PDT 24 Jul 17 05:03:19 PM PDT 24 10156421359 ps
T398 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.9192508 Jul 17 05:02:40 PM PDT 24 Jul 17 05:02:54 PM PDT 24 2450652579 ps
T75 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.424516502 Jul 17 05:02:39 PM PDT 24 Jul 17 05:03:09 PM PDT 24 2320799332 ps
T110 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1160149776 Jul 17 05:02:38 PM PDT 24 Jul 17 05:04:13 PM PDT 24 2655719170 ps
T100 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2508413830 Jul 17 05:02:51 PM PDT 24 Jul 17 05:05:26 PM PDT 24 321862767 ps
T399 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1614129633 Jul 17 05:02:51 PM PDT 24 Jul 17 05:03:02 PM PDT 24 338555396 ps
T103 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.544531126 Jul 17 05:02:54 PM PDT 24 Jul 17 05:05:34 PM PDT 24 1097846965 ps
T400 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.950069689 Jul 17 05:03:05 PM PDT 24 Jul 17 05:04:06 PM PDT 24 1091876514 ps
T401 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1788387742 Jul 17 05:02:43 PM PDT 24 Jul 17 05:02:52 PM PDT 24 264188232 ps
T402 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.777316751 Jul 17 05:03:05 PM PDT 24 Jul 17 05:03:36 PM PDT 24 12559064069 ps
T403 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.907615204 Jul 17 05:02:51 PM PDT 24 Jul 17 05:03:33 PM PDT 24 4163109797 ps
T80 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.717935203 Jul 17 05:03:06 PM PDT 24 Jul 17 05:03:43 PM PDT 24 6089126979 ps
T404 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2176837225 Jul 17 05:02:38 PM PDT 24 Jul 17 05:03:15 PM PDT 24 4135488971 ps
T405 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2710352820 Jul 17 05:02:45 PM PDT 24 Jul 17 05:03:11 PM PDT 24 3022975040 ps
T406 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.991433829 Jul 17 05:03:05 PM PDT 24 Jul 17 05:03:34 PM PDT 24 7108953463 ps
T77 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1157308208 Jul 17 05:02:53 PM PDT 24 Jul 17 05:03:04 PM PDT 24 339043891 ps
T407 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.4244091484 Jul 17 05:02:51 PM PDT 24 Jul 17 05:03:12 PM PDT 24 1699327908 ps
T104 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1524222630 Jul 17 05:02:51 PM PDT 24 Jul 17 05:05:49 PM PDT 24 9285997594 ps
T408 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3330747264 Jul 17 05:02:43 PM PDT 24 Jul 17 05:03:19 PM PDT 24 6563270541 ps
T409 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3516607919 Jul 17 05:02:53 PM PDT 24 Jul 17 05:03:10 PM PDT 24 842899703 ps
T410 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2518289751 Jul 17 05:02:37 PM PDT 24 Jul 17 05:02:46 PM PDT 24 176070327 ps
T411 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.154471118 Jul 17 05:02:52 PM PDT 24 Jul 17 05:03:11 PM PDT 24 1674135874 ps
T412 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3780753718 Jul 17 05:03:02 PM PDT 24 Jul 17 05:03:11 PM PDT 24 688316507 ps
T413 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2811723700 Jul 17 05:02:40 PM PDT 24 Jul 17 05:03:09 PM PDT 24 3081398846 ps
T414 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1428190226 Jul 17 05:02:54 PM PDT 24 Jul 17 05:03:28 PM PDT 24 29228801769 ps
T415 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2289584665 Jul 17 05:03:03 PM PDT 24 Jul 17 05:03:33 PM PDT 24 13286695912 ps
T416 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3936404574 Jul 17 05:02:52 PM PDT 24 Jul 17 05:03:28 PM PDT 24 8917089097 ps
T417 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4228290231 Jul 17 05:03:04 PM PDT 24 Jul 17 05:03:29 PM PDT 24 1893607726 ps
T418 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1741821256 Jul 17 05:02:53 PM PDT 24 Jul 17 05:03:14 PM PDT 24 1698110507 ps
T419 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.844710736 Jul 17 05:03:06 PM PDT 24 Jul 17 05:03:28 PM PDT 24 6541044885 ps
T420 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1686658499 Jul 17 05:02:52 PM PDT 24 Jul 17 05:03:23 PM PDT 24 3681326698 ps
T421 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3491221388 Jul 17 05:02:42 PM PDT 24 Jul 17 05:03:10 PM PDT 24 27464762377 ps
T422 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.4135349602 Jul 17 05:02:51 PM PDT 24 Jul 17 05:03:01 PM PDT 24 688493836 ps
T423 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2324676840 Jul 17 05:02:40 PM PDT 24 Jul 17 05:04:07 PM PDT 24 19411506639 ps
T424 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2727053258 Jul 17 05:02:38 PM PDT 24 Jul 17 05:03:01 PM PDT 24 8737340495 ps
T425 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4284535422 Jul 17 05:02:53 PM PDT 24 Jul 17 05:03:16 PM PDT 24 1652915572 ps
T81 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.628606680 Jul 17 05:02:51 PM PDT 24 Jul 17 05:03:05 PM PDT 24 1647632448 ps
T426 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2429477740 Jul 17 05:03:06 PM PDT 24 Jul 17 05:04:32 PM PDT 24 15021116632 ps
T427 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.214020161 Jul 17 05:02:43 PM PDT 24 Jul 17 05:05:21 PM PDT 24 20954514313 ps
T428 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.439513713 Jul 17 05:02:54 PM PDT 24 Jul 17 05:03:05 PM PDT 24 178066903 ps
T429 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1265759513 Jul 17 05:03:02 PM PDT 24 Jul 17 05:03:35 PM PDT 24 16062543198 ps
T430 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.401682698 Jul 17 05:02:38 PM PDT 24 Jul 17 05:02:56 PM PDT 24 4943636373 ps
T431 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1641400010 Jul 17 05:02:38 PM PDT 24 Jul 17 05:03:08 PM PDT 24 2396073314 ps
T432 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2418905787 Jul 17 05:02:53 PM PDT 24 Jul 17 05:03:20 PM PDT 24 2516346284 ps
T433 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.370613931 Jul 17 05:02:41 PM PDT 24 Jul 17 05:02:56 PM PDT 24 822415090 ps
T434 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2697539011 Jul 17 05:02:52 PM PDT 24 Jul 17 05:03:23 PM PDT 24 2997704395 ps
T78 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.876705823 Jul 17 05:02:52 PM PDT 24 Jul 17 05:04:45 PM PDT 24 50741221165 ps
T435 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.662235488 Jul 17 05:02:50 PM PDT 24 Jul 17 05:03:15 PM PDT 24 2504945164 ps
T436 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3308141470 Jul 17 05:02:53 PM PDT 24 Jul 17 05:03:09 PM PDT 24 688238269 ps
T437 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.236749173 Jul 17 05:03:07 PM PDT 24 Jul 17 05:03:39 PM PDT 24 16313092297 ps
T438 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2933105925 Jul 17 05:03:08 PM PDT 24 Jul 17 05:05:20 PM PDT 24 51307669649 ps
T439 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2333155933 Jul 17 05:03:05 PM PDT 24 Jul 17 05:03:34 PM PDT 24 2607663912 ps
T440 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2363396339 Jul 17 05:02:38 PM PDT 24 Jul 17 05:02:47 PM PDT 24 176043173 ps
T441 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2456035351 Jul 17 05:03:05 PM PDT 24 Jul 17 05:03:34 PM PDT 24 6905081234 ps
T442 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2664839470 Jul 17 05:02:45 PM PDT 24 Jul 17 05:03:08 PM PDT 24 2241099258 ps
T79 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1638478992 Jul 17 05:02:52 PM PDT 24 Jul 17 05:04:59 PM PDT 24 45401875346 ps
T443 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3239326739 Jul 17 05:03:04 PM PDT 24 Jul 17 05:03:36 PM PDT 24 3749993079 ps
T109 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1701489731 Jul 17 05:02:52 PM PDT 24 Jul 17 05:04:21 PM PDT 24 2964370449 ps
T444 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.128477105 Jul 17 05:02:54 PM PDT 24 Jul 17 05:03:16 PM PDT 24 3057711993 ps
T445 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3294232829 Jul 17 05:03:08 PM PDT 24 Jul 17 05:03:33 PM PDT 24 2403379969 ps
T446 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1075978329 Jul 17 05:02:52 PM PDT 24 Jul 17 05:03:24 PM PDT 24 11910951874 ps
T447 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.753485687 Jul 17 05:02:45 PM PDT 24 Jul 17 05:03:14 PM PDT 24 11396386424 ps
T448 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3546734648 Jul 17 05:02:53 PM PDT 24 Jul 17 05:03:08 PM PDT 24 660453100 ps
T449 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3163600671 Jul 17 05:03:02 PM PDT 24 Jul 17 05:03:32 PM PDT 24 3342212449 ps
T76 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3110379299 Jul 17 05:02:37 PM PDT 24 Jul 17 05:03:13 PM PDT 24 13851784421 ps
T450 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2288085428 Jul 17 05:02:51 PM PDT 24 Jul 17 05:03:20 PM PDT 24 13574766708 ps
T105 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2647204227 Jul 17 05:03:03 PM PDT 24 Jul 17 05:04:42 PM PDT 24 12207180758 ps
T451 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.493272393 Jul 17 05:03:06 PM PDT 24 Jul 17 05:03:39 PM PDT 24 13238323405 ps
T452 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2390648084 Jul 17 05:02:43 PM PDT 24 Jul 17 05:03:13 PM PDT 24 7412671338 ps
T453 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2267916056 Jul 17 05:02:52 PM PDT 24 Jul 17 05:03:07 PM PDT 24 5048620568 ps
T454 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2261036287 Jul 17 05:03:02 PM PDT 24 Jul 17 05:06:02 PM PDT 24 4015414948 ps
T455 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2377919575 Jul 17 05:03:04 PM PDT 24 Jul 17 05:03:33 PM PDT 24 3629062302 ps
T456 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3897270249 Jul 17 05:02:42 PM PDT 24 Jul 17 05:02:51 PM PDT 24 414498073 ps
T108 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.304096117 Jul 17 05:02:40 PM PDT 24 Jul 17 05:05:34 PM PDT 24 3549382217 ps
T457 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3272255731 Jul 17 05:02:43 PM PDT 24 Jul 17 05:03:04 PM PDT 24 1800277535 ps
T458 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1806017463 Jul 17 05:02:40 PM PDT 24 Jul 17 05:03:02 PM PDT 24 1904956099 ps

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.139017377
Short name T6
Test name
Test status
Simulation time 94713058450 ps
CPU time 8951.62 seconds
Started Jul 17 05:03:21 PM PDT 24
Finished Jul 17 07:32:36 PM PDT 24
Peak memory 235796 kb
Host smart-675d3b5c-e88f-476f-9ce2-939debb4cd03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139017377 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.139017377
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3460955472
Short name T13
Test name
Test status
Simulation time 261680985627 ps
CPU time 694.55 seconds
Started Jul 17 05:04:26 PM PDT 24
Finished Jul 17 05:16:04 PM PDT 24
Peak memory 234168 kb
Host smart-e15f5176-995b-47be-a27e-78b87039eceb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460955472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3460955472
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.1635223553
Short name T11
Test name
Test status
Simulation time 152453296770 ps
CPU time 1376.83 seconds
Started Jul 17 05:04:27 PM PDT 24
Finished Jul 17 05:27:26 PM PDT 24
Peak memory 238144 kb
Host smart-c6cc7131-eac7-402a-b5e1-c4f2f6658c3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635223553 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.1635223553
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.730577779
Short name T45
Test name
Test status
Simulation time 9618571232 ps
CPU time 167.51 seconds
Started Jul 17 05:02:53 PM PDT 24
Finished Jul 17 05:05:44 PM PDT 24
Peak memory 213476 kb
Host smart-c9ee9c0d-8e7a-4ea0-b58f-1b9c89a0e823
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730577779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.730577779
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2443687819
Short name T35
Test name
Test status
Simulation time 70306366908 ps
CPU time 779.03 seconds
Started Jul 17 05:04:38 PM PDT 24
Finished Jul 17 05:17:39 PM PDT 24
Peak memory 225752 kb
Host smart-fb1b7399-9da7-45f1-876e-ac5e9f9e2fca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443687819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2443687819
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2636719795
Short name T4
Test name
Test status
Simulation time 4284148991 ps
CPU time 138.3 seconds
Started Jul 17 05:03:06 PM PDT 24
Finished Jul 17 05:05:28 PM PDT 24
Peak memory 238376 kb
Host smart-851617e7-c148-497c-a1cb-562ff990e885
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636719795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2636719795
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.471762826
Short name T57
Test name
Test status
Simulation time 13230428542 ps
CPU time 130.95 seconds
Started Jul 17 05:02:53 PM PDT 24
Finished Jul 17 05:05:07 PM PDT 24
Peak memory 214800 kb
Host smart-de484494-4272-4c53-a4b5-e01c3498d71d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471762826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.471762826
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.304096117
Short name T108
Test name
Test status
Simulation time 3549382217 ps
CPU time 172.56 seconds
Started Jul 17 05:02:40 PM PDT 24
Finished Jul 17 05:05:34 PM PDT 24
Peak memory 213636 kb
Host smart-4578cdc9-d7f2-4d1d-b3d6-b4799477d532
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304096117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.304096117
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1625809197
Short name T14
Test name
Test status
Simulation time 2061757191 ps
CPU time 38.41 seconds
Started Jul 17 05:04:18 PM PDT 24
Finished Jul 17 05:04:58 PM PDT 24
Peak memory 216424 kb
Host smart-67c7d0cb-8d36-4473-9ab5-5fe668d5bffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625809197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1625809197
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.380745890
Short name T99
Test name
Test status
Simulation time 3485968671 ps
CPU time 158.49 seconds
Started Jul 17 05:03:05 PM PDT 24
Finished Jul 17 05:05:47 PM PDT 24
Peak memory 213784 kb
Host smart-d7b26695-b390-4771-baf1-bb9f5114f6b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380745890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.380745890
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2628100573
Short name T1
Test name
Test status
Simulation time 167425006 ps
CPU time 8.38 seconds
Started Jul 17 05:03:19 PM PDT 24
Finished Jul 17 05:03:29 PM PDT 24
Peak memory 216972 kb
Host smart-e452d443-fa9f-4821-82f6-78bcf94c1216
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628100573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2628100573
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.89847813
Short name T33
Test name
Test status
Simulation time 1374783009 ps
CPU time 19.11 seconds
Started Jul 17 05:03:21 PM PDT 24
Finished Jul 17 05:03:43 PM PDT 24
Peak memory 219240 kb
Host smart-fbc9e071-9e49-4229-9890-394e5f7099c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89847813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.89847813
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1435522641
Short name T134
Test name
Test status
Simulation time 5213531705 ps
CPU time 45.02 seconds
Started Jul 17 05:03:30 PM PDT 24
Finished Jul 17 05:04:17 PM PDT 24
Peak memory 219364 kb
Host smart-18a01aee-e540-4a5c-8ef7-2e66db5c1fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435522641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1435522641
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2946919
Short name T82
Test name
Test status
Simulation time 16006102506 ps
CPU time 23.39 seconds
Started Jul 17 05:04:47 PM PDT 24
Finished Jul 17 05:05:12 PM PDT 24
Peak memory 212012 kb
Host smart-65185755-1b88-414f-8482-79fa1351037d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2946919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2946919
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.987969992
Short name T101
Test name
Test status
Simulation time 429777045 ps
CPU time 156.36 seconds
Started Jul 17 05:02:41 PM PDT 24
Finished Jul 17 05:05:19 PM PDT 24
Peak memory 214680 kb
Host smart-2c96bd0e-03b8-4d05-b669-cb1144d57378
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987969992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.987969992
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3728821597
Short name T74
Test name
Test status
Simulation time 76929546583 ps
CPU time 163.04 seconds
Started Jul 17 05:02:52 PM PDT 24
Finished Jul 17 05:05:38 PM PDT 24
Peak memory 214644 kb
Host smart-a833f1e4-0b67-41e1-9c4a-4574be384b9a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728821597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3728821597
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1806017463
Short name T458
Test name
Test status
Simulation time 1904956099 ps
CPU time 20.05 seconds
Started Jul 17 05:02:40 PM PDT 24
Finished Jul 17 05:03:02 PM PDT 24
Peak memory 210576 kb
Host smart-84987d26-fba3-40ee-8b92-46a702f67104
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806017463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1806017463
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3272255731
Short name T457
Test name
Test status
Simulation time 1800277535 ps
CPU time 19.62 seconds
Started Jul 17 05:02:43 PM PDT 24
Finished Jul 17 05:03:04 PM PDT 24
Peak memory 210700 kb
Host smart-d941625c-b356-485b-96e1-00e9a61beeb2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272255731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3272255731
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3341482613
Short name T47
Test name
Test status
Simulation time 2577352676 ps
CPU time 30.1 seconds
Started Jul 17 05:02:41 PM PDT 24
Finished Jul 17 05:03:13 PM PDT 24
Peak memory 211060 kb
Host smart-7fd66ecc-75f1-42da-bfad-65263d678ae9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341482613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3341482613
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2390648084
Short name T452
Test name
Test status
Simulation time 7412671338 ps
CPU time 28.2 seconds
Started Jul 17 05:02:43 PM PDT 24
Finished Jul 17 05:03:13 PM PDT 24
Peak memory 213828 kb
Host smart-0aa2fbe4-490c-4630-8a5d-d257a568cb04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390648084 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2390648084
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1788387742
Short name T401
Test name
Test status
Simulation time 264188232 ps
CPU time 8.32 seconds
Started Jul 17 05:02:43 PM PDT 24
Finished Jul 17 05:02:52 PM PDT 24
Peak memory 210200 kb
Host smart-34bda1cd-d0e4-4d25-a0c6-7067a5549d31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788387742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1788387742
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1827101857
Short name T366
Test name
Test status
Simulation time 170932765 ps
CPU time 8.01 seconds
Started Jul 17 05:02:42 PM PDT 24
Finished Jul 17 05:02:51 PM PDT 24
Peak memory 210140 kb
Host smart-03ec8d10-e70b-4ec2-859d-17326d81efd5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827101857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1827101857
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.9192508
Short name T398
Test name
Test status
Simulation time 2450652579 ps
CPU time 13.03 seconds
Started Jul 17 05:02:40 PM PDT 24
Finished Jul 17 05:02:54 PM PDT 24
Peak memory 210212 kb
Host smart-70907902-cae5-4540-b055-ca40eb4c4bac
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9192508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.9192508
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2802250059
Short name T88
Test name
Test status
Simulation time 2163348987 ps
CPU time 56.72 seconds
Started Jul 17 05:02:36 PM PDT 24
Finished Jul 17 05:03:34 PM PDT 24
Peak memory 213452 kb
Host smart-9c0c8627-4a91-4ff3-8f42-c949e2001463
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802250059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2802250059
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2727053258
Short name T424
Test name
Test status
Simulation time 8737340495 ps
CPU time 22.53 seconds
Started Jul 17 05:02:38 PM PDT 24
Finished Jul 17 05:03:01 PM PDT 24
Peak memory 212376 kb
Host smart-ebc5b1ad-4201-43c8-8ab2-f55be7917f1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727053258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2727053258
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2561954029
Short name T394
Test name
Test status
Simulation time 7833175308 ps
CPU time 31.68 seconds
Started Jul 17 05:02:36 PM PDT 24
Finished Jul 17 05:03:09 PM PDT 24
Peak memory 218580 kb
Host smart-353dc8f8-7118-4b67-bcef-318d28efc628
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561954029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2561954029
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3110379299
Short name T76
Test name
Test status
Simulation time 13851784421 ps
CPU time 34.78 seconds
Started Jul 17 05:02:37 PM PDT 24
Finished Jul 17 05:03:13 PM PDT 24
Peak memory 211408 kb
Host smart-7bd0ca10-d88b-4fb6-b3e9-e9489afbf922
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110379299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3110379299
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2103708312
Short name T95
Test name
Test status
Simulation time 1645546878 ps
CPU time 18.14 seconds
Started Jul 17 05:02:42 PM PDT 24
Finished Jul 17 05:03:01 PM PDT 24
Peak memory 211160 kb
Host smart-0697e56b-4e68-428a-b930-2a5f495ab06e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103708312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2103708312
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2520009509
Short name T369
Test name
Test status
Simulation time 7523962877 ps
CPU time 36.09 seconds
Started Jul 17 05:02:43 PM PDT 24
Finished Jul 17 05:03:20 PM PDT 24
Peak memory 211640 kb
Host smart-8cfc1303-cbea-4488-85bd-71449969acab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520009509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2520009509
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2710352820
Short name T405
Test name
Test status
Simulation time 3022975040 ps
CPU time 26.02 seconds
Started Jul 17 05:02:45 PM PDT 24
Finished Jul 17 05:03:11 PM PDT 24
Peak memory 215184 kb
Host smart-1550e5b9-a43f-4045-81ba-6fc90bcc5f4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710352820 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2710352820
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.370613931
Short name T433
Test name
Test status
Simulation time 822415090 ps
CPU time 14.2 seconds
Started Jul 17 05:02:41 PM PDT 24
Finished Jul 17 05:02:56 PM PDT 24
Peak memory 210228 kb
Host smart-9b2c945b-ed17-42b0-b38d-8b413b614d1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370613931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.370613931
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.401682698
Short name T430
Test name
Test status
Simulation time 4943636373 ps
CPU time 16.05 seconds
Started Jul 17 05:02:38 PM PDT 24
Finished Jul 17 05:02:56 PM PDT 24
Peak memory 210232 kb
Host smart-dc1bf01c-9eb9-479a-b836-96997974a80f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401682698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.401682698
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2811723700
Short name T413
Test name
Test status
Simulation time 3081398846 ps
CPU time 27.56 seconds
Started Jul 17 05:02:40 PM PDT 24
Finished Jul 17 05:03:09 PM PDT 24
Peak memory 210200 kb
Host smart-2eddcbd0-3ae6-44bb-a7b8-c1647a9acfd1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811723700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2811723700
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2324676840
Short name T423
Test name
Test status
Simulation time 19411506639 ps
CPU time 85.21 seconds
Started Jul 17 05:02:40 PM PDT 24
Finished Jul 17 05:04:07 PM PDT 24
Peak memory 214608 kb
Host smart-cddfb3e0-e42e-4be5-adc1-7a1be5f1d981
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324676840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2324676840
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2664839470
Short name T442
Test name
Test status
Simulation time 2241099258 ps
CPU time 22.03 seconds
Started Jul 17 05:02:45 PM PDT 24
Finished Jul 17 05:03:08 PM PDT 24
Peak memory 211924 kb
Host smart-7e36054b-9aee-45fd-82e4-6a450fb33453
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664839470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2664839470
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.753485687
Short name T447
Test name
Test status
Simulation time 11396386424 ps
CPU time 28.81 seconds
Started Jul 17 05:02:45 PM PDT 24
Finished Jul 17 05:03:14 PM PDT 24
Peak memory 218580 kb
Host smart-f2519b84-a59e-4d32-9ef3-f992404afdc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753485687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.753485687
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2418905787
Short name T432
Test name
Test status
Simulation time 2516346284 ps
CPU time 23.21 seconds
Started Jul 17 05:02:53 PM PDT 24
Finished Jul 17 05:03:20 PM PDT 24
Peak memory 216756 kb
Host smart-cbf3531c-78ce-41e1-99c4-1807a4f73228
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418905787 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2418905787
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.424710992
Short name T395
Test name
Test status
Simulation time 1373028103 ps
CPU time 10.41 seconds
Started Jul 17 05:03:02 PM PDT 24
Finished Jul 17 05:03:14 PM PDT 24
Peak memory 210600 kb
Host smart-6fe27b6b-dace-4f7f-a3f6-5b71c0901dee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424710992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.424710992
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3163600671
Short name T449
Test name
Test status
Simulation time 3342212449 ps
CPU time 28.81 seconds
Started Jul 17 05:03:02 PM PDT 24
Finished Jul 17 05:03:32 PM PDT 24
Peak memory 211712 kb
Host smart-1c47505e-6e33-4ec8-b376-9e87d85ce140
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163600671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3163600671
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3602060614
Short name T390
Test name
Test status
Simulation time 9158146186 ps
CPU time 36.76 seconds
Started Jul 17 05:02:53 PM PDT 24
Finished Jul 17 05:03:33 PM PDT 24
Peak memory 217140 kb
Host smart-62ba0433-3034-474d-9c0f-bf55b062c83f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602060614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3602060614
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.544531126
Short name T103
Test name
Test status
Simulation time 1097846965 ps
CPU time 157.14 seconds
Started Jul 17 05:02:54 PM PDT 24
Finished Jul 17 05:05:34 PM PDT 24
Peak memory 212520 kb
Host smart-11fd54fb-836b-4ef3-90f3-7f0b46b4509c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544531126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.544531126
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3176198257
Short name T373
Test name
Test status
Simulation time 3102514454 ps
CPU time 18.01 seconds
Started Jul 17 05:02:53 PM PDT 24
Finished Jul 17 05:03:14 PM PDT 24
Peak memory 216784 kb
Host smart-30e1ef6e-bd0d-47d5-b3a7-1e7ee95e99a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176198257 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3176198257
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2742748197
Short name T62
Test name
Test status
Simulation time 8678495377 ps
CPU time 16.78 seconds
Started Jul 17 05:02:50 PM PDT 24
Finished Jul 17 05:03:08 PM PDT 24
Peak memory 210668 kb
Host smart-3682568d-4b8f-46b3-80b1-e282140c08d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742748197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2742748197
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3883105856
Short name T94
Test name
Test status
Simulation time 8988765532 ps
CPU time 94.05 seconds
Started Jul 17 05:03:02 PM PDT 24
Finished Jul 17 05:04:37 PM PDT 24
Peak memory 213340 kb
Host smart-08f2ba00-53af-4509-b6b1-af08b701292d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883105856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3883105856
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3382214651
Short name T58
Test name
Test status
Simulation time 688594930 ps
CPU time 8.33 seconds
Started Jul 17 05:02:52 PM PDT 24
Finished Jul 17 05:03:04 PM PDT 24
Peak memory 210652 kb
Host smart-59cf7195-8321-41fb-bfaf-42c5cbe2c792
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382214651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3382214651
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2524257411
Short name T362
Test name
Test status
Simulation time 611679851 ps
CPU time 14.01 seconds
Started Jul 17 05:02:55 PM PDT 24
Finished Jul 17 05:03:11 PM PDT 24
Peak memory 217164 kb
Host smart-42af4d93-afc3-4dd9-b3a6-5bd833c47f20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524257411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2524257411
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2929377773
Short name T44
Test name
Test status
Simulation time 477720195 ps
CPU time 82.74 seconds
Started Jul 17 05:02:52 PM PDT 24
Finished Jul 17 05:04:18 PM PDT 24
Peak memory 212196 kb
Host smart-16d24a2e-d9aa-406f-b7bd-0446f3b01608
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929377773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2929377773
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4265827553
Short name T375
Test name
Test status
Simulation time 6057839361 ps
CPU time 33.03 seconds
Started Jul 17 05:02:51 PM PDT 24
Finished Jul 17 05:03:27 PM PDT 24
Peak memory 214520 kb
Host smart-9113fdb9-f3e5-4162-af43-129109ec99e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265827553 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.4265827553
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.304125479
Short name T59
Test name
Test status
Simulation time 687930211 ps
CPU time 7.86 seconds
Started Jul 17 05:02:50 PM PDT 24
Finished Jul 17 05:02:58 PM PDT 24
Peak memory 210388 kb
Host smart-55f9cad7-b832-4ca6-b479-27b52334ae15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304125479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.304125479
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1638478992
Short name T79
Test name
Test status
Simulation time 45401875346 ps
CPU time 124.24 seconds
Started Jul 17 05:02:52 PM PDT 24
Finished Jul 17 05:04:59 PM PDT 24
Peak memory 218580 kb
Host smart-5fc2eebe-697c-4b47-847d-c4a3fc5228ff
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638478992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1638478992
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.439513713
Short name T428
Test name
Test status
Simulation time 178066903 ps
CPU time 8.28 seconds
Started Jul 17 05:02:54 PM PDT 24
Finished Jul 17 05:03:05 PM PDT 24
Peak memory 210720 kb
Host smart-0027fda1-cbe8-4b1a-a889-576e5920aad2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439513713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.439513713
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3308141470
Short name T436
Test name
Test status
Simulation time 688238269 ps
CPU time 12.57 seconds
Started Jul 17 05:02:53 PM PDT 24
Finished Jul 17 05:03:09 PM PDT 24
Peak memory 218524 kb
Host smart-a26c3526-54fb-4d8a-977f-e2c0f9df69e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308141470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3308141470
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.4178990218
Short name T386
Test name
Test status
Simulation time 578270197 ps
CPU time 8.86 seconds
Started Jul 17 05:03:04 PM PDT 24
Finished Jul 17 05:03:14 PM PDT 24
Peak memory 215124 kb
Host smart-2e6936d6-b2c2-405f-8f25-47a52341b4f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178990218 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.4178990218
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3730088432
Short name T380
Test name
Test status
Simulation time 6302113963 ps
CPU time 14.46 seconds
Started Jul 17 05:03:05 PM PDT 24
Finished Jul 17 05:03:22 PM PDT 24
Peak memory 210876 kb
Host smart-5f783753-753b-4663-a0ba-251168087799
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730088432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3730088432
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.965069352
Short name T56
Test name
Test status
Simulation time 2460550103 ps
CPU time 56.49 seconds
Started Jul 17 05:02:53 PM PDT 24
Finished Jul 17 05:03:53 PM PDT 24
Peak memory 214092 kb
Host smart-6b6ee535-5d0e-4e1f-b54b-869337a9b8d6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965069352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.965069352
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2333155933
Short name T439
Test name
Test status
Simulation time 2607663912 ps
CPU time 24.64 seconds
Started Jul 17 05:03:05 PM PDT 24
Finished Jul 17 05:03:34 PM PDT 24
Peak memory 211708 kb
Host smart-867ba1b4-b6b3-46dc-b5bf-1b0c7368bb84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333155933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2333155933
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.154471118
Short name T411
Test name
Test status
Simulation time 1674135874 ps
CPU time 16.29 seconds
Started Jul 17 05:02:52 PM PDT 24
Finished Jul 17 05:03:11 PM PDT 24
Peak memory 217672 kb
Host smart-c7f55400-5972-4c9f-9d77-9454ecf5d651
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154471118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.154471118
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2228121141
Short name T107
Test name
Test status
Simulation time 18261488601 ps
CPU time 172.45 seconds
Started Jul 17 05:03:05 PM PDT 24
Finished Jul 17 05:06:00 PM PDT 24
Peak memory 213844 kb
Host smart-fee2f1ee-1036-43d8-8322-dc2d4f57edd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228121141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2228121141
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2446099988
Short name T378
Test name
Test status
Simulation time 9096148270 ps
CPU time 29.86 seconds
Started Jul 17 05:03:04 PM PDT 24
Finished Jul 17 05:03:35 PM PDT 24
Peak memory 216820 kb
Host smart-eec48cd3-fefc-468f-a1b0-e016f51bd008
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446099988 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2446099988
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3294232829
Short name T445
Test name
Test status
Simulation time 2403379969 ps
CPU time 21.88 seconds
Started Jul 17 05:03:08 PM PDT 24
Finished Jul 17 05:03:33 PM PDT 24
Peak memory 211176 kb
Host smart-6d9a100a-96b1-40da-8de6-d16ba6cab6d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294232829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3294232829
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.950069689
Short name T400
Test name
Test status
Simulation time 1091876514 ps
CPU time 57.08 seconds
Started Jul 17 05:03:05 PM PDT 24
Finished Jul 17 05:04:06 PM PDT 24
Peak memory 213432 kb
Host smart-5809b89d-9a14-49c0-a499-c4269e9d39fc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950069689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa
ssthru_mem_tl_intg_err.950069689
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3239326739
Short name T443
Test name
Test status
Simulation time 3749993079 ps
CPU time 29.17 seconds
Started Jul 17 05:03:04 PM PDT 24
Finished Jul 17 05:03:36 PM PDT 24
Peak memory 211924 kb
Host smart-0dbce6c5-4245-4589-8418-437c4a5d1734
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239326739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3239326739
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3590686420
Short name T379
Test name
Test status
Simulation time 4328317867 ps
CPU time 24.86 seconds
Started Jul 17 05:03:04 PM PDT 24
Finished Jul 17 05:03:30 PM PDT 24
Peak memory 218596 kb
Host smart-d3cd3f09-010c-469e-a475-30b397e9b53e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590686420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3590686420
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.392690049
Short name T106
Test name
Test status
Simulation time 3812920321 ps
CPU time 102.15 seconds
Started Jul 17 05:03:05 PM PDT 24
Finished Jul 17 05:04:51 PM PDT 24
Peak memory 213188 kb
Host smart-401c6fe8-f99e-4cda-8aa7-7578dab8a12c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392690049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.392690049
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1884498333
Short name T364
Test name
Test status
Simulation time 4271970513 ps
CPU time 33.55 seconds
Started Jul 17 05:03:04 PM PDT 24
Finished Jul 17 05:03:40 PM PDT 24
Peak memory 218568 kb
Host smart-ffbb444a-f437-4b4d-8d04-20395a82e3b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884498333 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1884498333
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1657855267
Short name T384
Test name
Test status
Simulation time 1650536770 ps
CPU time 8.29 seconds
Started Jul 17 05:03:04 PM PDT 24
Finished Jul 17 05:03:15 PM PDT 24
Peak memory 210420 kb
Host smart-964c6ff9-3053-4c85-8141-281b33cb6e3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657855267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1657855267
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2429477740
Short name T426
Test name
Test status
Simulation time 15021116632 ps
CPU time 81.45 seconds
Started Jul 17 05:03:06 PM PDT 24
Finished Jul 17 05:04:32 PM PDT 24
Peak memory 214660 kb
Host smart-c819454e-5675-4e4e-a042-50a6b8e60886
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429477740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2429477740
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.991433829
Short name T406
Test name
Test status
Simulation time 7108953463 ps
CPU time 25.45 seconds
Started Jul 17 05:03:05 PM PDT 24
Finished Jul 17 05:03:34 PM PDT 24
Peak memory 212284 kb
Host smart-f8ca7122-cd8a-483d-a2c1-651aa04a8191
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991433829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.991433829
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1736984832
Short name T396
Test name
Test status
Simulation time 11880743909 ps
CPU time 33.57 seconds
Started Jul 17 05:03:04 PM PDT 24
Finished Jul 17 05:03:39 PM PDT 24
Peak memory 217292 kb
Host smart-87618190-06f6-45d4-adc8-942ab40289f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736984832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1736984832
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1800891578
Short name T97
Test name
Test status
Simulation time 251145974 ps
CPU time 81.22 seconds
Started Jul 17 05:03:06 PM PDT 24
Finished Jul 17 05:04:31 PM PDT 24
Peak memory 213088 kb
Host smart-2ca56ca2-a815-49cb-bae7-5ebe091e161c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800891578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1800891578
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2289584665
Short name T415
Test name
Test status
Simulation time 13286695912 ps
CPU time 28.35 seconds
Started Jul 17 05:03:03 PM PDT 24
Finished Jul 17 05:03:33 PM PDT 24
Peak memory 215748 kb
Host smart-8f683afc-fa3d-44f2-a87f-7c637dfbe7f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289584665 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2289584665
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.844710736
Short name T419
Test name
Test status
Simulation time 6541044885 ps
CPU time 17.92 seconds
Started Jul 17 05:03:06 PM PDT 24
Finished Jul 17 05:03:28 PM PDT 24
Peak memory 211928 kb
Host smart-d8caf511-ce3f-408e-972d-a56131de260f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844710736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.844710736
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2362979622
Short name T387
Test name
Test status
Simulation time 7419549498 ps
CPU time 87.99 seconds
Started Jul 17 05:03:04 PM PDT 24
Finished Jul 17 05:04:34 PM PDT 24
Peak memory 214584 kb
Host smart-6b7211c4-695b-4a82-905e-d21cd429efab
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362979622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2362979622
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2456035351
Short name T441
Test name
Test status
Simulation time 6905081234 ps
CPU time 25.87 seconds
Started Jul 17 05:03:05 PM PDT 24
Finished Jul 17 05:03:34 PM PDT 24
Peak memory 212260 kb
Host smart-672156c1-8386-4f82-9a1c-bb0aa0b5c657
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456035351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2456035351
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.493272393
Short name T451
Test name
Test status
Simulation time 13238323405 ps
CPU time 29.27 seconds
Started Jul 17 05:03:06 PM PDT 24
Finished Jul 17 05:03:39 PM PDT 24
Peak memory 218572 kb
Host smart-106138a0-a043-4e0b-8901-eacf3f6bc789
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493272393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.493272393
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2261036287
Short name T454
Test name
Test status
Simulation time 4015414948 ps
CPU time 178.98 seconds
Started Jul 17 05:03:02 PM PDT 24
Finished Jul 17 05:06:02 PM PDT 24
Peak memory 213664 kb
Host smart-87d8600d-6c1e-477c-b162-fde4caaeb292
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261036287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2261036287
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.141830544
Short name T365
Test name
Test status
Simulation time 378142137 ps
CPU time 9.85 seconds
Started Jul 17 05:03:03 PM PDT 24
Finished Jul 17 05:03:15 PM PDT 24
Peak memory 216860 kb
Host smart-e225cb11-ccc9-47f6-a90b-c3ac7750a9de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141830544 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.141830544
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.717935203
Short name T80
Test name
Test status
Simulation time 6089126979 ps
CPU time 33.21 seconds
Started Jul 17 05:03:06 PM PDT 24
Finished Jul 17 05:03:43 PM PDT 24
Peak memory 211344 kb
Host smart-86f60356-6f8d-4069-9862-ca7b184e234b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717935203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.717935203
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3135373370
Short name T376
Test name
Test status
Simulation time 35573630816 ps
CPU time 130.24 seconds
Started Jul 17 05:03:04 PM PDT 24
Finished Jul 17 05:05:17 PM PDT 24
Peak memory 213684 kb
Host smart-6b7ef592-3032-48af-9d3f-171c0dc622bd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135373370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3135373370
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2377919575
Short name T455
Test name
Test status
Simulation time 3629062302 ps
CPU time 26.23 seconds
Started Jul 17 05:03:04 PM PDT 24
Finished Jul 17 05:03:33 PM PDT 24
Peak memory 212132 kb
Host smart-eb397442-bbb0-44b9-be52-49685e548fcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377919575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2377919575
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.587596599
Short name T370
Test name
Test status
Simulation time 1413886818 ps
CPU time 23.3 seconds
Started Jul 17 05:03:06 PM PDT 24
Finished Jul 17 05:03:33 PM PDT 24
Peak memory 218460 kb
Host smart-8f6fe966-abf5-4181-ab5d-0bd948cda78b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587596599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.587596599
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1026809605
Short name T374
Test name
Test status
Simulation time 14589763351 ps
CPU time 34.19 seconds
Started Jul 17 05:03:06 PM PDT 24
Finished Jul 17 05:03:43 PM PDT 24
Peak memory 215848 kb
Host smart-bfeb80aa-430a-4eb1-bffc-9d6f384bc933
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026809605 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1026809605
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.777316751
Short name T402
Test name
Test status
Simulation time 12559064069 ps
CPU time 27.08 seconds
Started Jul 17 05:03:05 PM PDT 24
Finished Jul 17 05:03:36 PM PDT 24
Peak memory 212068 kb
Host smart-cc3ab503-e47f-4f06-a92e-456257ca4a07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777316751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.777316751
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1194472713
Short name T63
Test name
Test status
Simulation time 62759092356 ps
CPU time 114.56 seconds
Started Jul 17 05:03:05 PM PDT 24
Finished Jul 17 05:05:02 PM PDT 24
Peak memory 215140 kb
Host smart-dfbb199e-8cad-4052-83b2-5baf901c15b3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194472713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1194472713
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3154890941
Short name T92
Test name
Test status
Simulation time 2393229804 ps
CPU time 26.65 seconds
Started Jul 17 05:03:05 PM PDT 24
Finished Jul 17 05:03:34 PM PDT 24
Peak memory 211932 kb
Host smart-5c4a4380-a28a-42c3-8517-7cc0581cf990
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154890941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3154890941
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1907090267
Short name T372
Test name
Test status
Simulation time 2777968066 ps
CPU time 28.69 seconds
Started Jul 17 05:03:04 PM PDT 24
Finished Jul 17 05:03:35 PM PDT 24
Peak memory 218152 kb
Host smart-ab285e46-981f-432f-9354-8703a743485d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907090267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1907090267
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2571675322
Short name T46
Test name
Test status
Simulation time 1174545476 ps
CPU time 155.49 seconds
Started Jul 17 05:03:03 PM PDT 24
Finished Jul 17 05:05:40 PM PDT 24
Peak memory 212352 kb
Host smart-d3645764-2a76-4fc0-abe9-10998a8bc7bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571675322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2571675322
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.236749173
Short name T437
Test name
Test status
Simulation time 16313092297 ps
CPU time 28.91 seconds
Started Jul 17 05:03:07 PM PDT 24
Finished Jul 17 05:03:39 PM PDT 24
Peak memory 216680 kb
Host smart-754b44ab-5d45-42dc-aea1-0c74ce4c9c01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236749173 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.236749173
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2537722808
Short name T60
Test name
Test status
Simulation time 11794024785 ps
CPU time 26.16 seconds
Started Jul 17 05:03:03 PM PDT 24
Finished Jul 17 05:03:30 PM PDT 24
Peak memory 211548 kb
Host smart-e83c9d75-ae93-45f9-a3a3-c4945d992c52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537722808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2537722808
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2933105925
Short name T438
Test name
Test status
Simulation time 51307669649 ps
CPU time 128.66 seconds
Started Jul 17 05:03:08 PM PDT 24
Finished Jul 17 05:05:20 PM PDT 24
Peak memory 214496 kb
Host smart-b9a68af2-899e-4bc2-a1d0-c7c675fdeca7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933105925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2933105925
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1871981356
Short name T385
Test name
Test status
Simulation time 15582265458 ps
CPU time 32.83 seconds
Started Jul 17 05:03:05 PM PDT 24
Finished Jul 17 05:03:42 PM PDT 24
Peak memory 212044 kb
Host smart-19557cc7-1baa-408e-9e71-c1475cb7d801
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871981356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1871981356
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4228290231
Short name T417
Test name
Test status
Simulation time 1893607726 ps
CPU time 22.12 seconds
Started Jul 17 05:03:04 PM PDT 24
Finished Jul 17 05:03:29 PM PDT 24
Peak memory 215928 kb
Host smart-52a423cb-1451-4c42-9635-ddb766019e67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228290231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.4228290231
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2647204227
Short name T105
Test name
Test status
Simulation time 12207180758 ps
CPU time 98.23 seconds
Started Jul 17 05:03:03 PM PDT 24
Finished Jul 17 05:04:42 PM PDT 24
Peak memory 213380 kb
Host smart-241da01c-98c4-4375-90cf-385328e5484b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647204227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2647204227
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.322074030
Short name T55
Test name
Test status
Simulation time 1152141698 ps
CPU time 15.61 seconds
Started Jul 17 05:02:43 PM PDT 24
Finished Jul 17 05:03:00 PM PDT 24
Peak memory 211468 kb
Host smart-198f14fd-313a-4009-b35c-bbba6a1f2d91
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322074030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.322074030
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1527882886
Short name T367
Test name
Test status
Simulation time 4225145548 ps
CPU time 31.66 seconds
Started Jul 17 05:02:43 PM PDT 24
Finished Jul 17 05:03:16 PM PDT 24
Peak memory 210988 kb
Host smart-8d10783c-d2bd-4c99-ba1d-b1652ab11ca0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527882886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1527882886
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3330747264
Short name T408
Test name
Test status
Simulation time 6563270541 ps
CPU time 34.51 seconds
Started Jul 17 05:02:43 PM PDT 24
Finished Jul 17 05:03:19 PM PDT 24
Peak memory 211836 kb
Host smart-39d61c50-c1b8-4b39-87fe-0c4b596b0f87
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330747264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3330747264
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2363396339
Short name T440
Test name
Test status
Simulation time 176043173 ps
CPU time 8.65 seconds
Started Jul 17 05:02:38 PM PDT 24
Finished Jul 17 05:02:47 PM PDT 24
Peak memory 213548 kb
Host smart-f0083d7a-6c1f-42a7-ab95-ec0bb35937f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363396339 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2363396339
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3491221388
Short name T421
Test name
Test status
Simulation time 27464762377 ps
CPU time 27.11 seconds
Started Jul 17 05:02:42 PM PDT 24
Finished Jul 17 05:03:10 PM PDT 24
Peak memory 211712 kb
Host smart-10389884-d4c5-41cc-9803-0e6dffd3d772
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491221388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3491221388
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3897270249
Short name T456
Test name
Test status
Simulation time 414498073 ps
CPU time 8.1 seconds
Started Jul 17 05:02:42 PM PDT 24
Finished Jul 17 05:02:51 PM PDT 24
Peak memory 210072 kb
Host smart-440a8695-bb29-4763-9999-cf75678e21cc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897270249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3897270249
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3523316237
Short name T383
Test name
Test status
Simulation time 13356522434 ps
CPU time 21.29 seconds
Started Jul 17 05:02:37 PM PDT 24
Finished Jul 17 05:03:00 PM PDT 24
Peak memory 210500 kb
Host smart-9b87ae0e-272d-413c-92bf-926d5379b481
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523316237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3523316237
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.214020161
Short name T427
Test name
Test status
Simulation time 20954514313 ps
CPU time 157.14 seconds
Started Jul 17 05:02:43 PM PDT 24
Finished Jul 17 05:05:21 PM PDT 24
Peak memory 214680 kb
Host smart-f72084ff-c61c-44b3-9d5b-068342063836
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214020161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pas
sthru_mem_tl_intg_err.214020161
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1454372167
Short name T91
Test name
Test status
Simulation time 8022262815 ps
CPU time 33.48 seconds
Started Jul 17 05:02:39 PM PDT 24
Finished Jul 17 05:03:14 PM PDT 24
Peak memory 212116 kb
Host smart-9c4b05fd-322c-4497-a9b2-d49f13522892
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454372167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1454372167
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2176837225
Short name T404
Test name
Test status
Simulation time 4135488971 ps
CPU time 34.7 seconds
Started Jul 17 05:02:38 PM PDT 24
Finished Jul 17 05:03:15 PM PDT 24
Peak memory 218512 kb
Host smart-a7ae7a9c-221b-4656-b91d-02593b061341
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176837225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2176837225
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2271693506
Short name T389
Test name
Test status
Simulation time 12643873038 ps
CPU time 94.09 seconds
Started Jul 17 05:02:38 PM PDT 24
Finished Jul 17 05:04:14 PM PDT 24
Peak memory 213112 kb
Host smart-002e314d-a90f-4f93-8530-774370e531dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271693506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2271693506
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.4884495
Short name T93
Test name
Test status
Simulation time 8202827877 ps
CPU time 33.56 seconds
Started Jul 17 05:02:51 PM PDT 24
Finished Jul 17 05:03:27 PM PDT 24
Peak memory 211280 kb
Host smart-df05f0b3-adc0-4471-9ad6-0263f28fb324
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4884495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_aliasin
g.4884495
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3516607919
Short name T409
Test name
Test status
Simulation time 842899703 ps
CPU time 13.81 seconds
Started Jul 17 05:02:53 PM PDT 24
Finished Jul 17 05:03:10 PM PDT 24
Peak memory 210284 kb
Host smart-8ee51e3e-365a-47c2-85f4-ef73b90b9c47
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516607919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3516607919
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.424516502
Short name T75
Test name
Test status
Simulation time 2320799332 ps
CPU time 28.67 seconds
Started Jul 17 05:02:39 PM PDT 24
Finished Jul 17 05:03:09 PM PDT 24
Peak memory 211292 kb
Host smart-e6ae5ac7-e78f-400a-a18f-2ef893a8ee65
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424516502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.424516502
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.128477105
Short name T444
Test name
Test status
Simulation time 3057711993 ps
CPU time 18.68 seconds
Started Jul 17 05:02:54 PM PDT 24
Finished Jul 17 05:03:16 PM PDT 24
Peak memory 217280 kb
Host smart-9b8b63e8-f70d-4eec-93aa-66c5c89dfe95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128477105 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.128477105
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.628606680
Short name T81
Test name
Test status
Simulation time 1647632448 ps
CPU time 11.02 seconds
Started Jul 17 05:02:51 PM PDT 24
Finished Jul 17 05:03:05 PM PDT 24
Peak memory 210416 kb
Host smart-571098f5-2c8e-4e76-a729-e3ed489f43b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628606680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.628606680
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2267724663
Short name T363
Test name
Test status
Simulation time 6062578409 ps
CPU time 26.66 seconds
Started Jul 17 05:02:40 PM PDT 24
Finished Jul 17 05:03:08 PM PDT 24
Peak memory 210220 kb
Host smart-30aff394-3249-436c-8c04-7e0287a0c07c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267724663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2267724663
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2518289751
Short name T410
Test name
Test status
Simulation time 176070327 ps
CPU time 8.11 seconds
Started Jul 17 05:02:37 PM PDT 24
Finished Jul 17 05:02:46 PM PDT 24
Peak memory 210144 kb
Host smart-4f4ec5eb-387c-4dd2-85af-ad15dc18d2e7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518289751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2518289751
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3581883815
Short name T73
Test name
Test status
Simulation time 53422497394 ps
CPU time 131.26 seconds
Started Jul 17 05:02:44 PM PDT 24
Finished Jul 17 05:04:56 PM PDT 24
Peak memory 214748 kb
Host smart-b3012e6e-b141-4f7c-83aa-5476e620f737
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581883815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3581883815
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3561369506
Short name T89
Test name
Test status
Simulation time 689438154 ps
CPU time 8.25 seconds
Started Jul 17 05:02:50 PM PDT 24
Finished Jul 17 05:03:00 PM PDT 24
Peak memory 210852 kb
Host smart-510188e7-a067-46a9-a47b-c561e30704f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561369506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3561369506
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1641400010
Short name T431
Test name
Test status
Simulation time 2396073314 ps
CPU time 28.91 seconds
Started Jul 17 05:02:38 PM PDT 24
Finished Jul 17 05:03:08 PM PDT 24
Peak memory 218128 kb
Host smart-5633468f-b614-45b9-ad13-92dfb2e9ad61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641400010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1641400010
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1160149776
Short name T110
Test name
Test status
Simulation time 2655719170 ps
CPU time 93.93 seconds
Started Jul 17 05:02:38 PM PDT 24
Finished Jul 17 05:04:13 PM PDT 24
Peak memory 213260 kb
Host smart-11b1ff36-fcb1-4c13-8b9b-30d12c587be8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160149776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1160149776
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1157308208
Short name T77
Test name
Test status
Simulation time 339043891 ps
CPU time 8.17 seconds
Started Jul 17 05:02:53 PM PDT 24
Finished Jul 17 05:03:04 PM PDT 24
Peak memory 210676 kb
Host smart-ca3d260d-07fd-4ff0-88d5-99aa181a6012
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157308208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1157308208
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.751401293
Short name T48
Test name
Test status
Simulation time 345748616 ps
CPU time 8.25 seconds
Started Jul 17 05:02:53 PM PDT 24
Finished Jul 17 05:03:05 PM PDT 24
Peak memory 210284 kb
Host smart-6912fa92-81c3-47aa-a38f-d20cf9d57ee2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751401293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.751401293
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3849511806
Short name T391
Test name
Test status
Simulation time 868192190 ps
CPU time 18.25 seconds
Started Jul 17 05:02:53 PM PDT 24
Finished Jul 17 05:03:15 PM PDT 24
Peak memory 211080 kb
Host smart-8dd07866-6c3f-42bf-8f97-e7c46ebdf871
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849511806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3849511806
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2288085428
Short name T450
Test name
Test status
Simulation time 13574766708 ps
CPU time 27.65 seconds
Started Jul 17 05:02:51 PM PDT 24
Finished Jul 17 05:03:20 PM PDT 24
Peak memory 217016 kb
Host smart-c6a70f9a-cef6-4477-b344-71f709712bd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288085428 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2288085428
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.4151554668
Short name T61
Test name
Test status
Simulation time 4597318540 ps
CPU time 15.62 seconds
Started Jul 17 05:02:53 PM PDT 24
Finished Jul 17 05:03:12 PM PDT 24
Peak memory 211192 kb
Host smart-8215369f-5c32-4b61-91fc-67ba39481b08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151554668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.4151554668
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.4135349602
Short name T422
Test name
Test status
Simulation time 688493836 ps
CPU time 8.27 seconds
Started Jul 17 05:02:51 PM PDT 24
Finished Jul 17 05:03:01 PM PDT 24
Peak memory 210140 kb
Host smart-3f652539-5ae6-4f57-9bbd-efba22a9a58a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135349602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.4135349602
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3780753718
Short name T412
Test name
Test status
Simulation time 688316507 ps
CPU time 8.1 seconds
Started Jul 17 05:03:02 PM PDT 24
Finished Jul 17 05:03:11 PM PDT 24
Peak memory 209884 kb
Host smart-210d8457-be6e-4e8e-b575-6a4c1b685aa0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780753718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3780753718
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.876705823
Short name T78
Test name
Test status
Simulation time 50741221165 ps
CPU time 110.25 seconds
Started Jul 17 05:02:52 PM PDT 24
Finished Jul 17 05:04:45 PM PDT 24
Peak memory 211428 kb
Host smart-70abaf1f-b048-4846-8b39-67c1befb2853
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876705823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.876705823
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.665696397
Short name T87
Test name
Test status
Simulation time 8832977016 ps
CPU time 21.15 seconds
Started Jul 17 05:02:51 PM PDT 24
Finished Jul 17 05:03:13 PM PDT 24
Peak memory 212364 kb
Host smart-f055dc60-b5fb-4821-aaf4-8c0516d5b1c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665696397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.665696397
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1640947816
Short name T377
Test name
Test status
Simulation time 3135650638 ps
CPU time 32.24 seconds
Started Jul 17 05:02:53 PM PDT 24
Finished Jul 17 05:03:29 PM PDT 24
Peak memory 218384 kb
Host smart-36065284-32ad-48e4-b3ba-aecb3e5e796c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640947816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1640947816
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1950015393
Short name T102
Test name
Test status
Simulation time 5924155980 ps
CPU time 88.85 seconds
Started Jul 17 05:02:54 PM PDT 24
Finished Jul 17 05:04:26 PM PDT 24
Peak memory 213808 kb
Host smart-4f08c8fa-23d9-4d0a-97c6-a03f9549145c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950015393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1950015393
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4284535422
Short name T425
Test name
Test status
Simulation time 1652915572 ps
CPU time 19.25 seconds
Started Jul 17 05:02:53 PM PDT 24
Finished Jul 17 05:03:16 PM PDT 24
Peak memory 215972 kb
Host smart-9319f6ac-ad2b-43ca-852a-ab03d1bad8c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284535422 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.4284535422
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3936404574
Short name T416
Test name
Test status
Simulation time 8917089097 ps
CPU time 32.83 seconds
Started Jul 17 05:02:52 PM PDT 24
Finished Jul 17 05:03:28 PM PDT 24
Peak memory 211440 kb
Host smart-474efb8d-243b-4e21-9180-ec8d14a80383
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936404574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3936404574
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1074098939
Short name T382
Test name
Test status
Simulation time 59604561907 ps
CPU time 139.85 seconds
Started Jul 17 05:02:51 PM PDT 24
Finished Jul 17 05:05:13 PM PDT 24
Peak memory 214916 kb
Host smart-da916aea-969b-4259-aec4-65b320e8fbc4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074098939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1074098939
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.216743312
Short name T90
Test name
Test status
Simulation time 1518237638 ps
CPU time 13.47 seconds
Started Jul 17 05:02:52 PM PDT 24
Finished Jul 17 05:03:08 PM PDT 24
Peak memory 211048 kb
Host smart-2ade1384-1b2c-45f7-a291-3a966685ea8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216743312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.216743312
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.230482075
Short name T397
Test name
Test status
Simulation time 10156421359 ps
CPU time 27.29 seconds
Started Jul 17 05:02:50 PM PDT 24
Finished Jul 17 05:03:19 PM PDT 24
Peak memory 217140 kb
Host smart-cb0fbc63-64f5-4fa0-95b8-bd9febaf6018
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230482075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.230482075
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1524222630
Short name T104
Test name
Test status
Simulation time 9285997594 ps
CPU time 176.51 seconds
Started Jul 17 05:02:51 PM PDT 24
Finished Jul 17 05:05:49 PM PDT 24
Peak memory 213816 kb
Host smart-268b557f-0884-4f84-bd59-aa8262165419
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524222630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1524222630
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1686658499
Short name T420
Test name
Test status
Simulation time 3681326698 ps
CPU time 28.96 seconds
Started Jul 17 05:02:52 PM PDT 24
Finished Jul 17 05:03:23 PM PDT 24
Peak memory 216764 kb
Host smart-5c5a4825-6e75-4c76-8034-1e2a653335c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686658499 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1686658499
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2267916056
Short name T453
Test name
Test status
Simulation time 5048620568 ps
CPU time 12.77 seconds
Started Jul 17 05:02:52 PM PDT 24
Finished Jul 17 05:03:07 PM PDT 24
Peak memory 210796 kb
Host smart-c89574c0-c850-4d72-abe0-4a4a7234eec4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267916056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2267916056
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1741821256
Short name T418
Test name
Test status
Simulation time 1698110507 ps
CPU time 18.28 seconds
Started Jul 17 05:02:53 PM PDT 24
Finished Jul 17 05:03:14 PM PDT 24
Peak memory 211844 kb
Host smart-82ecd7fe-8476-4e3a-9e96-49c03fc410d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741821256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1741821256
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.4244091484
Short name T407
Test name
Test status
Simulation time 1699327908 ps
CPU time 18.89 seconds
Started Jul 17 05:02:51 PM PDT 24
Finished Jul 17 05:03:12 PM PDT 24
Peak memory 217940 kb
Host smart-4965e3dd-3c12-4de3-a8f4-9e508ca603c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244091484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.4244091484
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2508413830
Short name T100
Test name
Test status
Simulation time 321862767 ps
CPU time 153.87 seconds
Started Jul 17 05:02:51 PM PDT 24
Finished Jul 17 05:05:26 PM PDT 24
Peak memory 213416 kb
Host smart-b05aec54-3947-432f-a8e0-7c16d2695716
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508413830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2508413830
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2697539011
Short name T434
Test name
Test status
Simulation time 2997704395 ps
CPU time 27.51 seconds
Started Jul 17 05:02:52 PM PDT 24
Finished Jul 17 05:03:23 PM PDT 24
Peak memory 217660 kb
Host smart-056cd362-c49f-4d07-91e4-435f8a8280b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697539011 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2697539011
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.716708950
Short name T371
Test name
Test status
Simulation time 1564167646 ps
CPU time 17.84 seconds
Started Jul 17 05:02:52 PM PDT 24
Finished Jul 17 05:03:13 PM PDT 24
Peak memory 210764 kb
Host smart-a39b2de3-37ce-4c98-91b1-6bf8d680a218
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716708950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.716708950
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2022915833
Short name T72
Test name
Test status
Simulation time 50439225388 ps
CPU time 203.13 seconds
Started Jul 17 05:02:53 PM PDT 24
Finished Jul 17 05:06:20 PM PDT 24
Peak memory 214620 kb
Host smart-1aa0d127-ebd9-4c72-848e-55c6044bed04
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022915833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2022915833
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1428190226
Short name T414
Test name
Test status
Simulation time 29228801769 ps
CPU time 30.73 seconds
Started Jul 17 05:02:54 PM PDT 24
Finished Jul 17 05:03:28 PM PDT 24
Peak memory 212040 kb
Host smart-7fad2f05-1426-49f2-94f1-fd8f0a852aff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428190226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1428190226
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.410162170
Short name T392
Test name
Test status
Simulation time 6793691067 ps
CPU time 35.45 seconds
Started Jul 17 05:02:51 PM PDT 24
Finished Jul 17 05:03:29 PM PDT 24
Peak memory 216940 kb
Host smart-ecbb8ae1-029f-4e35-8cea-c938645ac541
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410162170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.410162170
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1702741856
Short name T98
Test name
Test status
Simulation time 430138921 ps
CPU time 153.68 seconds
Started Jul 17 05:02:54 PM PDT 24
Finished Jul 17 05:05:31 PM PDT 24
Peak memory 213800 kb
Host smart-705c004c-45ea-414f-a5f4-74a2dc19c0c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702741856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1702741856
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1075978329
Short name T446
Test name
Test status
Simulation time 11910951874 ps
CPU time 28.45 seconds
Started Jul 17 05:02:52 PM PDT 24
Finished Jul 17 05:03:24 PM PDT 24
Peak memory 218788 kb
Host smart-a6b5cd7e-f7af-4341-b92b-d31cd18e6239
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075978329 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1075978329
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1265759513
Short name T429
Test name
Test status
Simulation time 16062543198 ps
CPU time 31.9 seconds
Started Jul 17 05:03:02 PM PDT 24
Finished Jul 17 05:03:35 PM PDT 24
Peak memory 211444 kb
Host smart-db89aff9-8c23-4c21-aa85-55ae2ba4b225
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265759513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1265759513
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3143349230
Short name T393
Test name
Test status
Simulation time 6858902406 ps
CPU time 27.57 seconds
Started Jul 17 05:02:52 PM PDT 24
Finished Jul 17 05:03:22 PM PDT 24
Peak memory 212184 kb
Host smart-f3c50f73-396d-477c-8e0f-50d517c5f32b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143349230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3143349230
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3546734648
Short name T448
Test name
Test status
Simulation time 660453100 ps
CPU time 12.05 seconds
Started Jul 17 05:02:53 PM PDT 24
Finished Jul 17 05:03:08 PM PDT 24
Peak memory 216856 kb
Host smart-4860bc85-2563-42dc-a821-e80c02bec5f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546734648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3546734648
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1895641179
Short name T381
Test name
Test status
Simulation time 4157728181 ps
CPU time 103.88 seconds
Started Jul 17 05:02:53 PM PDT 24
Finished Jul 17 05:04:39 PM PDT 24
Peak memory 213272 kb
Host smart-d8a7ff89-2d64-4a57-9457-cadb9e03e780
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895641179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1895641179
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3248295560
Short name T368
Test name
Test status
Simulation time 18729147817 ps
CPU time 25.47 seconds
Started Jul 17 05:03:02 PM PDT 24
Finished Jul 17 05:03:29 PM PDT 24
Peak memory 216592 kb
Host smart-5bfc10c8-56e7-45fa-bf76-e7464f1d766e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248295560 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3248295560
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.662235488
Short name T435
Test name
Test status
Simulation time 2504945164 ps
CPU time 23.11 seconds
Started Jul 17 05:02:50 PM PDT 24
Finished Jul 17 05:03:15 PM PDT 24
Peak memory 211356 kb
Host smart-d2fed8c7-9f1b-4d97-b530-c45698101964
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662235488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.662235488
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.230561877
Short name T388
Test name
Test status
Simulation time 5280991100 ps
CPU time 38.55 seconds
Started Jul 17 05:02:52 PM PDT 24
Finished Jul 17 05:03:33 PM PDT 24
Peak memory 213492 kb
Host smart-bd6a09aa-f042-4071-988a-6153e5c965de
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230561877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.230561877
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1614129633
Short name T399
Test name
Test status
Simulation time 338555396 ps
CPU time 8.25 seconds
Started Jul 17 05:02:51 PM PDT 24
Finished Jul 17 05:03:02 PM PDT 24
Peak memory 210912 kb
Host smart-2de95043-f559-4d58-97a3-2a6f92334088
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614129633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1614129633
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.907615204
Short name T403
Test name
Test status
Simulation time 4163109797 ps
CPU time 39.37 seconds
Started Jul 17 05:02:51 PM PDT 24
Finished Jul 17 05:03:33 PM PDT 24
Peak memory 218580 kb
Host smart-46b13d83-204d-4909-bc0e-0023e3a464c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907615204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.907615204
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1701489731
Short name T109
Test name
Test status
Simulation time 2964370449 ps
CPU time 86.64 seconds
Started Jul 17 05:02:52 PM PDT 24
Finished Jul 17 05:04:21 PM PDT 24
Peak memory 212920 kb
Host smart-a74d6c9c-9131-4e7a-9139-806d8d62cbe7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701489731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1701489731
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1573025524
Short name T256
Test name
Test status
Simulation time 4004684211 ps
CPU time 31.85 seconds
Started Jul 17 05:03:07 PM PDT 24
Finished Jul 17 05:03:42 PM PDT 24
Peak memory 217144 kb
Host smart-f5c852d6-62b8-4bf2-93ae-49f1c2570742
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573025524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1573025524
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3049430811
Short name T310
Test name
Test status
Simulation time 279649586895 ps
CPU time 729.87 seconds
Started Jul 17 05:03:07 PM PDT 24
Finished Jul 17 05:15:21 PM PDT 24
Peak memory 237828 kb
Host smart-d8b88e7c-a0f7-46f4-8349-58979dfe50aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049430811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3049430811
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.911908856
Short name T294
Test name
Test status
Simulation time 2061366285 ps
CPU time 18.99 seconds
Started Jul 17 05:03:06 PM PDT 24
Finished Jul 17 05:03:29 PM PDT 24
Peak memory 219264 kb
Host smart-9cd6c2c7-75bf-482f-8b31-574cee43742e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911908856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.911908856
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.355135094
Short name T278
Test name
Test status
Simulation time 4089274080 ps
CPU time 31.45 seconds
Started Jul 17 05:03:07 PM PDT 24
Finished Jul 17 05:03:42 PM PDT 24
Peak memory 217636 kb
Host smart-e5c41c7d-3198-47f0-8371-df23a82cdfc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=355135094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.355135094
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.908266806
Short name T26
Test name
Test status
Simulation time 965720681 ps
CPU time 117.07 seconds
Started Jul 17 05:03:06 PM PDT 24
Finished Jul 17 05:05:07 PM PDT 24
Peak memory 236236 kb
Host smart-714bf336-30aa-47ef-b779-1a7035977d76
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908266806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.908266806
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1133016791
Short name T245
Test name
Test status
Simulation time 3753083979 ps
CPU time 21.27 seconds
Started Jul 17 05:03:07 PM PDT 24
Finished Jul 17 05:03:32 PM PDT 24
Peak memory 218076 kb
Host smart-4ec6ce7b-0854-4720-8afa-2a6ecc508f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133016791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1133016791
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3348892613
Short name T296
Test name
Test status
Simulation time 4407551744 ps
CPU time 52.89 seconds
Started Jul 17 05:03:07 PM PDT 24
Finished Jul 17 05:04:04 PM PDT 24
Peak memory 219564 kb
Host smart-310346cd-0c24-4e28-b865-9f6df4e3154d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348892613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3348892613
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.322108638
Short name T39
Test name
Test status
Simulation time 210550003652 ps
CPU time 1509.99 seconds
Started Jul 17 05:03:07 PM PDT 24
Finished Jul 17 05:28:20 PM PDT 24
Peak memory 236632 kb
Host smart-80a22abc-de32-4757-9eb1-670d90419f98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322108638 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.322108638
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1741243806
Short name T317
Test name
Test status
Simulation time 9068347909 ps
CPU time 18.98 seconds
Started Jul 17 05:03:05 PM PDT 24
Finished Jul 17 05:03:28 PM PDT 24
Peak memory 217768 kb
Host smart-252eb8c9-22d1-4d71-9a92-8749aecb7571
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741243806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1741243806
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.963161465
Short name T142
Test name
Test status
Simulation time 48932999242 ps
CPU time 596.74 seconds
Started Jul 17 05:03:06 PM PDT 24
Finished Jul 17 05:13:06 PM PDT 24
Peak memory 219528 kb
Host smart-4264b2cc-d66e-4bfa-8b56-b399da6b52f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963161465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.963161465
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3243284653
Short name T268
Test name
Test status
Simulation time 25850515312 ps
CPU time 31.89 seconds
Started Jul 17 05:03:04 PM PDT 24
Finished Jul 17 05:03:39 PM PDT 24
Peak memory 219348 kb
Host smart-1722e13d-98cd-4d6a-835f-7a6da121ce95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243284653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3243284653
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.370507940
Short name T306
Test name
Test status
Simulation time 724190569 ps
CPU time 10.51 seconds
Started Jul 17 05:03:06 PM PDT 24
Finished Jul 17 05:03:20 PM PDT 24
Peak memory 219288 kb
Host smart-6fb9eb43-241f-4d05-9aff-14631ec43509
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=370507940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.370507940
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2891290749
Short name T19
Test name
Test status
Simulation time 19442187291 ps
CPU time 128.18 seconds
Started Jul 17 05:03:06 PM PDT 24
Finished Jul 17 05:05:17 PM PDT 24
Peak memory 237592 kb
Host smart-b852138b-3885-4bbb-b2a1-78d174bff34a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891290749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2891290749
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2413081460
Short name T333
Test name
Test status
Simulation time 8418304083 ps
CPU time 67.63 seconds
Started Jul 17 05:03:05 PM PDT 24
Finished Jul 17 05:04:15 PM PDT 24
Peak memory 217060 kb
Host smart-b9f19fcb-3eb6-4a26-8403-63b191cce85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413081460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2413081460
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3192487251
Short name T254
Test name
Test status
Simulation time 2152386754 ps
CPU time 58.98 seconds
Started Jul 17 05:03:04 PM PDT 24
Finished Jul 17 05:04:05 PM PDT 24
Peak memory 219316 kb
Host smart-b3466f23-2392-4cac-addf-9c5f5c43346e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192487251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3192487251
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2996607081
Short name T251
Test name
Test status
Simulation time 4228641393 ps
CPU time 33.32 seconds
Started Jul 17 05:03:22 PM PDT 24
Finished Jul 17 05:03:57 PM PDT 24
Peak memory 217112 kb
Host smart-d0f1e336-5fb0-4343-9344-bd6606f9bb3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996607081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2996607081
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.980295018
Short name T153
Test name
Test status
Simulation time 2758053383 ps
CPU time 161.52 seconds
Started Jul 17 05:03:19 PM PDT 24
Finished Jul 17 05:06:02 PM PDT 24
Peak memory 237936 kb
Host smart-e5f975f5-38e1-4635-9d98-6e4fcaecc2ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980295018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.980295018
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.821033212
Short name T113
Test name
Test status
Simulation time 15040200549 ps
CPU time 31.89 seconds
Started Jul 17 05:03:20 PM PDT 24
Finished Jul 17 05:03:54 PM PDT 24
Peak memory 219276 kb
Host smart-ca11c025-463c-46dc-b435-8887b0bda976
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=821033212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.821033212
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1723381188
Short name T204
Test name
Test status
Simulation time 15159273316 ps
CPU time 66.01 seconds
Started Jul 17 05:03:23 PM PDT 24
Finished Jul 17 05:04:31 PM PDT 24
Peak memory 216464 kb
Host smart-8ce31cb1-c95b-4d21-be1e-36e0e562cb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723381188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1723381188
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3574929594
Short name T249
Test name
Test status
Simulation time 152413285516 ps
CPU time 135.45 seconds
Started Jul 17 05:03:21 PM PDT 24
Finished Jul 17 05:05:39 PM PDT 24
Peak memory 219320 kb
Host smart-d10d8d2b-4e00-4e32-8d10-2026a0c8bb82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574929594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3574929594
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3001270020
Short name T327
Test name
Test status
Simulation time 1981086144 ps
CPU time 20.92 seconds
Started Jul 17 05:03:17 PM PDT 24
Finished Jul 17 05:03:39 PM PDT 24
Peak memory 217076 kb
Host smart-88ad3f84-b828-4e86-833f-3373e5f694bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001270020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3001270020
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1921165212
Short name T325
Test name
Test status
Simulation time 2494474201 ps
CPU time 162.37 seconds
Started Jul 17 05:03:20 PM PDT 24
Finished Jul 17 05:06:05 PM PDT 24
Peak memory 235892 kb
Host smart-0fcad1ba-450b-4229-be66-977318750fab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921165212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1921165212
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3344923630
Short name T246
Test name
Test status
Simulation time 1321085551 ps
CPU time 19.11 seconds
Started Jul 17 05:03:20 PM PDT 24
Finished Jul 17 05:03:41 PM PDT 24
Peak memory 219216 kb
Host smart-6c4e48c8-2c1d-4db5-85a9-c9a4f64617f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344923630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3344923630
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1651110750
Short name T83
Test name
Test status
Simulation time 1672744695 ps
CPU time 13.07 seconds
Started Jul 17 05:03:21 PM PDT 24
Finished Jul 17 05:03:36 PM PDT 24
Peak memory 218512 kb
Host smart-9dbe83ba-b8ad-4343-8975-551022c08a53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1651110750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1651110750
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3277145793
Short name T223
Test name
Test status
Simulation time 3906033933 ps
CPU time 36.96 seconds
Started Jul 17 05:03:21 PM PDT 24
Finished Jul 17 05:04:00 PM PDT 24
Peak memory 215736 kb
Host smart-c838fd9f-44ec-4a83-a345-fcaa5afb66fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277145793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3277145793
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.474801764
Short name T218
Test name
Test status
Simulation time 12465676042 ps
CPU time 59.48 seconds
Started Jul 17 05:03:19 PM PDT 24
Finished Jul 17 05:04:20 PM PDT 24
Peak memory 217276 kb
Host smart-b972704e-8850-4271-8632-f9ea3050580c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474801764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.474801764
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3173169815
Short name T240
Test name
Test status
Simulation time 2928092812 ps
CPU time 215.06 seconds
Started Jul 17 05:03:22 PM PDT 24
Finished Jul 17 05:06:59 PM PDT 24
Peak memory 224996 kb
Host smart-40a43309-10fd-4259-a27a-2af787b4fab7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173169815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3173169815
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2187441498
Short name T232
Test name
Test status
Simulation time 15071194526 ps
CPU time 64.52 seconds
Started Jul 17 05:03:20 PM PDT 24
Finished Jul 17 05:04:26 PM PDT 24
Peak memory 219212 kb
Host smart-ec16ea68-68bb-44bc-b8d1-05f80d3e12ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187441498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2187441498
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1529903774
Short name T112
Test name
Test status
Simulation time 733902424 ps
CPU time 10.66 seconds
Started Jul 17 05:03:18 PM PDT 24
Finished Jul 17 05:03:29 PM PDT 24
Peak memory 219216 kb
Host smart-33fea52d-2604-4778-bcca-d519a936d93e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1529903774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1529903774
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3826563454
Short name T84
Test name
Test status
Simulation time 355295908 ps
CPU time 19.65 seconds
Started Jul 17 05:03:20 PM PDT 24
Finished Jul 17 05:03:41 PM PDT 24
Peak memory 216408 kb
Host smart-eb3cc308-4b87-4986-bc96-3d9a45544b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826563454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3826563454
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2232344506
Short name T119
Test name
Test status
Simulation time 11518961215 ps
CPU time 120.16 seconds
Started Jul 17 05:03:19 PM PDT 24
Finished Jul 17 05:05:21 PM PDT 24
Peak memory 219340 kb
Host smart-f015e285-6e61-4c44-a22c-ebd5a63a97ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232344506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2232344506
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1231102441
Short name T51
Test name
Test status
Simulation time 3895682311 ps
CPU time 14.69 seconds
Started Jul 17 05:03:22 PM PDT 24
Finished Jul 17 05:03:39 PM PDT 24
Peak memory 217264 kb
Host smart-7c547b01-79ba-43ba-9ccd-4354e2f2ed76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231102441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1231102441
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.893203910
Short name T277
Test name
Test status
Simulation time 77192373180 ps
CPU time 740.35 seconds
Started Jul 17 05:03:22 PM PDT 24
Finished Jul 17 05:15:45 PM PDT 24
Peak memory 219412 kb
Host smart-983fdd00-66d3-4781-9fff-031e1fefabca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893203910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_c
orrupt_sig_fatal_chk.893203910
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.188409682
Short name T350
Test name
Test status
Simulation time 33621785192 ps
CPU time 67.71 seconds
Started Jul 17 05:03:22 PM PDT 24
Finished Jul 17 05:04:32 PM PDT 24
Peak memory 219288 kb
Host smart-98ad247f-e154-40c9-b420-8255aac5169a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188409682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.188409682
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2457954810
Short name T243
Test name
Test status
Simulation time 1155560896 ps
CPU time 10.62 seconds
Started Jul 17 05:03:22 PM PDT 24
Finished Jul 17 05:03:34 PM PDT 24
Peak memory 219264 kb
Host smart-6f41a761-24a9-4895-b57c-d49842ac10db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2457954810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2457954810
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2041556499
Short name T65
Test name
Test status
Simulation time 2613467539 ps
CPU time 19.69 seconds
Started Jul 17 05:03:21 PM PDT 24
Finished Jul 17 05:03:43 PM PDT 24
Peak memory 215904 kb
Host smart-84d2d200-b61c-4317-a12b-55ad1d0c8de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041556499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2041556499
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1683141561
Short name T354
Test name
Test status
Simulation time 67450038109 ps
CPU time 169.8 seconds
Started Jul 17 05:03:19 PM PDT 24
Finished Jul 17 05:06:10 PM PDT 24
Peak memory 227508 kb
Host smart-48ed3a69-6967-4817-9a53-cb57f4bccf90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683141561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1683141561
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.723602590
Short name T311
Test name
Test status
Simulation time 2421012305 ps
CPU time 13.13 seconds
Started Jul 17 05:03:30 PM PDT 24
Finished Jul 17 05:03:45 PM PDT 24
Peak memory 213224 kb
Host smart-84918b75-6b33-4d87-9efc-7ca1dfb32616
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723602590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.723602590
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3119916721
Short name T3
Test name
Test status
Simulation time 36941254732 ps
CPU time 314.5 seconds
Started Jul 17 05:03:30 PM PDT 24
Finished Jul 17 05:08:46 PM PDT 24
Peak memory 238040 kb
Host smart-933ed324-8b44-43b5-819d-a1da5f5e079c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119916721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3119916721
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3064187353
Short name T264
Test name
Test status
Simulation time 1800071703 ps
CPU time 31.6 seconds
Started Jul 17 05:03:34 PM PDT 24
Finished Jul 17 05:04:07 PM PDT 24
Peak memory 219264 kb
Host smart-f221f6c9-e546-44a5-8d48-1e3246531222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064187353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3064187353
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.728166808
Short name T252
Test name
Test status
Simulation time 5625519736 ps
CPU time 19.52 seconds
Started Jul 17 05:03:31 PM PDT 24
Finished Jul 17 05:03:52 PM PDT 24
Peak memory 211580 kb
Host smart-f9897cf3-8277-45e3-909d-5fc68d820d09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=728166808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.728166808
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.393639083
Short name T67
Test name
Test status
Simulation time 6475347957 ps
CPU time 28.46 seconds
Started Jul 17 05:03:20 PM PDT 24
Finished Jul 17 05:03:51 PM PDT 24
Peak memory 217784 kb
Host smart-f64a7609-215c-409a-a97f-1afa1a8be594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393639083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.393639083
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1119408104
Short name T170
Test name
Test status
Simulation time 2772546815 ps
CPU time 44.51 seconds
Started Jul 17 05:03:31 PM PDT 24
Finished Jul 17 05:04:17 PM PDT 24
Peak memory 219220 kb
Host smart-7eb43400-01f5-4346-8851-60907d82ce5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119408104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1119408104
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2935687710
Short name T185
Test name
Test status
Simulation time 11493554813 ps
CPU time 26.49 seconds
Started Jul 17 05:03:30 PM PDT 24
Finished Jul 17 05:03:58 PM PDT 24
Peak memory 217632 kb
Host smart-40278532-012f-45a6-a98d-b7b22e9b55f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935687710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2935687710
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3749618300
Short name T27
Test name
Test status
Simulation time 3189836401 ps
CPU time 232.94 seconds
Started Jul 17 05:03:32 PM PDT 24
Finished Jul 17 05:07:27 PM PDT 24
Peak memory 241016 kb
Host smart-981ddb98-c8b2-410a-af6a-33cddab398e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749618300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3749618300
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3043557126
Short name T282
Test name
Test status
Simulation time 15458567470 ps
CPU time 51.71 seconds
Started Jul 17 05:03:29 PM PDT 24
Finished Jul 17 05:04:22 PM PDT 24
Peak memory 219288 kb
Host smart-4acf299d-7bcd-4227-8cc9-cafd00de21cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043557126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3043557126
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2490501296
Short name T211
Test name
Test status
Simulation time 8784868655 ps
CPU time 32.37 seconds
Started Jul 17 05:03:31 PM PDT 24
Finished Jul 17 05:04:05 PM PDT 24
Peak memory 219304 kb
Host smart-5c766307-9bb4-45cf-a896-c164f138d343
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2490501296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2490501296
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.453726413
Short name T155
Test name
Test status
Simulation time 364080164 ps
CPU time 19.87 seconds
Started Jul 17 05:03:28 PM PDT 24
Finished Jul 17 05:03:49 PM PDT 24
Peak memory 216332 kb
Host smart-4ddabb58-87ce-4201-8700-2bfbab40d5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453726413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.453726413
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.4105675834
Short name T64
Test name
Test status
Simulation time 18609458209 ps
CPU time 120.2 seconds
Started Jul 17 05:03:29 PM PDT 24
Finished Jul 17 05:05:31 PM PDT 24
Peak memory 220032 kb
Host smart-bc97f039-82cc-49b1-91ed-046657c8d5d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105675834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.4105675834
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2217856185
Short name T271
Test name
Test status
Simulation time 21146683342 ps
CPU time 18.91 seconds
Started Jul 17 05:03:33 PM PDT 24
Finished Jul 17 05:03:54 PM PDT 24
Peak memory 213252 kb
Host smart-3475d81f-84bb-4c31-8246-0954d7f9191e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217856185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2217856185
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1888464785
Short name T175
Test name
Test status
Simulation time 142549001371 ps
CPU time 450.67 seconds
Started Jul 17 05:03:28 PM PDT 24
Finished Jul 17 05:11:00 PM PDT 24
Peak memory 219432 kb
Host smart-976bb54c-1281-4088-a2f5-444ca59fda26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888464785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1888464785
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1006628948
Short name T342
Test name
Test status
Simulation time 6796381791 ps
CPU time 58.64 seconds
Started Jul 17 05:03:32 PM PDT 24
Finished Jul 17 05:04:33 PM PDT 24
Peak memory 219324 kb
Host smart-9da6f8b7-df79-4845-982a-7851eea1a43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006628948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1006628948
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1158261682
Short name T195
Test name
Test status
Simulation time 688877387 ps
CPU time 14.46 seconds
Started Jul 17 05:03:31 PM PDT 24
Finished Jul 17 05:03:48 PM PDT 24
Peak memory 218532 kb
Host smart-f86ce4b2-8238-4677-af87-056724e39fd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1158261682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1158261682
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3970866994
Short name T158
Test name
Test status
Simulation time 7612655749 ps
CPU time 67.66 seconds
Started Jul 17 05:03:39 PM PDT 24
Finished Jul 17 05:04:48 PM PDT 24
Peak memory 216272 kb
Host smart-b662b12e-2996-45ec-ab01-fbb4be5d0848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970866994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3970866994
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.39242881
Short name T360
Test name
Test status
Simulation time 14188405062 ps
CPU time 90.6 seconds
Started Jul 17 05:03:28 PM PDT 24
Finished Jul 17 05:05:00 PM PDT 24
Peak memory 228712 kb
Host smart-216a08f3-83d8-4678-b56c-8c030182c05b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39242881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 16.rom_ctrl_stress_all.39242881
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.452182460
Short name T38
Test name
Test status
Simulation time 148098090824 ps
CPU time 476.61 seconds
Started Jul 17 05:03:30 PM PDT 24
Finished Jul 17 05:11:29 PM PDT 24
Peak memory 232436 kb
Host smart-0676b2b9-0ee0-4944-9680-8ec59a966120
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452182460 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.452182460
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.981485595
Short name T34
Test name
Test status
Simulation time 4415066847 ps
CPU time 21.3 seconds
Started Jul 17 05:03:32 PM PDT 24
Finished Jul 17 05:03:55 PM PDT 24
Peak memory 217452 kb
Host smart-c9571888-49b1-453f-8dc4-830c5656abcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981485595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.981485595
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3447989130
Short name T348
Test name
Test status
Simulation time 186766896667 ps
CPU time 446.52 seconds
Started Jul 17 05:03:39 PM PDT 24
Finished Jul 17 05:11:06 PM PDT 24
Peak memory 225824 kb
Host smart-b15f269f-5ca6-4926-ad59-1c8896591962
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447989130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3447989130
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1717522345
Short name T215
Test name
Test status
Simulation time 3265879584 ps
CPU time 39.54 seconds
Started Jul 17 05:03:31 PM PDT 24
Finished Jul 17 05:04:12 PM PDT 24
Peak memory 219308 kb
Host smart-ba09cf24-352e-4c3b-bc14-2515f7e0d090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717522345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1717522345
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2575846556
Short name T214
Test name
Test status
Simulation time 513783000 ps
CPU time 13.69 seconds
Started Jul 17 05:03:29 PM PDT 24
Finished Jul 17 05:03:44 PM PDT 24
Peak memory 219476 kb
Host smart-161d2d85-0be3-4b91-aeec-10bf20241b34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2575846556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2575846556
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1182293238
Short name T123
Test name
Test status
Simulation time 6682787234 ps
CPU time 53.82 seconds
Started Jul 17 05:03:29 PM PDT 24
Finished Jul 17 05:04:25 PM PDT 24
Peak memory 218048 kb
Host smart-77598fb5-bb14-43e6-92d0-93d63d443c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182293238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1182293238
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.243227208
Short name T135
Test name
Test status
Simulation time 13486349889 ps
CPU time 142.49 seconds
Started Jul 17 05:03:31 PM PDT 24
Finished Jul 17 05:05:55 PM PDT 24
Peak memory 219480 kb
Host smart-e29f1d61-bf1e-416a-9d53-7a4135c3d485
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243227208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.243227208
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3296712195
Short name T147
Test name
Test status
Simulation time 662119446 ps
CPU time 8.41 seconds
Started Jul 17 05:03:29 PM PDT 24
Finished Jul 17 05:03:39 PM PDT 24
Peak memory 217200 kb
Host smart-c4223e3f-cee5-4143-93a1-b6250650c734
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296712195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3296712195
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.828379578
Short name T166
Test name
Test status
Simulation time 80622012805 ps
CPU time 294.77 seconds
Started Jul 17 05:03:29 PM PDT 24
Finished Jul 17 05:08:25 PM PDT 24
Peak memory 249028 kb
Host smart-d33848bc-b23b-4769-b55c-10f5eff01a2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828379578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.828379578
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2616409836
Short name T320
Test name
Test status
Simulation time 6281709963 ps
CPU time 56.52 seconds
Started Jul 17 05:03:30 PM PDT 24
Finished Jul 17 05:04:28 PM PDT 24
Peak memory 219388 kb
Host smart-4327ec28-0a03-452c-86fd-06b3badcd7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616409836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2616409836
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.389033215
Short name T125
Test name
Test status
Simulation time 4251282579 ps
CPU time 35.24 seconds
Started Jul 17 05:03:31 PM PDT 24
Finished Jul 17 05:04:09 PM PDT 24
Peak memory 219300 kb
Host smart-051be64d-3ff1-4f4e-939c-1ee75398bd43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=389033215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.389033215
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2822903758
Short name T203
Test name
Test status
Simulation time 1893030115 ps
CPU time 20.19 seconds
Started Jul 17 05:03:33 PM PDT 24
Finished Jul 17 05:03:55 PM PDT 24
Peak memory 216096 kb
Host smart-5a4154ab-4e68-4419-a264-3bb74e1796bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822903758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2822903758
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3660785912
Short name T260
Test name
Test status
Simulation time 23580743135 ps
CPU time 66.91 seconds
Started Jul 17 05:03:31 PM PDT 24
Finished Jul 17 05:04:40 PM PDT 24
Peak memory 218156 kb
Host smart-ebed09d9-2942-4890-9e0f-9236ae107143
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660785912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3660785912
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.899325347
Short name T156
Test name
Test status
Simulation time 1010176733 ps
CPU time 11.6 seconds
Started Jul 17 05:03:39 PM PDT 24
Finished Jul 17 05:03:52 PM PDT 24
Peak memory 217036 kb
Host smart-4edeaa70-0f21-4a89-8102-cd04fe709be7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899325347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.899325347
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1134023610
Short name T208
Test name
Test status
Simulation time 39844807903 ps
CPU time 544.79 seconds
Started Jul 17 05:03:32 PM PDT 24
Finished Jul 17 05:12:39 PM PDT 24
Peak memory 240356 kb
Host smart-fd050554-1760-4c79-92cc-265b49229106
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134023610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1134023610
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.565176659
Short name T248
Test name
Test status
Simulation time 3299818749 ps
CPU time 19.09 seconds
Started Jul 17 05:03:30 PM PDT 24
Finished Jul 17 05:03:51 PM PDT 24
Peak memory 219276 kb
Host smart-6326b260-2b82-4f66-bddd-5e6b7fd14959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565176659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.565176659
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.4287647884
Short name T355
Test name
Test status
Simulation time 670683608 ps
CPU time 14.46 seconds
Started Jul 17 05:03:39 PM PDT 24
Finished Jul 17 05:03:55 PM PDT 24
Peak memory 218480 kb
Host smart-63766423-ccae-430c-b7a8-65d9e6d07796
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4287647884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.4287647884
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2115121268
Short name T353
Test name
Test status
Simulation time 36170823484 ps
CPU time 169.84 seconds
Started Jul 17 05:03:30 PM PDT 24
Finished Jul 17 05:06:22 PM PDT 24
Peak memory 222416 kb
Host smart-192a92c5-f807-48f8-8a60-96a2cba48218
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115121268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2115121268
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1199375612
Short name T160
Test name
Test status
Simulation time 1884436151 ps
CPU time 15.7 seconds
Started Jul 17 05:03:08 PM PDT 24
Finished Jul 17 05:03:27 PM PDT 24
Peak memory 217140 kb
Host smart-23de2d3f-284d-4001-82cd-dcc89d8510a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199375612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1199375612
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1544703176
Short name T314
Test name
Test status
Simulation time 680376614076 ps
CPU time 781.96 seconds
Started Jul 17 05:03:04 PM PDT 24
Finished Jul 17 05:16:09 PM PDT 24
Peak memory 219528 kb
Host smart-2c325610-6803-46df-9db0-01b40b904727
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544703176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1544703176
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.4087428599
Short name T269
Test name
Test status
Simulation time 4672218260 ps
CPU time 47.98 seconds
Started Jul 17 05:03:07 PM PDT 24
Finished Jul 17 05:03:59 PM PDT 24
Peak memory 219284 kb
Host smart-2c0bd37d-3d44-4733-b1be-ea50354bc4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087428599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.4087428599
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3957030817
Short name T130
Test name
Test status
Simulation time 14732042826 ps
CPU time 31.35 seconds
Started Jul 17 05:03:05 PM PDT 24
Finished Jul 17 05:03:39 PM PDT 24
Peak memory 211996 kb
Host smart-28828d51-1dc0-4d2a-9710-81f08f517711
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3957030817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3957030817
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1727533493
Short name T263
Test name
Test status
Simulation time 10340027295 ps
CPU time 36.33 seconds
Started Jul 17 05:03:07 PM PDT 24
Finished Jul 17 05:03:47 PM PDT 24
Peak memory 216972 kb
Host smart-b3ab510e-9034-4422-a612-0b06909de39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727533493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1727533493
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.854354487
Short name T115
Test name
Test status
Simulation time 11145716839 ps
CPU time 59.9 seconds
Started Jul 17 05:03:07 PM PDT 24
Finished Jul 17 05:04:11 PM PDT 24
Peak memory 219152 kb
Host smart-ef36b68a-3f08-458a-bd37-c3295d8fe0a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854354487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.854354487
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.2148682079
Short name T352
Test name
Test status
Simulation time 200495216053 ps
CPU time 1780.06 seconds
Started Jul 17 05:03:06 PM PDT 24
Finished Jul 17 05:32:50 PM PDT 24
Peak memory 243968 kb
Host smart-cdef9fa8-efd1-4d17-a02a-2d821d22d12b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148682079 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.2148682079
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3332255562
Short name T152
Test name
Test status
Simulation time 6324896602 ps
CPU time 26.35 seconds
Started Jul 17 05:03:46 PM PDT 24
Finished Jul 17 05:04:14 PM PDT 24
Peak memory 217412 kb
Host smart-db6c5daa-6936-4143-9f80-b2f36fa096ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332255562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3332255562
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2020094253
Short name T309
Test name
Test status
Simulation time 6863768088 ps
CPU time 374.3 seconds
Started Jul 17 05:03:32 PM PDT 24
Finished Jul 17 05:09:49 PM PDT 24
Peak memory 240372 kb
Host smart-724b69b2-88d1-478f-aa3a-49027cda03f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020094253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2020094253
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.825204083
Short name T54
Test name
Test status
Simulation time 185723051 ps
CPU time 10.82 seconds
Started Jul 17 05:03:29 PM PDT 24
Finished Jul 17 05:03:42 PM PDT 24
Peak memory 219252 kb
Host smart-f4bab2fc-9884-4a40-812b-86753925e056
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=825204083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.825204083
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.126113308
Short name T274
Test name
Test status
Simulation time 9982253920 ps
CPU time 28.46 seconds
Started Jul 17 05:03:34 PM PDT 24
Finished Jul 17 05:04:04 PM PDT 24
Peak memory 216524 kb
Host smart-15c3d395-f1fa-4085-b7c4-d6fd5739766f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126113308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.126113308
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2079637549
Short name T196
Test name
Test status
Simulation time 17038660252 ps
CPU time 42.22 seconds
Started Jul 17 05:03:33 PM PDT 24
Finished Jul 17 05:04:17 PM PDT 24
Peak memory 219200 kb
Host smart-65c401f0-2036-4c01-833e-cdee4150d9b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079637549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2079637549
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1584247897
Short name T279
Test name
Test status
Simulation time 4270690453 ps
CPU time 29.71 seconds
Started Jul 17 05:03:44 PM PDT 24
Finished Jul 17 05:04:16 PM PDT 24
Peak memory 217136 kb
Host smart-143b2c4e-a919-4a68-9c09-9f5173c07847
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584247897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1584247897
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1280097344
Short name T283
Test name
Test status
Simulation time 77577903440 ps
CPU time 768.43 seconds
Started Jul 17 05:03:43 PM PDT 24
Finished Jul 17 05:16:34 PM PDT 24
Peak memory 233804 kb
Host smart-43362533-974c-49d9-b683-49c360d1206c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280097344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1280097344
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3584986861
Short name T10
Test name
Test status
Simulation time 24824371242 ps
CPU time 53.09 seconds
Started Jul 17 05:03:42 PM PDT 24
Finished Jul 17 05:04:39 PM PDT 24
Peak memory 219340 kb
Host smart-9643c827-4ddf-4959-a04e-18d47381e1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584986861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3584986861
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2646412160
Short name T284
Test name
Test status
Simulation time 3145159615 ps
CPU time 29.11 seconds
Started Jul 17 05:03:42 PM PDT 24
Finished Jul 17 05:04:13 PM PDT 24
Peak memory 219276 kb
Host smart-900d5dad-e228-48d6-8782-a7649e3963e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2646412160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2646412160
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.754467963
Short name T7
Test name
Test status
Simulation time 4445724484 ps
CPU time 24.9 seconds
Started Jul 17 05:03:44 PM PDT 24
Finished Jul 17 05:04:11 PM PDT 24
Peak memory 216596 kb
Host smart-a4861b5c-8027-4e98-8a12-c79b85e9d6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754467963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.754467963
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.237630533
Short name T120
Test name
Test status
Simulation time 23355833641 ps
CPU time 53.57 seconds
Started Jul 17 05:03:42 PM PDT 24
Finished Jul 17 05:04:38 PM PDT 24
Peak memory 219348 kb
Host smart-7e6d78d5-7186-4361-b29d-6b889b966d06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237630533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.237630533
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1441228672
Short name T21
Test name
Test status
Simulation time 5835217520 ps
CPU time 25.42 seconds
Started Jul 17 05:03:43 PM PDT 24
Finished Jul 17 05:04:11 PM PDT 24
Peak memory 217504 kb
Host smart-cf9ae628-545c-4f2a-95ea-6788cff14034
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441228672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1441228672
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2000332462
Short name T349
Test name
Test status
Simulation time 78068908621 ps
CPU time 460.93 seconds
Started Jul 17 05:03:43 PM PDT 24
Finished Jul 17 05:11:26 PM PDT 24
Peak memory 215844 kb
Host smart-7d321747-d221-467b-aab7-b0ca23f5bbf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000332462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2000332462
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.921525841
Short name T316
Test name
Test status
Simulation time 25603116445 ps
CPU time 59.92 seconds
Started Jul 17 05:03:42 PM PDT 24
Finished Jul 17 05:04:44 PM PDT 24
Peak memory 219104 kb
Host smart-04f9b166-d53c-454e-819c-ab4d149889b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921525841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.921525841
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.768851831
Short name T272
Test name
Test status
Simulation time 18217314705 ps
CPU time 32.61 seconds
Started Jul 17 05:03:41 PM PDT 24
Finished Jul 17 05:04:15 PM PDT 24
Peak memory 219288 kb
Host smart-e430e090-4234-4651-a42f-e2644a677cdb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=768851831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.768851831
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.796554276
Short name T68
Test name
Test status
Simulation time 6584414536 ps
CPU time 33.03 seconds
Started Jul 17 05:03:42 PM PDT 24
Finished Jul 17 05:04:18 PM PDT 24
Peak memory 216852 kb
Host smart-72eebec2-a1c6-4497-835a-5d22f098579e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796554276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.796554276
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1988510026
Short name T221
Test name
Test status
Simulation time 7747398140 ps
CPU time 55.71 seconds
Started Jul 17 05:03:43 PM PDT 24
Finished Jul 17 05:04:41 PM PDT 24
Peak memory 218332 kb
Host smart-1b62a274-b35e-409a-b819-dbd3c1bebba3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988510026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1988510026
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1734249050
Short name T231
Test name
Test status
Simulation time 2216475443 ps
CPU time 13.86 seconds
Started Jul 17 05:03:41 PM PDT 24
Finished Jul 17 05:03:55 PM PDT 24
Peak memory 217164 kb
Host smart-4cbab1f7-dfeb-415c-ac0b-3c0d47f9c765
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734249050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1734249050
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3374543252
Short name T305
Test name
Test status
Simulation time 75904830585 ps
CPU time 807.46 seconds
Started Jul 17 05:03:42 PM PDT 24
Finished Jul 17 05:17:12 PM PDT 24
Peak memory 229764 kb
Host smart-fb517b6b-0613-43cc-81ad-4d51e4d925f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374543252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3374543252
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2110123487
Short name T244
Test name
Test status
Simulation time 5209350297 ps
CPU time 27.32 seconds
Started Jul 17 05:03:44 PM PDT 24
Finished Jul 17 05:04:14 PM PDT 24
Peak memory 219292 kb
Host smart-463768ab-9d53-498b-8000-ff0f34a7081a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110123487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2110123487
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.666939502
Short name T16
Test name
Test status
Simulation time 2427087634 ps
CPU time 17.5 seconds
Started Jul 17 05:03:43 PM PDT 24
Finished Jul 17 05:04:04 PM PDT 24
Peak memory 211736 kb
Host smart-6c636937-b682-4079-8428-8d41d62aeaca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=666939502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.666939502
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1200812394
Short name T191
Test name
Test status
Simulation time 364103889 ps
CPU time 20.34 seconds
Started Jul 17 05:03:45 PM PDT 24
Finished Jul 17 05:04:07 PM PDT 24
Peak memory 216492 kb
Host smart-e9db1c79-ec3c-4a19-a2e7-e322564f5c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200812394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1200812394
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2567946122
Short name T257
Test name
Test status
Simulation time 7729254504 ps
CPU time 22.06 seconds
Started Jul 17 05:03:44 PM PDT 24
Finished Jul 17 05:04:08 PM PDT 24
Peak memory 214596 kb
Host smart-2387117d-640f-45c4-b155-2e45eb158dc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567946122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2567946122
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2911644598
Short name T228
Test name
Test status
Simulation time 3777534725 ps
CPU time 19.76 seconds
Started Jul 17 05:03:43 PM PDT 24
Finished Jul 17 05:04:06 PM PDT 24
Peak memory 217216 kb
Host smart-694c91e5-641c-4f8b-8def-542a5e07b468
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911644598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2911644598
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2352263436
Short name T29
Test name
Test status
Simulation time 83717237146 ps
CPU time 650.69 seconds
Started Jul 17 05:03:44 PM PDT 24
Finished Jul 17 05:14:37 PM PDT 24
Peak memory 236648 kb
Host smart-3fdf7ad2-81d2-4e2f-978d-9332c69a1862
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352263436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2352263436
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3637668087
Short name T308
Test name
Test status
Simulation time 1436336429 ps
CPU time 19.42 seconds
Started Jul 17 05:03:44 PM PDT 24
Finished Jul 17 05:04:06 PM PDT 24
Peak memory 219252 kb
Host smart-668133f5-fc7c-45aa-8a08-3cbab7b5e61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637668087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3637668087
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2400852523
Short name T193
Test name
Test status
Simulation time 3095672088 ps
CPU time 28.37 seconds
Started Jul 17 05:03:43 PM PDT 24
Finished Jul 17 05:04:14 PM PDT 24
Peak memory 219236 kb
Host smart-36f3cb21-3d68-4108-8bd4-216f86e3e59a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2400852523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2400852523
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.4082955762
Short name T357
Test name
Test status
Simulation time 20622255477 ps
CPU time 48.74 seconds
Started Jul 17 05:03:45 PM PDT 24
Finished Jul 17 05:04:36 PM PDT 24
Peak memory 216196 kb
Host smart-b9670198-22e3-474d-a8e2-1849470abb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082955762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.4082955762
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1891526592
Short name T293
Test name
Test status
Simulation time 3498821308 ps
CPU time 21.13 seconds
Started Jul 17 05:03:42 PM PDT 24
Finished Jul 17 05:04:06 PM PDT 24
Peak memory 219412 kb
Host smart-0474afa8-fb37-4ac3-8451-a9508dffda72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891526592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1891526592
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3542751215
Short name T136
Test name
Test status
Simulation time 7835422839 ps
CPU time 20.44 seconds
Started Jul 17 05:03:53 PM PDT 24
Finished Jul 17 05:04:15 PM PDT 24
Peak memory 217380 kb
Host smart-17bb606e-c571-46df-b10b-72105a3a7801
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542751215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3542751215
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3183314002
Short name T31
Test name
Test status
Simulation time 117107492564 ps
CPU time 417.79 seconds
Started Jul 17 05:03:53 PM PDT 24
Finished Jul 17 05:10:52 PM PDT 24
Peak memory 232660 kb
Host smart-4816e582-08b2-43f4-bc07-7c4d611fd46e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183314002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3183314002
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2864917114
Short name T36
Test name
Test status
Simulation time 2397910306 ps
CPU time 27.36 seconds
Started Jul 17 05:03:54 PM PDT 24
Finished Jul 17 05:04:23 PM PDT 24
Peak memory 215752 kb
Host smart-65cd62f0-7360-493e-bf46-8cfdf2eb7bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864917114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2864917114
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1674164341
Short name T172
Test name
Test status
Simulation time 3267361512 ps
CPU time 29.49 seconds
Started Jul 17 05:03:55 PM PDT 24
Finished Jul 17 05:04:26 PM PDT 24
Peak memory 211304 kb
Host smart-d7767fcc-ac85-44bc-b4ad-916c6ee27e0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1674164341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1674164341
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3133663478
Short name T66
Test name
Test status
Simulation time 31475068214 ps
CPU time 66.01 seconds
Started Jul 17 05:03:53 PM PDT 24
Finished Jul 17 05:05:01 PM PDT 24
Peak memory 216008 kb
Host smart-d4e61e70-627c-43b5-9ce2-e14f1905fb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133663478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3133663478
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2087491611
Short name T163
Test name
Test status
Simulation time 3261139968 ps
CPU time 40.33 seconds
Started Jul 17 05:03:57 PM PDT 24
Finished Jul 17 05:04:39 PM PDT 24
Peak memory 219324 kb
Host smart-c415bd4e-a85e-4751-865d-05d050d272c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087491611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2087491611
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2085873236
Short name T141
Test name
Test status
Simulation time 216463951 ps
CPU time 8.47 seconds
Started Jul 17 05:03:55 PM PDT 24
Finished Jul 17 05:04:05 PM PDT 24
Peak memory 217136 kb
Host smart-07322848-5d2e-4113-8071-29520cde86c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085873236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2085873236
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3127548354
Short name T18
Test name
Test status
Simulation time 53413128966 ps
CPU time 357.28 seconds
Started Jul 17 05:03:55 PM PDT 24
Finished Jul 17 05:09:53 PM PDT 24
Peak memory 234024 kb
Host smart-bcae821b-e95a-48d1-bab3-f299025226f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127548354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3127548354
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1676976986
Short name T150
Test name
Test status
Simulation time 112574561161 ps
CPU time 67.35 seconds
Started Jul 17 05:03:58 PM PDT 24
Finished Jul 17 05:05:07 PM PDT 24
Peak memory 219208 kb
Host smart-15d9aeac-4d86-462a-a6c7-3cfd6e6350ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676976986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1676976986
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1651024929
Short name T212
Test name
Test status
Simulation time 612107548 ps
CPU time 10.62 seconds
Started Jul 17 05:03:57 PM PDT 24
Finished Jul 17 05:04:09 PM PDT 24
Peak memory 219260 kb
Host smart-1fa15577-53db-4afa-b185-ded826cefc32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1651024929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1651024929
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1779396735
Short name T184
Test name
Test status
Simulation time 5782460125 ps
CPU time 50.78 seconds
Started Jul 17 05:03:54 PM PDT 24
Finished Jul 17 05:04:46 PM PDT 24
Peak memory 216364 kb
Host smart-68c437ab-efd2-438e-aa41-10484b3b2fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779396735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1779396735
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2520696645
Short name T266
Test name
Test status
Simulation time 2534527367 ps
CPU time 23.9 seconds
Started Jul 17 05:03:55 PM PDT 24
Finished Jul 17 05:04:21 PM PDT 24
Peak memory 216664 kb
Host smart-d6845f00-a752-41ee-bee1-2d8578f903c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520696645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2520696645
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1910356048
Short name T122
Test name
Test status
Simulation time 753276290 ps
CPU time 13.44 seconds
Started Jul 17 05:04:00 PM PDT 24
Finished Jul 17 05:04:14 PM PDT 24
Peak memory 217044 kb
Host smart-6bd44ed9-2620-4184-8c72-c9092ca41d48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910356048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1910356048
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3483311828
Short name T183
Test name
Test status
Simulation time 50579751064 ps
CPU time 612.33 seconds
Started Jul 17 05:03:54 PM PDT 24
Finished Jul 17 05:14:08 PM PDT 24
Peak memory 236144 kb
Host smart-fb8837af-ef9d-46ae-bee5-60756ebc412d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483311828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3483311828
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3552373181
Short name T138
Test name
Test status
Simulation time 18414438036 ps
CPU time 48.92 seconds
Started Jul 17 05:03:53 PM PDT 24
Finished Jul 17 05:04:44 PM PDT 24
Peak memory 219532 kb
Host smart-0bb0988b-3f86-4e03-8c17-fafe755e8ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552373181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3552373181
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.4238702709
Short name T114
Test name
Test status
Simulation time 5393376769 ps
CPU time 17.82 seconds
Started Jul 17 05:03:55 PM PDT 24
Finished Jul 17 05:04:15 PM PDT 24
Peak memory 219328 kb
Host smart-311aa077-78cd-4340-b53c-0223173085c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4238702709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.4238702709
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2937324383
Short name T168
Test name
Test status
Simulation time 15735236939 ps
CPU time 42.14 seconds
Started Jul 17 05:03:57 PM PDT 24
Finished Jul 17 05:04:41 PM PDT 24
Peak memory 216044 kb
Host smart-7bfdd1bc-d681-498d-885b-69023dfb4703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937324383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2937324383
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1533544375
Short name T132
Test name
Test status
Simulation time 122735777249 ps
CPU time 97.9 seconds
Started Jul 17 05:03:53 PM PDT 24
Finished Jul 17 05:05:32 PM PDT 24
Peak memory 219308 kb
Host smart-7350a818-224a-4ef7-8367-f281acce61f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533544375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1533544375
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1582673497
Short name T280
Test name
Test status
Simulation time 5176462759 ps
CPU time 15.94 seconds
Started Jul 17 05:03:52 PM PDT 24
Finished Jul 17 05:04:09 PM PDT 24
Peak memory 217308 kb
Host smart-63cc2ad1-c5bd-492d-91be-705d6a4a64be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582673497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1582673497
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2042468874
Short name T194
Test name
Test status
Simulation time 243055810379 ps
CPU time 583.79 seconds
Started Jul 17 05:03:57 PM PDT 24
Finished Jul 17 05:13:42 PM PDT 24
Peak memory 234676 kb
Host smart-cce79176-cafa-4e44-ad21-cf15deeefe82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042468874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2042468874
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3262923996
Short name T139
Test name
Test status
Simulation time 1500869958 ps
CPU time 19.09 seconds
Started Jul 17 05:03:56 PM PDT 24
Finished Jul 17 05:04:16 PM PDT 24
Peak memory 219276 kb
Host smart-2cf51f8b-4ffe-4e61-8b3b-37a68ad0c2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262923996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3262923996
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.519680131
Short name T297
Test name
Test status
Simulation time 1719735449 ps
CPU time 20.35 seconds
Started Jul 17 05:03:59 PM PDT 24
Finished Jul 17 05:04:20 PM PDT 24
Peak memory 219288 kb
Host smart-aebf5062-ba7b-4905-88f1-9f3e776d1b23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=519680131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.519680131
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.700936243
Short name T198
Test name
Test status
Simulation time 2899039498 ps
CPU time 40.95 seconds
Started Jul 17 05:03:56 PM PDT 24
Finished Jul 17 05:04:38 PM PDT 24
Peak memory 216216 kb
Host smart-541084cc-0593-44ef-9afb-93391825dc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700936243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.700936243
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.4113749658
Short name T339
Test name
Test status
Simulation time 152598311945 ps
CPU time 117.02 seconds
Started Jul 17 05:03:58 PM PDT 24
Finished Jul 17 05:05:56 PM PDT 24
Peak memory 227532 kb
Host smart-b1600b8f-bdb0-42af-b248-02d9fcf4b119
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113749658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.4113749658
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1625859184
Short name T40
Test name
Test status
Simulation time 25780491775 ps
CPU time 3160.54 seconds
Started Jul 17 05:03:53 PM PDT 24
Finished Jul 17 05:56:35 PM PDT 24
Peak memory 232216 kb
Host smart-94e2cbe2-9499-4592-987c-15e5367a710d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625859184 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.1625859184
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1967898983
Short name T167
Test name
Test status
Simulation time 2467346280 ps
CPU time 23.03 seconds
Started Jul 17 05:03:55 PM PDT 24
Finished Jul 17 05:04:20 PM PDT 24
Peak memory 217176 kb
Host smart-6e421b63-3a5b-4229-bac2-f7a58da6570e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967898983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1967898983
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2689217389
Short name T319
Test name
Test status
Simulation time 24166181147 ps
CPU time 239.3 seconds
Started Jul 17 05:03:58 PM PDT 24
Finished Jul 17 05:07:58 PM PDT 24
Peak memory 228948 kb
Host smart-08762938-90ab-45e8-9468-f3d3e6c785fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689217389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2689217389
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1570028331
Short name T202
Test name
Test status
Simulation time 20089579003 ps
CPU time 45.95 seconds
Started Jul 17 05:03:57 PM PDT 24
Finished Jul 17 05:04:44 PM PDT 24
Peak memory 219224 kb
Host smart-3c4af36f-b0aa-446c-a6c3-e5db5332a8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570028331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1570028331
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2926162796
Short name T336
Test name
Test status
Simulation time 723919703 ps
CPU time 10.77 seconds
Started Jul 17 05:03:54 PM PDT 24
Finished Jul 17 05:04:06 PM PDT 24
Peak memory 219244 kb
Host smart-9608ffa7-3c2b-4411-bcbc-8b2afc3a707f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2926162796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2926162796
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.920024637
Short name T335
Test name
Test status
Simulation time 13559157425 ps
CPU time 56.45 seconds
Started Jul 17 05:03:56 PM PDT 24
Finished Jul 17 05:04:54 PM PDT 24
Peak memory 216376 kb
Host smart-6227303e-3d20-4232-b9ac-386197633f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920024637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.920024637
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.555433475
Short name T226
Test name
Test status
Simulation time 7055203238 ps
CPU time 82.31 seconds
Started Jul 17 05:03:56 PM PDT 24
Finished Jul 17 05:05:20 PM PDT 24
Peak memory 219512 kb
Host smart-0fff32d9-b898-427d-bf35-bd3c350f0109
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555433475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.555433475
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1702002441
Short name T361
Test name
Test status
Simulation time 68282964621 ps
CPU time 2292.6 seconds
Started Jul 17 05:03:55 PM PDT 24
Finished Jul 17 05:42:10 PM PDT 24
Peak memory 239388 kb
Host smart-6376a5a8-9bf4-476f-b904-4d0ee48b6970
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702002441 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.1702002441
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.4231768298
Short name T356
Test name
Test status
Simulation time 4109610721 ps
CPU time 31.43 seconds
Started Jul 17 05:03:07 PM PDT 24
Finished Jul 17 05:03:42 PM PDT 24
Peak memory 217120 kb
Host smart-7ef83839-0f66-43ef-b3ed-4d38812401a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231768298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.4231768298
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1670963070
Short name T157
Test name
Test status
Simulation time 41370143541 ps
CPU time 387.52 seconds
Started Jul 17 05:03:10 PM PDT 24
Finished Jul 17 05:09:39 PM PDT 24
Peak memory 235160 kb
Host smart-d356f328-1fea-422e-93ff-15b2f8fb0b27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670963070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1670963070
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1617935002
Short name T236
Test name
Test status
Simulation time 345779294 ps
CPU time 19.4 seconds
Started Jul 17 05:03:05 PM PDT 24
Finished Jul 17 05:03:29 PM PDT 24
Peak memory 219216 kb
Host smart-18ea1236-0049-43ef-bd64-1fa675b124de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617935002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1617935002
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1357587209
Short name T143
Test name
Test status
Simulation time 6208200628 ps
CPU time 19.93 seconds
Started Jul 17 05:03:06 PM PDT 24
Finished Jul 17 05:03:29 PM PDT 24
Peak memory 211992 kb
Host smart-9dc9f068-ac95-4151-ae1c-d0d47d519e37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1357587209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1357587209
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.4009180064
Short name T20
Test name
Test status
Simulation time 994458316 ps
CPU time 236.3 seconds
Started Jul 17 05:03:06 PM PDT 24
Finished Jul 17 05:07:07 PM PDT 24
Peak memory 237820 kb
Host smart-458fbec7-c606-4ba1-ac16-c24b4cbc1b3b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009180064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.4009180064
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2183660200
Short name T15
Test name
Test status
Simulation time 406555131 ps
CPU time 19.64 seconds
Started Jul 17 05:03:07 PM PDT 24
Finished Jul 17 05:03:30 PM PDT 24
Peak memory 216740 kb
Host smart-6d3d4f79-7afe-4a26-b00d-af682beee362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183660200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2183660200
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2869601660
Short name T173
Test name
Test status
Simulation time 6911071654 ps
CPU time 86.83 seconds
Started Jul 17 05:03:06 PM PDT 24
Finished Jul 17 05:04:37 PM PDT 24
Peak memory 219452 kb
Host smart-23491b3b-b7b9-4874-8b52-7d8df5ae99b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869601660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2869601660
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3028256725
Short name T200
Test name
Test status
Simulation time 1691924269 ps
CPU time 18.98 seconds
Started Jul 17 05:03:55 PM PDT 24
Finished Jul 17 05:04:16 PM PDT 24
Peak memory 217084 kb
Host smart-9fa84e17-802f-43b4-83c5-04b973323c45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028256725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3028256725
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1548775944
Short name T315
Test name
Test status
Simulation time 2847485040 ps
CPU time 206.61 seconds
Started Jul 17 05:03:54 PM PDT 24
Finished Jul 17 05:07:22 PM PDT 24
Peak memory 242068 kb
Host smart-3b9ee4ee-a1ad-45b2-a875-072ba2a649af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548775944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1548775944
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1326916404
Short name T273
Test name
Test status
Simulation time 13747034125 ps
CPU time 57.03 seconds
Started Jul 17 05:03:55 PM PDT 24
Finished Jul 17 05:04:54 PM PDT 24
Peak memory 219284 kb
Host smart-ea0dcdaa-35de-44b9-a01d-8e48b2a032d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326916404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1326916404
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2387822566
Short name T275
Test name
Test status
Simulation time 3029792362 ps
CPU time 27.65 seconds
Started Jul 17 05:03:55 PM PDT 24
Finished Jul 17 05:04:24 PM PDT 24
Peak memory 211452 kb
Host smart-0ad3a14e-e893-41b4-8a68-d2c7b9d07bea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2387822566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2387822566
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1715493987
Short name T71
Test name
Test status
Simulation time 14481793521 ps
CPU time 48.97 seconds
Started Jul 17 05:03:55 PM PDT 24
Finished Jul 17 05:04:46 PM PDT 24
Peak memory 216468 kb
Host smart-72fd3f1d-9918-47a1-87fc-7d3c64e51d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715493987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1715493987
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1328851560
Short name T337
Test name
Test status
Simulation time 48343698753 ps
CPU time 109.37 seconds
Started Jul 17 05:03:58 PM PDT 24
Finished Jul 17 05:05:49 PM PDT 24
Peak memory 219188 kb
Host smart-2a7a0394-814c-4f4c-8270-ef4c61a29f19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328851560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1328851560
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.924884231
Short name T43
Test name
Test status
Simulation time 48421383643 ps
CPU time 1823.74 seconds
Started Jul 17 05:03:58 PM PDT 24
Finished Jul 17 05:34:23 PM PDT 24
Peak memory 243980 kb
Host smart-5deb3667-0dce-43bf-a3a3-99f16e270f22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924884231 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.924884231
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1724245206
Short name T207
Test name
Test status
Simulation time 174197041 ps
CPU time 8.16 seconds
Started Jul 17 05:04:14 PM PDT 24
Finished Jul 17 05:04:23 PM PDT 24
Peak memory 217720 kb
Host smart-4ebbf80e-3150-4a14-8a35-93f2a7665f4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724245206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1724245206
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.693243424
Short name T298
Test name
Test status
Simulation time 27046131930 ps
CPU time 273.68 seconds
Started Jul 17 05:04:18 PM PDT 24
Finished Jul 17 05:08:53 PM PDT 24
Peak memory 239292 kb
Host smart-9953be41-eb3f-4989-be1d-aebfa63f1c54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693243424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.693243424
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2555843018
Short name T351
Test name
Test status
Simulation time 3945040480 ps
CPU time 44.19 seconds
Started Jul 17 05:04:18 PM PDT 24
Finished Jul 17 05:05:03 PM PDT 24
Peak memory 219312 kb
Host smart-e782f78f-d53f-43c3-b08a-0b78d073ce40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555843018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2555843018
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3471488982
Short name T131
Test name
Test status
Simulation time 721000446 ps
CPU time 10.63 seconds
Started Jul 17 05:03:56 PM PDT 24
Finished Jul 17 05:04:08 PM PDT 24
Peak memory 219272 kb
Host smart-69adabba-25a0-448a-9c90-6011bf56cc03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3471488982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3471488982
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3167583828
Short name T307
Test name
Test status
Simulation time 27797341821 ps
CPU time 56.04 seconds
Started Jul 17 05:03:55 PM PDT 24
Finished Jul 17 05:04:53 PM PDT 24
Peak memory 217100 kb
Host smart-6108636d-be6c-495b-8f95-626fab200645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167583828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3167583828
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3043096847
Short name T192
Test name
Test status
Simulation time 21845629941 ps
CPU time 60.1 seconds
Started Jul 17 05:03:56 PM PDT 24
Finished Jul 17 05:04:57 PM PDT 24
Peak memory 217236 kb
Host smart-fd617bb7-779f-43fe-a700-87c722697a12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043096847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3043096847
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.4168719863
Short name T224
Test name
Test status
Simulation time 174171855 ps
CPU time 8.21 seconds
Started Jul 17 05:04:16 PM PDT 24
Finished Jul 17 05:04:25 PM PDT 24
Peak memory 217000 kb
Host smart-b2cbecc4-f04a-4b7e-9652-b17742c36a80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168719863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.4168719863
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1738174519
Short name T133
Test name
Test status
Simulation time 182291659532 ps
CPU time 642.12 seconds
Started Jul 17 05:04:22 PM PDT 24
Finished Jul 17 05:15:05 PM PDT 24
Peak memory 237988 kb
Host smart-d7c693d8-5184-491d-8cd3-04e24d834360
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738174519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1738174519
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.784809241
Short name T239
Test name
Test status
Simulation time 9951467096 ps
CPU time 47.93 seconds
Started Jul 17 05:04:19 PM PDT 24
Finished Jul 17 05:05:08 PM PDT 24
Peak memory 219216 kb
Host smart-d929bd8f-7662-4575-82e1-36a86d621cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784809241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.784809241
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.4220999426
Short name T227
Test name
Test status
Simulation time 2091121016 ps
CPU time 21.97 seconds
Started Jul 17 05:04:19 PM PDT 24
Finished Jul 17 05:04:42 PM PDT 24
Peak memory 219312 kb
Host smart-2a344f00-bd08-4939-8b1b-b0b18082bd2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4220999426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.4220999426
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2594933497
Short name T86
Test name
Test status
Simulation time 4849573234 ps
CPU time 27.81 seconds
Started Jul 17 05:04:13 PM PDT 24
Finished Jul 17 05:04:41 PM PDT 24
Peak memory 219168 kb
Host smart-f3f4de0c-2c66-418b-b8c5-65214e0a9a38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594933497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2594933497
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3919328131
Short name T265
Test name
Test status
Simulation time 15955211201 ps
CPU time 27.19 seconds
Started Jul 17 05:04:12 PM PDT 24
Finished Jul 17 05:04:40 PM PDT 24
Peak memory 217516 kb
Host smart-897c85d7-9fd5-46ae-996c-9cf972b3a715
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919328131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3919328131
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1581081773
Short name T144
Test name
Test status
Simulation time 239122888415 ps
CPU time 190.23 seconds
Started Jul 17 05:04:15 PM PDT 24
Finished Jul 17 05:07:26 PM PDT 24
Peak memory 217012 kb
Host smart-562f8308-221c-427b-a581-9a8c2272cc6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581081773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1581081773
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2689080311
Short name T235
Test name
Test status
Simulation time 6948942383 ps
CPU time 31.74 seconds
Started Jul 17 05:04:18 PM PDT 24
Finished Jul 17 05:04:51 PM PDT 24
Peak memory 219388 kb
Host smart-a3912903-70eb-4cee-874a-2cce97bd2c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689080311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2689080311
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1821832582
Short name T291
Test name
Test status
Simulation time 4009988405 ps
CPU time 33.35 seconds
Started Jul 17 05:04:19 PM PDT 24
Finished Jul 17 05:04:53 PM PDT 24
Peak memory 219316 kb
Host smart-0f479b7e-db15-45e7-957b-3452f2aa8b54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1821832582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1821832582
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2465537379
Short name T322
Test name
Test status
Simulation time 2440932143 ps
CPU time 35.36 seconds
Started Jul 17 05:04:19 PM PDT 24
Finished Jul 17 05:04:56 PM PDT 24
Peak memory 216476 kb
Host smart-2c3a04d3-900a-4d20-8993-fd8b1b70367e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465537379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2465537379
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3153495089
Short name T210
Test name
Test status
Simulation time 762627056 ps
CPU time 28.52 seconds
Started Jul 17 05:04:13 PM PDT 24
Finished Jul 17 05:04:43 PM PDT 24
Peak memory 219292 kb
Host smart-9601c2a3-4eef-49cc-b011-5d877bf6b747
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153495089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3153495089
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.4158569753
Short name T186
Test name
Test status
Simulation time 7011001637 ps
CPU time 28.2 seconds
Started Jul 17 05:04:17 PM PDT 24
Finished Jul 17 05:04:46 PM PDT 24
Peak memory 217640 kb
Host smart-734794a4-0ce9-47f5-8fb9-3a268b0c5b07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158569753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.4158569753
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.689686733
Short name T250
Test name
Test status
Simulation time 265811992282 ps
CPU time 526.61 seconds
Started Jul 17 05:04:14 PM PDT 24
Finished Jul 17 05:13:02 PM PDT 24
Peak memory 216848 kb
Host smart-3638a4c0-0da9-49d4-a47c-8161d77944b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689686733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.689686733
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.438458869
Short name T324
Test name
Test status
Simulation time 1374467884 ps
CPU time 19.25 seconds
Started Jul 17 05:04:18 PM PDT 24
Finished Jul 17 05:04:38 PM PDT 24
Peak memory 219260 kb
Host smart-15ebf791-dbb7-41c5-8265-08ac345332f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438458869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.438458869
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.658791865
Short name T162
Test name
Test status
Simulation time 5108013619 ps
CPU time 26.08 seconds
Started Jul 17 05:04:19 PM PDT 24
Finished Jul 17 05:04:46 PM PDT 24
Peak memory 219608 kb
Host smart-36b56aca-7074-4472-a094-6c1285d91008
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=658791865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.658791865
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1408491892
Short name T288
Test name
Test status
Simulation time 17413326919 ps
CPU time 66.48 seconds
Started Jul 17 05:04:12 PM PDT 24
Finished Jul 17 05:05:20 PM PDT 24
Peak memory 215736 kb
Host smart-c7b51271-261b-4770-b2ee-cede2148aa9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408491892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1408491892
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.4175827297
Short name T42
Test name
Test status
Simulation time 280379345343 ps
CPU time 2571.22 seconds
Started Jul 17 05:04:17 PM PDT 24
Finished Jul 17 05:47:09 PM PDT 24
Peak memory 252196 kb
Host smart-1e3cee0d-7cb0-4824-b77c-a71955c9c182
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175827297 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.4175827297
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2549607787
Short name T148
Test name
Test status
Simulation time 30746293580 ps
CPU time 30.09 seconds
Started Jul 17 05:04:14 PM PDT 24
Finished Jul 17 05:04:45 PM PDT 24
Peak memory 217296 kb
Host smart-51982c3f-b2f2-4d87-863d-748ca083ff35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549607787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2549607787
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1445371962
Short name T300
Test name
Test status
Simulation time 106460426750 ps
CPU time 328.72 seconds
Started Jul 17 05:04:15 PM PDT 24
Finished Jul 17 05:09:45 PM PDT 24
Peak memory 237780 kb
Host smart-3650f84b-0c97-4940-ba89-60f8be79f398
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445371962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1445371962
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2136042697
Short name T285
Test name
Test status
Simulation time 12421819696 ps
CPU time 38.71 seconds
Started Jul 17 05:04:16 PM PDT 24
Finished Jul 17 05:04:55 PM PDT 24
Peak memory 219408 kb
Host smart-e1fd9b55-a86c-40a0-b5fa-e8cae00761af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136042697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2136042697
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.305055456
Short name T149
Test name
Test status
Simulation time 2579707165 ps
CPU time 15.44 seconds
Started Jul 17 05:04:14 PM PDT 24
Finished Jul 17 05:04:30 PM PDT 24
Peak memory 219128 kb
Host smart-be0330a9-33bb-407b-bcfd-37462b3879f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=305055456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.305055456
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2925225088
Short name T318
Test name
Test status
Simulation time 1837791756 ps
CPU time 36.29 seconds
Started Jul 17 05:04:12 PM PDT 24
Finished Jul 17 05:04:49 PM PDT 24
Peak memory 217792 kb
Host smart-35010717-8d1a-404c-b585-b828463b8a29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925225088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2925225088
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2588786292
Short name T344
Test name
Test status
Simulation time 6896618691 ps
CPU time 29.29 seconds
Started Jul 17 05:04:24 PM PDT 24
Finished Jul 17 05:04:55 PM PDT 24
Peak memory 213244 kb
Host smart-df2dd1af-37f0-423e-b1be-581e89e90e8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588786292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2588786292
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.832033950
Short name T326
Test name
Test status
Simulation time 135630837913 ps
CPU time 285.34 seconds
Started Jul 17 05:04:15 PM PDT 24
Finished Jul 17 05:09:01 PM PDT 24
Peak memory 234384 kb
Host smart-4ae4be95-ef4b-4259-933f-07dfb28b63be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832033950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.832033950
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2155184018
Short name T229
Test name
Test status
Simulation time 2396421839 ps
CPU time 36.31 seconds
Started Jul 17 05:04:13 PM PDT 24
Finished Jul 17 05:04:51 PM PDT 24
Peak memory 219280 kb
Host smart-a1b31a9d-5542-4e69-8a2f-af2dfdad22c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155184018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2155184018
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2245680382
Short name T341
Test name
Test status
Simulation time 4224953475 ps
CPU time 21.94 seconds
Started Jul 17 05:04:20 PM PDT 24
Finished Jul 17 05:04:43 PM PDT 24
Peak memory 219328 kb
Host smart-a1c1f67c-06ec-4a16-a77e-901334e4e5e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2245680382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2245680382
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2376940899
Short name T188
Test name
Test status
Simulation time 3424649669 ps
CPU time 39.59 seconds
Started Jul 17 05:04:14 PM PDT 24
Finished Jul 17 05:04:54 PM PDT 24
Peak memory 218076 kb
Host smart-1113ad04-07aa-447f-9310-c327f6df3fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376940899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2376940899
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.11298381
Short name T303
Test name
Test status
Simulation time 10309775655 ps
CPU time 113.99 seconds
Started Jul 17 05:04:14 PM PDT 24
Finished Jul 17 05:06:09 PM PDT 24
Peak memory 220832 kb
Host smart-9f7fa382-db24-4298-899d-c7508272795d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11298381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 36.rom_ctrl_stress_all.11298381
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1984744767
Short name T216
Test name
Test status
Simulation time 1586489844 ps
CPU time 14.26 seconds
Started Jul 17 05:04:26 PM PDT 24
Finished Jul 17 05:04:44 PM PDT 24
Peak memory 217044 kb
Host smart-b1752c0d-3fce-4a13-803b-e6d68e46db64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984744767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1984744767
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.472183765
Short name T329
Test name
Test status
Simulation time 2754608492 ps
CPU time 202.83 seconds
Started Jul 17 05:04:24 PM PDT 24
Finished Jul 17 05:07:48 PM PDT 24
Peak memory 219480 kb
Host smart-2f1fa029-6b42-4797-a582-5b17e0cbbfb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472183765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.472183765
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2638230432
Short name T209
Test name
Test status
Simulation time 15599758147 ps
CPU time 64.47 seconds
Started Jul 17 05:04:26 PM PDT 24
Finished Jul 17 05:05:34 PM PDT 24
Peak memory 219120 kb
Host smart-2a24945f-2424-4cf7-9b8c-df74f6019e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638230432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2638230432
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.270260241
Short name T137
Test name
Test status
Simulation time 7207881214 ps
CPU time 29.42 seconds
Started Jul 17 05:04:28 PM PDT 24
Finished Jul 17 05:05:00 PM PDT 24
Peak memory 211984 kb
Host smart-f7a042d6-8813-43fe-94d1-0737da01d8a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=270260241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.270260241
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3136326504
Short name T178
Test name
Test status
Simulation time 28139552178 ps
CPU time 59.54 seconds
Started Jul 17 05:04:22 PM PDT 24
Finished Jul 17 05:05:23 PM PDT 24
Peak memory 218088 kb
Host smart-2ae673b4-c793-481e-b644-1465861ae070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136326504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3136326504
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.735978175
Short name T346
Test name
Test status
Simulation time 52380280978 ps
CPU time 217.25 seconds
Started Jul 17 05:04:22 PM PDT 24
Finished Jul 17 05:08:00 PM PDT 24
Peak memory 220408 kb
Host smart-00ecf5e6-7065-486a-bd1c-a97ff9f31471
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735978175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.735978175
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2841689731
Short name T129
Test name
Test status
Simulation time 1055686654 ps
CPU time 14.71 seconds
Started Jul 17 05:04:24 PM PDT 24
Finished Jul 17 05:04:40 PM PDT 24
Peak memory 217008 kb
Host smart-6a979801-4ab4-4ada-b0c4-c3c6077a156f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841689731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2841689731
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3063251549
Short name T334
Test name
Test status
Simulation time 1685176401 ps
CPU time 23.7 seconds
Started Jul 17 05:04:27 PM PDT 24
Finished Jul 17 05:04:53 PM PDT 24
Peak memory 218752 kb
Host smart-02929b62-56a3-4b12-9105-d4aaf7f5b5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063251549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3063251549
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.584000003
Short name T5
Test name
Test status
Simulation time 4806500252 ps
CPU time 23.26 seconds
Started Jul 17 05:04:22 PM PDT 24
Finished Jul 17 05:04:46 PM PDT 24
Peak memory 219316 kb
Host smart-d1972a2f-55d2-4245-8fb3-215ceb88f03d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=584000003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.584000003
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.1525275629
Short name T321
Test name
Test status
Simulation time 714062338 ps
CPU time 19.4 seconds
Started Jul 17 05:04:25 PM PDT 24
Finished Jul 17 05:04:46 PM PDT 24
Peak memory 215988 kb
Host smart-9de0bd67-c655-4c27-b052-289f182600a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525275629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1525275629
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3184017384
Short name T140
Test name
Test status
Simulation time 29386594491 ps
CPU time 60.28 seconds
Started Jul 17 05:04:24 PM PDT 24
Finished Jul 17 05:05:26 PM PDT 24
Peak memory 219364 kb
Host smart-15794aed-bd61-4197-a601-3123acd400de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184017384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3184017384
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3749745886
Short name T52
Test name
Test status
Simulation time 11862304394 ps
CPU time 26.17 seconds
Started Jul 17 05:04:27 PM PDT 24
Finished Jul 17 05:04:56 PM PDT 24
Peak memory 217424 kb
Host smart-ff4376b3-ebea-46af-a4d3-173393fce5be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749745886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3749745886
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1373722972
Short name T347
Test name
Test status
Simulation time 79646495708 ps
CPU time 291.2 seconds
Started Jul 17 05:04:24 PM PDT 24
Finished Jul 17 05:09:17 PM PDT 24
Peak memory 236408 kb
Host smart-a36832bc-d2ac-431c-8dd9-ac74e2a54082
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373722972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1373722972
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3239971890
Short name T241
Test name
Test status
Simulation time 33186240426 ps
CPU time 69.56 seconds
Started Jul 17 05:04:22 PM PDT 24
Finished Jul 17 05:05:33 PM PDT 24
Peak memory 219196 kb
Host smart-375a01bd-ed81-4649-aabc-03cac00006fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239971890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3239971890
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3323746470
Short name T299
Test name
Test status
Simulation time 352273657 ps
CPU time 10.35 seconds
Started Jul 17 05:04:25 PM PDT 24
Finished Jul 17 05:04:39 PM PDT 24
Peak memory 219248 kb
Host smart-25da2383-d0ee-43a0-b226-3d0fa6897760
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3323746470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3323746470
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.3211409226
Short name T53
Test name
Test status
Simulation time 697699300 ps
CPU time 20.29 seconds
Started Jul 17 05:04:24 PM PDT 24
Finished Jul 17 05:04:46 PM PDT 24
Peak memory 216428 kb
Host smart-eadf95e8-240a-4395-946c-50a8755c90d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211409226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.3211409226
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2462951070
Short name T270
Test name
Test status
Simulation time 11772144216 ps
CPU time 98.23 seconds
Started Jul 17 05:04:25 PM PDT 24
Finished Jul 17 05:06:06 PM PDT 24
Peak memory 220908 kb
Host smart-ab0af0f3-98b7-43a5-808d-78048c7db462
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462951070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2462951070
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1246893083
Short name T197
Test name
Test status
Simulation time 3781174010 ps
CPU time 31.64 seconds
Started Jul 17 05:03:17 PM PDT 24
Finished Jul 17 05:03:50 PM PDT 24
Peak memory 217268 kb
Host smart-6745abc8-8cb4-4509-848f-7b34fc01e907
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246893083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1246893083
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1168662137
Short name T340
Test name
Test status
Simulation time 107418072378 ps
CPU time 516.55 seconds
Started Jul 17 05:03:19 PM PDT 24
Finished Jul 17 05:11:57 PM PDT 24
Peak memory 233716 kb
Host smart-74759dfc-cb2d-4458-a153-fa9df6033c46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168662137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1168662137
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2367872267
Short name T126
Test name
Test status
Simulation time 54600344572 ps
CPU time 40.47 seconds
Started Jul 17 05:03:22 PM PDT 24
Finished Jul 17 05:04:05 PM PDT 24
Peak memory 219284 kb
Host smart-3776025b-ceb1-44cc-9d05-5a9d7c4cc785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367872267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2367872267
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3658469664
Short name T259
Test name
Test status
Simulation time 177276972 ps
CPU time 10.79 seconds
Started Jul 17 05:03:22 PM PDT 24
Finished Jul 17 05:03:35 PM PDT 24
Peak memory 219184 kb
Host smart-2819316a-ba80-47f0-8f5d-5f17dea95cbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3658469664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3658469664
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3634452106
Short name T25
Test name
Test status
Simulation time 1630205739 ps
CPU time 119.24 seconds
Started Jul 17 05:03:17 PM PDT 24
Finished Jul 17 05:05:17 PM PDT 24
Peak memory 234344 kb
Host smart-7936e664-fdd9-43a2-8e53-6305335846c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634452106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3634452106
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2578100784
Short name T12
Test name
Test status
Simulation time 735459592 ps
CPU time 20.59 seconds
Started Jul 17 05:03:06 PM PDT 24
Finished Jul 17 05:03:31 PM PDT 24
Peak memory 215564 kb
Host smart-2a95911c-6cb9-4c59-8bd7-31bc25785c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578100784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2578100784
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2732221687
Short name T247
Test name
Test status
Simulation time 25124964407 ps
CPU time 135.32 seconds
Started Jul 17 05:03:17 PM PDT 24
Finished Jul 17 05:05:33 PM PDT 24
Peak memory 219292 kb
Host smart-1d9a13ba-4516-467d-be91-12b91aa9ff05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732221687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2732221687
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1463067627
Short name T37
Test name
Test status
Simulation time 61273595479 ps
CPU time 685.5 seconds
Started Jul 17 05:03:22 PM PDT 24
Finished Jul 17 05:14:50 PM PDT 24
Peak memory 235776 kb
Host smart-df41624e-c7dd-4e85-8014-9b8671fc9b6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463067627 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.1463067627
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2364203318
Short name T199
Test name
Test status
Simulation time 5891772525 ps
CPU time 26.7 seconds
Started Jul 17 05:04:24 PM PDT 24
Finished Jul 17 05:04:54 PM PDT 24
Peak memory 217636 kb
Host smart-9537581a-bea3-4b63-b0fa-396821e7ceee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364203318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2364203318
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1658207833
Short name T28
Test name
Test status
Simulation time 101811833815 ps
CPU time 479.74 seconds
Started Jul 17 05:04:24 PM PDT 24
Finished Jul 17 05:12:26 PM PDT 24
Peak memory 233864 kb
Host smart-d57456e6-d1b2-4f27-9283-3b98e6e728b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658207833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1658207833
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1509782159
Short name T331
Test name
Test status
Simulation time 2795812091 ps
CPU time 38.06 seconds
Started Jul 17 05:04:24 PM PDT 24
Finished Jul 17 05:05:04 PM PDT 24
Peak memory 219312 kb
Host smart-a3908494-adb5-4ce7-a0fa-f7a4d8fc80bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509782159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1509782159
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.4256851404
Short name T242
Test name
Test status
Simulation time 3031927430 ps
CPU time 19.1 seconds
Started Jul 17 05:08:38 PM PDT 24
Finished Jul 17 05:08:59 PM PDT 24
Peak memory 211268 kb
Host smart-226bfcc6-f0da-4e59-92a4-d07d4b3cdac9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4256851404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.4256851404
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1012051963
Short name T206
Test name
Test status
Simulation time 2158748828 ps
CPU time 20.33 seconds
Started Jul 17 05:04:24 PM PDT 24
Finished Jul 17 05:04:46 PM PDT 24
Peak memory 216820 kb
Host smart-2777ec28-7685-48a6-8976-217f3ed54d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012051963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1012051963
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1623176038
Short name T261
Test name
Test status
Simulation time 429669896 ps
CPU time 21.25 seconds
Started Jul 17 05:04:24 PM PDT 24
Finished Jul 17 05:04:48 PM PDT 24
Peak memory 217700 kb
Host smart-7dd1913a-37d7-4f5d-86fd-489deda12b06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623176038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1623176038
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2168354205
Short name T312
Test name
Test status
Simulation time 17378147035 ps
CPU time 31.19 seconds
Started Jul 17 05:04:23 PM PDT 24
Finished Jul 17 05:04:56 PM PDT 24
Peak memory 217324 kb
Host smart-976a2adb-10a8-4a50-b651-9da6a8ec905b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168354205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2168354205
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1650649912
Short name T234
Test name
Test status
Simulation time 5115450002 ps
CPU time 329.29 seconds
Started Jul 17 05:04:24 PM PDT 24
Finished Jul 17 05:09:56 PM PDT 24
Peak memory 226104 kb
Host smart-8acb59ab-b766-4a5d-86b9-7627f8fcebbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650649912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1650649912
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2392830875
Short name T169
Test name
Test status
Simulation time 2884320917 ps
CPU time 30.1 seconds
Started Jul 17 05:04:24 PM PDT 24
Finished Jul 17 05:04:56 PM PDT 24
Peak memory 219304 kb
Host smart-e6b4357d-56b8-480f-8472-8dae0f23ad21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392830875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2392830875
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2401429563
Short name T359
Test name
Test status
Simulation time 274598801 ps
CPU time 10.88 seconds
Started Jul 17 05:04:26 PM PDT 24
Finished Jul 17 05:04:40 PM PDT 24
Peak memory 219252 kb
Host smart-e711ee5a-47a9-42ab-814f-1b325fd91cac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2401429563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2401429563
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.4093685630
Short name T8
Test name
Test status
Simulation time 6879847942 ps
CPU time 60.61 seconds
Started Jul 17 05:04:24 PM PDT 24
Finished Jul 17 05:05:26 PM PDT 24
Peak memory 217212 kb
Host smart-43e26b75-3d92-4ef3-9c8e-0ec84875e496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093685630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.4093685630
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2179624688
Short name T118
Test name
Test status
Simulation time 414404747 ps
CPU time 28.08 seconds
Started Jul 17 05:04:28 PM PDT 24
Finished Jul 17 05:04:59 PM PDT 24
Peak memory 219192 kb
Host smart-ccf00baf-681a-40fa-a88d-d5049c3cfdd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179624688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2179624688
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.4118508896
Short name T2
Test name
Test status
Simulation time 13620956742 ps
CPU time 27.94 seconds
Started Jul 17 05:04:25 PM PDT 24
Finished Jul 17 05:04:56 PM PDT 24
Peak memory 217468 kb
Host smart-737904df-d5f1-4f0f-a6bc-6c2663dd5990
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118508896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.4118508896
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1201484279
Short name T287
Test name
Test status
Simulation time 4092013615 ps
CPU time 169.81 seconds
Started Jul 17 05:04:23 PM PDT 24
Finished Jul 17 05:07:15 PM PDT 24
Peak memory 228468 kb
Host smart-2d32c5ae-5f29-4c70-8f21-0ada331a7db6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201484279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1201484279
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.617785143
Short name T23
Test name
Test status
Simulation time 3769734963 ps
CPU time 43.43 seconds
Started Jul 17 05:04:26 PM PDT 24
Finished Jul 17 05:05:12 PM PDT 24
Peak memory 218772 kb
Host smart-47c30901-c4a7-4fc7-a9a3-28bb03d494a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617785143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.617785143
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.4179459443
Short name T253
Test name
Test status
Simulation time 347572533 ps
CPU time 10.16 seconds
Started Jul 17 05:04:23 PM PDT 24
Finished Jul 17 05:04:35 PM PDT 24
Peak memory 219240 kb
Host smart-f1d498f3-5a38-4a25-86b1-f1332bb40969
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4179459443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.4179459443
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3966155591
Short name T176
Test name
Test status
Simulation time 361768519 ps
CPU time 20.3 seconds
Started Jul 17 05:04:26 PM PDT 24
Finished Jul 17 05:04:49 PM PDT 24
Peak memory 215980 kb
Host smart-f13acda1-b99c-47d6-8c10-fadd7c9a0088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966155591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3966155591
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1581696358
Short name T267
Test name
Test status
Simulation time 39122170645 ps
CPU time 376.65 seconds
Started Jul 17 05:04:25 PM PDT 24
Finished Jul 17 05:10:44 PM PDT 24
Peak memory 222004 kb
Host smart-1d513665-2f87-4bb0-9839-61122b8ae757
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581696358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1581696358
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2238945244
Short name T220
Test name
Test status
Simulation time 16837035217 ps
CPU time 27.48 seconds
Started Jul 17 05:04:27 PM PDT 24
Finished Jul 17 05:04:57 PM PDT 24
Peak memory 217596 kb
Host smart-874816c1-2530-4002-9252-529061ca35da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238945244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2238945244
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3115816614
Short name T217
Test name
Test status
Simulation time 100602608809 ps
CPU time 953.12 seconds
Started Jul 17 05:04:27 PM PDT 24
Finished Jul 17 05:20:23 PM PDT 24
Peak memory 229748 kb
Host smart-c091fe86-1137-4eac-86a5-0841123744e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115816614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3115816614
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.4212476668
Short name T201
Test name
Test status
Simulation time 7284265108 ps
CPU time 61.63 seconds
Started Jul 17 05:04:25 PM PDT 24
Finished Jul 17 05:05:29 PM PDT 24
Peak memory 219284 kb
Host smart-7cb23de2-3dba-4271-b382-ee9e097dd8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212476668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.4212476668
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.811517110
Short name T146
Test name
Test status
Simulation time 882466017 ps
CPU time 13.55 seconds
Started Jul 17 05:04:26 PM PDT 24
Finished Jul 17 05:04:43 PM PDT 24
Peak memory 218852 kb
Host smart-09b945b7-35e7-4776-975e-84d16c175d03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=811517110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.811517110
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3048573508
Short name T96
Test name
Test status
Simulation time 9761953793 ps
CPU time 36.84 seconds
Started Jul 17 05:04:24 PM PDT 24
Finished Jul 17 05:05:04 PM PDT 24
Peak memory 216476 kb
Host smart-e3135c5d-28b9-4e86-99b6-5814e9a90819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048573508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3048573508
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2433540396
Short name T233
Test name
Test status
Simulation time 805346982 ps
CPU time 24.06 seconds
Started Jul 17 05:04:23 PM PDT 24
Finished Jul 17 05:04:49 PM PDT 24
Peak memory 219248 kb
Host smart-9c410a5c-86b1-4bc5-991f-11684734b545
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433540396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2433540396
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3940294991
Short name T213
Test name
Test status
Simulation time 1894625520 ps
CPU time 20.3 seconds
Started Jul 17 05:04:27 PM PDT 24
Finished Jul 17 05:04:50 PM PDT 24
Peak memory 217232 kb
Host smart-3c063ad1-4081-426d-8ffe-6dad4256f6b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940294991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3940294991
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3441138144
Short name T182
Test name
Test status
Simulation time 138777231467 ps
CPU time 762.39 seconds
Started Jul 17 05:04:27 PM PDT 24
Finished Jul 17 05:17:12 PM PDT 24
Peak memory 234740 kb
Host smart-35d5b10a-0dd6-44e3-8c76-174a930f84b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441138144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3441138144
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1261734448
Short name T165
Test name
Test status
Simulation time 7516312870 ps
CPU time 41.69 seconds
Started Jul 17 05:04:27 PM PDT 24
Finished Jul 17 05:05:12 PM PDT 24
Peak memory 219348 kb
Host smart-137bd5f7-eab5-465c-9700-66338da78bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261734448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1261734448
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1293601932
Short name T85
Test name
Test status
Simulation time 919321099 ps
CPU time 10.34 seconds
Started Jul 17 05:04:27 PM PDT 24
Finished Jul 17 05:04:40 PM PDT 24
Peak memory 219244 kb
Host smart-9f800fa2-3ba5-40b1-8172-828d02f9fd1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1293601932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1293601932
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.849682311
Short name T323
Test name
Test status
Simulation time 350983595 ps
CPU time 20.11 seconds
Started Jul 17 05:04:27 PM PDT 24
Finished Jul 17 05:04:50 PM PDT 24
Peak memory 215868 kb
Host smart-40a3f968-f7a9-4bfa-b0eb-f9890440f93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849682311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.849682311
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1491834189
Short name T237
Test name
Test status
Simulation time 6704336771 ps
CPU time 69.62 seconds
Started Jul 17 05:04:27 PM PDT 24
Finished Jul 17 05:05:40 PM PDT 24
Peak memory 219340 kb
Host smart-18f58991-a20d-4565-8457-931d579f592b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491834189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1491834189
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3621059783
Short name T181
Test name
Test status
Simulation time 660454280 ps
CPU time 8.6 seconds
Started Jul 17 05:04:29 PM PDT 24
Finished Jul 17 05:04:40 PM PDT 24
Peak memory 217112 kb
Host smart-819e7948-5314-4d9b-b78e-002a59b67506
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621059783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3621059783
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.144170120
Short name T164
Test name
Test status
Simulation time 27038075046 ps
CPU time 268.52 seconds
Started Jul 17 05:04:29 PM PDT 24
Finished Jul 17 05:09:00 PM PDT 24
Peak memory 216044 kb
Host smart-06347a7e-9d15-47ae-805f-a62ea427bb30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144170120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.144170120
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1696671542
Short name T345
Test name
Test status
Simulation time 21819343890 ps
CPU time 51.08 seconds
Started Jul 17 05:04:28 PM PDT 24
Finished Jul 17 05:05:22 PM PDT 24
Peak memory 219216 kb
Host smart-449e9d6f-3c18-4d88-bbcf-57e0f44bd5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696671542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1696671542
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.902733704
Short name T205
Test name
Test status
Simulation time 10874102131 ps
CPU time 25.25 seconds
Started Jul 17 05:04:28 PM PDT 24
Finished Jul 17 05:04:56 PM PDT 24
Peak memory 211540 kb
Host smart-7d369a1b-7299-4556-a0a5-060d41c33ec7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=902733704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.902733704
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1210216415
Short name T343
Test name
Test status
Simulation time 8069717929 ps
CPU time 79.38 seconds
Started Jul 17 05:04:27 PM PDT 24
Finished Jul 17 05:05:49 PM PDT 24
Peak memory 216536 kb
Host smart-530acdd6-0e57-4864-bdb5-22da2483249d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210216415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1210216415
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2828747057
Short name T116
Test name
Test status
Simulation time 15860373660 ps
CPU time 46.49 seconds
Started Jul 17 05:04:23 PM PDT 24
Finished Jul 17 05:05:11 PM PDT 24
Peak memory 217792 kb
Host smart-5a0cba57-a817-43b7-bc9c-08336ce7844a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828747057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2828747057
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2147246127
Short name T17
Test name
Test status
Simulation time 174489148 ps
CPU time 8.37 seconds
Started Jul 17 05:04:36 PM PDT 24
Finished Jul 17 05:04:45 PM PDT 24
Peak memory 217120 kb
Host smart-0b6c0384-7720-4828-a1be-d88ed097ca0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147246127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2147246127
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2681281402
Short name T222
Test name
Test status
Simulation time 128772582610 ps
CPU time 573.73 seconds
Started Jul 17 05:04:27 PM PDT 24
Finished Jul 17 05:14:04 PM PDT 24
Peak memory 233756 kb
Host smart-9992b5fb-f910-409f-83e7-8dd2c20bf2c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681281402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2681281402
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.334917092
Short name T24
Test name
Test status
Simulation time 662010626 ps
CPU time 19.63 seconds
Started Jul 17 05:04:31 PM PDT 24
Finished Jul 17 05:04:52 PM PDT 24
Peak memory 219268 kb
Host smart-84ef972e-8559-4627-afed-e8849ff6e377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334917092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.334917092
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.774579194
Short name T159
Test name
Test status
Simulation time 39040765877 ps
CPU time 27.23 seconds
Started Jul 17 05:04:25 PM PDT 24
Finished Jul 17 05:04:55 PM PDT 24
Peak memory 219276 kb
Host smart-fcde94af-a489-412f-937a-be0c8357b3db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=774579194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.774579194
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.2354846399
Short name T174
Test name
Test status
Simulation time 8268363224 ps
CPU time 65.4 seconds
Started Jul 17 05:04:30 PM PDT 24
Finished Jul 17 05:05:37 PM PDT 24
Peak memory 216940 kb
Host smart-9721ae7d-15c8-46cf-8daa-f6b7194d2a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354846399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2354846399
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3069248041
Short name T255
Test name
Test status
Simulation time 12129014381 ps
CPU time 37.8 seconds
Started Jul 17 05:04:30 PM PDT 24
Finished Jul 17 05:05:09 PM PDT 24
Peak memory 214812 kb
Host smart-ae357fe6-261c-4163-acc5-6e71755ac08e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069248041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3069248041
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2689274312
Short name T313
Test name
Test status
Simulation time 3736195935 ps
CPU time 14.33 seconds
Started Jul 17 05:04:48 PM PDT 24
Finished Jul 17 05:05:04 PM PDT 24
Peak memory 217100 kb
Host smart-4d459eef-1882-422d-8f79-0309bbc4abd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689274312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2689274312
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3513345184
Short name T328
Test name
Test status
Simulation time 14291800785 ps
CPU time 40.4 seconds
Started Jul 17 05:04:38 PM PDT 24
Finished Jul 17 05:05:21 PM PDT 24
Peak memory 219372 kb
Host smart-eb60873c-096e-411c-853a-84171e1943c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513345184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3513345184
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3096625798
Short name T281
Test name
Test status
Simulation time 3370396400 ps
CPU time 29.87 seconds
Started Jul 17 05:04:36 PM PDT 24
Finished Jul 17 05:05:08 PM PDT 24
Peak memory 219312 kb
Host smart-2acc9a27-8989-434f-a21c-ef2dc8f87133
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3096625798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3096625798
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.463306040
Short name T189
Test name
Test status
Simulation time 3938498698 ps
CPU time 47.11 seconds
Started Jul 17 05:04:37 PM PDT 24
Finished Jul 17 05:05:25 PM PDT 24
Peak memory 216156 kb
Host smart-0650289d-d432-4b5d-bfde-f254ed54a03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463306040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.463306040
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1392452553
Short name T171
Test name
Test status
Simulation time 29285016683 ps
CPU time 138.6 seconds
Started Jul 17 05:04:39 PM PDT 24
Finished Jul 17 05:07:00 PM PDT 24
Peak memory 219504 kb
Host smart-da35b14b-f454-44a3-b743-78285cb83fe5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392452553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1392452553
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.275810897
Short name T190
Test name
Test status
Simulation time 15942424708 ps
CPU time 23.67 seconds
Started Jul 17 05:04:37 PM PDT 24
Finished Jul 17 05:05:02 PM PDT 24
Peak memory 217448 kb
Host smart-ab2e7fdf-9e52-4171-9505-79be3afff7a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275810897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.275810897
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3877352335
Short name T230
Test name
Test status
Simulation time 45625212415 ps
CPU time 162.21 seconds
Started Jul 17 05:04:39 PM PDT 24
Finished Jul 17 05:07:23 PM PDT 24
Peak memory 236388 kb
Host smart-86e34e91-22f6-4c54-a5b5-0cd3d482f946
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877352335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3877352335
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.302799272
Short name T177
Test name
Test status
Simulation time 332500694 ps
CPU time 18.98 seconds
Started Jul 17 05:04:39 PM PDT 24
Finished Jul 17 05:05:00 PM PDT 24
Peak memory 219216 kb
Host smart-272bf096-9a91-4746-8ad2-ae64a0fbd936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302799272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.302799272
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1960161628
Short name T111
Test name
Test status
Simulation time 2834888952 ps
CPU time 25.09 seconds
Started Jul 17 05:04:37 PM PDT 24
Finished Jul 17 05:05:03 PM PDT 24
Peak memory 211240 kb
Host smart-43491ac9-64ec-437b-b73f-474290b21ccd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1960161628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1960161628
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3109772590
Short name T262
Test name
Test status
Simulation time 40380948535 ps
CPU time 67.23 seconds
Started Jul 17 05:04:36 PM PDT 24
Finished Jul 17 05:05:45 PM PDT 24
Peak memory 216216 kb
Host smart-47e036f9-0422-4747-b759-92415b7ba467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109772590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3109772590
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3241638176
Short name T70
Test name
Test status
Simulation time 567291355 ps
CPU time 32.04 seconds
Started Jul 17 05:04:37 PM PDT 24
Finished Jul 17 05:05:11 PM PDT 24
Peak memory 220032 kb
Host smart-abc9afcd-f082-49c3-8fc9-37761acc4a78
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241638176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3241638176
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.182323353
Short name T286
Test name
Test status
Simulation time 3017626541 ps
CPU time 12.47 seconds
Started Jul 17 05:04:37 PM PDT 24
Finished Jul 17 05:04:51 PM PDT 24
Peak memory 217284 kb
Host smart-164b6905-5681-4aa9-9470-bfefa48c6f8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182323353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.182323353
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3161848150
Short name T161
Test name
Test status
Simulation time 22143184315 ps
CPU time 335.02 seconds
Started Jul 17 05:04:36 PM PDT 24
Finished Jul 17 05:10:13 PM PDT 24
Peak memory 237996 kb
Host smart-71b16e7b-595d-456c-b010-d87ad521e3a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161848150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3161848150
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3972746761
Short name T290
Test name
Test status
Simulation time 35589489883 ps
CPU time 70.65 seconds
Started Jul 17 05:04:38 PM PDT 24
Finished Jul 17 05:05:51 PM PDT 24
Peak memory 219308 kb
Host smart-1ae00843-1f08-49ba-9ece-d0f6d18d43e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972746761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3972746761
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.4275565135
Short name T145
Test name
Test status
Simulation time 32886238212 ps
CPU time 62.45 seconds
Started Jul 17 05:04:36 PM PDT 24
Finished Jul 17 05:05:39 PM PDT 24
Peak memory 215780 kb
Host smart-e9b4f996-b56e-4f65-b5cb-e7f2006a1a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275565135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.4275565135
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2593420067
Short name T301
Test name
Test status
Simulation time 3297403200 ps
CPU time 48.03 seconds
Started Jul 17 05:04:48 PM PDT 24
Finished Jul 17 05:05:37 PM PDT 24
Peak memory 218848 kb
Host smart-7d802917-a6ff-45cf-b4b1-50a9f4854d13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593420067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2593420067
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1698919747
Short name T49
Test name
Test status
Simulation time 16065608739 ps
CPU time 31.07 seconds
Started Jul 17 05:03:20 PM PDT 24
Finished Jul 17 05:03:53 PM PDT 24
Peak memory 217436 kb
Host smart-251f90fc-04bd-4fab-9692-aacee112eaf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698919747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1698919747
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3342377764
Short name T30
Test name
Test status
Simulation time 170131462924 ps
CPU time 457.93 seconds
Started Jul 17 05:03:24 PM PDT 24
Finished Jul 17 05:11:03 PM PDT 24
Peak memory 233884 kb
Host smart-41b5f52d-93f5-4a01-9388-f5397a173d51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342377764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3342377764
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1181554110
Short name T238
Test name
Test status
Simulation time 386370695 ps
CPU time 19.31 seconds
Started Jul 17 05:03:16 PM PDT 24
Finished Jul 17 05:03:37 PM PDT 24
Peak memory 219252 kb
Host smart-5b8bd25e-4f3d-41ba-a17f-d22102298964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181554110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1181554110
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.286903721
Short name T127
Test name
Test status
Simulation time 222170745 ps
CPU time 10.93 seconds
Started Jul 17 05:03:18 PM PDT 24
Finished Jul 17 05:03:30 PM PDT 24
Peak memory 219216 kb
Host smart-2dcae2f6-62c3-4392-bc6f-b556dc6951d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=286903721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.286903721
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2987970847
Short name T276
Test name
Test status
Simulation time 8490949556 ps
CPU time 66.77 seconds
Started Jul 17 05:03:20 PM PDT 24
Finished Jul 17 05:04:29 PM PDT 24
Peak memory 216504 kb
Host smart-c8988e73-3d9d-4868-950b-cf1090aac80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987970847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2987970847
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.707543936
Short name T338
Test name
Test status
Simulation time 5411331812 ps
CPU time 40.21 seconds
Started Jul 17 05:03:16 PM PDT 24
Finished Jul 17 05:03:57 PM PDT 24
Peak memory 219360 kb
Host smart-7d3bb664-c06d-45dc-aab3-5432bfccacb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707543936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.707543936
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1823539884
Short name T151
Test name
Test status
Simulation time 689633971 ps
CPU time 8.23 seconds
Started Jul 17 05:03:20 PM PDT 24
Finished Jul 17 05:03:31 PM PDT 24
Peak memory 216976 kb
Host smart-c82dbb85-6207-434b-b620-a3348b1e4212
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823539884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1823539884
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1333561108
Short name T358
Test name
Test status
Simulation time 215656892512 ps
CPU time 578.23 seconds
Started Jul 17 05:03:21 PM PDT 24
Finished Jul 17 05:13:02 PM PDT 24
Peak memory 237960 kb
Host smart-75898538-6c83-404e-85e8-3e3c32093ef4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333561108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1333561108
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.238483116
Short name T258
Test name
Test status
Simulation time 719558797 ps
CPU time 19.38 seconds
Started Jul 17 05:03:17 PM PDT 24
Finished Jul 17 05:03:38 PM PDT 24
Peak memory 219300 kb
Host smart-6f602111-1276-430f-adf2-488289d818df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238483116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.238483116
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1395917995
Short name T128
Test name
Test status
Simulation time 18830752913 ps
CPU time 30.42 seconds
Started Jul 17 05:03:15 PM PDT 24
Finished Jul 17 05:03:47 PM PDT 24
Peak memory 211876 kb
Host smart-ed6efc72-0404-40ab-a0e2-3caa8036a49e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1395917995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1395917995
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1502337284
Short name T9
Test name
Test status
Simulation time 22225316759 ps
CPU time 44.48 seconds
Started Jul 17 05:03:22 PM PDT 24
Finished Jul 17 05:04:08 PM PDT 24
Peak memory 216892 kb
Host smart-1b4051e4-e989-426e-bc5c-e74ebbfa2ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502337284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1502337284
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.208226620
Short name T69
Test name
Test status
Simulation time 5889677728 ps
CPU time 62.65 seconds
Started Jul 17 05:03:19 PM PDT 24
Finished Jul 17 05:04:23 PM PDT 24
Peak memory 219288 kb
Host smart-037e9aad-0836-4f6e-a805-7ae7c26aa0a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208226620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.208226620
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.655225362
Short name T304
Test name
Test status
Simulation time 10510445390 ps
CPU time 24.42 seconds
Started Jul 17 05:03:17 PM PDT 24
Finished Jul 17 05:03:42 PM PDT 24
Peak memory 217432 kb
Host smart-7bf855e4-c219-44d3-875a-475443c212ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655225362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.655225362
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2566871175
Short name T292
Test name
Test status
Simulation time 24961059797 ps
CPU time 233.96 seconds
Started Jul 17 05:03:17 PM PDT 24
Finished Jul 17 05:07:12 PM PDT 24
Peak memory 238236 kb
Host smart-f6247f43-8a00-49e2-ab1e-8a898e96ff84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566871175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2566871175
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.36542574
Short name T180
Test name
Test status
Simulation time 675061457 ps
CPU time 19.2 seconds
Started Jul 17 05:03:20 PM PDT 24
Finished Jul 17 05:03:41 PM PDT 24
Peak memory 219264 kb
Host smart-b766d59e-6d43-454d-9fa7-c8bba34fe0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36542574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.36542574
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3997003162
Short name T330
Test name
Test status
Simulation time 4087611466 ps
CPU time 33.69 seconds
Started Jul 17 05:03:19 PM PDT 24
Finished Jul 17 05:03:54 PM PDT 24
Peak memory 211316 kb
Host smart-71cb0bb5-9220-4833-8406-772f88743c29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3997003162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3997003162
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3444017667
Short name T121
Test name
Test status
Simulation time 29964276257 ps
CPU time 76.44 seconds
Started Jul 17 05:03:22 PM PDT 24
Finished Jul 17 05:04:40 PM PDT 24
Peak memory 216852 kb
Host smart-d9700c1b-b0d5-4c75-931c-7adde05561e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444017667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3444017667
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.818695770
Short name T124
Test name
Test status
Simulation time 1109916115 ps
CPU time 44.09 seconds
Started Jul 17 05:03:17 PM PDT 24
Finished Jul 17 05:04:03 PM PDT 24
Peak memory 219252 kb
Host smart-fed490c2-98eb-4a8a-88c8-568836c95e26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818695770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.818695770
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.257426914
Short name T22
Test name
Test status
Simulation time 62262223786 ps
CPU time 2088.64 seconds
Started Jul 17 05:03:16 PM PDT 24
Finished Jul 17 05:38:06 PM PDT 24
Peak memory 232220 kb
Host smart-ea62b12c-2dbf-4271-b2a8-ee5c1efd5dbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257426914 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.257426914
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2313333167
Short name T302
Test name
Test status
Simulation time 1806666541 ps
CPU time 18.26 seconds
Started Jul 17 05:03:22 PM PDT 24
Finished Jul 17 05:03:42 PM PDT 24
Peak memory 217048 kb
Host smart-0a6e9ed6-b903-4edd-b90d-5a46a23fa882
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313333167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2313333167
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.191574310
Short name T289
Test name
Test status
Simulation time 46834506566 ps
CPU time 252.99 seconds
Started Jul 17 05:03:15 PM PDT 24
Finished Jul 17 05:07:29 PM PDT 24
Peak memory 233856 kb
Host smart-458ab640-5d63-41e8-a0be-1622ff97d201
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191574310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.191574310
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1644123766
Short name T32
Test name
Test status
Simulation time 689630736 ps
CPU time 20.06 seconds
Started Jul 17 05:03:19 PM PDT 24
Finished Jul 17 05:03:40 PM PDT 24
Peak memory 219244 kb
Host smart-1aac900b-1737-458e-8f8e-2bc9920566af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644123766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1644123766
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3453014815
Short name T225
Test name
Test status
Simulation time 9912715981 ps
CPU time 24.2 seconds
Started Jul 17 05:03:20 PM PDT 24
Finished Jul 17 05:03:47 PM PDT 24
Peak memory 217652 kb
Host smart-c6a1bbf6-4ade-41ec-8f14-912b2a43104d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3453014815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3453014815
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2484931144
Short name T219
Test name
Test status
Simulation time 1560927494 ps
CPU time 20.34 seconds
Started Jul 17 05:03:16 PM PDT 24
Finished Jul 17 05:03:38 PM PDT 24
Peak memory 216508 kb
Host smart-aaba0e2b-e0e2-4bd6-a6b2-4d4c67cab036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484931144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2484931144
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2637387991
Short name T295
Test name
Test status
Simulation time 10166507266 ps
CPU time 77.85 seconds
Started Jul 17 05:03:17 PM PDT 24
Finished Jul 17 05:04:36 PM PDT 24
Peak memory 219336 kb
Host smart-10140bbb-c9c1-4741-a890-0b2364f4fa1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637387991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2637387991
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3894781246
Short name T41
Test name
Test status
Simulation time 69078629188 ps
CPU time 2782.41 seconds
Started Jul 17 05:03:16 PM PDT 24
Finished Jul 17 05:49:39 PM PDT 24
Peak memory 252180 kb
Host smart-fc3fc330-27b3-4963-8cac-611b26b5c11d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894781246 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.3894781246
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.476698242
Short name T50
Test name
Test status
Simulation time 2587017385 ps
CPU time 12.45 seconds
Started Jul 17 05:03:21 PM PDT 24
Finished Jul 17 05:03:36 PM PDT 24
Peak memory 217072 kb
Host smart-8983229f-80d9-47c3-87a1-5eaca769e8b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476698242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.476698242
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1149646300
Short name T179
Test name
Test status
Simulation time 183560735843 ps
CPU time 556.26 seconds
Started Jul 17 05:03:22 PM PDT 24
Finished Jul 17 05:12:40 PM PDT 24
Peak memory 229504 kb
Host smart-eaad3f0e-35db-44bf-93af-3e18211d3de5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149646300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1149646300
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.236101420
Short name T187
Test name
Test status
Simulation time 6485209034 ps
CPU time 57.68 seconds
Started Jul 17 05:03:16 PM PDT 24
Finished Jul 17 05:04:15 PM PDT 24
Peak memory 219124 kb
Host smart-670ae8cf-8901-4d45-a243-fb39c0562b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236101420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.236101420
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3508921431
Short name T154
Test name
Test status
Simulation time 1032580202 ps
CPU time 10.42 seconds
Started Jul 17 05:03:21 PM PDT 24
Finished Jul 17 05:03:33 PM PDT 24
Peak memory 219228 kb
Host smart-bc3d67dd-8c0c-4982-a432-6424545a9391
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3508921431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3508921431
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1966265825
Short name T117
Test name
Test status
Simulation time 1381061694 ps
CPU time 20.28 seconds
Started Jul 17 05:03:21 PM PDT 24
Finished Jul 17 05:03:44 PM PDT 24
Peak memory 216740 kb
Host smart-c8271adf-5e5c-4110-8abd-0a1f0900c4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966265825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1966265825
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1531316064
Short name T332
Test name
Test status
Simulation time 14338509285 ps
CPU time 63.83 seconds
Started Jul 17 05:03:20 PM PDT 24
Finished Jul 17 05:04:25 PM PDT 24
Peak memory 218104 kb
Host smart-da2f5447-fb31-46e0-b032-769698de09b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531316064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1531316064
Directory /workspace/9.rom_ctrl_stress_all/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%