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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.19 96.89 91.85 97.68 100.00 98.28 97.30 98.37


Total test records in report: 460
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T293 /workspace/coverage/default/7.rom_ctrl_alert_test.3491058120 Jul 18 06:00:46 PM PDT 24 Jul 18 06:01:11 PM PDT 24 26837107819 ps
T294 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3074968773 Jul 18 06:01:07 PM PDT 24 Jul 18 06:10:25 PM PDT 24 107562319908 ps
T295 /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2415673291 Jul 18 06:01:04 PM PDT 24 Jul 18 06:55:10 PM PDT 24 78448444237 ps
T296 /workspace/coverage/default/42.rom_ctrl_smoke.552318425 Jul 18 06:01:18 PM PDT 24 Jul 18 06:02:40 PM PDT 24 6616284228 ps
T297 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3829259564 Jul 18 06:01:30 PM PDT 24 Jul 18 06:02:15 PM PDT 24 2623589383 ps
T298 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3066077837 Jul 18 06:01:04 PM PDT 24 Jul 18 06:01:56 PM PDT 24 7849187124 ps
T299 /workspace/coverage/default/0.rom_ctrl_alert_test.196108778 Jul 18 06:01:05 PM PDT 24 Jul 18 06:01:34 PM PDT 24 1475855474 ps
T300 /workspace/coverage/default/9.rom_ctrl_smoke.3801226021 Jul 18 06:00:56 PM PDT 24 Jul 18 06:02:09 PM PDT 24 21906557793 ps
T301 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.4209769756 Jul 18 06:00:49 PM PDT 24 Jul 18 06:01:24 PM PDT 24 15726286866 ps
T28 /workspace/coverage/default/2.rom_ctrl_sec_cm.2177810656 Jul 18 06:00:55 PM PDT 24 Jul 18 06:04:43 PM PDT 24 748558077 ps
T302 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.715084856 Jul 18 06:01:16 PM PDT 24 Jul 18 06:01:56 PM PDT 24 13747276097 ps
T303 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.4005208641 Jul 18 06:01:13 PM PDT 24 Jul 18 06:01:46 PM PDT 24 335967350 ps
T304 /workspace/coverage/default/32.rom_ctrl_smoke.3208387840 Jul 18 06:01:03 PM PDT 24 Jul 18 06:01:55 PM PDT 24 5165505661 ps
T305 /workspace/coverage/default/33.rom_ctrl_stress_all.1401205350 Jul 18 06:01:23 PM PDT 24 Jul 18 06:03:34 PM PDT 24 22359180225 ps
T306 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.277335496 Jul 18 06:01:11 PM PDT 24 Jul 18 06:02:25 PM PDT 24 7320886134 ps
T307 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3971324474 Jul 18 06:01:08 PM PDT 24 Jul 18 06:06:04 PM PDT 24 29128501786 ps
T308 /workspace/coverage/default/28.rom_ctrl_smoke.896248058 Jul 18 06:01:40 PM PDT 24 Jul 18 06:02:48 PM PDT 24 39699231279 ps
T309 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1661659579 Jul 18 06:01:07 PM PDT 24 Jul 18 06:01:31 PM PDT 24 763240494 ps
T310 /workspace/coverage/default/14.rom_ctrl_smoke.3435763182 Jul 18 06:01:05 PM PDT 24 Jul 18 06:01:37 PM PDT 24 448115860 ps
T311 /workspace/coverage/default/37.rom_ctrl_alert_test.59462342 Jul 18 06:01:13 PM PDT 24 Jul 18 06:01:51 PM PDT 24 54113027579 ps
T312 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3963617113 Jul 18 06:01:17 PM PDT 24 Jul 18 06:06:40 PM PDT 24 8654354316 ps
T313 /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2084522258 Jul 18 06:01:07 PM PDT 24 Jul 18 07:51:18 PM PDT 24 96516604175 ps
T314 /workspace/coverage/default/2.rom_ctrl_alert_test.2010087538 Jul 18 06:01:02 PM PDT 24 Jul 18 06:01:20 PM PDT 24 2060471067 ps
T315 /workspace/coverage/default/18.rom_ctrl_alert_test.3230619915 Jul 18 06:01:12 PM PDT 24 Jul 18 06:01:43 PM PDT 24 5280154154 ps
T316 /workspace/coverage/default/46.rom_ctrl_stress_all.3921816256 Jul 18 06:01:35 PM PDT 24 Jul 18 06:02:06 PM PDT 24 415702249 ps
T317 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2937640699 Jul 18 06:01:13 PM PDT 24 Jul 18 06:01:37 PM PDT 24 182993771 ps
T318 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1479003451 Jul 18 06:01:05 PM PDT 24 Jul 18 06:01:35 PM PDT 24 335565108 ps
T29 /workspace/coverage/default/3.rom_ctrl_sec_cm.957986104 Jul 18 06:01:04 PM PDT 24 Jul 18 06:03:31 PM PDT 24 3830099791 ps
T319 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2076375226 Jul 18 06:01:28 PM PDT 24 Jul 18 06:01:54 PM PDT 24 2827673597 ps
T320 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2171546902 Jul 18 06:01:10 PM PDT 24 Jul 18 06:01:56 PM PDT 24 2201856807 ps
T321 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2760198890 Jul 18 06:01:07 PM PDT 24 Jul 18 06:06:40 PM PDT 24 53767120610 ps
T322 /workspace/coverage/default/35.rom_ctrl_alert_test.410329506 Jul 18 06:01:13 PM PDT 24 Jul 18 06:01:46 PM PDT 24 7521632416 ps
T323 /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.4167719358 Jul 18 06:01:28 PM PDT 24 Jul 18 06:03:33 PM PDT 24 2532069445 ps
T324 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.561399567 Jul 18 06:01:29 PM PDT 24 Jul 18 06:02:30 PM PDT 24 5652691984 ps
T325 /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.167772331 Jul 18 06:01:08 PM PDT 24 Jul 18 06:16:35 PM PDT 24 85200665780 ps
T326 /workspace/coverage/default/25.rom_ctrl_smoke.1874613057 Jul 18 06:01:12 PM PDT 24 Jul 18 06:01:45 PM PDT 24 1443843419 ps
T327 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2120485409 Jul 18 06:01:09 PM PDT 24 Jul 18 06:02:00 PM PDT 24 4082327305 ps
T328 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.445406843 Jul 18 06:01:04 PM PDT 24 Jul 18 06:02:23 PM PDT 24 8297886898 ps
T329 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2753346068 Jul 18 06:01:05 PM PDT 24 Jul 18 06:01:38 PM PDT 24 3461350207 ps
T330 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3596631014 Jul 18 06:01:27 PM PDT 24 Jul 18 06:08:23 PM PDT 24 38717908840 ps
T331 /workspace/coverage/default/6.rom_ctrl_smoke.3195729198 Jul 18 06:00:45 PM PDT 24 Jul 18 06:01:54 PM PDT 24 30075043474 ps
T332 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3773143903 Jul 18 06:01:07 PM PDT 24 Jul 18 06:01:48 PM PDT 24 3413073386 ps
T333 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.253990399 Jul 18 06:01:19 PM PDT 24 Jul 18 06:23:46 PM PDT 24 127334978138 ps
T334 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.182249465 Jul 18 06:01:37 PM PDT 24 Jul 18 06:02:52 PM PDT 24 7603473946 ps
T335 /workspace/coverage/default/18.rom_ctrl_smoke.18736991 Jul 18 06:01:04 PM PDT 24 Jul 18 06:02:13 PM PDT 24 10954975412 ps
T336 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.63117393 Jul 18 06:01:12 PM PDT 24 Jul 18 06:02:20 PM PDT 24 6899663531 ps
T337 /workspace/coverage/default/36.rom_ctrl_smoke.3761619757 Jul 18 06:01:20 PM PDT 24 Jul 18 06:02:33 PM PDT 24 20471852950 ps
T338 /workspace/coverage/default/27.rom_ctrl_alert_test.3675483130 Jul 18 06:01:07 PM PDT 24 Jul 18 06:01:46 PM PDT 24 3228146486 ps
T339 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2664729210 Jul 18 06:01:35 PM PDT 24 Jul 18 06:02:13 PM PDT 24 1130278410 ps
T340 /workspace/coverage/default/30.rom_ctrl_stress_all.4146206700 Jul 18 06:01:09 PM PDT 24 Jul 18 06:02:54 PM PDT 24 4473688004 ps
T341 /workspace/coverage/default/35.rom_ctrl_stress_all.2796517654 Jul 18 06:01:39 PM PDT 24 Jul 18 06:02:29 PM PDT 24 7338810002 ps
T342 /workspace/coverage/default/29.rom_ctrl_stress_all.1954533231 Jul 18 06:01:19 PM PDT 24 Jul 18 06:03:49 PM PDT 24 68370309505 ps
T343 /workspace/coverage/default/16.rom_ctrl_alert_test.3017250839 Jul 18 06:01:08 PM PDT 24 Jul 18 06:01:52 PM PDT 24 7545895520 ps
T344 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1053049044 Jul 18 06:01:05 PM PDT 24 Jul 18 06:05:38 PM PDT 24 52098936400 ps
T345 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3978758115 Jul 18 06:00:53 PM PDT 24 Jul 18 06:08:10 PM PDT 24 39558695156 ps
T346 /workspace/coverage/default/9.rom_ctrl_alert_test.3268329079 Jul 18 06:01:09 PM PDT 24 Jul 18 06:01:41 PM PDT 24 1748231227 ps
T347 /workspace/coverage/default/41.rom_ctrl_stress_all.1845954174 Jul 18 06:01:28 PM PDT 24 Jul 18 06:03:11 PM PDT 24 8275943508 ps
T348 /workspace/coverage/default/20.rom_ctrl_stress_all.4022298285 Jul 18 06:01:07 PM PDT 24 Jul 18 06:03:39 PM PDT 24 13748108599 ps
T349 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.4207696395 Jul 18 06:00:53 PM PDT 24 Jul 18 06:06:51 PM PDT 24 23947223797 ps
T350 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.4185802797 Jul 18 06:01:11 PM PDT 24 Jul 18 06:02:20 PM PDT 24 6095744455 ps
T351 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2571745098 Jul 18 06:01:07 PM PDT 24 Jul 18 06:10:42 PM PDT 24 55771604770 ps
T352 /workspace/coverage/default/5.rom_ctrl_alert_test.907457376 Jul 18 06:01:01 PM PDT 24 Jul 18 06:01:31 PM PDT 24 10234873523 ps
T353 /workspace/coverage/default/13.rom_ctrl_stress_all.1132563023 Jul 18 06:01:00 PM PDT 24 Jul 18 06:02:08 PM PDT 24 8847694977 ps
T354 /workspace/coverage/default/26.rom_ctrl_stress_all.812172725 Jul 18 06:01:02 PM PDT 24 Jul 18 06:01:37 PM PDT 24 3424394900 ps
T355 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.51282660 Jul 18 06:01:35 PM PDT 24 Jul 18 06:02:14 PM PDT 24 12175642186 ps
T356 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.398128374 Jul 18 06:00:58 PM PDT 24 Jul 18 06:01:24 PM PDT 24 1376111426 ps
T62 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.575038446 Jul 18 04:44:10 PM PDT 24 Jul 18 04:44:30 PM PDT 24 6253955106 ps
T63 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1796297870 Jul 18 04:44:05 PM PDT 24 Jul 18 04:45:03 PM PDT 24 4130806544 ps
T64 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3807197782 Jul 18 04:44:25 PM PDT 24 Jul 18 04:44:46 PM PDT 24 1802154095 ps
T90 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1813378356 Jul 18 04:44:04 PM PDT 24 Jul 18 04:44:13 PM PDT 24 331888694 ps
T59 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2872412423 Jul 18 04:44:28 PM PDT 24 Jul 18 04:47:05 PM PDT 24 972751033 ps
T68 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1114055002 Jul 18 04:44:06 PM PDT 24 Jul 18 04:46:13 PM PDT 24 62983072985 ps
T69 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1339762786 Jul 18 04:44:27 PM PDT 24 Jul 18 04:44:49 PM PDT 24 15735321922 ps
T357 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3990508742 Jul 18 04:44:26 PM PDT 24 Jul 18 04:44:49 PM PDT 24 5131685247 ps
T358 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2457291478 Jul 18 04:44:13 PM PDT 24 Jul 18 04:44:45 PM PDT 24 16665829461 ps
T359 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4224972878 Jul 18 04:44:28 PM PDT 24 Jul 18 04:44:53 PM PDT 24 6754939238 ps
T70 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3462673492 Jul 18 04:43:45 PM PDT 24 Jul 18 04:44:14 PM PDT 24 13761515748 ps
T71 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2636204089 Jul 18 04:43:50 PM PDT 24 Jul 18 04:44:05 PM PDT 24 2613998818 ps
T72 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.976946099 Jul 18 04:44:03 PM PDT 24 Jul 18 04:45:32 PM PDT 24 8931129559 ps
T73 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3331038670 Jul 18 04:44:27 PM PDT 24 Jul 18 04:44:58 PM PDT 24 3868471452 ps
T94 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.4013953180 Jul 18 04:44:02 PM PDT 24 Jul 18 04:44:59 PM PDT 24 10300527332 ps
T360 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.266617988 Jul 18 04:44:03 PM PDT 24 Jul 18 04:44:22 PM PDT 24 10658449640 ps
T361 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.325171610 Jul 18 04:44:12 PM PDT 24 Jul 18 04:44:42 PM PDT 24 12905099037 ps
T74 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3010395968 Jul 18 04:44:08 PM PDT 24 Jul 18 04:44:18 PM PDT 24 1497803997 ps
T362 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1277689266 Jul 18 04:43:54 PM PDT 24 Jul 18 04:44:20 PM PDT 24 5811177165 ps
T60 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1509032542 Jul 18 04:44:03 PM PDT 24 Jul 18 04:46:49 PM PDT 24 3030050873 ps
T363 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1826348977 Jul 18 04:43:54 PM PDT 24 Jul 18 04:44:25 PM PDT 24 5537550649 ps
T75 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.297567303 Jul 18 04:43:52 PM PDT 24 Jul 18 04:44:21 PM PDT 24 3325804103 ps
T364 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1340746470 Jul 18 04:44:09 PM PDT 24 Jul 18 04:44:19 PM PDT 24 689507765 ps
T61 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.601554978 Jul 18 04:43:46 PM PDT 24 Jul 18 04:46:34 PM PDT 24 5462690748 ps
T91 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.807278716 Jul 18 04:44:04 PM PDT 24 Jul 18 04:45:35 PM PDT 24 5588028269 ps
T102 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.406275504 Jul 18 04:44:04 PM PDT 24 Jul 18 04:45:46 PM PDT 24 7673191798 ps
T81 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3324841809 Jul 18 04:44:28 PM PDT 24 Jul 18 04:46:02 PM PDT 24 9176441738 ps
T99 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1081996690 Jul 18 04:44:29 PM PDT 24 Jul 18 04:47:05 PM PDT 24 5316243670 ps
T92 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2592579377 Jul 18 04:44:04 PM PDT 24 Jul 18 04:44:14 PM PDT 24 169065153 ps
T365 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3834849773 Jul 18 04:43:49 PM PDT 24 Jul 18 04:44:08 PM PDT 24 6157236709 ps
T366 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4009825164 Jul 18 04:43:50 PM PDT 24 Jul 18 04:44:00 PM PDT 24 175972841 ps
T367 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1797918817 Jul 18 04:44:05 PM PDT 24 Jul 18 04:44:24 PM PDT 24 1512984139 ps
T82 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3847370845 Jul 18 04:43:46 PM PDT 24 Jul 18 04:44:15 PM PDT 24 66283746349 ps
T368 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2406770665 Jul 18 04:44:02 PM PDT 24 Jul 18 04:44:12 PM PDT 24 354999530 ps
T83 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3805962381 Jul 18 04:43:49 PM PDT 24 Jul 18 04:44:18 PM PDT 24 9417987519 ps
T104 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.915413384 Jul 18 04:43:44 PM PDT 24 Jul 18 04:45:05 PM PDT 24 493205302 ps
T369 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3771315044 Jul 18 04:44:08 PM PDT 24 Jul 18 04:44:19 PM PDT 24 341020413 ps
T370 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3595413788 Jul 18 04:43:42 PM PDT 24 Jul 18 04:44:01 PM PDT 24 17542130251 ps
T371 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3251030543 Jul 18 04:44:31 PM PDT 24 Jul 18 04:45:02 PM PDT 24 6456589390 ps
T103 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3272082906 Jul 18 04:44:04 PM PDT 24 Jul 18 04:47:01 PM PDT 24 4346045224 ps
T372 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.819335245 Jul 18 04:44:05 PM PDT 24 Jul 18 04:44:37 PM PDT 24 7934917158 ps
T84 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1204832150 Jul 18 04:43:52 PM PDT 24 Jul 18 04:45:53 PM PDT 24 15384228611 ps
T373 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1786629619 Jul 18 04:43:50 PM PDT 24 Jul 18 04:44:20 PM PDT 24 11720951064 ps
T374 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1076709571 Jul 18 04:44:09 PM PDT 24 Jul 18 04:44:35 PM PDT 24 3375281730 ps
T85 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.481072991 Jul 18 04:43:48 PM PDT 24 Jul 18 04:44:09 PM PDT 24 990864369 ps
T375 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.214970465 Jul 18 04:44:03 PM PDT 24 Jul 18 04:45:26 PM PDT 24 434308765 ps
T93 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.4106876897 Jul 18 04:44:04 PM PDT 24 Jul 18 04:44:35 PM PDT 24 15681963812 ps
T376 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.322180698 Jul 18 04:44:06 PM PDT 24 Jul 18 04:44:36 PM PDT 24 2871508954 ps
T377 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3182324784 Jul 18 04:43:50 PM PDT 24 Jul 18 04:44:14 PM PDT 24 3571147327 ps
T378 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3744051657 Jul 18 04:43:48 PM PDT 24 Jul 18 04:44:20 PM PDT 24 17225039189 ps
T379 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3086253868 Jul 18 04:44:07 PM PDT 24 Jul 18 04:44:29 PM PDT 24 1508865629 ps
T380 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3324535183 Jul 18 04:44:01 PM PDT 24 Jul 18 04:44:13 PM PDT 24 687977331 ps
T381 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1560033389 Jul 18 04:44:28 PM PDT 24 Jul 18 04:46:36 PM PDT 24 30853334933 ps
T106 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4280984070 Jul 18 04:44:29 PM PDT 24 Jul 18 04:47:07 PM PDT 24 3862852059 ps
T86 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.667549374 Jul 18 04:43:54 PM PDT 24 Jul 18 04:44:29 PM PDT 24 18473219090 ps
T382 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2343886704 Jul 18 04:44:08 PM PDT 24 Jul 18 04:45:30 PM PDT 24 1234206188 ps
T108 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.92872422 Jul 18 04:43:44 PM PDT 24 Jul 18 04:45:20 PM PDT 24 3434480562 ps
T383 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3129904794 Jul 18 04:44:03 PM PDT 24 Jul 18 04:45:54 PM PDT 24 32896320545 ps
T384 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.483727066 Jul 18 04:44:08 PM PDT 24 Jul 18 04:44:32 PM PDT 24 2646284922 ps
T385 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.570521481 Jul 18 04:43:47 PM PDT 24 Jul 18 04:47:16 PM PDT 24 102378121800 ps
T386 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3941386323 Jul 18 04:43:50 PM PDT 24 Jul 18 04:44:15 PM PDT 24 21965930097 ps
T387 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2616890647 Jul 18 04:43:51 PM PDT 24 Jul 18 04:44:15 PM PDT 24 10609265685 ps
T388 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4282698280 Jul 18 04:43:51 PM PDT 24 Jul 18 04:44:23 PM PDT 24 7964656018 ps
T389 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.813595135 Jul 18 04:43:46 PM PDT 24 Jul 18 04:44:04 PM PDT 24 4818870362 ps
T390 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2885354769 Jul 18 04:44:05 PM PDT 24 Jul 18 04:45:44 PM PDT 24 6487015927 ps
T391 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1332684511 Jul 18 04:43:45 PM PDT 24 Jul 18 04:44:15 PM PDT 24 14961295542 ps
T392 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.4022248861 Jul 18 04:44:10 PM PDT 24 Jul 18 04:44:25 PM PDT 24 5132743116 ps
T393 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2526771012 Jul 18 04:44:05 PM PDT 24 Jul 18 04:44:15 PM PDT 24 167467505 ps
T394 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1774864438 Jul 18 04:44:10 PM PDT 24 Jul 18 04:45:31 PM PDT 24 3634626475 ps
T395 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1436761146 Jul 18 04:44:02 PM PDT 24 Jul 18 04:44:28 PM PDT 24 2761003600 ps
T396 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2735592716 Jul 18 04:43:50 PM PDT 24 Jul 18 04:44:39 PM PDT 24 5371718540 ps
T397 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1536265128 Jul 18 04:43:49 PM PDT 24 Jul 18 04:44:15 PM PDT 24 1318609005 ps
T398 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2241230891 Jul 18 04:44:10 PM PDT 24 Jul 18 04:44:20 PM PDT 24 660357583 ps
T399 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2561580368 Jul 18 04:44:26 PM PDT 24 Jul 18 04:44:50 PM PDT 24 2312787955 ps
T400 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.866506121 Jul 18 04:43:51 PM PDT 24 Jul 18 04:44:19 PM PDT 24 16804553768 ps
T401 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2710170073 Jul 18 04:44:09 PM PDT 24 Jul 18 04:45:51 PM PDT 24 11160278936 ps
T402 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3592568352 Jul 18 04:44:29 PM PDT 24 Jul 18 04:45:04 PM PDT 24 8549593951 ps
T403 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3377963628 Jul 18 04:43:47 PM PDT 24 Jul 18 04:44:26 PM PDT 24 4192212649 ps
T87 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2217441296 Jul 18 04:44:29 PM PDT 24 Jul 18 04:44:54 PM PDT 24 18223280765 ps
T404 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2392511693 Jul 18 04:44:25 PM PDT 24 Jul 18 04:44:43 PM PDT 24 1370913199 ps
T405 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3847268053 Jul 18 04:43:51 PM PDT 24 Jul 18 04:44:28 PM PDT 24 15376977676 ps
T406 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3633378706 Jul 18 04:44:25 PM PDT 24 Jul 18 04:44:34 PM PDT 24 688099402 ps
T407 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1444829618 Jul 18 04:44:04 PM PDT 24 Jul 18 04:47:01 PM PDT 24 21887420266 ps
T100 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4115743743 Jul 18 04:44:29 PM PDT 24 Jul 18 04:47:07 PM PDT 24 350148415 ps
T408 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.41989158 Jul 18 04:44:02 PM PDT 24 Jul 18 04:44:11 PM PDT 24 176316465 ps
T409 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.678856950 Jul 18 04:44:30 PM PDT 24 Jul 18 04:45:02 PM PDT 24 17330738660 ps
T410 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3833308387 Jul 18 04:44:28 PM PDT 24 Jul 18 04:44:39 PM PDT 24 167599641 ps
T411 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1430409614 Jul 18 04:43:50 PM PDT 24 Jul 18 04:44:22 PM PDT 24 35186349897 ps
T107 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.606592401 Jul 18 04:44:06 PM PDT 24 Jul 18 04:47:04 PM PDT 24 22936871619 ps
T412 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1810631919 Jul 18 04:44:09 PM PDT 24 Jul 18 04:44:25 PM PDT 24 6308595949 ps
T413 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3001276075 Jul 18 04:44:26 PM PDT 24 Jul 18 04:46:15 PM PDT 24 18259033506 ps
T414 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3202913578 Jul 18 04:43:46 PM PDT 24 Jul 18 04:44:00 PM PDT 24 352586603 ps
T415 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3108830107 Jul 18 04:44:03 PM PDT 24 Jul 18 04:44:36 PM PDT 24 3497423192 ps
T101 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2030518234 Jul 18 04:43:54 PM PDT 24 Jul 18 04:46:27 PM PDT 24 848722865 ps
T416 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4060171603 Jul 18 04:44:07 PM PDT 24 Jul 18 04:44:21 PM PDT 24 759136306 ps
T417 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.159952916 Jul 18 04:43:51 PM PDT 24 Jul 18 04:44:19 PM PDT 24 5426387680 ps
T418 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1292860714 Jul 18 04:44:07 PM PDT 24 Jul 18 04:44:17 PM PDT 24 174571893 ps
T419 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.4134628347 Jul 18 04:44:07 PM PDT 24 Jul 18 04:44:17 PM PDT 24 174685380 ps
T420 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1632811459 Jul 18 04:44:03 PM PDT 24 Jul 18 04:44:13 PM PDT 24 1646753904 ps
T421 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3389108874 Jul 18 04:43:47 PM PDT 24 Jul 18 04:44:24 PM PDT 24 15676339710 ps
T422 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.4076981704 Jul 18 04:44:05 PM PDT 24 Jul 18 04:45:46 PM PDT 24 3998064511 ps
T423 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3438137626 Jul 18 04:44:04 PM PDT 24 Jul 18 04:44:27 PM PDT 24 8890876883 ps
T424 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4086825338 Jul 18 04:44:07 PM PDT 24 Jul 18 04:44:33 PM PDT 24 2789335431 ps
T425 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.567481380 Jul 18 04:43:47 PM PDT 24 Jul 18 04:44:20 PM PDT 24 7217075143 ps
T426 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2634432073 Jul 18 04:44:08 PM PDT 24 Jul 18 04:44:34 PM PDT 24 4786927629 ps
T427 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1428711948 Jul 18 04:43:44 PM PDT 24 Jul 18 04:44:00 PM PDT 24 2364164533 ps
T428 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2616661202 Jul 18 04:44:08 PM PDT 24 Jul 18 04:44:42 PM PDT 24 4178491560 ps
T429 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4196728050 Jul 18 04:44:06 PM PDT 24 Jul 18 04:44:24 PM PDT 24 614846322 ps
T430 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2065932578 Jul 18 04:44:13 PM PDT 24 Jul 18 04:44:22 PM PDT 24 345466975 ps
T431 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3644898579 Jul 18 04:44:03 PM PDT 24 Jul 18 04:44:28 PM PDT 24 2628507095 ps
T432 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3799502967 Jul 18 04:44:05 PM PDT 24 Jul 18 04:44:33 PM PDT 24 3127131499 ps
T89 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2977693714 Jul 18 04:43:48 PM PDT 24 Jul 18 04:44:55 PM PDT 24 8610915678 ps
T433 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.782293325 Jul 18 04:44:30 PM PDT 24 Jul 18 04:44:43 PM PDT 24 353904065 ps
T434 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1681047275 Jul 18 04:44:10 PM PDT 24 Jul 18 04:44:28 PM PDT 24 19016339006 ps
T435 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.336498694 Jul 18 04:43:43 PM PDT 24 Jul 18 04:44:13 PM PDT 24 15425589589 ps
T109 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3147250919 Jul 18 04:44:03 PM PDT 24 Jul 18 04:46:49 PM PDT 24 2495835161 ps
T436 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.4109915905 Jul 18 04:44:26 PM PDT 24 Jul 18 04:44:43 PM PDT 24 4129251496 ps
T437 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4205302515 Jul 18 04:44:08 PM PDT 24 Jul 18 04:44:30 PM PDT 24 21650865524 ps
T438 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1697040127 Jul 18 04:44:09 PM PDT 24 Jul 18 04:46:17 PM PDT 24 66937431452 ps
T439 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3297504930 Jul 18 04:43:54 PM PDT 24 Jul 18 04:44:04 PM PDT 24 169310080 ps
T440 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.71759032 Jul 18 04:44:28 PM PDT 24 Jul 18 04:44:59 PM PDT 24 22399891626 ps
T441 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1542564972 Jul 18 04:44:09 PM PDT 24 Jul 18 04:44:32 PM PDT 24 16304292419 ps
T88 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2047397634 Jul 18 04:44:25 PM PDT 24 Jul 18 04:46:28 PM PDT 24 61667029409 ps
T442 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2956210990 Jul 18 04:44:04 PM PDT 24 Jul 18 04:44:20 PM PDT 24 8145857933 ps
T443 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3339126343 Jul 18 04:44:26 PM PDT 24 Jul 18 04:46:05 PM PDT 24 5251327971 ps
T444 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.296396407 Jul 18 04:43:51 PM PDT 24 Jul 18 04:44:15 PM PDT 24 20910060172 ps
T445 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2291059244 Jul 18 04:43:45 PM PDT 24 Jul 18 04:43:55 PM PDT 24 687881105 ps
T446 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.785001148 Jul 18 04:43:50 PM PDT 24 Jul 18 04:44:22 PM PDT 24 5278899751 ps
T447 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.902054185 Jul 18 04:44:29 PM PDT 24 Jul 18 04:44:49 PM PDT 24 2026814815 ps
T448 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3392544770 Jul 18 04:43:52 PM PDT 24 Jul 18 04:44:12 PM PDT 24 1731558720 ps
T449 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1512319166 Jul 18 04:44:26 PM PDT 24 Jul 18 04:44:54 PM PDT 24 6192760826 ps
T450 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2404058576 Jul 18 04:44:29 PM PDT 24 Jul 18 04:44:54 PM PDT 24 1990374138 ps
T451 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2899980471 Jul 18 04:44:07 PM PDT 24 Jul 18 04:44:33 PM PDT 24 3184806612 ps
T452 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.624714046 Jul 18 04:44:07 PM PDT 24 Jul 18 04:44:33 PM PDT 24 14231170674 ps
T453 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4019103350 Jul 18 04:43:51 PM PDT 24 Jul 18 04:44:17 PM PDT 24 10942968137 ps
T454 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3224964861 Jul 18 04:44:25 PM PDT 24 Jul 18 04:44:34 PM PDT 24 174889252 ps
T455 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.679022099 Jul 18 04:44:11 PM PDT 24 Jul 18 04:44:38 PM PDT 24 3562900345 ps
T105 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3703355953 Jul 18 04:43:47 PM PDT 24 Jul 18 04:46:44 PM PDT 24 4534337617 ps
T456 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1504303854 Jul 18 04:43:59 PM PDT 24 Jul 18 04:44:08 PM PDT 24 661704065 ps
T110 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1434344514 Jul 18 04:44:08 PM PDT 24 Jul 18 04:46:58 PM PDT 24 6204345922 ps
T457 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3210342091 Jul 18 04:45:55 PM PDT 24 Jul 18 04:46:25 PM PDT 24 6512972169 ps
T458 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2587533585 Jul 18 04:44:30 PM PDT 24 Jul 18 04:45:36 PM PDT 24 17143252959 ps
T459 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.967123816 Jul 18 04:43:47 PM PDT 24 Jul 18 04:44:13 PM PDT 24 11173906093 ps
T460 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3631954131 Jul 18 04:44:07 PM PDT 24 Jul 18 04:44:33 PM PDT 24 2720246112 ps

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.4031458108
Short name T2
Test name
Test status
Simulation time 305694071770 ps
CPU time 812.36 seconds
Started Jul 18 06:00:43 PM PDT 24
Finished Jul 18 06:14:19 PM PDT 24
Peak memory 239904 kb
Host smart-7446da8b-5620-45c4-871f-16156c454a3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031458108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.4031458108
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.1196004414
Short name T12
Test name
Test status
Simulation time 87844230311 ps
CPU time 965.08 seconds
Started Jul 18 06:01:33 PM PDT 24
Finished Jul 18 06:17:51 PM PDT 24
Peak memory 236464 kb
Host smart-6bf484b7-8ef7-460e-8f95-50c006c61689
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196004414 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.1196004414
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.513393920
Short name T44
Test name
Test status
Simulation time 9287287739 ps
CPU time 173.49 seconds
Started Jul 18 06:01:35 PM PDT 24
Finished Jul 18 06:04:43 PM PDT 24
Peak memory 238064 kb
Host smart-a9d6c1d2-44ea-4498-ba2a-ecc8090eac7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513393920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.513393920
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2872412423
Short name T59
Test name
Test status
Simulation time 972751033 ps
CPU time 154.43 seconds
Started Jul 18 04:44:28 PM PDT 24
Finished Jul 18 04:47:05 PM PDT 24
Peak memory 213928 kb
Host smart-b02d43cb-3f71-4568-bfe0-02470fedc556
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872412423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2872412423
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.4165426081
Short name T16
Test name
Test status
Simulation time 4214077247 ps
CPU time 52.31 seconds
Started Jul 18 06:01:12 PM PDT 24
Finished Jul 18 06:02:18 PM PDT 24
Peak memory 216396 kb
Host smart-b2487cbd-bd73-42ce-bf5d-65b73abe0b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165426081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.4165426081
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2077062004
Short name T22
Test name
Test status
Simulation time 8619443621 ps
CPU time 234.33 seconds
Started Jul 18 06:00:59 PM PDT 24
Finished Jul 18 06:05:01 PM PDT 24
Peak memory 238384 kb
Host smart-3e1dede0-92bd-4987-907e-c9d2d3994f7f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077062004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2077062004
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1796297870
Short name T63
Test name
Test status
Simulation time 4130806544 ps
CPU time 56.65 seconds
Started Jul 18 04:44:05 PM PDT 24
Finished Jul 18 04:45:03 PM PDT 24
Peak memory 213916 kb
Host smart-3ff9ca99-ef74-4ee1-95e9-421c7f2b7ee6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796297870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1796297870
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.915413384
Short name T104
Test name
Test status
Simulation time 493205302 ps
CPU time 80.1 seconds
Started Jul 18 04:43:44 PM PDT 24
Finished Jul 18 04:45:05 PM PDT 24
Peak memory 213496 kb
Host smart-37dc002e-5b57-41d8-a779-cbc65c3555d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915413384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.915413384
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3036709642
Short name T123
Test name
Test status
Simulation time 174522090 ps
CPU time 8.54 seconds
Started Jul 18 06:00:50 PM PDT 24
Finished Jul 18 06:01:03 PM PDT 24
Peak memory 213288 kb
Host smart-2227ca6b-1171-4ab8-8b24-91e0c37a826e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036709642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3036709642
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2021386484
Short name T47
Test name
Test status
Simulation time 1321053388 ps
CPU time 19.19 seconds
Started Jul 18 06:00:54 PM PDT 24
Finished Jul 18 06:01:19 PM PDT 24
Peak memory 219356 kb
Host smart-39c4b60f-2f63-4cf8-8dab-7ebfdd8db589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021386484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2021386484
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2465934354
Short name T135
Test name
Test status
Simulation time 5493064921 ps
CPU time 51.67 seconds
Started Jul 18 06:01:03 PM PDT 24
Finished Jul 18 06:02:05 PM PDT 24
Peak memory 219400 kb
Host smart-2ef687cf-02de-4274-8806-4803d635362d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465934354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2465934354
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3240834203
Short name T15
Test name
Test status
Simulation time 109232627119 ps
CPU time 1039.78 seconds
Started Jul 18 06:00:58 PM PDT 24
Finished Jul 18 06:18:24 PM PDT 24
Peak memory 235896 kb
Host smart-eb8e1b55-abdb-4003-8c78-5b413e8ab044
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240834203 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.3240834203
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4115743743
Short name T100
Test name
Test status
Simulation time 350148415 ps
CPU time 156.31 seconds
Started Jul 18 04:44:29 PM PDT 24
Finished Jul 18 04:47:07 PM PDT 24
Peak memory 213808 kb
Host smart-2447ab8f-8761-4a47-a93c-80d1833acb65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115743743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.4115743743
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1434344514
Short name T110
Test name
Test status
Simulation time 6204345922 ps
CPU time 168.67 seconds
Started Jul 18 04:44:08 PM PDT 24
Finished Jul 18 04:46:58 PM PDT 24
Peak memory 215072 kb
Host smart-ae332d22-1250-435c-84c7-ad5ef0a9ef1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434344514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1434344514
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3272082906
Short name T103
Test name
Test status
Simulation time 4346045224 ps
CPU time 175.67 seconds
Started Jul 18 04:44:04 PM PDT 24
Finished Jul 18 04:47:01 PM PDT 24
Peak memory 214064 kb
Host smart-e7804bc7-991e-4cb0-a7d2-04429b620001
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272082906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3272082906
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.4271767496
Short name T124
Test name
Test status
Simulation time 4149289116 ps
CPU time 33.19 seconds
Started Jul 18 06:01:06 PM PDT 24
Finished Jul 18 06:01:52 PM PDT 24
Peak memory 219424 kb
Host smart-e8306c54-c154-43ac-aeff-143df93d19de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4271767496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.4271767496
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3462673492
Short name T70
Test name
Test status
Simulation time 13761515748 ps
CPU time 27.64 seconds
Started Jul 18 04:43:45 PM PDT 24
Finished Jul 18 04:44:14 PM PDT 24
Peak memory 212240 kb
Host smart-774bcc93-1b0b-479c-9943-40a34062c442
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462673492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3462673492
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2636204089
Short name T71
Test name
Test status
Simulation time 2613998818 ps
CPU time 12.01 seconds
Started Jul 18 04:43:50 PM PDT 24
Finished Jul 18 04:44:05 PM PDT 24
Peak memory 210676 kb
Host smart-83ab0921-3899-4b63-82f0-02e120e2c880
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636204089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2636204089
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.785001148
Short name T446
Test name
Test status
Simulation time 5278899751 ps
CPU time 30.2 seconds
Started Jul 18 04:43:50 PM PDT 24
Finished Jul 18 04:44:22 PM PDT 24
Peak memory 211584 kb
Host smart-5eaac959-d4f4-4ba1-ab8d-7d12d7b388d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785001148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.785001148
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.481072991
Short name T85
Test name
Test status
Simulation time 990864369 ps
CPU time 18.49 seconds
Started Jul 18 04:43:48 PM PDT 24
Finished Jul 18 04:44:09 PM PDT 24
Peak memory 211244 kb
Host smart-11670426-9440-4f60-80ca-b7213206bb0d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481072991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.481072991
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3595413788
Short name T370
Test name
Test status
Simulation time 17542130251 ps
CPU time 18.12 seconds
Started Jul 18 04:43:42 PM PDT 24
Finished Jul 18 04:44:01 PM PDT 24
Peak memory 216736 kb
Host smart-9c05077c-946a-4a00-93a3-942cf005e9e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595413788 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3595413788
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.667549374
Short name T86
Test name
Test status
Simulation time 18473219090 ps
CPU time 33.09 seconds
Started Jul 18 04:43:54 PM PDT 24
Finished Jul 18 04:44:29 PM PDT 24
Peak memory 211780 kb
Host smart-9b79e719-a34f-4394-b8e3-5ab308f34171
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667549374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.667549374
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3834849773
Short name T365
Test name
Test status
Simulation time 6157236709 ps
CPU time 17.05 seconds
Started Jul 18 04:43:49 PM PDT 24
Finished Jul 18 04:44:08 PM PDT 24
Peak memory 210672 kb
Host smart-b1c11fe2-ee17-43cf-93ba-3cc0c4b6ac80
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834849773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3834849773
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1786629619
Short name T373
Test name
Test status
Simulation time 11720951064 ps
CPU time 26.75 seconds
Started Jul 18 04:43:50 PM PDT 24
Finished Jul 18 04:44:20 PM PDT 24
Peak memory 210784 kb
Host smart-b765d767-a2fc-4cbc-a385-e2e553ff844a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786629619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1786629619
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2735592716
Short name T396
Test name
Test status
Simulation time 5371718540 ps
CPU time 46.95 seconds
Started Jul 18 04:43:50 PM PDT 24
Finished Jul 18 04:44:39 PM PDT 24
Peak memory 218796 kb
Host smart-ff3ecee1-e1e2-401f-8052-bbaa8eabd385
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735592716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2735592716
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3392544770
Short name T448
Test name
Test status
Simulation time 1731558720 ps
CPU time 17.88 seconds
Started Jul 18 04:43:52 PM PDT 24
Finished Jul 18 04:44:12 PM PDT 24
Peak memory 212112 kb
Host smart-1ec7c391-2b44-48b0-8ded-c845128f108d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392544770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3392544770
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.159952916
Short name T417
Test name
Test status
Simulation time 5426387680 ps
CPU time 25.22 seconds
Started Jul 18 04:43:51 PM PDT 24
Finished Jul 18 04:44:19 PM PDT 24
Peak memory 218764 kb
Host smart-0e0c4da7-2d4e-4b44-9140-356ed01b0572
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159952916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.159952916
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.813595135
Short name T389
Test name
Test status
Simulation time 4818870362 ps
CPU time 16.93 seconds
Started Jul 18 04:43:46 PM PDT 24
Finished Jul 18 04:44:04 PM PDT 24
Peak memory 211804 kb
Host smart-d915c3ae-bdb3-4254-b969-68ae4874c939
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813595135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.813595135
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3941386323
Short name T386
Test name
Test status
Simulation time 21965930097 ps
CPU time 23.14 seconds
Started Jul 18 04:43:50 PM PDT 24
Finished Jul 18 04:44:15 PM PDT 24
Peak memory 211856 kb
Host smart-e39cf535-2a3d-4a67-bca1-4b11748f8be9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941386323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3941386323
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1536265128
Short name T397
Test name
Test status
Simulation time 1318609005 ps
CPU time 23.48 seconds
Started Jul 18 04:43:49 PM PDT 24
Finished Jul 18 04:44:15 PM PDT 24
Peak memory 211328 kb
Host smart-ec36ee03-c426-4578-8d41-af67b80f5ead
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536265128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1536265128
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.336498694
Short name T435
Test name
Test status
Simulation time 15425589589 ps
CPU time 29.13 seconds
Started Jul 18 04:43:43 PM PDT 24
Finished Jul 18 04:44:13 PM PDT 24
Peak memory 216524 kb
Host smart-6a81ab04-e2c6-4ea3-b0f5-f52d79f3277c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336498694 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.336498694
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.866506121
Short name T400
Test name
Test status
Simulation time 16804553768 ps
CPU time 25.14 seconds
Started Jul 18 04:43:51 PM PDT 24
Finished Jul 18 04:44:19 PM PDT 24
Peak memory 212376 kb
Host smart-66833593-3e6b-4ef3-a7c0-0262e9bca091
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866506121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.866506121
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4009825164
Short name T366
Test name
Test status
Simulation time 175972841 ps
CPU time 7.96 seconds
Started Jul 18 04:43:50 PM PDT 24
Finished Jul 18 04:44:00 PM PDT 24
Peak memory 210312 kb
Host smart-6070fd63-6d20-410c-9616-47a8500d961a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009825164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.4009825164
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.296396407
Short name T444
Test name
Test status
Simulation time 20910060172 ps
CPU time 20.79 seconds
Started Jul 18 04:43:51 PM PDT 24
Finished Jul 18 04:44:15 PM PDT 24
Peak memory 210728 kb
Host smart-a46433e1-1914-4bfc-bdfb-456c9bfdc8bd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296396407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
296396407
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3202913578
Short name T414
Test name
Test status
Simulation time 352586603 ps
CPU time 12.65 seconds
Started Jul 18 04:43:46 PM PDT 24
Finished Jul 18 04:44:00 PM PDT 24
Peak memory 218676 kb
Host smart-15b0aab5-0c33-4ce9-99a8-fb6af0e9e704
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202913578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3202913578
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.601554978
Short name T61
Test name
Test status
Simulation time 5462690748 ps
CPU time 166.32 seconds
Started Jul 18 04:43:46 PM PDT 24
Finished Jul 18 04:46:34 PM PDT 24
Peak memory 213824 kb
Host smart-5afe11ef-0403-4d9c-85ba-a0b3c693d5f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601554978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.601554978
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.4022248861
Short name T392
Test name
Test status
Simulation time 5132743116 ps
CPU time 13.8 seconds
Started Jul 18 04:44:10 PM PDT 24
Finished Jul 18 04:44:25 PM PDT 24
Peak memory 213476 kb
Host smart-55d191e6-f90d-4d78-a394-4030075bcc4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022248861 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.4022248861
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2956210990
Short name T442
Test name
Test status
Simulation time 8145857933 ps
CPU time 14.28 seconds
Started Jul 18 04:44:04 PM PDT 24
Finished Jul 18 04:44:20 PM PDT 24
Peak memory 210816 kb
Host smart-be96bbc0-6ed7-4050-876b-6c5a57ee0f91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956210990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2956210990
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1444829618
Short name T407
Test name
Test status
Simulation time 21887420266 ps
CPU time 174.48 seconds
Started Jul 18 04:44:04 PM PDT 24
Finished Jul 18 04:47:01 PM PDT 24
Peak memory 215184 kb
Host smart-e8176db0-ef15-413d-95bc-b748aabc5761
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444829618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1444829618
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.41989158
Short name T408
Test name
Test status
Simulation time 176316465 ps
CPU time 8.28 seconds
Started Jul 18 04:44:02 PM PDT 24
Finished Jul 18 04:44:11 PM PDT 24
Peak memory 211388 kb
Host smart-7998dc8f-4e74-4366-8505-85d5af5cc38a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41989158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ct
rl_same_csr_outstanding.41989158
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1542564972
Short name T441
Test name
Test status
Simulation time 16304292419 ps
CPU time 21.45 seconds
Started Jul 18 04:44:09 PM PDT 24
Finished Jul 18 04:44:32 PM PDT 24
Peak memory 218492 kb
Host smart-16353e58-23c0-4237-aedb-570aff5bb176
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542564972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1542564972
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4205302515
Short name T437
Test name
Test status
Simulation time 21650865524 ps
CPU time 19.78 seconds
Started Jul 18 04:44:08 PM PDT 24
Finished Jul 18 04:44:30 PM PDT 24
Peak memory 216472 kb
Host smart-d16ab9a5-b9ef-41ac-8ee8-76d83c88b1f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205302515 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.4205302515
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4086825338
Short name T424
Test name
Test status
Simulation time 2789335431 ps
CPU time 23.63 seconds
Started Jul 18 04:44:07 PM PDT 24
Finished Jul 18 04:44:33 PM PDT 24
Peak memory 210452 kb
Host smart-d38fb1a9-64d7-4e30-9d7f-057f0a9e70e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086825338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.4086825338
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3129904794
Short name T383
Test name
Test status
Simulation time 32896320545 ps
CPU time 109.24 seconds
Started Jul 18 04:44:03 PM PDT 24
Finished Jul 18 04:45:54 PM PDT 24
Peak memory 214764 kb
Host smart-55fd28e1-43d5-4ba9-9c43-7c790e8a9277
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129904794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3129904794
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2899980471
Short name T451
Test name
Test status
Simulation time 3184806612 ps
CPU time 23.99 seconds
Started Jul 18 04:44:07 PM PDT 24
Finished Jul 18 04:44:33 PM PDT 24
Peak memory 211920 kb
Host smart-d66c4bdb-5470-4a02-88d5-185ab75f9280
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899980471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2899980471
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3086253868
Short name T379
Test name
Test status
Simulation time 1508865629 ps
CPU time 20.15 seconds
Started Jul 18 04:44:07 PM PDT 24
Finished Jul 18 04:44:29 PM PDT 24
Peak memory 217920 kb
Host smart-bafcf0e4-c2a4-426f-a92b-8e64066fbb84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086253868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3086253868
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.624714046
Short name T452
Test name
Test status
Simulation time 14231170674 ps
CPU time 23.69 seconds
Started Jul 18 04:44:07 PM PDT 24
Finished Jul 18 04:44:33 PM PDT 24
Peak memory 217784 kb
Host smart-47df1908-df4d-4338-9482-d01d5d70a7e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624714046 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.624714046
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3010395968
Short name T74
Test name
Test status
Simulation time 1497803997 ps
CPU time 8.04 seconds
Started Jul 18 04:44:08 PM PDT 24
Finished Jul 18 04:44:18 PM PDT 24
Peak memory 210724 kb
Host smart-f0d1b205-c8ed-4899-b2ad-fa4ae73e27a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010395968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3010395968
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.807278716
Short name T91
Test name
Test status
Simulation time 5588028269 ps
CPU time 90.06 seconds
Started Jul 18 04:44:04 PM PDT 24
Finished Jul 18 04:45:35 PM PDT 24
Peak memory 215160 kb
Host smart-7ea7faf2-62be-4fef-ad0c-58beb6e9c39c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807278716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.807278716
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2526771012
Short name T393
Test name
Test status
Simulation time 167467505 ps
CPU time 8.21 seconds
Started Jul 18 04:44:05 PM PDT 24
Finished Jul 18 04:44:15 PM PDT 24
Peak memory 210512 kb
Host smart-3ba5c5df-7d06-48be-92c4-682442b5d4da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526771012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2526771012
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2616661202
Short name T428
Test name
Test status
Simulation time 4178491560 ps
CPU time 32 seconds
Started Jul 18 04:44:08 PM PDT 24
Finished Jul 18 04:44:42 PM PDT 24
Peak memory 218316 kb
Host smart-ccef2c7b-3fc1-4174-94c7-ebd9e078056e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616661202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2616661202
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.606592401
Short name T107
Test name
Test status
Simulation time 22936871619 ps
CPU time 175.5 seconds
Started Jul 18 04:44:06 PM PDT 24
Finished Jul 18 04:47:04 PM PDT 24
Peak memory 213872 kb
Host smart-d65baa5b-250c-4798-b5c3-838d870cfa1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606592401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.606592401
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1810631919
Short name T412
Test name
Test status
Simulation time 6308595949 ps
CPU time 14.22 seconds
Started Jul 18 04:44:09 PM PDT 24
Finished Jul 18 04:44:25 PM PDT 24
Peak memory 217636 kb
Host smart-40d54d45-1459-48e0-a71c-b76a9b0808b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810631919 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1810631919
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1436761146
Short name T395
Test name
Test status
Simulation time 2761003600 ps
CPU time 24.96 seconds
Started Jul 18 04:44:02 PM PDT 24
Finished Jul 18 04:44:28 PM PDT 24
Peak memory 211540 kb
Host smart-ef140c75-5457-44a8-a12c-5896df0d853f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436761146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1436761146
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1114055002
Short name T68
Test name
Test status
Simulation time 62983072985 ps
CPU time 125.59 seconds
Started Jul 18 04:44:06 PM PDT 24
Finished Jul 18 04:46:13 PM PDT 24
Peak memory 213692 kb
Host smart-3f5ff2da-45e7-4d71-bcf7-0a115bf76012
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114055002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1114055002
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1681047275
Short name T434
Test name
Test status
Simulation time 19016339006 ps
CPU time 16.56 seconds
Started Jul 18 04:44:10 PM PDT 24
Finished Jul 18 04:44:28 PM PDT 24
Peak memory 211612 kb
Host smart-315469ea-6d1c-446e-b097-e3adab56b160
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681047275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1681047275
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3644898579
Short name T431
Test name
Test status
Simulation time 2628507095 ps
CPU time 24.47 seconds
Started Jul 18 04:44:03 PM PDT 24
Finished Jul 18 04:44:28 PM PDT 24
Peak memory 218140 kb
Host smart-309afa0a-2ca6-40de-901d-09d5fcb9d55b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644898579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3644898579
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.406275504
Short name T102
Test name
Test status
Simulation time 7673191798 ps
CPU time 99.4 seconds
Started Jul 18 04:44:04 PM PDT 24
Finished Jul 18 04:45:46 PM PDT 24
Peak memory 213752 kb
Host smart-0ac1974a-3feb-4e37-a1ff-014daa989fc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406275504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.406275504
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.71759032
Short name T440
Test name
Test status
Simulation time 22399891626 ps
CPU time 29.03 seconds
Started Jul 18 04:44:28 PM PDT 24
Finished Jul 18 04:44:59 PM PDT 24
Peak memory 215708 kb
Host smart-b8898853-bcc1-413a-9e0e-cd3232030118
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71759032 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.71759032
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1813378356
Short name T90
Test name
Test status
Simulation time 331888694 ps
CPU time 8.01 seconds
Started Jul 18 04:44:04 PM PDT 24
Finished Jul 18 04:44:13 PM PDT 24
Peak memory 210620 kb
Host smart-7a71707f-2f37-4342-ba7d-bbe3faa87477
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813378356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1813378356
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1774864438
Short name T394
Test name
Test status
Simulation time 3634626475 ps
CPU time 79.94 seconds
Started Jul 18 04:44:10 PM PDT 24
Finished Jul 18 04:45:31 PM PDT 24
Peak memory 214100 kb
Host smart-f79be002-a768-4b1a-a4dd-c477152429d2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774864438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1774864438
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4196728050
Short name T429
Test name
Test status
Simulation time 614846322 ps
CPU time 15.78 seconds
Started Jul 18 04:44:06 PM PDT 24
Finished Jul 18 04:44:24 PM PDT 24
Peak memory 212108 kb
Host smart-eedd9091-5a04-49e3-adcf-8738ad052e14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196728050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.4196728050
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.266617988
Short name T360
Test name
Test status
Simulation time 10658449640 ps
CPU time 18.33 seconds
Started Jul 18 04:44:03 PM PDT 24
Finished Jul 18 04:44:22 PM PDT 24
Peak memory 217328 kb
Host smart-6a0839f2-3254-46fd-a68d-49ccbf17df4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266617988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.266617988
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1509032542
Short name T60
Test name
Test status
Simulation time 3030050873 ps
CPU time 164.78 seconds
Started Jul 18 04:44:03 PM PDT 24
Finished Jul 18 04:46:49 PM PDT 24
Peak memory 214720 kb
Host smart-3428bfd6-cac8-4d09-88de-438cf6a04e9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509032542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1509032542
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.902054185
Short name T447
Test name
Test status
Simulation time 2026814815 ps
CPU time 18.32 seconds
Started Jul 18 04:44:29 PM PDT 24
Finished Jul 18 04:44:49 PM PDT 24
Peak memory 218764 kb
Host smart-09c43899-de7f-4602-ae98-7ecd0b239f97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902054185 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.902054185
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1512319166
Short name T449
Test name
Test status
Simulation time 6192760826 ps
CPU time 26.56 seconds
Started Jul 18 04:44:26 PM PDT 24
Finished Jul 18 04:44:54 PM PDT 24
Peak memory 211296 kb
Host smart-b33d2684-637e-4668-b234-99f673c19c94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512319166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1512319166
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3001276075
Short name T413
Test name
Test status
Simulation time 18259033506 ps
CPU time 106.63 seconds
Started Jul 18 04:44:26 PM PDT 24
Finished Jul 18 04:46:15 PM PDT 24
Peak memory 213896 kb
Host smart-d0c26e36-9cd2-45ec-8ad5-be7c0693a158
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001276075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3001276075
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.4109915905
Short name T436
Test name
Test status
Simulation time 4129251496 ps
CPU time 14.75 seconds
Started Jul 18 04:44:26 PM PDT 24
Finished Jul 18 04:44:43 PM PDT 24
Peak memory 210820 kb
Host smart-c8aed640-53fb-4aad-9ff5-79dead8e99ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109915905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.4109915905
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.678856950
Short name T409
Test name
Test status
Simulation time 17330738660 ps
CPU time 30.61 seconds
Started Jul 18 04:44:30 PM PDT 24
Finished Jul 18 04:45:02 PM PDT 24
Peak memory 217372 kb
Host smart-bec5e5c2-a323-431d-bdca-cad6e1d2969c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678856950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.678856950
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4280984070
Short name T106
Test name
Test status
Simulation time 3862852059 ps
CPU time 155.69 seconds
Started Jul 18 04:44:29 PM PDT 24
Finished Jul 18 04:47:07 PM PDT 24
Peak memory 214804 kb
Host smart-0f4f1c9a-ae07-43b2-9744-53405b7d0caf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280984070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.4280984070
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.782293325
Short name T433
Test name
Test status
Simulation time 353904065 ps
CPU time 11 seconds
Started Jul 18 04:44:30 PM PDT 24
Finished Jul 18 04:44:43 PM PDT 24
Peak memory 215652 kb
Host smart-cf7d812c-d1d1-4b36-ac85-16124bcc33bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782293325 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.782293325
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2217441296
Short name T87
Test name
Test status
Simulation time 18223280765 ps
CPU time 22.67 seconds
Started Jul 18 04:44:29 PM PDT 24
Finished Jul 18 04:44:54 PM PDT 24
Peak memory 211700 kb
Host smart-9136b4a0-8291-44b1-ac98-b094a7425b63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217441296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2217441296
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2047397634
Short name T88
Test name
Test status
Simulation time 61667029409 ps
CPU time 122.7 seconds
Started Jul 18 04:44:25 PM PDT 24
Finished Jul 18 04:46:28 PM PDT 24
Peak memory 213692 kb
Host smart-6e5df58e-0858-41c6-9fc1-cb15f5b018b6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047397634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2047397634
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3807197782
Short name T64
Test name
Test status
Simulation time 1802154095 ps
CPU time 19.73 seconds
Started Jul 18 04:44:25 PM PDT 24
Finished Jul 18 04:44:46 PM PDT 24
Peak memory 211796 kb
Host smart-8f6f1b35-f173-46be-a0e9-59b068d871a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807197782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3807197782
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2404058576
Short name T450
Test name
Test status
Simulation time 1990374138 ps
CPU time 23.15 seconds
Started Jul 18 04:44:29 PM PDT 24
Finished Jul 18 04:44:54 PM PDT 24
Peak memory 216100 kb
Host smart-0e871884-e13a-42ec-b886-ca255373c7b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404058576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2404058576
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1081996690
Short name T99
Test name
Test status
Simulation time 5316243670 ps
CPU time 153.69 seconds
Started Jul 18 04:44:29 PM PDT 24
Finished Jul 18 04:47:05 PM PDT 24
Peak memory 214040 kb
Host smart-342e36c4-2849-4076-8d87-11aa02f466b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081996690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1081996690
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3210342091
Short name T457
Test name
Test status
Simulation time 6512972169 ps
CPU time 27.57 seconds
Started Jul 18 04:45:55 PM PDT 24
Finished Jul 18 04:46:25 PM PDT 24
Peak memory 218884 kb
Host smart-3f9ae5c6-590d-48dc-b217-898b0aaa38c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210342091 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3210342091
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1339762786
Short name T69
Test name
Test status
Simulation time 15735321922 ps
CPU time 19.46 seconds
Started Jul 18 04:44:27 PM PDT 24
Finished Jul 18 04:44:49 PM PDT 24
Peak memory 212376 kb
Host smart-25d10c29-c4e8-4048-b2c1-857ede2398e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339762786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1339762786
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3324841809
Short name T81
Test name
Test status
Simulation time 9176441738 ps
CPU time 91.64 seconds
Started Jul 18 04:44:28 PM PDT 24
Finished Jul 18 04:46:02 PM PDT 24
Peak memory 214008 kb
Host smart-44cd3aa3-b7f1-45d6-8147-aee05a3aac79
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324841809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3324841809
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2392511693
Short name T404
Test name
Test status
Simulation time 1370913199 ps
CPU time 15.96 seconds
Started Jul 18 04:44:25 PM PDT 24
Finished Jul 18 04:44:43 PM PDT 24
Peak memory 211780 kb
Host smart-a71a1914-9382-418d-a1f5-d44c65ce4381
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392511693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2392511693
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3990508742
Short name T357
Test name
Test status
Simulation time 5131685247 ps
CPU time 20.36 seconds
Started Jul 18 04:44:26 PM PDT 24
Finished Jul 18 04:44:49 PM PDT 24
Peak memory 217488 kb
Host smart-a43e5ff3-e2e9-48a1-af8d-b54983fa841b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990508742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3990508742
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3224964861
Short name T454
Test name
Test status
Simulation time 174889252 ps
CPU time 8.19 seconds
Started Jul 18 04:44:25 PM PDT 24
Finished Jul 18 04:44:34 PM PDT 24
Peak memory 213352 kb
Host smart-fef44aee-f4f5-45f5-ae72-486ba1e38328
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224964861 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3224964861
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3331038670
Short name T73
Test name
Test status
Simulation time 3868471452 ps
CPU time 29.51 seconds
Started Jul 18 04:44:27 PM PDT 24
Finished Jul 18 04:44:58 PM PDT 24
Peak memory 211488 kb
Host smart-a34c28f2-07a7-4ee5-986e-cb5dde4c7ccc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331038670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3331038670
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1560033389
Short name T381
Test name
Test status
Simulation time 30853334933 ps
CPU time 125.07 seconds
Started Jul 18 04:44:28 PM PDT 24
Finished Jul 18 04:46:36 PM PDT 24
Peak memory 213704 kb
Host smart-c2e39813-81b6-4403-a6f6-849dd42496a0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560033389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1560033389
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3833308387
Short name T410
Test name
Test status
Simulation time 167599641 ps
CPU time 8.53 seconds
Started Jul 18 04:44:28 PM PDT 24
Finished Jul 18 04:44:39 PM PDT 24
Peak memory 211088 kb
Host smart-e725df75-4d55-4bba-8c54-29b7736e954a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833308387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3833308387
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4224972878
Short name T359
Test name
Test status
Simulation time 6754939238 ps
CPU time 22.73 seconds
Started Jul 18 04:44:28 PM PDT 24
Finished Jul 18 04:44:53 PM PDT 24
Peak memory 218636 kb
Host smart-e09599fc-97d8-47fb-a620-87e7fe5b6626
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224972878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.4224972878
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3339126343
Short name T443
Test name
Test status
Simulation time 5251327971 ps
CPU time 96.28 seconds
Started Jul 18 04:44:26 PM PDT 24
Finished Jul 18 04:46:05 PM PDT 24
Peak memory 218804 kb
Host smart-1e8d51ad-0a0a-40fd-b4a4-4e2c065e1369
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339126343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3339126343
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3592568352
Short name T402
Test name
Test status
Simulation time 8549593951 ps
CPU time 32.68 seconds
Started Jul 18 04:44:29 PM PDT 24
Finished Jul 18 04:45:04 PM PDT 24
Peak memory 218560 kb
Host smart-3d910b22-3fa2-4b93-af59-7228bef9f01c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592568352 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3592568352
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3633378706
Short name T406
Test name
Test status
Simulation time 688099402 ps
CPU time 8.18 seconds
Started Jul 18 04:44:25 PM PDT 24
Finished Jul 18 04:44:34 PM PDT 24
Peak memory 210760 kb
Host smart-f6c0ba75-0a1e-40e9-8aa8-d1fef2cf2488
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633378706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3633378706
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2587533585
Short name T458
Test name
Test status
Simulation time 17143252959 ps
CPU time 64.2 seconds
Started Jul 18 04:44:30 PM PDT 24
Finished Jul 18 04:45:36 PM PDT 24
Peak memory 213700 kb
Host smart-188f95e7-2801-40b9-a175-c7e488753d0e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587533585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2587533585
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2561580368
Short name T399
Test name
Test status
Simulation time 2312787955 ps
CPU time 21.86 seconds
Started Jul 18 04:44:26 PM PDT 24
Finished Jul 18 04:44:50 PM PDT 24
Peak memory 212120 kb
Host smart-761f5c2b-ceb6-41bd-89b5-cf52d630e1cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561580368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2561580368
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3251030543
Short name T371
Test name
Test status
Simulation time 6456589390 ps
CPU time 29.11 seconds
Started Jul 18 04:44:31 PM PDT 24
Finished Jul 18 04:45:02 PM PDT 24
Peak memory 217580 kb
Host smart-fab77f92-7f05-459d-8cb0-da9e0de0b9c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251030543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3251030543
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3847370845
Short name T82
Test name
Test status
Simulation time 66283746349 ps
CPU time 27.64 seconds
Started Jul 18 04:43:46 PM PDT 24
Finished Jul 18 04:44:15 PM PDT 24
Peak memory 212356 kb
Host smart-7cf8826b-5035-4bd6-b59a-c186ae70d427
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847370845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3847370845
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2291059244
Short name T445
Test name
Test status
Simulation time 687881105 ps
CPU time 8.13 seconds
Started Jul 18 04:43:45 PM PDT 24
Finished Jul 18 04:43:55 PM PDT 24
Peak memory 210480 kb
Host smart-76142e62-c942-4743-a41c-36395badc7fb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291059244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2291059244
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1430409614
Short name T411
Test name
Test status
Simulation time 35186349897 ps
CPU time 30.29 seconds
Started Jul 18 04:43:50 PM PDT 24
Finished Jul 18 04:44:22 PM PDT 24
Peak memory 212044 kb
Host smart-81d63079-fb93-41d1-8123-52651c0210b7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430409614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1430409614
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3182324784
Short name T377
Test name
Test status
Simulation time 3571147327 ps
CPU time 21.97 seconds
Started Jul 18 04:43:50 PM PDT 24
Finished Jul 18 04:44:14 PM PDT 24
Peak memory 218460 kb
Host smart-78d75992-5893-45bc-aefa-417713f3a4b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182324784 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3182324784
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3744051657
Short name T378
Test name
Test status
Simulation time 17225039189 ps
CPU time 29.41 seconds
Started Jul 18 04:43:48 PM PDT 24
Finished Jul 18 04:44:20 PM PDT 24
Peak memory 211480 kb
Host smart-4e43a2c6-5e62-43cb-926f-350afce5ac40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744051657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3744051657
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.567481380
Short name T425
Test name
Test status
Simulation time 7217075143 ps
CPU time 29.79 seconds
Started Jul 18 04:43:47 PM PDT 24
Finished Jul 18 04:44:20 PM PDT 24
Peak memory 210560 kb
Host smart-dffcf97a-205f-4c9c-9e9b-103727e44fc4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567481380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.567481380
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1428711948
Short name T427
Test name
Test status
Simulation time 2364164533 ps
CPU time 15.35 seconds
Started Jul 18 04:43:44 PM PDT 24
Finished Jul 18 04:44:00 PM PDT 24
Peak memory 210440 kb
Host smart-989404fe-b3c9-4f81-9d4a-3002861e6b23
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428711948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1428711948
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2977693714
Short name T89
Test name
Test status
Simulation time 8610915678 ps
CPU time 64.6 seconds
Started Jul 18 04:43:48 PM PDT 24
Finished Jul 18 04:44:55 PM PDT 24
Peak memory 214748 kb
Host smart-d2130f36-1381-426d-98d2-485762d0d0dd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977693714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2977693714
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1332684511
Short name T391
Test name
Test status
Simulation time 14961295542 ps
CPU time 27.75 seconds
Started Jul 18 04:43:45 PM PDT 24
Finished Jul 18 04:44:15 PM PDT 24
Peak memory 212336 kb
Host smart-b634bfac-066e-42bf-b7b3-a5b50ebc4d34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332684511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1332684511
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3377963628
Short name T403
Test name
Test status
Simulation time 4192212649 ps
CPU time 36.51 seconds
Started Jul 18 04:43:47 PM PDT 24
Finished Jul 18 04:44:26 PM PDT 24
Peak memory 217244 kb
Host smart-46026bc6-7c81-416c-8050-ac46ca913441
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377963628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3377963628
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3703355953
Short name T105
Test name
Test status
Simulation time 4534337617 ps
CPU time 175.66 seconds
Started Jul 18 04:43:47 PM PDT 24
Finished Jul 18 04:46:44 PM PDT 24
Peak memory 214120 kb
Host smart-d4fea915-a20a-447b-9802-0b442a767e20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703355953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3703355953
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.967123816
Short name T459
Test name
Test status
Simulation time 11173906093 ps
CPU time 24.68 seconds
Started Jul 18 04:43:47 PM PDT 24
Finished Jul 18 04:44:13 PM PDT 24
Peak memory 211600 kb
Host smart-228cd5f0-9fc8-4500-a135-0ddfbc2377a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967123816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.967123816
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3297504930
Short name T439
Test name
Test status
Simulation time 169310080 ps
CPU time 8.35 seconds
Started Jul 18 04:43:54 PM PDT 24
Finished Jul 18 04:44:04 PM PDT 24
Peak memory 210320 kb
Host smart-f9a03729-ca1e-4735-a68b-6ec036620aaa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297504930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3297504930
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3805962381
Short name T83
Test name
Test status
Simulation time 9417987519 ps
CPU time 26.45 seconds
Started Jul 18 04:43:49 PM PDT 24
Finished Jul 18 04:44:18 PM PDT 24
Peak memory 212076 kb
Host smart-3d17c98e-17c8-450d-a9e8-a3dacb2782e1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805962381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3805962381
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1826348977
Short name T363
Test name
Test status
Simulation time 5537550649 ps
CPU time 29.17 seconds
Started Jul 18 04:43:54 PM PDT 24
Finished Jul 18 04:44:25 PM PDT 24
Peak memory 216196 kb
Host smart-c5011385-b746-4e5a-b215-7d0825f9344b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826348977 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1826348977
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4282698280
Short name T388
Test name
Test status
Simulation time 7964656018 ps
CPU time 29.38 seconds
Started Jul 18 04:43:51 PM PDT 24
Finished Jul 18 04:44:23 PM PDT 24
Peak memory 211904 kb
Host smart-663818d7-9e96-4e0d-97a6-0bfa3fcc4212
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282698280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.4282698280
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2616890647
Short name T387
Test name
Test status
Simulation time 10609265685 ps
CPU time 22.04 seconds
Started Jul 18 04:43:51 PM PDT 24
Finished Jul 18 04:44:15 PM PDT 24
Peak memory 210760 kb
Host smart-c9f190d6-d633-4e63-bb96-103b1d2595c4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616890647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2616890647
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1277689266
Short name T362
Test name
Test status
Simulation time 5811177165 ps
CPU time 24.9 seconds
Started Jul 18 04:43:54 PM PDT 24
Finished Jul 18 04:44:20 PM PDT 24
Peak memory 210324 kb
Host smart-a664cb7b-a504-49e4-859b-ba0f07dc8488
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277689266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1277689266
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.570521481
Short name T385
Test name
Test status
Simulation time 102378121800 ps
CPU time 206.4 seconds
Started Jul 18 04:43:47 PM PDT 24
Finished Jul 18 04:47:16 PM PDT 24
Peak memory 215004 kb
Host smart-98b0fedb-6484-40f9-af24-40b5d9a8b959
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570521481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.570521481
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.297567303
Short name T75
Test name
Test status
Simulation time 3325804103 ps
CPU time 26.6 seconds
Started Jul 18 04:43:52 PM PDT 24
Finished Jul 18 04:44:21 PM PDT 24
Peak memory 212168 kb
Host smart-6df40a85-e8ca-4cd3-90b5-379b5f2e7997
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297567303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.297567303
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3847268053
Short name T405
Test name
Test status
Simulation time 15376977676 ps
CPU time 34.23 seconds
Started Jul 18 04:43:51 PM PDT 24
Finished Jul 18 04:44:28 PM PDT 24
Peak memory 217504 kb
Host smart-c6bb8ef6-289c-4183-8040-1234833da763
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847268053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3847268053
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.92872422
Short name T108
Test name
Test status
Simulation time 3434480562 ps
CPU time 95.4 seconds
Started Jul 18 04:43:44 PM PDT 24
Finished Jul 18 04:45:20 PM PDT 24
Peak memory 213292 kb
Host smart-ee4c22ee-bc24-4cad-815b-429aa4fb8245
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92872422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_intg
_err.92872422
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3799502967
Short name T432
Test name
Test status
Simulation time 3127131499 ps
CPU time 25.97 seconds
Started Jul 18 04:44:05 PM PDT 24
Finished Jul 18 04:44:33 PM PDT 24
Peak memory 211028 kb
Host smart-1c244b61-a872-42aa-8ed1-128d93cff383
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799502967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3799502967
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1340746470
Short name T364
Test name
Test status
Simulation time 689507765 ps
CPU time 8.53 seconds
Started Jul 18 04:44:09 PM PDT 24
Finished Jul 18 04:44:19 PM PDT 24
Peak memory 210780 kb
Host smart-a9a701a8-985d-4d59-9743-323221114a4e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340746470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1340746470
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4060171603
Short name T416
Test name
Test status
Simulation time 759136306 ps
CPU time 11.54 seconds
Started Jul 18 04:44:07 PM PDT 24
Finished Jul 18 04:44:21 PM PDT 24
Peak memory 210508 kb
Host smart-36e6c32c-1ec2-4b2b-85e9-b95f3e51f279
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060171603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.4060171603
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.819335245
Short name T372
Test name
Test status
Simulation time 7934917158 ps
CPU time 30.34 seconds
Started Jul 18 04:44:05 PM PDT 24
Finished Jul 18 04:44:37 PM PDT 24
Peak memory 217784 kb
Host smart-623b59bc-664e-47d2-ba1f-f85aaedfb58b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819335245 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.819335245
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.679022099
Short name T455
Test name
Test status
Simulation time 3562900345 ps
CPU time 26.61 seconds
Started Jul 18 04:44:11 PM PDT 24
Finished Jul 18 04:44:38 PM PDT 24
Peak memory 211020 kb
Host smart-afe9fd3d-5c15-4cd8-8112-3bc36f6d2a77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679022099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.679022099
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1797918817
Short name T367
Test name
Test status
Simulation time 1512984139 ps
CPU time 17.62 seconds
Started Jul 18 04:44:05 PM PDT 24
Finished Jul 18 04:44:24 PM PDT 24
Peak memory 210328 kb
Host smart-5bcc2683-3d1b-4252-9cbc-e53a6c9cc7aa
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797918817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1797918817
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4019103350
Short name T453
Test name
Test status
Simulation time 10942968137 ps
CPU time 23.52 seconds
Started Jul 18 04:43:51 PM PDT 24
Finished Jul 18 04:44:17 PM PDT 24
Peak memory 210704 kb
Host smart-e25d7ce9-04b4-4dff-bea9-5604796b647b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019103350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.4019103350
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1204832150
Short name T84
Test name
Test status
Simulation time 15384228611 ps
CPU time 118.81 seconds
Started Jul 18 04:43:52 PM PDT 24
Finished Jul 18 04:45:53 PM PDT 24
Peak memory 214120 kb
Host smart-b0b101ea-2874-4d19-b531-cc6f6e45caad
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204832150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1204832150
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2592579377
Short name T92
Test name
Test status
Simulation time 169065153 ps
CPU time 8.55 seconds
Started Jul 18 04:44:04 PM PDT 24
Finished Jul 18 04:44:14 PM PDT 24
Peak memory 211268 kb
Host smart-7d89130b-3613-4221-8061-1d8c8d6424a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592579377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2592579377
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3389108874
Short name T421
Test name
Test status
Simulation time 15676339710 ps
CPU time 35.02 seconds
Started Jul 18 04:43:47 PM PDT 24
Finished Jul 18 04:44:24 PM PDT 24
Peak memory 217588 kb
Host smart-f11049f3-5365-4928-9026-a0e817a2b59e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389108874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3389108874
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2030518234
Short name T101
Test name
Test status
Simulation time 848722865 ps
CPU time 151.2 seconds
Started Jul 18 04:43:54 PM PDT 24
Finished Jul 18 04:46:27 PM PDT 24
Peak memory 218668 kb
Host smart-bff83789-80a2-4bbd-aa78-2e83d4372b99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030518234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2030518234
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2457291478
Short name T358
Test name
Test status
Simulation time 16665829461 ps
CPU time 31.19 seconds
Started Jul 18 04:44:13 PM PDT 24
Finished Jul 18 04:44:45 PM PDT 24
Peak memory 214948 kb
Host smart-305d599d-abe1-4f2b-86f5-4e03dd5c648f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457291478 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2457291478
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.4134628347
Short name T419
Test name
Test status
Simulation time 174685380 ps
CPU time 8.17 seconds
Started Jul 18 04:44:07 PM PDT 24
Finished Jul 18 04:44:17 PM PDT 24
Peak memory 210504 kb
Host smart-37b4b8d9-aa5c-4fd9-9efc-195222cd3cd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134628347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.4134628347
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.976946099
Short name T72
Test name
Test status
Simulation time 8931129559 ps
CPU time 87.36 seconds
Started Jul 18 04:44:03 PM PDT 24
Finished Jul 18 04:45:32 PM PDT 24
Peak memory 215344 kb
Host smart-55e3a52f-4551-4ada-b1b1-1622d03134ff
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976946099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.976946099
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1504303854
Short name T456
Test name
Test status
Simulation time 661704065 ps
CPU time 8.25 seconds
Started Jul 18 04:43:59 PM PDT 24
Finished Jul 18 04:44:08 PM PDT 24
Peak memory 210880 kb
Host smart-de3aad67-af14-436e-8323-42079312982d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504303854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1504303854
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.322180698
Short name T376
Test name
Test status
Simulation time 2871508954 ps
CPU time 28.2 seconds
Started Jul 18 04:44:06 PM PDT 24
Finished Jul 18 04:44:36 PM PDT 24
Peak memory 218112 kb
Host smart-7d632b31-5f49-49a6-a06d-72bc1d6ca5e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322180698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.322180698
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.214970465
Short name T375
Test name
Test status
Simulation time 434308765 ps
CPU time 82.25 seconds
Started Jul 18 04:44:03 PM PDT 24
Finished Jul 18 04:45:26 PM PDT 24
Peak memory 212320 kb
Host smart-c6d0685e-ef9f-4f08-a5ce-c42d868c8fe7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214970465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.214970465
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.575038446
Short name T62
Test name
Test status
Simulation time 6253955106 ps
CPU time 18.36 seconds
Started Jul 18 04:44:10 PM PDT 24
Finished Jul 18 04:44:30 PM PDT 24
Peak memory 217440 kb
Host smart-5b48c61e-ec13-4a6d-a8ab-cd2ff5fab4a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575038446 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.575038446
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3438137626
Short name T423
Test name
Test status
Simulation time 8890876883 ps
CPU time 21 seconds
Started Jul 18 04:44:04 PM PDT 24
Finished Jul 18 04:44:27 PM PDT 24
Peak memory 212140 kb
Host smart-d259f3fe-0dba-446a-84d6-dd41f3f6230e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438137626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3438137626
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2710170073
Short name T401
Test name
Test status
Simulation time 11160278936 ps
CPU time 100.57 seconds
Started Jul 18 04:44:09 PM PDT 24
Finished Jul 18 04:45:51 PM PDT 24
Peak memory 213768 kb
Host smart-a8235dba-16ed-43b9-b879-5fc6685b716d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710170073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2710170073
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2241230891
Short name T398
Test name
Test status
Simulation time 660357583 ps
CPU time 8.41 seconds
Started Jul 18 04:44:10 PM PDT 24
Finished Jul 18 04:44:20 PM PDT 24
Peak memory 210692 kb
Host smart-ef9cc61c-730f-4f13-8af9-7fa5f08d4627
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241230891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2241230891
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2634432073
Short name T426
Test name
Test status
Simulation time 4786927629 ps
CPU time 23.82 seconds
Started Jul 18 04:44:08 PM PDT 24
Finished Jul 18 04:44:34 PM PDT 24
Peak memory 217376 kb
Host smart-dcacacf0-3e5b-400f-b618-57208ed908ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634432073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2634432073
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2343886704
Short name T382
Test name
Test status
Simulation time 1234206188 ps
CPU time 79.98 seconds
Started Jul 18 04:44:08 PM PDT 24
Finished Jul 18 04:45:30 PM PDT 24
Peak memory 213516 kb
Host smart-83860fb1-a541-4ade-8047-ebf023e3b841
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343886704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2343886704
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3631954131
Short name T460
Test name
Test status
Simulation time 2720246112 ps
CPU time 24.15 seconds
Started Jul 18 04:44:07 PM PDT 24
Finished Jul 18 04:44:33 PM PDT 24
Peak memory 217152 kb
Host smart-03285457-da8b-4030-b792-9fb2d86fe7a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631954131 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3631954131
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1632811459
Short name T420
Test name
Test status
Simulation time 1646753904 ps
CPU time 8.21 seconds
Started Jul 18 04:44:03 PM PDT 24
Finished Jul 18 04:44:13 PM PDT 24
Peak memory 210396 kb
Host smart-4fe03ec9-b486-4e7d-a859-00420b58a8c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632811459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1632811459
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.4106876897
Short name T93
Test name
Test status
Simulation time 15681963812 ps
CPU time 29.05 seconds
Started Jul 18 04:44:04 PM PDT 24
Finished Jul 18 04:44:35 PM PDT 24
Peak memory 212548 kb
Host smart-d7c4e6a3-3e32-4188-8444-fb98cd905a9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106876897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.4106876897
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3324535183
Short name T380
Test name
Test status
Simulation time 687977331 ps
CPU time 11.51 seconds
Started Jul 18 04:44:01 PM PDT 24
Finished Jul 18 04:44:13 PM PDT 24
Peak memory 216876 kb
Host smart-c7fe3049-3510-4a33-af09-e6a45025bdca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324535183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3324535183
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3147250919
Short name T109
Test name
Test status
Simulation time 2495835161 ps
CPU time 164.33 seconds
Started Jul 18 04:44:03 PM PDT 24
Finished Jul 18 04:46:49 PM PDT 24
Peak memory 213600 kb
Host smart-45998d69-7965-445e-9258-9cc5eeca8509
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147250919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3147250919
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3771315044
Short name T369
Test name
Test status
Simulation time 341020413 ps
CPU time 8.52 seconds
Started Jul 18 04:44:08 PM PDT 24
Finished Jul 18 04:44:19 PM PDT 24
Peak memory 218668 kb
Host smart-5bede200-5b8a-4ab3-a8c2-26f408dc6e9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771315044 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3771315044
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1076709571
Short name T374
Test name
Test status
Simulation time 3375281730 ps
CPU time 24.83 seconds
Started Jul 18 04:44:09 PM PDT 24
Finished Jul 18 04:44:35 PM PDT 24
Peak memory 211476 kb
Host smart-5395f85f-2d53-483d-adb5-10ed2a21ba03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076709571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1076709571
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1697040127
Short name T438
Test name
Test status
Simulation time 66937431452 ps
CPU time 126.67 seconds
Started Jul 18 04:44:09 PM PDT 24
Finished Jul 18 04:46:17 PM PDT 24
Peak memory 214012 kb
Host smart-9629668b-62cc-4bf5-a049-3db898cd6e4d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697040127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1697040127
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2065932578
Short name T430
Test name
Test status
Simulation time 345466975 ps
CPU time 8.24 seconds
Started Jul 18 04:44:13 PM PDT 24
Finished Jul 18 04:44:22 PM PDT 24
Peak memory 210920 kb
Host smart-718120b8-d3ee-4017-8cd3-249b4eefa996
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065932578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2065932578
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3108830107
Short name T415
Test name
Test status
Simulation time 3497423192 ps
CPU time 31.4 seconds
Started Jul 18 04:44:03 PM PDT 24
Finished Jul 18 04:44:36 PM PDT 24
Peak memory 216908 kb
Host smart-621f4010-44f4-4a68-b970-cb3cf47c646c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108830107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3108830107
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2885354769
Short name T390
Test name
Test status
Simulation time 6487015927 ps
CPU time 96.83 seconds
Started Jul 18 04:44:05 PM PDT 24
Finished Jul 18 04:45:44 PM PDT 24
Peak memory 213356 kb
Host smart-88fb58f4-f8ef-4db6-bf1e-87362d0be513
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885354769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2885354769
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2406770665
Short name T368
Test name
Test status
Simulation time 354999530 ps
CPU time 9.35 seconds
Started Jul 18 04:44:02 PM PDT 24
Finished Jul 18 04:44:12 PM PDT 24
Peak memory 216204 kb
Host smart-da934fe4-58f3-40a0-8cca-b4e084cee437
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406770665 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2406770665
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.483727066
Short name T384
Test name
Test status
Simulation time 2646284922 ps
CPU time 21.94 seconds
Started Jul 18 04:44:08 PM PDT 24
Finished Jul 18 04:44:32 PM PDT 24
Peak memory 211536 kb
Host smart-eea6ca08-db95-4970-a9d5-7bcecacf4925
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483727066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.483727066
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.4013953180
Short name T94
Test name
Test status
Simulation time 10300527332 ps
CPU time 56.4 seconds
Started Jul 18 04:44:02 PM PDT 24
Finished Jul 18 04:44:59 PM PDT 24
Peak memory 214868 kb
Host smart-a9f28b90-488e-4a0d-8d50-b0a925eae102
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013953180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.4013953180
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1292860714
Short name T418
Test name
Test status
Simulation time 174571893 ps
CPU time 8.51 seconds
Started Jul 18 04:44:07 PM PDT 24
Finished Jul 18 04:44:17 PM PDT 24
Peak memory 210720 kb
Host smart-920b51b5-81a5-4134-b0a9-73a0b9a87f80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292860714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1292860714
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.325171610
Short name T361
Test name
Test status
Simulation time 12905099037 ps
CPU time 29.59 seconds
Started Jul 18 04:44:12 PM PDT 24
Finished Jul 18 04:44:42 PM PDT 24
Peak memory 217200 kb
Host smart-41c298ac-896c-4990-bbb5-4f053a842d98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325171610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.325171610
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.4076981704
Short name T422
Test name
Test status
Simulation time 3998064511 ps
CPU time 99.71 seconds
Started Jul 18 04:44:05 PM PDT 24
Finished Jul 18 04:45:46 PM PDT 24
Peak memory 213324 kb
Host smart-091fcf97-a945-45c4-9c25-d80cf0c2786a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076981704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.4076981704
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.196108778
Short name T299
Test name
Test status
Simulation time 1475855474 ps
CPU time 17.77 seconds
Started Jul 18 06:01:05 PM PDT 24
Finished Jul 18 06:01:34 PM PDT 24
Peak memory 217180 kb
Host smart-0c630e42-cd20-4d79-ac4a-c82a4eeefb7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196108778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.196108778
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.4207696395
Short name T349
Test name
Test status
Simulation time 23947223797 ps
CPU time 352.12 seconds
Started Jul 18 06:00:53 PM PDT 24
Finished Jul 18 06:06:51 PM PDT 24
Peak memory 240168 kb
Host smart-810fb048-b8f6-4f74-b81f-1d8180882b02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207696395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.4207696395
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.4109467420
Short name T283
Test name
Test status
Simulation time 402785397 ps
CPU time 10.38 seconds
Started Jul 18 06:00:53 PM PDT 24
Finished Jul 18 06:01:08 PM PDT 24
Peak memory 219364 kb
Host smart-6170f7fc-3457-4164-a10d-3d2be5ccebd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4109467420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.4109467420
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3584469516
Short name T206
Test name
Test status
Simulation time 34179035982 ps
CPU time 66.23 seconds
Started Jul 18 06:01:03 PM PDT 24
Finished Jul 18 06:02:19 PM PDT 24
Peak memory 215960 kb
Host smart-9170f51b-b6ac-40a6-a292-63ba223b757f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584469516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3584469516
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2997752915
Short name T248
Test name
Test status
Simulation time 6308032431 ps
CPU time 54.08 seconds
Started Jul 18 06:01:05 PM PDT 24
Finished Jul 18 06:02:11 PM PDT 24
Peak memory 217116 kb
Host smart-536cfc7b-f085-45ec-a567-37fddff292e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997752915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2997752915
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2494897602
Short name T169
Test name
Test status
Simulation time 167711359 ps
CPU time 8.81 seconds
Started Jul 18 06:00:51 PM PDT 24
Finished Jul 18 06:01:04 PM PDT 24
Peak memory 217264 kb
Host smart-11bbd996-969a-47a0-8cd9-b7a0b4278f09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494897602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2494897602
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1697588486
Short name T156
Test name
Test status
Simulation time 36990573230 ps
CPU time 465.58 seconds
Started Jul 18 06:00:55 PM PDT 24
Finished Jul 18 06:08:47 PM PDT 24
Peak memory 233836 kb
Host smart-4876da81-8923-4c4d-9f32-539b39c507f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697588486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1697588486
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.697931697
Short name T263
Test name
Test status
Simulation time 5082814941 ps
CPU time 50.14 seconds
Started Jul 18 06:00:55 PM PDT 24
Finished Jul 18 06:01:52 PM PDT 24
Peak memory 219432 kb
Host smart-c74f1607-0433-49f6-a020-e4016062152e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697931697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.697931697
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1028050810
Short name T281
Test name
Test status
Simulation time 4952309566 ps
CPU time 24.84 seconds
Started Jul 18 06:01:04 PM PDT 24
Finished Jul 18 06:01:39 PM PDT 24
Peak memory 219428 kb
Host smart-2e46f65c-d078-4006-b8c8-8a99fb56f54b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1028050810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1028050810
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3882052517
Short name T23
Test name
Test status
Simulation time 1422266869 ps
CPU time 221.62 seconds
Started Jul 18 06:01:06 PM PDT 24
Finished Jul 18 06:05:00 PM PDT 24
Peak memory 238076 kb
Host smart-5851a80d-7cd1-4f03-ae52-db9d11d255ee
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882052517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3882052517
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3075145766
Short name T234
Test name
Test status
Simulation time 9205214616 ps
CPU time 68.21 seconds
Started Jul 18 06:01:04 PM PDT 24
Finished Jul 18 06:02:23 PM PDT 24
Peak memory 217172 kb
Host smart-50c30cf7-3173-4c4a-89d9-9152b0931d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075145766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3075145766
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3750234353
Short name T19
Test name
Test status
Simulation time 9373531693 ps
CPU time 32.49 seconds
Started Jul 18 06:00:51 PM PDT 24
Finished Jul 18 06:01:28 PM PDT 24
Peak memory 217928 kb
Host smart-4208c5f3-22eb-4926-a819-a3bcbe9e32e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750234353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3750234353
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.741152536
Short name T252
Test name
Test status
Simulation time 205883357542 ps
CPU time 594.87 seconds
Started Jul 18 06:01:02 PM PDT 24
Finished Jul 18 06:11:06 PM PDT 24
Peak memory 236312 kb
Host smart-a0aff6f7-02e4-415f-ac37-661115f0a7d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741152536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.741152536
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3522315
Short name T215
Test name
Test status
Simulation time 18524457880 ps
CPU time 23.24 seconds
Started Jul 18 06:00:57 PM PDT 24
Finished Jul 18 06:01:27 PM PDT 24
Peak memory 217756 kb
Host smart-a88be75d-b801-48ff-ae8c-6882af731e21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3522315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3522315
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2496557149
Short name T9
Test name
Test status
Simulation time 3548679828 ps
CPU time 48.09 seconds
Started Jul 18 06:00:57 PM PDT 24
Finished Jul 18 06:01:52 PM PDT 24
Peak memory 219412 kb
Host smart-6a4c3ded-d66e-4e39-9349-e612b43590f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496557149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2496557149
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2282627259
Short name T270
Test name
Test status
Simulation time 425775323 ps
CPU time 11.74 seconds
Started Jul 18 06:01:19 PM PDT 24
Finished Jul 18 06:01:41 PM PDT 24
Peak memory 213312 kb
Host smart-956cc9ac-04f4-4bc0-8712-3323d0081958
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282627259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2282627259
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3978758115
Short name T345
Test name
Test status
Simulation time 39558695156 ps
CPU time 432.05 seconds
Started Jul 18 06:00:53 PM PDT 24
Finished Jul 18 06:08:10 PM PDT 24
Peak memory 216936 kb
Host smart-9b893b29-0d35-4009-bd03-d7584d36e9bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978758115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3978758115
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.148322336
Short name T223
Test name
Test status
Simulation time 19729181924 ps
CPU time 49.61 seconds
Started Jul 18 06:01:07 PM PDT 24
Finished Jul 18 06:02:10 PM PDT 24
Peak memory 219540 kb
Host smart-28993ed7-e184-46d8-8c26-5a5a2825329d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148322336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.148322336
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.454251131
Short name T220
Test name
Test status
Simulation time 11217939442 ps
CPU time 23.98 seconds
Started Jul 18 06:01:00 PM PDT 24
Finished Jul 18 06:01:31 PM PDT 24
Peak memory 217956 kb
Host smart-fddce057-62d3-45e7-8e32-99d7473cf352
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=454251131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.454251131
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2123164776
Short name T260
Test name
Test status
Simulation time 4596033664 ps
CPU time 57.4 seconds
Started Jul 18 06:01:14 PM PDT 24
Finished Jul 18 06:02:25 PM PDT 24
Peak memory 215648 kb
Host smart-4f3c0203-66ac-42c6-9061-5e4abe0cc06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123164776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2123164776
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3383203057
Short name T285
Test name
Test status
Simulation time 4481101383 ps
CPU time 52.17 seconds
Started Jul 18 06:01:00 PM PDT 24
Finished Jul 18 06:02:01 PM PDT 24
Peak memory 219420 kb
Host smart-041e04b9-b7b1-40c7-9984-6496d7fc3689
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383203057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3383203057
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.3700674243
Short name T55
Test name
Test status
Simulation time 116791181834 ps
CPU time 2135.12 seconds
Started Jul 18 06:01:07 PM PDT 24
Finished Jul 18 06:36:56 PM PDT 24
Peak memory 244060 kb
Host smart-31de3b3e-2c99-4277-b30a-2b741a7f8dcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700674243 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.3700674243
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2823934555
Short name T154
Test name
Test status
Simulation time 1027243553 ps
CPU time 11.71 seconds
Started Jul 18 06:01:02 PM PDT 24
Finished Jul 18 06:01:22 PM PDT 24
Peak memory 217112 kb
Host smart-7406d4da-f6f5-4c5f-90d1-68fe9e3f2a56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823934555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2823934555
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1747095379
Short name T11
Test name
Test status
Simulation time 79840828765 ps
CPU time 207.77 seconds
Started Jul 18 06:01:04 PM PDT 24
Finished Jul 18 06:04:43 PM PDT 24
Peak memory 229348 kb
Host smart-53cca88d-1faf-436a-9905-f1fc20a74221
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747095379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1747095379
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.445406843
Short name T328
Test name
Test status
Simulation time 8297886898 ps
CPU time 68.28 seconds
Started Jul 18 06:01:04 PM PDT 24
Finished Jul 18 06:02:23 PM PDT 24
Peak memory 219304 kb
Host smart-e9b315b4-bdef-4f74-9be0-712814c1a9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445406843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.445406843
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1661659579
Short name T309
Test name
Test status
Simulation time 763240494 ps
CPU time 10.65 seconds
Started Jul 18 06:01:07 PM PDT 24
Finished Jul 18 06:01:31 PM PDT 24
Peak memory 219344 kb
Host smart-e6d31d70-3fd7-418a-8caa-054c7adc2f0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1661659579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1661659579
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3705731004
Short name T289
Test name
Test status
Simulation time 4883074680 ps
CPU time 25.22 seconds
Started Jul 18 06:00:58 PM PDT 24
Finished Jul 18 06:01:29 PM PDT 24
Peak memory 216728 kb
Host smart-24aebf3a-05ff-47e3-9917-6cfe5cadfe8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705731004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3705731004
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2861377369
Short name T238
Test name
Test status
Simulation time 8892086053 ps
CPU time 84.43 seconds
Started Jul 18 06:00:54 PM PDT 24
Finished Jul 18 06:02:25 PM PDT 24
Peak memory 219404 kb
Host smart-def15b83-5abd-418d-a281-a359c51cded9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861377369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2861377369
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2940696541
Short name T240
Test name
Test status
Simulation time 971786204 ps
CPU time 8.46 seconds
Started Jul 18 06:00:58 PM PDT 24
Finished Jul 18 06:01:14 PM PDT 24
Peak memory 213292 kb
Host smart-bed8ebad-43c2-4cc2-854c-b80794c45383
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940696541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2940696541
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3377459121
Short name T43
Test name
Test status
Simulation time 141862201114 ps
CPU time 696.59 seconds
Started Jul 18 06:01:13 PM PDT 24
Finished Jul 18 06:13:03 PM PDT 24
Peak memory 217848 kb
Host smart-60c83f8c-8742-4745-89f6-92f785d740e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377459121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3377459121
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.427772432
Short name T129
Test name
Test status
Simulation time 7473630189 ps
CPU time 52.02 seconds
Started Jul 18 06:01:00 PM PDT 24
Finished Jul 18 06:02:00 PM PDT 24
Peak memory 219424 kb
Host smart-a4663f8a-8e9e-4ee7-9014-1f97024551a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427772432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.427772432
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1449868534
Short name T152
Test name
Test status
Simulation time 2193256451 ps
CPU time 33.55 seconds
Started Jul 18 06:01:00 PM PDT 24
Finished Jul 18 06:01:41 PM PDT 24
Peak memory 216528 kb
Host smart-3fb263a0-5c8e-4a05-97a0-a230d9853e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449868534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1449868534
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1132563023
Short name T353
Test name
Test status
Simulation time 8847694977 ps
CPU time 59.53 seconds
Started Jul 18 06:01:00 PM PDT 24
Finished Jul 18 06:02:08 PM PDT 24
Peak memory 219444 kb
Host smart-52fdfcf8-da38-4f73-b05a-6469e181cae0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132563023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1132563023
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.1984840755
Short name T18
Test name
Test status
Simulation time 51594806004 ps
CPU time 2004.1 seconds
Started Jul 18 06:01:10 PM PDT 24
Finished Jul 18 06:34:47 PM PDT 24
Peak memory 237900 kb
Host smart-503ccd02-e7f9-47de-b282-448927525e5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984840755 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.1984840755
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3210630686
Short name T33
Test name
Test status
Simulation time 3172158951 ps
CPU time 26.63 seconds
Started Jul 18 06:01:00 PM PDT 24
Finished Jul 18 06:01:35 PM PDT 24
Peak memory 217232 kb
Host smart-d6fb53d0-8bc7-4af5-96cf-793398236004
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210630686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3210630686
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.131267729
Short name T21
Test name
Test status
Simulation time 73418576100 ps
CPU time 601.8 seconds
Started Jul 18 06:01:04 PM PDT 24
Finished Jul 18 06:11:18 PM PDT 24
Peak memory 228704 kb
Host smart-42b50e0f-2445-4dad-a10c-b857da3b5735
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131267729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.131267729
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1487359601
Short name T278
Test name
Test status
Simulation time 17172680761 ps
CPU time 66.18 seconds
Started Jul 18 06:01:07 PM PDT 24
Finished Jul 18 06:02:32 PM PDT 24
Peak memory 219400 kb
Host smart-5483830e-e1c2-4508-ae91-e447ec729027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487359601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1487359601
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3019691632
Short name T35
Test name
Test status
Simulation time 3956348390 ps
CPU time 21.99 seconds
Started Jul 18 06:01:07 PM PDT 24
Finished Jul 18 06:01:42 PM PDT 24
Peak memory 211988 kb
Host smart-912216e7-d4cc-4f98-b76d-45794dbb2370
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3019691632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3019691632
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3435763182
Short name T310
Test name
Test status
Simulation time 448115860 ps
CPU time 19.68 seconds
Started Jul 18 06:01:05 PM PDT 24
Finished Jul 18 06:01:37 PM PDT 24
Peak memory 216224 kb
Host smart-aaf71be4-9618-403c-8347-d923bff2718c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435763182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3435763182
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2455182687
Short name T251
Test name
Test status
Simulation time 1283688115 ps
CPU time 28.59 seconds
Started Jul 18 06:01:03 PM PDT 24
Finished Jul 18 06:01:41 PM PDT 24
Peak memory 219212 kb
Host smart-52dab74f-d42d-4824-be4a-3606fb0b312d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455182687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2455182687
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.4193342421
Short name T229
Test name
Test status
Simulation time 918214318 ps
CPU time 14.37 seconds
Started Jul 18 06:01:06 PM PDT 24
Finished Jul 18 06:01:32 PM PDT 24
Peak memory 217236 kb
Host smart-cddad6b1-79e2-4876-981a-09c9b239c6c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193342421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.4193342421
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.323646922
Short name T254
Test name
Test status
Simulation time 45492331923 ps
CPU time 712.22 seconds
Started Jul 18 06:01:00 PM PDT 24
Finished Jul 18 06:13:00 PM PDT 24
Peak memory 233416 kb
Host smart-2604b8e6-c3a2-4973-a852-27b3b4983e93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323646922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.323646922
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1479003451
Short name T318
Test name
Test status
Simulation time 335565108 ps
CPU time 19.18 seconds
Started Jul 18 06:01:05 PM PDT 24
Finished Jul 18 06:01:35 PM PDT 24
Peak memory 219360 kb
Host smart-fc03c3ab-05af-4354-af46-d0c41082628d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479003451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1479003451
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.939562250
Short name T4
Test name
Test status
Simulation time 371100757 ps
CPU time 10.79 seconds
Started Jul 18 06:01:02 PM PDT 24
Finished Jul 18 06:01:22 PM PDT 24
Peak memory 219340 kb
Host smart-400b4382-b778-4f30-b948-b0d6465597db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=939562250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.939562250
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.682505829
Short name T196
Test name
Test status
Simulation time 27256910027 ps
CPU time 65.89 seconds
Started Jul 18 06:01:08 PM PDT 24
Finished Jul 18 06:02:27 PM PDT 24
Peak memory 216292 kb
Host smart-49bc0c2c-c0a7-44d1-aad4-7329b87ce436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682505829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.682505829
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.157408250
Short name T179
Test name
Test status
Simulation time 12125311625 ps
CPU time 87.07 seconds
Started Jul 18 06:01:00 PM PDT 24
Finished Jul 18 06:02:35 PM PDT 24
Peak memory 227628 kb
Host smart-40e04c9a-6c10-44cd-a75a-f91b33932d28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157408250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.157408250
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3017250839
Short name T343
Test name
Test status
Simulation time 7545895520 ps
CPU time 30.26 seconds
Started Jul 18 06:01:08 PM PDT 24
Finished Jul 18 06:01:52 PM PDT 24
Peak memory 213340 kb
Host smart-d94118a0-2e6d-4cec-b2b4-47b47c3ceca8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017250839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3017250839
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2571745098
Short name T351
Test name
Test status
Simulation time 55771604770 ps
CPU time 561.05 seconds
Started Jul 18 06:01:07 PM PDT 24
Finished Jul 18 06:10:42 PM PDT 24
Peak memory 226212 kb
Host smart-1317e44a-664a-4992-b77a-aff9ed3dca11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571745098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2571745098
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.398128374
Short name T356
Test name
Test status
Simulation time 1376111426 ps
CPU time 19.33 seconds
Started Jul 18 06:00:58 PM PDT 24
Finished Jul 18 06:01:24 PM PDT 24
Peak memory 219296 kb
Host smart-67bc90a6-963f-4379-b401-d352d86cf30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398128374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.398128374
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2120485409
Short name T327
Test name
Test status
Simulation time 4082327305 ps
CPU time 32.5 seconds
Started Jul 18 06:01:09 PM PDT 24
Finished Jul 18 06:02:00 PM PDT 24
Peak memory 219612 kb
Host smart-54bf3c8f-a8f2-4b2d-b180-ccfcd0818286
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2120485409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2120485409
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3478550506
Short name T198
Test name
Test status
Simulation time 22789327166 ps
CPU time 61.66 seconds
Started Jul 18 06:01:00 PM PDT 24
Finished Jul 18 06:02:17 PM PDT 24
Peak memory 216652 kb
Host smart-b4d7848e-5a96-4c44-becb-e2f355ee4d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478550506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3478550506
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3987063665
Short name T221
Test name
Test status
Simulation time 19727893529 ps
CPU time 50.04 seconds
Started Jul 18 06:01:04 PM PDT 24
Finished Jul 18 06:02:04 PM PDT 24
Peak memory 215648 kb
Host smart-4769d102-0917-4e40-a01d-444a47b2b14e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987063665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3987063665
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2415673291
Short name T295
Test name
Test status
Simulation time 78448444237 ps
CPU time 3235.48 seconds
Started Jul 18 06:01:04 PM PDT 24
Finished Jul 18 06:55:10 PM PDT 24
Peak memory 252280 kb
Host smart-d0e00f36-4ff8-4e9a-bed8-0ce91d1bb589
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415673291 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.2415673291
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1029510841
Short name T139
Test name
Test status
Simulation time 174235102 ps
CPU time 8.15 seconds
Started Jul 18 06:00:58 PM PDT 24
Finished Jul 18 06:01:14 PM PDT 24
Peak memory 217232 kb
Host smart-9efe7790-d313-4e6b-8258-0a0d77f2c0a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029510841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1029510841
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3850969958
Short name T46
Test name
Test status
Simulation time 66079487408 ps
CPU time 419.02 seconds
Started Jul 18 06:00:58 PM PDT 24
Finished Jul 18 06:08:03 PM PDT 24
Peak memory 236340 kb
Host smart-a20c1b82-32ca-45df-ab60-bfaa91f919aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850969958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3850969958
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1716978186
Short name T205
Test name
Test status
Simulation time 161363194384 ps
CPU time 69.87 seconds
Started Jul 18 06:00:54 PM PDT 24
Finished Jul 18 06:02:10 PM PDT 24
Peak memory 219420 kb
Host smart-1f16d709-42ab-4f47-91f1-6cb5789407b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716978186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1716978186
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2383875569
Short name T151
Test name
Test status
Simulation time 3914222294 ps
CPU time 15.47 seconds
Started Jul 18 06:01:01 PM PDT 24
Finished Jul 18 06:01:25 PM PDT 24
Peak memory 219392 kb
Host smart-7e227f89-b4ef-4aa1-9a36-67f9842e05df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2383875569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2383875569
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.36972955
Short name T76
Test name
Test status
Simulation time 14022685083 ps
CPU time 39.98 seconds
Started Jul 18 06:01:02 PM PDT 24
Finished Jul 18 06:01:52 PM PDT 24
Peak memory 217356 kb
Host smart-22edaec2-3828-41a5-a6ec-58e7cde790ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36972955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.36972955
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3199792064
Short name T37
Test name
Test status
Simulation time 11438867423 ps
CPU time 89.51 seconds
Started Jul 18 06:01:02 PM PDT 24
Finished Jul 18 06:02:41 PM PDT 24
Peak memory 219728 kb
Host smart-3ce2c860-f998-4804-8a25-4210e5d55d78
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199792064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3199792064
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.701142986
Short name T14
Test name
Test status
Simulation time 499820588138 ps
CPU time 5406.5 seconds
Started Jul 18 06:01:04 PM PDT 24
Finished Jul 18 07:31:21 PM PDT 24
Peak memory 255772 kb
Host smart-e153288a-cb51-49e3-a833-9d87d6b4655a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701142986 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.701142986
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3230619915
Short name T315
Test name
Test status
Simulation time 5280154154 ps
CPU time 18.04 seconds
Started Jul 18 06:01:12 PM PDT 24
Finished Jul 18 06:01:43 PM PDT 24
Peak memory 213336 kb
Host smart-d320d9ae-4886-4902-ad5c-4043e1e48423
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230619915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3230619915
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2760198890
Short name T321
Test name
Test status
Simulation time 53767120610 ps
CPU time 319.57 seconds
Started Jul 18 06:01:07 PM PDT 24
Finished Jul 18 06:06:40 PM PDT 24
Peak memory 240252 kb
Host smart-d8ff0501-5696-4f05-8bac-2f894f78ac5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760198890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2760198890
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3066077837
Short name T298
Test name
Test status
Simulation time 7849187124 ps
CPU time 41.06 seconds
Started Jul 18 06:01:04 PM PDT 24
Finished Jul 18 06:01:56 PM PDT 24
Peak memory 219400 kb
Host smart-9afd734e-dfcd-4bd9-bfa6-062640a0ab9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066077837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3066077837
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.135435134
Short name T32
Test name
Test status
Simulation time 3726879869 ps
CPU time 31.62 seconds
Started Jul 18 06:00:59 PM PDT 24
Finished Jul 18 06:01:38 PM PDT 24
Peak memory 211480 kb
Host smart-5f9e02a6-d5a9-45e0-8676-577b052aaba4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=135435134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.135435134
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.18736991
Short name T335
Test name
Test status
Simulation time 10954975412 ps
CPU time 58.93 seconds
Started Jul 18 06:01:04 PM PDT 24
Finished Jul 18 06:02:13 PM PDT 24
Peak memory 215932 kb
Host smart-61762111-5883-441e-aefc-2722d8648479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18736991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.18736991
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1669364520
Short name T155
Test name
Test status
Simulation time 109869952836 ps
CPU time 224.9 seconds
Started Jul 18 06:01:12 PM PDT 24
Finished Jul 18 06:05:10 PM PDT 24
Peak memory 221352 kb
Host smart-14d15996-ba9e-4333-a8d1-c9bf1f32dd6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669364520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1669364520
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.52016096
Short name T269
Test name
Test status
Simulation time 843328166 ps
CPU time 13.07 seconds
Started Jul 18 06:01:07 PM PDT 24
Finished Jul 18 06:01:33 PM PDT 24
Peak memory 212448 kb
Host smart-f4ca7d00-9fa8-4489-b274-86ef023ecc50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52016096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.52016096
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3706773487
Short name T39
Test name
Test status
Simulation time 248166605571 ps
CPU time 626.77 seconds
Started Jul 18 06:01:12 PM PDT 24
Finished Jul 18 06:11:52 PM PDT 24
Peak memory 217104 kb
Host smart-59da04c9-b13e-450f-a83b-3e0dc7281555
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706773487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3706773487
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3370616704
Short name T291
Test name
Test status
Simulation time 12949306647 ps
CPU time 55.97 seconds
Started Jul 18 06:01:06 PM PDT 24
Finished Jul 18 06:02:14 PM PDT 24
Peak memory 219420 kb
Host smart-5f139877-67c9-452c-b35b-5a3dfbbe85bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370616704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3370616704
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.278605341
Short name T280
Test name
Test status
Simulation time 6205640460 ps
CPU time 26.82 seconds
Started Jul 18 06:01:07 PM PDT 24
Finished Jul 18 06:01:47 PM PDT 24
Peak memory 211412 kb
Host smart-c31fea81-e075-408e-baf3-2757b9fa162b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=278605341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.278605341
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.2425206687
Short name T210
Test name
Test status
Simulation time 3276753792 ps
CPU time 42.67 seconds
Started Jul 18 06:01:12 PM PDT 24
Finished Jul 18 06:02:08 PM PDT 24
Peak memory 216252 kb
Host smart-af66c652-f986-4464-844a-eac3b438ddb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425206687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.2425206687
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2564959452
Short name T8
Test name
Test status
Simulation time 8760505500 ps
CPU time 44.1 seconds
Started Jul 18 06:01:05 PM PDT 24
Finished Jul 18 06:02:02 PM PDT 24
Peak memory 212368 kb
Host smart-488b8ec5-0adc-4ee7-8987-5924c93a5a0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564959452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2564959452
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2010087538
Short name T314
Test name
Test status
Simulation time 2060471067 ps
CPU time 8.57 seconds
Started Jul 18 06:01:02 PM PDT 24
Finished Jul 18 06:01:20 PM PDT 24
Peak memory 213316 kb
Host smart-7dfbfed6-ce30-48de-8e9a-74478b4c9481
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010087538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2010087538
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3102891704
Short name T172
Test name
Test status
Simulation time 16366671999 ps
CPU time 342.75 seconds
Started Jul 18 06:01:04 PM PDT 24
Finished Jul 18 06:07:05 PM PDT 24
Peak memory 219596 kb
Host smart-aa609e1e-1bb4-4ddf-af8e-d44e18817916
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102891704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3102891704
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.4063619331
Short name T237
Test name
Test status
Simulation time 34620392893 ps
CPU time 68.79 seconds
Started Jul 18 06:01:07 PM PDT 24
Finished Jul 18 06:02:29 PM PDT 24
Peak memory 219444 kb
Host smart-5f140853-4099-4d11-9fd5-22794f296c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063619331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.4063619331
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.4209769756
Short name T301
Test name
Test status
Simulation time 15726286866 ps
CPU time 30.76 seconds
Started Jul 18 06:00:49 PM PDT 24
Finished Jul 18 06:01:24 PM PDT 24
Peak memory 219376 kb
Host smart-361072ea-abd8-4492-832f-5b66ea47c792
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4209769756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.4209769756
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2177810656
Short name T28
Test name
Test status
Simulation time 748558077 ps
CPU time 221.96 seconds
Started Jul 18 06:00:55 PM PDT 24
Finished Jul 18 06:04:43 PM PDT 24
Peak memory 238324 kb
Host smart-3e16b76a-a109-4158-8802-8e6777d4b5f5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177810656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2177810656
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.4024036786
Short name T191
Test name
Test status
Simulation time 16392516230 ps
CPU time 50.94 seconds
Started Jul 18 06:01:00 PM PDT 24
Finished Jul 18 06:01:59 PM PDT 24
Peak memory 216380 kb
Host smart-5edf7e35-e52c-4558-aed5-efe7137c53de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024036786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.4024036786
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.245067361
Short name T192
Test name
Test status
Simulation time 22637595630 ps
CPU time 124.46 seconds
Started Jul 18 06:00:56 PM PDT 24
Finished Jul 18 06:03:06 PM PDT 24
Peak memory 221680 kb
Host smart-a914e604-8022-4b3b-b889-08aa9afa12fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245067361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.245067361
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.949658877
Short name T3
Test name
Test status
Simulation time 5560656734 ps
CPU time 20.41 seconds
Started Jul 18 06:01:40 PM PDT 24
Finished Jul 18 06:02:16 PM PDT 24
Peak memory 213336 kb
Host smart-ac6849f7-6ef5-465e-aa83-9688e8a54d69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949658877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.949658877
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1459257147
Short name T195
Test name
Test status
Simulation time 3173267422 ps
CPU time 188.46 seconds
Started Jul 18 06:01:07 PM PDT 24
Finished Jul 18 06:04:28 PM PDT 24
Peak memory 217720 kb
Host smart-3005b354-1a9c-4669-8082-1284c7816f0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459257147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1459257147
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2255202266
Short name T225
Test name
Test status
Simulation time 18910700532 ps
CPU time 45.66 seconds
Started Jul 18 06:01:07 PM PDT 24
Finished Jul 18 06:02:05 PM PDT 24
Peak memory 218928 kb
Host smart-e9306fbe-c46a-404f-913e-c505b62004f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255202266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2255202266
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2753346068
Short name T329
Test name
Test status
Simulation time 3461350207 ps
CPU time 20.98 seconds
Started Jul 18 06:01:05 PM PDT 24
Finished Jul 18 06:01:38 PM PDT 24
Peak memory 211724 kb
Host smart-c638acef-2235-46fb-84b3-3bf24e7e0ff1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2753346068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2753346068
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.4022298285
Short name T348
Test name
Test status
Simulation time 13748108599 ps
CPU time 138.64 seconds
Started Jul 18 06:01:07 PM PDT 24
Finished Jul 18 06:03:39 PM PDT 24
Peak memory 219272 kb
Host smart-9aeabee1-b9b7-497d-adcb-38d468638185
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022298285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.4022298285
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2084522258
Short name T313
Test name
Test status
Simulation time 96516604175 ps
CPU time 6597.73 seconds
Started Jul 18 06:01:07 PM PDT 24
Finished Jul 18 07:51:18 PM PDT 24
Peak memory 233672 kb
Host smart-6c9c8f3a-075c-4f21-8543-3ee2a438fbb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084522258 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.2084522258
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3712580906
Short name T164
Test name
Test status
Simulation time 2214420194 ps
CPU time 21.12 seconds
Started Jul 18 06:01:41 PM PDT 24
Finished Jul 18 06:02:18 PM PDT 24
Peak memory 216672 kb
Host smart-1cbc03e0-b510-495e-9163-d6886a1dd888
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712580906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3712580906
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1317431184
Short name T275
Test name
Test status
Simulation time 231709521775 ps
CPU time 520.71 seconds
Started Jul 18 06:00:59 PM PDT 24
Finished Jul 18 06:09:48 PM PDT 24
Peak memory 242968 kb
Host smart-62dcbcb3-c5b6-441b-9f13-d2be00990083
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317431184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1317431184
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.277004987
Short name T200
Test name
Test status
Simulation time 14347399527 ps
CPU time 41.69 seconds
Started Jul 18 06:01:39 PM PDT 24
Finished Jul 18 06:02:36 PM PDT 24
Peak memory 215268 kb
Host smart-f71bda8c-1e8b-4474-a51c-e26c3920e5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277004987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.277004987
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3773143903
Short name T332
Test name
Test status
Simulation time 3413073386 ps
CPU time 27.79 seconds
Started Jul 18 06:01:07 PM PDT 24
Finished Jul 18 06:01:48 PM PDT 24
Peak memory 219348 kb
Host smart-c2597b31-4c4f-415e-8101-377910bcbe33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3773143903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3773143903
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2865408559
Short name T34
Test name
Test status
Simulation time 18309749064 ps
CPU time 78.55 seconds
Started Jul 18 06:01:06 PM PDT 24
Finished Jul 18 06:02:37 PM PDT 24
Peak memory 215928 kb
Host smart-96442144-0aa2-4581-8875-026393f50b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865408559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2865408559
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1274939485
Short name T57
Test name
Test status
Simulation time 3199712947 ps
CPU time 36.26 seconds
Started Jul 18 06:01:33 PM PDT 24
Finished Jul 18 06:02:20 PM PDT 24
Peak memory 219256 kb
Host smart-8cfca843-c195-418d-bf80-70369bfd8f21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274939485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1274939485
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.914740822
Short name T36
Test name
Test status
Simulation time 6491055361 ps
CPU time 17.17 seconds
Started Jul 18 06:01:09 PM PDT 24
Finished Jul 18 06:01:39 PM PDT 24
Peak memory 217520 kb
Host smart-abdcba39-48ad-4bfa-aa4d-8ec8864288b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914740822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.914740822
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3971324474
Short name T307
Test name
Test status
Simulation time 29128501786 ps
CPU time 283.03 seconds
Started Jul 18 06:01:08 PM PDT 24
Finished Jul 18 06:06:04 PM PDT 24
Peak memory 236764 kb
Host smart-944d216f-13f6-4b35-b435-8733056d3842
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971324474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3971324474
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2171546902
Short name T320
Test name
Test status
Simulation time 2201856807 ps
CPU time 32.28 seconds
Started Jul 18 06:01:10 PM PDT 24
Finished Jul 18 06:01:56 PM PDT 24
Peak memory 219396 kb
Host smart-d76a6879-b6ed-4c45-9b88-fc8603960123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171546902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2171546902
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1613642065
Short name T159
Test name
Test status
Simulation time 289834316 ps
CPU time 12.29 seconds
Started Jul 18 06:01:04 PM PDT 24
Finished Jul 18 06:01:27 PM PDT 24
Peak memory 219348 kb
Host smart-3df046e1-bb36-4fb1-afad-a2da700b569e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1613642065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1613642065
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.4127801197
Short name T261
Test name
Test status
Simulation time 4128729533 ps
CPU time 37.13 seconds
Started Jul 18 06:01:05 PM PDT 24
Finished Jul 18 06:01:53 PM PDT 24
Peak memory 216268 kb
Host smart-2a6c7fac-adc2-4846-ad1b-0c5cf910f140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127801197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.4127801197
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1688622107
Short name T80
Test name
Test status
Simulation time 4093757340 ps
CPU time 38.05 seconds
Started Jul 18 06:01:03 PM PDT 24
Finished Jul 18 06:01:51 PM PDT 24
Peak memory 219160 kb
Host smart-198b6bc4-60fb-48c0-b934-8ea77d287757
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688622107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1688622107
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2307938060
Short name T245
Test name
Test status
Simulation time 688938225 ps
CPU time 8.38 seconds
Started Jul 18 06:00:57 PM PDT 24
Finished Jul 18 06:01:12 PM PDT 24
Peak memory 213372 kb
Host smart-926823e9-6599-4315-b2a6-7a1e0313ad55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307938060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2307938060
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3555429492
Short name T40
Test name
Test status
Simulation time 70209303802 ps
CPU time 649.09 seconds
Started Jul 18 06:01:09 PM PDT 24
Finished Jul 18 06:12:11 PM PDT 24
Peak memory 239876 kb
Host smart-db5f239c-068b-411c-80d5-a6e312e55eef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555429492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3555429492
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1309904117
Short name T184
Test name
Test status
Simulation time 8506569215 ps
CPU time 45.2 seconds
Started Jul 18 06:01:03 PM PDT 24
Finished Jul 18 06:01:59 PM PDT 24
Peak memory 219420 kb
Host smart-cc3e4cdc-6b21-4e43-aa16-ae8c3db77d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309904117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1309904117
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.4151717754
Short name T277
Test name
Test status
Simulation time 7683724890 ps
CPU time 30.41 seconds
Started Jul 18 06:01:07 PM PDT 24
Finished Jul 18 06:01:51 PM PDT 24
Peak memory 219416 kb
Host smart-1b5782da-219d-471b-9a0a-0abeea8cdfea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4151717754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.4151717754
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2957245475
Short name T150
Test name
Test status
Simulation time 9952529323 ps
CPU time 35.05 seconds
Started Jul 18 06:01:04 PM PDT 24
Finished Jul 18 06:01:51 PM PDT 24
Peak memory 216992 kb
Host smart-a2790576-ee6d-4622-9bd8-19f24a2ea2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957245475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2957245475
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3598279244
Short name T292
Test name
Test status
Simulation time 2191083572 ps
CPU time 37.29 seconds
Started Jul 18 06:01:14 PM PDT 24
Finished Jul 18 06:02:04 PM PDT 24
Peak memory 219420 kb
Host smart-61ab4d43-00ab-4bbf-8f8d-610999d55987
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598279244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3598279244
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3857644039
Short name T148
Test name
Test status
Simulation time 4736578985 ps
CPU time 22.1 seconds
Started Jul 18 06:01:11 PM PDT 24
Finished Jul 18 06:01:47 PM PDT 24
Peak memory 217472 kb
Host smart-a33b845f-8242-4fe8-a968-74ba6d9dfc8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857644039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3857644039
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2720845036
Short name T175
Test name
Test status
Simulation time 18086936576 ps
CPU time 270.39 seconds
Started Jul 18 06:00:56 PM PDT 24
Finished Jul 18 06:05:32 PM PDT 24
Peak memory 217008 kb
Host smart-50304daa-8c78-4b29-803c-2d820a3a7fb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720845036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2720845036
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.4185802797
Short name T350
Test name
Test status
Simulation time 6095744455 ps
CPU time 55.42 seconds
Started Jul 18 06:01:11 PM PDT 24
Finished Jul 18 06:02:20 PM PDT 24
Peak memory 219264 kb
Host smart-e79c3534-7d3e-43d2-a533-0a67ece2fd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185802797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.4185802797
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2769811299
Short name T267
Test name
Test status
Simulation time 3559195127 ps
CPU time 29.14 seconds
Started Jul 18 06:01:11 PM PDT 24
Finished Jul 18 06:01:54 PM PDT 24
Peak memory 219292 kb
Host smart-bbef47d2-3a03-413d-9d56-00fa3d97b949
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2769811299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2769811299
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.2355196496
Short name T7
Test name
Test status
Simulation time 3827575001 ps
CPU time 35.8 seconds
Started Jul 18 06:01:10 PM PDT 24
Finished Jul 18 06:01:59 PM PDT 24
Peak memory 216616 kb
Host smart-57b2e76c-3baa-4e6c-8a27-487330150e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355196496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.2355196496
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1235552516
Short name T236
Test name
Test status
Simulation time 50333014267 ps
CPU time 109.89 seconds
Started Jul 18 06:01:11 PM PDT 24
Finished Jul 18 06:03:15 PM PDT 24
Peak memory 216600 kb
Host smart-588235ae-c812-4ce9-b0c3-7e323e083f9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235552516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1235552516
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.417948234
Short name T54
Test name
Test status
Simulation time 50469757162 ps
CPU time 990.6 seconds
Started Jul 18 06:01:11 PM PDT 24
Finished Jul 18 06:17:55 PM PDT 24
Peak memory 235868 kb
Host smart-9c41abfc-fe0c-4bf5-a185-f95c5da3649d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417948234 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.417948234
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3057687061
Short name T233
Test name
Test status
Simulation time 7048082879 ps
CPU time 27.35 seconds
Started Jul 18 06:01:05 PM PDT 24
Finished Jul 18 06:01:43 PM PDT 24
Peak memory 217524 kb
Host smart-e7592e2a-67f9-4e46-98ac-357338714594
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057687061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3057687061
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.452891223
Short name T258
Test name
Test status
Simulation time 28376999870 ps
CPU time 212.95 seconds
Started Jul 18 06:01:04 PM PDT 24
Finished Jul 18 06:04:48 PM PDT 24
Peak memory 237196 kb
Host smart-1470d74e-8510-4e20-9204-9c826b8134a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452891223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.452891223
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.88553783
Short name T217
Test name
Test status
Simulation time 90014088528 ps
CPU time 51.85 seconds
Started Jul 18 06:01:02 PM PDT 24
Finished Jul 18 06:02:02 PM PDT 24
Peak memory 219396 kb
Host smart-364137b9-b044-4cf7-84ca-d5158da52fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88553783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.88553783
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3085104023
Short name T268
Test name
Test status
Simulation time 17588398847 ps
CPU time 31.07 seconds
Started Jul 18 06:01:12 PM PDT 24
Finished Jul 18 06:01:56 PM PDT 24
Peak memory 219376 kb
Host smart-64440b51-d119-4500-9434-e452094556e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3085104023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3085104023
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1874613057
Short name T326
Test name
Test status
Simulation time 1443843419 ps
CPU time 19.87 seconds
Started Jul 18 06:01:12 PM PDT 24
Finished Jul 18 06:01:45 PM PDT 24
Peak memory 215824 kb
Host smart-1b847e20-2959-408a-a76b-6c733da98b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874613057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1874613057
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.4145174316
Short name T56
Test name
Test status
Simulation time 3099233747 ps
CPU time 26.23 seconds
Started Jul 18 06:00:55 PM PDT 24
Finished Jul 18 06:01:28 PM PDT 24
Peak memory 219288 kb
Host smart-7ded5e26-6ac1-4117-80f7-441470f72eaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145174316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.4145174316
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2671616715
Short name T264
Test name
Test status
Simulation time 2998032937 ps
CPU time 25.95 seconds
Started Jul 18 06:01:04 PM PDT 24
Finished Jul 18 06:01:40 PM PDT 24
Peak memory 213328 kb
Host smart-60762bb0-86c1-4818-b325-6eafe5017267
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671616715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2671616715
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1053049044
Short name T344
Test name
Test status
Simulation time 52098936400 ps
CPU time 261.6 seconds
Started Jul 18 06:01:05 PM PDT 24
Finished Jul 18 06:05:38 PM PDT 24
Peak memory 235776 kb
Host smart-515019b4-ea5d-48ac-8169-07fdb2db00db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053049044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1053049044
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.4101869161
Short name T177
Test name
Test status
Simulation time 8040588285 ps
CPU time 60.71 seconds
Started Jul 18 06:01:05 PM PDT 24
Finished Jul 18 06:02:18 PM PDT 24
Peak memory 219400 kb
Host smart-24130823-4ec2-4654-88f0-5851024d0a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101869161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.4101869161
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.740306089
Short name T162
Test name
Test status
Simulation time 2998293411 ps
CPU time 24.18 seconds
Started Jul 18 06:01:01 PM PDT 24
Finished Jul 18 06:01:33 PM PDT 24
Peak memory 219428 kb
Host smart-d981535f-69c3-4e9e-a9e5-7c9208d8e97d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=740306089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.740306089
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.880649232
Short name T202
Test name
Test status
Simulation time 380275529 ps
CPU time 19.46 seconds
Started Jul 18 06:01:05 PM PDT 24
Finished Jul 18 06:01:37 PM PDT 24
Peak memory 215684 kb
Host smart-037e1835-35d1-4f4c-b9b5-5799b98433a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880649232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.880649232
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.812172725
Short name T354
Test name
Test status
Simulation time 3424394900 ps
CPU time 25.47 seconds
Started Jul 18 06:01:02 PM PDT 24
Finished Jul 18 06:01:37 PM PDT 24
Peak memory 219416 kb
Host smart-5955d2f8-2b71-4b54-b975-bf5f52e00e30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812172725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.812172725
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3675483130
Short name T338
Test name
Test status
Simulation time 3228146486 ps
CPU time 26 seconds
Started Jul 18 06:01:07 PM PDT 24
Finished Jul 18 06:01:46 PM PDT 24
Peak memory 213312 kb
Host smart-54f2d8aa-2b03-434e-9e55-1415fb2b7326
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675483130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3675483130
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3596631014
Short name T330
Test name
Test status
Simulation time 38717908840 ps
CPU time 408.43 seconds
Started Jul 18 06:01:27 PM PDT 24
Finished Jul 18 06:08:23 PM PDT 24
Peak memory 225608 kb
Host smart-98c74496-8bd5-43ee-acdf-a7de2171411c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596631014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3596631014
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3114187601
Short name T1
Test name
Test status
Simulation time 2802602397 ps
CPU time 37.39 seconds
Started Jul 18 06:01:33 PM PDT 24
Finished Jul 18 06:02:23 PM PDT 24
Peak memory 219372 kb
Host smart-0d625d10-abae-4ca7-be62-63449a564caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114187601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3114187601
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3884778579
Short name T227
Test name
Test status
Simulation time 643359665 ps
CPU time 10.59 seconds
Started Jul 18 06:00:55 PM PDT 24
Finished Jul 18 06:01:12 PM PDT 24
Peak memory 219364 kb
Host smart-007e902f-1ca7-47fd-a696-2d74f920ebbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3884778579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3884778579
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3392623511
Short name T235
Test name
Test status
Simulation time 706437658 ps
CPU time 20.53 seconds
Started Jul 18 06:01:08 PM PDT 24
Finished Jul 18 06:01:42 PM PDT 24
Peak memory 215788 kb
Host smart-916500c2-052e-4b47-a24e-605501ecc22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392623511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3392623511
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.532334979
Short name T160
Test name
Test status
Simulation time 9090601146 ps
CPU time 79.36 seconds
Started Jul 18 06:01:05 PM PDT 24
Finished Jul 18 06:02:36 PM PDT 24
Peak memory 219408 kb
Host smart-0c32584d-9fda-4c62-83cc-4d5b5a897eaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532334979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.532334979
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2655284433
Short name T26
Test name
Test status
Simulation time 3939233564 ps
CPU time 20.45 seconds
Started Jul 18 06:01:03 PM PDT 24
Finished Jul 18 06:01:34 PM PDT 24
Peak memory 213356 kb
Host smart-049bb874-2445-4665-9f07-68eda7c13f35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655284433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2655284433
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3590203897
Short name T146
Test name
Test status
Simulation time 61502892231 ps
CPU time 272.43 seconds
Started Jul 18 06:01:35 PM PDT 24
Finished Jul 18 06:06:20 PM PDT 24
Peak memory 237096 kb
Host smart-41ccdfe5-4434-472a-8d87-91bf22c46ee2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590203897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3590203897
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2509926435
Short name T231
Test name
Test status
Simulation time 49165143408 ps
CPU time 57.32 seconds
Started Jul 18 06:01:32 PM PDT 24
Finished Jul 18 06:02:39 PM PDT 24
Peak memory 219260 kb
Host smart-1d193807-18b5-4fcd-8703-dd02db4156d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509926435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2509926435
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3061863165
Short name T126
Test name
Test status
Simulation time 363309700 ps
CPU time 12.65 seconds
Started Jul 18 06:01:03 PM PDT 24
Finished Jul 18 06:01:26 PM PDT 24
Peak memory 218084 kb
Host smart-a6255272-a9ca-4849-a558-561e675fb084
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3061863165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3061863165
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.896248058
Short name T308
Test name
Test status
Simulation time 39699231279 ps
CPU time 52.26 seconds
Started Jul 18 06:01:40 PM PDT 24
Finished Jul 18 06:02:48 PM PDT 24
Peak memory 216020 kb
Host smart-5af23c52-fdde-49bc-bf2b-ab9712e89fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896248058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.896248058
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3359504923
Short name T144
Test name
Test status
Simulation time 24691179217 ps
CPU time 121.63 seconds
Started Jul 18 06:01:03 PM PDT 24
Finished Jul 18 06:03:15 PM PDT 24
Peak memory 220128 kb
Host smart-44ba7187-fb69-4520-bf39-d13de3b2e889
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359504923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3359504923
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.315876967
Short name T212
Test name
Test status
Simulation time 386175032 ps
CPU time 8.43 seconds
Started Jul 18 06:01:05 PM PDT 24
Finished Jul 18 06:01:25 PM PDT 24
Peak memory 217176 kb
Host smart-c4e10eaf-9c59-41c1-967e-aff8c208a552
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315876967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.315876967
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3178377122
Short name T284
Test name
Test status
Simulation time 14766784091 ps
CPU time 283.14 seconds
Started Jul 18 06:01:12 PM PDT 24
Finished Jul 18 06:06:08 PM PDT 24
Peak memory 242100 kb
Host smart-ce129fd4-5a42-406c-b914-90d03448902e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178377122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3178377122
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2611556041
Short name T147
Test name
Test status
Simulation time 43175282729 ps
CPU time 59.43 seconds
Started Jul 18 06:01:11 PM PDT 24
Finished Jul 18 06:02:25 PM PDT 24
Peak memory 219216 kb
Host smart-e47a64eb-35ff-4e4e-90f5-1507fd733f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611556041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2611556041
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.715084856
Short name T302
Test name
Test status
Simulation time 13747276097 ps
CPU time 28.13 seconds
Started Jul 18 06:01:16 PM PDT 24
Finished Jul 18 06:01:56 PM PDT 24
Peak memory 211660 kb
Host smart-33b792eb-f78c-43cb-a290-edf839758c13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=715084856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.715084856
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2358156348
Short name T77
Test name
Test status
Simulation time 25292904575 ps
CPU time 64.96 seconds
Started Jul 18 06:01:10 PM PDT 24
Finished Jul 18 06:02:29 PM PDT 24
Peak memory 216796 kb
Host smart-97bc881f-e130-4e4a-a2af-f4a884a6da75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358156348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2358156348
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1954533231
Short name T342
Test name
Test status
Simulation time 68370309505 ps
CPU time 139.5 seconds
Started Jul 18 06:01:19 PM PDT 24
Finished Jul 18 06:03:49 PM PDT 24
Peak memory 219920 kb
Host smart-aed03d7e-c8dc-4dab-ab17-dc23a28e729e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954533231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1954533231
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1547081232
Short name T216
Test name
Test status
Simulation time 3227991289 ps
CPU time 26.79 seconds
Started Jul 18 06:01:07 PM PDT 24
Finished Jul 18 06:01:47 PM PDT 24
Peak memory 217468 kb
Host smart-e0be9ce2-6b35-451b-8964-1c7304c8e76b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547081232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1547081232
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.167232472
Short name T288
Test name
Test status
Simulation time 43493842052 ps
CPU time 613.97 seconds
Started Jul 18 06:01:06 PM PDT 24
Finished Jul 18 06:11:32 PM PDT 24
Peak memory 229452 kb
Host smart-a2aa55f2-35f6-4bb2-94bd-c61fab312bca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167232472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.167232472
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.254884026
Short name T250
Test name
Test status
Simulation time 356857497 ps
CPU time 19.78 seconds
Started Jul 18 06:00:45 PM PDT 24
Finished Jul 18 06:01:10 PM PDT 24
Peak memory 219360 kb
Host smart-ebd9d091-efd4-452c-b169-e574c19bf9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254884026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.254884026
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.955763646
Short name T204
Test name
Test status
Simulation time 2265189051 ps
CPU time 14.06 seconds
Started Jul 18 06:00:54 PM PDT 24
Finished Jul 18 06:01:14 PM PDT 24
Peak memory 219204 kb
Host smart-ac74e36f-0dea-4831-94ae-4993114cc68d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=955763646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.955763646
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.957986104
Short name T29
Test name
Test status
Simulation time 3830099791 ps
CPU time 136.9 seconds
Started Jul 18 06:01:04 PM PDT 24
Finished Jul 18 06:03:31 PM PDT 24
Peak memory 238620 kb
Host smart-a8f489f6-a4c5-4b9e-b27c-98a9c4b9475e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957986104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.957986104
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.4102971557
Short name T121
Test name
Test status
Simulation time 37337392898 ps
CPU time 52.65 seconds
Started Jul 18 06:00:55 PM PDT 24
Finished Jul 18 06:01:54 PM PDT 24
Peak memory 216452 kb
Host smart-60aa70d6-cd66-48d4-ae32-a7a0c85c2f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102971557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.4102971557
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1174748038
Short name T58
Test name
Test status
Simulation time 19251872321 ps
CPU time 108.95 seconds
Started Jul 18 06:00:54 PM PDT 24
Finished Jul 18 06:02:49 PM PDT 24
Peak memory 219192 kb
Host smart-e0c1cb7d-85aa-4b71-9baf-74139ffd6660
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174748038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1174748038
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.2312884439
Short name T51
Test name
Test status
Simulation time 42823729650 ps
CPU time 833.9 seconds
Started Jul 18 06:00:55 PM PDT 24
Finished Jul 18 06:14:55 PM PDT 24
Peak memory 230688 kb
Host smart-dfee3adb-e0fb-401b-8c5a-7c8cec9d5d18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312884439 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.2312884439
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1169501953
Short name T168
Test name
Test status
Simulation time 10580403280 ps
CPU time 20.98 seconds
Started Jul 18 06:01:10 PM PDT 24
Finished Jul 18 06:01:44 PM PDT 24
Peak memory 217324 kb
Host smart-39c42f06-29ef-42b0-9797-0c4769c9c15e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169501953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1169501953
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2170749998
Short name T188
Test name
Test status
Simulation time 170812211043 ps
CPU time 576.01 seconds
Started Jul 18 06:00:57 PM PDT 24
Finished Jul 18 06:10:39 PM PDT 24
Peak memory 236420 kb
Host smart-f3376967-a22b-406f-97fd-ae4e630af0e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170749998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2170749998
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.63117393
Short name T336
Test name
Test status
Simulation time 6899663531 ps
CPU time 54.5 seconds
Started Jul 18 06:01:12 PM PDT 24
Finished Jul 18 06:02:20 PM PDT 24
Peak memory 219224 kb
Host smart-bf3b66fe-2739-4352-989c-bfc5ea73f476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63117393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.63117393
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1760959979
Short name T218
Test name
Test status
Simulation time 17809615060 ps
CPU time 31.89 seconds
Started Jul 18 06:01:09 PM PDT 24
Finished Jul 18 06:01:54 PM PDT 24
Peak memory 217760 kb
Host smart-9bb403c3-fe75-4f6c-ab84-2db121a93c00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1760959979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1760959979
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1484154954
Short name T170
Test name
Test status
Simulation time 664562344 ps
CPU time 19.52 seconds
Started Jul 18 06:00:56 PM PDT 24
Finished Jul 18 06:01:21 PM PDT 24
Peak memory 216544 kb
Host smart-b2b732d6-755f-48b2-8e2c-831023e77127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484154954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1484154954
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.4146206700
Short name T340
Test name
Test status
Simulation time 4473688004 ps
CPU time 91.64 seconds
Started Jul 18 06:01:09 PM PDT 24
Finished Jul 18 06:02:54 PM PDT 24
Peak memory 219932 kb
Host smart-2ddda8e3-77f6-43b9-868d-a3394fd6334d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146206700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.4146206700
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1082796637
Short name T213
Test name
Test status
Simulation time 7584206907 ps
CPU time 20 seconds
Started Jul 18 06:01:04 PM PDT 24
Finished Jul 18 06:01:35 PM PDT 24
Peak memory 213344 kb
Host smart-3abb6136-49b7-433a-a726-72491563d37e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082796637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1082796637
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.744293313
Short name T190
Test name
Test status
Simulation time 17950489457 ps
CPU time 432.35 seconds
Started Jul 18 06:01:11 PM PDT 24
Finished Jul 18 06:08:37 PM PDT 24
Peak memory 236676 kb
Host smart-5fe067f5-7afe-486f-81eb-6ab7b15af3dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744293313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.744293313
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.277335496
Short name T306
Test name
Test status
Simulation time 7320886134 ps
CPU time 59.97 seconds
Started Jul 18 06:01:11 PM PDT 24
Finished Jul 18 06:02:25 PM PDT 24
Peak memory 219392 kb
Host smart-bd9a1d9f-cd51-43b7-b72e-1381bd3c8bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277335496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.277335496
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.651835611
Short name T230
Test name
Test status
Simulation time 3089621658 ps
CPU time 26.13 seconds
Started Jul 18 06:01:11 PM PDT 24
Finished Jul 18 06:01:51 PM PDT 24
Peak memory 219216 kb
Host smart-92c2e3f6-d21a-4926-b373-832f3829fc16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=651835611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.651835611
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3952454128
Short name T116
Test name
Test status
Simulation time 2582248606 ps
CPU time 19.43 seconds
Started Jul 18 06:01:11 PM PDT 24
Finished Jul 18 06:01:44 PM PDT 24
Peak memory 217016 kb
Host smart-f365f431-d670-44aa-8026-30159be1ac69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952454128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3952454128
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3938855442
Short name T10
Test name
Test status
Simulation time 39381894672 ps
CPU time 112.65 seconds
Started Jul 18 06:01:11 PM PDT 24
Finished Jul 18 06:03:17 PM PDT 24
Peak memory 227600 kb
Host smart-b2ecd780-f0fc-447b-ba6a-18a7f7ebac51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938855442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3938855442
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3519131822
Short name T120
Test name
Test status
Simulation time 1495677128 ps
CPU time 17.5 seconds
Started Jul 18 06:01:14 PM PDT 24
Finished Jul 18 06:01:44 PM PDT 24
Peak memory 213276 kb
Host smart-8ec3f426-3751-4cae-8ebb-a619fbc4f5bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519131822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3519131822
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.708480259
Short name T45
Test name
Test status
Simulation time 64137901917 ps
CPU time 561.66 seconds
Started Jul 18 06:01:16 PM PDT 24
Finished Jul 18 06:10:49 PM PDT 24
Peak memory 218080 kb
Host smart-ce668a2f-2d08-48ad-bc49-d2e30f925a30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708480259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.708480259
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.561399567
Short name T324
Test name
Test status
Simulation time 5652691984 ps
CPU time 52.74 seconds
Started Jul 18 06:01:29 PM PDT 24
Finished Jul 18 06:02:30 PM PDT 24
Peak memory 219244 kb
Host smart-77a99ffb-348e-4a35-87fb-aaee881f57fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561399567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.561399567
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.918215874
Short name T241
Test name
Test status
Simulation time 1921463493 ps
CPU time 10.59 seconds
Started Jul 18 06:00:55 PM PDT 24
Finished Jul 18 06:01:12 PM PDT 24
Peak memory 219320 kb
Host smart-cb90e221-4c29-4a0c-86b8-d32446ddaa2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=918215874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.918215874
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3208387840
Short name T304
Test name
Test status
Simulation time 5165505661 ps
CPU time 42.39 seconds
Started Jul 18 06:01:03 PM PDT 24
Finished Jul 18 06:01:55 PM PDT 24
Peak memory 216232 kb
Host smart-42d6d208-7494-4897-b2c7-f8c9f28695b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208387840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3208387840
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.4095549930
Short name T149
Test name
Test status
Simulation time 10953037315 ps
CPU time 96.35 seconds
Started Jul 18 06:00:54 PM PDT 24
Finished Jul 18 06:02:36 PM PDT 24
Peak memory 219712 kb
Host smart-8ed5a36d-ff7f-4e7c-9182-42c1fec5445b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095549930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.4095549930
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1400597858
Short name T25
Test name
Test status
Simulation time 2681956877 ps
CPU time 24.61 seconds
Started Jul 18 06:01:17 PM PDT 24
Finished Jul 18 06:01:53 PM PDT 24
Peak memory 217240 kb
Host smart-06ccf951-c49b-4f8f-b1c0-cf30b3ab7bd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400597858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1400597858
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2307945909
Short name T41
Test name
Test status
Simulation time 185100793436 ps
CPU time 527.35 seconds
Started Jul 18 06:01:29 PM PDT 24
Finished Jul 18 06:10:25 PM PDT 24
Peak memory 237088 kb
Host smart-7dd0a05d-46d4-4209-bed6-4cd7e70a1eb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307945909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2307945909
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.320811723
Short name T27
Test name
Test status
Simulation time 22011946472 ps
CPU time 54.21 seconds
Started Jul 18 06:01:10 PM PDT 24
Finished Jul 18 06:02:18 PM PDT 24
Peak memory 219240 kb
Host smart-90b089af-616b-4a62-a637-6f5eb92c7ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320811723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.320811723
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2937640699
Short name T317
Test name
Test status
Simulation time 182993771 ps
CPU time 10.33 seconds
Started Jul 18 06:01:13 PM PDT 24
Finished Jul 18 06:01:37 PM PDT 24
Peak memory 219348 kb
Host smart-39900f59-4b3e-4fb7-894d-76bfaf85a9e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2937640699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2937640699
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.354700059
Short name T5
Test name
Test status
Simulation time 345676174 ps
CPU time 20.22 seconds
Started Jul 18 06:01:32 PM PDT 24
Finished Jul 18 06:02:02 PM PDT 24
Peak memory 216236 kb
Host smart-85c2c654-ef71-4d21-bf16-e4c9490b342c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354700059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.354700059
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1401205350
Short name T305
Test name
Test status
Simulation time 22359180225 ps
CPU time 121.77 seconds
Started Jul 18 06:01:23 PM PDT 24
Finished Jul 18 06:03:34 PM PDT 24
Peak memory 221076 kb
Host smart-645eca78-4dd1-4c26-9572-772fb4fceb07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401205350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1401205350
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.1007466911
Short name T50
Test name
Test status
Simulation time 163192858247 ps
CPU time 3152.72 seconds
Started Jul 18 06:01:32 PM PDT 24
Finished Jul 18 06:54:15 PM PDT 24
Peak memory 246872 kb
Host smart-fbbeb160-1730-4a3e-ab46-4251914b2292
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007466911 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.1007466911
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.880493087
Short name T65
Test name
Test status
Simulation time 2225119072 ps
CPU time 22.24 seconds
Started Jul 18 06:01:36 PM PDT 24
Finished Jul 18 06:02:12 PM PDT 24
Peak memory 217224 kb
Host smart-70f12ec8-d34d-45a3-b0c2-9bf8bec990b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880493087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.880493087
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.253990399
Short name T333
Test name
Test status
Simulation time 127334978138 ps
CPU time 1336.77 seconds
Started Jul 18 06:01:19 PM PDT 24
Finished Jul 18 06:23:46 PM PDT 24
Peak memory 240924 kb
Host smart-06b8bf1c-45a2-4dbd-8adb-761e46628caa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253990399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.253990399
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.904901483
Short name T158
Test name
Test status
Simulation time 41054393751 ps
CPU time 53.84 seconds
Started Jul 18 06:01:09 PM PDT 24
Finished Jul 18 06:02:16 PM PDT 24
Peak memory 219404 kb
Host smart-ce2f7fc4-8fce-430a-ac98-a484ff4ad2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904901483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.904901483
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3349176021
Short name T118
Test name
Test status
Simulation time 693441694 ps
CPU time 10.3 seconds
Started Jul 18 06:01:08 PM PDT 24
Finished Jul 18 06:01:32 PM PDT 24
Peak memory 219364 kb
Host smart-02cef4cd-618b-47ab-96b4-cab1d05a9f69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3349176021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3349176021
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2273323397
Short name T287
Test name
Test status
Simulation time 2338613069 ps
CPU time 29.16 seconds
Started Jul 18 06:01:27 PM PDT 24
Finished Jul 18 06:02:04 PM PDT 24
Peak memory 217116 kb
Host smart-0ac042b7-8d49-4632-8cdd-3100c5b849c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273323397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2273323397
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2845551675
Short name T271
Test name
Test status
Simulation time 13549539329 ps
CPU time 33.68 seconds
Started Jul 18 06:01:16 PM PDT 24
Finished Jul 18 06:02:01 PM PDT 24
Peak memory 214704 kb
Host smart-4893f44c-d403-4308-bbb8-43e7f250a091
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845551675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2845551675
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.410329506
Short name T322
Test name
Test status
Simulation time 7521632416 ps
CPU time 19.86 seconds
Started Jul 18 06:01:13 PM PDT 24
Finished Jul 18 06:01:46 PM PDT 24
Peak memory 217528 kb
Host smart-97dc772d-96ec-41e6-9575-e9fdaf631c66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410329506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.410329506
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3074968773
Short name T294
Test name
Test status
Simulation time 107562319908 ps
CPU time 544.5 seconds
Started Jul 18 06:01:07 PM PDT 24
Finished Jul 18 06:10:25 PM PDT 24
Peak memory 219604 kb
Host smart-56640da0-aee0-45ee-9cc9-a60ca0236b4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074968773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3074968773
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3829259564
Short name T297
Test name
Test status
Simulation time 2623589383 ps
CPU time 36.37 seconds
Started Jul 18 06:01:30 PM PDT 24
Finished Jul 18 06:02:15 PM PDT 24
Peak memory 219424 kb
Host smart-e126c4de-f0b7-4d5c-8611-f5c0a9cb9537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829259564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3829259564
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.920433720
Short name T138
Test name
Test status
Simulation time 1195639601 ps
CPU time 17.27 seconds
Started Jul 18 06:01:26 PM PDT 24
Finished Jul 18 06:01:51 PM PDT 24
Peak memory 211280 kb
Host smart-52c77868-8088-4c78-a63b-1becf528e225
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=920433720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.920433720
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.206869805
Short name T189
Test name
Test status
Simulation time 349575155 ps
CPU time 20.31 seconds
Started Jul 18 06:01:21 PM PDT 24
Finished Jul 18 06:01:51 PM PDT 24
Peak memory 216636 kb
Host smart-afaf0cdb-f327-4301-b738-53e0440d686c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206869805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.206869805
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2796517654
Short name T341
Test name
Test status
Simulation time 7338810002 ps
CPU time 33.86 seconds
Started Jul 18 06:01:39 PM PDT 24
Finished Jul 18 06:02:29 PM PDT 24
Peak memory 219388 kb
Host smart-924766fe-4401-495f-96cc-70b89be5df81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796517654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2796517654
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1110170715
Short name T145
Test name
Test status
Simulation time 13868632266 ps
CPU time 28.22 seconds
Started Jul 18 06:01:17 PM PDT 24
Finished Jul 18 06:01:57 PM PDT 24
Peak memory 213376 kb
Host smart-3ab20821-1168-48cc-9942-c053bdcf89e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110170715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1110170715
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3963617113
Short name T312
Test name
Test status
Simulation time 8654354316 ps
CPU time 311.49 seconds
Started Jul 18 06:01:17 PM PDT 24
Finished Jul 18 06:06:40 PM PDT 24
Peak memory 234772 kb
Host smart-631cae71-320c-4eca-b41f-d2150b2a8280
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963617113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3963617113
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.4037398418
Short name T273
Test name
Test status
Simulation time 6014481360 ps
CPU time 53.56 seconds
Started Jul 18 06:01:28 PM PDT 24
Finished Jul 18 06:02:29 PM PDT 24
Peak memory 219380 kb
Host smart-9368c65e-4272-4b1f-bd8a-82f3f28845b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037398418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.4037398418
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2596881510
Short name T197
Test name
Test status
Simulation time 3147427502 ps
CPU time 24.15 seconds
Started Jul 18 06:01:17 PM PDT 24
Finished Jul 18 06:01:53 PM PDT 24
Peak memory 219420 kb
Host smart-8be5e508-42ee-44c9-860d-f08a46d4aa57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2596881510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2596881510
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3761619757
Short name T337
Test name
Test status
Simulation time 20471852950 ps
CPU time 63.22 seconds
Started Jul 18 06:01:20 PM PDT 24
Finished Jul 18 06:02:33 PM PDT 24
Peak memory 218048 kb
Host smart-059d38b3-7dc8-46d5-9ae1-5b6d4438d076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761619757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3761619757
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2125314537
Short name T132
Test name
Test status
Simulation time 22498666300 ps
CPU time 87.37 seconds
Started Jul 18 06:01:47 PM PDT 24
Finished Jul 18 06:03:28 PM PDT 24
Peak memory 227592 kb
Host smart-dc42ff01-2f04-406c-96ef-7ea12a47fdc9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125314537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2125314537
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.59462342
Short name T311
Test name
Test status
Simulation time 54113027579 ps
CPU time 25.19 seconds
Started Jul 18 06:01:13 PM PDT 24
Finished Jul 18 06:01:51 PM PDT 24
Peak memory 213348 kb
Host smart-f0f39f95-6cb7-48de-8cfe-66100c63350c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59462342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.59462342
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.4167719358
Short name T323
Test name
Test status
Simulation time 2532069445 ps
CPU time 116.42 seconds
Started Jul 18 06:01:28 PM PDT 24
Finished Jul 18 06:03:33 PM PDT 24
Peak memory 237132 kb
Host smart-e3c7912d-7212-4508-b00f-7860c958ee3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167719358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.4167719358
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3806134925
Short name T183
Test name
Test status
Simulation time 1649841481 ps
CPU time 19.31 seconds
Started Jul 18 06:01:09 PM PDT 24
Finished Jul 18 06:01:42 PM PDT 24
Peak memory 219356 kb
Host smart-ca603e64-5ccd-4778-acdd-d1df29921f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806134925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3806134925
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3938812622
Short name T167
Test name
Test status
Simulation time 12033096858 ps
CPU time 27.07 seconds
Started Jul 18 06:01:18 PM PDT 24
Finished Jul 18 06:01:56 PM PDT 24
Peak memory 219396 kb
Host smart-b8f5f559-1e81-496f-ae01-0dcdc6eefcf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3938812622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3938812622
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3837422504
Short name T78
Test name
Test status
Simulation time 4287115474 ps
CPU time 32.08 seconds
Started Jul 18 06:01:21 PM PDT 24
Finished Jul 18 06:02:03 PM PDT 24
Peak memory 217496 kb
Host smart-c85b1597-8104-436d-a8aa-639450bf9862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837422504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3837422504
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2307393815
Short name T274
Test name
Test status
Simulation time 83985494686 ps
CPU time 166.4 seconds
Started Jul 18 06:01:34 PM PDT 24
Finished Jul 18 06:04:32 PM PDT 24
Peak memory 221168 kb
Host smart-07fdcac0-4b3c-40b0-a872-bf258b819eac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307393815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2307393815
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.894861779
Short name T117
Test name
Test status
Simulation time 2928690886 ps
CPU time 13.76 seconds
Started Jul 18 06:01:12 PM PDT 24
Finished Jul 18 06:01:42 PM PDT 24
Peak memory 213356 kb
Host smart-e8920e94-5f92-439d-9197-a574fd6580ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894861779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.894861779
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3288594169
Short name T242
Test name
Test status
Simulation time 394611681619 ps
CPU time 411.36 seconds
Started Jul 18 06:01:28 PM PDT 24
Finished Jul 18 06:08:27 PM PDT 24
Peak memory 216028 kb
Host smart-e07a2f4d-53ba-43bb-8dbe-bb66ef1d7b08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288594169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3288594169
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1788832094
Short name T207
Test name
Test status
Simulation time 164254432801 ps
CPU time 69.07 seconds
Started Jul 18 06:01:16 PM PDT 24
Finished Jul 18 06:02:37 PM PDT 24
Peak memory 219444 kb
Host smart-0e56f6e0-f95f-474b-a979-e58157ba5b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788832094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1788832094
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.4214628941
Short name T222
Test name
Test status
Simulation time 7772417238 ps
CPU time 30.6 seconds
Started Jul 18 06:01:21 PM PDT 24
Finished Jul 18 06:02:01 PM PDT 24
Peak memory 219376 kb
Host smart-d84428a6-d8dd-4c0e-a363-e1a6dceb12ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4214628941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.4214628941
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2611893931
Short name T239
Test name
Test status
Simulation time 28430373508 ps
CPU time 59.36 seconds
Started Jul 18 06:01:23 PM PDT 24
Finished Jul 18 06:02:31 PM PDT 24
Peak memory 217464 kb
Host smart-34d79e18-f2e0-495b-b55b-bbcd14f3dbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611893931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2611893931
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.329184333
Short name T165
Test name
Test status
Simulation time 1423277457 ps
CPU time 56.97 seconds
Started Jul 18 06:01:20 PM PDT 24
Finished Jul 18 06:02:26 PM PDT 24
Peak memory 219340 kb
Host smart-8f6bb848-51eb-4f11-9c03-b003d3ae5982
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329184333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.329184333
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2766162867
Short name T199
Test name
Test status
Simulation time 10577135147 ps
CPU time 23.03 seconds
Started Jul 18 06:01:11 PM PDT 24
Finished Jul 18 06:01:48 PM PDT 24
Peak memory 217516 kb
Host smart-23d45b7e-e12c-458e-aaad-d41e8edfddd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766162867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2766162867
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2616532422
Short name T97
Test name
Test status
Simulation time 10377815161 ps
CPU time 190.96 seconds
Started Jul 18 06:01:08 PM PDT 24
Finished Jul 18 06:04:32 PM PDT 24
Peak memory 236972 kb
Host smart-88d55a24-b0e5-4d2f-9018-fa84c96db491
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616532422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2616532422
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2276013782
Short name T161
Test name
Test status
Simulation time 1321311221 ps
CPU time 19.59 seconds
Started Jul 18 06:01:10 PM PDT 24
Finished Jul 18 06:01:43 PM PDT 24
Peak memory 219356 kb
Host smart-d9fa0c4b-aa47-4434-83af-304b3580df81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276013782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2276013782
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2076375226
Short name T319
Test name
Test status
Simulation time 2827673597 ps
CPU time 18.21 seconds
Started Jul 18 06:01:28 PM PDT 24
Finished Jul 18 06:01:54 PM PDT 24
Peak memory 211692 kb
Host smart-bf5b178f-1b60-4c52-8a67-e96f011fe0e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2076375226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2076375226
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1511784797
Short name T131
Test name
Test status
Simulation time 1431409322 ps
CPU time 20.24 seconds
Started Jul 18 06:01:33 PM PDT 24
Finished Jul 18 06:02:06 PM PDT 24
Peak memory 216328 kb
Host smart-248c08fd-8ff0-4b2f-9fd6-6e5385a95b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511784797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1511784797
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2247579200
Short name T119
Test name
Test status
Simulation time 18308692187 ps
CPU time 83.82 seconds
Started Jul 18 06:01:06 PM PDT 24
Finished Jul 18 06:02:49 PM PDT 24
Peak memory 219432 kb
Host smart-06ada2cf-d14f-40a7-b01d-ecad017b961f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247579200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2247579200
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3801463051
Short name T115
Test name
Test status
Simulation time 5912285452 ps
CPU time 18.09 seconds
Started Jul 18 06:00:53 PM PDT 24
Finished Jul 18 06:01:17 PM PDT 24
Peak memory 217516 kb
Host smart-31f413f4-91a7-4d81-a155-83dddc9de92c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801463051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3801463051
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2737532235
Short name T38
Test name
Test status
Simulation time 178250070906 ps
CPU time 533.79 seconds
Started Jul 18 06:01:00 PM PDT 24
Finished Jul 18 06:10:02 PM PDT 24
Peak memory 237564 kb
Host smart-03eccc85-ec86-4a1e-804d-21d104bf9a4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737532235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2737532235
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.285365106
Short name T49
Test name
Test status
Simulation time 5218401470 ps
CPU time 51.34 seconds
Started Jul 18 06:03:36 PM PDT 24
Finished Jul 18 06:04:30 PM PDT 24
Peak memory 219340 kb
Host smart-ab5e0ea5-04cf-4a05-b953-a6cde63ba938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285365106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.285365106
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3599920157
Short name T173
Test name
Test status
Simulation time 15842092407 ps
CPU time 22.54 seconds
Started Jul 18 06:01:01 PM PDT 24
Finished Jul 18 06:01:31 PM PDT 24
Peak memory 211984 kb
Host smart-4757d3b6-108b-480c-bb73-443df15b08ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3599920157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3599920157
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.79291220
Short name T24
Test name
Test status
Simulation time 2938999855 ps
CPU time 227.58 seconds
Started Jul 18 06:00:53 PM PDT 24
Finished Jul 18 06:04:46 PM PDT 24
Peak memory 237852 kb
Host smart-96fd5b13-8d2c-4cc0-9116-9ce64ce9e99c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79291220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.79291220
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1926575118
Short name T130
Test name
Test status
Simulation time 18225365124 ps
CPU time 51.17 seconds
Started Jul 18 06:00:54 PM PDT 24
Finished Jul 18 06:01:51 PM PDT 24
Peak memory 217044 kb
Host smart-60222337-f8b2-4175-b5ef-7917ab0c799a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926575118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1926575118
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2451681545
Short name T114
Test name
Test status
Simulation time 22321754915 ps
CPU time 88.54 seconds
Started Jul 18 06:01:01 PM PDT 24
Finished Jul 18 06:02:38 PM PDT 24
Peak memory 219440 kb
Host smart-ba22d52d-12c3-45a5-919c-e752460a8e95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451681545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2451681545
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1201680229
Short name T176
Test name
Test status
Simulation time 832617545 ps
CPU time 13.12 seconds
Started Jul 18 06:01:23 PM PDT 24
Finished Jul 18 06:01:45 PM PDT 24
Peak memory 217096 kb
Host smart-b6b3ca5c-62dd-4d06-9984-3c3f29a52085
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201680229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1201680229
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2188780529
Short name T255
Test name
Test status
Simulation time 267570659885 ps
CPU time 788.52 seconds
Started Jul 18 06:01:30 PM PDT 24
Finished Jul 18 06:14:49 PM PDT 24
Peak memory 219604 kb
Host smart-ee2e61d7-d28d-4972-8f74-eee41e01663f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188780529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2188780529
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.4005208641
Short name T303
Test name
Test status
Simulation time 335967350 ps
CPU time 19.65 seconds
Started Jul 18 06:01:13 PM PDT 24
Finished Jul 18 06:01:46 PM PDT 24
Peak memory 219308 kb
Host smart-489529b3-096c-46a4-b914-937e563c7d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005208641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.4005208641
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.766092835
Short name T122
Test name
Test status
Simulation time 2532415733 ps
CPU time 17.77 seconds
Started Jul 18 06:01:29 PM PDT 24
Finished Jul 18 06:01:55 PM PDT 24
Peak memory 211520 kb
Host smart-020787a9-4981-4214-aa72-9d0850320e99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=766092835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.766092835
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.526378574
Short name T209
Test name
Test status
Simulation time 4796682198 ps
CPU time 47.43 seconds
Started Jul 18 06:01:15 PM PDT 24
Finished Jul 18 06:02:15 PM PDT 24
Peak memory 217012 kb
Host smart-3bda8956-64d3-49e2-ac47-31bf031329d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526378574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.526378574
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1459540031
Short name T174
Test name
Test status
Simulation time 1603185928 ps
CPU time 25.08 seconds
Started Jul 18 06:01:34 PM PDT 24
Finished Jul 18 06:02:11 PM PDT 24
Peak memory 219328 kb
Host smart-526e1e88-27a3-47c2-9067-4c03bea68394
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459540031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1459540031
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.3695814377
Short name T52
Test name
Test status
Simulation time 151804882547 ps
CPU time 1493.16 seconds
Started Jul 18 06:01:21 PM PDT 24
Finished Jul 18 06:26:24 PM PDT 24
Peak memory 235860 kb
Host smart-e2b8d23d-1d91-4eea-88d8-3960ebeebbb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695814377 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.3695814377
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2277331031
Short name T262
Test name
Test status
Simulation time 9534208394 ps
CPU time 22.74 seconds
Started Jul 18 06:01:20 PM PDT 24
Finished Jul 18 06:01:52 PM PDT 24
Peak memory 213352 kb
Host smart-74ea2aa5-2280-4122-b370-6241ded8e2b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277331031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2277331031
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3426847731
Short name T111
Test name
Test status
Simulation time 121093090706 ps
CPU time 210.34 seconds
Started Jul 18 06:01:30 PM PDT 24
Finished Jul 18 06:05:10 PM PDT 24
Peak memory 237784 kb
Host smart-24d6643b-595a-4923-9ea8-198e56ced8fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426847731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3426847731
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3557176156
Short name T13
Test name
Test status
Simulation time 6445317847 ps
CPU time 55.93 seconds
Started Jul 18 06:01:13 PM PDT 24
Finished Jul 18 06:02:22 PM PDT 24
Peak memory 219404 kb
Host smart-0f206ed3-61ae-4467-a55a-ed499e8abf14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557176156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3557176156
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1129944288
Short name T98
Test name
Test status
Simulation time 2447508070 ps
CPU time 14.52 seconds
Started Jul 18 06:01:10 PM PDT 24
Finished Jul 18 06:01:38 PM PDT 24
Peak memory 219388 kb
Host smart-c0995a2d-f969-49d4-aabf-12385716e400
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1129944288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1129944288
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1845954174
Short name T347
Test name
Test status
Simulation time 8275943508 ps
CPU time 94.76 seconds
Started Jul 18 06:01:28 PM PDT 24
Finished Jul 18 06:03:11 PM PDT 24
Peak memory 220508 kb
Host smart-786da347-f678-4b6b-8cee-3f658a33d120
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845954174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1845954174
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1690137637
Short name T67
Test name
Test status
Simulation time 176290334 ps
CPU time 8.23 seconds
Started Jul 18 06:01:18 PM PDT 24
Finished Jul 18 06:01:37 PM PDT 24
Peak memory 217132 kb
Host smart-35be49a5-6a32-48de-ad80-2a7f55a5d08c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690137637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1690137637
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1897229037
Short name T279
Test name
Test status
Simulation time 223125987083 ps
CPU time 422.88 seconds
Started Jul 18 06:01:32 PM PDT 24
Finished Jul 18 06:08:44 PM PDT 24
Peak memory 240364 kb
Host smart-145bcf66-e263-4c36-99d4-f7d015975377
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897229037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1897229037
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3236367362
Short name T219
Test name
Test status
Simulation time 8542539438 ps
CPU time 64.89 seconds
Started Jul 18 06:01:07 PM PDT 24
Finished Jul 18 06:02:24 PM PDT 24
Peak memory 219420 kb
Host smart-bbc37f7e-720c-4bad-b0b3-44929f58bffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236367362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3236367362
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1968608117
Short name T113
Test name
Test status
Simulation time 13682688500 ps
CPU time 28.4 seconds
Started Jul 18 06:01:33 PM PDT 24
Finished Jul 18 06:02:12 PM PDT 24
Peak memory 217800 kb
Host smart-73724b90-9f87-4e3d-b3c1-89cde0f00ef9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1968608117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1968608117
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.552318425
Short name T296
Test name
Test status
Simulation time 6616284228 ps
CPU time 70.98 seconds
Started Jul 18 06:01:18 PM PDT 24
Finished Jul 18 06:02:40 PM PDT 24
Peak memory 216824 kb
Host smart-2e4ad4a3-817c-4c6f-a020-6378956831e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552318425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.552318425
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2361683733
Short name T17
Test name
Test status
Simulation time 43089542198 ps
CPU time 94.36 seconds
Started Jul 18 06:01:14 PM PDT 24
Finished Jul 18 06:03:01 PM PDT 24
Peak memory 219696 kb
Host smart-37625e2e-bcb4-4ab3-8ae8-35d01882c2f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361683733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2361683733
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.997433832
Short name T253
Test name
Test status
Simulation time 13289988207 ps
CPU time 27.43 seconds
Started Jul 18 06:01:36 PM PDT 24
Finished Jul 18 06:02:18 PM PDT 24
Peak memory 213376 kb
Host smart-d489c287-a05d-468a-b795-deb8d7ef2897
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997433832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.997433832
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.904308554
Short name T193
Test name
Test status
Simulation time 156402995738 ps
CPU time 517.16 seconds
Started Jul 18 06:01:32 PM PDT 24
Finished Jul 18 06:10:19 PM PDT 24
Peak memory 237984 kb
Host smart-28e96f7b-8835-4d8c-8c66-a3c720ebcfed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904308554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.904308554
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.217542201
Short name T48
Test name
Test status
Simulation time 688768639 ps
CPU time 18.83 seconds
Started Jul 18 06:01:42 PM PDT 24
Finished Jul 18 06:02:16 PM PDT 24
Peak memory 219336 kb
Host smart-8c4f2a55-29ec-4721-9f7a-6c2be7fa70a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217542201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.217542201
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.51282660
Short name T355
Test name
Test status
Simulation time 12175642186 ps
CPU time 26.74 seconds
Started Jul 18 06:01:35 PM PDT 24
Finished Jul 18 06:02:14 PM PDT 24
Peak memory 219380 kb
Host smart-c19ca4ca-2395-465b-b2d9-9c5f4eb0dd2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=51282660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.51282660
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.978508540
Short name T79
Test name
Test status
Simulation time 15494761484 ps
CPU time 70.82 seconds
Started Jul 18 06:01:31 PM PDT 24
Finished Jul 18 06:02:52 PM PDT 24
Peak memory 216692 kb
Host smart-f7a6aad7-8850-4354-a325-1431a41bd389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978508540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.978508540
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.948174608
Short name T133
Test name
Test status
Simulation time 3462158866 ps
CPU time 52.92 seconds
Started Jul 18 06:01:30 PM PDT 24
Finished Jul 18 06:02:33 PM PDT 24
Peak memory 219688 kb
Host smart-f27fa984-2776-4d9a-abc0-ff6366e1cbb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948174608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.948174608
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2281970342
Short name T134
Test name
Test status
Simulation time 40953477052 ps
CPU time 27.89 seconds
Started Jul 18 06:01:44 PM PDT 24
Finished Jul 18 06:02:27 PM PDT 24
Peak memory 213340 kb
Host smart-ad98af9a-d92a-4f9c-b8b0-4bb662e43d5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281970342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2281970342
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3888036394
Short name T166
Test name
Test status
Simulation time 177764321678 ps
CPU time 574.72 seconds
Started Jul 18 06:01:31 PM PDT 24
Finished Jul 18 06:11:16 PM PDT 24
Peak memory 239364 kb
Host smart-c142addb-b13e-425d-a1b6-2141115ef5d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888036394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3888036394
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2254742805
Short name T125
Test name
Test status
Simulation time 8509366370 ps
CPU time 32.91 seconds
Started Jul 18 06:01:46 PM PDT 24
Finished Jul 18 06:02:34 PM PDT 24
Peak memory 215884 kb
Host smart-81fbbbcd-9280-4975-b2a4-dd9555f72923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254742805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2254742805
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2192217987
Short name T265
Test name
Test status
Simulation time 16477513028 ps
CPU time 20.82 seconds
Started Jul 18 06:01:41 PM PDT 24
Finished Jul 18 06:02:17 PM PDT 24
Peak memory 212068 kb
Host smart-c2c4729f-ad72-4e2a-a67b-3e644afb10b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2192217987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2192217987
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1841762301
Short name T31
Test name
Test status
Simulation time 2851361923 ps
CPU time 20.28 seconds
Started Jul 18 06:01:47 PM PDT 24
Finished Jul 18 06:02:22 PM PDT 24
Peak memory 217144 kb
Host smart-72f54aee-6673-487f-8538-ebf40588ed79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841762301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1841762301
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1251479745
Short name T282
Test name
Test status
Simulation time 2951796632 ps
CPU time 44.14 seconds
Started Jul 18 06:01:46 PM PDT 24
Finished Jul 18 06:02:45 PM PDT 24
Peak memory 219424 kb
Host smart-7350d1fa-b502-428c-bf41-d16de9a03ee9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251479745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1251479745
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1681940819
Short name T180
Test name
Test status
Simulation time 688139814 ps
CPU time 8.2 seconds
Started Jul 18 06:01:37 PM PDT 24
Finished Jul 18 06:01:59 PM PDT 24
Peak memory 217136 kb
Host smart-ff6ba71c-0c1e-403e-b495-5da5a1e2985e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681940819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1681940819
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1335553006
Short name T42
Test name
Test status
Simulation time 3598675872 ps
CPU time 246.72 seconds
Started Jul 18 06:01:46 PM PDT 24
Finished Jul 18 06:06:07 PM PDT 24
Peak memory 237548 kb
Host smart-1c9d3255-e48b-4d67-bb1f-b59bbf491e6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335553006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1335553006
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2664729210
Short name T339
Test name
Test status
Simulation time 1130278410 ps
CPU time 25.35 seconds
Started Jul 18 06:01:35 PM PDT 24
Finished Jul 18 06:02:13 PM PDT 24
Peak memory 218672 kb
Host smart-bc422df1-33d6-45ad-86e1-7ab754eb7903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664729210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2664729210
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3788044415
Short name T201
Test name
Test status
Simulation time 2607259828 ps
CPU time 24.69 seconds
Started Jul 18 06:01:39 PM PDT 24
Finished Jul 18 06:02:19 PM PDT 24
Peak memory 219352 kb
Host smart-c83b5dee-58ae-491e-b907-d2bea7e0a83f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3788044415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3788044415
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.4184241926
Short name T276
Test name
Test status
Simulation time 2290072720 ps
CPU time 19.46 seconds
Started Jul 18 06:01:32 PM PDT 24
Finished Jul 18 06:02:01 PM PDT 24
Peak memory 216088 kb
Host smart-95327115-ad57-4f0f-80d8-50dcca9f2071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184241926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.4184241926
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2187429141
Short name T232
Test name
Test status
Simulation time 9560440135 ps
CPU time 104.2 seconds
Started Jul 18 06:01:35 PM PDT 24
Finished Jul 18 06:03:31 PM PDT 24
Peak memory 220340 kb
Host smart-8a680d63-488f-45e0-8488-0beb7f469e63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187429141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2187429141
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1586705573
Short name T256
Test name
Test status
Simulation time 770951933 ps
CPU time 14.03 seconds
Started Jul 18 06:01:42 PM PDT 24
Finished Jul 18 06:02:11 PM PDT 24
Peak memory 213280 kb
Host smart-7bdff374-d7fb-4ea0-a175-f4d17e1f2a3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586705573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1586705573
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.329486773
Short name T127
Test name
Test status
Simulation time 347512387727 ps
CPU time 496.25 seconds
Started Jul 18 06:01:38 PM PDT 24
Finished Jul 18 06:10:09 PM PDT 24
Peak memory 236728 kb
Host smart-589e0b2f-59ac-48c0-bee2-c493b4222d46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329486773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.329486773
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.926338266
Short name T226
Test name
Test status
Simulation time 19790573420 ps
CPU time 47.6 seconds
Started Jul 18 06:01:36 PM PDT 24
Finished Jul 18 06:02:37 PM PDT 24
Peak memory 219404 kb
Host smart-1c94eb53-5572-48e3-9715-9fb3ffadf042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926338266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.926338266
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2242883189
Short name T182
Test name
Test status
Simulation time 3944760654 ps
CPU time 32.09 seconds
Started Jul 18 06:01:46 PM PDT 24
Finished Jul 18 06:02:33 PM PDT 24
Peak memory 219420 kb
Host smart-d40469e5-d00a-441f-93cc-cc6da8b28de0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2242883189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2242883189
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.2042010837
Short name T185
Test name
Test status
Simulation time 5484174350 ps
CPU time 62.83 seconds
Started Jul 18 06:01:29 PM PDT 24
Finished Jul 18 06:02:41 PM PDT 24
Peak memory 216824 kb
Host smart-b71b22b0-f664-4b88-bba6-31eda73e6d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042010837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2042010837
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3921816256
Short name T316
Test name
Test status
Simulation time 415702249 ps
CPU time 18.57 seconds
Started Jul 18 06:01:35 PM PDT 24
Finished Jul 18 06:02:06 PM PDT 24
Peak memory 219376 kb
Host smart-d5ec619e-76db-4a42-b964-8d3074feecf8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921816256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3921816256
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3768243398
Short name T257
Test name
Test status
Simulation time 591305515 ps
CPU time 8.43 seconds
Started Jul 18 06:01:45 PM PDT 24
Finished Jul 18 06:02:07 PM PDT 24
Peak memory 217180 kb
Host smart-15b45326-4123-419b-9a86-f4aa138d6bfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768243398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3768243398
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3860296985
Short name T186
Test name
Test status
Simulation time 5670505981 ps
CPU time 217.95 seconds
Started Jul 18 06:01:30 PM PDT 24
Finished Jul 18 06:05:18 PM PDT 24
Peak memory 240584 kb
Host smart-cf4e741d-4907-4887-b281-f784b0b36cd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860296985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3860296985
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2420379171
Short name T140
Test name
Test status
Simulation time 7978736848 ps
CPU time 67.87 seconds
Started Jul 18 06:01:30 PM PDT 24
Finished Jul 18 06:02:47 PM PDT 24
Peak memory 219356 kb
Host smart-ca055f95-a3f0-46bf-a2aa-355e04508958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420379171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2420379171
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1042884764
Short name T178
Test name
Test status
Simulation time 1886918661 ps
CPU time 21.37 seconds
Started Jul 18 06:01:47 PM PDT 24
Finished Jul 18 06:02:22 PM PDT 24
Peak memory 217720 kb
Host smart-8b0a6593-4d34-4388-b413-f8548a336dcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1042884764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1042884764
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2286368651
Short name T286
Test name
Test status
Simulation time 23238598620 ps
CPU time 54.34 seconds
Started Jul 18 06:01:32 PM PDT 24
Finished Jul 18 06:02:36 PM PDT 24
Peak memory 216752 kb
Host smart-94491ecb-cfca-49b9-9342-6f03b98ae808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286368651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2286368651
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.317269447
Short name T272
Test name
Test status
Simulation time 6060860938 ps
CPU time 34.76 seconds
Started Jul 18 06:01:35 PM PDT 24
Finished Jul 18 06:02:22 PM PDT 24
Peak memory 219296 kb
Host smart-d86a84ab-1af3-435f-bd17-829d064f1ddc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317269447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.317269447
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.4009686656
Short name T66
Test name
Test status
Simulation time 7140226705 ps
CPU time 18.87 seconds
Started Jul 18 06:01:44 PM PDT 24
Finished Jul 18 06:02:17 PM PDT 24
Peak memory 217504 kb
Host smart-78a483db-8f20-412d-af2f-6e730a787eda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009686656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.4009686656
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1606834868
Short name T157
Test name
Test status
Simulation time 70295489599 ps
CPU time 451.93 seconds
Started Jul 18 06:01:44 PM PDT 24
Finished Jul 18 06:09:30 PM PDT 24
Peak memory 239044 kb
Host smart-42e23d0c-ac34-47e3-afe0-62ca4e3a7260
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606834868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1606834868
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1011839596
Short name T128
Test name
Test status
Simulation time 26561512314 ps
CPU time 57.38 seconds
Started Jul 18 06:01:48 PM PDT 24
Finished Jul 18 06:02:59 PM PDT 24
Peak memory 219388 kb
Host smart-f304c166-08a0-497b-af24-657f63276a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011839596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1011839596
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2638965138
Short name T6
Test name
Test status
Simulation time 45036710757 ps
CPU time 26.07 seconds
Started Jul 18 06:01:35 PM PDT 24
Finished Jul 18 06:02:15 PM PDT 24
Peak memory 219424 kb
Host smart-828bc96e-e904-4068-8649-c537cf7d8404
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2638965138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2638965138
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3678074922
Short name T141
Test name
Test status
Simulation time 26405923095 ps
CPU time 53.79 seconds
Started Jul 18 06:01:46 PM PDT 24
Finished Jul 18 06:02:54 PM PDT 24
Peak memory 217004 kb
Host smart-e94c9fe3-a90b-44be-ad84-0a159d0f5d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678074922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3678074922
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1969530926
Short name T137
Test name
Test status
Simulation time 21521125672 ps
CPU time 206.09 seconds
Started Jul 18 06:01:41 PM PDT 24
Finished Jul 18 06:05:22 PM PDT 24
Peak memory 220188 kb
Host smart-24d11298-2704-4e33-a1d4-3411ddbab4e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969530926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1969530926
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2495798741
Short name T208
Test name
Test status
Simulation time 20210702239 ps
CPU time 21.83 seconds
Started Jul 18 06:01:41 PM PDT 24
Finished Jul 18 06:02:18 PM PDT 24
Peak memory 217700 kb
Host smart-2d3a3690-957a-4f45-9ee0-8293550d9887
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495798741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2495798741
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.182249465
Short name T334
Test name
Test status
Simulation time 7603473946 ps
CPU time 61.1 seconds
Started Jul 18 06:01:37 PM PDT 24
Finished Jul 18 06:02:52 PM PDT 24
Peak memory 219384 kb
Host smart-096f429d-55ff-4c78-be33-0a4fbcaa6949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182249465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.182249465
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1677762017
Short name T249
Test name
Test status
Simulation time 9960131615 ps
CPU time 24.84 seconds
Started Jul 18 06:01:35 PM PDT 24
Finished Jul 18 06:02:13 PM PDT 24
Peak memory 211948 kb
Host smart-d4082d30-31e4-42b6-bb66-34ce958de3a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1677762017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1677762017
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.19786941
Short name T224
Test name
Test status
Simulation time 30113187377 ps
CPU time 61.02 seconds
Started Jul 18 06:01:32 PM PDT 24
Finished Jul 18 06:02:44 PM PDT 24
Peak memory 216500 kb
Host smart-8604fd9f-7299-47c0-8955-bb87e4393b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19786941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.19786941
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3886471971
Short name T20
Test name
Test status
Simulation time 3459418473 ps
CPU time 30.23 seconds
Started Jul 18 06:01:39 PM PDT 24
Finished Jul 18 06:02:24 PM PDT 24
Peak memory 214704 kb
Host smart-61ae0fa0-30e9-4fbd-99b6-038b57ef43eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886471971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3886471971
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2543950733
Short name T290
Test name
Test status
Simulation time 124122422288 ps
CPU time 7397.41 seconds
Started Jul 18 06:01:43 PM PDT 24
Finished Jul 18 08:05:16 PM PDT 24
Peak memory 252192 kb
Host smart-02827114-9b2d-4cba-94fd-7fa71031b6cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543950733 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.2543950733
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.907457376
Short name T352
Test name
Test status
Simulation time 10234873523 ps
CPU time 22.93 seconds
Started Jul 18 06:01:01 PM PDT 24
Finished Jul 18 06:01:31 PM PDT 24
Peak memory 217536 kb
Host smart-442f4203-f7ac-4488-82cb-96117a967b20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907457376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.907457376
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3907570535
Short name T246
Test name
Test status
Simulation time 333821972 ps
CPU time 18.97 seconds
Started Jul 18 06:01:06 PM PDT 24
Finished Jul 18 06:01:38 PM PDT 24
Peak memory 219356 kb
Host smart-0411ad67-5c42-4a37-8224-ee68e850a1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907570535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3907570535
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2198535969
Short name T96
Test name
Test status
Simulation time 23192208851 ps
CPU time 33.07 seconds
Started Jul 18 06:01:06 PM PDT 24
Finished Jul 18 06:01:51 PM PDT 24
Peak memory 219412 kb
Host smart-42c46c4a-57ba-4065-a40a-ef62be83b8be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2198535969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2198535969
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2390743143
Short name T243
Test name
Test status
Simulation time 717431265 ps
CPU time 19.95 seconds
Started Jul 18 06:01:01 PM PDT 24
Finished Jul 18 06:01:30 PM PDT 24
Peak memory 216296 kb
Host smart-ccb64291-f716-4282-81cb-d29e56b72691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390743143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2390743143
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.4150627387
Short name T153
Test name
Test status
Simulation time 94807572599 ps
CPU time 244.74 seconds
Started Jul 18 06:00:51 PM PDT 24
Finished Jul 18 06:04:59 PM PDT 24
Peak memory 222204 kb
Host smart-7772cf03-249e-45b2-a4ac-73143ae6eb3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150627387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.4150627387
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3677288059
Short name T187
Test name
Test status
Simulation time 3295655936 ps
CPU time 11.74 seconds
Started Jul 18 06:01:06 PM PDT 24
Finished Jul 18 06:01:30 PM PDT 24
Peak memory 217148 kb
Host smart-bdb1610c-7341-46c6-b1e3-9af98eafee81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677288059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3677288059
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1230899477
Short name T228
Test name
Test status
Simulation time 2006078702 ps
CPU time 32.02 seconds
Started Jul 18 06:01:06 PM PDT 24
Finished Jul 18 06:01:50 PM PDT 24
Peak memory 219356 kb
Host smart-1dfc79a7-e433-4903-9665-eb8348e58e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230899477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1230899477
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.109361238
Short name T171
Test name
Test status
Simulation time 2783411994 ps
CPU time 26.63 seconds
Started Jul 18 06:00:51 PM PDT 24
Finished Jul 18 06:01:21 PM PDT 24
Peak memory 217900 kb
Host smart-5885942c-f9c5-44bb-bc23-5125e0308c90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=109361238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.109361238
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3195729198
Short name T331
Test name
Test status
Simulation time 30075043474 ps
CPU time 63.45 seconds
Started Jul 18 06:00:45 PM PDT 24
Finished Jul 18 06:01:54 PM PDT 24
Peak memory 216980 kb
Host smart-1ae8ef39-59b5-4df9-9cec-2eae8fb5a9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195729198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3195729198
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2622387488
Short name T95
Test name
Test status
Simulation time 4947152314 ps
CPU time 72.39 seconds
Started Jul 18 06:00:42 PM PDT 24
Finished Jul 18 06:01:57 PM PDT 24
Peak memory 219500 kb
Host smart-02369f90-285f-4b15-8bac-ff8a71fecddd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622387488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2622387488
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3491058120
Short name T293
Test name
Test status
Simulation time 26837107819 ps
CPU time 20.11 seconds
Started Jul 18 06:00:46 PM PDT 24
Finished Jul 18 06:01:11 PM PDT 24
Peak memory 217492 kb
Host smart-73cd572d-160a-4816-8e3f-9ac092d48c68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491058120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3491058120
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2598330255
Short name T136
Test name
Test status
Simulation time 34666697615 ps
CPU time 373.87 seconds
Started Jul 18 06:00:52 PM PDT 24
Finished Jul 18 06:07:12 PM PDT 24
Peak memory 236936 kb
Host smart-bc11e032-b3e6-42f4-b6f7-15ae3321f19a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598330255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2598330255
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.4280000457
Short name T143
Test name
Test status
Simulation time 4453980928 ps
CPU time 33.53 seconds
Started Jul 18 06:01:03 PM PDT 24
Finished Jul 18 06:01:47 PM PDT 24
Peak memory 215748 kb
Host smart-9e12c2ae-af61-4f3e-a9eb-d4f523d61ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280000457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.4280000457
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.712465786
Short name T247
Test name
Test status
Simulation time 700367537 ps
CPU time 10.23 seconds
Started Jul 18 06:00:59 PM PDT 24
Finished Jul 18 06:01:16 PM PDT 24
Peak memory 219336 kb
Host smart-031cb1ac-fdc9-40ca-a62b-019604a7d503
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=712465786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.712465786
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.4066904061
Short name T214
Test name
Test status
Simulation time 12862538043 ps
CPU time 33.44 seconds
Started Jul 18 06:01:08 PM PDT 24
Finished Jul 18 06:01:54 PM PDT 24
Peak memory 216820 kb
Host smart-247db63b-35cf-419e-9e32-7a8b304c0017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066904061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.4066904061
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3662526455
Short name T244
Test name
Test status
Simulation time 12319350875 ps
CPU time 42.06 seconds
Started Jul 18 06:01:03 PM PDT 24
Finished Jul 18 06:01:55 PM PDT 24
Peak memory 218520 kb
Host smart-eff82f74-0c20-4f54-9390-97be871f9de7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662526455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3662526455
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1147971681
Short name T203
Test name
Test status
Simulation time 4738460163 ps
CPU time 23.24 seconds
Started Jul 18 06:01:02 PM PDT 24
Finished Jul 18 06:01:33 PM PDT 24
Peak memory 217636 kb
Host smart-091857ec-24d8-405d-b3be-500aa77691af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147971681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1147971681
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.107695877
Short name T259
Test name
Test status
Simulation time 74695885034 ps
CPU time 499.84 seconds
Started Jul 18 06:00:57 PM PDT 24
Finished Jul 18 06:09:24 PM PDT 24
Peak memory 239320 kb
Host smart-025735d0-dac3-4770-be35-4adc06fcff48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107695877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.107695877
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2544987431
Short name T163
Test name
Test status
Simulation time 1011218097 ps
CPU time 22.21 seconds
Started Jul 18 06:00:58 PM PDT 24
Finished Jul 18 06:01:28 PM PDT 24
Peak memory 219396 kb
Host smart-a2bf8846-4b8c-4f96-9d4b-8cf595d5c924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544987431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2544987431
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1974468509
Short name T112
Test name
Test status
Simulation time 8551488094 ps
CPU time 32.68 seconds
Started Jul 18 06:00:55 PM PDT 24
Finished Jul 18 06:01:34 PM PDT 24
Peak memory 219396 kb
Host smart-3cc71606-cca3-45ab-846c-f9cae277121e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1974468509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1974468509
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1835574345
Short name T194
Test name
Test status
Simulation time 7756845706 ps
CPU time 60.77 seconds
Started Jul 18 06:01:03 PM PDT 24
Finished Jul 18 06:02:14 PM PDT 24
Peak memory 216924 kb
Host smart-1664d9a3-a5a6-493a-b907-1ec95452b092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835574345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1835574345
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1383623198
Short name T266
Test name
Test status
Simulation time 906243861 ps
CPU time 58.17 seconds
Started Jul 18 06:01:03 PM PDT 24
Finished Jul 18 06:02:11 PM PDT 24
Peak memory 219356 kb
Host smart-cef8688e-1eda-46ae-b319-3875ca0b7e03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383623198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1383623198
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.167772331
Short name T325
Test name
Test status
Simulation time 85200665780 ps
CPU time 913.43 seconds
Started Jul 18 06:01:08 PM PDT 24
Finished Jul 18 06:16:35 PM PDT 24
Peak memory 235836 kb
Host smart-17099f2a-b8f8-4267-9c24-edda673fe9c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167772331 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.167772331
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3268329079
Short name T346
Test name
Test status
Simulation time 1748231227 ps
CPU time 18.49 seconds
Started Jul 18 06:01:09 PM PDT 24
Finished Jul 18 06:01:41 PM PDT 24
Peak memory 213276 kb
Host smart-3140db2f-b10c-4f78-bf88-8593b908849f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268329079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3268329079
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.361102087
Short name T30
Test name
Test status
Simulation time 20964155758 ps
CPU time 221.92 seconds
Started Jul 18 06:01:09 PM PDT 24
Finished Jul 18 06:05:04 PM PDT 24
Peak memory 237040 kb
Host smart-cb4d482c-8f20-44e2-88ba-e7eb3b0e95f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361102087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.361102087
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1362301274
Short name T211
Test name
Test status
Simulation time 31863093204 ps
CPU time 55.95 seconds
Started Jul 18 06:01:07 PM PDT 24
Finished Jul 18 06:02:15 PM PDT 24
Peak memory 219464 kb
Host smart-90a59619-a618-4003-a96d-f8b72563ab85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362301274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1362301274
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.381338713
Short name T142
Test name
Test status
Simulation time 364335543 ps
CPU time 10.63 seconds
Started Jul 18 06:01:00 PM PDT 24
Finished Jul 18 06:01:18 PM PDT 24
Peak memory 219380 kb
Host smart-aa28f8c3-ccdf-4fb4-8721-b41453cb78e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=381338713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.381338713
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3801226021
Short name T300
Test name
Test status
Simulation time 21906557793 ps
CPU time 66.91 seconds
Started Jul 18 06:00:56 PM PDT 24
Finished Jul 18 06:02:09 PM PDT 24
Peak memory 217372 kb
Host smart-82f36c82-ce95-49e5-965e-46d8ecaec644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801226021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3801226021
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3990326138
Short name T181
Test name
Test status
Simulation time 10275600131 ps
CPU time 23.05 seconds
Started Jul 18 06:01:08 PM PDT 24
Finished Jul 18 06:01:44 PM PDT 24
Peak memory 216728 kb
Host smart-ed1df081-b187-43eb-a9c4-0244c651c13f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990326138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3990326138
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.537077043
Short name T53
Test name
Test status
Simulation time 7136364547 ps
CPU time 292.47 seconds
Started Jul 18 06:01:13 PM PDT 24
Finished Jul 18 06:06:18 PM PDT 24
Peak memory 228812 kb
Host smart-f9235dd4-8fae-44fe-a4c0-7a6fd0610def
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537077043 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.537077043
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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