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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.26 96.89 91.99 97.68 100.00 98.62 97.30 98.37


Total test records in report: 461
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T301 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2389804846 Jul 19 04:40:27 PM PDT 24 Jul 19 04:41:02 PM PDT 24 4214650012 ps
T302 /workspace/coverage/default/3.rom_ctrl_smoke.2280120833 Jul 19 04:40:25 PM PDT 24 Jul 19 04:41:07 PM PDT 24 16490432816 ps
T303 /workspace/coverage/default/28.rom_ctrl_alert_test.3513820888 Jul 19 04:40:56 PM PDT 24 Jul 19 04:41:25 PM PDT 24 9584962202 ps
T304 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2589855770 Jul 19 04:40:39 PM PDT 24 Jul 19 04:40:53 PM PDT 24 707819966 ps
T305 /workspace/coverage/default/16.rom_ctrl_alert_test.1967100633 Jul 19 04:40:43 PM PDT 24 Jul 19 04:41:17 PM PDT 24 3877422797 ps
T306 /workspace/coverage/default/18.rom_ctrl_alert_test.3514105928 Jul 19 04:40:42 PM PDT 24 Jul 19 04:41:08 PM PDT 24 2816428757 ps
T307 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.4011534198 Jul 19 04:40:51 PM PDT 24 Jul 19 04:41:20 PM PDT 24 935624643 ps
T308 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.191134249 Jul 19 04:40:50 PM PDT 24 Jul 19 04:44:33 PM PDT 24 11364845200 ps
T309 /workspace/coverage/default/5.rom_ctrl_stress_all.1806107868 Jul 19 04:40:32 PM PDT 24 Jul 19 04:42:20 PM PDT 24 13517129718 ps
T310 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.139845678 Jul 19 04:41:06 PM PDT 24 Jul 19 04:41:36 PM PDT 24 3041286685 ps
T311 /workspace/coverage/default/13.rom_ctrl_smoke.3711670489 Jul 19 04:40:42 PM PDT 24 Jul 19 04:41:40 PM PDT 24 25302252944 ps
T312 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1541473922 Jul 19 04:40:49 PM PDT 24 Jul 19 04:41:07 PM PDT 24 696986508 ps
T313 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2403431528 Jul 19 04:41:02 PM PDT 24 Jul 19 04:41:42 PM PDT 24 15301337917 ps
T314 /workspace/coverage/default/39.rom_ctrl_smoke.725847228 Jul 19 04:41:03 PM PDT 24 Jul 19 04:42:09 PM PDT 24 6419976442 ps
T315 /workspace/coverage/default/11.rom_ctrl_stress_all.1068012456 Jul 19 04:40:33 PM PDT 24 Jul 19 04:41:11 PM PDT 24 5335997250 ps
T316 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3722010686 Jul 19 04:40:48 PM PDT 24 Jul 19 04:41:22 PM PDT 24 4168359903 ps
T317 /workspace/coverage/default/29.rom_ctrl_stress_all.190759150 Jul 19 04:40:50 PM PDT 24 Jul 19 04:41:45 PM PDT 24 8052963134 ps
T318 /workspace/coverage/default/6.rom_ctrl_stress_all.749843284 Jul 19 04:40:29 PM PDT 24 Jul 19 04:41:05 PM PDT 24 4037305260 ps
T319 /workspace/coverage/default/48.rom_ctrl_stress_all.1453130053 Jul 19 04:41:10 PM PDT 24 Jul 19 04:41:53 PM PDT 24 37830947056 ps
T320 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1252801896 Jul 19 04:41:02 PM PDT 24 Jul 19 04:41:30 PM PDT 24 2537090236 ps
T321 /workspace/coverage/default/45.rom_ctrl_alert_test.1595133130 Jul 19 04:41:07 PM PDT 24 Jul 19 04:41:28 PM PDT 24 345648511 ps
T322 /workspace/coverage/default/10.rom_ctrl_stress_all.3481979023 Jul 19 04:40:34 PM PDT 24 Jul 19 04:41:01 PM PDT 24 4918264310 ps
T323 /workspace/coverage/default/9.rom_ctrl_alert_test.124933517 Jul 19 04:40:32 PM PDT 24 Jul 19 04:41:05 PM PDT 24 8639496785 ps
T324 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2821622240 Jul 19 04:40:46 PM PDT 24 Jul 19 04:41:15 PM PDT 24 2905879140 ps
T325 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2491016658 Jul 19 04:41:06 PM PDT 24 Jul 19 04:41:51 PM PDT 24 4461207290 ps
T326 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.817553480 Jul 19 04:41:13 PM PDT 24 Jul 19 04:51:46 PM PDT 24 69217850891 ps
T327 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2628758650 Jul 19 04:40:43 PM PDT 24 Jul 19 04:44:11 PM PDT 24 5048929576 ps
T328 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.4051452844 Jul 19 04:40:46 PM PDT 24 Jul 19 04:41:52 PM PDT 24 7210745422 ps
T329 /workspace/coverage/default/30.rom_ctrl_stress_all.224209830 Jul 19 04:40:54 PM PDT 24 Jul 19 04:42:20 PM PDT 24 83769263844 ps
T330 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.4292322321 Jul 19 04:40:39 PM PDT 24 Jul 19 04:41:01 PM PDT 24 346433920 ps
T331 /workspace/coverage/default/28.rom_ctrl_stress_all.2599395771 Jul 19 04:40:53 PM PDT 24 Jul 19 04:42:46 PM PDT 24 36794371325 ps
T332 /workspace/coverage/default/24.rom_ctrl_smoke.1936758803 Jul 19 04:40:39 PM PDT 24 Jul 19 04:41:29 PM PDT 24 14445476156 ps
T333 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.119358782 Jul 19 04:40:47 PM PDT 24 Jul 19 04:41:09 PM PDT 24 847417002 ps
T334 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2949261789 Jul 19 04:40:59 PM PDT 24 Jul 19 04:41:22 PM PDT 24 3146086323 ps
T335 /workspace/coverage/default/5.rom_ctrl_alert_test.1073791263 Jul 19 04:40:30 PM PDT 24 Jul 19 04:41:03 PM PDT 24 37757305051 ps
T336 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1694948733 Jul 19 04:41:15 PM PDT 24 Jul 19 04:42:26 PM PDT 24 6499753169 ps
T337 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2296531909 Jul 19 04:40:39 PM PDT 24 Jul 19 04:40:53 PM PDT 24 697271061 ps
T338 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3401033203 Jul 19 04:40:46 PM PDT 24 Jul 19 04:41:21 PM PDT 24 2152555427 ps
T339 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2699151010 Jul 19 04:40:38 PM PDT 24 Jul 19 04:40:57 PM PDT 24 5738057934 ps
T340 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2338626585 Jul 19 04:41:10 PM PDT 24 Jul 19 04:42:34 PM PDT 24 8042882084 ps
T341 /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1187712318 Jul 19 04:40:35 PM PDT 24 Jul 19 06:18:38 PM PDT 24 161143454217 ps
T342 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1460882578 Jul 19 04:40:32 PM PDT 24 Jul 19 04:40:58 PM PDT 24 769638743 ps
T343 /workspace/coverage/default/6.rom_ctrl_alert_test.3051262897 Jul 19 04:40:36 PM PDT 24 Jul 19 04:41:08 PM PDT 24 36927110730 ps
T344 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.352795816 Jul 19 04:40:33 PM PDT 24 Jul 19 04:41:30 PM PDT 24 24389297071 ps
T345 /workspace/coverage/default/23.rom_ctrl_stress_all.1584738439 Jul 19 04:40:46 PM PDT 24 Jul 19 04:41:24 PM PDT 24 3127065181 ps
T346 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.4030851967 Jul 19 04:40:39 PM PDT 24 Jul 19 04:41:54 PM PDT 24 10398854104 ps
T347 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1209338745 Jul 19 04:40:43 PM PDT 24 Jul 19 04:41:49 PM PDT 24 16700455142 ps
T348 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3933275430 Jul 19 04:40:53 PM PDT 24 Jul 19 04:50:37 PM PDT 24 223765898987 ps
T349 /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.50619149 Jul 19 04:41:12 PM PDT 24 Jul 19 06:03:18 PM PDT 24 85075579143 ps
T350 /workspace/coverage/default/14.rom_ctrl_smoke.637285928 Jul 19 04:40:40 PM PDT 24 Jul 19 04:42:00 PM PDT 24 7979820618 ps
T351 /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.2780496247 Jul 19 04:41:00 PM PDT 24 Jul 19 05:16:22 PM PDT 24 547780164534 ps
T352 /workspace/coverage/default/43.rom_ctrl_alert_test.2129774051 Jul 19 04:40:50 PM PDT 24 Jul 19 04:41:14 PM PDT 24 8147203493 ps
T353 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2645199296 Jul 19 04:41:10 PM PDT 24 Jul 19 04:41:33 PM PDT 24 351396935 ps
T354 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.4206302093 Jul 19 04:40:42 PM PDT 24 Jul 19 04:40:56 PM PDT 24 365770010 ps
T355 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1377052696 Jul 19 04:41:06 PM PDT 24 Jul 19 04:48:47 PM PDT 24 41004906086 ps
T356 /workspace/coverage/default/49.rom_ctrl_stress_all.4281995715 Jul 19 04:41:05 PM PDT 24 Jul 19 04:43:09 PM PDT 24 48420744536 ps
T26 /workspace/coverage/default/1.rom_ctrl_sec_cm.1957510643 Jul 19 04:40:31 PM PDT 24 Jul 19 04:44:40 PM PDT 24 16137285411 ps
T357 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.877940234 Jul 19 04:40:32 PM PDT 24 Jul 19 04:41:41 PM PDT 24 61967354908 ps
T358 /workspace/coverage/default/45.rom_ctrl_stress_all.713269809 Jul 19 04:41:16 PM PDT 24 Jul 19 04:42:17 PM PDT 24 591716399 ps
T359 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.65425003 Jul 19 04:41:15 PM PDT 24 Jul 19 04:50:17 PM PDT 24 241787186592 ps
T360 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2187681385 Jul 19 04:40:31 PM PDT 24 Jul 19 04:41:18 PM PDT 24 17758776770 ps
T361 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2733965187 Jul 19 04:40:54 PM PDT 24 Jul 19 04:45:44 PM PDT 24 62698635215 ps
T362 /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.350443492 Jul 19 04:40:51 PM PDT 24 Jul 19 05:04:25 PM PDT 24 80641908756 ps
T363 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2522744022 Jul 19 04:40:52 PM PDT 24 Jul 19 04:41:15 PM PDT 24 354188291 ps
T364 /workspace/coverage/default/1.rom_ctrl_smoke.370300299 Jul 19 04:40:28 PM PDT 24 Jul 19 04:41:06 PM PDT 24 2752200118 ps
T365 /workspace/coverage/default/16.rom_ctrl_smoke.3122088277 Jul 19 04:40:51 PM PDT 24 Jul 19 04:42:17 PM PDT 24 60607974561 ps
T366 /workspace/coverage/default/46.rom_ctrl_smoke.350447675 Jul 19 04:41:13 PM PDT 24 Jul 19 04:42:20 PM PDT 24 9922891320 ps
T367 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3410695362 Jul 19 04:29:46 PM PDT 24 Jul 19 04:30:03 PM PDT 24 170920361 ps
T56 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3693569201 Jul 19 04:29:41 PM PDT 24 Jul 19 04:30:02 PM PDT 24 7236861889 ps
T57 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2773475776 Jul 19 04:29:47 PM PDT 24 Jul 19 04:30:30 PM PDT 24 691139450 ps
T58 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2188632966 Jul 19 04:29:32 PM PDT 24 Jul 19 04:30:05 PM PDT 24 16176633280 ps
T63 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.600862397 Jul 19 04:29:33 PM PDT 24 Jul 19 04:30:33 PM PDT 24 1081190009 ps
T368 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2547040297 Jul 19 04:29:32 PM PDT 24 Jul 19 04:29:58 PM PDT 24 9082877647 ps
T93 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1542283975 Jul 19 04:29:42 PM PDT 24 Jul 19 04:29:59 PM PDT 24 1268590993 ps
T64 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2805148609 Jul 19 04:29:42 PM PDT 24 Jul 19 04:30:03 PM PDT 24 1674242989 ps
T65 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.342968453 Jul 19 04:29:44 PM PDT 24 Jul 19 04:30:00 PM PDT 24 357485574 ps
T369 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2183552990 Jul 19 04:29:43 PM PDT 24 Jul 19 04:30:17 PM PDT 24 14155368872 ps
T66 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1716576147 Jul 19 04:29:40 PM PDT 24 Jul 19 04:29:50 PM PDT 24 353091148 ps
T53 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2271853001 Jul 19 04:29:47 PM PDT 24 Jul 19 04:32:43 PM PDT 24 16746696732 ps
T54 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4084623735 Jul 19 04:29:41 PM PDT 24 Jul 19 04:31:00 PM PDT 24 1044166318 ps
T98 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4079205967 Jul 19 04:29:29 PM PDT 24 Jul 19 04:30:02 PM PDT 24 8039556877 ps
T370 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4072592813 Jul 19 04:29:42 PM PDT 24 Jul 19 04:30:07 PM PDT 24 2558845146 ps
T94 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3571861571 Jul 19 04:29:33 PM PDT 24 Jul 19 04:30:02 PM PDT 24 5874307998 ps
T371 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1562111547 Jul 19 04:29:43 PM PDT 24 Jul 19 04:30:09 PM PDT 24 5259666653 ps
T372 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1293349648 Jul 19 04:29:39 PM PDT 24 Jul 19 04:29:59 PM PDT 24 4218719705 ps
T55 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.121668557 Jul 19 04:29:42 PM PDT 24 Jul 19 04:31:17 PM PDT 24 7522843215 ps
T95 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3235555620 Jul 19 04:29:33 PM PDT 24 Jul 19 04:30:06 PM PDT 24 13060437783 ps
T373 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3673169295 Jul 19 04:29:33 PM PDT 24 Jul 19 04:30:13 PM PDT 24 4316230129 ps
T101 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.927149152 Jul 19 04:29:44 PM PDT 24 Jul 19 04:31:11 PM PDT 24 1067212628 ps
T67 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.4084965758 Jul 19 04:29:32 PM PDT 24 Jul 19 04:29:57 PM PDT 24 4799567110 ps
T374 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4256210733 Jul 19 04:29:31 PM PDT 24 Jul 19 04:29:40 PM PDT 24 1830415769 ps
T96 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2490421977 Jul 19 04:29:48 PM PDT 24 Jul 19 04:30:06 PM PDT 24 1399936359 ps
T375 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2679412695 Jul 19 04:29:32 PM PDT 24 Jul 19 04:29:47 PM PDT 24 727375747 ps
T376 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1665522604 Jul 19 04:29:34 PM PDT 24 Jul 19 04:29:46 PM PDT 24 308349894 ps
T377 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2163429266 Jul 19 04:29:32 PM PDT 24 Jul 19 04:29:44 PM PDT 24 687190620 ps
T378 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.964673392 Jul 19 04:29:32 PM PDT 24 Jul 19 04:30:04 PM PDT 24 13303496020 ps
T379 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1723618033 Jul 19 04:29:47 PM PDT 24 Jul 19 04:30:18 PM PDT 24 9289128475 ps
T380 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3113719928 Jul 19 04:29:35 PM PDT 24 Jul 19 04:29:58 PM PDT 24 5694719962 ps
T381 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3352351323 Jul 19 04:29:31 PM PDT 24 Jul 19 04:29:47 PM PDT 24 895780598 ps
T68 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.688859786 Jul 19 04:29:43 PM PDT 24 Jul 19 04:31:08 PM PDT 24 7655253950 ps
T382 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.4041380666 Jul 19 04:29:46 PM PDT 24 Jul 19 04:30:03 PM PDT 24 170809981 ps
T383 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3077051842 Jul 19 04:29:44 PM PDT 24 Jul 19 04:30:11 PM PDT 24 8557234134 ps
T384 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2362640225 Jul 19 04:29:41 PM PDT 24 Jul 19 04:30:16 PM PDT 24 24752380480 ps
T97 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2437836077 Jul 19 04:29:41 PM PDT 24 Jul 19 04:29:51 PM PDT 24 425151156 ps
T385 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2980332074 Jul 19 04:29:31 PM PDT 24 Jul 19 04:30:03 PM PDT 24 12103969141 ps
T386 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.293754309 Jul 19 04:29:31 PM PDT 24 Jul 19 04:29:57 PM PDT 24 12016062434 ps
T387 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4293020197 Jul 19 04:29:46 PM PDT 24 Jul 19 04:30:15 PM PDT 24 7055845648 ps
T102 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.483752524 Jul 19 04:29:34 PM PDT 24 Jul 19 04:32:16 PM PDT 24 1243531120 ps
T69 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.112026718 Jul 19 04:29:40 PM PDT 24 Jul 19 04:30:04 PM PDT 24 2043914885 ps
T103 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3564076941 Jul 19 04:29:45 PM PDT 24 Jul 19 04:32:36 PM PDT 24 15518760151 ps
T388 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1422067177 Jul 19 04:29:43 PM PDT 24 Jul 19 04:30:15 PM PDT 24 12478271482 ps
T389 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2209806962 Jul 19 04:29:37 PM PDT 24 Jul 19 04:30:07 PM PDT 24 3789404835 ps
T106 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.869753171 Jul 19 04:29:34 PM PDT 24 Jul 19 04:32:25 PM PDT 24 3328244269 ps
T390 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2466992460 Jul 19 04:29:31 PM PDT 24 Jul 19 04:29:43 PM PDT 24 2294789347 ps
T70 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3935848579 Jul 19 04:29:34 PM PDT 24 Jul 19 04:30:10 PM PDT 24 24623545527 ps
T71 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.79302652 Jul 19 04:29:47 PM PDT 24 Jul 19 04:30:15 PM PDT 24 9170839791 ps
T72 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1741437818 Jul 19 04:29:34 PM PDT 24 Jul 19 04:31:00 PM PDT 24 37445044498 ps
T391 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3553024110 Jul 19 04:29:45 PM PDT 24 Jul 19 04:30:04 PM PDT 24 805981576 ps
T110 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3668949504 Jul 19 04:31:38 PM PDT 24 Jul 19 04:34:28 PM PDT 24 2115027038 ps
T392 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2008763338 Jul 19 04:29:35 PM PDT 24 Jul 19 04:29:49 PM PDT 24 332832749 ps
T78 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3315229618 Jul 19 04:29:41 PM PDT 24 Jul 19 04:32:02 PM PDT 24 14236091622 ps
T393 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2168964506 Jul 19 04:29:31 PM PDT 24 Jul 19 04:29:57 PM PDT 24 5834646606 ps
T79 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.868337344 Jul 19 04:29:44 PM PDT 24 Jul 19 04:30:08 PM PDT 24 1970442669 ps
T80 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2157405837 Jul 19 04:29:21 PM PDT 24 Jul 19 04:31:31 PM PDT 24 49256613692 ps
T394 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2516887182 Jul 19 04:29:41 PM PDT 24 Jul 19 04:29:56 PM PDT 24 656395757 ps
T395 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.773144205 Jul 19 04:29:44 PM PDT 24 Jul 19 04:30:01 PM PDT 24 1720199373 ps
T396 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2527571284 Jul 19 04:29:46 PM PDT 24 Jul 19 04:31:13 PM PDT 24 8126080279 ps
T81 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1554319427 Jul 19 04:29:48 PM PDT 24 Jul 19 04:30:02 PM PDT 24 234655141 ps
T397 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3107789591 Jul 19 04:29:34 PM PDT 24 Jul 19 04:29:49 PM PDT 24 344473330 ps
T398 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2302541089 Jul 19 04:29:31 PM PDT 24 Jul 19 04:30:05 PM PDT 24 25081355678 ps
T399 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.317376712 Jul 19 04:29:33 PM PDT 24 Jul 19 04:30:07 PM PDT 24 16827352377 ps
T82 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3321996710 Jul 19 04:29:32 PM PDT 24 Jul 19 04:32:30 PM PDT 24 82659644573 ps
T400 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2349550443 Jul 19 04:29:46 PM PDT 24 Jul 19 04:32:28 PM PDT 24 2958601687 ps
T401 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1947998143 Jul 19 04:29:46 PM PDT 24 Jul 19 04:29:59 PM PDT 24 916435549 ps
T402 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2550510314 Jul 19 04:29:34 PM PDT 24 Jul 19 04:30:07 PM PDT 24 18552284872 ps
T107 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.698836619 Jul 19 04:29:30 PM PDT 24 Jul 19 04:32:19 PM PDT 24 5209896895 ps
T403 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2070916427 Jul 19 04:29:34 PM PDT 24 Jul 19 04:30:05 PM PDT 24 14087479004 ps
T404 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2532269121 Jul 19 04:29:31 PM PDT 24 Jul 19 04:30:09 PM PDT 24 34619829018 ps
T405 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2092669516 Jul 19 04:29:32 PM PDT 24 Jul 19 04:29:47 PM PDT 24 336098730 ps
T112 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1805467813 Jul 19 04:29:50 PM PDT 24 Jul 19 04:31:29 PM PDT 24 9163564386 ps
T406 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.4200445109 Jul 19 04:29:34 PM PDT 24 Jul 19 04:29:45 PM PDT 24 167778348 ps
T90 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1211070259 Jul 19 04:29:36 PM PDT 24 Jul 19 04:29:56 PM PDT 24 2857824102 ps
T407 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.4107100407 Jul 19 04:29:50 PM PDT 24 Jul 19 04:30:27 PM PDT 24 46110035099 ps
T408 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4135077762 Jul 19 04:29:37 PM PDT 24 Jul 19 04:31:04 PM PDT 24 440375558 ps
T83 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1548942718 Jul 19 04:29:45 PM PDT 24 Jul 19 04:31:50 PM PDT 24 53963350673 ps
T409 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2334244348 Jul 19 04:29:47 PM PDT 24 Jul 19 04:30:01 PM PDT 24 182097172 ps
T410 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3156139516 Jul 19 04:29:33 PM PDT 24 Jul 19 04:29:46 PM PDT 24 688679122 ps
T411 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2545910704 Jul 19 04:29:39 PM PDT 24 Jul 19 04:29:49 PM PDT 24 758725207 ps
T412 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.743308714 Jul 19 04:29:44 PM PDT 24 Jul 19 04:30:22 PM PDT 24 29280637603 ps
T413 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3349355846 Jul 19 04:29:32 PM PDT 24 Jul 19 04:29:55 PM PDT 24 4301373862 ps
T414 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3928381701 Jul 19 04:29:35 PM PDT 24 Jul 19 04:31:09 PM PDT 24 37054708286 ps
T84 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1207358768 Jul 19 04:29:41 PM PDT 24 Jul 19 04:32:17 PM PDT 24 147885543871 ps
T85 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4064295497 Jul 19 04:29:39 PM PDT 24 Jul 19 04:30:03 PM PDT 24 9517595017 ps
T109 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2148941562 Jul 19 04:29:45 PM PDT 24 Jul 19 04:32:23 PM PDT 24 473902263 ps
T415 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1879415370 Jul 19 04:29:48 PM PDT 24 Jul 19 04:30:28 PM PDT 24 5007800640 ps
T416 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3640517548 Jul 19 04:29:36 PM PDT 24 Jul 19 04:29:50 PM PDT 24 446879774 ps
T86 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3140429548 Jul 19 04:29:42 PM PDT 24 Jul 19 04:30:14 PM PDT 24 15113007520 ps
T417 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1524688686 Jul 19 04:29:36 PM PDT 24 Jul 19 04:30:59 PM PDT 24 494497876 ps
T418 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.439840200 Jul 19 04:29:34 PM PDT 24 Jul 19 04:29:57 PM PDT 24 8175672790 ps
T419 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3743796306 Jul 19 04:29:44 PM PDT 24 Jul 19 04:32:59 PM PDT 24 96351884987 ps
T87 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4290702363 Jul 19 04:29:46 PM PDT 24 Jul 19 04:30:18 PM PDT 24 3665831554 ps
T420 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2983379146 Jul 19 04:29:32 PM PDT 24 Jul 19 04:30:02 PM PDT 24 3402353199 ps
T421 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3786885340 Jul 19 04:29:33 PM PDT 24 Jul 19 04:29:57 PM PDT 24 2066784512 ps
T422 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4249581187 Jul 19 04:29:47 PM PDT 24 Jul 19 04:30:01 PM PDT 24 192263996 ps
T423 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.157416476 Jul 19 04:29:41 PM PDT 24 Jul 19 04:30:48 PM PDT 24 4378322787 ps
T88 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3479270302 Jul 19 04:29:35 PM PDT 24 Jul 19 04:29:53 PM PDT 24 987136564 ps
T424 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.917537183 Jul 19 04:29:31 PM PDT 24 Jul 19 04:29:57 PM PDT 24 8723491057 ps
T92 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3596037624 Jul 19 04:29:37 PM PDT 24 Jul 19 04:31:41 PM PDT 24 54279628883 ps
T425 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1569433108 Jul 19 04:29:35 PM PDT 24 Jul 19 04:30:02 PM PDT 24 10729106519 ps
T426 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2235200578 Jul 19 04:29:44 PM PDT 24 Jul 19 04:30:07 PM PDT 24 9464523018 ps
T427 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2823530684 Jul 19 04:29:43 PM PDT 24 Jul 19 04:30:00 PM PDT 24 338737089 ps
T428 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2286576936 Jul 19 04:29:34 PM PDT 24 Jul 19 04:30:06 PM PDT 24 11641872013 ps
T429 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1745092246 Jul 19 04:29:36 PM PDT 24 Jul 19 04:29:47 PM PDT 24 169116422 ps
T91 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.907353478 Jul 19 04:29:34 PM PDT 24 Jul 19 04:30:32 PM PDT 24 11070228502 ps
T430 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2290491301 Jul 19 04:29:34 PM PDT 24 Jul 19 04:31:49 PM PDT 24 104400527033 ps
T104 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3410774677 Jul 19 04:29:46 PM PDT 24 Jul 19 04:31:08 PM PDT 24 3235929323 ps
T431 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3792996326 Jul 19 04:29:41 PM PDT 24 Jul 19 04:30:09 PM PDT 24 11232169231 ps
T108 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.729562572 Jul 19 04:29:39 PM PDT 24 Jul 19 04:32:25 PM PDT 24 2289662133 ps
T432 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2431647310 Jul 19 04:29:35 PM PDT 24 Jul 19 04:30:05 PM PDT 24 3461558703 ps
T433 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2931589049 Jul 19 04:29:35 PM PDT 24 Jul 19 04:29:59 PM PDT 24 2212931324 ps
T434 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.525450882 Jul 19 04:29:35 PM PDT 24 Jul 19 04:30:06 PM PDT 24 14063244283 ps
T435 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3929321112 Jul 19 04:29:31 PM PDT 24 Jul 19 04:30:55 PM PDT 24 487661372 ps
T436 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.275180879 Jul 19 04:29:33 PM PDT 24 Jul 19 04:30:04 PM PDT 24 9936469064 ps
T437 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.709811614 Jul 19 04:29:36 PM PDT 24 Jul 19 04:29:56 PM PDT 24 263619629 ps
T105 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1007481113 Jul 19 04:29:34 PM PDT 24 Jul 19 04:32:31 PM PDT 24 4198114984 ps
T438 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3490300648 Jul 19 04:29:31 PM PDT 24 Jul 19 04:30:02 PM PDT 24 14023484319 ps
T439 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3253898850 Jul 19 04:29:32 PM PDT 24 Jul 19 04:29:53 PM PDT 24 1970931362 ps
T89 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3910657206 Jul 19 04:29:43 PM PDT 24 Jul 19 04:30:24 PM PDT 24 1406557730 ps
T440 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1880406413 Jul 19 04:29:44 PM PDT 24 Jul 19 04:30:09 PM PDT 24 4834084872 ps
T441 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3797714525 Jul 19 04:29:29 PM PDT 24 Jul 19 04:31:02 PM PDT 24 36754862183 ps
T442 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.843167616 Jul 19 04:29:41 PM PDT 24 Jul 19 04:29:58 PM PDT 24 7327079360 ps
T443 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1698274494 Jul 19 04:29:44 PM PDT 24 Jul 19 04:32:37 PM PDT 24 30154840724 ps
T444 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3424200818 Jul 19 04:29:44 PM PDT 24 Jul 19 04:30:23 PM PDT 24 7536814413 ps
T445 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2451346286 Jul 19 04:29:19 PM PDT 24 Jul 19 04:29:51 PM PDT 24 5860325292 ps
T446 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2701589421 Jul 19 04:29:42 PM PDT 24 Jul 19 04:30:08 PM PDT 24 2776240361 ps
T447 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.4008623025 Jul 19 04:29:47 PM PDT 24 Jul 19 04:30:01 PM PDT 24 177745563 ps
T448 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2481180737 Jul 19 04:29:36 PM PDT 24 Jul 19 04:29:58 PM PDT 24 3596099560 ps
T449 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1190910196 Jul 19 04:29:42 PM PDT 24 Jul 19 04:30:14 PM PDT 24 43051675390 ps
T111 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.799169840 Jul 19 04:29:32 PM PDT 24 Jul 19 04:32:24 PM PDT 24 3249079719 ps
T450 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3213598689 Jul 19 04:29:37 PM PDT 24 Jul 19 04:30:09 PM PDT 24 15818834765 ps
T451 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3399852250 Jul 19 04:29:32 PM PDT 24 Jul 19 04:30:02 PM PDT 24 15144212156 ps
T452 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3551797322 Jul 19 04:29:36 PM PDT 24 Jul 19 04:30:08 PM PDT 24 3626564689 ps
T453 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3267796497 Jul 19 04:29:36 PM PDT 24 Jul 19 04:30:03 PM PDT 24 8472771831 ps
T454 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3788297650 Jul 19 04:29:32 PM PDT 24 Jul 19 04:29:53 PM PDT 24 1724138325 ps
T455 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3176277642 Jul 19 04:29:42 PM PDT 24 Jul 19 04:30:13 PM PDT 24 3615623285 ps
T456 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.120826649 Jul 19 04:29:45 PM PDT 24 Jul 19 04:30:01 PM PDT 24 2621860972 ps
T457 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.202897409 Jul 19 04:29:32 PM PDT 24 Jul 19 04:30:00 PM PDT 24 38616019553 ps
T458 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2674230558 Jul 19 04:29:45 PM PDT 24 Jul 19 04:30:11 PM PDT 24 2140499107 ps
T459 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2706616304 Jul 19 04:29:32 PM PDT 24 Jul 19 04:30:10 PM PDT 24 21923117772 ps
T460 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2291411173 Jul 19 04:29:41 PM PDT 24 Jul 19 04:30:44 PM PDT 24 30287294223 ps
T461 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.54667714 Jul 19 04:29:35 PM PDT 24 Jul 19 04:30:13 PM PDT 24 15375123397 ps

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1110214533
Short name T5
Test name
Test status
Simulation time 65671276146 ps
CPU time 267.85 seconds
Started Jul 19 04:41:06 PM PDT 24
Finished Jul 19 04:45:45 PM PDT 24
Peak memory 218044 kb
Host smart-7ea6cab8-0208-41d5-a25d-c9a17adc8c1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110214533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1110214533
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.116786415
Short name T11
Test name
Test status
Simulation time 50005735390 ps
CPU time 1940.9 seconds
Started Jul 19 04:40:47 PM PDT 24
Finished Jul 19 05:13:11 PM PDT 24
Peak memory 239468 kb
Host smart-b75c6f99-5946-4ab2-8ff0-ba4ea1ec3fe2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116786415 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.116786415
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3213913416
Short name T41
Test name
Test status
Simulation time 72726783022 ps
CPU time 816.76 seconds
Started Jul 19 04:40:32 PM PDT 24
Finished Jul 19 04:54:11 PM PDT 24
Peak memory 239432 kb
Host smart-0b303d23-3216-4066-a19f-da5ec269e2e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213913416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3213913416
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2271853001
Short name T53
Test name
Test status
Simulation time 16746696732 ps
CPU time 169.72 seconds
Started Jul 19 04:29:47 PM PDT 24
Finished Jul 19 04:32:43 PM PDT 24
Peak memory 214228 kb
Host smart-917fe04c-47da-4c63-9d7d-dbd6b63042d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271853001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2271853001
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2923761635
Short name T15
Test name
Test status
Simulation time 715617203 ps
CPU time 19.46 seconds
Started Jul 19 04:41:03 PM PDT 24
Finished Jul 19 04:41:31 PM PDT 24
Peak memory 216496 kb
Host smart-67d505c1-b53b-4d88-8578-1ef10319723b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923761635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2923761635
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.962861636
Short name T20
Test name
Test status
Simulation time 3249532762 ps
CPU time 133.51 seconds
Started Jul 19 04:40:34 PM PDT 24
Finished Jul 19 04:42:50 PM PDT 24
Peak memory 238288 kb
Host smart-3a2af2ee-af79-45f8-9b09-ab8fd2d28daf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962861636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.962861636
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3998967950
Short name T22
Test name
Test status
Simulation time 3536026651 ps
CPU time 28.28 seconds
Started Jul 19 04:40:44 PM PDT 24
Finished Jul 19 04:41:16 PM PDT 24
Peak memory 213340 kb
Host smart-08e99b7b-88d9-442b-bbb3-1e16dfc8df32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998967950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3998967950
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.600862397
Short name T63
Test name
Test status
Simulation time 1081190009 ps
CPU time 57.07 seconds
Started Jul 19 04:29:33 PM PDT 24
Finished Jul 19 04:30:33 PM PDT 24
Peak memory 211404 kb
Host smart-52c1c800-f3d2-4786-9b25-967327c13f9c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600862397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.600862397
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.698836619
Short name T107
Test name
Test status
Simulation time 5209896895 ps
CPU time 168.2 seconds
Started Jul 19 04:29:30 PM PDT 24
Finished Jul 19 04:32:19 PM PDT 24
Peak memory 215060 kb
Host smart-50e72ced-a91b-457e-a775-e721deb9c652
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698836619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.698836619
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.1950901409
Short name T47
Test name
Test status
Simulation time 66919815907 ps
CPU time 2680.15 seconds
Started Jul 19 04:41:02 PM PDT 24
Finished Jul 19 05:25:50 PM PDT 24
Peak memory 248948 kb
Host smart-e7302230-e0bb-4338-bea1-e5a955e21e04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950901409 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.1950901409
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2427880466
Short name T12
Test name
Test status
Simulation time 44095109980 ps
CPU time 67.06 seconds
Started Jul 19 04:40:29 PM PDT 24
Finished Jul 19 04:41:38 PM PDT 24
Peak memory 219348 kb
Host smart-a287a6c5-8353-4c84-9195-7aa4c17e529e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427880466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2427880466
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.267626982
Short name T288
Test name
Test status
Simulation time 1323094564 ps
CPU time 19.19 seconds
Started Jul 19 04:40:31 PM PDT 24
Finished Jul 19 04:40:52 PM PDT 24
Peak memory 219276 kb
Host smart-ae51cffc-b5ef-488f-a065-4e04f25a7e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267626982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.267626982
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3112373303
Short name T43
Test name
Test status
Simulation time 35753048517 ps
CPU time 66.59 seconds
Started Jul 19 04:40:49 PM PDT 24
Finished Jul 19 04:42:00 PM PDT 24
Peak memory 219136 kb
Host smart-09a221c4-95bd-453f-a441-0da036b7b9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112373303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3112373303
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3564076941
Short name T103
Test name
Test status
Simulation time 15518760151 ps
CPU time 166.19 seconds
Started Jul 19 04:29:45 PM PDT 24
Finished Jul 19 04:32:36 PM PDT 24
Peak memory 212980 kb
Host smart-e10652e9-92c2-43c8-8a91-548dc449a6d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564076941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3564076941
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.581973574
Short name T37
Test name
Test status
Simulation time 329560831690 ps
CPU time 749.33 seconds
Started Jul 19 04:40:34 PM PDT 24
Finished Jul 19 04:53:06 PM PDT 24
Peak memory 225440 kb
Host smart-6fc1b75b-9c97-4629-a0d1-e1f604f7e3e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581973574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.581973574
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3321996710
Short name T82
Test name
Test status
Simulation time 82659644573 ps
CPU time 175.93 seconds
Started Jul 19 04:29:32 PM PDT 24
Finished Jul 19 04:32:30 PM PDT 24
Peak memory 215032 kb
Host smart-01adee61-72cf-46fc-a4f1-d55cbe6e03ee
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321996710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3321996710
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.96101038
Short name T77
Test name
Test status
Simulation time 4944061801 ps
CPU time 58.03 seconds
Started Jul 19 04:40:30 PM PDT 24
Finished Jul 19 04:41:30 PM PDT 24
Peak memory 220004 kb
Host smart-0fb3040e-2ccf-4eab-89f8-5503e5d549f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96101038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 7.rom_ctrl_stress_all.96101038
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.483752524
Short name T102
Test name
Test status
Simulation time 1243531120 ps
CPU time 158.52 seconds
Started Jul 19 04:29:34 PM PDT 24
Finished Jul 19 04:32:16 PM PDT 24
Peak memory 213436 kb
Host smart-557a03ca-660c-47ee-93e0-bcdf82817a70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483752524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.483752524
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1805467813
Short name T112
Test name
Test status
Simulation time 9163564386 ps
CPU time 92.56 seconds
Started Jul 19 04:29:50 PM PDT 24
Finished Jul 19 04:31:29 PM PDT 24
Peak memory 218796 kb
Host smart-6b3fd01b-75e4-41e0-b4ce-cff55801fbe4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805467813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1805467813
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4084623735
Short name T54
Test name
Test status
Simulation time 1044166318 ps
CPU time 77.51 seconds
Started Jul 19 04:29:41 PM PDT 24
Finished Jul 19 04:31:00 PM PDT 24
Peak memory 213560 kb
Host smart-db8adc44-5931-4710-85ef-f76b80d2a0ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084623735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.4084623735
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3668949504
Short name T110
Test name
Test status
Simulation time 2115027038 ps
CPU time 159.15 seconds
Started Jul 19 04:31:38 PM PDT 24
Finished Jul 19 04:34:28 PM PDT 24
Peak memory 213764 kb
Host smart-10726db1-5c6a-4881-ba78-3fd4390616e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668949504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3668949504
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2679412695
Short name T375
Test name
Test status
Simulation time 727375747 ps
CPU time 11.92 seconds
Started Jul 19 04:29:32 PM PDT 24
Finished Jul 19 04:29:47 PM PDT 24
Peak memory 210416 kb
Host smart-207461f9-dc9b-42b8-bdcc-9369ad4fda61
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679412695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2679412695
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.317376712
Short name T399
Test name
Test status
Simulation time 16827352377 ps
CPU time 30 seconds
Started Jul 19 04:29:33 PM PDT 24
Finished Jul 19 04:30:07 PM PDT 24
Peak memory 211252 kb
Host smart-70e20bac-85c2-46bc-8bba-ec35a2d7e6c4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317376712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.317376712
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2092669516
Short name T405
Test name
Test status
Simulation time 336098730 ps
CPU time 11.74 seconds
Started Jul 19 04:29:32 PM PDT 24
Finished Jul 19 04:29:47 PM PDT 24
Peak memory 211424 kb
Host smart-7c3214e9-ebc1-4956-940d-ad66c6ffad42
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092669516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2092669516
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2188632966
Short name T58
Test name
Test status
Simulation time 16176633280 ps
CPU time 29.28 seconds
Started Jul 19 04:29:32 PM PDT 24
Finished Jul 19 04:30:05 PM PDT 24
Peak memory 218312 kb
Host smart-85143c4e-bab2-461e-b1d7-55ca372cf152
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188632966 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2188632966
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3490300648
Short name T438
Test name
Test status
Simulation time 14023484319 ps
CPU time 29.49 seconds
Started Jul 19 04:29:31 PM PDT 24
Finished Jul 19 04:30:02 PM PDT 24
Peak memory 212264 kb
Host smart-8ba9f667-6e30-455d-813b-a4c72ba3cfa2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490300648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3490300648
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.964673392
Short name T378
Test name
Test status
Simulation time 13303496020 ps
CPU time 29.71 seconds
Started Jul 19 04:29:32 PM PDT 24
Finished Jul 19 04:30:04 PM PDT 24
Peak memory 210724 kb
Host smart-e1fb0e1d-07bf-40d1-a90d-ff4ee62587dc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964673392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.964673392
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2466992460
Short name T390
Test name
Test status
Simulation time 2294789347 ps
CPU time 11.51 seconds
Started Jul 19 04:29:31 PM PDT 24
Finished Jul 19 04:29:43 PM PDT 24
Peak memory 210376 kb
Host smart-e610fe17-0139-4693-84b5-b0d3290f91f2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466992460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2466992460
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2157405837
Short name T80
Test name
Test status
Simulation time 49256613692 ps
CPU time 128.75 seconds
Started Jul 19 04:29:21 PM PDT 24
Finished Jul 19 04:31:31 PM PDT 24
Peak memory 214836 kb
Host smart-4ba0ab60-6f90-430a-a52f-7d6248a512ff
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157405837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2157405837
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.4084965758
Short name T67
Test name
Test status
Simulation time 4799567110 ps
CPU time 22.11 seconds
Started Jul 19 04:29:32 PM PDT 24
Finished Jul 19 04:29:57 PM PDT 24
Peak memory 212324 kb
Host smart-35079dc5-e03f-42d6-8a79-143b746b45e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084965758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.4084965758
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2451346286
Short name T445
Test name
Test status
Simulation time 5860325292 ps
CPU time 29.95 seconds
Started Jul 19 04:29:19 PM PDT 24
Finished Jul 19 04:29:51 PM PDT 24
Peak memory 217544 kb
Host smart-4788f507-9ad9-4cc9-b24f-de872e854fd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451346286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2451346286
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4079205967
Short name T98
Test name
Test status
Simulation time 8039556877 ps
CPU time 31.33 seconds
Started Jul 19 04:29:29 PM PDT 24
Finished Jul 19 04:30:02 PM PDT 24
Peak memory 211912 kb
Host smart-8a7b3180-716c-4209-9740-492de7097fb2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079205967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.4079205967
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2302541089
Short name T398
Test name
Test status
Simulation time 25081355678 ps
CPU time 31.57 seconds
Started Jul 19 04:29:31 PM PDT 24
Finished Jul 19 04:30:05 PM PDT 24
Peak memory 211900 kb
Host smart-67278e6a-3467-42c6-adb8-cca3350812ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302541089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2302541089
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2286576936
Short name T428
Test name
Test status
Simulation time 11641872013 ps
CPU time 28.55 seconds
Started Jul 19 04:29:34 PM PDT 24
Finished Jul 19 04:30:06 PM PDT 24
Peak memory 211840 kb
Host smart-94e59c63-d598-4f7b-8c57-b2f4426d21d0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286576936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2286576936
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2168964506
Short name T393
Test name
Test status
Simulation time 5834646606 ps
CPU time 23.5 seconds
Started Jul 19 04:29:31 PM PDT 24
Finished Jul 19 04:29:57 PM PDT 24
Peak memory 216224 kb
Host smart-fb2347d0-dcc0-4db4-92ab-a220f43709ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168964506 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2168964506
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4256210733
Short name T374
Test name
Test status
Simulation time 1830415769 ps
CPU time 8.11 seconds
Started Jul 19 04:29:31 PM PDT 24
Finished Jul 19 04:29:40 PM PDT 24
Peak memory 210396 kb
Host smart-9b8ebabb-088a-4b10-804e-e80dbaefe5f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256210733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.4256210733
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2070916427
Short name T403
Test name
Test status
Simulation time 14087479004 ps
CPU time 27.3 seconds
Started Jul 19 04:29:34 PM PDT 24
Finished Jul 19 04:30:05 PM PDT 24
Peak memory 210660 kb
Host smart-0b37019b-80b1-4ea7-b7ae-08e9fcacc963
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070916427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2070916427
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.917537183
Short name T424
Test name
Test status
Simulation time 8723491057 ps
CPU time 24.39 seconds
Started Jul 19 04:29:31 PM PDT 24
Finished Jul 19 04:29:57 PM PDT 24
Peak memory 210420 kb
Host smart-9c0367c4-61c7-4bd0-8410-ad2930186863
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917537183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
917537183
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2290491301
Short name T430
Test name
Test status
Simulation time 104400527033 ps
CPU time 131.82 seconds
Started Jul 19 04:29:34 PM PDT 24
Finished Jul 19 04:31:49 PM PDT 24
Peak memory 213592 kb
Host smart-9c0dd978-ebeb-4080-9ece-b91df173ae27
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290491301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2290491301
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2008763338
Short name T392
Test name
Test status
Simulation time 332832749 ps
CPU time 10.35 seconds
Started Jul 19 04:29:35 PM PDT 24
Finished Jul 19 04:29:49 PM PDT 24
Peak memory 210544 kb
Host smart-73202e41-6032-4fc4-8564-9f5e3f47b436
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008763338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2008763338
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3673169295
Short name T373
Test name
Test status
Simulation time 4316230129 ps
CPU time 37.59 seconds
Started Jul 19 04:29:33 PM PDT 24
Finished Jul 19 04:30:13 PM PDT 24
Peak memory 217480 kb
Host smart-23765753-5e5a-4fb1-ba25-8206d04a614e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673169295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3673169295
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3553024110
Short name T391
Test name
Test status
Simulation time 805981576 ps
CPU time 13.46 seconds
Started Jul 19 04:29:45 PM PDT 24
Finished Jul 19 04:30:04 PM PDT 24
Peak memory 216252 kb
Host smart-1ecb6c57-97a8-4b3c-9f70-a3d097c87baf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553024110 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3553024110
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4290702363
Short name T87
Test name
Test status
Simulation time 3665831554 ps
CPU time 27.24 seconds
Started Jul 19 04:29:46 PM PDT 24
Finished Jul 19 04:30:18 PM PDT 24
Peak memory 211496 kb
Host smart-34c78186-2358-4e6d-b1c1-ced17317cb46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290702363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.4290702363
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1548942718
Short name T83
Test name
Test status
Simulation time 53963350673 ps
CPU time 120.35 seconds
Started Jul 19 04:29:45 PM PDT 24
Finished Jul 19 04:31:50 PM PDT 24
Peak memory 213984 kb
Host smart-861fc96c-d404-47ce-a943-386926071f3a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548942718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1548942718
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.743308714
Short name T412
Test name
Test status
Simulation time 29280637603 ps
CPU time 34.97 seconds
Started Jul 19 04:29:44 PM PDT 24
Finished Jul 19 04:30:22 PM PDT 24
Peak memory 212584 kb
Host smart-1f997b1c-115c-473a-8733-3ab7a121a3fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743308714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.743308714
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.4041380666
Short name T382
Test name
Test status
Simulation time 170809981 ps
CPU time 11.4 seconds
Started Jul 19 04:29:46 PM PDT 24
Finished Jul 19 04:30:03 PM PDT 24
Peak memory 218688 kb
Host smart-37d64a2b-afc4-4a64-bdb1-a56eb405908e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041380666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.4041380666
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.729562572
Short name T108
Test name
Test status
Simulation time 2289662133 ps
CPU time 165.27 seconds
Started Jul 19 04:29:39 PM PDT 24
Finished Jul 19 04:32:25 PM PDT 24
Peak memory 213692 kb
Host smart-10b0faee-487a-46b3-8027-fc51c46b637c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729562572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.729562572
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1562111547
Short name T371
Test name
Test status
Simulation time 5259666653 ps
CPU time 23.31 seconds
Started Jul 19 04:29:43 PM PDT 24
Finished Jul 19 04:30:09 PM PDT 24
Peak memory 218764 kb
Host smart-6b30d5b0-c127-40fb-9e59-43e392438848
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562111547 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1562111547
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3140429548
Short name T86
Test name
Test status
Simulation time 15113007520 ps
CPU time 30.15 seconds
Started Jul 19 04:29:42 PM PDT 24
Finished Jul 19 04:30:14 PM PDT 24
Peak memory 212076 kb
Host smart-52ab2d93-d78b-483f-b481-9b9ee4201f29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140429548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3140429548
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2773475776
Short name T57
Test name
Test status
Simulation time 691139450 ps
CPU time 36.56 seconds
Started Jul 19 04:29:47 PM PDT 24
Finished Jul 19 04:30:30 PM PDT 24
Peak memory 213564 kb
Host smart-c1d1a7ed-0427-4ae9-9a1c-1c94af5afcca
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773475776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2773475776
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1947998143
Short name T401
Test name
Test status
Simulation time 916435549 ps
CPU time 8.41 seconds
Started Jul 19 04:29:46 PM PDT 24
Finished Jul 19 04:29:59 PM PDT 24
Peak memory 210984 kb
Host smart-438507b4-577a-41c4-bc8b-284f59e34c81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947998143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1947998143
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.843167616
Short name T442
Test name
Test status
Simulation time 7327079360 ps
CPU time 15.88 seconds
Started Jul 19 04:29:41 PM PDT 24
Finished Jul 19 04:29:58 PM PDT 24
Peak memory 217492 kb
Host smart-00277cd5-dcdc-4e53-ab9b-3dbb114af221
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843167616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.843167616
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2148941562
Short name T109
Test name
Test status
Simulation time 473902263 ps
CPU time 153.83 seconds
Started Jul 19 04:29:45 PM PDT 24
Finished Jul 19 04:32:23 PM PDT 24
Peak memory 213728 kb
Host smart-2b1948cf-2d29-4576-9ada-03871f46cc5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148941562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2148941562
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2183552990
Short name T369
Test name
Test status
Simulation time 14155368872 ps
CPU time 31.04 seconds
Started Jul 19 04:29:43 PM PDT 24
Finished Jul 19 04:30:17 PM PDT 24
Peak memory 218152 kb
Host smart-57408775-8a46-418a-8ab8-42193ccfe2b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183552990 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2183552990
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1716576147
Short name T66
Test name
Test status
Simulation time 353091148 ps
CPU time 8.28 seconds
Started Jul 19 04:29:40 PM PDT 24
Finished Jul 19 04:29:50 PM PDT 24
Peak memory 210384 kb
Host smart-faf2af64-dba2-4c34-b056-3108e3b9d9d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716576147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1716576147
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3315229618
Short name T78
Test name
Test status
Simulation time 14236091622 ps
CPU time 140.12 seconds
Started Jul 19 04:29:41 PM PDT 24
Finished Jul 19 04:32:02 PM PDT 24
Peak memory 215060 kb
Host smart-781c6c94-47d7-41ea-be81-e320cbdd1306
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315229618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3315229618
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2805148609
Short name T64
Test name
Test status
Simulation time 1674242989 ps
CPU time 17.29 seconds
Started Jul 19 04:29:42 PM PDT 24
Finished Jul 19 04:30:03 PM PDT 24
Peak memory 212264 kb
Host smart-6a11cfd2-c2dd-47e4-bfb5-1a5bedeb4390
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805148609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2805148609
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3792996326
Short name T431
Test name
Test status
Simulation time 11232169231 ps
CPU time 26.47 seconds
Started Jul 19 04:29:41 PM PDT 24
Finished Jul 19 04:30:09 PM PDT 24
Peak memory 218788 kb
Host smart-415a0fee-7bff-4403-beb1-8a5e5db6e1dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792996326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3792996326
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3176277642
Short name T455
Test name
Test status
Simulation time 3615623285 ps
CPU time 28.19 seconds
Started Jul 19 04:29:42 PM PDT 24
Finished Jul 19 04:30:13 PM PDT 24
Peak memory 214384 kb
Host smart-e994ecc5-34c8-4ee6-9d27-a5de3e0094e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176277642 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3176277642
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4064295497
Short name T85
Test name
Test status
Simulation time 9517595017 ps
CPU time 22.69 seconds
Started Jul 19 04:29:39 PM PDT 24
Finished Jul 19 04:30:03 PM PDT 24
Peak memory 212492 kb
Host smart-d8f34b94-1b4d-4700-a2d3-581652ddcb1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064295497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.4064295497
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2527571284
Short name T396
Test name
Test status
Simulation time 8126080279 ps
CPU time 81.23 seconds
Started Jul 19 04:29:46 PM PDT 24
Finished Jul 19 04:31:13 PM PDT 24
Peak memory 214348 kb
Host smart-b71381ed-c389-4bc6-8e30-69ce9734f99c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527571284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2527571284
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2490421977
Short name T96
Test name
Test status
Simulation time 1399936359 ps
CPU time 11.64 seconds
Started Jul 19 04:29:48 PM PDT 24
Finished Jul 19 04:30:06 PM PDT 24
Peak memory 212128 kb
Host smart-8b5d1d4d-ad87-4022-9f5b-5d6b50c59bf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490421977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2490421977
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2362640225
Short name T384
Test name
Test status
Simulation time 24752380480 ps
CPU time 32.1 seconds
Started Jul 19 04:29:41 PM PDT 24
Finished Jul 19 04:30:16 PM PDT 24
Peak memory 218524 kb
Host smart-6bee068c-e75a-49d7-990e-78a350f208b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362640225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2362640225
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.927149152
Short name T101
Test name
Test status
Simulation time 1067212628 ps
CPU time 83.29 seconds
Started Jul 19 04:29:44 PM PDT 24
Finished Jul 19 04:31:11 PM PDT 24
Peak memory 218640 kb
Host smart-d183c7c9-b4ae-48ec-b5c2-3fb28a7b40b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927149152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.927149152
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2334244348
Short name T409
Test name
Test status
Simulation time 182097172 ps
CPU time 8.47 seconds
Started Jul 19 04:29:47 PM PDT 24
Finished Jul 19 04:30:01 PM PDT 24
Peak memory 216280 kb
Host smart-a18169f7-52b8-4f60-bc55-31924c16da62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334244348 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2334244348
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2701589421
Short name T446
Test name
Test status
Simulation time 2776240361 ps
CPU time 23.48 seconds
Started Jul 19 04:29:42 PM PDT 24
Finished Jul 19 04:30:08 PM PDT 24
Peak memory 211300 kb
Host smart-62aa1d13-fc00-4c16-915f-5a3b9a8b81cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701589421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2701589421
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.688859786
Short name T68
Test name
Test status
Simulation time 7655253950 ps
CPU time 81.85 seconds
Started Jul 19 04:29:43 PM PDT 24
Finished Jul 19 04:31:08 PM PDT 24
Peak memory 215788 kb
Host smart-c8a440dc-708a-40b1-ac50-84fce607a642
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688859786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa
ssthru_mem_tl_intg_err.688859786
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1542283975
Short name T93
Test name
Test status
Simulation time 1268590993 ps
CPU time 14.09 seconds
Started Jul 19 04:29:42 PM PDT 24
Finished Jul 19 04:29:59 PM PDT 24
Peak memory 211276 kb
Host smart-9f381d0c-4922-453d-b468-5d3d512d2cee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542283975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1542283975
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3410695362
Short name T367
Test name
Test status
Simulation time 170920361 ps
CPU time 12.74 seconds
Started Jul 19 04:29:46 PM PDT 24
Finished Jul 19 04:30:03 PM PDT 24
Peak memory 217148 kb
Host smart-18aeee29-f6a4-4ab5-9e11-d6059b4a8d5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410695362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3410695362
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3410774677
Short name T104
Test name
Test status
Simulation time 3235929323 ps
CPU time 77.25 seconds
Started Jul 19 04:29:46 PM PDT 24
Finished Jul 19 04:31:08 PM PDT 24
Peak memory 213596 kb
Host smart-442b7b8e-6ab1-4c94-b669-9abac5061c74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410774677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3410774677
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.4008623025
Short name T447
Test name
Test status
Simulation time 177745563 ps
CPU time 8.01 seconds
Started Jul 19 04:29:47 PM PDT 24
Finished Jul 19 04:30:01 PM PDT 24
Peak memory 213608 kb
Host smart-40c8ea4f-5119-4a33-ae8a-314142ce9204
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008623025 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.4008623025
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1190910196
Short name T449
Test name
Test status
Simulation time 43051675390 ps
CPU time 29.15 seconds
Started Jul 19 04:29:42 PM PDT 24
Finished Jul 19 04:30:14 PM PDT 24
Peak memory 212088 kb
Host smart-3f470c62-7b6a-40fa-8b09-41aeb32a06c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190910196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1190910196
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3743796306
Short name T419
Test name
Test status
Simulation time 96351884987 ps
CPU time 190.63 seconds
Started Jul 19 04:29:44 PM PDT 24
Finished Jul 19 04:32:59 PM PDT 24
Peak memory 214816 kb
Host smart-7ee0143c-c869-4103-afc9-c6eae8bd8824
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743796306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3743796306
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2437836077
Short name T97
Test name
Test status
Simulation time 425151156 ps
CPU time 8.15 seconds
Started Jul 19 04:29:41 PM PDT 24
Finished Jul 19 04:29:51 PM PDT 24
Peak memory 210904 kb
Host smart-372478aa-e4b8-4bdb-bb3a-9bb4f85db304
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437836077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2437836077
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.773144205
Short name T395
Test name
Test status
Simulation time 1720199373 ps
CPU time 13.92 seconds
Started Jul 19 04:29:44 PM PDT 24
Finished Jul 19 04:30:01 PM PDT 24
Peak memory 216916 kb
Host smart-4abd12ce-8e13-41de-ac46-c502790c7ca6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773144205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.773144205
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4072592813
Short name T370
Test name
Test status
Simulation time 2558845146 ps
CPU time 22.76 seconds
Started Jul 19 04:29:42 PM PDT 24
Finished Jul 19 04:30:07 PM PDT 24
Peak memory 215392 kb
Host smart-fde723a7-8eef-422e-926f-ff9e43dea6c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072592813 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.4072592813
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1880406413
Short name T440
Test name
Test status
Simulation time 4834084872 ps
CPU time 21.49 seconds
Started Jul 19 04:29:44 PM PDT 24
Finished Jul 19 04:30:09 PM PDT 24
Peak memory 211904 kb
Host smart-b86407ac-e5ad-4951-9cfe-4856a5f47d19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880406413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1880406413
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3910657206
Short name T89
Test name
Test status
Simulation time 1406557730 ps
CPU time 36.9 seconds
Started Jul 19 04:29:43 PM PDT 24
Finished Jul 19 04:30:24 PM PDT 24
Peak memory 214768 kb
Host smart-34ea3eef-a34a-4912-8355-f7095aaa5122
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910657206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3910657206
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.342968453
Short name T65
Test name
Test status
Simulation time 357485574 ps
CPU time 11.8 seconds
Started Jul 19 04:29:44 PM PDT 24
Finished Jul 19 04:30:00 PM PDT 24
Peak memory 212536 kb
Host smart-fb55b09e-fbcc-40c7-8443-0e09dbf716c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342968453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.342968453
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3077051842
Short name T383
Test name
Test status
Simulation time 8557234134 ps
CPU time 22.8 seconds
Started Jul 19 04:29:44 PM PDT 24
Finished Jul 19 04:30:11 PM PDT 24
Peak memory 216920 kb
Host smart-7293d503-921b-4bc3-bf2d-7c007373037c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077051842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3077051842
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4293020197
Short name T387
Test name
Test status
Simulation time 7055845648 ps
CPU time 22.56 seconds
Started Jul 19 04:29:46 PM PDT 24
Finished Jul 19 04:30:15 PM PDT 24
Peak memory 216680 kb
Host smart-403cd970-8964-4bab-ade3-fcedf254c745
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293020197 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.4293020197
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.120826649
Short name T456
Test name
Test status
Simulation time 2621860972 ps
CPU time 12.33 seconds
Started Jul 19 04:29:45 PM PDT 24
Finished Jul 19 04:30:01 PM PDT 24
Peak memory 210756 kb
Host smart-9588ac51-5c0c-49bb-ba41-09a213e1c1ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120826649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.120826649
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2674230558
Short name T458
Test name
Test status
Simulation time 2140499107 ps
CPU time 20.65 seconds
Started Jul 19 04:29:45 PM PDT 24
Finished Jul 19 04:30:11 PM PDT 24
Peak memory 212068 kb
Host smart-18ef11c5-1e50-486a-9656-1f7166d3d1f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674230558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2674230558
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3424200818
Short name T444
Test name
Test status
Simulation time 7536814413 ps
CPU time 34.32 seconds
Started Jul 19 04:29:44 PM PDT 24
Finished Jul 19 04:30:23 PM PDT 24
Peak memory 217324 kb
Host smart-918254b4-4921-4fa2-99e7-257c1100b99b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424200818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3424200818
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2545910704
Short name T411
Test name
Test status
Simulation time 758725207 ps
CPU time 8.79 seconds
Started Jul 19 04:29:39 PM PDT 24
Finished Jul 19 04:29:49 PM PDT 24
Peak memory 216772 kb
Host smart-a12d77e8-96b4-41da-a157-bb90c5df717e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545910704 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2545910704
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2235200578
Short name T426
Test name
Test status
Simulation time 9464523018 ps
CPU time 19.33 seconds
Started Jul 19 04:29:44 PM PDT 24
Finished Jul 19 04:30:07 PM PDT 24
Peak memory 211880 kb
Host smart-0779ad29-c7ff-48c1-b388-c1759a0116a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235200578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2235200578
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1207358768
Short name T84
Test name
Test status
Simulation time 147885543871 ps
CPU time 154.56 seconds
Started Jul 19 04:29:41 PM PDT 24
Finished Jul 19 04:32:17 PM PDT 24
Peak memory 215712 kb
Host smart-ab0746f5-d77c-45bc-9685-7abe6a57175f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207358768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1207358768
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2516887182
Short name T394
Test name
Test status
Simulation time 656395757 ps
CPU time 13.11 seconds
Started Jul 19 04:29:41 PM PDT 24
Finished Jul 19 04:29:56 PM PDT 24
Peak memory 211148 kb
Host smart-f3148fea-91c7-48d9-a3cf-a9dd75e388b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516887182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2516887182
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1723618033
Short name T379
Test name
Test status
Simulation time 9289128475 ps
CPU time 25.44 seconds
Started Jul 19 04:29:47 PM PDT 24
Finished Jul 19 04:30:18 PM PDT 24
Peak memory 218296 kb
Host smart-f1fa5d32-7728-4eb6-9eeb-3122bddc3275
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723618033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1723618033
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3693569201
Short name T56
Test name
Test status
Simulation time 7236861889 ps
CPU time 19.09 seconds
Started Jul 19 04:29:41 PM PDT 24
Finished Jul 19 04:30:02 PM PDT 24
Peak memory 216572 kb
Host smart-9615d095-efd7-41ee-bcb2-42ccc5070f52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693569201 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3693569201
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1554319427
Short name T81
Test name
Test status
Simulation time 234655141 ps
CPU time 7.95 seconds
Started Jul 19 04:29:48 PM PDT 24
Finished Jul 19 04:30:02 PM PDT 24
Peak memory 210376 kb
Host smart-5472e8d3-259e-4ebc-ae6e-b7d250d9e2ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554319427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1554319427
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.157416476
Short name T423
Test name
Test status
Simulation time 4378322787 ps
CPU time 64.06 seconds
Started Jul 19 04:29:41 PM PDT 24
Finished Jul 19 04:30:48 PM PDT 24
Peak memory 214536 kb
Host smart-ee19efbf-e0c5-48b3-82d1-c329dbd3d7ee
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157416476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.157416476
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1422067177
Short name T388
Test name
Test status
Simulation time 12478271482 ps
CPU time 27.85 seconds
Started Jul 19 04:29:43 PM PDT 24
Finished Jul 19 04:30:15 PM PDT 24
Peak memory 212396 kb
Host smart-f2b9f4a5-94c0-427a-974e-eac220d5ffd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422067177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1422067177
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2823530684
Short name T427
Test name
Test status
Simulation time 338737089 ps
CPU time 12.9 seconds
Started Jul 19 04:29:43 PM PDT 24
Finished Jul 19 04:30:00 PM PDT 24
Peak memory 217240 kb
Host smart-f1f3b578-c509-4af1-9e6d-eb1d8a0ef364
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823530684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2823530684
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2349550443
Short name T400
Test name
Test status
Simulation time 2958601687 ps
CPU time 155.68 seconds
Started Jul 19 04:29:46 PM PDT 24
Finished Jul 19 04:32:28 PM PDT 24
Peak memory 213500 kb
Host smart-ab672906-33d1-4f45-91d5-4cbdfa8ff670
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349550443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2349550443
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1745092246
Short name T429
Test name
Test status
Simulation time 169116422 ps
CPU time 8.21 seconds
Started Jul 19 04:29:36 PM PDT 24
Finished Jul 19 04:29:47 PM PDT 24
Peak memory 210344 kb
Host smart-d6a9c625-93eb-45f8-a6aa-2f9fb1b0b1da
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745092246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1745092246
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.293754309
Short name T386
Test name
Test status
Simulation time 12016062434 ps
CPU time 24.7 seconds
Started Jul 19 04:29:31 PM PDT 24
Finished Jul 19 04:29:57 PM PDT 24
Peak memory 211556 kb
Host smart-4070fefe-a5b5-4102-9e1e-2d03ada51721
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293754309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.293754309
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.275180879
Short name T436
Test name
Test status
Simulation time 9936469064 ps
CPU time 27.78 seconds
Started Jul 19 04:29:33 PM PDT 24
Finished Jul 19 04:30:04 PM PDT 24
Peak memory 212156 kb
Host smart-95d2cc9b-4e48-4d64-a04c-c740f0d09fb3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275180879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.275180879
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2163429266
Short name T377
Test name
Test status
Simulation time 687190620 ps
CPU time 8.33 seconds
Started Jul 19 04:29:32 PM PDT 24
Finished Jul 19 04:29:44 PM PDT 24
Peak memory 214600 kb
Host smart-08629f1e-da24-41d8-9048-3ce94c3da934
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163429266 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2163429266
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.4200445109
Short name T406
Test name
Test status
Simulation time 167778348 ps
CPU time 8.35 seconds
Started Jul 19 04:29:34 PM PDT 24
Finished Jul 19 04:29:45 PM PDT 24
Peak memory 210328 kb
Host smart-87269a4b-fd2b-4775-b656-479831225c9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200445109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.4200445109
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2931589049
Short name T433
Test name
Test status
Simulation time 2212931324 ps
CPU time 21.12 seconds
Started Jul 19 04:29:35 PM PDT 24
Finished Jul 19 04:29:59 PM PDT 24
Peak memory 210288 kb
Host smart-82323c87-53d6-4fbb-bb10-6696e55a7858
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931589049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2931589049
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3786885340
Short name T421
Test name
Test status
Simulation time 2066784512 ps
CPU time 20.11 seconds
Started Jul 19 04:29:33 PM PDT 24
Finished Jul 19 04:29:57 PM PDT 24
Peak memory 210236 kb
Host smart-5fe0375b-3b9c-482e-8c76-df76aa2c7a38
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786885340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3786885340
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3935848579
Short name T70
Test name
Test status
Simulation time 24623545527 ps
CPU time 32.33 seconds
Started Jul 19 04:29:34 PM PDT 24
Finished Jul 19 04:30:10 PM PDT 24
Peak memory 212372 kb
Host smart-4bd31c34-6b63-4441-84cf-ce78e3453367
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935848579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3935848579
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3352351323
Short name T381
Test name
Test status
Simulation time 895780598 ps
CPU time 14.17 seconds
Started Jul 19 04:29:31 PM PDT 24
Finished Jul 19 04:29:47 PM PDT 24
Peak memory 216244 kb
Host smart-b57093b2-1796-4578-920e-ee355ac9df10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352351323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3352351323
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.799169840
Short name T111
Test name
Test status
Simulation time 3249079719 ps
CPU time 169.26 seconds
Started Jul 19 04:29:32 PM PDT 24
Finished Jul 19 04:32:24 PM PDT 24
Peak memory 213784 kb
Host smart-3125d013-af40-462d-9828-781dc4883fb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799169840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.799169840
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1211070259
Short name T90
Test name
Test status
Simulation time 2857824102 ps
CPU time 16.36 seconds
Started Jul 19 04:29:36 PM PDT 24
Finished Jul 19 04:29:56 PM PDT 24
Peak memory 211404 kb
Host smart-f260adb2-f3e0-48d9-aea7-1b486c1e8c04
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211070259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1211070259
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3267796497
Short name T453
Test name
Test status
Simulation time 8472771831 ps
CPU time 23.35 seconds
Started Jul 19 04:29:36 PM PDT 24
Finished Jul 19 04:30:03 PM PDT 24
Peak memory 211944 kb
Host smart-5ff512a1-c385-419f-81da-b64072b096cf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267796497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3267796497
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2980332074
Short name T385
Test name
Test status
Simulation time 12103969141 ps
CPU time 30.49 seconds
Started Jul 19 04:29:31 PM PDT 24
Finished Jul 19 04:30:03 PM PDT 24
Peak memory 212192 kb
Host smart-61b9f725-b2d6-480b-8a25-313c530dad87
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980332074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2980332074
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3399852250
Short name T451
Test name
Test status
Simulation time 15144212156 ps
CPU time 28.05 seconds
Started Jul 19 04:29:32 PM PDT 24
Finished Jul 19 04:30:02 PM PDT 24
Peak memory 219116 kb
Host smart-b09f111e-80c6-4335-afb5-28be681b1506
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399852250 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3399852250
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3253898850
Short name T439
Test name
Test status
Simulation time 1970931362 ps
CPU time 18.71 seconds
Started Jul 19 04:29:32 PM PDT 24
Finished Jul 19 04:29:53 PM PDT 24
Peak memory 211388 kb
Host smart-b79e4355-f36b-4fd2-b192-1cd4e84d56e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253898850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3253898850
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.439840200
Short name T418
Test name
Test status
Simulation time 8175672790 ps
CPU time 19.42 seconds
Started Jul 19 04:29:34 PM PDT 24
Finished Jul 19 04:29:57 PM PDT 24
Peak memory 210592 kb
Host smart-2052e516-da8b-4c66-8fb5-2cb128668a3b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439840200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.439840200
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2983379146
Short name T420
Test name
Test status
Simulation time 3402353199 ps
CPU time 26.67 seconds
Started Jul 19 04:29:32 PM PDT 24
Finished Jul 19 04:30:02 PM PDT 24
Peak memory 210320 kb
Host smart-9410abef-598b-45f2-b6d6-0a51f1809d1d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983379146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2983379146
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3235555620
Short name T95
Test name
Test status
Simulation time 13060437783 ps
CPU time 29.23 seconds
Started Jul 19 04:29:33 PM PDT 24
Finished Jul 19 04:30:06 PM PDT 24
Peak memory 212424 kb
Host smart-34569d11-2e8f-4b66-8726-ca6d0b230cf4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235555620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3235555620
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2532269121
Short name T404
Test name
Test status
Simulation time 34619829018 ps
CPU time 37.02 seconds
Started Jul 19 04:29:31 PM PDT 24
Finished Jul 19 04:30:09 PM PDT 24
Peak memory 218728 kb
Host smart-788969d5-f31c-4cfa-b53d-316657f46531
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532269121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2532269121
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3929321112
Short name T435
Test name
Test status
Simulation time 487661372 ps
CPU time 82.95 seconds
Started Jul 19 04:29:31 PM PDT 24
Finished Jul 19 04:30:55 PM PDT 24
Peak memory 213476 kb
Host smart-46fb3b8e-e394-4542-bce9-0276ac32e5a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929321112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3929321112
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3640517548
Short name T416
Test name
Test status
Simulation time 446879774 ps
CPU time 11.21 seconds
Started Jul 19 04:29:36 PM PDT 24
Finished Jul 19 04:29:50 PM PDT 24
Peak memory 210376 kb
Host smart-58881f4f-449a-4cc2-9a30-cb83638b6074
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640517548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3640517548
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3156139516
Short name T410
Test name
Test status
Simulation time 688679122 ps
CPU time 10.24 seconds
Started Jul 19 04:29:33 PM PDT 24
Finished Jul 19 04:29:46 PM PDT 24
Peak memory 210460 kb
Host smart-175eba61-425d-4d23-868e-43b1a0690c27
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156139516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3156139516
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.709811614
Short name T437
Test name
Test status
Simulation time 263619629 ps
CPU time 16.51 seconds
Started Jul 19 04:29:36 PM PDT 24
Finished Jul 19 04:29:56 PM PDT 24
Peak memory 211380 kb
Host smart-d057e80f-dabd-4934-ba80-5df307481db8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709811614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.709811614
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1665522604
Short name T376
Test name
Test status
Simulation time 308349894 ps
CPU time 8.93 seconds
Started Jul 19 04:29:34 PM PDT 24
Finished Jul 19 04:29:46 PM PDT 24
Peak memory 216504 kb
Host smart-57acfd38-a127-403d-b731-7ceafd52e5ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665522604 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1665522604
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3479270302
Short name T88
Test name
Test status
Simulation time 987136564 ps
CPU time 14.3 seconds
Started Jul 19 04:29:35 PM PDT 24
Finished Jul 19 04:29:53 PM PDT 24
Peak memory 211300 kb
Host smart-b9c1e733-94a3-49c1-8171-94f4f60a093e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479270302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3479270302
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2481180737
Short name T448
Test name
Test status
Simulation time 3596099560 ps
CPU time 18.4 seconds
Started Jul 19 04:29:36 PM PDT 24
Finished Jul 19 04:29:58 PM PDT 24
Peak memory 210204 kb
Host smart-722e1121-077a-4910-84e2-059e6917cea3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481180737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2481180737
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3551797322
Short name T452
Test name
Test status
Simulation time 3626564689 ps
CPU time 29.11 seconds
Started Jul 19 04:29:36 PM PDT 24
Finished Jul 19 04:30:08 PM PDT 24
Peak memory 210148 kb
Host smart-07e060dd-39d3-401e-8b36-50d7a0d9d670
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551797322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3551797322
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3928381701
Short name T414
Test name
Test status
Simulation time 37054708286 ps
CPU time 90.51 seconds
Started Jul 19 04:29:35 PM PDT 24
Finished Jul 19 04:31:09 PM PDT 24
Peak memory 213648 kb
Host smart-6f34e08d-df31-4ae7-bb10-cf5776e6dd5f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928381701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3928381701
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3107789591
Short name T397
Test name
Test status
Simulation time 344473330 ps
CPU time 11.44 seconds
Started Jul 19 04:29:34 PM PDT 24
Finished Jul 19 04:29:49 PM PDT 24
Peak memory 212020 kb
Host smart-7cad7968-f606-422c-a83d-67925c718b0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107789591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3107789591
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3113719928
Short name T380
Test name
Test status
Simulation time 5694719962 ps
CPU time 19.6 seconds
Started Jul 19 04:29:35 PM PDT 24
Finished Jul 19 04:29:58 PM PDT 24
Peak memory 218560 kb
Host smart-4f2ebf61-ba1d-468d-9115-cd9e681de2fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113719928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3113719928
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.869753171
Short name T106
Test name
Test status
Simulation time 3328244269 ps
CPU time 166.88 seconds
Started Jul 19 04:29:34 PM PDT 24
Finished Jul 19 04:32:25 PM PDT 24
Peak memory 213644 kb
Host smart-3894879f-1526-4786-bb4c-17f5b530a053
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869753171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.869753171
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2431647310
Short name T432
Test name
Test status
Simulation time 3461558703 ps
CPU time 26.85 seconds
Started Jul 19 04:29:35 PM PDT 24
Finished Jul 19 04:30:05 PM PDT 24
Peak memory 216952 kb
Host smart-646fde90-24c3-4951-a225-6176831268aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431647310 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2431647310
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3788297650
Short name T454
Test name
Test status
Simulation time 1724138325 ps
CPU time 18.52 seconds
Started Jul 19 04:29:32 PM PDT 24
Finished Jul 19 04:29:53 PM PDT 24
Peak memory 211452 kb
Host smart-1a67047c-adc7-4649-81f4-61815eced18a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788297650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3788297650
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1741437818
Short name T72
Test name
Test status
Simulation time 37445044498 ps
CPU time 82.38 seconds
Started Jul 19 04:29:34 PM PDT 24
Finished Jul 19 04:31:00 PM PDT 24
Peak memory 213620 kb
Host smart-079a8763-347e-42ca-b3cf-d188b9006c21
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741437818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1741437818
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3571861571
Short name T94
Test name
Test status
Simulation time 5874307998 ps
CPU time 26.41 seconds
Started Jul 19 04:29:33 PM PDT 24
Finished Jul 19 04:30:02 PM PDT 24
Peak memory 212524 kb
Host smart-29016946-991a-4f82-b819-bdaab417b9fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571861571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3571861571
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2706616304
Short name T459
Test name
Test status
Simulation time 21923117772 ps
CPU time 34.83 seconds
Started Jul 19 04:29:32 PM PDT 24
Finished Jul 19 04:30:10 PM PDT 24
Peak memory 218776 kb
Host smart-070153a6-9ba4-4e79-9bb1-f918935e8c79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706616304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2706616304
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1524688686
Short name T417
Test name
Test status
Simulation time 494497876 ps
CPU time 79.41 seconds
Started Jul 19 04:29:36 PM PDT 24
Finished Jul 19 04:30:59 PM PDT 24
Peak memory 212280 kb
Host smart-33a58552-0e6f-45c8-bf38-bac1a90c8ee4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524688686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1524688686
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3349355846
Short name T413
Test name
Test status
Simulation time 4301373862 ps
CPU time 20.56 seconds
Started Jul 19 04:29:32 PM PDT 24
Finished Jul 19 04:29:55 PM PDT 24
Peak memory 215532 kb
Host smart-23956d04-ce34-4f5c-950f-14ec8ea6796d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349355846 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3349355846
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.202897409
Short name T457
Test name
Test status
Simulation time 38616019553 ps
CPU time 24.91 seconds
Started Jul 19 04:29:32 PM PDT 24
Finished Jul 19 04:30:00 PM PDT 24
Peak memory 211936 kb
Host smart-099c6846-099e-431f-8e13-3f50a1a70629
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202897409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.202897409
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3797714525
Short name T441
Test name
Test status
Simulation time 36754862183 ps
CPU time 92.51 seconds
Started Jul 19 04:29:29 PM PDT 24
Finished Jul 19 04:31:02 PM PDT 24
Peak memory 213652 kb
Host smart-7b41d3bb-25a8-49e6-8bc1-34002ac4b946
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797714525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3797714525
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1569433108
Short name T425
Test name
Test status
Simulation time 10729106519 ps
CPU time 23.98 seconds
Started Jul 19 04:29:35 PM PDT 24
Finished Jul 19 04:30:02 PM PDT 24
Peak memory 212020 kb
Host smart-7e759012-c09e-4301-ba1f-ff04fec55cc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569433108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1569433108
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2547040297
Short name T368
Test name
Test status
Simulation time 9082877647 ps
CPU time 22.98 seconds
Started Jul 19 04:29:32 PM PDT 24
Finished Jul 19 04:29:58 PM PDT 24
Peak memory 218440 kb
Host smart-983a3e71-eee3-4a14-bc5c-ab366269ec91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547040297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2547040297
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1007481113
Short name T105
Test name
Test status
Simulation time 4198114984 ps
CPU time 172.6 seconds
Started Jul 19 04:29:34 PM PDT 24
Finished Jul 19 04:32:31 PM PDT 24
Peak memory 213476 kb
Host smart-8469b153-c851-4c99-b77d-81ed98841c42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007481113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1007481113
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2209806962
Short name T389
Test name
Test status
Simulation time 3789404835 ps
CPU time 26.82 seconds
Started Jul 19 04:29:37 PM PDT 24
Finished Jul 19 04:30:07 PM PDT 24
Peak memory 217416 kb
Host smart-2ae1ecf2-3d2d-421f-8d53-7699d4e7757f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209806962 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2209806962
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.525450882
Short name T434
Test name
Test status
Simulation time 14063244283 ps
CPU time 27.56 seconds
Started Jul 19 04:29:35 PM PDT 24
Finished Jul 19 04:30:06 PM PDT 24
Peak memory 211848 kb
Host smart-1d3878c3-4222-465c-84a6-17d3d9b1e981
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525450882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.525450882
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3596037624
Short name T92
Test name
Test status
Simulation time 54279628883 ps
CPU time 121.06 seconds
Started Jul 19 04:29:37 PM PDT 24
Finished Jul 19 04:31:41 PM PDT 24
Peak memory 215016 kb
Host smart-363ea6de-189b-4788-95af-5bd045e8d01f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596037624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3596037624
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3213598689
Short name T450
Test name
Test status
Simulation time 15818834765 ps
CPU time 29.74 seconds
Started Jul 19 04:29:37 PM PDT 24
Finished Jul 19 04:30:09 PM PDT 24
Peak memory 212568 kb
Host smart-174666e5-e989-4059-a299-6fcb8e90c68e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213598689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3213598689
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.54667714
Short name T461
Test name
Test status
Simulation time 15375123397 ps
CPU time 34.19 seconds
Started Jul 19 04:29:35 PM PDT 24
Finished Jul 19 04:30:13 PM PDT 24
Peak memory 217576 kb
Host smart-d012cb67-8fcc-4ad7-9cda-38945b17aeb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54667714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.54667714
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4135077762
Short name T408
Test name
Test status
Simulation time 440375558 ps
CPU time 83.89 seconds
Started Jul 19 04:29:37 PM PDT 24
Finished Jul 19 04:31:04 PM PDT 24
Peak memory 214468 kb
Host smart-3196e220-8aa6-4b1b-b03f-0a17d1706b3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135077762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.4135077762
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4249581187
Short name T422
Test name
Test status
Simulation time 192263996 ps
CPU time 8.68 seconds
Started Jul 19 04:29:47 PM PDT 24
Finished Jul 19 04:30:01 PM PDT 24
Peak memory 216000 kb
Host smart-d31f03ec-26f9-4f5e-be30-f6a0e5788623
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249581187 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.4249581187
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.868337344
Short name T79
Test name
Test status
Simulation time 1970442669 ps
CPU time 19.67 seconds
Started Jul 19 04:29:44 PM PDT 24
Finished Jul 19 04:30:08 PM PDT 24
Peak memory 211292 kb
Host smart-98b434a7-bfe7-4550-86b1-5c21ab37aefc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868337344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.868337344
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.907353478
Short name T91
Test name
Test status
Simulation time 11070228502 ps
CPU time 55.18 seconds
Started Jul 19 04:29:34 PM PDT 24
Finished Jul 19 04:30:32 PM PDT 24
Peak memory 218744 kb
Host smart-31ba8a0f-63ba-4f98-9a14-074c9b326926
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907353478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.907353478
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.112026718
Short name T69
Test name
Test status
Simulation time 2043914885 ps
CPU time 23.62 seconds
Started Jul 19 04:29:40 PM PDT 24
Finished Jul 19 04:30:04 PM PDT 24
Peak memory 212228 kb
Host smart-f0c340a6-62d6-48ba-a747-c7adfa182309
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112026718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.112026718
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2550510314
Short name T402
Test name
Test status
Simulation time 18552284872 ps
CPU time 29.8 seconds
Started Jul 19 04:29:34 PM PDT 24
Finished Jul 19 04:30:07 PM PDT 24
Peak memory 217400 kb
Host smart-2844701b-0538-4cf3-8fda-221658231759
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550510314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2550510314
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1698274494
Short name T443
Test name
Test status
Simulation time 30154840724 ps
CPU time 168.13 seconds
Started Jul 19 04:29:44 PM PDT 24
Finished Jul 19 04:32:37 PM PDT 24
Peak memory 218676 kb
Host smart-4a5dcce7-a014-42f9-bb49-943410f43282
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698274494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1698274494
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1293349648
Short name T372
Test name
Test status
Simulation time 4218719705 ps
CPU time 19.13 seconds
Started Jul 19 04:29:39 PM PDT 24
Finished Jul 19 04:29:59 PM PDT 24
Peak memory 218056 kb
Host smart-a8bff2c2-baa5-4528-8a2a-8ccb6adc85a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293349648 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1293349648
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.79302652
Short name T71
Test name
Test status
Simulation time 9170839791 ps
CPU time 21.9 seconds
Started Jul 19 04:29:47 PM PDT 24
Finished Jul 19 04:30:15 PM PDT 24
Peak memory 212232 kb
Host smart-6ebb4a73-0f53-4fe1-9153-0796f206991d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79302652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.79302652
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2291411173
Short name T460
Test name
Test status
Simulation time 30287294223 ps
CPU time 62.12 seconds
Started Jul 19 04:29:41 PM PDT 24
Finished Jul 19 04:30:44 PM PDT 24
Peak memory 213780 kb
Host smart-e9a0c3e6-aadd-4cf4-b0de-4fdadf7ed614
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291411173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2291411173
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.4107100407
Short name T407
Test name
Test status
Simulation time 46110035099 ps
CPU time 29.45 seconds
Started Jul 19 04:29:50 PM PDT 24
Finished Jul 19 04:30:27 PM PDT 24
Peak memory 212640 kb
Host smart-0d0bd4f7-7d6c-4069-89e4-9c16a24e67b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107100407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.4107100407
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1879415370
Short name T415
Test name
Test status
Simulation time 5007800640 ps
CPU time 33.91 seconds
Started Jul 19 04:29:48 PM PDT 24
Finished Jul 19 04:30:28 PM PDT 24
Peak memory 217472 kb
Host smart-885719b4-7b1e-49d6-9321-2e9af48f6519
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879415370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1879415370
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.121668557
Short name T55
Test name
Test status
Simulation time 7522843215 ps
CPU time 92.98 seconds
Started Jul 19 04:29:42 PM PDT 24
Finished Jul 19 04:31:17 PM PDT 24
Peak memory 212408 kb
Host smart-6c720e5c-6db9-411b-aeb9-5e99c5cbcf37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121668557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.121668557
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3210229030
Short name T250
Test name
Test status
Simulation time 688285258 ps
CPU time 8.31 seconds
Started Jul 19 04:40:32 PM PDT 24
Finished Jul 19 04:40:43 PM PDT 24
Peak memory 217016 kb
Host smart-064e1d85-3131-458c-8ae4-79cdff671722
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210229030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3210229030
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.217852935
Short name T10
Test name
Test status
Simulation time 19750938571 ps
CPU time 217.7 seconds
Started Jul 19 04:40:27 PM PDT 24
Finished Jul 19 04:44:05 PM PDT 24
Peak memory 241148 kb
Host smart-1eeb2f99-02a7-4314-805f-6338efa428a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217852935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.217852935
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.483074040
Short name T122
Test name
Test status
Simulation time 1978578685 ps
CPU time 22.24 seconds
Started Jul 19 04:40:27 PM PDT 24
Finished Jul 19 04:40:51 PM PDT 24
Peak memory 219288 kb
Host smart-9d5bac19-0b84-4e51-acd5-43a1ac70d022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483074040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.483074040
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3661948928
Short name T141
Test name
Test status
Simulation time 13580924844 ps
CPU time 26.8 seconds
Started Jul 19 04:40:30 PM PDT 24
Finished Jul 19 04:40:58 PM PDT 24
Peak memory 219296 kb
Host smart-38a96163-900e-4ad7-993a-573a83962e6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3661948928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3661948928
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1842874042
Short name T18
Test name
Test status
Simulation time 4130253520 ps
CPU time 248.84 seconds
Started Jul 19 04:40:26 PM PDT 24
Finished Jul 19 04:44:36 PM PDT 24
Peak memory 238092 kb
Host smart-9a5222a4-e661-46e5-9d36-74577e32746b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842874042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1842874042
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2892034228
Short name T224
Test name
Test status
Simulation time 12932184361 ps
CPU time 69.66 seconds
Started Jul 19 04:40:29 PM PDT 24
Finished Jul 19 04:41:40 PM PDT 24
Peak memory 217280 kb
Host smart-1b0e27e9-92cd-4f40-b63a-7ec8ccfe0f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892034228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2892034228
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1838301635
Short name T162
Test name
Test status
Simulation time 41273964561 ps
CPU time 60.48 seconds
Started Jul 19 04:40:31 PM PDT 24
Finished Jul 19 04:41:34 PM PDT 24
Peak memory 219348 kb
Host smart-b6f1523d-3a0f-44c0-a913-0f126fc029b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838301635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1838301635
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.25531987
Short name T253
Test name
Test status
Simulation time 1722164401 ps
CPU time 19.29 seconds
Started Jul 19 04:40:28 PM PDT 24
Finished Jul 19 04:40:49 PM PDT 24
Peak memory 217140 kb
Host smart-479eeef5-ea7a-4f21-bfe5-7e834df9720d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25531987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.25531987
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1929390105
Short name T243
Test name
Test status
Simulation time 343848220323 ps
CPU time 509.81 seconds
Started Jul 19 04:40:27 PM PDT 24
Finished Jul 19 04:48:59 PM PDT 24
Peak memory 240008 kb
Host smart-7864f887-d222-4004-a69c-df5b33e16dbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929390105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1929390105
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1313796713
Short name T142
Test name
Test status
Simulation time 1024457469 ps
CPU time 16.61 seconds
Started Jul 19 04:40:27 PM PDT 24
Finished Jul 19 04:40:46 PM PDT 24
Peak memory 211324 kb
Host smart-28da9e6f-6dba-4355-aec4-e2007010fbf6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1313796713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1313796713
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1957510643
Short name T26
Test name
Test status
Simulation time 16137285411 ps
CPU time 247.35 seconds
Started Jul 19 04:40:31 PM PDT 24
Finished Jul 19 04:44:40 PM PDT 24
Peak memory 236120 kb
Host smart-214323c0-0875-405e-afe5-f1971ee2beaf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957510643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1957510643
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.370300299
Short name T364
Test name
Test status
Simulation time 2752200118 ps
CPU time 35.8 seconds
Started Jul 19 04:40:28 PM PDT 24
Finished Jul 19 04:41:06 PM PDT 24
Peak memory 216476 kb
Host smart-694d3861-29ed-44ff-93c2-6a2ea1786804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370300299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.370300299
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3240743619
Short name T186
Test name
Test status
Simulation time 397045118 ps
CPU time 14.61 seconds
Started Jul 19 04:40:27 PM PDT 24
Finished Jul 19 04:40:42 PM PDT 24
Peak memory 219308 kb
Host smart-4df60f78-8879-4e91-9d99-fab353a85de4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240743619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3240743619
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.512393736
Short name T13
Test name
Test status
Simulation time 89979756256 ps
CPU time 1969.13 seconds
Started Jul 19 04:40:36 PM PDT 24
Finished Jul 19 05:13:28 PM PDT 24
Peak memory 226152 kb
Host smart-7cf83daa-cd8f-4edc-ba9c-5565b7ca42a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512393736 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.512393736
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3732740190
Short name T189
Test name
Test status
Simulation time 3552510869 ps
CPU time 29.78 seconds
Started Jul 19 04:40:30 PM PDT 24
Finished Jul 19 04:41:02 PM PDT 24
Peak memory 217260 kb
Host smart-3a2f9119-fa3a-4cbd-9656-3b369e91f167
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732740190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3732740190
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.574638139
Short name T217
Test name
Test status
Simulation time 475430349129 ps
CPU time 819.83 seconds
Started Jul 19 04:40:34 PM PDT 24
Finished Jul 19 04:54:17 PM PDT 24
Peak memory 233936 kb
Host smart-2de6dbc8-54a2-4c2f-907a-39f852719b20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574638139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.574638139
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.877940234
Short name T357
Test name
Test status
Simulation time 61967354908 ps
CPU time 67.15 seconds
Started Jul 19 04:40:32 PM PDT 24
Finished Jul 19 04:41:41 PM PDT 24
Peak memory 219336 kb
Host smart-f2a3dee0-781c-462a-badd-4a1c619a1a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877940234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.877940234
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1369543062
Short name T147
Test name
Test status
Simulation time 2544687623 ps
CPU time 24.11 seconds
Started Jul 19 04:40:33 PM PDT 24
Finished Jul 19 04:41:00 PM PDT 24
Peak memory 211308 kb
Host smart-e0a5ea46-a73f-4d25-b76d-d69471231902
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1369543062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1369543062
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.19075741
Short name T196
Test name
Test status
Simulation time 678705057 ps
CPU time 20.27 seconds
Started Jul 19 04:40:33 PM PDT 24
Finished Jul 19 04:40:56 PM PDT 24
Peak memory 216148 kb
Host smart-ec595445-bac0-4596-8b59-fb9c2ed36436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19075741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.19075741
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3481979023
Short name T322
Test name
Test status
Simulation time 4918264310 ps
CPU time 24.38 seconds
Started Jul 19 04:40:34 PM PDT 24
Finished Jul 19 04:41:01 PM PDT 24
Peak memory 219192 kb
Host smart-8abab622-8502-42e9-a84a-2b39725c7aff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481979023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3481979023
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.1744158083
Short name T45
Test name
Test status
Simulation time 827286827498 ps
CPU time 2341.74 seconds
Started Jul 19 04:40:30 PM PDT 24
Finished Jul 19 05:19:34 PM PDT 24
Peak memory 244024 kb
Host smart-db872515-191d-45aa-a522-8e9587ed63cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744158083 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.1744158083
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.399260384
Short name T289
Test name
Test status
Simulation time 12684029663 ps
CPU time 27.38 seconds
Started Jul 19 04:40:36 PM PDT 24
Finished Jul 19 04:41:07 PM PDT 24
Peak memory 213268 kb
Host smart-e4c4005d-bd04-4dac-82aa-effac3720cf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399260384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.399260384
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2762289234
Short name T251
Test name
Test status
Simulation time 29762687179 ps
CPU time 376.49 seconds
Started Jul 19 04:40:49 PM PDT 24
Finished Jul 19 04:47:08 PM PDT 24
Peak memory 216944 kb
Host smart-5eb59eb0-2192-4bdb-ae58-4a2003874c8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762289234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2762289234
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.4030851967
Short name T346
Test name
Test status
Simulation time 10398854104 ps
CPU time 67.01 seconds
Started Jul 19 04:40:39 PM PDT 24
Finished Jul 19 04:41:54 PM PDT 24
Peak memory 219244 kb
Host smart-92ba85b9-d054-4dea-be61-6a0a55994d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030851967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.4030851967
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3909674255
Short name T246
Test name
Test status
Simulation time 16092774386 ps
CPU time 32.01 seconds
Started Jul 19 04:40:57 PM PDT 24
Finished Jul 19 04:41:36 PM PDT 24
Peak memory 217692 kb
Host smart-6f607bc3-d082-4130-b950-c7d85c56af06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3909674255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3909674255
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3586431654
Short name T2
Test name
Test status
Simulation time 348922282 ps
CPU time 20.48 seconds
Started Jul 19 04:40:31 PM PDT 24
Finished Jul 19 04:40:54 PM PDT 24
Peak memory 215884 kb
Host smart-bf2b2d48-dabf-407f-9396-e846e750389e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586431654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3586431654
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1068012456
Short name T315
Test name
Test status
Simulation time 5335997250 ps
CPU time 34.21 seconds
Started Jul 19 04:40:33 PM PDT 24
Finished Jul 19 04:41:11 PM PDT 24
Peak memory 219364 kb
Host smart-87b9222e-5511-459f-b692-504a0d210e49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068012456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1068012456
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2275944378
Short name T49
Test name
Test status
Simulation time 190995083662 ps
CPU time 3700.39 seconds
Started Jul 19 04:40:50 PM PDT 24
Finished Jul 19 05:42:36 PM PDT 24
Peak memory 247408 kb
Host smart-54a3b913-2a7f-47e4-84a4-be0bdec2ecf1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275944378 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.2275944378
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2211597515
Short name T185
Test name
Test status
Simulation time 339063967 ps
CPU time 8.26 seconds
Started Jul 19 04:40:42 PM PDT 24
Finished Jul 19 04:40:53 PM PDT 24
Peak memory 217164 kb
Host smart-0d1d243b-b56f-42c8-a2e5-6b2f2af1d6bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211597515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2211597515
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2781242391
Short name T99
Test name
Test status
Simulation time 1595038539 ps
CPU time 105.21 seconds
Started Jul 19 04:40:40 PM PDT 24
Finished Jul 19 04:42:28 PM PDT 24
Peak memory 237576 kb
Host smart-641b1357-a15e-4a24-a82d-07ba8fdea164
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781242391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2781242391
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.119358782
Short name T333
Test name
Test status
Simulation time 847417002 ps
CPU time 18.81 seconds
Started Jul 19 04:40:47 PM PDT 24
Finished Jul 19 04:41:09 PM PDT 24
Peak memory 219260 kb
Host smart-0ec33689-82e9-4db6-bac4-aac5845e6739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119358782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.119358782
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.4206302093
Short name T354
Test name
Test status
Simulation time 365770010 ps
CPU time 10.34 seconds
Started Jul 19 04:40:42 PM PDT 24
Finished Jul 19 04:40:56 PM PDT 24
Peak memory 219216 kb
Host smart-85add394-4245-4161-8a80-cb3cf355f296
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4206302093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.4206302093
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2856108878
Short name T238
Test name
Test status
Simulation time 2774003539 ps
CPU time 25.7 seconds
Started Jul 19 04:40:38 PM PDT 24
Finished Jul 19 04:41:07 PM PDT 24
Peak memory 217384 kb
Host smart-d69868c0-542c-42f4-b1e3-f5e7830cf3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856108878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2856108878
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.788540792
Short name T32
Test name
Test status
Simulation time 41936158322 ps
CPU time 107.07 seconds
Started Jul 19 04:40:44 PM PDT 24
Finished Jul 19 04:42:34 PM PDT 24
Peak memory 219364 kb
Host smart-9cdb495a-c9fb-4134-aa7f-b8e29dc384ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788540792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.788540792
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.1017325945
Short name T46
Test name
Test status
Simulation time 6752355154 ps
CPU time 272.02 seconds
Started Jul 19 04:40:38 PM PDT 24
Finished Jul 19 04:45:13 PM PDT 24
Peak memory 226792 kb
Host smart-eda8eb4b-4778-49fc-9816-f8668b1a40b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017325945 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.1017325945
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2755374581
Short name T241
Test name
Test status
Simulation time 3574497610 ps
CPU time 28.68 seconds
Started Jul 19 04:40:50 PM PDT 24
Finished Jul 19 04:41:23 PM PDT 24
Peak memory 213284 kb
Host smart-e8a1309d-39a0-407e-9ca8-078c2145af00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755374581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2755374581
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3304781909
Short name T218
Test name
Test status
Simulation time 34743845366 ps
CPU time 326.25 seconds
Started Jul 19 04:40:51 PM PDT 24
Finished Jul 19 04:46:23 PM PDT 24
Peak memory 233736 kb
Host smart-6d70e742-bd2a-41d4-8526-fce8944a3439
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304781909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3304781909
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1938700713
Short name T125
Test name
Test status
Simulation time 8531542415 ps
CPU time 66.41 seconds
Started Jul 19 04:40:51 PM PDT 24
Finished Jul 19 04:42:02 PM PDT 24
Peak memory 219320 kb
Host smart-756f9cf1-3ed3-42ed-9e14-4913eb6cc9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938700713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1938700713
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2296531909
Short name T337
Test name
Test status
Simulation time 697271061 ps
CPU time 10.51 seconds
Started Jul 19 04:40:39 PM PDT 24
Finished Jul 19 04:40:53 PM PDT 24
Peak memory 219436 kb
Host smart-48f3f2a3-7b76-4a8b-be44-bcf21f8fa668
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2296531909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2296531909
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3711670489
Short name T311
Test name
Test status
Simulation time 25302252944 ps
CPU time 55.37 seconds
Started Jul 19 04:40:42 PM PDT 24
Finished Jul 19 04:41:40 PM PDT 24
Peak memory 216136 kb
Host smart-ee77ca36-7575-4649-bfe7-65ee1beaad26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711670489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3711670489
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2304629123
Short name T175
Test name
Test status
Simulation time 13305246067 ps
CPU time 87.85 seconds
Started Jul 19 04:40:48 PM PDT 24
Finished Jul 19 04:42:18 PM PDT 24
Peak memory 220364 kb
Host smart-bce6064a-3b84-45a9-b509-2553d88250f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304629123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2304629123
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3206258834
Short name T299
Test name
Test status
Simulation time 174459744 ps
CPU time 8.26 seconds
Started Jul 19 04:40:41 PM PDT 24
Finished Jul 19 04:40:52 PM PDT 24
Peak memory 213160 kb
Host smart-d9716dce-ced1-4ae8-9468-18336f92f941
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206258834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3206258834
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.260598932
Short name T163
Test name
Test status
Simulation time 70007505571 ps
CPU time 681.99 seconds
Started Jul 19 04:40:39 PM PDT 24
Finished Jul 19 04:52:04 PM PDT 24
Peak memory 241052 kb
Host smart-b059aa78-c2c2-402a-aed4-3d3a1ed8a746
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260598932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.260598932
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.689760950
Short name T275
Test name
Test status
Simulation time 3761337260 ps
CPU time 43.79 seconds
Started Jul 19 04:40:42 PM PDT 24
Finished Jul 19 04:41:29 PM PDT 24
Peak memory 219344 kb
Host smart-724e2306-8b83-4c03-a416-d54a8f3de71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689760950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.689760950
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2699151010
Short name T339
Test name
Test status
Simulation time 5738057934 ps
CPU time 16.19 seconds
Started Jul 19 04:40:38 PM PDT 24
Finished Jul 19 04:40:57 PM PDT 24
Peak memory 219044 kb
Host smart-dfa721ba-9423-4b9b-baec-765052196b40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2699151010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2699151010
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.637285928
Short name T350
Test name
Test status
Simulation time 7979820618 ps
CPU time 77.32 seconds
Started Jul 19 04:40:40 PM PDT 24
Finished Jul 19 04:42:00 PM PDT 24
Peak memory 216816 kb
Host smart-37973d4a-96c3-4209-8d1b-9b7196b9cd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637285928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.637285928
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1509656169
Short name T9
Test name
Test status
Simulation time 5053171065 ps
CPU time 48.84 seconds
Started Jul 19 04:40:37 PM PDT 24
Finished Jul 19 04:41:29 PM PDT 24
Peak memory 219348 kb
Host smart-bdc7b601-c3e7-4dba-a235-6b7f49b341d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509656169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1509656169
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.2780496247
Short name T351
Test name
Test status
Simulation time 547780164534 ps
CPU time 2113.45 seconds
Started Jul 19 04:41:00 PM PDT 24
Finished Jul 19 05:16:22 PM PDT 24
Peak memory 246364 kb
Host smart-81d88026-23ca-473d-b83b-4f7c0d157969
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780496247 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.2780496247
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2632812373
Short name T216
Test name
Test status
Simulation time 500967840 ps
CPU time 8.41 seconds
Started Jul 19 04:40:41 PM PDT 24
Finished Jul 19 04:40:52 PM PDT 24
Peak memory 217156 kb
Host smart-f31687d9-518d-44d2-baf6-156a2ef9b0c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632812373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2632812373
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1035136209
Short name T17
Test name
Test status
Simulation time 455320010608 ps
CPU time 473.35 seconds
Started Jul 19 04:40:39 PM PDT 24
Finished Jul 19 04:48:36 PM PDT 24
Peak memory 228828 kb
Host smart-a2970cd6-2aa1-4010-b690-a3bb45ff7b4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035136209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1035136209
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2746786853
Short name T274
Test name
Test status
Simulation time 8424474175 ps
CPU time 37.17 seconds
Started Jul 19 04:40:52 PM PDT 24
Finished Jul 19 04:41:34 PM PDT 24
Peak memory 219372 kb
Host smart-daf4d01f-c8e0-4563-9958-66b6d0f0b607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746786853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2746786853
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2433822181
Short name T100
Test name
Test status
Simulation time 586402363 ps
CPU time 14.07 seconds
Started Jul 19 04:40:37 PM PDT 24
Finished Jul 19 04:40:55 PM PDT 24
Peak memory 219296 kb
Host smart-8b760028-4da2-4acf-9821-85cecb874138
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2433822181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2433822181
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.2948842167
Short name T121
Test name
Test status
Simulation time 345323749 ps
CPU time 20.47 seconds
Started Jul 19 04:40:40 PM PDT 24
Finished Jul 19 04:41:04 PM PDT 24
Peak memory 217968 kb
Host smart-1340c19a-5246-4785-b779-3ac9e62ea66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948842167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2948842167
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3689688905
Short name T200
Test name
Test status
Simulation time 7380772706 ps
CPU time 39.68 seconds
Started Jul 19 04:40:39 PM PDT 24
Finished Jul 19 04:41:32 PM PDT 24
Peak memory 219324 kb
Host smart-84ee4b81-9b2c-4452-9dd9-c3182c0ea4bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689688905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3689688905
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1967100633
Short name T305
Test name
Test status
Simulation time 3877422797 ps
CPU time 30.22 seconds
Started Jul 19 04:40:43 PM PDT 24
Finished Jul 19 04:41:17 PM PDT 24
Peak memory 213344 kb
Host smart-4edc80f7-ee62-495b-a762-b40608e7359d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967100633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1967100633
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2670665420
Short name T266
Test name
Test status
Simulation time 73575237579 ps
CPU time 393.03 seconds
Started Jul 19 04:40:42 PM PDT 24
Finished Jul 19 04:47:18 PM PDT 24
Peak memory 218036 kb
Host smart-2c857b2f-fe9f-4752-bd96-72e53d8536a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670665420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2670665420
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.4292322321
Short name T330
Test name
Test status
Simulation time 346433920 ps
CPU time 19.17 seconds
Started Jul 19 04:40:39 PM PDT 24
Finished Jul 19 04:41:01 PM PDT 24
Peak memory 219312 kb
Host smart-4773ed98-f1ad-4983-b14b-5864db713d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292322321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.4292322321
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3627438374
Short name T270
Test name
Test status
Simulation time 2322710340 ps
CPU time 13.33 seconds
Started Jul 19 04:40:48 PM PDT 24
Finished Jul 19 04:41:05 PM PDT 24
Peak memory 219280 kb
Host smart-1ede4bfc-dcc7-4e5f-8ca2-5ea021848ced
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3627438374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3627438374
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3122088277
Short name T365
Test name
Test status
Simulation time 60607974561 ps
CPU time 81.51 seconds
Started Jul 19 04:40:51 PM PDT 24
Finished Jul 19 04:42:17 PM PDT 24
Peak memory 215480 kb
Host smart-2698ccfd-fa82-4a47-bb4d-43e0df7a6d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122088277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3122088277
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2402854756
Short name T252
Test name
Test status
Simulation time 1462323288 ps
CPU time 23.78 seconds
Started Jul 19 04:40:41 PM PDT 24
Finished Jul 19 04:41:08 PM PDT 24
Peak memory 218860 kb
Host smart-eb701cdf-bd78-4d95-a372-9658b14b1529
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402854756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2402854756
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1412153402
Short name T179
Test name
Test status
Simulation time 514322084 ps
CPU time 11.98 seconds
Started Jul 19 04:40:55 PM PDT 24
Finished Jul 19 04:41:14 PM PDT 24
Peak memory 217056 kb
Host smart-b4d6bd9e-e1cd-432e-a447-e94dccf985d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412153402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1412153402
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2628758650
Short name T327
Test name
Test status
Simulation time 5048929576 ps
CPU time 203.94 seconds
Started Jul 19 04:40:43 PM PDT 24
Finished Jul 19 04:44:11 PM PDT 24
Peak memory 236592 kb
Host smart-38d423ca-289f-4122-94cb-03ebaca4e218
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628758650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2628758650
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.496332800
Short name T219
Test name
Test status
Simulation time 15735269316 ps
CPU time 44.94 seconds
Started Jul 19 04:40:40 PM PDT 24
Finished Jul 19 04:41:28 PM PDT 24
Peak memory 219292 kb
Host smart-0c87a2c3-67c5-4f82-b934-d72c05404b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496332800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.496332800
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1805831307
Short name T262
Test name
Test status
Simulation time 12534498081 ps
CPU time 28.85 seconds
Started Jul 19 04:40:44 PM PDT 24
Finished Jul 19 04:41:16 PM PDT 24
Peak memory 211928 kb
Host smart-1ca6fead-560a-4000-a425-48dfb3f5387c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1805831307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1805831307
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2146472948
Short name T282
Test name
Test status
Simulation time 10180463279 ps
CPU time 67.94 seconds
Started Jul 19 04:40:41 PM PDT 24
Finished Jul 19 04:41:53 PM PDT 24
Peak memory 216336 kb
Host smart-1b5b17b1-6d7b-40b7-a83b-5fa3816a250a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146472948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2146472948
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.553484955
Short name T73
Test name
Test status
Simulation time 776893521 ps
CPU time 14.51 seconds
Started Jul 19 04:40:41 PM PDT 24
Finished Jul 19 04:40:59 PM PDT 24
Peak memory 219260 kb
Host smart-0fb9a620-c002-4a7c-93c2-5d53842e94ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553484955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.553484955
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.1396350955
Short name T50
Test name
Test status
Simulation time 22381014685 ps
CPU time 246.2 seconds
Started Jul 19 04:40:43 PM PDT 24
Finished Jul 19 04:44:53 PM PDT 24
Peak memory 227756 kb
Host smart-d7ba9f0a-1975-45ad-b7f4-4ad5c5ecffa5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396350955 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.1396350955
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3514105928
Short name T306
Test name
Test status
Simulation time 2816428757 ps
CPU time 22.69 seconds
Started Jul 19 04:40:42 PM PDT 24
Finished Jul 19 04:41:08 PM PDT 24
Peak memory 217160 kb
Host smart-a04cc95e-5630-4b09-aaf3-e1f54a448f2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514105928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3514105928
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.643435070
Short name T148
Test name
Test status
Simulation time 32804822383 ps
CPU time 240.62 seconds
Started Jul 19 04:41:00 PM PDT 24
Finished Jul 19 04:45:08 PM PDT 24
Peak memory 218980 kb
Host smart-3ddf53f8-19b4-4035-bbf6-de09db5ad257
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643435070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.643435070
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3353612836
Short name T264
Test name
Test status
Simulation time 6774667999 ps
CPU time 58.89 seconds
Started Jul 19 04:40:43 PM PDT 24
Finished Jul 19 04:41:45 PM PDT 24
Peak memory 219212 kb
Host smart-d51273a6-ad63-4733-a659-9c5b5e8b2493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353612836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3353612836
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2821622240
Short name T324
Test name
Test status
Simulation time 2905879140 ps
CPU time 25.68 seconds
Started Jul 19 04:40:46 PM PDT 24
Finished Jul 19 04:41:15 PM PDT 24
Peak memory 211576 kb
Host smart-41f98fa2-8942-4e3f-ba38-b2cdf8ccaeaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2821622240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2821622240
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1358976391
Short name T3
Test name
Test status
Simulation time 17793755543 ps
CPU time 50.11 seconds
Started Jul 19 04:40:51 PM PDT 24
Finished Jul 19 04:41:47 PM PDT 24
Peak memory 216444 kb
Host smart-8e0670ad-8d35-4de9-9df9-308aff5e4a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358976391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1358976391
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.340282296
Short name T242
Test name
Test status
Simulation time 49265022112 ps
CPU time 67.24 seconds
Started Jul 19 04:40:45 PM PDT 24
Finished Jul 19 04:41:56 PM PDT 24
Peak memory 219348 kb
Host smart-c6a81fc5-ae06-4f26-b0fa-308c09b98ab4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340282296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.340282296
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.678225898
Short name T207
Test name
Test status
Simulation time 6149712698 ps
CPU time 25.18 seconds
Started Jul 19 04:40:47 PM PDT 24
Finished Jul 19 04:41:15 PM PDT 24
Peak memory 213308 kb
Host smart-d3b5d737-9b79-4177-b2dd-9da1c719d15e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678225898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.678225898
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3925969546
Short name T191
Test name
Test status
Simulation time 6227073283 ps
CPU time 245.57 seconds
Started Jul 19 04:40:54 PM PDT 24
Finished Jul 19 04:45:05 PM PDT 24
Peak memory 234856 kb
Host smart-aebe1fd6-b8a4-4a1c-a61b-7e1f303a48b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925969546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3925969546
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3245464833
Short name T161
Test name
Test status
Simulation time 12515500962 ps
CPU time 39.48 seconds
Started Jul 19 04:40:38 PM PDT 24
Finished Jul 19 04:41:21 PM PDT 24
Peak memory 219244 kb
Host smart-70ed26a4-fac6-43b5-b950-1c619ada9bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245464833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3245464833
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3401777226
Short name T192
Test name
Test status
Simulation time 1019420259 ps
CPU time 16.4 seconds
Started Jul 19 04:40:47 PM PDT 24
Finished Jul 19 04:41:06 PM PDT 24
Peak memory 218548 kb
Host smart-f521e8a5-8984-4530-bd64-95170afe3b56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3401777226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3401777226
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.827469258
Short name T201
Test name
Test status
Simulation time 8585485244 ps
CPU time 32.36 seconds
Started Jul 19 04:40:41 PM PDT 24
Finished Jul 19 04:41:17 PM PDT 24
Peak memory 217100 kb
Host smart-b167bddf-47ad-43c7-97a4-0e659a1d4932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827469258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.827469258
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.301503940
Short name T113
Test name
Test status
Simulation time 2532905239 ps
CPU time 44.96 seconds
Started Jul 19 04:40:44 PM PDT 24
Finished Jul 19 04:41:33 PM PDT 24
Peak memory 219300 kb
Host smart-c48c30a5-0844-42d0-9ba8-a76c6ed308d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301503940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.301503940
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.693011468
Short name T48
Test name
Test status
Simulation time 58004155004 ps
CPU time 1736.83 seconds
Started Jul 19 04:40:50 PM PDT 24
Finished Jul 19 05:09:50 PM PDT 24
Peak memory 238604 kb
Host smart-dcfcd0dc-8279-42ba-8ef8-4b9aaba4d86c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693011468 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.693011468
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1239422697
Short name T209
Test name
Test status
Simulation time 3776267742 ps
CPU time 17.76 seconds
Started Jul 19 04:40:32 PM PDT 24
Finished Jul 19 04:40:52 PM PDT 24
Peak memory 217056 kb
Host smart-2697eddd-64f5-479c-a59b-0c496be8cc6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239422697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1239422697
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2417276565
Short name T195
Test name
Test status
Simulation time 16113134602 ps
CPU time 284.67 seconds
Started Jul 19 04:40:27 PM PDT 24
Finished Jul 19 04:45:14 PM PDT 24
Peak memory 237864 kb
Host smart-904b8f60-a259-4d7c-9055-b38f568ee58b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417276565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2417276565
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1460882578
Short name T342
Test name
Test status
Simulation time 769638743 ps
CPU time 23.82 seconds
Started Jul 19 04:40:32 PM PDT 24
Finished Jul 19 04:40:58 PM PDT 24
Peak memory 218896 kb
Host smart-96f64c49-1253-4038-a320-65e07c041378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460882578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1460882578
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3459726940
Short name T30
Test name
Test status
Simulation time 699854213 ps
CPU time 10.33 seconds
Started Jul 19 04:40:26 PM PDT 24
Finished Jul 19 04:40:37 PM PDT 24
Peak memory 219256 kb
Host smart-a70cc69b-082f-45e7-9e18-9b4d7e3cc09b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3459726940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3459726940
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.842501421
Short name T19
Test name
Test status
Simulation time 1078522523 ps
CPU time 234.59 seconds
Started Jul 19 04:40:31 PM PDT 24
Finished Jul 19 04:44:27 PM PDT 24
Peak memory 239304 kb
Host smart-74c9fc2a-095f-4a1f-b41d-9e0f6e9d2046
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842501421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.842501421
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1628788061
Short name T258
Test name
Test status
Simulation time 675229565 ps
CPU time 25.42 seconds
Started Jul 19 04:40:36 PM PDT 24
Finished Jul 19 04:41:05 PM PDT 24
Peak memory 216084 kb
Host smart-1a92c608-7cea-4568-82bb-88d1b29ff2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628788061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1628788061
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3620866109
Short name T187
Test name
Test status
Simulation time 22590472735 ps
CPU time 122.79 seconds
Started Jul 19 04:40:28 PM PDT 24
Finished Jul 19 04:42:32 PM PDT 24
Peak memory 219408 kb
Host smart-573caa8e-c5c4-49aa-954c-bb79ae3b8a64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620866109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3620866109
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1187712318
Short name T341
Test name
Test status
Simulation time 161143454217 ps
CPU time 5879.32 seconds
Started Jul 19 04:40:35 PM PDT 24
Finished Jul 19 06:18:38 PM PDT 24
Peak memory 234088 kb
Host smart-e96c805d-5268-495c-bc3e-bae6da8fcb65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187712318 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.1187712318
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.4035152092
Short name T60
Test name
Test status
Simulation time 1101651715 ps
CPU time 7.94 seconds
Started Jul 19 04:40:49 PM PDT 24
Finished Jul 19 04:41:01 PM PDT 24
Peak memory 212960 kb
Host smart-bb733c20-0cd8-4e9f-bd31-35bc1e51e02d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035152092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.4035152092
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.335790626
Short name T139
Test name
Test status
Simulation time 21965631899 ps
CPU time 539.82 seconds
Started Jul 19 04:40:49 PM PDT 24
Finished Jul 19 04:49:52 PM PDT 24
Peak memory 235744 kb
Host smart-fc17a2df-6f71-4348-9893-25a24521601f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335790626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.335790626
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.4051452844
Short name T328
Test name
Test status
Simulation time 7210745422 ps
CPU time 62.99 seconds
Started Jul 19 04:40:46 PM PDT 24
Finished Jul 19 04:41:52 PM PDT 24
Peak memory 219324 kb
Host smart-7d9ddc0c-7eed-4d0e-bfe4-41dd4ba0a8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051452844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.4051452844
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2428599432
Short name T133
Test name
Test status
Simulation time 1078153539 ps
CPU time 16.5 seconds
Started Jul 19 04:40:44 PM PDT 24
Finished Jul 19 04:41:04 PM PDT 24
Peak memory 218848 kb
Host smart-fd29a45b-4c26-48a2-b848-7255b79cb2fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2428599432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2428599432
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2245119000
Short name T225
Test name
Test status
Simulation time 8558515045 ps
CPU time 67.76 seconds
Started Jul 19 04:40:44 PM PDT 24
Finished Jul 19 04:41:55 PM PDT 24
Peak memory 216664 kb
Host smart-db64ee95-7700-444c-8683-9610485253d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245119000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2245119000
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.1213181334
Short name T237
Test name
Test status
Simulation time 380042412 ps
CPU time 13.97 seconds
Started Jul 19 04:40:46 PM PDT 24
Finished Jul 19 04:41:03 PM PDT 24
Peak memory 214560 kb
Host smart-399bea23-c026-4958-ba79-aaa638c69cc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213181334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.1213181334
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2826381851
Short name T160
Test name
Test status
Simulation time 5891384294 ps
CPU time 18.15 seconds
Started Jul 19 04:40:45 PM PDT 24
Finished Jul 19 04:41:06 PM PDT 24
Peak memory 213084 kb
Host smart-9c76adb6-10d8-447e-9585-f87fe3d0f542
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826381851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2826381851
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2733965187
Short name T361
Test name
Test status
Simulation time 62698635215 ps
CPU time 284.55 seconds
Started Jul 19 04:40:54 PM PDT 24
Finished Jul 19 04:45:44 PM PDT 24
Peak memory 219548 kb
Host smart-41fd0a81-c9f4-447a-acdd-053737cff9a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733965187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2733965187
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1271393874
Short name T123
Test name
Test status
Simulation time 2167279413 ps
CPU time 33.33 seconds
Started Jul 19 04:40:41 PM PDT 24
Finished Jul 19 04:41:18 PM PDT 24
Peak memory 219112 kb
Host smart-4d1f1b7b-355c-4efc-92b5-763adfa5b810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271393874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1271393874
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.735443525
Short name T144
Test name
Test status
Simulation time 5106491879 ps
CPU time 31.5 seconds
Started Jul 19 04:40:45 PM PDT 24
Finished Jul 19 04:41:20 PM PDT 24
Peak memory 219052 kb
Host smart-e10085cd-1134-4ba6-80b5-83d7ec550adc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=735443525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.735443525
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.157769224
Short name T188
Test name
Test status
Simulation time 8093529963 ps
CPU time 50.9 seconds
Started Jul 19 04:40:47 PM PDT 24
Finished Jul 19 04:41:40 PM PDT 24
Peak memory 216896 kb
Host smart-18b01d36-22cf-4195-8a15-1c7b0e5e6be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157769224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.157769224
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3290111117
Short name T286
Test name
Test status
Simulation time 78876244723 ps
CPU time 137.3 seconds
Started Jul 19 04:40:44 PM PDT 24
Finished Jul 19 04:43:05 PM PDT 24
Peak memory 220916 kb
Host smart-5a5a6d73-a199-4972-8af1-563cb61b0469
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290111117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3290111117
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1190115440
Short name T183
Test name
Test status
Simulation time 7867725719 ps
CPU time 20.69 seconds
Started Jul 19 04:40:50 PM PDT 24
Finished Jul 19 04:41:15 PM PDT 24
Peak memory 217456 kb
Host smart-98c39233-cca4-4ea8-83f0-664f472cc6be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190115440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1190115440
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3933275430
Short name T348
Test name
Test status
Simulation time 223765898987 ps
CPU time 578.56 seconds
Started Jul 19 04:40:53 PM PDT 24
Finished Jul 19 04:50:37 PM PDT 24
Peak memory 240064 kb
Host smart-093676c3-009c-490f-9428-4fb54a513ce7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933275430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3933275430
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2303703031
Short name T271
Test name
Test status
Simulation time 4304194229 ps
CPU time 16.42 seconds
Started Jul 19 04:40:46 PM PDT 24
Finished Jul 19 04:41:06 PM PDT 24
Peak memory 211616 kb
Host smart-3120badb-969a-4703-8cab-e24084c5534e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2303703031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2303703031
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2499828243
Short name T149
Test name
Test status
Simulation time 12212101320 ps
CPU time 42.01 seconds
Started Jul 19 04:40:45 PM PDT 24
Finished Jul 19 04:41:30 PM PDT 24
Peak memory 216996 kb
Host smart-4b48661f-40c4-4645-a778-e5882525aa55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499828243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2499828243
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.730109899
Short name T295
Test name
Test status
Simulation time 2189218794 ps
CPU time 32.66 seconds
Started Jul 19 04:40:44 PM PDT 24
Finished Jul 19 04:41:20 PM PDT 24
Peak memory 219240 kb
Host smart-f345c447-b9bd-460d-8b1c-18215c816dd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730109899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.730109899
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3224562058
Short name T190
Test name
Test status
Simulation time 1388070586 ps
CPU time 16.89 seconds
Started Jul 19 04:40:38 PM PDT 24
Finished Jul 19 04:40:58 PM PDT 24
Peak memory 217092 kb
Host smart-f8708444-a708-44ba-9470-8ee9034cd1f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224562058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3224562058
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.989054466
Short name T184
Test name
Test status
Simulation time 110127435709 ps
CPU time 755.17 seconds
Started Jul 19 04:40:41 PM PDT 24
Finished Jul 19 04:53:20 PM PDT 24
Peak memory 236496 kb
Host smart-5fdacd40-3367-45ce-92c8-5953fb8f290d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989054466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.989054466
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1209338745
Short name T347
Test name
Test status
Simulation time 16700455142 ps
CPU time 63.08 seconds
Started Jul 19 04:40:43 PM PDT 24
Finished Jul 19 04:41:49 PM PDT 24
Peak memory 219336 kb
Host smart-f479637c-eafb-4b6b-a16a-765e75e0f596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209338745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1209338745
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.4102144170
Short name T283
Test name
Test status
Simulation time 1187536903 ps
CPU time 17.48 seconds
Started Jul 19 04:40:42 PM PDT 24
Finished Jul 19 04:41:03 PM PDT 24
Peak memory 219256 kb
Host smart-bc998f37-32df-4d37-b040-a211d7e2cbfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4102144170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.4102144170
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.4116885155
Short name T151
Test name
Test status
Simulation time 11646320583 ps
CPU time 52.3 seconds
Started Jul 19 04:40:47 PM PDT 24
Finished Jul 19 04:41:42 PM PDT 24
Peak memory 216280 kb
Host smart-d8be97b0-116e-4a8a-90e9-1826bc4f0ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116885155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.4116885155
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1584738439
Short name T345
Test name
Test status
Simulation time 3127065181 ps
CPU time 34.83 seconds
Started Jul 19 04:40:46 PM PDT 24
Finished Jul 19 04:41:24 PM PDT 24
Peak memory 219256 kb
Host smart-091f3797-63c9-4f79-ab2d-6d5a6dcf7901
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584738439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1584738439
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2757239843
Short name T287
Test name
Test status
Simulation time 169369218 ps
CPU time 8.32 seconds
Started Jul 19 04:40:46 PM PDT 24
Finished Jul 19 04:40:57 PM PDT 24
Peak memory 217064 kb
Host smart-dbdca428-ae92-4ebe-933e-1d18c149133f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757239843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2757239843
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1413156716
Short name T146
Test name
Test status
Simulation time 38632024933 ps
CPU time 305.59 seconds
Started Jul 19 04:40:40 PM PDT 24
Finished Jul 19 04:45:48 PM PDT 24
Peak memory 225016 kb
Host smart-7c162ee2-3f50-4570-b08f-b3f78dc43d58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413156716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1413156716
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1369510167
Short name T8
Test name
Test status
Simulation time 4963096203 ps
CPU time 49.41 seconds
Started Jul 19 04:40:40 PM PDT 24
Finished Jul 19 04:41:33 PM PDT 24
Peak memory 219312 kb
Host smart-b0c89dd0-8aff-42cd-8375-4471843a4d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369510167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1369510167
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2589855770
Short name T304
Test name
Test status
Simulation time 707819966 ps
CPU time 10.64 seconds
Started Jul 19 04:40:39 PM PDT 24
Finished Jul 19 04:40:53 PM PDT 24
Peak memory 219300 kb
Host smart-98ed4815-3919-4d9f-a268-0de34086c660
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2589855770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2589855770
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1936758803
Short name T332
Test name
Test status
Simulation time 14445476156 ps
CPU time 46.04 seconds
Started Jul 19 04:40:39 PM PDT 24
Finished Jul 19 04:41:29 PM PDT 24
Peak memory 215928 kb
Host smart-8b71f420-75a7-4075-bba2-18aaab867143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936758803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1936758803
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.731093172
Short name T16
Test name
Test status
Simulation time 7580071927 ps
CPU time 21.06 seconds
Started Jul 19 04:40:51 PM PDT 24
Finished Jul 19 04:41:17 PM PDT 24
Peak memory 218184 kb
Host smart-2256b53c-2b99-43ff-89a6-588336d7984e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731093172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.731093172
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.4038046289
Short name T276
Test name
Test status
Simulation time 60457229305 ps
CPU time 552.39 seconds
Started Jul 19 04:40:50 PM PDT 24
Finished Jul 19 04:50:07 PM PDT 24
Peak memory 234736 kb
Host smart-350d537c-f230-40ee-8857-44580ebb8bc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038046289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.4038046289
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2659690639
Short name T208
Test name
Test status
Simulation time 3181787708 ps
CPU time 38.03 seconds
Started Jul 19 04:40:43 PM PDT 24
Finished Jul 19 04:41:25 PM PDT 24
Peak memory 219332 kb
Host smart-1e885a96-b831-43a7-a6e1-66c0085a6b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659690639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2659690639
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1541473922
Short name T312
Test name
Test status
Simulation time 696986508 ps
CPU time 14.4 seconds
Started Jul 19 04:40:49 PM PDT 24
Finished Jul 19 04:41:07 PM PDT 24
Peak memory 218552 kb
Host smart-e7bc5cce-5611-4e15-a7e7-625243d4afea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1541473922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1541473922
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1746339777
Short name T33
Test name
Test status
Simulation time 11439384146 ps
CPU time 59.77 seconds
Started Jul 19 04:40:43 PM PDT 24
Finished Jul 19 04:41:46 PM PDT 24
Peak memory 216100 kb
Host smart-389631b9-4617-4070-b4af-df407492fe6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746339777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1746339777
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1187104693
Short name T140
Test name
Test status
Simulation time 10486972717 ps
CPU time 37.3 seconds
Started Jul 19 04:40:42 PM PDT 24
Finished Jul 19 04:41:23 PM PDT 24
Peak memory 219104 kb
Host smart-a54951ec-a377-4632-8287-da23c52c4baf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187104693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1187104693
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.350443492
Short name T362
Test name
Test status
Simulation time 80641908756 ps
CPU time 1409.96 seconds
Started Jul 19 04:40:51 PM PDT 24
Finished Jul 19 05:04:25 PM PDT 24
Peak memory 231408 kb
Host smart-faa9bca0-bbcb-44d2-a318-e8209c73ca93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350443492 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.350443492
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.324740186
Short name T165
Test name
Test status
Simulation time 4243117504 ps
CPU time 33.35 seconds
Started Jul 19 04:40:51 PM PDT 24
Finished Jul 19 04:41:29 PM PDT 24
Peak memory 213268 kb
Host smart-242e69b8-f718-42ac-898e-d56ba9d2e5cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324740186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.324740186
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3484118630
Short name T278
Test name
Test status
Simulation time 34702157495 ps
CPU time 204.3 seconds
Started Jul 19 04:40:43 PM PDT 24
Finished Jul 19 04:44:11 PM PDT 24
Peak memory 234628 kb
Host smart-972755b6-049f-434d-8b33-9ea76b948051
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484118630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3484118630
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1996174340
Short name T38
Test name
Test status
Simulation time 1377144918 ps
CPU time 18.68 seconds
Started Jul 19 04:40:52 PM PDT 24
Finished Jul 19 04:41:16 PM PDT 24
Peak memory 219252 kb
Host smart-9a53fc19-ead4-46e6-ab2c-4b5453dc37a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996174340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1996174340
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3722010686
Short name T316
Test name
Test status
Simulation time 4168359903 ps
CPU time 31.41 seconds
Started Jul 19 04:40:48 PM PDT 24
Finished Jul 19 04:41:22 PM PDT 24
Peak memory 211584 kb
Host smart-0946b766-b12b-434b-a4bd-797cdeb2f6c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3722010686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3722010686
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2015349974
Short name T74
Test name
Test status
Simulation time 47156712291 ps
CPU time 73.76 seconds
Started Jul 19 04:40:48 PM PDT 24
Finished Jul 19 04:42:04 PM PDT 24
Peak memory 216240 kb
Host smart-42b0b560-bc03-4404-986e-d660ffb598ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015349974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2015349974
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3399469146
Short name T115
Test name
Test status
Simulation time 23179943787 ps
CPU time 120.19 seconds
Started Jul 19 04:40:43 PM PDT 24
Finished Jul 19 04:42:46 PM PDT 24
Peak memory 220564 kb
Host smart-6dec0ec1-f7f3-4487-b527-999b2da5d735
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399469146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3399469146
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.368419698
Short name T220
Test name
Test status
Simulation time 6825027226 ps
CPU time 27.74 seconds
Started Jul 19 04:41:03 PM PDT 24
Finished Jul 19 04:41:40 PM PDT 24
Peak memory 217460 kb
Host smart-8441249f-2022-4fbe-89f6-fd5bcd546968
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368419698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.368419698
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2623701598
Short name T233
Test name
Test status
Simulation time 77162024390 ps
CPU time 323.27 seconds
Started Jul 19 04:40:52 PM PDT 24
Finished Jul 19 04:46:21 PM PDT 24
Peak memory 219108 kb
Host smart-51f08543-86a0-4790-81b8-a42cdd7dd473
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623701598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2623701598
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3401033203
Short name T338
Test name
Test status
Simulation time 2152555427 ps
CPU time 31.71 seconds
Started Jul 19 04:40:46 PM PDT 24
Finished Jul 19 04:41:21 PM PDT 24
Peak memory 219380 kb
Host smart-1a16e6b6-6ea8-420f-b1b6-8c7f4d412c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401033203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3401033203
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.4197685952
Short name T177
Test name
Test status
Simulation time 14003797322 ps
CPU time 19.15 seconds
Started Jul 19 04:40:53 PM PDT 24
Finished Jul 19 04:41:17 PM PDT 24
Peak memory 211932 kb
Host smart-e4a4a480-4b37-415e-8c0a-7bf0f6f6c208
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4197685952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.4197685952
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.1072383860
Short name T150
Test name
Test status
Simulation time 7220965234 ps
CPU time 48.58 seconds
Started Jul 19 04:40:52 PM PDT 24
Finished Jul 19 04:41:46 PM PDT 24
Peak memory 217424 kb
Host smart-07e426f9-8d91-463e-b11a-ecbbdba42836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072383860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.1072383860
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.772879247
Short name T300
Test name
Test status
Simulation time 2693821562 ps
CPU time 40.79 seconds
Started Jul 19 04:40:53 PM PDT 24
Finished Jul 19 04:41:39 PM PDT 24
Peak memory 219500 kb
Host smart-d122e9d9-ee23-4081-acf2-4d7cffb887a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772879247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.772879247
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3513820888
Short name T303
Test name
Test status
Simulation time 9584962202 ps
CPU time 22.38 seconds
Started Jul 19 04:40:56 PM PDT 24
Finished Jul 19 04:41:25 PM PDT 24
Peak memory 213272 kb
Host smart-b0087254-a894-46f8-a1c2-02d9f645cecf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513820888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3513820888
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.817553480
Short name T326
Test name
Test status
Simulation time 69217850891 ps
CPU time 617.72 seconds
Started Jul 19 04:41:13 PM PDT 24
Finished Jul 19 04:51:46 PM PDT 24
Peak memory 219404 kb
Host smart-632ac70a-fec5-4816-84a4-2a0471ab0995
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817553480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.817553480
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.715180221
Short name T126
Test name
Test status
Simulation time 32131036543 ps
CPU time 61.24 seconds
Started Jul 19 04:40:47 PM PDT 24
Finished Jul 19 04:41:51 PM PDT 24
Peak memory 219328 kb
Host smart-51d5ecb6-0e43-4567-baa9-7f864d298a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715180221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.715180221
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.640793769
Short name T202
Test name
Test status
Simulation time 5933775567 ps
CPU time 27.28 seconds
Started Jul 19 04:40:48 PM PDT 24
Finished Jul 19 04:41:17 PM PDT 24
Peak memory 219348 kb
Host smart-74d1f3b1-cfe1-4695-a067-cc457ee3b355
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=640793769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.640793769
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1164438595
Short name T120
Test name
Test status
Simulation time 8213828694 ps
CPU time 45.17 seconds
Started Jul 19 04:40:49 PM PDT 24
Finished Jul 19 04:41:38 PM PDT 24
Peak memory 217316 kb
Host smart-cb9a2ca2-e1a7-4a11-a5ca-5fa45ac0f3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164438595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1164438595
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2599395771
Short name T331
Test name
Test status
Simulation time 36794371325 ps
CPU time 106.3 seconds
Started Jul 19 04:40:53 PM PDT 24
Finished Jul 19 04:42:46 PM PDT 24
Peak memory 219868 kb
Host smart-7b60ad2b-f11e-4bea-96e9-71abc048bed1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599395771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2599395771
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3353895009
Short name T23
Test name
Test status
Simulation time 171007059 ps
CPU time 8.2 seconds
Started Jul 19 04:40:50 PM PDT 24
Finished Jul 19 04:41:02 PM PDT 24
Peak memory 217080 kb
Host smart-aa5efb6f-bab3-42b3-9536-3cec14d47c16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353895009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3353895009
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1806002273
Short name T232
Test name
Test status
Simulation time 105456960759 ps
CPU time 317.39 seconds
Started Jul 19 04:40:58 PM PDT 24
Finished Jul 19 04:46:23 PM PDT 24
Peak memory 230012 kb
Host smart-6ed941b3-66d6-45bb-97c4-a4b6bfa1bff4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806002273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1806002273
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2522744022
Short name T363
Test name
Test status
Simulation time 354188291 ps
CPU time 18.82 seconds
Started Jul 19 04:40:52 PM PDT 24
Finished Jul 19 04:41:15 PM PDT 24
Peak memory 219276 kb
Host smart-79fa19b0-3f16-46b3-bc5c-e9223232f2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522744022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2522744022
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2949261789
Short name T334
Test name
Test status
Simulation time 3146086323 ps
CPU time 15.17 seconds
Started Jul 19 04:40:59 PM PDT 24
Finished Jul 19 04:41:22 PM PDT 24
Peak memory 219336 kb
Host smart-8800dcb5-6a25-4e42-a70c-b4b2aaf357c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2949261789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2949261789
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1602193114
Short name T6
Test name
Test status
Simulation time 16329980366 ps
CPU time 41.89 seconds
Started Jul 19 04:41:09 PM PDT 24
Finished Jul 19 04:42:04 PM PDT 24
Peak memory 216564 kb
Host smart-ad46d5a4-3122-47f9-b75b-f68cb11b6e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602193114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1602193114
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.190759150
Short name T317
Test name
Test status
Simulation time 8052963134 ps
CPU time 50.89 seconds
Started Jul 19 04:40:50 PM PDT 24
Finished Jul 19 04:41:45 PM PDT 24
Peak memory 216736 kb
Host smart-9104568d-37ab-46e9-b46f-c07213b7e2e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190759150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.190759150
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2715770278
Short name T255
Test name
Test status
Simulation time 6072258632 ps
CPU time 26.7 seconds
Started Jul 19 04:40:30 PM PDT 24
Finished Jul 19 04:40:59 PM PDT 24
Peak memory 213216 kb
Host smart-77fe2f74-fc8b-41c1-a45d-20445694f40d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715770278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2715770278
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2187681385
Short name T360
Test name
Test status
Simulation time 17758776770 ps
CPU time 45.69 seconds
Started Jul 19 04:40:31 PM PDT 24
Finished Jul 19 04:41:18 PM PDT 24
Peak memory 219396 kb
Host smart-f95fc5d0-66fd-4c5e-a84f-80b64b9f149c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187681385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2187681385
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2781876261
Short name T131
Test name
Test status
Simulation time 175848270 ps
CPU time 10.32 seconds
Started Jul 19 04:40:28 PM PDT 24
Finished Jul 19 04:40:39 PM PDT 24
Peak memory 219292 kb
Host smart-009b07c2-ed20-4e48-8d45-232791174a9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2781876261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2781876261
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2280120833
Short name T302
Test name
Test status
Simulation time 16490432816 ps
CPU time 41.52 seconds
Started Jul 19 04:40:25 PM PDT 24
Finished Jul 19 04:41:07 PM PDT 24
Peak memory 216020 kb
Host smart-674864a9-683e-414b-a30b-49f54a230bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280120833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2280120833
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3693028415
Short name T145
Test name
Test status
Simulation time 789112325 ps
CPU time 27.85 seconds
Started Jul 19 04:40:27 PM PDT 24
Finished Jul 19 04:40:56 PM PDT 24
Peak memory 219360 kb
Host smart-53a1df83-1536-4597-be20-564a496f82f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693028415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3693028415
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2625199057
Short name T222
Test name
Test status
Simulation time 2234128887 ps
CPU time 20.88 seconds
Started Jul 19 04:41:09 PM PDT 24
Finished Jul 19 04:41:43 PM PDT 24
Peak memory 217156 kb
Host smart-51ad69a2-847d-4243-aabd-e4433de91c2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625199057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2625199057
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.168152253
Short name T230
Test name
Test status
Simulation time 3681174317 ps
CPU time 139.87 seconds
Started Jul 19 04:40:55 PM PDT 24
Finished Jul 19 04:43:21 PM PDT 24
Peak memory 229744 kb
Host smart-4e66dc76-f343-491c-a233-a80e66cf7142
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168152253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.168152253
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.4011534198
Short name T307
Test name
Test status
Simulation time 935624643 ps
CPU time 24.39 seconds
Started Jul 19 04:40:51 PM PDT 24
Finished Jul 19 04:41:20 PM PDT 24
Peak memory 218888 kb
Host smart-00a9df14-f724-4122-96e9-77b590a873bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011534198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.4011534198
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.643090062
Short name T221
Test name
Test status
Simulation time 5407018781 ps
CPU time 18.04 seconds
Started Jul 19 04:40:50 PM PDT 24
Finished Jul 19 04:41:12 PM PDT 24
Peak memory 211948 kb
Host smart-ccd7dec5-d33e-44f8-9318-4f9075cbdb2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=643090062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.643090062
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1059358671
Short name T52
Test name
Test status
Simulation time 17457171973 ps
CPU time 64 seconds
Started Jul 19 04:40:58 PM PDT 24
Finished Jul 19 04:42:10 PM PDT 24
Peak memory 216924 kb
Host smart-c5f5c3d1-87f3-4543-a13c-d52fd8294d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059358671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1059358671
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.224209830
Short name T329
Test name
Test status
Simulation time 83769263844 ps
CPU time 80.14 seconds
Started Jul 19 04:40:54 PM PDT 24
Finished Jul 19 04:42:20 PM PDT 24
Peak memory 219340 kb
Host smart-c4022fb8-f8bb-423b-a7f3-f5b6d6f090fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224209830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.224209830
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1048342777
Short name T155
Test name
Test status
Simulation time 1371065645 ps
CPU time 16.76 seconds
Started Jul 19 04:41:06 PM PDT 24
Finished Jul 19 04:41:34 PM PDT 24
Peak memory 217092 kb
Host smart-67a1ed09-a234-4589-ae08-d91587a01ba8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048342777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1048342777
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1066644196
Short name T34
Test name
Test status
Simulation time 228845696738 ps
CPU time 546.7 seconds
Started Jul 19 04:40:57 PM PDT 24
Finished Jul 19 04:50:11 PM PDT 24
Peak memory 219552 kb
Host smart-e183716c-aec0-4671-be85-0edc0460a2fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066644196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1066644196
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3741340983
Short name T181
Test name
Test status
Simulation time 15019539445 ps
CPU time 60.74 seconds
Started Jul 19 04:41:01 PM PDT 24
Finished Jul 19 04:42:10 PM PDT 24
Peak memory 219316 kb
Host smart-13ee7b90-243c-4a09-8523-26b2f5393b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741340983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3741340983
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2603210661
Short name T294
Test name
Test status
Simulation time 4124110681 ps
CPU time 32.58 seconds
Started Jul 19 04:41:05 PM PDT 24
Finished Jul 19 04:41:48 PM PDT 24
Peak memory 211484 kb
Host smart-9f59199e-75d0-42fa-96ea-b478a5a0ab8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2603210661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2603210661
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.4195567669
Short name T129
Test name
Test status
Simulation time 497315708 ps
CPU time 19.59 seconds
Started Jul 19 04:40:58 PM PDT 24
Finished Jul 19 04:41:25 PM PDT 24
Peak memory 216148 kb
Host smart-33039898-8b65-47ed-b889-69a182309020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195567669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.4195567669
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2101461685
Short name T143
Test name
Test status
Simulation time 17355673612 ps
CPU time 34.63 seconds
Started Jul 19 04:40:50 PM PDT 24
Finished Jul 19 04:41:29 PM PDT 24
Peak memory 216656 kb
Host smart-a104638c-9095-4c80-b827-b6ee72d8952a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101461685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2101461685
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1472854752
Short name T59
Test name
Test status
Simulation time 14572014830 ps
CPU time 30.16 seconds
Started Jul 19 04:41:04 PM PDT 24
Finished Jul 19 04:41:43 PM PDT 24
Peak memory 213312 kb
Host smart-096c3ec5-7a59-4092-bce8-fabe389a1a82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472854752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1472854752
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.191134249
Short name T308
Test name
Test status
Simulation time 11364845200 ps
CPU time 218.89 seconds
Started Jul 19 04:40:50 PM PDT 24
Finished Jul 19 04:44:33 PM PDT 24
Peak memory 241888 kb
Host smart-a3390686-5615-4281-92a2-ae376396855a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191134249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.191134249
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1252801896
Short name T320
Test name
Test status
Simulation time 2537090236 ps
CPU time 19.43 seconds
Started Jul 19 04:41:02 PM PDT 24
Finished Jul 19 04:41:30 PM PDT 24
Peak memory 219312 kb
Host smart-b5052cb4-2a45-44bf-aae1-247fe7928c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252801896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1252801896
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.908112292
Short name T285
Test name
Test status
Simulation time 29193024288 ps
CPU time 28.45 seconds
Started Jul 19 04:40:58 PM PDT 24
Finished Jul 19 04:41:34 PM PDT 24
Peak memory 219332 kb
Host smart-2b252629-99af-481b-943c-a131fff05bd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=908112292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.908112292
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.367462806
Short name T280
Test name
Test status
Simulation time 45221819537 ps
CPU time 44.62 seconds
Started Jul 19 04:40:50 PM PDT 24
Finished Jul 19 04:41:39 PM PDT 24
Peak memory 217104 kb
Host smart-2137600e-48b8-4777-8a46-9491f3053ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367462806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.367462806
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1146273691
Short name T267
Test name
Test status
Simulation time 1037707863 ps
CPU time 65.94 seconds
Started Jul 19 04:41:00 PM PDT 24
Finished Jul 19 04:42:14 PM PDT 24
Peak memory 220160 kb
Host smart-125aedd8-08ff-437d-83ee-4b8c1fe6db1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146273691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1146273691
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2908507699
Short name T62
Test name
Test status
Simulation time 32844483126 ps
CPU time 24.61 seconds
Started Jul 19 04:40:50 PM PDT 24
Finished Jul 19 04:41:19 PM PDT 24
Peak memory 213280 kb
Host smart-e46a3f9f-1ad7-479f-8e14-06f9cd442748
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908507699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2908507699
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3980242048
Short name T42
Test name
Test status
Simulation time 5135677571 ps
CPU time 228.06 seconds
Started Jul 19 04:40:55 PM PDT 24
Finished Jul 19 04:44:50 PM PDT 24
Peak memory 224316 kb
Host smart-15d85ee0-d825-4041-97de-c264852fcabe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980242048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3980242048
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.710915044
Short name T213
Test name
Test status
Simulation time 2336003460 ps
CPU time 33.15 seconds
Started Jul 19 04:41:05 PM PDT 24
Finished Jul 19 04:41:48 PM PDT 24
Peak memory 215828 kb
Host smart-64963235-9ac9-438c-9c57-f3ca1a2b75db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710915044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.710915044
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2403431528
Short name T313
Test name
Test status
Simulation time 15301337917 ps
CPU time 31.58 seconds
Started Jul 19 04:41:02 PM PDT 24
Finished Jul 19 04:41:42 PM PDT 24
Peak memory 211980 kb
Host smart-5a5ea39b-d579-480b-8921-0bbfbc3f103d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2403431528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2403431528
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1689109969
Short name T27
Test name
Test status
Simulation time 31485946843 ps
CPU time 62.5 seconds
Started Jul 19 04:40:50 PM PDT 24
Finished Jul 19 04:41:58 PM PDT 24
Peak memory 216736 kb
Host smart-2a91717d-58aa-48f2-a99a-bfea09111dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689109969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1689109969
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.412249072
Short name T167
Test name
Test status
Simulation time 6404316350 ps
CPU time 74.73 seconds
Started Jul 19 04:41:07 PM PDT 24
Finished Jul 19 04:42:33 PM PDT 24
Peak memory 219324 kb
Host smart-194c6f27-756d-45b3-a8ef-1c1678c66671
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412249072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.412249072
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3210309392
Short name T249
Test name
Test status
Simulation time 2955367908 ps
CPU time 26.59 seconds
Started Jul 19 04:40:51 PM PDT 24
Finished Jul 19 04:41:22 PM PDT 24
Peak memory 213272 kb
Host smart-28d1d00d-7928-47ed-90e4-771f7b542fa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210309392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3210309392
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2246632568
Short name T277
Test name
Test status
Simulation time 224300300235 ps
CPU time 408.89 seconds
Started Jul 19 04:40:58 PM PDT 24
Finished Jul 19 04:47:54 PM PDT 24
Peak memory 236888 kb
Host smart-ca0323d7-40ef-41ba-9df0-729e5500c1e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246632568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2246632568
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3766997667
Short name T284
Test name
Test status
Simulation time 346178025 ps
CPU time 18.75 seconds
Started Jul 19 04:41:09 PM PDT 24
Finished Jul 19 04:41:41 PM PDT 24
Peak memory 219284 kb
Host smart-7f08b78a-66a2-4a8c-a549-152fcf687a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766997667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3766997667
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1382261368
Short name T137
Test name
Test status
Simulation time 5590419234 ps
CPU time 18.25 seconds
Started Jul 19 04:41:04 PM PDT 24
Finished Jul 19 04:41:33 PM PDT 24
Peak memory 219348 kb
Host smart-f0776a60-928c-4607-a562-32dd1d32afcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1382261368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1382261368
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.481006662
Short name T127
Test name
Test status
Simulation time 16389673302 ps
CPU time 66.7 seconds
Started Jul 19 04:41:04 PM PDT 24
Finished Jul 19 04:42:21 PM PDT 24
Peak memory 216116 kb
Host smart-31935e4c-98fd-48b6-95e9-5c5fb141aff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481006662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.481006662
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.974055576
Short name T212
Test name
Test status
Simulation time 3155916092 ps
CPU time 41.95 seconds
Started Jul 19 04:40:57 PM PDT 24
Finished Jul 19 04:41:45 PM PDT 24
Peak memory 216656 kb
Host smart-8a55429d-e596-45b0-889b-e5840be5ec20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974055576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.974055576
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.41844835
Short name T256
Test name
Test status
Simulation time 174399183 ps
CPU time 8.15 seconds
Started Jul 19 04:41:21 PM PDT 24
Finished Jul 19 04:41:45 PM PDT 24
Peak memory 216568 kb
Host smart-b1d8027b-6abb-495a-b6a1-7062612459e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41844835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.41844835
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.555245546
Short name T7
Test name
Test status
Simulation time 289552042921 ps
CPU time 965.04 seconds
Started Jul 19 04:41:04 PM PDT 24
Finished Jul 19 04:57:19 PM PDT 24
Peak memory 219520 kb
Host smart-7b7701a9-4919-4248-9822-7eabf1292975
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555245546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.555245546
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1222536294
Short name T210
Test name
Test status
Simulation time 2014091287 ps
CPU time 31.85 seconds
Started Jul 19 04:41:09 PM PDT 24
Finished Jul 19 04:41:54 PM PDT 24
Peak memory 219256 kb
Host smart-5e26073a-5738-4b33-b407-24e32640a1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222536294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1222536294
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.643739869
Short name T168
Test name
Test status
Simulation time 8694159834 ps
CPU time 32.46 seconds
Started Jul 19 04:41:03 PM PDT 24
Finished Jul 19 04:41:45 PM PDT 24
Peak memory 219380 kb
Host smart-30644f0f-cf51-446d-acf3-ab2f3e8340a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=643739869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.643739869
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1747997759
Short name T116
Test name
Test status
Simulation time 32997753561 ps
CPU time 66.43 seconds
Started Jul 19 04:41:04 PM PDT 24
Finished Jul 19 04:42:21 PM PDT 24
Peak memory 216032 kb
Host smart-46c970c4-2575-4228-8fbb-b97dcd62c71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747997759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1747997759
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2639275743
Short name T76
Test name
Test status
Simulation time 2590117111 ps
CPU time 42.92 seconds
Started Jul 19 04:41:02 PM PDT 24
Finished Jul 19 04:41:53 PM PDT 24
Peak memory 218648 kb
Host smart-d27e6fe4-ed05-46aa-b66c-55d52d2f4adc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639275743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2639275743
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.764067161
Short name T156
Test name
Test status
Simulation time 7837086847 ps
CPU time 29.51 seconds
Started Jul 19 04:41:01 PM PDT 24
Finished Jul 19 04:41:38 PM PDT 24
Peak memory 217492 kb
Host smart-0ea2deb6-d497-4269-80b5-9678aa068ccc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764067161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.764067161
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3716187426
Short name T199
Test name
Test status
Simulation time 75344000733 ps
CPU time 522.19 seconds
Started Jul 19 04:41:04 PM PDT 24
Finished Jul 19 04:49:55 PM PDT 24
Peak memory 233960 kb
Host smart-707d2931-8e54-45c2-aac1-b2a62308cd0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716187426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3716187426
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1575053244
Short name T124
Test name
Test status
Simulation time 63595637580 ps
CPU time 51.62 seconds
Started Jul 19 04:41:10 PM PDT 24
Finished Jul 19 04:42:15 PM PDT 24
Peak memory 219324 kb
Host smart-73e0eca8-489f-4361-9991-e1049183e0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575053244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1575053244
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2785289390
Short name T203
Test name
Test status
Simulation time 24610767592 ps
CPU time 32.29 seconds
Started Jul 19 04:40:59 PM PDT 24
Finished Jul 19 04:41:39 PM PDT 24
Peak memory 212056 kb
Host smart-b291b0ea-4cee-452d-9e2a-a8fc51d1a46d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2785289390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2785289390
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.445458921
Short name T31
Test name
Test status
Simulation time 11787565465 ps
CPU time 52.87 seconds
Started Jul 19 04:41:06 PM PDT 24
Finished Jul 19 04:42:10 PM PDT 24
Peak memory 216148 kb
Host smart-14360712-bcc0-467f-a4ce-bd0301bf4cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445458921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.445458921
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2907468247
Short name T296
Test name
Test status
Simulation time 3043155952 ps
CPU time 72.86 seconds
Started Jul 19 04:41:06 PM PDT 24
Finished Jul 19 04:42:31 PM PDT 24
Peak memory 219572 kb
Host smart-7fcd8242-32b4-4d82-ba37-928906eac5d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907468247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2907468247
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2406605037
Short name T244
Test name
Test status
Simulation time 6145771010 ps
CPU time 17.32 seconds
Started Jul 19 04:40:52 PM PDT 24
Finished Jul 19 04:41:15 PM PDT 24
Peak memory 213300 kb
Host smart-6885f2d4-2b67-464e-96f4-7f408a6c2f47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406605037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2406605037
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3554709667
Short name T153
Test name
Test status
Simulation time 111908747433 ps
CPU time 360.48 seconds
Started Jul 19 04:41:10 PM PDT 24
Finished Jul 19 04:47:24 PM PDT 24
Peak memory 235904 kb
Host smart-671a4f3a-ac7d-4be5-afc4-eb8d1659eeca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554709667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3554709667
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.4070497615
Short name T197
Test name
Test status
Simulation time 23516085308 ps
CPU time 55.24 seconds
Started Jul 19 04:41:06 PM PDT 24
Finished Jul 19 04:42:13 PM PDT 24
Peak memory 219348 kb
Host smart-befeb4d3-b4d8-449b-a010-b61820e993cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070497615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.4070497615
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.821984053
Short name T172
Test name
Test status
Simulation time 852737567 ps
CPU time 15.35 seconds
Started Jul 19 04:41:12 PM PDT 24
Finished Jul 19 04:41:42 PM PDT 24
Peak memory 219280 kb
Host smart-f34313ad-10da-4470-a5de-df685412a8f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=821984053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.821984053
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1217859587
Short name T132
Test name
Test status
Simulation time 45910245718 ps
CPU time 114.6 seconds
Started Jul 19 04:41:07 PM PDT 24
Finished Jul 19 04:43:13 PM PDT 24
Peak memory 220348 kb
Host smart-d83729c1-91a2-4976-a379-dd50e4e69aef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217859587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1217859587
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.50619149
Short name T349
Test name
Test status
Simulation time 85075579143 ps
CPU time 4910.85 seconds
Started Jul 19 04:41:12 PM PDT 24
Finished Jul 19 06:03:18 PM PDT 24
Peak memory 239736 kb
Host smart-5dee186d-3ea4-48bf-a0be-9ab07798bdf3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50619149 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.50619149
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.569022371
Short name T259
Test name
Test status
Simulation time 167662620 ps
CPU time 8.58 seconds
Started Jul 19 04:41:03 PM PDT 24
Finished Jul 19 04:41:21 PM PDT 24
Peak memory 217148 kb
Host smart-5c69bb6e-663c-4213-ae9d-297c05adb982
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569022371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.569022371
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3475901503
Short name T239
Test name
Test status
Simulation time 862981803080 ps
CPU time 626.85 seconds
Started Jul 19 04:41:08 PM PDT 24
Finished Jul 19 04:51:48 PM PDT 24
Peak memory 234348 kb
Host smart-8b982fe3-4fbc-4db2-8fda-3b4aa3602186
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475901503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3475901503
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2379376220
Short name T297
Test name
Test status
Simulation time 346118657 ps
CPU time 18.54 seconds
Started Jul 19 04:41:11 PM PDT 24
Finished Jul 19 04:41:44 PM PDT 24
Peak memory 219280 kb
Host smart-23061b59-f03c-4600-bdc6-874705aeaca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379376220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2379376220
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1479166916
Short name T235
Test name
Test status
Simulation time 2344836864 ps
CPU time 13.84 seconds
Started Jul 19 04:41:08 PM PDT 24
Finished Jul 19 04:41:35 PM PDT 24
Peak memory 211012 kb
Host smart-2a4dc50b-7d11-46f6-8417-417211c6458e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1479166916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1479166916
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.980000678
Short name T176
Test name
Test status
Simulation time 31535955501 ps
CPU time 42.37 seconds
Started Jul 19 04:41:01 PM PDT 24
Finished Jul 19 04:41:52 PM PDT 24
Peak memory 217200 kb
Host smart-937bfa9a-c818-4898-b523-8832de6724ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980000678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.980000678
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.4018607534
Short name T114
Test name
Test status
Simulation time 10000027447 ps
CPU time 107.79 seconds
Started Jul 19 04:41:05 PM PDT 24
Finished Jul 19 04:43:03 PM PDT 24
Peak memory 219876 kb
Host smart-d5d2e2f0-3184-467e-a730-093c16683494
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018607534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.4018607534
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.4274524566
Short name T170
Test name
Test status
Simulation time 9213636413 ps
CPU time 21.1 seconds
Started Jul 19 04:40:59 PM PDT 24
Finished Jul 19 04:41:28 PM PDT 24
Peak memory 213268 kb
Host smart-542db683-de90-4a80-a184-0a1a188d11d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274524566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.4274524566
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.240175676
Short name T36
Test name
Test status
Simulation time 75863750074 ps
CPU time 372.16 seconds
Started Jul 19 04:41:10 PM PDT 24
Finished Jul 19 04:47:36 PM PDT 24
Peak memory 233900 kb
Host smart-38f306b5-c85f-4410-9f53-0fbf277fe9d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240175676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.240175676
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.4117017926
Short name T205
Test name
Test status
Simulation time 5259998730 ps
CPU time 49.2 seconds
Started Jul 19 04:41:08 PM PDT 24
Finished Jul 19 04:42:10 PM PDT 24
Peak memory 219276 kb
Host smart-e21af6f3-3b5b-47f3-8dd2-3fa9b18a28c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117017926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.4117017926
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1728114017
Short name T214
Test name
Test status
Simulation time 836900699 ps
CPU time 15.3 seconds
Started Jul 19 04:41:02 PM PDT 24
Finished Jul 19 04:41:25 PM PDT 24
Peak memory 219272 kb
Host smart-4f3c9d6e-95f7-4813-9781-6c7be6b34b05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1728114017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1728114017
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.725847228
Short name T314
Test name
Test status
Simulation time 6419976442 ps
CPU time 57.18 seconds
Started Jul 19 04:41:03 PM PDT 24
Finished Jul 19 04:42:09 PM PDT 24
Peak memory 217300 kb
Host smart-588434c9-8bb1-4d14-a2bc-25353d449726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725847228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.725847228
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.364559124
Short name T134
Test name
Test status
Simulation time 982200463 ps
CPU time 33.57 seconds
Started Jul 19 04:41:08 PM PDT 24
Finished Jul 19 04:41:54 PM PDT 24
Peak memory 219444 kb
Host smart-c77e17b9-4000-4194-9bf5-8cb354e46b6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364559124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.364559124
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2745877244
Short name T204
Test name
Test status
Simulation time 1636042008 ps
CPU time 13.81 seconds
Started Jul 19 04:40:36 PM PDT 24
Finished Jul 19 04:40:52 PM PDT 24
Peak memory 216852 kb
Host smart-2acf3b2d-33c6-4dcd-aed3-67800d863711
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745877244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2745877244
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.954969996
Short name T228
Test name
Test status
Simulation time 35812792298 ps
CPU time 244.15 seconds
Started Jul 19 04:40:30 PM PDT 24
Finished Jul 19 04:44:36 PM PDT 24
Peak memory 234872 kb
Host smart-66bea6d9-d728-43a5-8fc6-a5b5fcfea090
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954969996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.954969996
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3912071263
Short name T180
Test name
Test status
Simulation time 35621649853 ps
CPU time 65.62 seconds
Started Jul 19 04:40:36 PM PDT 24
Finished Jul 19 04:41:44 PM PDT 24
Peak memory 219256 kb
Host smart-39a0ca47-58b0-4617-b8dd-a83ba064b79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912071263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3912071263
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2389804846
Short name T301
Test name
Test status
Simulation time 4214650012 ps
CPU time 34.01 seconds
Started Jul 19 04:40:27 PM PDT 24
Finished Jul 19 04:41:02 PM PDT 24
Peak memory 211404 kb
Host smart-638e13cd-b5c5-4d8e-9ff0-f508ddaedfe4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2389804846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2389804846
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3036424193
Short name T25
Test name
Test status
Simulation time 2439961480 ps
CPU time 130.61 seconds
Started Jul 19 04:40:27 PM PDT 24
Finished Jul 19 04:42:39 PM PDT 24
Peak memory 238440 kb
Host smart-05d2ab5c-4b80-4c85-bc9b-bd8a8a52229e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036424193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3036424193
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2253959674
Short name T138
Test name
Test status
Simulation time 1031485502 ps
CPU time 26.75 seconds
Started Jul 19 04:40:29 PM PDT 24
Finished Jul 19 04:40:57 PM PDT 24
Peak memory 215788 kb
Host smart-a93dbea6-ec81-4884-a1c5-8c4eeb17d123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253959674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2253959674
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3653225188
Short name T157
Test name
Test status
Simulation time 15431072231 ps
CPU time 132.7 seconds
Started Jul 19 04:40:27 PM PDT 24
Finished Jul 19 04:42:41 PM PDT 24
Peak memory 220944 kb
Host smart-5bff8a43-a743-490d-9662-c465aeb13094
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653225188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3653225188
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.251638428
Short name T21
Test name
Test status
Simulation time 1390298154 ps
CPU time 13.23 seconds
Started Jul 19 04:40:51 PM PDT 24
Finished Jul 19 04:41:09 PM PDT 24
Peak memory 213236 kb
Host smart-80aa1b85-568c-4757-b598-7b8c9b7c75a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251638428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.251638428
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1939290815
Short name T35
Test name
Test status
Simulation time 7529674946 ps
CPU time 195.36 seconds
Started Jul 19 04:41:06 PM PDT 24
Finished Jul 19 04:44:32 PM PDT 24
Peak memory 224752 kb
Host smart-b4161a9a-cc7e-45f3-a3b3-599d98f2037d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939290815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1939290815
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3002092449
Short name T240
Test name
Test status
Simulation time 2738648390 ps
CPU time 23.5 seconds
Started Jul 19 04:41:01 PM PDT 24
Finished Jul 19 04:41:32 PM PDT 24
Peak memory 218796 kb
Host smart-f80c1d98-0609-4809-aa31-42b75e0ad3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002092449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3002092449
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2645199296
Short name T353
Test name
Test status
Simulation time 351396935 ps
CPU time 10.02 seconds
Started Jul 19 04:41:10 PM PDT 24
Finished Jul 19 04:41:33 PM PDT 24
Peak memory 219252 kb
Host smart-c9bb8aec-165c-4b84-b71f-d51ecef978d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2645199296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2645199296
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2598177683
Short name T75
Test name
Test status
Simulation time 810723785 ps
CPU time 19.91 seconds
Started Jul 19 04:41:12 PM PDT 24
Finished Jul 19 04:41:47 PM PDT 24
Peak memory 218000 kb
Host smart-2a08861f-56e5-4808-a140-18dc687d089c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598177683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2598177683
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.4143328749
Short name T226
Test name
Test status
Simulation time 6426064787 ps
CPU time 67.27 seconds
Started Jul 19 04:40:52 PM PDT 24
Finished Jul 19 04:42:04 PM PDT 24
Peak memory 219356 kb
Host smart-8dff5ef6-3081-489f-85eb-5632317f1ced
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143328749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.4143328749
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1503503210
Short name T169
Test name
Test status
Simulation time 9497373268 ps
CPU time 22.74 seconds
Started Jul 19 04:41:07 PM PDT 24
Finished Jul 19 04:41:42 PM PDT 24
Peak memory 217432 kb
Host smart-295ba00a-c23c-48af-9e8d-96cb5bbe9c1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503503210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1503503210
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1273778161
Short name T227
Test name
Test status
Simulation time 187273771628 ps
CPU time 453.9 seconds
Started Jul 19 04:41:06 PM PDT 24
Finished Jul 19 04:48:51 PM PDT 24
Peak memory 235076 kb
Host smart-dfb3dd81-b6fc-4edf-8906-0cba1b168e86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273778161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1273778161
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.386301411
Short name T39
Test name
Test status
Simulation time 1831795558 ps
CPU time 18.98 seconds
Started Jul 19 04:41:11 PM PDT 24
Finished Jul 19 04:41:44 PM PDT 24
Peak memory 219256 kb
Host smart-a7af8371-ae10-4833-9854-fa33224a9067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386301411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.386301411
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.331724710
Short name T223
Test name
Test status
Simulation time 3581294011 ps
CPU time 30.15 seconds
Started Jul 19 04:41:02 PM PDT 24
Finished Jul 19 04:41:40 PM PDT 24
Peak memory 211308 kb
Host smart-41ae7483-9ec5-4d92-a8c3-f3d5db13ff9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=331724710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.331724710
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1366719326
Short name T1
Test name
Test status
Simulation time 360342730 ps
CPU time 19.55 seconds
Started Jul 19 04:41:11 PM PDT 24
Finished Jul 19 04:41:45 PM PDT 24
Peak memory 215956 kb
Host smart-d42daed9-9321-41c7-bcb8-18fb868ce350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366719326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1366719326
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.550614921
Short name T215
Test name
Test status
Simulation time 3688246782 ps
CPU time 52.25 seconds
Started Jul 19 04:40:53 PM PDT 24
Finished Jul 19 04:41:51 PM PDT 24
Peak memory 220916 kb
Host smart-1523fae5-0e8b-4169-a770-759b80a2227c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550614921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.550614921
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.956750678
Short name T152
Test name
Test status
Simulation time 17653207007 ps
CPU time 30.23 seconds
Started Jul 19 04:41:15 PM PDT 24
Finished Jul 19 04:42:01 PM PDT 24
Peak memory 217168 kb
Host smart-1162ee5f-1133-4d6e-9c17-7a3723f78159
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956750678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.956750678
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2788238036
Short name T44
Test name
Test status
Simulation time 28504652440 ps
CPU time 318.21 seconds
Started Jul 19 04:41:06 PM PDT 24
Finished Jul 19 04:46:34 PM PDT 24
Peak memory 234920 kb
Host smart-f6d24fc7-d458-4f35-9f70-5851b82fa6db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788238036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2788238036
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1783758134
Short name T265
Test name
Test status
Simulation time 5475339771 ps
CPU time 28.33 seconds
Started Jul 19 04:41:10 PM PDT 24
Finished Jul 19 04:41:52 PM PDT 24
Peak memory 218708 kb
Host smart-9f781f7c-575d-475d-807b-dfe2eca06654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783758134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1783758134
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.444863108
Short name T272
Test name
Test status
Simulation time 27675031596 ps
CPU time 23.42 seconds
Started Jul 19 04:40:56 PM PDT 24
Finished Jul 19 04:41:26 PM PDT 24
Peak memory 217704 kb
Host smart-e614ef2e-a8a3-4b5b-9508-94c7c233e899
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=444863108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.444863108
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2277448125
Short name T260
Test name
Test status
Simulation time 344251766 ps
CPU time 19.11 seconds
Started Jul 19 04:40:59 PM PDT 24
Finished Jul 19 04:41:26 PM PDT 24
Peak memory 217992 kb
Host smart-d89cd670-9304-4abf-9434-1109c4b89b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277448125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2277448125
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.4139084269
Short name T263
Test name
Test status
Simulation time 4198512116 ps
CPU time 50.64 seconds
Started Jul 19 04:41:05 PM PDT 24
Finished Jul 19 04:42:06 PM PDT 24
Peak memory 219344 kb
Host smart-d371678e-5743-410a-bbc6-d0eecee55b38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139084269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.4139084269
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2129774051
Short name T352
Test name
Test status
Simulation time 8147203493 ps
CPU time 19.41 seconds
Started Jul 19 04:40:50 PM PDT 24
Finished Jul 19 04:41:14 PM PDT 24
Peak memory 217460 kb
Host smart-7be12233-03bf-483c-bdb3-96cc73173793
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129774051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2129774051
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.65425003
Short name T359
Test name
Test status
Simulation time 241787186592 ps
CPU time 525.89 seconds
Started Jul 19 04:41:15 PM PDT 24
Finished Jul 19 04:50:17 PM PDT 24
Peak memory 235608 kb
Host smart-54adf84e-ba9a-46f3-a7a1-95db896874a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65425003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_co
rrupt_sig_fatal_chk.65425003
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3946121553
Short name T279
Test name
Test status
Simulation time 5876954706 ps
CPU time 51.56 seconds
Started Jul 19 04:40:51 PM PDT 24
Finished Jul 19 04:41:47 PM PDT 24
Peak memory 219336 kb
Host smart-b897a0c7-f9e6-4514-b8fb-93cb55b7e609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946121553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3946121553
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3555093693
Short name T193
Test name
Test status
Simulation time 181076041 ps
CPU time 10.39 seconds
Started Jul 19 04:41:10 PM PDT 24
Finished Jul 19 04:41:35 PM PDT 24
Peak memory 219252 kb
Host smart-d86a595a-c1dd-418a-a92f-f0ea869c5467
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3555093693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3555093693
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.875810706
Short name T136
Test name
Test status
Simulation time 27245335062 ps
CPU time 57.85 seconds
Started Jul 19 04:41:09 PM PDT 24
Finished Jul 19 04:42:21 PM PDT 24
Peak memory 216208 kb
Host smart-e563865f-8371-4bc3-9a44-3f4b055f3100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875810706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.875810706
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2426667021
Short name T268
Test name
Test status
Simulation time 3234066422 ps
CPU time 29.5 seconds
Started Jul 19 04:40:55 PM PDT 24
Finished Jul 19 04:41:30 PM PDT 24
Peak memory 214764 kb
Host smart-93108e7c-86e5-4fc6-bbaf-4d6174a58837
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426667021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2426667021
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1128696208
Short name T61
Test name
Test status
Simulation time 4100445073 ps
CPU time 19.93 seconds
Started Jul 19 04:41:06 PM PDT 24
Finished Jul 19 04:41:37 PM PDT 24
Peak memory 217144 kb
Host smart-cd94c753-de56-4de6-9c3c-e7ea04c9b269
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128696208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1128696208
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1694948733
Short name T336
Test name
Test status
Simulation time 6499753169 ps
CPU time 55.6 seconds
Started Jul 19 04:41:15 PM PDT 24
Finished Jul 19 04:42:26 PM PDT 24
Peak memory 219336 kb
Host smart-f833f43e-e4fa-43d0-b3c8-267fab808eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694948733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1694948733
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2491016658
Short name T325
Test name
Test status
Simulation time 4461207290 ps
CPU time 33.44 seconds
Started Jul 19 04:41:06 PM PDT 24
Finished Jul 19 04:41:51 PM PDT 24
Peak memory 219508 kb
Host smart-de1117af-5962-431b-8c0f-cec548718745
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2491016658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2491016658
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2396598825
Short name T182
Test name
Test status
Simulation time 1624725585 ps
CPU time 88.98 seconds
Started Jul 19 04:41:07 PM PDT 24
Finished Jul 19 04:42:49 PM PDT 24
Peak memory 219296 kb
Host smart-79ccadbe-5ff5-4a9a-9039-034dfdd9a73e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396598825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2396598825
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1595133130
Short name T321
Test name
Test status
Simulation time 345648511 ps
CPU time 8.44 seconds
Started Jul 19 04:41:07 PM PDT 24
Finished Jul 19 04:41:28 PM PDT 24
Peak memory 218320 kb
Host smart-704dedfd-8d65-4920-ac79-4c4204494b90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595133130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1595133130
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2294474053
Short name T291
Test name
Test status
Simulation time 10409233337 ps
CPU time 152.41 seconds
Started Jul 19 04:41:13 PM PDT 24
Finished Jul 19 04:44:01 PM PDT 24
Peak memory 240272 kb
Host smart-12ccee8c-37a5-4f80-acc4-3f1ddf2aba3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294474053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2294474053
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2338626585
Short name T340
Test name
Test status
Simulation time 8042882084 ps
CPU time 69.72 seconds
Started Jul 19 04:41:10 PM PDT 24
Finished Jul 19 04:42:34 PM PDT 24
Peak memory 219324 kb
Host smart-81218d45-9f54-4a23-8705-e26340bd241f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338626585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2338626585
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1301575582
Short name T247
Test name
Test status
Simulation time 4225837171 ps
CPU time 34.23 seconds
Started Jul 19 04:41:10 PM PDT 24
Finished Jul 19 04:41:58 PM PDT 24
Peak memory 219404 kb
Host smart-2bb678ef-3416-4d9a-bff8-7bdaf1bf8867
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1301575582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1301575582
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2998253725
Short name T269
Test name
Test status
Simulation time 24670099987 ps
CPU time 60.05 seconds
Started Jul 19 04:41:11 PM PDT 24
Finished Jul 19 04:42:26 PM PDT 24
Peak memory 215908 kb
Host smart-d267df59-6a18-49a6-9b40-a912f7e41036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998253725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2998253725
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.713269809
Short name T358
Test name
Test status
Simulation time 591716399 ps
CPU time 45.77 seconds
Started Jul 19 04:41:16 PM PDT 24
Finished Jul 19 04:42:17 PM PDT 24
Peak memory 219256 kb
Host smart-60e22cd0-0df1-4aee-8085-33cc8fa2ed5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713269809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.713269809
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3420862782
Short name T298
Test name
Test status
Simulation time 2398023871 ps
CPU time 12.6 seconds
Started Jul 19 04:41:01 PM PDT 24
Finished Jul 19 04:41:22 PM PDT 24
Peak memory 217124 kb
Host smart-f5eb7538-a4ea-42af-a64a-938c3f3f28a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420862782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3420862782
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1377052696
Short name T355
Test name
Test status
Simulation time 41004906086 ps
CPU time 449.42 seconds
Started Jul 19 04:41:06 PM PDT 24
Finished Jul 19 04:48:47 PM PDT 24
Peak memory 227300 kb
Host smart-bcca3192-32ae-4a50-8c5f-877e41ecb5d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377052696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1377052696
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3332214923
Short name T29
Test name
Test status
Simulation time 13160789380 ps
CPU time 57.32 seconds
Started Jul 19 04:41:04 PM PDT 24
Finished Jul 19 04:42:11 PM PDT 24
Peak memory 219320 kb
Host smart-b5517336-74f8-4dd5-b8b0-62a35dc32397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332214923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3332214923
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1845883140
Short name T130
Test name
Test status
Simulation time 6293743605 ps
CPU time 19.6 seconds
Started Jul 19 04:41:12 PM PDT 24
Finished Jul 19 04:41:46 PM PDT 24
Peak memory 219308 kb
Host smart-5004cfa5-859e-4275-a69e-0af284ff5f37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1845883140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1845883140
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.350447675
Short name T366
Test name
Test status
Simulation time 9922891320 ps
CPU time 51.66 seconds
Started Jul 19 04:41:13 PM PDT 24
Finished Jul 19 04:42:20 PM PDT 24
Peak memory 217492 kb
Host smart-34a11b2f-0ce3-474e-8215-c83e2c04c78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350447675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.350447675
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2918772301
Short name T245
Test name
Test status
Simulation time 15261123719 ps
CPU time 36.81 seconds
Started Jul 19 04:41:09 PM PDT 24
Finished Jul 19 04:41:59 PM PDT 24
Peak memory 216772 kb
Host smart-cf2c87f3-afb3-4b95-b656-c678a399516d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918772301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2918772301
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.4107470025
Short name T166
Test name
Test status
Simulation time 1232817693 ps
CPU time 10 seconds
Started Jul 19 04:41:14 PM PDT 24
Finished Jul 19 04:41:39 PM PDT 24
Peak memory 213248 kb
Host smart-3fcbdc9d-d689-4dbb-b827-6e774fca77eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107470025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.4107470025
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1199752746
Short name T128
Test name
Test status
Simulation time 21748568148 ps
CPU time 199.84 seconds
Started Jul 19 04:41:07 PM PDT 24
Finished Jul 19 04:44:38 PM PDT 24
Peak memory 238872 kb
Host smart-4dfdb057-eb7e-4894-8abd-4a92f14cf8ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199752746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1199752746
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1812842753
Short name T24
Test name
Test status
Simulation time 21149640139 ps
CPU time 64.55 seconds
Started Jul 19 04:41:08 PM PDT 24
Finished Jul 19 04:42:26 PM PDT 24
Peak memory 219348 kb
Host smart-456a3a5e-ef84-4d35-aa3f-ae21501c154a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812842753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1812842753
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.164842162
Short name T273
Test name
Test status
Simulation time 14485774162 ps
CPU time 32.13 seconds
Started Jul 19 04:41:08 PM PDT 24
Finished Jul 19 04:41:53 PM PDT 24
Peak memory 218712 kb
Host smart-7c9bb0ef-b3c3-4b06-ab3b-660369d17a08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=164842162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.164842162
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1951014715
Short name T234
Test name
Test status
Simulation time 11398780371 ps
CPU time 108.43 seconds
Started Jul 19 04:41:02 PM PDT 24
Finished Jul 19 04:42:59 PM PDT 24
Peak memory 219728 kb
Host smart-3fa57308-7aba-4714-94fe-551daae13ca5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951014715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1951014715
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.651933482
Short name T174
Test name
Test status
Simulation time 1487384318 ps
CPU time 17.41 seconds
Started Jul 19 04:41:12 PM PDT 24
Finished Jul 19 04:41:44 PM PDT 24
Peak memory 213212 kb
Host smart-7c7acd46-8554-4f22-85e1-214589a6080a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651933482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.651933482
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.288203229
Short name T198
Test name
Test status
Simulation time 18858772507 ps
CPU time 336.11 seconds
Started Jul 19 04:41:18 PM PDT 24
Finished Jul 19 04:47:10 PM PDT 24
Peak memory 225524 kb
Host smart-c97e8e93-cd31-40b2-a3c7-67d93f27afd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288203229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.288203229
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3544191947
Short name T4
Test name
Test status
Simulation time 30284518412 ps
CPU time 65.21 seconds
Started Jul 19 04:41:03 PM PDT 24
Finished Jul 19 04:42:18 PM PDT 24
Peak memory 219328 kb
Host smart-70910b4d-f01f-41de-aa40-a451b4932725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544191947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3544191947
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.139845678
Short name T310
Test name
Test status
Simulation time 3041286685 ps
CPU time 19.1 seconds
Started Jul 19 04:41:06 PM PDT 24
Finished Jul 19 04:41:36 PM PDT 24
Peak memory 217880 kb
Host smart-2100f282-f248-4145-a34d-de03d3bcc66f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=139845678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.139845678
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.386043455
Short name T119
Test name
Test status
Simulation time 1819751303 ps
CPU time 20.03 seconds
Started Jul 19 04:41:10 PM PDT 24
Finished Jul 19 04:41:44 PM PDT 24
Peak memory 216532 kb
Host smart-18bc8794-d190-4abd-a991-92bc72378c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386043455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.386043455
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1453130053
Short name T319
Test name
Test status
Simulation time 37830947056 ps
CPU time 29.09 seconds
Started Jul 19 04:41:10 PM PDT 24
Finished Jul 19 04:41:53 PM PDT 24
Peak memory 218660 kb
Host smart-aaa5f9ee-b493-422d-817f-1f2fa5ec205d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453130053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1453130053
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.626754988
Short name T248
Test name
Test status
Simulation time 1404993820 ps
CPU time 16.61 seconds
Started Jul 19 04:41:09 PM PDT 24
Finished Jul 19 04:41:39 PM PDT 24
Peak memory 213192 kb
Host smart-aa751393-e5bc-478f-b111-ebdcc36fe627
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626754988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.626754988
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3976917135
Short name T178
Test name
Test status
Simulation time 4000203820 ps
CPU time 286.6 seconds
Started Jul 19 04:41:05 PM PDT 24
Finished Jul 19 04:46:01 PM PDT 24
Peak memory 238024 kb
Host smart-84745a04-e845-41fd-af56-5f07ed4f2c23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976917135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3976917135
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1695154340
Short name T194
Test name
Test status
Simulation time 28108213376 ps
CPU time 61.98 seconds
Started Jul 19 04:41:07 PM PDT 24
Finished Jul 19 04:42:20 PM PDT 24
Peak memory 219380 kb
Host smart-15b7a31f-8435-47fa-8126-e5584708b3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695154340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1695154340
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1730529208
Short name T293
Test name
Test status
Simulation time 731922505 ps
CPU time 10.49 seconds
Started Jul 19 04:41:10 PM PDT 24
Finished Jul 19 04:41:34 PM PDT 24
Peak memory 219300 kb
Host smart-7096cdb6-4e9c-4d69-bf5b-018f64e141d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1730529208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1730529208
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.4253265842
Short name T290
Test name
Test status
Simulation time 29234841268 ps
CPU time 57.5 seconds
Started Jul 19 04:41:13 PM PDT 24
Finished Jul 19 04:42:26 PM PDT 24
Peak memory 216680 kb
Host smart-11779f31-cbc8-4dbf-ba9a-0ec91bd62c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253265842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.4253265842
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.4281995715
Short name T356
Test name
Test status
Simulation time 48420744536 ps
CPU time 113.26 seconds
Started Jul 19 04:41:05 PM PDT 24
Finished Jul 19 04:43:09 PM PDT 24
Peak memory 220204 kb
Host smart-6430fb92-2b7f-4c49-baae-ac2fc5ab6fcf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281995715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.4281995715
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1073791263
Short name T335
Test name
Test status
Simulation time 37757305051 ps
CPU time 31.19 seconds
Started Jul 19 04:40:30 PM PDT 24
Finished Jul 19 04:41:03 PM PDT 24
Peak memory 213280 kb
Host smart-08d31795-ae20-41bc-816e-db1b47c0cab4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073791263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1073791263
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.512496168
Short name T257
Test name
Test status
Simulation time 62859632215 ps
CPU time 299.2 seconds
Started Jul 19 04:40:29 PM PDT 24
Finished Jul 19 04:45:30 PM PDT 24
Peak memory 231020 kb
Host smart-a62b4229-707f-4bd2-886f-448fcdccad97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512496168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.512496168
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1890386874
Short name T40
Test name
Test status
Simulation time 1321300944 ps
CPU time 19.57 seconds
Started Jul 19 04:40:33 PM PDT 24
Finished Jul 19 04:40:56 PM PDT 24
Peak memory 219252 kb
Host smart-c6b100c2-4a3f-4c8b-a5de-950543515eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890386874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1890386874
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.4284939728
Short name T118
Test name
Test status
Simulation time 3130179519 ps
CPU time 27.62 seconds
Started Jul 19 04:40:36 PM PDT 24
Finished Jul 19 04:41:06 PM PDT 24
Peak memory 211264 kb
Host smart-6af1c44d-7108-4292-a64b-d4ab5285dbd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4284939728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.4284939728
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.4268457633
Short name T211
Test name
Test status
Simulation time 63846119444 ps
CPU time 49.72 seconds
Started Jul 19 04:40:29 PM PDT 24
Finished Jul 19 04:41:20 PM PDT 24
Peak memory 215680 kb
Host smart-6b9a23b7-ac99-4378-90f1-21eb472b82e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268457633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.4268457633
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1806107868
Short name T309
Test name
Test status
Simulation time 13517129718 ps
CPU time 105.49 seconds
Started Jul 19 04:40:32 PM PDT 24
Finished Jul 19 04:42:20 PM PDT 24
Peak memory 220488 kb
Host smart-6223c73a-0714-4def-b516-d27299e7fb6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806107868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1806107868
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3051262897
Short name T343
Test name
Test status
Simulation time 36927110730 ps
CPU time 29.85 seconds
Started Jul 19 04:40:36 PM PDT 24
Finished Jul 19 04:41:08 PM PDT 24
Peak memory 213272 kb
Host smart-1bfb7f0f-d377-47d3-8439-3466d58dab52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051262897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3051262897
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.4292431022
Short name T171
Test name
Test status
Simulation time 228305600209 ps
CPU time 490.74 seconds
Started Jul 19 04:40:31 PM PDT 24
Finished Jul 19 04:48:43 PM PDT 24
Peak memory 235460 kb
Host smart-0f74e7f9-25ae-4d5c-be47-83131a58e4b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292431022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.4292431022
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2754870519
Short name T231
Test name
Test status
Simulation time 51036821912 ps
CPU time 25.66 seconds
Started Jul 19 04:40:31 PM PDT 24
Finished Jul 19 04:40:59 PM PDT 24
Peak memory 212004 kb
Host smart-b170ae7f-bf93-4bd4-96f7-db5f42312f5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2754870519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2754870519
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2410392760
Short name T117
Test name
Test status
Simulation time 5896561951 ps
CPU time 51.63 seconds
Started Jul 19 04:40:32 PM PDT 24
Finished Jul 19 04:41:27 PM PDT 24
Peak memory 216680 kb
Host smart-1efac1b5-4ec8-448c-bec7-338d63839052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410392760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2410392760
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.749843284
Short name T318
Test name
Test status
Simulation time 4037305260 ps
CPU time 34.46 seconds
Started Jul 19 04:40:29 PM PDT 24
Finished Jul 19 04:41:05 PM PDT 24
Peak memory 217240 kb
Host smart-f20ce5a7-cd33-4f3a-bf30-824dc6782e24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749843284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.749843284
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3294649571
Short name T14
Test name
Test status
Simulation time 44985494293 ps
CPU time 1760.78 seconds
Started Jul 19 04:40:29 PM PDT 24
Finished Jul 19 05:09:52 PM PDT 24
Peak memory 236896 kb
Host smart-8ad3bb4b-ff77-4630-8f26-6cf18efae29e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294649571 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.3294649571
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2354083806
Short name T154
Test name
Test status
Simulation time 3400238656 ps
CPU time 27.57 seconds
Started Jul 19 04:40:31 PM PDT 24
Finished Jul 19 04:41:01 PM PDT 24
Peak memory 213280 kb
Host smart-8ab3d730-36c9-497c-9bed-8b851eb7dce3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354083806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2354083806
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3892895261
Short name T28
Test name
Test status
Simulation time 3140086359 ps
CPU time 34.4 seconds
Started Jul 19 04:40:31 PM PDT 24
Finished Jul 19 04:41:08 PM PDT 24
Peak memory 219352 kb
Host smart-8ee50e9b-25d3-4372-b585-0206faa1b8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892895261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3892895261
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2662729869
Short name T164
Test name
Test status
Simulation time 1463196402 ps
CPU time 15.22 seconds
Started Jul 19 04:40:27 PM PDT 24
Finished Jul 19 04:40:44 PM PDT 24
Peak memory 218552 kb
Host smart-ee7982f8-6e07-4989-ae3c-7f429c46002d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2662729869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2662729869
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3966273285
Short name T229
Test name
Test status
Simulation time 26879884207 ps
CPU time 64.3 seconds
Started Jul 19 04:40:30 PM PDT 24
Finished Jul 19 04:41:41 PM PDT 24
Peak memory 217200 kb
Host smart-b5b21afb-34d7-4566-8beb-e61145f1ba6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966273285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3966273285
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.4140944505
Short name T51
Test name
Test status
Simulation time 39409547895 ps
CPU time 4928.8 seconds
Started Jul 19 04:40:28 PM PDT 24
Finished Jul 19 06:02:38 PM PDT 24
Peak memory 233440 kb
Host smart-1ff777c8-9640-4bf7-9063-52c3864abbf2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140944505 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.4140944505
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2345677532
Short name T206
Test name
Test status
Simulation time 15777663856 ps
CPU time 21.03 seconds
Started Jul 19 04:40:31 PM PDT 24
Finished Jul 19 04:40:54 PM PDT 24
Peak memory 217416 kb
Host smart-b90a098f-b763-4fd6-94b1-46c27a5c9a94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345677532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2345677532
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.587638283
Short name T281
Test name
Test status
Simulation time 231665827643 ps
CPU time 605.33 seconds
Started Jul 19 04:40:35 PM PDT 24
Finished Jul 19 04:50:44 PM PDT 24
Peak memory 234928 kb
Host smart-c4ce9c40-3f36-4353-ab9a-0add341d8dc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587638283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.587638283
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1691728667
Short name T261
Test name
Test status
Simulation time 2699003719 ps
CPU time 35.87 seconds
Started Jul 19 04:40:35 PM PDT 24
Finished Jul 19 04:41:14 PM PDT 24
Peak memory 218900 kb
Host smart-ee128df7-70c8-4dc3-85b1-79960ee9029d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691728667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1691728667
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3746467923
Short name T158
Test name
Test status
Simulation time 1241195294 ps
CPU time 17.59 seconds
Started Jul 19 04:40:32 PM PDT 24
Finished Jul 19 04:40:52 PM PDT 24
Peak memory 211240 kb
Host smart-3f9a1f80-e824-4efe-9b9c-1bdb333c6c27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3746467923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3746467923
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1612486017
Short name T236
Test name
Test status
Simulation time 3774766819 ps
CPU time 43.36 seconds
Started Jul 19 04:40:33 PM PDT 24
Finished Jul 19 04:41:19 PM PDT 24
Peak memory 216360 kb
Host smart-ccb4e2ee-ca43-4f3f-97c8-b29e850a6069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612486017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1612486017
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3534040891
Short name T292
Test name
Test status
Simulation time 8254982008 ps
CPU time 95.05 seconds
Started Jul 19 04:40:30 PM PDT 24
Finished Jul 19 04:42:06 PM PDT 24
Peak memory 217964 kb
Host smart-65efc0b7-6cae-4d99-8f11-b480c81ff635
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534040891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3534040891
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.124933517
Short name T323
Test name
Test status
Simulation time 8639496785 ps
CPU time 30.71 seconds
Started Jul 19 04:40:32 PM PDT 24
Finished Jul 19 04:41:05 PM PDT 24
Peak memory 217548 kb
Host smart-d7f72b18-71d6-41c3-b0c2-69959cb80e96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124933517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.124933517
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1092395834
Short name T173
Test name
Test status
Simulation time 79120956545 ps
CPU time 372.55 seconds
Started Jul 19 04:40:34 PM PDT 24
Finished Jul 19 04:46:49 PM PDT 24
Peak memory 240096 kb
Host smart-a5ac8b81-43ec-44bd-b274-1da0105fd646
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092395834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1092395834
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.352795816
Short name T344
Test name
Test status
Simulation time 24389297071 ps
CPU time 54.33 seconds
Started Jul 19 04:40:33 PM PDT 24
Finished Jul 19 04:41:30 PM PDT 24
Peak memory 219356 kb
Host smart-8f7fc941-774b-4b97-b9e5-8047e38b9876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352795816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.352795816
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1956570119
Short name T135
Test name
Test status
Simulation time 1685020597 ps
CPU time 19.93 seconds
Started Jul 19 04:40:34 PM PDT 24
Finished Jul 19 04:40:56 PM PDT 24
Peak memory 211356 kb
Host smart-cd991319-0fe4-4e1e-949e-3f0a3e40c506
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1956570119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1956570119
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.511327233
Short name T159
Test name
Test status
Simulation time 11177565195 ps
CPU time 35.63 seconds
Started Jul 19 04:40:32 PM PDT 24
Finished Jul 19 04:41:10 PM PDT 24
Peak memory 216072 kb
Host smart-81a8eb54-67a7-4d2c-b07e-6ea906710b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511327233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.511327233
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.4140482770
Short name T254
Test name
Test status
Simulation time 47195372645 ps
CPU time 52.16 seconds
Started Jul 19 04:40:31 PM PDT 24
Finished Jul 19 04:41:26 PM PDT 24
Peak memory 219356 kb
Host smart-03b38342-d94a-4bdf-8e10-1100373de55a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140482770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.4140482770
Directory /workspace/9.rom_ctrl_stress_all/latest
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