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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.39 96.89 91.99 97.68 100.00 98.62 97.45 99.07


Total test records in report: 456
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T303 /workspace/coverage/default/33.rom_ctrl_alert_test.1636700117 Jul 20 05:28:43 PM PDT 24 Jul 20 05:28:57 PM PDT 24 3298323476 ps
T304 /workspace/coverage/default/2.rom_ctrl_alert_test.733870630 Jul 20 05:27:56 PM PDT 24 Jul 20 05:28:21 PM PDT 24 2994899149 ps
T305 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.4288294134 Jul 20 05:29:00 PM PDT 24 Jul 20 05:29:33 PM PDT 24 18316275016 ps
T306 /workspace/coverage/default/44.rom_ctrl_smoke.3587429517 Jul 20 05:28:54 PM PDT 24 Jul 20 05:30:21 PM PDT 24 8529732993 ps
T44 /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.1115676036 Jul 20 05:28:47 PM PDT 24 Jul 20 05:40:03 PM PDT 24 70076745321 ps
T307 /workspace/coverage/default/4.rom_ctrl_alert_test.2078709033 Jul 20 05:27:54 PM PDT 24 Jul 20 05:28:27 PM PDT 24 3766603428 ps
T308 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1769747916 Jul 20 05:27:56 PM PDT 24 Jul 20 05:28:47 PM PDT 24 26674091765 ps
T309 /workspace/coverage/default/17.rom_ctrl_stress_all.1820792586 Jul 20 05:28:10 PM PDT 24 Jul 20 05:28:43 PM PDT 24 3599499854 ps
T310 /workspace/coverage/default/0.rom_ctrl_smoke.1889081077 Jul 20 05:27:47 PM PDT 24 Jul 20 05:28:49 PM PDT 24 6462071089 ps
T311 /workspace/coverage/default/32.rom_ctrl_stress_all.546974142 Jul 20 05:28:34 PM PDT 24 Jul 20 05:29:52 PM PDT 24 5790675417 ps
T312 /workspace/coverage/default/10.rom_ctrl_alert_test.3330727820 Jul 20 05:28:03 PM PDT 24 Jul 20 05:28:24 PM PDT 24 16423327059 ps
T313 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3310090766 Jul 20 05:28:21 PM PDT 24 Jul 20 05:31:10 PM PDT 24 16281187569 ps
T314 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2352832609 Jul 20 05:28:02 PM PDT 24 Jul 20 05:28:17 PM PDT 24 341862333 ps
T315 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1870266074 Jul 20 05:28:28 PM PDT 24 Jul 20 05:28:56 PM PDT 24 6580682617 ps
T316 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1028295117 Jul 20 05:28:36 PM PDT 24 Jul 20 05:29:04 PM PDT 24 11287412468 ps
T317 /workspace/coverage/default/12.rom_ctrl_smoke.4191956726 Jul 20 05:28:05 PM PDT 24 Jul 20 05:28:54 PM PDT 24 10436344543 ps
T318 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.4103030779 Jul 20 05:28:21 PM PDT 24 Jul 20 05:28:54 PM PDT 24 14469915559 ps
T319 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2652611526 Jul 20 05:28:02 PM PDT 24 Jul 20 05:28:23 PM PDT 24 1321419178 ps
T320 /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2932043158 Jul 20 05:28:36 PM PDT 24 Jul 20 05:37:44 PM PDT 24 259488166143 ps
T321 /workspace/coverage/default/16.rom_ctrl_alert_test.215646157 Jul 20 05:28:12 PM PDT 24 Jul 20 05:28:22 PM PDT 24 661328419 ps
T322 /workspace/coverage/default/1.rom_ctrl_stress_all.323968487 Jul 20 05:27:53 PM PDT 24 Jul 20 05:28:42 PM PDT 24 10399701342 ps
T323 /workspace/coverage/default/5.rom_ctrl_smoke.3185723969 Jul 20 05:28:01 PM PDT 24 Jul 20 05:28:56 PM PDT 24 25361125533 ps
T324 /workspace/coverage/default/32.rom_ctrl_alert_test.3018688768 Jul 20 05:28:35 PM PDT 24 Jul 20 05:28:47 PM PDT 24 372238718 ps
T325 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1032983689 Jul 20 05:28:27 PM PDT 24 Jul 20 05:29:08 PM PDT 24 3566783815 ps
T326 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3958369313 Jul 20 05:28:35 PM PDT 24 Jul 20 05:28:59 PM PDT 24 2322164937 ps
T327 /workspace/coverage/default/8.rom_ctrl_smoke.4259577076 Jul 20 05:28:01 PM PDT 24 Jul 20 05:28:23 PM PDT 24 690633679 ps
T328 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3887635927 Jul 20 05:28:11 PM PDT 24 Jul 20 05:28:46 PM PDT 24 4165680474 ps
T329 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.594540058 Jul 20 05:28:22 PM PDT 24 Jul 20 05:36:56 PM PDT 24 39300741287 ps
T330 /workspace/coverage/default/40.rom_ctrl_stress_all.1322297118 Jul 20 05:28:43 PM PDT 24 Jul 20 05:29:21 PM PDT 24 3787191525 ps
T331 /workspace/coverage/default/48.rom_ctrl_smoke.1942019292 Jul 20 05:29:00 PM PDT 24 Jul 20 05:29:26 PM PDT 24 5170132359 ps
T332 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2043233769 Jul 20 05:28:00 PM PDT 24 Jul 20 05:28:53 PM PDT 24 12000827635 ps
T333 /workspace/coverage/default/2.rom_ctrl_smoke.2634032510 Jul 20 05:27:53 PM PDT 24 Jul 20 05:28:29 PM PDT 24 5709783166 ps
T334 /workspace/coverage/default/3.rom_ctrl_smoke.3915911063 Jul 20 05:27:53 PM PDT 24 Jul 20 05:28:47 PM PDT 24 5007181188 ps
T335 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3339774931 Jul 20 05:28:19 PM PDT 24 Jul 20 05:31:40 PM PDT 24 10232552394 ps
T336 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.808573170 Jul 20 05:28:02 PM PDT 24 Jul 20 05:32:38 PM PDT 24 11242240337 ps
T337 /workspace/coverage/default/23.rom_ctrl_smoke.1671997174 Jul 20 05:28:20 PM PDT 24 Jul 20 05:29:37 PM PDT 24 12614992416 ps
T338 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2738048696 Jul 20 05:28:32 PM PDT 24 Jul 20 05:28:43 PM PDT 24 187405136 ps
T339 /workspace/coverage/default/26.rom_ctrl_alert_test.1334694642 Jul 20 05:28:30 PM PDT 24 Jul 20 05:28:52 PM PDT 24 2219445548 ps
T340 /workspace/coverage/default/18.rom_ctrl_smoke.3654710765 Jul 20 05:28:20 PM PDT 24 Jul 20 05:29:19 PM PDT 24 9191061310 ps
T341 /workspace/coverage/default/37.rom_ctrl_stress_all.335112972 Jul 20 05:28:35 PM PDT 24 Jul 20 05:30:31 PM PDT 24 23667698678 ps
T342 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3759491986 Jul 20 05:28:36 PM PDT 24 Jul 20 05:29:36 PM PDT 24 6849697915 ps
T343 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1033202404 Jul 20 05:28:30 PM PDT 24 Jul 20 05:28:45 PM PDT 24 670683272 ps
T344 /workspace/coverage/default/41.rom_ctrl_stress_all.2290390935 Jul 20 05:28:45 PM PDT 24 Jul 20 05:29:31 PM PDT 24 2485060663 ps
T345 /workspace/coverage/default/22.rom_ctrl_alert_test.3090020765 Jul 20 05:28:18 PM PDT 24 Jul 20 05:28:53 PM PDT 24 4312387220 ps
T346 /workspace/coverage/default/23.rom_ctrl_stress_all.4008344377 Jul 20 05:28:23 PM PDT 24 Jul 20 05:28:48 PM PDT 24 728695233 ps
T347 /workspace/coverage/default/45.rom_ctrl_stress_all.3953361599 Jul 20 05:29:02 PM PDT 24 Jul 20 05:31:13 PM PDT 24 145114295380 ps
T348 /workspace/coverage/default/30.rom_ctrl_stress_all.2428472269 Jul 20 05:28:30 PM PDT 24 Jul 20 05:29:50 PM PDT 24 54978973122 ps
T349 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1411431061 Jul 20 05:28:03 PM PDT 24 Jul 20 05:28:24 PM PDT 24 1319698888 ps
T350 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3579715724 Jul 20 05:28:54 PM PDT 24 Jul 20 05:29:15 PM PDT 24 6177861648 ps
T351 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2783973743 Jul 20 05:28:21 PM PDT 24 Jul 20 05:29:18 PM PDT 24 5953573051 ps
T39 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.309591017 Jul 20 05:28:27 PM PDT 24 Jul 20 05:29:13 PM PDT 24 4112049047 ps
T352 /workspace/coverage/default/11.rom_ctrl_alert_test.2320893045 Jul 20 05:28:03 PM PDT 24 Jul 20 05:28:13 PM PDT 24 660466770 ps
T353 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2089481899 Jul 20 05:28:37 PM PDT 24 Jul 20 05:29:33 PM PDT 24 27933563328 ps
T354 /workspace/coverage/default/48.rom_ctrl_stress_all.1153250042 Jul 20 05:29:00 PM PDT 24 Jul 20 05:32:01 PM PDT 24 76818120500 ps
T29 /workspace/coverage/default/3.rom_ctrl_sec_cm.3677221875 Jul 20 05:27:54 PM PDT 24 Jul 20 05:29:51 PM PDT 24 904213903 ps
T355 /workspace/coverage/default/49.rom_ctrl_smoke.1547809682 Jul 20 05:29:09 PM PDT 24 Jul 20 05:29:57 PM PDT 24 5175211141 ps
T356 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2851398905 Jul 20 05:28:19 PM PDT 24 Jul 20 05:28:39 PM PDT 24 332401743 ps
T357 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3283955725 Jul 20 05:28:20 PM PDT 24 Jul 20 05:28:41 PM PDT 24 335979411 ps
T358 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.886445965 Jul 20 05:29:02 PM PDT 24 Jul 20 05:34:59 PM PDT 24 21317237082 ps
T359 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3297317249 Jul 20 05:27:56 PM PDT 24 Jul 20 05:28:24 PM PDT 24 13424519179 ps
T360 /workspace/coverage/default/16.rom_ctrl_stress_all.3221621335 Jul 20 05:28:10 PM PDT 24 Jul 20 05:29:04 PM PDT 24 11102758290 ps
T361 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.272109656 Jul 20 05:27:11 PM PDT 24 Jul 20 05:27:33 PM PDT 24 7581927392 ps
T45 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1441530102 Jul 20 05:27:38 PM PDT 24 Jul 20 05:27:53 PM PDT 24 4635230543 ps
T58 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1728291174 Jul 20 05:27:46 PM PDT 24 Jul 20 05:29:47 PM PDT 24 11334558278 ps
T59 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2223840216 Jul 20 05:27:40 PM PDT 24 Jul 20 05:28:05 PM PDT 24 15885869448 ps
T46 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.4088262504 Jul 20 05:27:29 PM PDT 24 Jul 20 05:27:39 PM PDT 24 727852860 ps
T47 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3193430147 Jul 20 05:27:31 PM PDT 24 Jul 20 05:27:43 PM PDT 24 167473805 ps
T67 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3886181090 Jul 20 05:27:32 PM PDT 24 Jul 20 05:28:58 PM PDT 24 16558800647 ps
T362 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1221526557 Jul 20 05:27:37 PM PDT 24 Jul 20 05:28:11 PM PDT 24 8861467175 ps
T98 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.854931329 Jul 20 05:27:37 PM PDT 24 Jul 20 05:27:53 PM PDT 24 6628431126 ps
T68 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.408552469 Jul 20 05:27:21 PM PDT 24 Jul 20 05:27:47 PM PDT 24 12624441895 ps
T54 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.897219119 Jul 20 05:27:44 PM PDT 24 Jul 20 05:29:18 PM PDT 24 11416141358 ps
T69 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2360347293 Jul 20 05:27:38 PM PDT 24 Jul 20 05:28:10 PM PDT 24 3367332673 ps
T99 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1025953970 Jul 20 05:27:20 PM PDT 24 Jul 20 05:27:44 PM PDT 24 18746287043 ps
T70 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3996621013 Jul 20 05:27:02 PM PDT 24 Jul 20 05:29:27 PM PDT 24 29219351898 ps
T100 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3426400105 Jul 20 05:27:04 PM PDT 24 Jul 20 05:27:27 PM PDT 24 1132698387 ps
T363 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3618052636 Jul 20 05:27:45 PM PDT 24 Jul 20 05:28:09 PM PDT 24 16368308659 ps
T71 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.738826597 Jul 20 05:27:22 PM PDT 24 Jul 20 05:27:32 PM PDT 24 339196821 ps
T72 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.113638346 Jul 20 05:27:13 PM PDT 24 Jul 20 05:27:38 PM PDT 24 10536431913 ps
T364 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2939140649 Jul 20 05:27:14 PM PDT 24 Jul 20 05:29:44 PM PDT 24 16897781950 ps
T92 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.548642850 Jul 20 05:27:31 PM PDT 24 Jul 20 05:27:53 PM PDT 24 7014168310 ps
T365 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.200495480 Jul 20 05:27:47 PM PDT 24 Jul 20 05:28:10 PM PDT 24 4369785362 ps
T366 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3756921072 Jul 20 05:27:12 PM PDT 24 Jul 20 05:27:24 PM PDT 24 809517284 ps
T93 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3695091855 Jul 20 05:27:45 PM PDT 24 Jul 20 05:28:12 PM PDT 24 7938756262 ps
T73 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2643826936 Jul 20 05:27:06 PM PDT 24 Jul 20 05:27:21 PM PDT 24 181768082 ps
T55 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.833888458 Jul 20 05:27:23 PM PDT 24 Jul 20 05:29:59 PM PDT 24 759940579 ps
T367 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3145872392 Jul 20 05:27:24 PM PDT 24 Jul 20 05:27:39 PM PDT 24 688798416 ps
T368 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3611563311 Jul 20 05:27:23 PM PDT 24 Jul 20 05:27:52 PM PDT 24 29596942901 ps
T369 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1943130442 Jul 20 05:27:08 PM PDT 24 Jul 20 05:27:37 PM PDT 24 8534692110 ps
T74 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.524875411 Jul 20 05:27:41 PM PDT 24 Jul 20 05:30:35 PM PDT 24 43233301141 ps
T79 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2927952528 Jul 20 05:27:46 PM PDT 24 Jul 20 05:29:40 PM PDT 24 28728190658 ps
T80 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.796371864 Jul 20 05:27:11 PM PDT 24 Jul 20 05:27:27 PM PDT 24 291590944 ps
T370 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.619307896 Jul 20 05:27:13 PM PDT 24 Jul 20 05:27:33 PM PDT 24 18275367341 ps
T81 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4182260725 Jul 20 05:27:30 PM PDT 24 Jul 20 05:29:35 PM PDT 24 43380630494 ps
T87 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3600212378 Jul 20 05:27:47 PM PDT 24 Jul 20 05:28:19 PM PDT 24 9193525647 ps
T56 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3408128173 Jul 20 05:27:21 PM PDT 24 Jul 20 05:29:57 PM PDT 24 614383054 ps
T371 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1209681956 Jul 20 05:27:21 PM PDT 24 Jul 20 05:27:43 PM PDT 24 9218403479 ps
T372 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3623242213 Jul 20 05:27:20 PM PDT 24 Jul 20 05:27:29 PM PDT 24 719504907 ps
T373 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3249964968 Jul 20 05:27:25 PM PDT 24 Jul 20 05:27:45 PM PDT 24 9573536970 ps
T374 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1034023622 Jul 20 05:27:02 PM PDT 24 Jul 20 05:27:35 PM PDT 24 17698212251 ps
T94 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3562520721 Jul 20 05:27:22 PM PDT 24 Jul 20 05:27:57 PM PDT 24 8346085747 ps
T375 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1460456908 Jul 20 05:27:29 PM PDT 24 Jul 20 05:28:02 PM PDT 24 4296294305 ps
T95 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1782651550 Jul 20 05:27:41 PM PDT 24 Jul 20 05:27:55 PM PDT 24 179632258 ps
T88 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.378463166 Jul 20 05:27:39 PM PDT 24 Jul 20 05:28:10 PM PDT 24 26385186531 ps
T376 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2129492695 Jul 20 05:27:16 PM PDT 24 Jul 20 05:27:41 PM PDT 24 7535094155 ps
T96 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1260133650 Jul 20 05:27:22 PM PDT 24 Jul 20 05:27:38 PM PDT 24 905523095 ps
T113 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1477715825 Jul 20 05:27:40 PM PDT 24 Jul 20 05:29:13 PM PDT 24 8429635412 ps
T377 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1278817241 Jul 20 05:27:33 PM PDT 24 Jul 20 05:27:58 PM PDT 24 5488932031 ps
T378 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1335585299 Jul 20 05:27:28 PM PDT 24 Jul 20 05:28:53 PM PDT 24 16125245849 ps
T379 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.152188453 Jul 20 05:27:00 PM PDT 24 Jul 20 05:27:21 PM PDT 24 3640903430 ps
T97 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2182368388 Jul 20 05:27:11 PM PDT 24 Jul 20 05:27:35 PM PDT 24 2696013177 ps
T380 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.576671993 Jul 20 05:27:29 PM PDT 24 Jul 20 05:27:43 PM PDT 24 1675540256 ps
T104 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.100673973 Jul 20 05:27:39 PM PDT 24 Jul 20 05:29:23 PM PDT 24 4109658226 ps
T381 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3848557874 Jul 20 05:27:13 PM PDT 24 Jul 20 05:27:22 PM PDT 24 688615433 ps
T89 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1616162319 Jul 20 05:27:23 PM PDT 24 Jul 20 05:28:36 PM PDT 24 2062416145 ps
T382 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.953218555 Jul 20 05:27:03 PM PDT 24 Jul 20 05:27:18 PM PDT 24 1649912474 ps
T383 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.912057711 Jul 20 05:27:30 PM PDT 24 Jul 20 05:27:59 PM PDT 24 14026721104 ps
T384 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.873455680 Jul 20 05:27:36 PM PDT 24 Jul 20 05:27:52 PM PDT 24 1180220977 ps
T90 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2879448598 Jul 20 05:27:29 PM PDT 24 Jul 20 05:27:58 PM PDT 24 29152829625 ps
T108 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3765231308 Jul 20 05:27:13 PM PDT 24 Jul 20 05:28:37 PM PDT 24 3789255570 ps
T385 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3453409120 Jul 20 05:27:11 PM PDT 24 Jul 20 05:27:30 PM PDT 24 3593469459 ps
T110 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2016031181 Jul 20 05:27:21 PM PDT 24 Jul 20 05:30:14 PM PDT 24 12163384088 ps
T386 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.960892114 Jul 20 05:27:02 PM PDT 24 Jul 20 05:27:27 PM PDT 24 2549872898 ps
T91 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1110849213 Jul 20 05:27:22 PM PDT 24 Jul 20 05:29:21 PM PDT 24 26499424439 ps
T387 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1958498030 Jul 20 05:27:03 PM PDT 24 Jul 20 05:27:12 PM PDT 24 687971193 ps
T388 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.374849556 Jul 20 05:26:59 PM PDT 24 Jul 20 05:27:20 PM PDT 24 10602395906 ps
T389 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2310282850 Jul 20 05:27:23 PM PDT 24 Jul 20 05:29:30 PM PDT 24 30828122853 ps
T390 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.455706606 Jul 20 05:27:24 PM PDT 24 Jul 20 05:27:52 PM PDT 24 3189904220 ps
T82 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1965971858 Jul 20 05:27:46 PM PDT 24 Jul 20 05:28:13 PM PDT 24 12851236009 ps
T391 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.255146289 Jul 20 05:27:27 PM PDT 24 Jul 20 05:27:53 PM PDT 24 10791596702 ps
T392 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2117978494 Jul 20 05:27:29 PM PDT 24 Jul 20 05:27:37 PM PDT 24 167365904 ps
T393 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2760891539 Jul 20 05:27:38 PM PDT 24 Jul 20 05:27:48 PM PDT 24 729284322 ps
T394 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2085874318 Jul 20 05:27:20 PM PDT 24 Jul 20 05:27:34 PM PDT 24 1395870016 ps
T107 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4185717740 Jul 20 05:27:12 PM PDT 24 Jul 20 05:29:59 PM PDT 24 13044608627 ps
T395 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.59686300 Jul 20 05:27:39 PM PDT 24 Jul 20 05:27:49 PM PDT 24 2743262636 ps
T396 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2238295371 Jul 20 05:27:20 PM PDT 24 Jul 20 05:27:40 PM PDT 24 2579775035 ps
T397 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2256948770 Jul 20 05:27:16 PM PDT 24 Jul 20 05:27:36 PM PDT 24 1647197092 ps
T398 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2393055051 Jul 20 05:27:02 PM PDT 24 Jul 20 05:27:12 PM PDT 24 534563415 ps
T83 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2354847695 Jul 20 05:27:24 PM PDT 24 Jul 20 05:27:53 PM PDT 24 13649764199 ps
T399 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.317794590 Jul 20 05:27:12 PM PDT 24 Jul 20 05:27:41 PM PDT 24 13469890614 ps
T400 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3760074510 Jul 20 05:27:12 PM PDT 24 Jul 20 05:27:28 PM PDT 24 705049410 ps
T401 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2911239121 Jul 20 05:27:23 PM PDT 24 Jul 20 05:27:50 PM PDT 24 9852553166 ps
T402 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2286544420 Jul 20 05:27:30 PM PDT 24 Jul 20 05:27:45 PM PDT 24 3780200616 ps
T111 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1076035311 Jul 20 05:27:12 PM PDT 24 Jul 20 05:30:08 PM PDT 24 4150256723 ps
T403 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1534738913 Jul 20 05:27:23 PM PDT 24 Jul 20 05:27:57 PM PDT 24 4357010748 ps
T404 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3509561874 Jul 20 05:27:13 PM PDT 24 Jul 20 05:27:23 PM PDT 24 662180553 ps
T405 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2682030850 Jul 20 05:27:03 PM PDT 24 Jul 20 05:27:38 PM PDT 24 17255568980 ps
T103 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1402147984 Jul 20 05:27:03 PM PDT 24 Jul 20 05:30:00 PM PDT 24 4215065814 ps
T406 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.234672646 Jul 20 05:27:41 PM PDT 24 Jul 20 05:28:12 PM PDT 24 14427904662 ps
T407 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.833123557 Jul 20 05:27:16 PM PDT 24 Jul 20 05:27:25 PM PDT 24 612380561 ps
T408 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.405989859 Jul 20 05:27:46 PM PDT 24 Jul 20 05:28:06 PM PDT 24 2517743382 ps
T409 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2605188178 Jul 20 05:27:32 PM PDT 24 Jul 20 05:27:44 PM PDT 24 2890933109 ps
T84 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3204168124 Jul 20 05:27:14 PM PDT 24 Jul 20 05:27:23 PM PDT 24 688979532 ps
T410 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4087210318 Jul 20 05:27:23 PM PDT 24 Jul 20 05:27:51 PM PDT 24 6289935422 ps
T85 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1440640612 Jul 20 05:27:24 PM PDT 24 Jul 20 05:28:03 PM PDT 24 4877084876 ps
T411 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.551815857 Jul 20 05:27:02 PM PDT 24 Jul 20 05:27:33 PM PDT 24 14462689195 ps
T106 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1469971622 Jul 20 05:27:37 PM PDT 24 Jul 20 05:29:12 PM PDT 24 4790844476 ps
T412 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.719496060 Jul 20 05:27:02 PM PDT 24 Jul 20 05:27:21 PM PDT 24 3002201664 ps
T413 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1669487784 Jul 20 05:27:07 PM PDT 24 Jul 20 05:27:16 PM PDT 24 331635500 ps
T112 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3106239534 Jul 20 05:27:21 PM PDT 24 Jul 20 05:28:53 PM PDT 24 4075302226 ps
T414 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.367927123 Jul 20 05:27:00 PM PDT 24 Jul 20 05:27:32 PM PDT 24 3870757237 ps
T415 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3178349350 Jul 20 05:27:13 PM PDT 24 Jul 20 05:28:06 PM PDT 24 2082870547 ps
T416 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.636955358 Jul 20 05:27:38 PM PDT 24 Jul 20 05:29:27 PM PDT 24 57584730009 ps
T417 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.460019665 Jul 20 05:27:14 PM PDT 24 Jul 20 05:27:23 PM PDT 24 688542256 ps
T418 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1195542366 Jul 20 05:27:23 PM PDT 24 Jul 20 05:29:03 PM PDT 24 38133967591 ps
T419 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3846993041 Jul 20 05:27:12 PM PDT 24 Jul 20 05:27:33 PM PDT 24 1824962902 ps
T105 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1976231666 Jul 20 05:27:29 PM PDT 24 Jul 20 05:30:08 PM PDT 24 18463803094 ps
T420 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3901156658 Jul 20 05:27:13 PM PDT 24 Jul 20 05:28:55 PM PDT 24 43633823963 ps
T421 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.785398379 Jul 20 05:27:01 PM PDT 24 Jul 20 05:27:25 PM PDT 24 10250973797 ps
T422 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2226228138 Jul 20 05:27:23 PM PDT 24 Jul 20 05:27:45 PM PDT 24 7179932785 ps
T423 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.782066102 Jul 20 05:27:24 PM PDT 24 Jul 20 05:27:49 PM PDT 24 2404908214 ps
T424 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2239230184 Jul 20 05:27:38 PM PDT 24 Jul 20 05:27:59 PM PDT 24 2008114161 ps
T425 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2921233472 Jul 20 05:27:07 PM PDT 24 Jul 20 05:27:32 PM PDT 24 2891677405 ps
T86 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1447643417 Jul 20 05:27:23 PM PDT 24 Jul 20 05:29:01 PM PDT 24 20712240889 ps
T426 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.615130881 Jul 20 05:27:31 PM PDT 24 Jul 20 05:27:56 PM PDT 24 2894374621 ps
T427 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3692752613 Jul 20 05:27:39 PM PDT 24 Jul 20 05:27:53 PM PDT 24 424945168 ps
T428 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2949922126 Jul 20 05:27:26 PM PDT 24 Jul 20 05:27:34 PM PDT 24 662183275 ps
T429 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2579142599 Jul 20 05:27:43 PM PDT 24 Jul 20 05:28:14 PM PDT 24 3945930978 ps
T430 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3383958197 Jul 20 05:27:38 PM PDT 24 Jul 20 05:28:04 PM PDT 24 13508395387 ps
T431 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1672132627 Jul 20 05:27:13 PM PDT 24 Jul 20 05:27:35 PM PDT 24 2311515032 ps
T432 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1372293395 Jul 20 05:27:12 PM PDT 24 Jul 20 05:27:39 PM PDT 24 44945933710 ps
T433 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1743901406 Jul 20 05:27:01 PM PDT 24 Jul 20 05:28:09 PM PDT 24 19017715987 ps
T434 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2074488820 Jul 20 05:27:45 PM PDT 24 Jul 20 05:30:29 PM PDT 24 8395605190 ps
T435 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1735289914 Jul 20 05:27:39 PM PDT 24 Jul 20 05:29:48 PM PDT 24 66907216347 ps
T436 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4239692407 Jul 20 05:27:34 PM PDT 24 Jul 20 05:30:14 PM PDT 24 7028502550 ps
T437 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1510234135 Jul 20 05:27:38 PM PDT 24 Jul 20 05:28:08 PM PDT 24 2547570915 ps
T438 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.339524749 Jul 20 05:27:23 PM PDT 24 Jul 20 05:27:45 PM PDT 24 1316218794 ps
T439 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2893206768 Jul 20 05:27:23 PM PDT 24 Jul 20 05:27:42 PM PDT 24 842907607 ps
T440 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2747351345 Jul 20 05:27:33 PM PDT 24 Jul 20 05:27:49 PM PDT 24 431190454 ps
T441 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.180718083 Jul 20 05:27:25 PM PDT 24 Jul 20 05:27:49 PM PDT 24 1882592997 ps
T442 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2895949171 Jul 20 05:27:07 PM PDT 24 Jul 20 05:27:33 PM PDT 24 2011638753 ps
T109 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1964907661 Jul 20 05:27:32 PM PDT 24 Jul 20 05:29:13 PM PDT 24 3654994667 ps
T443 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2488762292 Jul 20 05:27:38 PM PDT 24 Jul 20 05:28:00 PM PDT 24 2669665367 ps
T444 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.454165815 Jul 20 05:27:40 PM PDT 24 Jul 20 05:27:52 PM PDT 24 696859308 ps
T445 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.310301678 Jul 20 05:27:20 PM PDT 24 Jul 20 05:28:54 PM PDT 24 2218213516 ps
T446 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3036188729 Jul 20 05:27:45 PM PDT 24 Jul 20 05:27:56 PM PDT 24 1321891990 ps
T447 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3969691711 Jul 20 05:27:41 PM PDT 24 Jul 20 05:28:58 PM PDT 24 22186614921 ps
T448 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1846806350 Jul 20 05:27:30 PM PDT 24 Jul 20 05:27:54 PM PDT 24 1774788333 ps
T449 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2209023493 Jul 20 05:27:01 PM PDT 24 Jul 20 05:28:38 PM PDT 24 9827337138 ps
T450 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.722422637 Jul 20 05:27:38 PM PDT 24 Jul 20 05:27:52 PM PDT 24 849942323 ps
T451 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2686831108 Jul 20 05:27:13 PM PDT 24 Jul 20 05:27:46 PM PDT 24 12763018245 ps
T452 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.599645915 Jul 20 05:27:12 PM PDT 24 Jul 20 05:27:36 PM PDT 24 4911710018 ps
T453 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4082721113 Jul 20 05:27:22 PM PDT 24 Jul 20 05:27:49 PM PDT 24 6124083385 ps
T454 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3787774439 Jul 20 05:27:45 PM PDT 24 Jul 20 05:28:00 PM PDT 24 259961495 ps
T455 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1034694108 Jul 20 05:27:23 PM PDT 24 Jul 20 05:30:44 PM PDT 24 25667337932 ps
T456 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2290591127 Jul 20 05:27:37 PM PDT 24 Jul 20 05:28:58 PM PDT 24 858053757 ps

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3131917456
Short name T5
Test name
Test status
Simulation time 312245501896 ps
CPU time 655.27 seconds
Started Jul 20 05:28:02 PM PDT 24
Finished Jul 20 05:38:59 PM PDT 24
Peak memory 239456 kb
Host smart-3934e24e-0b39-413c-9da1-994d7ffa073e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131917456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3131917456
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.759012177
Short name T14
Test name
Test status
Simulation time 2932105026 ps
CPU time 117.97 seconds
Started Jul 20 05:28:09 PM PDT 24
Finished Jul 20 05:30:08 PM PDT 24
Peak memory 223684 kb
Host smart-65532bb3-6d48-4b68-8699-a153857dda80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759012177 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.759012177
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2314055763
Short name T12
Test name
Test status
Simulation time 4346328773 ps
CPU time 88.72 seconds
Started Jul 20 05:28:45 PM PDT 24
Finished Jul 20 05:30:14 PM PDT 24
Peak memory 219392 kb
Host smart-a028278f-df52-4bab-b7fd-a64938f8076d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314055763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2314055763
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1059152808
Short name T36
Test name
Test status
Simulation time 6952713579 ps
CPU time 182.61 seconds
Started Jul 20 05:28:59 PM PDT 24
Finished Jul 20 05:32:03 PM PDT 24
Peak memory 240724 kb
Host smart-cac8b30a-09f6-453e-befe-bb04388a7cd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059152808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1059152808
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3408128173
Short name T56
Test name
Test status
Simulation time 614383054 ps
CPU time 154.78 seconds
Started Jul 20 05:27:21 PM PDT 24
Finished Jul 20 05:29:57 PM PDT 24
Peak memory 213840 kb
Host smart-f995e4df-52bc-43d8-aa96-0da48bf50f89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408128173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3408128173
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3054253939
Short name T30
Test name
Test status
Simulation time 72862105481 ps
CPU time 879.73 seconds
Started Jul 20 05:28:22 PM PDT 24
Finished Jul 20 05:43:04 PM PDT 24
Peak memory 217844 kb
Host smart-7e1d777a-f65c-4cf4-ac03-c7b90e364778
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054253939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3054253939
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3996621013
Short name T70
Test name
Test status
Simulation time 29219351898 ps
CPU time 144.23 seconds
Started Jul 20 05:27:02 PM PDT 24
Finished Jul 20 05:29:27 PM PDT 24
Peak memory 215264 kb
Host smart-842294aa-f2ae-487b-ba43-9524ae8798a8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996621013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3996621013
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.4281362231
Short name T2
Test name
Test status
Simulation time 12507185675 ps
CPU time 135.41 seconds
Started Jul 20 05:27:54 PM PDT 24
Finished Jul 20 05:30:11 PM PDT 24
Peak memory 235536 kb
Host smart-91f4af3b-8926-41b9-b088-8c511d80f4c7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281362231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.4281362231
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.100673973
Short name T104
Test name
Test status
Simulation time 4109658226 ps
CPU time 102.37 seconds
Started Jul 20 05:27:39 PM PDT 24
Finished Jul 20 05:29:23 PM PDT 24
Peak memory 213544 kb
Host smart-9c19246e-6886-4f2d-ab79-2ac1d008cbad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100673973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.100673973
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2882715892
Short name T43
Test name
Test status
Simulation time 41495812423 ps
CPU time 391.17 seconds
Started Jul 20 05:27:53 PM PDT 24
Finished Jul 20 05:34:26 PM PDT 24
Peak memory 228872 kb
Host smart-d3d2074b-cc0e-4465-80e6-4b7b6fd0c9d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882715892 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.2882715892
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.280655009
Short name T60
Test name
Test status
Simulation time 1030093754 ps
CPU time 8.06 seconds
Started Jul 20 05:28:54 PM PDT 24
Finished Jul 20 05:29:03 PM PDT 24
Peak memory 217328 kb
Host smart-cb6c98a4-0b90-4cdb-ade9-56e809357113
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280655009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.280655009
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.897219119
Short name T54
Test name
Test status
Simulation time 11416141358 ps
CPU time 92.59 seconds
Started Jul 20 05:27:44 PM PDT 24
Finished Jul 20 05:29:18 PM PDT 24
Peak memory 214032 kb
Host smart-ab62c9be-da01-41fb-8f72-1c315d18f85f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897219119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.897219119
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2110778490
Short name T1
Test name
Test status
Simulation time 1502696818 ps
CPU time 19.17 seconds
Started Jul 20 05:28:10 PM PDT 24
Finished Jul 20 05:28:30 PM PDT 24
Peak memory 219296 kb
Host smart-c0208588-753a-4df5-b9d7-4b6b2e6ee9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110778490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2110778490
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1326196164
Short name T132
Test name
Test status
Simulation time 28735653917 ps
CPU time 51.6 seconds
Started Jul 20 05:28:12 PM PDT 24
Finished Jul 20 05:29:05 PM PDT 24
Peak memory 219392 kb
Host smart-0cd363e1-8839-439d-8562-07a6f3282b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326196164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1326196164
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.309591017
Short name T39
Test name
Test status
Simulation time 4112049047 ps
CPU time 45.47 seconds
Started Jul 20 05:28:27 PM PDT 24
Finished Jul 20 05:29:13 PM PDT 24
Peak memory 218748 kb
Host smart-e723a142-3533-4d58-86e9-88f91dfbf54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309591017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.309591017
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.3057564808
Short name T16
Test name
Test status
Simulation time 30756855750 ps
CPU time 963.82 seconds
Started Jul 20 05:28:37 PM PDT 24
Finished Jul 20 05:44:42 PM PDT 24
Peak memory 233992 kb
Host smart-03305387-8f37-453d-a762-9f5b72123cd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057564808 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.3057564808
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.337742547
Short name T11
Test name
Test status
Simulation time 2069856269 ps
CPU time 16.85 seconds
Started Jul 20 05:29:07 PM PDT 24
Finished Jul 20 05:29:25 PM PDT 24
Peak memory 217844 kb
Host smart-71c62ea4-531a-4185-a131-1bb0bce9279b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=337742547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.337742547
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1402147984
Short name T103
Test name
Test status
Simulation time 4215065814 ps
CPU time 175.97 seconds
Started Jul 20 05:27:03 PM PDT 24
Finished Jul 20 05:30:00 PM PDT 24
Peak memory 213888 kb
Host smart-5934054e-d25b-4ef6-b393-47897caf0a53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402147984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1402147984
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.548642850
Short name T92
Test name
Test status
Simulation time 7014168310 ps
CPU time 20.97 seconds
Started Jul 20 05:27:31 PM PDT 24
Finished Jul 20 05:27:53 PM PDT 24
Peak memory 212480 kb
Host smart-a82fcdaf-8d35-4c39-b256-3a30165a7fa8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548642850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.548642850
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.152188453
Short name T379
Test name
Test status
Simulation time 3640903430 ps
CPU time 19.42 seconds
Started Jul 20 05:27:00 PM PDT 24
Finished Jul 20 05:27:21 PM PDT 24
Peak memory 211024 kb
Host smart-cfe0e0a2-89f4-449d-bb04-ee9b1d9d1319
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152188453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.152188453
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.960892114
Short name T386
Test name
Test status
Simulation time 2549872898 ps
CPU time 23.4 seconds
Started Jul 20 05:27:02 PM PDT 24
Finished Jul 20 05:27:27 PM PDT 24
Peak memory 210620 kb
Host smart-1249aafd-486a-4f22-8691-2eaf2966c82c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960892114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.960892114
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2643826936
Short name T73
Test name
Test status
Simulation time 181768082 ps
CPU time 15.03 seconds
Started Jul 20 05:27:06 PM PDT 24
Finished Jul 20 05:27:21 PM PDT 24
Peak memory 211304 kb
Host smart-875dd1cc-13fd-4963-abe2-42caab7c0090
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643826936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2643826936
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2682030850
Short name T405
Test name
Test status
Simulation time 17255568980 ps
CPU time 33.81 seconds
Started Jul 20 05:27:03 PM PDT 24
Finished Jul 20 05:27:38 PM PDT 24
Peak memory 216988 kb
Host smart-7f852d7a-2091-46e2-8826-14dee3eaf0dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682030850 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2682030850
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.785398379
Short name T421
Test name
Test status
Simulation time 10250973797 ps
CPU time 22.93 seconds
Started Jul 20 05:27:01 PM PDT 24
Finished Jul 20 05:27:25 PM PDT 24
Peak memory 212256 kb
Host smart-21a4237c-5e90-4516-a3fa-54e973949321
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785398379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.785398379
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.551815857
Short name T411
Test name
Test status
Simulation time 14462689195 ps
CPU time 29.59 seconds
Started Jul 20 05:27:02 PM PDT 24
Finished Jul 20 05:27:33 PM PDT 24
Peak memory 210708 kb
Host smart-fc3f7cd7-4da7-44ec-959a-3a0205b0a44e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551815857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.551815857
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.367927123
Short name T414
Test name
Test status
Simulation time 3870757237 ps
CPU time 30.82 seconds
Started Jul 20 05:27:00 PM PDT 24
Finished Jul 20 05:27:32 PM PDT 24
Peak memory 210484 kb
Host smart-d2efdb95-c063-4131-8fb6-4ab0c159b22e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367927123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
367927123
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1743901406
Short name T433
Test name
Test status
Simulation time 19017715987 ps
CPU time 66.87 seconds
Started Jul 20 05:27:01 PM PDT 24
Finished Jul 20 05:28:09 PM PDT 24
Peak memory 214212 kb
Host smart-337e52f2-953c-43c5-b224-086d4cd020ff
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743901406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1743901406
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.953218555
Short name T382
Test name
Test status
Simulation time 1649912474 ps
CPU time 13.88 seconds
Started Jul 20 05:27:03 PM PDT 24
Finished Jul 20 05:27:18 PM PDT 24
Peak memory 211328 kb
Host smart-e904e07e-ab60-4d4b-b360-9757a3424e4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953218555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.953218555
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2895949171
Short name T442
Test name
Test status
Simulation time 2011638753 ps
CPU time 24.64 seconds
Started Jul 20 05:27:07 PM PDT 24
Finished Jul 20 05:27:33 PM PDT 24
Peak memory 218188 kb
Host smart-cd3d7a63-5d93-414f-85a6-b79a756cb421
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895949171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2895949171
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1669487784
Short name T413
Test name
Test status
Simulation time 331635500 ps
CPU time 7.98 seconds
Started Jul 20 05:27:07 PM PDT 24
Finished Jul 20 05:27:16 PM PDT 24
Peak memory 210492 kb
Host smart-a72e3ada-e9d3-4ae7-ad6b-1fddde34f53e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669487784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1669487784
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2921233472
Short name T425
Test name
Test status
Simulation time 2891677405 ps
CPU time 24.8 seconds
Started Jul 20 05:27:07 PM PDT 24
Finished Jul 20 05:27:32 PM PDT 24
Peak memory 211496 kb
Host smart-3dac6e72-29c2-46e2-9037-ed38c4883632
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921233472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2921233472
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3426400105
Short name T100
Test name
Test status
Simulation time 1132698387 ps
CPU time 22.72 seconds
Started Jul 20 05:27:04 PM PDT 24
Finished Jul 20 05:27:27 PM PDT 24
Peak memory 211424 kb
Host smart-0b050af9-7e2f-428c-98dd-622f0ff53160
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426400105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3426400105
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.374849556
Short name T388
Test name
Test status
Simulation time 10602395906 ps
CPU time 19.75 seconds
Started Jul 20 05:26:59 PM PDT 24
Finished Jul 20 05:27:20 PM PDT 24
Peak memory 217884 kb
Host smart-bbb7fdf3-9632-4fd7-8a76-5e699f3951cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374849556 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.374849556
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2393055051
Short name T398
Test name
Test status
Simulation time 534563415 ps
CPU time 8.23 seconds
Started Jul 20 05:27:02 PM PDT 24
Finished Jul 20 05:27:12 PM PDT 24
Peak memory 210780 kb
Host smart-8b45e016-17da-4ba9-bac5-07ac33117908
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393055051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2393055051
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1943130442
Short name T369
Test name
Test status
Simulation time 8534692110 ps
CPU time 28.21 seconds
Started Jul 20 05:27:08 PM PDT 24
Finished Jul 20 05:27:37 PM PDT 24
Peak memory 210548 kb
Host smart-7644b90b-869a-4174-b3e0-862c79d9e1cb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943130442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1943130442
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1958498030
Short name T387
Test name
Test status
Simulation time 687971193 ps
CPU time 8.01 seconds
Started Jul 20 05:27:03 PM PDT 24
Finished Jul 20 05:27:12 PM PDT 24
Peak memory 210424 kb
Host smart-b92ad25d-f5f2-4ffb-9950-02d4a7d5f074
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958498030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1958498030
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.719496060
Short name T412
Test name
Test status
Simulation time 3002201664 ps
CPU time 17.71 seconds
Started Jul 20 05:27:02 PM PDT 24
Finished Jul 20 05:27:21 PM PDT 24
Peak memory 212280 kb
Host smart-815cde4e-9e62-4250-b065-360a87776dae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719496060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.719496060
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1034023622
Short name T374
Test name
Test status
Simulation time 17698212251 ps
CPU time 31.67 seconds
Started Jul 20 05:27:02 PM PDT 24
Finished Jul 20 05:27:35 PM PDT 24
Peak memory 216348 kb
Host smart-9e13ce68-ecd0-4c0a-b82e-7cc85760e446
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034023622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1034023622
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2209023493
Short name T449
Test name
Test status
Simulation time 9827337138 ps
CPU time 95.34 seconds
Started Jul 20 05:27:01 PM PDT 24
Finished Jul 20 05:28:38 PM PDT 24
Peak memory 212948 kb
Host smart-f07b33bc-b725-409c-b3db-96181efc16c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209023493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2209023493
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.4088262504
Short name T46
Test name
Test status
Simulation time 727852860 ps
CPU time 8.82 seconds
Started Jul 20 05:27:29 PM PDT 24
Finished Jul 20 05:27:39 PM PDT 24
Peak memory 216136 kb
Host smart-139d6798-ea0e-4a63-a3c4-b4e3f7a7f37d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088262504 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.4088262504
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.615130881
Short name T426
Test name
Test status
Simulation time 2894374621 ps
CPU time 24.58 seconds
Started Jul 20 05:27:31 PM PDT 24
Finished Jul 20 05:27:56 PM PDT 24
Peak memory 211920 kb
Host smart-27ccf314-1cbb-4a88-a198-10626c923dd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615130881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.615130881
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2310282850
Short name T389
Test name
Test status
Simulation time 30828122853 ps
CPU time 125.14 seconds
Started Jul 20 05:27:23 PM PDT 24
Finished Jul 20 05:29:30 PM PDT 24
Peak memory 213788 kb
Host smart-e0b2e55d-c439-4cd8-bc5f-1b9bd3d1b691
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310282850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2310282850
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2286544420
Short name T402
Test name
Test status
Simulation time 3780200616 ps
CPU time 14.36 seconds
Started Jul 20 05:27:30 PM PDT 24
Finished Jul 20 05:27:45 PM PDT 24
Peak memory 211260 kb
Host smart-8ab97327-cbec-4168-af8a-6c73fd84b128
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286544420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2286544420
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.339524749
Short name T438
Test name
Test status
Simulation time 1316218794 ps
CPU time 20.25 seconds
Started Jul 20 05:27:23 PM PDT 24
Finished Jul 20 05:27:45 PM PDT 24
Peak memory 218176 kb
Host smart-a5f6f8b3-69d9-4c39-9e17-74242631bcb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339524749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.339524749
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1195542366
Short name T418
Test name
Test status
Simulation time 38133967591 ps
CPU time 97.41 seconds
Started Jul 20 05:27:23 PM PDT 24
Finished Jul 20 05:29:03 PM PDT 24
Peak memory 218924 kb
Host smart-c704cf39-2667-44c3-a1d6-3b1ea182bfff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195542366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1195542366
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1460456908
Short name T375
Test name
Test status
Simulation time 4296294305 ps
CPU time 32.1 seconds
Started Jul 20 05:27:29 PM PDT 24
Finished Jul 20 05:28:02 PM PDT 24
Peak memory 216432 kb
Host smart-ce80d947-f938-4ebe-bcd0-cb2e11b79374
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460456908 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1460456908
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.912057711
Short name T383
Test name
Test status
Simulation time 14026721104 ps
CPU time 28.85 seconds
Started Jul 20 05:27:30 PM PDT 24
Finished Jul 20 05:27:59 PM PDT 24
Peak memory 210668 kb
Host smart-73094554-31de-4c26-8aef-7995c6bd2f79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912057711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.912057711
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4182260725
Short name T81
Test name
Test status
Simulation time 43380630494 ps
CPU time 124.01 seconds
Started Jul 20 05:27:30 PM PDT 24
Finished Jul 20 05:29:35 PM PDT 24
Peak memory 218912 kb
Host smart-d404bacd-8dd8-48a5-973a-d43d06be727f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182260725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.4182260725
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2747351345
Short name T440
Test name
Test status
Simulation time 431190454 ps
CPU time 14.84 seconds
Started Jul 20 05:27:33 PM PDT 24
Finished Jul 20 05:27:49 PM PDT 24
Peak memory 217288 kb
Host smart-2d73d295-f2f4-4965-9d7a-53a6d8097abe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747351345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2747351345
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1976231666
Short name T105
Test name
Test status
Simulation time 18463803094 ps
CPU time 158.77 seconds
Started Jul 20 05:27:29 PM PDT 24
Finished Jul 20 05:30:08 PM PDT 24
Peak memory 214340 kb
Host smart-c2867a21-9db8-45e7-af4a-377c9f0deac1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976231666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1976231666
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1278817241
Short name T377
Test name
Test status
Simulation time 5488932031 ps
CPU time 24.23 seconds
Started Jul 20 05:27:33 PM PDT 24
Finished Jul 20 05:27:58 PM PDT 24
Peak memory 216900 kb
Host smart-5618d013-fa6e-4db0-a003-ba7648b4c533
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278817241 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1278817241
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2117978494
Short name T392
Test name
Test status
Simulation time 167365904 ps
CPU time 8.18 seconds
Started Jul 20 05:27:29 PM PDT 24
Finished Jul 20 05:27:37 PM PDT 24
Peak memory 210460 kb
Host smart-26b17a0a-d5f5-4853-a2a5-5a039aae5a57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117978494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2117978494
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1335585299
Short name T378
Test name
Test status
Simulation time 16125245849 ps
CPU time 84.26 seconds
Started Jul 20 05:27:28 PM PDT 24
Finished Jul 20 05:28:53 PM PDT 24
Peak memory 214132 kb
Host smart-fdead186-9741-4d3d-8e83-a74cf09c008e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335585299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1335585299
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2605188178
Short name T409
Test name
Test status
Simulation time 2890933109 ps
CPU time 12.16 seconds
Started Jul 20 05:27:32 PM PDT 24
Finished Jul 20 05:27:44 PM PDT 24
Peak memory 212376 kb
Host smart-bba0119a-b5ce-4e1e-b12c-41f428cef05d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605188178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2605188178
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3193430147
Short name T47
Test name
Test status
Simulation time 167473805 ps
CPU time 10.7 seconds
Started Jul 20 05:27:31 PM PDT 24
Finished Jul 20 05:27:43 PM PDT 24
Peak memory 216412 kb
Host smart-7d286a24-5178-42b0-bdea-9d1762eaa3d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193430147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3193430147
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1964907661
Short name T109
Test name
Test status
Simulation time 3654994667 ps
CPU time 99.76 seconds
Started Jul 20 05:27:32 PM PDT 24
Finished Jul 20 05:29:13 PM PDT 24
Peak memory 213476 kb
Host smart-44388f4a-366d-49bf-918f-9dbd612fc385
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964907661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1964907661
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1221526557
Short name T362
Test name
Test status
Simulation time 8861467175 ps
CPU time 33.37 seconds
Started Jul 20 05:27:37 PM PDT 24
Finished Jul 20 05:28:11 PM PDT 24
Peak memory 216712 kb
Host smart-828dc1d4-9a9e-4b22-83ac-de43792452a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221526557 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1221526557
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.378463166
Short name T88
Test name
Test status
Simulation time 26385186531 ps
CPU time 29.39 seconds
Started Jul 20 05:27:39 PM PDT 24
Finished Jul 20 05:28:10 PM PDT 24
Peak memory 211960 kb
Host smart-9a3504e3-e0e8-4ccd-88c0-52ca4c9131bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378463166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.378463166
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3886181090
Short name T67
Test name
Test status
Simulation time 16558800647 ps
CPU time 85.62 seconds
Started Jul 20 05:27:32 PM PDT 24
Finished Jul 20 05:28:58 PM PDT 24
Peak memory 218540 kb
Host smart-af705c8f-e6e4-46ea-9a86-f7e0a3db8750
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886181090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3886181090
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.454165815
Short name T444
Test name
Test status
Simulation time 696859308 ps
CPU time 11.74 seconds
Started Jul 20 05:27:40 PM PDT 24
Finished Jul 20 05:27:52 PM PDT 24
Peak memory 212540 kb
Host smart-82e82ff9-f76e-4485-a08f-017cc615f5bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454165815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.454165815
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1846806350
Short name T448
Test name
Test status
Simulation time 1774788333 ps
CPU time 23.79 seconds
Started Jul 20 05:27:30 PM PDT 24
Finished Jul 20 05:27:54 PM PDT 24
Peak memory 218800 kb
Host smart-299322ae-3c96-49a1-85e3-f7e896b76148
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846806350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1846806350
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4239692407
Short name T436
Test name
Test status
Simulation time 7028502550 ps
CPU time 160.05 seconds
Started Jul 20 05:27:34 PM PDT 24
Finished Jul 20 05:30:14 PM PDT 24
Peak memory 214108 kb
Host smart-8ce9b0c5-e3bb-49a8-b299-ebb566d9445a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239692407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.4239692407
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.234672646
Short name T406
Test name
Test status
Simulation time 14427904662 ps
CPU time 28.81 seconds
Started Jul 20 05:27:41 PM PDT 24
Finished Jul 20 05:28:12 PM PDT 24
Peak memory 214928 kb
Host smart-2989894f-a4b1-4425-b865-9a41a79ee8ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234672646 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.234672646
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.722422637
Short name T450
Test name
Test status
Simulation time 849942323 ps
CPU time 13.54 seconds
Started Jul 20 05:27:38 PM PDT 24
Finished Jul 20 05:27:52 PM PDT 24
Peak memory 210672 kb
Host smart-01bba6c2-db5f-4c25-a6a5-ef4c82efd3c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722422637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.722422637
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.636955358
Short name T416
Test name
Test status
Simulation time 57584730009 ps
CPU time 108.39 seconds
Started Jul 20 05:27:38 PM PDT 24
Finished Jul 20 05:29:27 PM PDT 24
Peak memory 210824 kb
Host smart-cfb542fa-74e4-4041-9f44-98d060cad0e8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636955358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa
ssthru_mem_tl_intg_err.636955358
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2360347293
Short name T69
Test name
Test status
Simulation time 3367332673 ps
CPU time 30.68 seconds
Started Jul 20 05:27:38 PM PDT 24
Finished Jul 20 05:28:10 PM PDT 24
Peak memory 212188 kb
Host smart-cb0d8517-a750-4fcf-98aa-1905489822ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360347293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2360347293
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1510234135
Short name T437
Test name
Test status
Simulation time 2547570915 ps
CPU time 29.2 seconds
Started Jul 20 05:27:38 PM PDT 24
Finished Jul 20 05:28:08 PM PDT 24
Peak memory 218864 kb
Host smart-711eb199-30d7-416f-a59f-3d7e6e072a71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510234135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1510234135
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1477715825
Short name T113
Test name
Test status
Simulation time 8429635412 ps
CPU time 92.86 seconds
Started Jul 20 05:27:40 PM PDT 24
Finished Jul 20 05:29:13 PM PDT 24
Peak memory 218916 kb
Host smart-c9926bf9-947c-456d-8e5a-90878dedbc44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477715825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1477715825
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2760891539
Short name T393
Test name
Test status
Simulation time 729284322 ps
CPU time 9.49 seconds
Started Jul 20 05:27:38 PM PDT 24
Finished Jul 20 05:27:48 PM PDT 24
Peak memory 217136 kb
Host smart-517e9b59-ec28-4c4c-bf81-85d49890b8d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760891539 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2760891539
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2488762292
Short name T443
Test name
Test status
Simulation time 2669665367 ps
CPU time 20.88 seconds
Started Jul 20 05:27:38 PM PDT 24
Finished Jul 20 05:28:00 PM PDT 24
Peak memory 211652 kb
Host smart-dc1633cb-96ce-4ac9-9cbf-4aa4f984677d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488762292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2488762292
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.524875411
Short name T74
Test name
Test status
Simulation time 43233301141 ps
CPU time 171.34 seconds
Started Jul 20 05:27:41 PM PDT 24
Finished Jul 20 05:30:35 PM PDT 24
Peak memory 214848 kb
Host smart-0d0690a1-35c2-486e-8b37-1c3ee13b8e92
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524875411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.524875411
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1782651550
Short name T95
Test name
Test status
Simulation time 179632258 ps
CPU time 11.67 seconds
Started Jul 20 05:27:41 PM PDT 24
Finished Jul 20 05:27:55 PM PDT 24
Peak memory 212284 kb
Host smart-a63baa71-4d1e-468f-9f66-c8a7770c9a16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782651550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1782651550
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3692752613
Short name T427
Test name
Test status
Simulation time 424945168 ps
CPU time 13.89 seconds
Started Jul 20 05:27:39 PM PDT 24
Finished Jul 20 05:27:53 PM PDT 24
Peak memory 217424 kb
Host smart-0fb53dba-a980-4c2e-8701-6dbcd862a8ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692752613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3692752613
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1469971622
Short name T106
Test name
Test status
Simulation time 4790844476 ps
CPU time 94.72 seconds
Started Jul 20 05:27:37 PM PDT 24
Finished Jul 20 05:29:12 PM PDT 24
Peak memory 213860 kb
Host smart-cc794b3b-ca25-458f-839c-5f343c44b9c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469971622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1469971622
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1441530102
Short name T45
Test name
Test status
Simulation time 4635230543 ps
CPU time 14.22 seconds
Started Jul 20 05:27:38 PM PDT 24
Finished Jul 20 05:27:53 PM PDT 24
Peak memory 216504 kb
Host smart-372d4616-55a3-44fb-8107-b2d7f9cd6520
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441530102 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1441530102
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3383958197
Short name T430
Test name
Test status
Simulation time 13508395387 ps
CPU time 24.55 seconds
Started Jul 20 05:27:38 PM PDT 24
Finished Jul 20 05:28:04 PM PDT 24
Peak memory 210572 kb
Host smart-680c9d69-6303-4ae6-9215-9c48cc572ac3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383958197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3383958197
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1735289914
Short name T435
Test name
Test status
Simulation time 66907216347 ps
CPU time 127.82 seconds
Started Jul 20 05:27:39 PM PDT 24
Finished Jul 20 05:29:48 PM PDT 24
Peak memory 218852 kb
Host smart-de0a1f6e-3aed-4089-b77e-86926ae3a4e8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735289914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1735289914
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2223840216
Short name T59
Test name
Test status
Simulation time 15885869448 ps
CPU time 24.4 seconds
Started Jul 20 05:27:40 PM PDT 24
Finished Jul 20 05:28:05 PM PDT 24
Peak memory 212572 kb
Host smart-68f57bed-d2b3-45e6-ae78-7912068db698
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223840216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2223840216
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2239230184
Short name T424
Test name
Test status
Simulation time 2008114161 ps
CPU time 19.95 seconds
Started Jul 20 05:27:38 PM PDT 24
Finished Jul 20 05:27:59 PM PDT 24
Peak memory 217376 kb
Host smart-436b70da-4e12-4312-9f1d-fcb58f88458b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239230184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2239230184
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2290591127
Short name T456
Test name
Test status
Simulation time 858053757 ps
CPU time 80.5 seconds
Started Jul 20 05:27:37 PM PDT 24
Finished Jul 20 05:28:58 PM PDT 24
Peak memory 212584 kb
Host smart-8655a816-5371-4380-92fc-4739bb3e8fcf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290591127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2290591127
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.405989859
Short name T408
Test name
Test status
Simulation time 2517743382 ps
CPU time 19.2 seconds
Started Jul 20 05:27:46 PM PDT 24
Finished Jul 20 05:28:06 PM PDT 24
Peak memory 217224 kb
Host smart-d27b4a71-b77c-4d5e-a4fd-ea8e64ca3014
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405989859 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.405989859
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.854931329
Short name T98
Test name
Test status
Simulation time 6628431126 ps
CPU time 15.1 seconds
Started Jul 20 05:27:37 PM PDT 24
Finished Jul 20 05:27:53 PM PDT 24
Peak memory 211012 kb
Host smart-3d0197d4-91a1-4fc9-88f1-f33578ff93f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854931329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.854931329
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3969691711
Short name T447
Test name
Test status
Simulation time 22186614921 ps
CPU time 74.41 seconds
Started Jul 20 05:27:41 PM PDT 24
Finished Jul 20 05:28:58 PM PDT 24
Peak memory 213796 kb
Host smart-e38071da-5d8c-4948-8f3d-450b86b7c54a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969691711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3969691711
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.59686300
Short name T395
Test name
Test status
Simulation time 2743262636 ps
CPU time 8.54 seconds
Started Jul 20 05:27:39 PM PDT 24
Finished Jul 20 05:27:49 PM PDT 24
Peak memory 211252 kb
Host smart-82de903d-a0ee-4f6c-b8a4-52abc057939b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59686300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ct
rl_same_csr_outstanding.59686300
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.873455680
Short name T384
Test name
Test status
Simulation time 1180220977 ps
CPU time 15.21 seconds
Started Jul 20 05:27:36 PM PDT 24
Finished Jul 20 05:27:52 PM PDT 24
Peak memory 217140 kb
Host smart-68be29f3-4ea9-4c72-86f5-1e578e8e948b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873455680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.873455680
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.200495480
Short name T365
Test name
Test status
Simulation time 4369785362 ps
CPU time 21.24 seconds
Started Jul 20 05:27:47 PM PDT 24
Finished Jul 20 05:28:10 PM PDT 24
Peak memory 217956 kb
Host smart-3e684ea0-1cc7-4160-a7e4-a5b542a80d5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200495480 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.200495480
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1965971858
Short name T82
Test name
Test status
Simulation time 12851236009 ps
CPU time 26.76 seconds
Started Jul 20 05:27:46 PM PDT 24
Finished Jul 20 05:28:13 PM PDT 24
Peak memory 210984 kb
Host smart-f149c593-51bc-4c63-8044-3e49ebb6f784
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965971858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1965971858
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2927952528
Short name T79
Test name
Test status
Simulation time 28728190658 ps
CPU time 112.38 seconds
Started Jul 20 05:27:46 PM PDT 24
Finished Jul 20 05:29:40 PM PDT 24
Peak memory 213816 kb
Host smart-e84041a6-c441-4ec6-a9e0-9e3a26191821
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927952528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2927952528
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3695091855
Short name T93
Test name
Test status
Simulation time 7938756262 ps
CPU time 26.19 seconds
Started Jul 20 05:27:45 PM PDT 24
Finished Jul 20 05:28:12 PM PDT 24
Peak memory 212672 kb
Host smart-67318bb2-2d3c-4dd9-8633-41a3a306210d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695091855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3695091855
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3618052636
Short name T363
Test name
Test status
Simulation time 16368308659 ps
CPU time 23.04 seconds
Started Jul 20 05:27:45 PM PDT 24
Finished Jul 20 05:28:09 PM PDT 24
Peak memory 218816 kb
Host smart-0ff3b019-7fa0-4370-83ae-ec5a40444ba7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618052636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3618052636
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2074488820
Short name T434
Test name
Test status
Simulation time 8395605190 ps
CPU time 163.43 seconds
Started Jul 20 05:27:45 PM PDT 24
Finished Jul 20 05:30:29 PM PDT 24
Peak memory 214204 kb
Host smart-b052c39b-ebe9-4d24-aa93-ae9e9d7ed8e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074488820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2074488820
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2579142599
Short name T429
Test name
Test status
Simulation time 3945930978 ps
CPU time 30.42 seconds
Started Jul 20 05:27:43 PM PDT 24
Finished Jul 20 05:28:14 PM PDT 24
Peak memory 217112 kb
Host smart-9cdedc49-91c8-4a53-b02f-7eb08ed1bace
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579142599 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2579142599
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3600212378
Short name T87
Test name
Test status
Simulation time 9193525647 ps
CPU time 30.16 seconds
Started Jul 20 05:27:47 PM PDT 24
Finished Jul 20 05:28:19 PM PDT 24
Peak memory 211452 kb
Host smart-b84a3660-f169-44ca-8e29-c78014c3be30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600212378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3600212378
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1728291174
Short name T58
Test name
Test status
Simulation time 11334558278 ps
CPU time 119.8 seconds
Started Jul 20 05:27:46 PM PDT 24
Finished Jul 20 05:29:47 PM PDT 24
Peak memory 215168 kb
Host smart-ec0c9b8c-ce0f-4be7-92b2-ca05ddf5760e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728291174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1728291174
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3036188729
Short name T446
Test name
Test status
Simulation time 1321891990 ps
CPU time 10.55 seconds
Started Jul 20 05:27:45 PM PDT 24
Finished Jul 20 05:27:56 PM PDT 24
Peak memory 211004 kb
Host smart-a9a48258-5049-4d1e-b22e-42de1a858a7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036188729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3036188729
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3787774439
Short name T454
Test name
Test status
Simulation time 259961495 ps
CPU time 14.18 seconds
Started Jul 20 05:27:45 PM PDT 24
Finished Jul 20 05:28:00 PM PDT 24
Peak memory 218312 kb
Host smart-d22ec414-2017-439a-9227-df88a1fe33c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787774439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3787774439
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1672132627
Short name T431
Test name
Test status
Simulation time 2311515032 ps
CPU time 21.31 seconds
Started Jul 20 05:27:13 PM PDT 24
Finished Jul 20 05:27:35 PM PDT 24
Peak memory 211700 kb
Host smart-ea3e1484-d3f5-4eac-a332-00e08df5c396
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672132627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1672132627
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.599645915
Short name T452
Test name
Test status
Simulation time 4911710018 ps
CPU time 22.42 seconds
Started Jul 20 05:27:12 PM PDT 24
Finished Jul 20 05:27:36 PM PDT 24
Peak memory 211368 kb
Host smart-e2d8c98c-8cdc-45c9-b2c1-cede53c0e18c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599645915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.599645915
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.796371864
Short name T80
Test name
Test status
Simulation time 291590944 ps
CPU time 15.11 seconds
Started Jul 20 05:27:11 PM PDT 24
Finished Jul 20 05:27:27 PM PDT 24
Peak memory 211532 kb
Host smart-472c8a51-6991-406f-aeb2-8dbed70404a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796371864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.796371864
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2256948770
Short name T397
Test name
Test status
Simulation time 1647197092 ps
CPU time 18.5 seconds
Started Jul 20 05:27:16 PM PDT 24
Finished Jul 20 05:27:36 PM PDT 24
Peak memory 214408 kb
Host smart-80a33e7d-2901-4dfa-9516-774f353ff1c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256948770 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2256948770
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.113638346
Short name T72
Test name
Test status
Simulation time 10536431913 ps
CPU time 23.74 seconds
Started Jul 20 05:27:13 PM PDT 24
Finished Jul 20 05:27:38 PM PDT 24
Peak memory 212272 kb
Host smart-b52c3b9f-f6ee-4ba0-8c79-8c4239f6617c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113638346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.113638346
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1372293395
Short name T432
Test name
Test status
Simulation time 44945933710 ps
CPU time 26.32 seconds
Started Jul 20 05:27:12 PM PDT 24
Finished Jul 20 05:27:39 PM PDT 24
Peak memory 210820 kb
Host smart-46638cb8-2c5a-4908-82ce-3ca39a291c1c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372293395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1372293395
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.833123557
Short name T407
Test name
Test status
Simulation time 612380561 ps
CPU time 8.08 seconds
Started Jul 20 05:27:16 PM PDT 24
Finished Jul 20 05:27:25 PM PDT 24
Peak memory 210424 kb
Host smart-537ca43e-734d-4b57-81eb-bae52ac7719d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833123557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
833123557
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3178349350
Short name T415
Test name
Test status
Simulation time 2082870547 ps
CPU time 52.23 seconds
Started Jul 20 05:27:13 PM PDT 24
Finished Jul 20 05:28:06 PM PDT 24
Peak memory 213852 kb
Host smart-f02d745a-49de-47eb-9d71-52345bec707e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178349350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3178349350
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3848557874
Short name T381
Test name
Test status
Simulation time 688615433 ps
CPU time 8.16 seconds
Started Jul 20 05:27:13 PM PDT 24
Finished Jul 20 05:27:22 PM PDT 24
Peak memory 210964 kb
Host smart-c54091ca-3b57-419a-be8e-e5d52f191074
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848557874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3848557874
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2129492695
Short name T376
Test name
Test status
Simulation time 7535094155 ps
CPU time 24.92 seconds
Started Jul 20 05:27:16 PM PDT 24
Finished Jul 20 05:27:41 PM PDT 24
Peak memory 218436 kb
Host smart-f71f0818-33ff-4387-be26-a2a93549d585
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129492695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2129492695
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3765231308
Short name T108
Test name
Test status
Simulation time 3789255570 ps
CPU time 82.55 seconds
Started Jul 20 05:27:13 PM PDT 24
Finished Jul 20 05:28:37 PM PDT 24
Peak memory 213520 kb
Host smart-4ec996d1-9a22-4776-a4a3-f83fd4240f7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765231308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3765231308
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3204168124
Short name T84
Test name
Test status
Simulation time 688979532 ps
CPU time 8.28 seconds
Started Jul 20 05:27:14 PM PDT 24
Finished Jul 20 05:27:23 PM PDT 24
Peak memory 210556 kb
Host smart-6e28f152-98ba-47d8-8501-72f9a24b61a8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204168124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3204168124
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3509561874
Short name T404
Test name
Test status
Simulation time 662180553 ps
CPU time 8.82 seconds
Started Jul 20 05:27:13 PM PDT 24
Finished Jul 20 05:27:23 PM PDT 24
Peak memory 210812 kb
Host smart-e1e88b9d-962c-49c6-a178-631c16021243
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509561874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3509561874
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3760074510
Short name T400
Test name
Test status
Simulation time 705049410 ps
CPU time 15.37 seconds
Started Jul 20 05:27:12 PM PDT 24
Finished Jul 20 05:27:28 PM PDT 24
Peak memory 211968 kb
Host smart-a40eb7d9-78c3-43cd-9c69-aed063ca3305
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760074510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3760074510
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3453409120
Short name T385
Test name
Test status
Simulation time 3593469459 ps
CPU time 17.58 seconds
Started Jul 20 05:27:11 PM PDT 24
Finished Jul 20 05:27:30 PM PDT 24
Peak memory 216416 kb
Host smart-1da0df86-b18b-4161-ac0a-f6f763abbd4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453409120 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3453409120
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3756921072
Short name T366
Test name
Test status
Simulation time 809517284 ps
CPU time 11.18 seconds
Started Jul 20 05:27:12 PM PDT 24
Finished Jul 20 05:27:24 PM PDT 24
Peak memory 211660 kb
Host smart-624c5fb9-3ce1-4117-912e-ff3ae9ee3ba8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756921072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3756921072
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.619307896
Short name T370
Test name
Test status
Simulation time 18275367341 ps
CPU time 18.84 seconds
Started Jul 20 05:27:13 PM PDT 24
Finished Jul 20 05:27:33 PM PDT 24
Peak memory 210852 kb
Host smart-b1ba190c-bbe1-47ea-b118-7dd08fbfd11f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619307896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.619307896
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.272109656
Short name T361
Test name
Test status
Simulation time 7581927392 ps
CPU time 20.42 seconds
Started Jul 20 05:27:11 PM PDT 24
Finished Jul 20 05:27:33 PM PDT 24
Peak memory 210528 kb
Host smart-f6382da0-d91c-48cc-9a95-0154485cbef9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272109656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
272109656
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2939140649
Short name T364
Test name
Test status
Simulation time 16897781950 ps
CPU time 149.47 seconds
Started Jul 20 05:27:14 PM PDT 24
Finished Jul 20 05:29:44 PM PDT 24
Peak memory 214996 kb
Host smart-b80743e8-1c03-4f4b-b5da-3bf3ad3e248c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939140649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2939140649
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2182368388
Short name T97
Test name
Test status
Simulation time 2696013177 ps
CPU time 23.41 seconds
Started Jul 20 05:27:11 PM PDT 24
Finished Jul 20 05:27:35 PM PDT 24
Peak memory 212200 kb
Host smart-aa4d72e1-008d-4b53-a615-777023da43f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182368388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2182368388
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2686831108
Short name T451
Test name
Test status
Simulation time 12763018245 ps
CPU time 31.69 seconds
Started Jul 20 05:27:13 PM PDT 24
Finished Jul 20 05:27:46 PM PDT 24
Peak memory 218684 kb
Host smart-a49c12ab-8590-4779-8c79-a00c142c368b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686831108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2686831108
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1076035311
Short name T111
Test name
Test status
Simulation time 4150256723 ps
CPU time 174.74 seconds
Started Jul 20 05:27:12 PM PDT 24
Finished Jul 20 05:30:08 PM PDT 24
Peak memory 213884 kb
Host smart-3126480a-bf4c-4fb6-8a39-d9e8332addde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076035311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1076035311
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2354847695
Short name T83
Test name
Test status
Simulation time 13649764199 ps
CPU time 27.57 seconds
Started Jul 20 05:27:24 PM PDT 24
Finished Jul 20 05:27:53 PM PDT 24
Peak memory 211804 kb
Host smart-0a274cf1-2bb6-49a3-a8c1-a7fabab86c7c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354847695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2354847695
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3611563311
Short name T368
Test name
Test status
Simulation time 29596942901 ps
CPU time 27.71 seconds
Started Jul 20 05:27:23 PM PDT 24
Finished Jul 20 05:27:52 PM PDT 24
Peak memory 211728 kb
Host smart-b89005c8-b47b-4c4c-a319-8448051c4578
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611563311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3611563311
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3249964968
Short name T373
Test name
Test status
Simulation time 9573536970 ps
CPU time 19.3 seconds
Started Jul 20 05:27:25 PM PDT 24
Finished Jul 20 05:27:45 PM PDT 24
Peak memory 210556 kb
Host smart-aeca6a23-bfef-41c8-b714-5cdaa8dd3964
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249964968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3249964968
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4082721113
Short name T453
Test name
Test status
Simulation time 6124083385 ps
CPU time 26.1 seconds
Started Jul 20 05:27:22 PM PDT 24
Finished Jul 20 05:27:49 PM PDT 24
Peak memory 217988 kb
Host smart-b9b84537-cd63-4716-a2ef-a0a5777354e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082721113 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.4082721113
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2879448598
Short name T90
Test name
Test status
Simulation time 29152829625 ps
CPU time 27.63 seconds
Started Jul 20 05:27:29 PM PDT 24
Finished Jul 20 05:27:58 PM PDT 24
Peak memory 211912 kb
Host smart-643c4621-1e83-447a-8a17-f79353b1d635
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879448598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2879448598
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.317794590
Short name T399
Test name
Test status
Simulation time 13469890614 ps
CPU time 28.12 seconds
Started Jul 20 05:27:12 PM PDT 24
Finished Jul 20 05:27:41 PM PDT 24
Peak memory 210516 kb
Host smart-b7027c5d-a615-4b6e-9fdc-afd12ec2ea84
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317794590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.317794590
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.460019665
Short name T417
Test name
Test status
Simulation time 688542256 ps
CPU time 8.15 seconds
Started Jul 20 05:27:14 PM PDT 24
Finished Jul 20 05:27:23 PM PDT 24
Peak memory 210408 kb
Host smart-03c1afaa-9402-4d27-9d90-6debecfab158
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460019665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
460019665
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3901156658
Short name T420
Test name
Test status
Simulation time 43633823963 ps
CPU time 100.7 seconds
Started Jul 20 05:27:13 PM PDT 24
Finished Jul 20 05:28:55 PM PDT 24
Peak memory 213856 kb
Host smart-9b8357ea-5dab-4c50-9164-f59e8098429b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901156658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3901156658
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.255146289
Short name T391
Test name
Test status
Simulation time 10791596702 ps
CPU time 25.01 seconds
Started Jul 20 05:27:27 PM PDT 24
Finished Jul 20 05:27:53 PM PDT 24
Peak memory 212256 kb
Host smart-4e366f3b-fee2-418b-92cc-9d6954dc35dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255146289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.255146289
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3846993041
Short name T419
Test name
Test status
Simulation time 1824962902 ps
CPU time 20.58 seconds
Started Jul 20 05:27:12 PM PDT 24
Finished Jul 20 05:27:33 PM PDT 24
Peak memory 217192 kb
Host smart-6866dd3c-b245-43c2-9f17-ad1f6ea56050
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846993041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3846993041
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4185717740
Short name T107
Test name
Test status
Simulation time 13044608627 ps
CPU time 166.37 seconds
Started Jul 20 05:27:12 PM PDT 24
Finished Jul 20 05:29:59 PM PDT 24
Peak memory 218856 kb
Host smart-7effeb1a-6130-4f5b-88e5-6c004a9d05c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185717740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.4185717740
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.782066102
Short name T423
Test name
Test status
Simulation time 2404908214 ps
CPU time 22.97 seconds
Started Jul 20 05:27:24 PM PDT 24
Finished Jul 20 05:27:49 PM PDT 24
Peak memory 216492 kb
Host smart-2a440e8c-e59c-47ae-9e3e-fc2acd318d84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782066102 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.782066102
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3623242213
Short name T372
Test name
Test status
Simulation time 719504907 ps
CPU time 8.27 seconds
Started Jul 20 05:27:20 PM PDT 24
Finished Jul 20 05:27:29 PM PDT 24
Peak memory 210720 kb
Host smart-d2d60aed-c0e3-4535-affa-a5c6a94ed98c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623242213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3623242213
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1110849213
Short name T91
Test name
Test status
Simulation time 26499424439 ps
CPU time 117.59 seconds
Started Jul 20 05:27:22 PM PDT 24
Finished Jul 20 05:29:21 PM PDT 24
Peak memory 213752 kb
Host smart-fb28750c-08ad-4c4b-94cb-28a9c8a299b2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110849213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1110849213
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2949922126
Short name T428
Test name
Test status
Simulation time 662183275 ps
CPU time 8.27 seconds
Started Jul 20 05:27:26 PM PDT 24
Finished Jul 20 05:27:34 PM PDT 24
Peak memory 211204 kb
Host smart-bf9afb4e-4cf1-4023-b174-460ed943c4d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949922126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2949922126
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1209681956
Short name T371
Test name
Test status
Simulation time 9218403479 ps
CPU time 20.44 seconds
Started Jul 20 05:27:21 PM PDT 24
Finished Jul 20 05:27:43 PM PDT 24
Peak memory 218380 kb
Host smart-249e66ec-f118-4703-a45e-d07a1aefbd78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209681956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1209681956
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.833888458
Short name T55
Test name
Test status
Simulation time 759940579 ps
CPU time 153.95 seconds
Started Jul 20 05:27:23 PM PDT 24
Finished Jul 20 05:29:59 PM PDT 24
Peak memory 213704 kb
Host smart-84547e09-6353-4a2d-a625-4487864c0b4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833888458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.833888458
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2911239121
Short name T401
Test name
Test status
Simulation time 9852553166 ps
CPU time 24.05 seconds
Started Jul 20 05:27:23 PM PDT 24
Finished Jul 20 05:27:50 PM PDT 24
Peak memory 217640 kb
Host smart-bf6ba409-f44d-4d54-ac98-dab254ea8318
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911239121 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2911239121
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.738826597
Short name T71
Test name
Test status
Simulation time 339196821 ps
CPU time 8.27 seconds
Started Jul 20 05:27:22 PM PDT 24
Finished Jul 20 05:27:32 PM PDT 24
Peak memory 210572 kb
Host smart-590d1893-f774-4cf4-8304-e2af04006afe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738826597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.738826597
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1616162319
Short name T89
Test name
Test status
Simulation time 2062416145 ps
CPU time 70.92 seconds
Started Jul 20 05:27:23 PM PDT 24
Finished Jul 20 05:28:36 PM PDT 24
Peak memory 213664 kb
Host smart-02d689d3-f623-4a1e-8bb4-694709ccc211
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616162319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1616162319
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.576671993
Short name T380
Test name
Test status
Simulation time 1675540256 ps
CPU time 13.35 seconds
Started Jul 20 05:27:29 PM PDT 24
Finished Jul 20 05:27:43 PM PDT 24
Peak memory 211072 kb
Host smart-531b2ac0-a304-470d-89a7-b2cdb6e7323a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576671993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.576671993
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2238295371
Short name T396
Test name
Test status
Simulation time 2579775035 ps
CPU time 19.3 seconds
Started Jul 20 05:27:20 PM PDT 24
Finished Jul 20 05:27:40 PM PDT 24
Peak memory 217248 kb
Host smart-040a8a0f-dfad-4301-ad71-b02adc2a3fc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238295371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2238295371
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3106239534
Short name T112
Test name
Test status
Simulation time 4075302226 ps
CPU time 90.95 seconds
Started Jul 20 05:27:21 PM PDT 24
Finished Jul 20 05:28:53 PM PDT 24
Peak memory 212480 kb
Host smart-0b4785cb-de96-47cc-92d2-9c8b24134aa9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106239534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3106239534
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2226228138
Short name T422
Test name
Test status
Simulation time 7179932785 ps
CPU time 19.26 seconds
Started Jul 20 05:27:23 PM PDT 24
Finished Jul 20 05:27:45 PM PDT 24
Peak memory 217224 kb
Host smart-881c4d9a-208e-4d06-95ac-0d4f2605bc56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226228138 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2226228138
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1534738913
Short name T403
Test name
Test status
Simulation time 4357010748 ps
CPU time 31.81 seconds
Started Jul 20 05:27:23 PM PDT 24
Finished Jul 20 05:27:57 PM PDT 24
Peak memory 212004 kb
Host smart-2755b201-6f4c-403e-8e47-1a4b02a9ba65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534738913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1534738913
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1440640612
Short name T85
Test name
Test status
Simulation time 4877084876 ps
CPU time 37.47 seconds
Started Jul 20 05:27:24 PM PDT 24
Finished Jul 20 05:28:03 PM PDT 24
Peak memory 214132 kb
Host smart-910a8c08-be74-4f6f-9429-177ea1fb7276
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440640612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1440640612
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1260133650
Short name T96
Test name
Test status
Simulation time 905523095 ps
CPU time 14.38 seconds
Started Jul 20 05:27:22 PM PDT 24
Finished Jul 20 05:27:38 PM PDT 24
Peak memory 211968 kb
Host smart-07974b33-f9ff-4a7f-9b80-fb9b161c202d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260133650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1260133650
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.180718083
Short name T441
Test name
Test status
Simulation time 1882592997 ps
CPU time 22.6 seconds
Started Jul 20 05:27:25 PM PDT 24
Finished Jul 20 05:27:49 PM PDT 24
Peak memory 216932 kb
Host smart-60c53ab9-b6d4-4b36-aaa5-29950715ed67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180718083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.180718083
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.310301678
Short name T445
Test name
Test status
Simulation time 2218213516 ps
CPU time 93.27 seconds
Started Jul 20 05:27:20 PM PDT 24
Finished Jul 20 05:28:54 PM PDT 24
Peak memory 214572 kb
Host smart-d806d10f-f473-4ea9-8fa9-90d2b050b71b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310301678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.310301678
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4087210318
Short name T410
Test name
Test status
Simulation time 6289935422 ps
CPU time 25.69 seconds
Started Jul 20 05:27:23 PM PDT 24
Finished Jul 20 05:27:51 PM PDT 24
Peak memory 216940 kb
Host smart-faeca0f3-5d7e-43fc-99a6-63c1b5989efb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087210318 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.4087210318
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.455706606
Short name T390
Test name
Test status
Simulation time 3189904220 ps
CPU time 26.92 seconds
Started Jul 20 05:27:24 PM PDT 24
Finished Jul 20 05:27:52 PM PDT 24
Peak memory 211732 kb
Host smart-42bb0526-7044-46b9-b0fb-391025edd1ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455706606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.455706606
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1447643417
Short name T86
Test name
Test status
Simulation time 20712240889 ps
CPU time 96.57 seconds
Started Jul 20 05:27:23 PM PDT 24
Finished Jul 20 05:29:01 PM PDT 24
Peak memory 213916 kb
Host smart-3cd4ca75-4899-49e7-bf87-5733259f876f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447643417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1447643417
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3562520721
Short name T94
Test name
Test status
Simulation time 8346085747 ps
CPU time 33.49 seconds
Started Jul 20 05:27:22 PM PDT 24
Finished Jul 20 05:27:57 PM PDT 24
Peak memory 212460 kb
Host smart-b7ec932d-3905-4405-aad7-e38b5e4ecf02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562520721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3562520721
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2893206768
Short name T439
Test name
Test status
Simulation time 842907607 ps
CPU time 16.99 seconds
Started Jul 20 05:27:23 PM PDT 24
Finished Jul 20 05:27:42 PM PDT 24
Peak memory 218776 kb
Host smart-5ebc902d-c3d6-43c6-80bb-89d44034ec5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893206768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2893206768
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2085874318
Short name T394
Test name
Test status
Simulation time 1395870016 ps
CPU time 13.16 seconds
Started Jul 20 05:27:20 PM PDT 24
Finished Jul 20 05:27:34 PM PDT 24
Peak memory 216496 kb
Host smart-f9889fc1-07b1-4748-9e7f-f40b8945ed0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085874318 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2085874318
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1025953970
Short name T99
Test name
Test status
Simulation time 18746287043 ps
CPU time 23.02 seconds
Started Jul 20 05:27:20 PM PDT 24
Finished Jul 20 05:27:44 PM PDT 24
Peak memory 211724 kb
Host smart-6127fdd7-5bd3-4097-9730-a3980206d4b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025953970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1025953970
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1034694108
Short name T455
Test name
Test status
Simulation time 25667337932 ps
CPU time 199.18 seconds
Started Jul 20 05:27:23 PM PDT 24
Finished Jul 20 05:30:44 PM PDT 24
Peak memory 216020 kb
Host smart-e2534ae2-4c6d-4721-bb30-6c50b5d82c2b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034694108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1034694108
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.408552469
Short name T68
Test name
Test status
Simulation time 12624441895 ps
CPU time 25.11 seconds
Started Jul 20 05:27:21 PM PDT 24
Finished Jul 20 05:27:47 PM PDT 24
Peak memory 212368 kb
Host smart-06a94092-17a6-4c19-99f7-a51a38efda8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408552469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.408552469
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3145872392
Short name T367
Test name
Test status
Simulation time 688798416 ps
CPU time 12.92 seconds
Started Jul 20 05:27:24 PM PDT 24
Finished Jul 20 05:27:39 PM PDT 24
Peak memory 217188 kb
Host smart-d6339678-03ad-419c-b942-f7d32b67fbf0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145872392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3145872392
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2016031181
Short name T110
Test name
Test status
Simulation time 12163384088 ps
CPU time 171.76 seconds
Started Jul 20 05:27:21 PM PDT 24
Finished Jul 20 05:30:14 PM PDT 24
Peak memory 213976 kb
Host smart-d044c491-f359-4c91-a11f-a94239848610
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016031181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2016031181
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.952004293
Short name T264
Test name
Test status
Simulation time 1234339590 ps
CPU time 17.07 seconds
Started Jul 20 05:27:47 PM PDT 24
Finished Jul 20 05:28:05 PM PDT 24
Peak memory 217160 kb
Host smart-e81ae133-26e2-4af3-878e-946d589b7ced
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952004293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.952004293
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2727658941
Short name T186
Test name
Test status
Simulation time 162583544056 ps
CPU time 784.92 seconds
Started Jul 20 05:27:47 PM PDT 24
Finished Jul 20 05:40:53 PM PDT 24
Peak memory 217036 kb
Host smart-1e635234-1e53-4be1-b8da-5a7aae14b79c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727658941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2727658941
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2490256517
Short name T163
Test name
Test status
Simulation time 6223170907 ps
CPU time 58.08 seconds
Started Jul 20 05:27:45 PM PDT 24
Finished Jul 20 05:28:44 PM PDT 24
Peak memory 219396 kb
Host smart-e65bce70-22dd-42c0-8c02-861c751d4743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490256517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2490256517
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2166256777
Short name T51
Test name
Test status
Simulation time 340050050 ps
CPU time 10.58 seconds
Started Jul 20 05:27:48 PM PDT 24
Finished Jul 20 05:28:00 PM PDT 24
Peak memory 219312 kb
Host smart-d10edd77-9408-4d9d-8610-b1aba543eecf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2166256777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2166256777
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3180235798
Short name T20
Test name
Test status
Simulation time 16891445170 ps
CPU time 248.19 seconds
Started Jul 20 05:27:47 PM PDT 24
Finished Jul 20 05:31:57 PM PDT 24
Peak memory 238276 kb
Host smart-bfb2fb5b-eaf1-476c-a1ef-575393867177
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180235798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3180235798
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1889081077
Short name T310
Test name
Test status
Simulation time 6462071089 ps
CPU time 60.83 seconds
Started Jul 20 05:27:47 PM PDT 24
Finished Jul 20 05:28:49 PM PDT 24
Peak memory 216956 kb
Host smart-941a936c-6634-4095-a910-e1c3caeb7a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889081077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1889081077
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.316454846
Short name T175
Test name
Test status
Simulation time 53146949985 ps
CPU time 60.61 seconds
Started Jul 20 05:27:46 PM PDT 24
Finished Jul 20 05:28:48 PM PDT 24
Peak memory 218416 kb
Host smart-0ac6a720-b928-4838-9621-d1e50a46f1f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316454846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.316454846
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1246120352
Short name T215
Test name
Test status
Simulation time 3068661271 ps
CPU time 13.84 seconds
Started Jul 20 05:27:53 PM PDT 24
Finished Jul 20 05:28:09 PM PDT 24
Peak memory 217204 kb
Host smart-851b9c99-eb48-47c1-8044-16512babd13d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246120352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1246120352
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.137132691
Short name T293
Test name
Test status
Simulation time 112843617823 ps
CPU time 586.94 seconds
Started Jul 20 05:27:53 PM PDT 24
Finished Jul 20 05:37:42 PM PDT 24
Peak memory 219584 kb
Host smart-4a3d56c6-f438-4a36-851a-acaee765caf6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137132691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.137132691
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3059767405
Short name T227
Test name
Test status
Simulation time 27452056170 ps
CPU time 59.83 seconds
Started Jul 20 05:27:52 PM PDT 24
Finished Jul 20 05:28:54 PM PDT 24
Peak memory 219324 kb
Host smart-9f1c6a6a-c736-4492-bfd0-ae0f4916bfe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059767405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3059767405
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3297317249
Short name T359
Test name
Test status
Simulation time 13424519179 ps
CPU time 26.79 seconds
Started Jul 20 05:27:56 PM PDT 24
Finished Jul 20 05:28:24 PM PDT 24
Peak memory 219400 kb
Host smart-d72e35d9-c27f-4f39-a3af-c5ab2f57c98b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3297317249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3297317249
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.394526381
Short name T21
Test name
Test status
Simulation time 15100480624 ps
CPU time 138.23 seconds
Started Jul 20 05:27:54 PM PDT 24
Finished Jul 20 05:30:14 PM PDT 24
Peak memory 236292 kb
Host smart-8e36e7a9-d358-4bf4-bc49-0cdbcf780f42
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394526381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.394526381
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2792505302
Short name T284
Test name
Test status
Simulation time 6743882815 ps
CPU time 57.57 seconds
Started Jul 20 05:27:52 PM PDT 24
Finished Jul 20 05:28:51 PM PDT 24
Peak memory 217296 kb
Host smart-c1ea9f08-bc29-4e7c-8c32-c25da275754e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792505302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2792505302
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.323968487
Short name T322
Test name
Test status
Simulation time 10399701342 ps
CPU time 47.11 seconds
Started Jul 20 05:27:53 PM PDT 24
Finished Jul 20 05:28:42 PM PDT 24
Peak memory 219348 kb
Host smart-c361af61-402b-456a-af3a-90dc551a2466
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323968487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.323968487
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3330727820
Short name T312
Test name
Test status
Simulation time 16423327059 ps
CPU time 19.34 seconds
Started Jul 20 05:28:03 PM PDT 24
Finished Jul 20 05:28:24 PM PDT 24
Peak memory 213356 kb
Host smart-4c65d7ec-9995-4f8e-9b2f-951f9d4a9866
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330727820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3330727820
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1423612176
Short name T210
Test name
Test status
Simulation time 323685742180 ps
CPU time 925.81 seconds
Started Jul 20 05:28:02 PM PDT 24
Finished Jul 20 05:43:29 PM PDT 24
Peak memory 229244 kb
Host smart-0e93b6c5-b94b-43fc-9e44-6497057dec2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423612176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1423612176
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3183775708
Short name T144
Test name
Test status
Simulation time 7695026322 ps
CPU time 64.59 seconds
Started Jul 20 05:28:03 PM PDT 24
Finished Jul 20 05:29:09 PM PDT 24
Peak memory 219400 kb
Host smart-1f054782-934e-430e-add4-aca27f1983c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183775708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3183775708
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2352832609
Short name T314
Test name
Test status
Simulation time 341862333 ps
CPU time 12.83 seconds
Started Jul 20 05:28:02 PM PDT 24
Finished Jul 20 05:28:17 PM PDT 24
Peak memory 218472 kb
Host smart-df4164f3-c86d-4a3b-9da7-0c0f66e17f0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2352832609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2352832609
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.640366006
Short name T117
Test name
Test status
Simulation time 5397427743 ps
CPU time 57.25 seconds
Started Jul 20 05:28:02 PM PDT 24
Finished Jul 20 05:29:01 PM PDT 24
Peak memory 215928 kb
Host smart-bfdd939a-5180-43f0-8ded-5e0c49e9c85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640366006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.640366006
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3509412214
Short name T233
Test name
Test status
Simulation time 40303346249 ps
CPU time 200.56 seconds
Started Jul 20 05:28:02 PM PDT 24
Finished Jul 20 05:31:24 PM PDT 24
Peak memory 220116 kb
Host smart-a1276af7-79af-444a-a8f6-42d9e967970b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509412214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3509412214
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2320893045
Short name T352
Test name
Test status
Simulation time 660466770 ps
CPU time 8.48 seconds
Started Jul 20 05:28:03 PM PDT 24
Finished Jul 20 05:28:13 PM PDT 24
Peak memory 217100 kb
Host smart-d67a1110-ac19-4451-b70f-8c3496777f5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320893045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2320893045
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1052948692
Short name T159
Test name
Test status
Simulation time 2654131149 ps
CPU time 161.37 seconds
Started Jul 20 05:28:04 PM PDT 24
Finished Jul 20 05:30:47 PM PDT 24
Peak memory 219544 kb
Host smart-72d16c99-562f-4ec8-a322-654bb7885196
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052948692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1052948692
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3186511355
Short name T292
Test name
Test status
Simulation time 335604844 ps
CPU time 19.3 seconds
Started Jul 20 05:28:01 PM PDT 24
Finished Jul 20 05:28:21 PM PDT 24
Peak memory 219280 kb
Host smart-3caeffad-c97f-40cc-9f38-85c3e8a1666e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186511355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3186511355
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.160008781
Short name T280
Test name
Test status
Simulation time 1086450612 ps
CPU time 17.27 seconds
Started Jul 20 05:28:04 PM PDT 24
Finished Jul 20 05:28:23 PM PDT 24
Peak memory 211424 kb
Host smart-3421d2fe-0e94-486e-bb14-8059908fcbdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=160008781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.160008781
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3653882210
Short name T49
Test name
Test status
Simulation time 349758915 ps
CPU time 21.06 seconds
Started Jul 20 05:28:02 PM PDT 24
Finished Jul 20 05:28:25 PM PDT 24
Peak memory 216700 kb
Host smart-0835dfdd-9790-4f3f-8b98-5399b8122bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653882210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3653882210
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1712039459
Short name T283
Test name
Test status
Simulation time 15951915633 ps
CPU time 148.93 seconds
Started Jul 20 05:28:04 PM PDT 24
Finished Jul 20 05:30:35 PM PDT 24
Peak memory 220512 kb
Host smart-f4415818-dc2f-41e9-8581-b9aba52b5462
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712039459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1712039459
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.534688549
Short name T149
Test name
Test status
Simulation time 4609392300 ps
CPU time 24.85 seconds
Started Jul 20 05:28:11 PM PDT 24
Finished Jul 20 05:28:37 PM PDT 24
Peak memory 213276 kb
Host smart-67c51cf9-8b39-431b-967e-2ef5f2361ee2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534688549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.534688549
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.561735584
Short name T164
Test name
Test status
Simulation time 40180745985 ps
CPU time 571.21 seconds
Started Jul 20 05:28:02 PM PDT 24
Finished Jul 20 05:37:34 PM PDT 24
Peak memory 224812 kb
Host smart-566d652d-0b5a-4eaf-bcdd-a314237929a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561735584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.561735584
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1411431061
Short name T349
Test name
Test status
Simulation time 1319698888 ps
CPU time 19.1 seconds
Started Jul 20 05:28:03 PM PDT 24
Finished Jul 20 05:28:24 PM PDT 24
Peak memory 219380 kb
Host smart-9f3cb741-f53f-4b17-b459-7f46c13b798b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411431061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1411431061
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1678272669
Short name T167
Test name
Test status
Simulation time 1364137751 ps
CPU time 14.78 seconds
Started Jul 20 05:28:00 PM PDT 24
Finished Jul 20 05:28:16 PM PDT 24
Peak memory 218668 kb
Host smart-3f1ebfd9-94e4-4775-995c-a93b51c129d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1678272669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1678272669
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.4191956726
Short name T317
Test name
Test status
Simulation time 10436344543 ps
CPU time 47.76 seconds
Started Jul 20 05:28:05 PM PDT 24
Finished Jul 20 05:28:54 PM PDT 24
Peak memory 216988 kb
Host smart-51b66516-d673-4523-befa-cd70fc469c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191956726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.4191956726
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.31421578
Short name T17
Test name
Test status
Simulation time 29302361753 ps
CPU time 158.83 seconds
Started Jul 20 05:28:03 PM PDT 24
Finished Jul 20 05:30:43 PM PDT 24
Peak memory 220904 kb
Host smart-c5879531-dfb0-417f-9e74-96d58ba5baf2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31421578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 12.rom_ctrl_stress_all.31421578
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3335293379
Short name T191
Test name
Test status
Simulation time 172752166 ps
CPU time 8.46 seconds
Started Jul 20 05:28:11 PM PDT 24
Finished Jul 20 05:28:20 PM PDT 24
Peak memory 217068 kb
Host smart-1f3f791d-53a5-4682-969b-9e0e3b167c71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335293379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3335293379
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2402115114
Short name T290
Test name
Test status
Simulation time 3215854760 ps
CPU time 236.01 seconds
Started Jul 20 05:28:10 PM PDT 24
Finished Jul 20 05:32:07 PM PDT 24
Peak memory 240116 kb
Host smart-3f827dfd-7540-4837-94b4-c1e12143b382
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402115114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2402115114
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1488663827
Short name T289
Test name
Test status
Simulation time 17667818640 ps
CPU time 47.31 seconds
Started Jul 20 05:28:11 PM PDT 24
Finished Jul 20 05:29:00 PM PDT 24
Peak memory 219388 kb
Host smart-dc2d7a29-512e-416a-a3b9-9ca0464963e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488663827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1488663827
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3887635927
Short name T328
Test name
Test status
Simulation time 4165680474 ps
CPU time 33.54 seconds
Started Jul 20 05:28:11 PM PDT 24
Finished Jul 20 05:28:46 PM PDT 24
Peak memory 211496 kb
Host smart-653e3ab2-424e-45f9-bcea-70c9a4be1095
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3887635927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3887635927
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1536754547
Short name T120
Test name
Test status
Simulation time 22649239513 ps
CPU time 55.08 seconds
Started Jul 20 05:28:13 PM PDT 24
Finished Jul 20 05:29:09 PM PDT 24
Peak memory 217480 kb
Host smart-65fd2836-f002-4d32-9085-76c2d08f21dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536754547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1536754547
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2279352063
Short name T245
Test name
Test status
Simulation time 25103455216 ps
CPU time 251.4 seconds
Started Jul 20 05:28:12 PM PDT 24
Finished Jul 20 05:32:24 PM PDT 24
Peak memory 222240 kb
Host smart-819bf09a-cea8-479d-9cbd-a0d93603fd2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279352063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2279352063
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3035833911
Short name T64
Test name
Test status
Simulation time 2318276894 ps
CPU time 21.95 seconds
Started Jul 20 05:28:11 PM PDT 24
Finished Jul 20 05:28:34 PM PDT 24
Peak memory 217204 kb
Host smart-2c2a3412-e853-41d5-bc07-310d34a125d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035833911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3035833911
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2666748480
Short name T242
Test name
Test status
Simulation time 35335899130 ps
CPU time 359.84 seconds
Started Jul 20 05:28:11 PM PDT 24
Finished Jul 20 05:34:13 PM PDT 24
Peak memory 217964 kb
Host smart-9a6a2ab8-390b-4806-8993-df0a936d0725
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666748480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2666748480
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3208230279
Short name T217
Test name
Test status
Simulation time 6858175204 ps
CPU time 56.82 seconds
Started Jul 20 05:28:12 PM PDT 24
Finished Jul 20 05:29:10 PM PDT 24
Peak memory 219348 kb
Host smart-e931e271-419d-467d-8c86-42c8801e148f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208230279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3208230279
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1588554645
Short name T133
Test name
Test status
Simulation time 8739267610 ps
CPU time 33.05 seconds
Started Jul 20 05:28:11 PM PDT 24
Finished Jul 20 05:28:45 PM PDT 24
Peak memory 219372 kb
Host smart-8cdf80af-048f-43df-a602-fb920fe1b91c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1588554645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1588554645
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2356226806
Short name T37
Test name
Test status
Simulation time 2654120797 ps
CPU time 31.35 seconds
Started Jul 20 05:28:12 PM PDT 24
Finished Jul 20 05:28:45 PM PDT 24
Peak memory 216104 kb
Host smart-c862ba76-1347-4a3d-acdb-5493a2146f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356226806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2356226806
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1723404131
Short name T75
Test name
Test status
Simulation time 31075048090 ps
CPU time 176.35 seconds
Started Jul 20 05:28:11 PM PDT 24
Finished Jul 20 05:31:09 PM PDT 24
Peak memory 227584 kb
Host smart-9b5f1f72-ad44-4c93-af61-e269c2246430
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723404131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1723404131
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1331068619
Short name T41
Test name
Test status
Simulation time 96774054712 ps
CPU time 1794.76 seconds
Started Jul 20 05:28:11 PM PDT 24
Finished Jul 20 05:58:07 PM PDT 24
Peak memory 233440 kb
Host smart-c1e39d03-172b-4cdf-adc8-69e4ba550e52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331068619 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.1331068619
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3393856168
Short name T23
Test name
Test status
Simulation time 174346691 ps
CPU time 8.25 seconds
Started Jul 20 05:28:11 PM PDT 24
Finished Jul 20 05:28:20 PM PDT 24
Peak memory 217176 kb
Host smart-896487d5-dc62-4a71-8fbc-59c378b94f4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393856168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3393856168
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3511633851
Short name T31
Test name
Test status
Simulation time 97567145001 ps
CPU time 416.7 seconds
Started Jul 20 05:28:13 PM PDT 24
Finished Jul 20 05:35:11 PM PDT 24
Peak memory 225824 kb
Host smart-a56556f6-4b1c-4bfd-aeb3-63cd895036fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511633851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3511633851
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.593049045
Short name T269
Test name
Test status
Simulation time 17143362394 ps
CPU time 32.81 seconds
Started Jul 20 05:28:12 PM PDT 24
Finished Jul 20 05:28:46 PM PDT 24
Peak memory 212044 kb
Host smart-5b761826-edf8-4b74-85a7-80780f0610e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=593049045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.593049045
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.2631130181
Short name T185
Test name
Test status
Simulation time 1486427482 ps
CPU time 19.89 seconds
Started Jul 20 05:28:10 PM PDT 24
Finished Jul 20 05:28:31 PM PDT 24
Peak memory 216640 kb
Host smart-95867cac-410a-43a9-a418-526be0f22106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631130181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2631130181
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2639478151
Short name T218
Test name
Test status
Simulation time 747950692 ps
CPU time 39.24 seconds
Started Jul 20 05:28:11 PM PDT 24
Finished Jul 20 05:28:51 PM PDT 24
Peak memory 219372 kb
Host smart-3bf4f15f-ce6c-4a49-9436-5d824a9f02da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639478151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2639478151
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.215646157
Short name T321
Test name
Test status
Simulation time 661328419 ps
CPU time 8.38 seconds
Started Jul 20 05:28:12 PM PDT 24
Finished Jul 20 05:28:22 PM PDT 24
Peak memory 217104 kb
Host smart-a22c969a-13ac-44f4-82b4-46bac9ce0fdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215646157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.215646157
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2861456811
Short name T123
Test name
Test status
Simulation time 12950551240 ps
CPU time 218.33 seconds
Started Jul 20 05:28:11 PM PDT 24
Finished Jul 20 05:31:50 PM PDT 24
Peak memory 237956 kb
Host smart-b5f1bae7-bd85-46db-8b75-04176f75712e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861456811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2861456811
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3740747254
Short name T300
Test name
Test status
Simulation time 5676982058 ps
CPU time 18.48 seconds
Started Jul 20 05:28:11 PM PDT 24
Finished Jul 20 05:28:30 PM PDT 24
Peak memory 217752 kb
Host smart-afa752ef-f021-474f-91cc-4c3be1082758
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3740747254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3740747254
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.138993896
Short name T198
Test name
Test status
Simulation time 6326292193 ps
CPU time 62.64 seconds
Started Jul 20 05:28:12 PM PDT 24
Finished Jul 20 05:29:16 PM PDT 24
Peak memory 217356 kb
Host smart-9b36fb67-bc41-4b0e-8065-1ceec8f228fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138993896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.138993896
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3221621335
Short name T360
Test name
Test status
Simulation time 11102758290 ps
CPU time 52.63 seconds
Started Jul 20 05:28:10 PM PDT 24
Finished Jul 20 05:29:04 PM PDT 24
Peak memory 219324 kb
Host smart-5f0a9adf-2f58-4eae-a428-c75289b10b4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221621335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3221621335
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.4025868589
Short name T165
Test name
Test status
Simulation time 169313831 ps
CPU time 8.51 seconds
Started Jul 20 05:28:12 PM PDT 24
Finished Jul 20 05:28:21 PM PDT 24
Peak memory 217104 kb
Host smart-8a17883b-a8c2-4008-9098-c5730df45a75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025868589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.4025868589
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2954478346
Short name T240
Test name
Test status
Simulation time 120336478947 ps
CPU time 224.49 seconds
Started Jul 20 05:28:09 PM PDT 24
Finished Jul 20 05:31:54 PM PDT 24
Peak memory 223764 kb
Host smart-3c42f2af-6d3c-4bc9-9ea6-8f3fc7ff08bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954478346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2954478346
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2469047189
Short name T287
Test name
Test status
Simulation time 18385760738 ps
CPU time 47.51 seconds
Started Jul 20 05:28:10 PM PDT 24
Finished Jul 20 05:28:58 PM PDT 24
Peak memory 219376 kb
Host smart-38fc8db3-501a-42c2-ae73-c32554cd7844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469047189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2469047189
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1869949186
Short name T223
Test name
Test status
Simulation time 4169809753 ps
CPU time 34.62 seconds
Started Jul 20 05:28:10 PM PDT 24
Finished Jul 20 05:28:46 PM PDT 24
Peak memory 219400 kb
Host smart-765489da-8aef-4173-87b1-0ebc454eadd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1869949186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1869949186
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1871379822
Short name T52
Test name
Test status
Simulation time 365342714 ps
CPU time 20 seconds
Started Jul 20 05:28:11 PM PDT 24
Finished Jul 20 05:28:33 PM PDT 24
Peak memory 216796 kb
Host smart-2c5b938e-366f-4df3-8d26-549bfe442b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871379822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1871379822
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1820792586
Short name T309
Test name
Test status
Simulation time 3599499854 ps
CPU time 31.56 seconds
Started Jul 20 05:28:10 PM PDT 24
Finished Jul 20 05:28:43 PM PDT 24
Peak memory 218244 kb
Host smart-52342263-f852-4a78-a565-76e56e54a49b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820792586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1820792586
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2826416333
Short name T61
Test name
Test status
Simulation time 2506191799 ps
CPU time 16.37 seconds
Started Jul 20 05:28:20 PM PDT 24
Finished Jul 20 05:28:38 PM PDT 24
Peak memory 213344 kb
Host smart-cb1b848a-b344-4ed2-903a-5cc7a1a20d43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826416333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2826416333
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3059752343
Short name T231
Test name
Test status
Simulation time 85140214157 ps
CPU time 692.02 seconds
Started Jul 20 05:28:19 PM PDT 24
Finished Jul 20 05:39:52 PM PDT 24
Peak memory 235336 kb
Host smart-80a7108c-2e25-48f8-a7a5-f79793d0799c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059752343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3059752343
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2484225840
Short name T295
Test name
Test status
Simulation time 349846425 ps
CPU time 18.87 seconds
Started Jul 20 05:28:20 PM PDT 24
Finished Jul 20 05:28:40 PM PDT 24
Peak memory 219260 kb
Host smart-cb9222f7-2a4a-4f83-b6d3-2b8ed9e2d95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484225840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2484225840
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2387695227
Short name T181
Test name
Test status
Simulation time 179760853 ps
CPU time 10.74 seconds
Started Jul 20 05:28:23 PM PDT 24
Finished Jul 20 05:28:35 PM PDT 24
Peak memory 219260 kb
Host smart-c26243d7-2642-4a79-9f44-33ee550810e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2387695227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2387695227
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.3654710765
Short name T340
Test name
Test status
Simulation time 9191061310 ps
CPU time 57.54 seconds
Started Jul 20 05:28:20 PM PDT 24
Finished Jul 20 05:29:19 PM PDT 24
Peak memory 217276 kb
Host smart-15ef20c6-f7d6-42c2-8551-ab9c2160ee48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654710765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.3654710765
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.4267713367
Short name T247
Test name
Test status
Simulation time 1063473547 ps
CPU time 62.74 seconds
Started Jul 20 05:28:19 PM PDT 24
Finished Jul 20 05:29:22 PM PDT 24
Peak memory 220512 kb
Host smart-34006cbc-5a07-4f91-a9a9-f2e5cc12de80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267713367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.4267713367
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.4145782735
Short name T199
Test name
Test status
Simulation time 169426372 ps
CPU time 8.37 seconds
Started Jul 20 05:28:20 PM PDT 24
Finished Jul 20 05:28:30 PM PDT 24
Peak memory 217088 kb
Host smart-0cc9a26d-6679-4472-afe8-fc9fca0c2f15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145782735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.4145782735
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1770198277
Short name T13
Test name
Test status
Simulation time 11261479398 ps
CPU time 207.97 seconds
Started Jul 20 05:28:19 PM PDT 24
Finished Jul 20 05:31:49 PM PDT 24
Peak memory 239436 kb
Host smart-2ee6d2e1-d216-4303-bb21-b187b2d04d20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770198277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1770198277
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3878601078
Short name T281
Test name
Test status
Simulation time 349943268 ps
CPU time 19.13 seconds
Started Jul 20 05:28:20 PM PDT 24
Finished Jul 20 05:28:40 PM PDT 24
Peak memory 219308 kb
Host smart-01dc8eda-261d-4fcf-8228-c3da1d6dd2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878601078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3878601078
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2087329043
Short name T187
Test name
Test status
Simulation time 6168567354 ps
CPU time 19.54 seconds
Started Jul 20 05:28:20 PM PDT 24
Finished Jul 20 05:28:42 PM PDT 24
Peak memory 212056 kb
Host smart-ebc2d546-80d7-4e53-835f-140be592c9ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2087329043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2087329043
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3812886463
Short name T197
Test name
Test status
Simulation time 47350187849 ps
CPU time 52.86 seconds
Started Jul 20 05:28:19 PM PDT 24
Finished Jul 20 05:29:12 PM PDT 24
Peak memory 218484 kb
Host smart-895a3b13-fc15-4f53-b46d-4f0bfd723603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812886463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3812886463
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2401199356
Short name T114
Test name
Test status
Simulation time 16927313151 ps
CPU time 137.32 seconds
Started Jul 20 05:28:21 PM PDT 24
Finished Jul 20 05:30:41 PM PDT 24
Peak memory 220968 kb
Host smart-a33d8e71-2bbd-41c7-95eb-b1c35486a715
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401199356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2401199356
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.733870630
Short name T304
Test name
Test status
Simulation time 2994899149 ps
CPU time 24.4 seconds
Started Jul 20 05:27:56 PM PDT 24
Finished Jul 20 05:28:21 PM PDT 24
Peak memory 217184 kb
Host smart-fb402c56-f60e-48cb-9d67-c003916a98f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733870630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.733870630
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2514867275
Short name T297
Test name
Test status
Simulation time 26161144998 ps
CPU time 314.78 seconds
Started Jul 20 05:27:54 PM PDT 24
Finished Jul 20 05:33:10 PM PDT 24
Peak memory 233808 kb
Host smart-afd0b7ef-aab9-42e2-b203-ad665c228f67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514867275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2514867275
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2141731770
Short name T141
Test name
Test status
Simulation time 19907654139 ps
CPU time 66.03 seconds
Started Jul 20 05:27:51 PM PDT 24
Finished Jul 20 05:28:58 PM PDT 24
Peak memory 219444 kb
Host smart-90264139-ef18-4684-a020-414926a3f655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141731770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2141731770
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2428864460
Short name T8
Test name
Test status
Simulation time 862088666 ps
CPU time 10.32 seconds
Started Jul 20 05:27:55 PM PDT 24
Finished Jul 20 05:28:06 PM PDT 24
Peak memory 219308 kb
Host smart-2e6d3a84-0e3a-4a4d-a945-c3afed959d83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2428864460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2428864460
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1118659287
Short name T28
Test name
Test status
Simulation time 5401372540 ps
CPU time 235.62 seconds
Started Jul 20 05:27:57 PM PDT 24
Finished Jul 20 05:31:54 PM PDT 24
Peak memory 238072 kb
Host smart-9fe2763f-1b23-406c-bedb-b361fe2a92d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118659287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1118659287
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2634032510
Short name T333
Test name
Test status
Simulation time 5709783166 ps
CPU time 34.41 seconds
Started Jul 20 05:27:53 PM PDT 24
Finished Jul 20 05:28:29 PM PDT 24
Peak memory 217220 kb
Host smart-9123874d-909a-467f-8a00-57e91169aa8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634032510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2634032510
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1738133077
Short name T6
Test name
Test status
Simulation time 1279978134 ps
CPU time 41.59 seconds
Started Jul 20 05:27:55 PM PDT 24
Finished Jul 20 05:28:38 PM PDT 24
Peak memory 219328 kb
Host smart-f63953e2-f08b-464d-aa14-d383f81060ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738133077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1738133077
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3180132159
Short name T262
Test name
Test status
Simulation time 660397713 ps
CPU time 8.39 seconds
Started Jul 20 05:28:26 PM PDT 24
Finished Jul 20 05:28:34 PM PDT 24
Peak memory 217264 kb
Host smart-0d3ef93c-8d30-4faf-a13a-dcc6aa13fec3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180132159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3180132159
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1061206353
Short name T148
Test name
Test status
Simulation time 82292922311 ps
CPU time 224.59 seconds
Started Jul 20 05:28:24 PM PDT 24
Finished Jul 20 05:32:10 PM PDT 24
Peak memory 237168 kb
Host smart-3db6ed9d-8814-4385-bc0c-107b94ce3899
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061206353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1061206353
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.561043114
Short name T139
Test name
Test status
Simulation time 5727044286 ps
CPU time 55.62 seconds
Started Jul 20 05:28:26 PM PDT 24
Finished Jul 20 05:29:22 PM PDT 24
Peak memory 219448 kb
Host smart-2ae60e47-3b7c-449e-a935-6dc887e10a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561043114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.561043114
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.102486766
Short name T277
Test name
Test status
Simulation time 1977821630 ps
CPU time 21.92 seconds
Started Jul 20 05:28:18 PM PDT 24
Finished Jul 20 05:28:40 PM PDT 24
Peak memory 217832 kb
Host smart-edfeae34-7f53-491c-880c-f2e699ee5f3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=102486766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.102486766
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.1177113785
Short name T250
Test name
Test status
Simulation time 7173895850 ps
CPU time 58.2 seconds
Started Jul 20 05:28:18 PM PDT 24
Finished Jul 20 05:29:17 PM PDT 24
Peak memory 217688 kb
Host smart-14c14b11-a750-489c-bda7-057d89a75871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177113785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.1177113785
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2027155717
Short name T212
Test name
Test status
Simulation time 930872694 ps
CPU time 50.88 seconds
Started Jul 20 05:28:21 PM PDT 24
Finished Jul 20 05:29:14 PM PDT 24
Peak memory 218412 kb
Host smart-46c45cae-dce0-40e9-b236-f028698784d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027155717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2027155717
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3217676649
Short name T121
Test name
Test status
Simulation time 4273585299 ps
CPU time 15.32 seconds
Started Jul 20 05:28:18 PM PDT 24
Finished Jul 20 05:28:34 PM PDT 24
Peak memory 217244 kb
Host smart-c4ef3892-85d7-4e3b-a35a-80ddf13a0ac9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217676649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3217676649
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3310090766
Short name T313
Test name
Test status
Simulation time 16281187569 ps
CPU time 166.46 seconds
Started Jul 20 05:28:21 PM PDT 24
Finished Jul 20 05:31:10 PM PDT 24
Peak memory 239032 kb
Host smart-5c5540ec-b772-4be8-9e20-514da63ce383
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310090766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3310090766
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3283955725
Short name T357
Test name
Test status
Simulation time 335979411 ps
CPU time 19.3 seconds
Started Jul 20 05:28:20 PM PDT 24
Finished Jul 20 05:28:41 PM PDT 24
Peak memory 219292 kb
Host smart-01efbaa5-6392-4076-959a-19d93ccd2b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283955725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3283955725
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.4103030779
Short name T318
Test name
Test status
Simulation time 14469915559 ps
CPU time 31.1 seconds
Started Jul 20 05:28:21 PM PDT 24
Finished Jul 20 05:28:54 PM PDT 24
Peak memory 212080 kb
Host smart-2d6fd288-ab4d-4445-8834-304de3e66a4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4103030779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.4103030779
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2123676540
Short name T116
Test name
Test status
Simulation time 8372449380 ps
CPU time 69.84 seconds
Started Jul 20 05:28:20 PM PDT 24
Finished Jul 20 05:29:32 PM PDT 24
Peak memory 217632 kb
Host smart-fa35edf3-1de8-4c78-8be9-161b8a17d066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123676540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2123676540
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1946228032
Short name T229
Test name
Test status
Simulation time 8564305662 ps
CPU time 103.98 seconds
Started Jul 20 05:28:19 PM PDT 24
Finished Jul 20 05:30:05 PM PDT 24
Peak memory 220032 kb
Host smart-fdc66ea5-38bd-4a79-a934-f3bf1555ad46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946228032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1946228032
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3090020765
Short name T345
Test name
Test status
Simulation time 4312387220 ps
CPU time 34.23 seconds
Started Jul 20 05:28:18 PM PDT 24
Finished Jul 20 05:28:53 PM PDT 24
Peak memory 213360 kb
Host smart-92bca569-c18d-4d67-b02e-105b98bd7b78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090020765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3090020765
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2783973743
Short name T351
Test name
Test status
Simulation time 5953573051 ps
CPU time 55.13 seconds
Started Jul 20 05:28:21 PM PDT 24
Finished Jul 20 05:29:18 PM PDT 24
Peak memory 219248 kb
Host smart-4d3ed355-4f10-4282-9de6-4c200b19ee27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783973743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2783973743
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.117796621
Short name T66
Test name
Test status
Simulation time 6678439582 ps
CPU time 29.07 seconds
Started Jul 20 05:28:26 PM PDT 24
Finished Jul 20 05:28:55 PM PDT 24
Peak memory 219420 kb
Host smart-fe7ad7a5-f28a-4a9e-8ec8-855a14b6e724
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=117796621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.117796621
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.4127285515
Short name T249
Test name
Test status
Simulation time 24694160325 ps
CPU time 42.77 seconds
Started Jul 20 05:28:20 PM PDT 24
Finished Jul 20 05:29:04 PM PDT 24
Peak memory 216664 kb
Host smart-bb13d747-bdc3-4681-8b84-4fe7fcc13609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127285515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.4127285515
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.785925269
Short name T273
Test name
Test status
Simulation time 2610646118 ps
CPU time 28.17 seconds
Started Jul 20 05:28:21 PM PDT 24
Finished Jul 20 05:28:51 PM PDT 24
Peak memory 214880 kb
Host smart-cd01e1b3-261b-400b-888c-018e9a1db59d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785925269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.785925269
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.325646374
Short name T38
Test name
Test status
Simulation time 6334269701 ps
CPU time 17.81 seconds
Started Jul 20 05:28:19 PM PDT 24
Finished Jul 20 05:28:38 PM PDT 24
Peak memory 217444 kb
Host smart-cd8a950d-1910-43f3-9569-5be91753af65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325646374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.325646374
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3339774931
Short name T335
Test name
Test status
Simulation time 10232552394 ps
CPU time 200.82 seconds
Started Jul 20 05:28:19 PM PDT 24
Finished Jul 20 05:31:40 PM PDT 24
Peak memory 236880 kb
Host smart-3b8ed49d-b650-4772-acf8-f050def2cc18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339774931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3339774931
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3155345397
Short name T235
Test name
Test status
Simulation time 4266441251 ps
CPU time 46.25 seconds
Started Jul 20 05:28:24 PM PDT 24
Finished Jul 20 05:29:11 PM PDT 24
Peak memory 218096 kb
Host smart-3d422d45-4d43-40b8-9a5f-480570fd690d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155345397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3155345397
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.36416157
Short name T131
Test name
Test status
Simulation time 12614710457 ps
CPU time 28.57 seconds
Started Jul 20 05:28:23 PM PDT 24
Finished Jul 20 05:28:53 PM PDT 24
Peak memory 219312 kb
Host smart-43a0101b-bf64-49c8-9e9d-173cc55529fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=36416157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.36416157
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1671997174
Short name T337
Test name
Test status
Simulation time 12614992416 ps
CPU time 75.55 seconds
Started Jul 20 05:28:20 PM PDT 24
Finished Jul 20 05:29:37 PM PDT 24
Peak memory 216372 kb
Host smart-bcff2348-1ef2-477d-9920-e0d0d2d11e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671997174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1671997174
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.4008344377
Short name T346
Test name
Test status
Simulation time 728695233 ps
CPU time 23.65 seconds
Started Jul 20 05:28:23 PM PDT 24
Finished Jul 20 05:28:48 PM PDT 24
Peak memory 219320 kb
Host smart-b215bcf3-e928-47a4-b666-1faa2c83ad22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008344377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.4008344377
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.290250931
Short name T62
Test name
Test status
Simulation time 4246942396 ps
CPU time 33.88 seconds
Started Jul 20 05:28:18 PM PDT 24
Finished Jul 20 05:28:53 PM PDT 24
Peak memory 217196 kb
Host smart-68f5c52f-dee9-48d5-8feb-e95ce5f4665b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290250931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.290250931
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.594540058
Short name T329
Test name
Test status
Simulation time 39300741287 ps
CPU time 513.12 seconds
Started Jul 20 05:28:22 PM PDT 24
Finished Jul 20 05:36:56 PM PDT 24
Peak memory 219576 kb
Host smart-26c4ae9f-bdbd-4c73-83e0-c787fb62d1de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594540058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.594540058
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2851398905
Short name T356
Test name
Test status
Simulation time 332401743 ps
CPU time 19.09 seconds
Started Jul 20 05:28:19 PM PDT 24
Finished Jul 20 05:28:39 PM PDT 24
Peak memory 219264 kb
Host smart-de9d8930-51de-43a6-9994-b5df2ae3662b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851398905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2851398905
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.939191359
Short name T241
Test name
Test status
Simulation time 3798170132 ps
CPU time 30.59 seconds
Started Jul 20 05:28:20 PM PDT 24
Finished Jul 20 05:28:52 PM PDT 24
Peak memory 219368 kb
Host smart-a640b25a-dde2-4426-8e3e-e2ab85d7aeab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=939191359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.939191359
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1728079854
Short name T170
Test name
Test status
Simulation time 2417952326 ps
CPU time 19.6 seconds
Started Jul 20 05:28:18 PM PDT 24
Finished Jul 20 05:28:39 PM PDT 24
Peak memory 216104 kb
Host smart-997b97e6-0389-4d11-b5d2-66164a885db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728079854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1728079854
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3334936569
Short name T256
Test name
Test status
Simulation time 31529503938 ps
CPU time 69.85 seconds
Started Jul 20 05:28:24 PM PDT 24
Finished Jul 20 05:29:35 PM PDT 24
Peak memory 217552 kb
Host smart-cae070cd-9d37-47ef-a910-474fd361505c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334936569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3334936569
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.297294109
Short name T274
Test name
Test status
Simulation time 34818648983 ps
CPU time 34.5 seconds
Started Jul 20 05:28:21 PM PDT 24
Finished Jul 20 05:28:57 PM PDT 24
Peak memory 217472 kb
Host smart-2664c1a0-7dd1-45de-ae06-853932a7b742
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297294109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.297294109
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.4045312002
Short name T22
Test name
Test status
Simulation time 118426050483 ps
CPU time 697.55 seconds
Started Jul 20 05:28:22 PM PDT 24
Finished Jul 20 05:40:02 PM PDT 24
Peak memory 224972 kb
Host smart-11127c72-212d-442e-9649-0e61e08c85ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045312002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.4045312002
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.4161716472
Short name T194
Test name
Test status
Simulation time 2526027879 ps
CPU time 34.88 seconds
Started Jul 20 05:28:22 PM PDT 24
Finished Jul 20 05:28:58 PM PDT 24
Peak memory 219332 kb
Host smart-d8217c75-a4ff-4238-81f9-6c1d186c7ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161716472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.4161716472
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1382680700
Short name T135
Test name
Test status
Simulation time 4827553191 ps
CPU time 23.61 seconds
Started Jul 20 05:28:21 PM PDT 24
Finished Jul 20 05:28:46 PM PDT 24
Peak memory 212064 kb
Host smart-eb1d904a-a6b3-49db-892a-75471bb7d0ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1382680700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1382680700
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.964746709
Short name T50
Test name
Test status
Simulation time 355400990 ps
CPU time 20.33 seconds
Started Jul 20 05:28:20 PM PDT 24
Finished Jul 20 05:28:42 PM PDT 24
Peak memory 216836 kb
Host smart-39c47dce-d0fd-47f7-9c4c-f00d32f98c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964746709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.964746709
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.531957780
Short name T201
Test name
Test status
Simulation time 23435743662 ps
CPU time 65.84 seconds
Started Jul 20 05:28:23 PM PDT 24
Finished Jul 20 05:29:30 PM PDT 24
Peak memory 219296 kb
Host smart-7752b979-dfcb-4362-9b02-ac1f78243729
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531957780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.531957780
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1334694642
Short name T339
Test name
Test status
Simulation time 2219445548 ps
CPU time 20.81 seconds
Started Jul 20 05:28:30 PM PDT 24
Finished Jul 20 05:28:52 PM PDT 24
Peak memory 213316 kb
Host smart-b691891d-9b07-4c0f-b122-82d5628c638f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334694642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1334694642
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1694337184
Short name T158
Test name
Test status
Simulation time 32649116094 ps
CPU time 195.98 seconds
Started Jul 20 05:28:23 PM PDT 24
Finished Jul 20 05:31:40 PM PDT 24
Peak memory 219572 kb
Host smart-f60d1f69-5bda-4a69-9323-09849bb8e844
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694337184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1694337184
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1032983689
Short name T325
Test name
Test status
Simulation time 3566783815 ps
CPU time 40.63 seconds
Started Jul 20 05:28:27 PM PDT 24
Finished Jul 20 05:29:08 PM PDT 24
Peak memory 219308 kb
Host smart-63914ce9-9131-4579-bc26-ae9e8be959c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032983689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1032983689
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.383005683
Short name T184
Test name
Test status
Simulation time 728308087 ps
CPU time 10.54 seconds
Started Jul 20 05:28:20 PM PDT 24
Finished Jul 20 05:28:33 PM PDT 24
Peak memory 219340 kb
Host smart-1d36900c-7207-41af-b778-ab85b6c8e8f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=383005683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.383005683
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1277367707
Short name T138
Test name
Test status
Simulation time 17116508093 ps
CPU time 67.44 seconds
Started Jul 20 05:28:21 PM PDT 24
Finished Jul 20 05:29:30 PM PDT 24
Peak memory 216316 kb
Host smart-ea6839bb-0170-405a-bf0c-b64ef5c583b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277367707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1277367707
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1271573009
Short name T236
Test name
Test status
Simulation time 5201009001 ps
CPU time 63.27 seconds
Started Jul 20 05:28:22 PM PDT 24
Finished Jul 20 05:29:27 PM PDT 24
Peak memory 219372 kb
Host smart-c7134cc1-c6f5-4289-988c-93f772bb5979
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271573009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1271573009
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1038503151
Short name T206
Test name
Test status
Simulation time 1637464624 ps
CPU time 18.31 seconds
Started Jul 20 05:28:30 PM PDT 24
Finished Jul 20 05:28:48 PM PDT 24
Peak memory 213240 kb
Host smart-d692f0fd-a4d5-4399-a9e4-884efcb40206
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038503151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1038503151
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2553320802
Short name T32
Test name
Test status
Simulation time 17318258423 ps
CPU time 278.51 seconds
Started Jul 20 05:28:29 PM PDT 24
Finished Jul 20 05:33:08 PM PDT 24
Peak memory 239876 kb
Host smart-dc47a249-4dd9-4f16-8754-af6f74130628
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553320802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2553320802
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1705134663
Short name T27
Test name
Test status
Simulation time 4420001628 ps
CPU time 45.32 seconds
Started Jul 20 05:28:31 PM PDT 24
Finished Jul 20 05:29:17 PM PDT 24
Peak memory 219352 kb
Host smart-fd936e7e-117e-4125-b8a5-3088d10311a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705134663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1705134663
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.70852648
Short name T53
Test name
Test status
Simulation time 3656729314 ps
CPU time 28.98 seconds
Started Jul 20 05:28:29 PM PDT 24
Finished Jul 20 05:28:58 PM PDT 24
Peak memory 211484 kb
Host smart-26019778-196f-4f3c-886f-9aa225645ec0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=70852648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.70852648
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.1148389157
Short name T183
Test name
Test status
Simulation time 7991087859 ps
CPU time 49.08 seconds
Started Jul 20 05:28:27 PM PDT 24
Finished Jul 20 05:29:16 PM PDT 24
Peak memory 217100 kb
Host smart-aedfa38d-06ce-4b20-9781-f5d91af5c2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148389157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.1148389157
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.573249915
Short name T296
Test name
Test status
Simulation time 45172918886 ps
CPU time 92.55 seconds
Started Jul 20 05:28:24 PM PDT 24
Finished Jul 20 05:29:58 PM PDT 24
Peak memory 219368 kb
Host smart-b1cf23fd-7025-473a-9921-788ea7137405
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573249915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.573249915
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.984627903
Short name T302
Test name
Test status
Simulation time 1153495490 ps
CPU time 15.47 seconds
Started Jul 20 05:28:30 PM PDT 24
Finished Jul 20 05:28:46 PM PDT 24
Peak memory 217104 kb
Host smart-6a966096-38d0-44d6-b7f9-370a461b86d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984627903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.984627903
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1178280795
Short name T221
Test name
Test status
Simulation time 14741724448 ps
CPU time 451.49 seconds
Started Jul 20 05:28:28 PM PDT 24
Finished Jul 20 05:36:00 PM PDT 24
Peak memory 235972 kb
Host smart-99f53ee3-7373-4b32-a672-4d0759a669b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178280795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1178280795
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.288276012
Short name T176
Test name
Test status
Simulation time 22014006242 ps
CPU time 51.52 seconds
Started Jul 20 05:28:30 PM PDT 24
Finished Jul 20 05:29:22 PM PDT 24
Peak memory 219380 kb
Host smart-a2b8519f-67fc-4f63-8199-d81a3b2e396c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288276012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.288276012
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2738048696
Short name T338
Test name
Test status
Simulation time 187405136 ps
CPU time 10.51 seconds
Started Jul 20 05:28:32 PM PDT 24
Finished Jul 20 05:28:43 PM PDT 24
Peak memory 219312 kb
Host smart-ece37b01-3252-4dad-b081-421960e8caaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2738048696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2738048696
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2467869968
Short name T129
Test name
Test status
Simulation time 41358781592 ps
CPU time 61.64 seconds
Started Jul 20 05:28:26 PM PDT 24
Finished Jul 20 05:29:29 PM PDT 24
Peak memory 216728 kb
Host smart-174a1386-221b-4880-9310-dcbc6e41b26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467869968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2467869968
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3890303668
Short name T174
Test name
Test status
Simulation time 12385791232 ps
CPU time 38.68 seconds
Started Jul 20 05:28:32 PM PDT 24
Finished Jul 20 05:29:11 PM PDT 24
Peak memory 212392 kb
Host smart-413a3553-1ca7-4947-a56c-8878d2df1153
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890303668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3890303668
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.557083284
Short name T193
Test name
Test status
Simulation time 4131868882 ps
CPU time 32.28 seconds
Started Jul 20 05:28:27 PM PDT 24
Finished Jul 20 05:29:00 PM PDT 24
Peak memory 217196 kb
Host smart-e69287fc-1684-47b1-9ad5-e1f99a36cd82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557083284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.557083284
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1133944092
Short name T161
Test name
Test status
Simulation time 3250616887 ps
CPU time 224.8 seconds
Started Jul 20 05:28:26 PM PDT 24
Finished Jul 20 05:32:12 PM PDT 24
Peak memory 219620 kb
Host smart-0b9c76f4-d68a-47ba-aa2a-72ae295c4096
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133944092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1133944092
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1758539867
Short name T127
Test name
Test status
Simulation time 693585109 ps
CPU time 10.54 seconds
Started Jul 20 05:28:27 PM PDT 24
Finished Jul 20 05:28:38 PM PDT 24
Peak memory 219340 kb
Host smart-9353fb13-ee4c-4ae1-88e5-01c77b60565e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1758539867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1758539867
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2738319426
Short name T288
Test name
Test status
Simulation time 25110709921 ps
CPU time 67.81 seconds
Started Jul 20 05:28:33 PM PDT 24
Finished Jul 20 05:29:42 PM PDT 24
Peak memory 218240 kb
Host smart-7c503c38-6d5a-4bf3-80ab-149c51c48032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738319426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2738319426
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1065048337
Short name T222
Test name
Test status
Simulation time 2528626812 ps
CPU time 41.02 seconds
Started Jul 20 05:28:26 PM PDT 24
Finished Jul 20 05:29:08 PM PDT 24
Peak memory 219384 kb
Host smart-44a8739f-a79a-4968-83d8-76920d9bac96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065048337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1065048337
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3695469315
Short name T168
Test name
Test status
Simulation time 6808397747 ps
CPU time 30.05 seconds
Started Jul 20 05:27:54 PM PDT 24
Finished Jul 20 05:28:26 PM PDT 24
Peak memory 217964 kb
Host smart-baea9632-de19-4bbd-8cf5-adc664c79914
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695469315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3695469315
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2263010248
Short name T219
Test name
Test status
Simulation time 77437888273 ps
CPU time 299.45 seconds
Started Jul 20 05:27:55 PM PDT 24
Finished Jul 20 05:32:56 PM PDT 24
Peak memory 236064 kb
Host smart-b86c69b0-ad02-4f47-ba96-d11dab01dbb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263010248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2263010248
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3926256276
Short name T195
Test name
Test status
Simulation time 496884023 ps
CPU time 22.7 seconds
Started Jul 20 05:27:54 PM PDT 24
Finished Jul 20 05:28:19 PM PDT 24
Peak memory 219324 kb
Host smart-128a7a02-81e0-4825-bb05-bad8011935da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926256276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3926256276
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1020208917
Short name T211
Test name
Test status
Simulation time 3129650664 ps
CPU time 27.29 seconds
Started Jul 20 05:27:57 PM PDT 24
Finished Jul 20 05:28:25 PM PDT 24
Peak memory 219376 kb
Host smart-d121d928-9e09-48a3-8512-33a1eb3523a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1020208917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1020208917
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3677221875
Short name T29
Test name
Test status
Simulation time 904213903 ps
CPU time 115.6 seconds
Started Jul 20 05:27:54 PM PDT 24
Finished Jul 20 05:29:51 PM PDT 24
Peak memory 238204 kb
Host smart-2a2eb359-1770-40bc-8932-c332237b3c35
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677221875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3677221875
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3915911063
Short name T334
Test name
Test status
Simulation time 5007181188 ps
CPU time 51.87 seconds
Started Jul 20 05:27:53 PM PDT 24
Finished Jul 20 05:28:47 PM PDT 24
Peak memory 216364 kb
Host smart-8d0a6bce-bd6a-417a-ac5e-053a978bcb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915911063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3915911063
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.4121873076
Short name T291
Test name
Test status
Simulation time 3967638275 ps
CPU time 59 seconds
Started Jul 20 05:27:52 PM PDT 24
Finished Jul 20 05:28:53 PM PDT 24
Peak memory 219400 kb
Host smart-c17304bd-53b5-40a3-9d87-b6b1459fc1d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121873076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.4121873076
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.745370852
Short name T268
Test name
Test status
Simulation time 15634186345 ps
CPU time 30.32 seconds
Started Jul 20 05:28:29 PM PDT 24
Finished Jul 20 05:29:00 PM PDT 24
Peak memory 213344 kb
Host smart-f7505543-a799-4e3f-83b3-003ac85dce66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745370852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.745370852
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.4116842872
Short name T153
Test name
Test status
Simulation time 107596131951 ps
CPU time 368.49 seconds
Started Jul 20 05:28:30 PM PDT 24
Finished Jul 20 05:34:40 PM PDT 24
Peak memory 219556 kb
Host smart-f7e27014-56b0-4a49-addd-83d01c4042e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116842872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.4116842872
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2570615850
Short name T275
Test name
Test status
Simulation time 32142122996 ps
CPU time 63.7 seconds
Started Jul 20 05:28:31 PM PDT 24
Finished Jul 20 05:29:35 PM PDT 24
Peak memory 219312 kb
Host smart-9fc24b47-b1a0-451b-9db5-3068e61989f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570615850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2570615850
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1870266074
Short name T315
Test name
Test status
Simulation time 6580682617 ps
CPU time 27.92 seconds
Started Jul 20 05:28:28 PM PDT 24
Finished Jul 20 05:28:56 PM PDT 24
Peak memory 217724 kb
Host smart-c41f3bd3-fa11-49bc-8b06-4d08beaf6b56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1870266074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1870266074
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.612391740
Short name T57
Test name
Test status
Simulation time 14414375246 ps
CPU time 60.02 seconds
Started Jul 20 05:28:33 PM PDT 24
Finished Jul 20 05:29:33 PM PDT 24
Peak memory 217256 kb
Host smart-b8ed6d50-f1f4-45ca-942b-66d44db6d136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612391740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.612391740
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2428472269
Short name T348
Test name
Test status
Simulation time 54978973122 ps
CPU time 79.5 seconds
Started Jul 20 05:28:30 PM PDT 24
Finished Jul 20 05:29:50 PM PDT 24
Peak memory 219400 kb
Host smart-81b87509-c6f2-47e0-9c38-f6a9d112c599
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428472269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2428472269
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2735089768
Short name T220
Test name
Test status
Simulation time 5851281269 ps
CPU time 28.5 seconds
Started Jul 20 05:28:34 PM PDT 24
Finished Jul 20 05:29:03 PM PDT 24
Peak memory 217428 kb
Host smart-26395d26-1f71-4756-9816-2c6c503e0a1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735089768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2735089768
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.823080764
Short name T244
Test name
Test status
Simulation time 3443126929 ps
CPU time 284.81 seconds
Started Jul 20 05:28:42 PM PDT 24
Finished Jul 20 05:33:28 PM PDT 24
Peak memory 233720 kb
Host smart-cf11d140-21a2-4122-8bf0-c10f6b9fe0f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823080764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.823080764
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3350114750
Short name T272
Test name
Test status
Simulation time 2047067965 ps
CPU time 27.45 seconds
Started Jul 20 05:28:35 PM PDT 24
Finished Jul 20 05:29:04 PM PDT 24
Peak memory 219312 kb
Host smart-d0f4ffb0-870f-4eed-914b-aa913706d43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350114750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3350114750
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1033202404
Short name T343
Test name
Test status
Simulation time 670683272 ps
CPU time 14.58 seconds
Started Jul 20 05:28:30 PM PDT 24
Finished Jul 20 05:28:45 PM PDT 24
Peak memory 218620 kb
Host smart-b1b5c4ed-a44f-4738-b6e7-3e6e01291d19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1033202404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1033202404
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1570691442
Short name T115
Test name
Test status
Simulation time 31892836206 ps
CPU time 51.11 seconds
Started Jul 20 05:28:27 PM PDT 24
Finished Jul 20 05:29:19 PM PDT 24
Peak memory 216900 kb
Host smart-f93ce6ce-8164-42f8-b742-6789b2f8b051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570691442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1570691442
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1350420342
Short name T172
Test name
Test status
Simulation time 32158089251 ps
CPU time 87.81 seconds
Started Jul 20 05:28:28 PM PDT 24
Finished Jul 20 05:29:57 PM PDT 24
Peak memory 218988 kb
Host smart-76ffe467-6f23-4055-a6e3-70fdc22e68ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350420342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1350420342
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3018688768
Short name T324
Test name
Test status
Simulation time 372238718 ps
CPU time 10.78 seconds
Started Jul 20 05:28:35 PM PDT 24
Finished Jul 20 05:28:47 PM PDT 24
Peak memory 217136 kb
Host smart-2147dbf4-43ff-44e8-abc0-16138bf77de6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018688768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3018688768
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2284984045
Short name T298
Test name
Test status
Simulation time 30631515399 ps
CPU time 344.59 seconds
Started Jul 20 05:28:34 PM PDT 24
Finished Jul 20 05:34:19 PM PDT 24
Peak memory 217176 kb
Host smart-dffec402-8b02-47af-a7c1-37a51ee7d2d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284984045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2284984045
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2089481899
Short name T353
Test name
Test status
Simulation time 27933563328 ps
CPU time 53.73 seconds
Started Jul 20 05:28:37 PM PDT 24
Finished Jul 20 05:29:33 PM PDT 24
Peak memory 219372 kb
Host smart-ebbe1fd5-e5ad-498e-b963-45dbcbc53499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089481899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2089481899
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.122430406
Short name T180
Test name
Test status
Simulation time 17700954438 ps
CPU time 33.73 seconds
Started Jul 20 05:28:34 PM PDT 24
Finished Jul 20 05:29:09 PM PDT 24
Peak memory 217756 kb
Host smart-73c9fb1e-a7a4-4e9e-8bcc-13a59c40811e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=122430406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.122430406
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2956494322
Short name T257
Test name
Test status
Simulation time 42330715961 ps
CPU time 61.46 seconds
Started Jul 20 05:28:36 PM PDT 24
Finished Jul 20 05:29:39 PM PDT 24
Peak memory 216132 kb
Host smart-6169ce44-68c0-436a-89ef-25c023295b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956494322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2956494322
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.546974142
Short name T311
Test name
Test status
Simulation time 5790675417 ps
CPU time 77.38 seconds
Started Jul 20 05:28:34 PM PDT 24
Finished Jul 20 05:29:52 PM PDT 24
Peak memory 219396 kb
Host smart-c1cc2761-8b09-403a-beb0-57822a151ca1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546974142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.546974142
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1636700117
Short name T303
Test name
Test status
Simulation time 3298323476 ps
CPU time 13.61 seconds
Started Jul 20 05:28:43 PM PDT 24
Finished Jul 20 05:28:57 PM PDT 24
Peak memory 213300 kb
Host smart-35f8347d-9d0e-4787-a931-bdd230b7e349
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636700117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1636700117
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3876434270
Short name T279
Test name
Test status
Simulation time 8773930777 ps
CPU time 189.44 seconds
Started Jul 20 05:28:36 PM PDT 24
Finished Jul 20 05:31:46 PM PDT 24
Peak memory 242076 kb
Host smart-477f90e6-3858-4a81-9482-88cb8f6ac981
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876434270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3876434270
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3759491986
Short name T342
Test name
Test status
Simulation time 6849697915 ps
CPU time 59.22 seconds
Started Jul 20 05:28:36 PM PDT 24
Finished Jul 20 05:29:36 PM PDT 24
Peak memory 219116 kb
Host smart-57147da5-f762-4a04-824e-49bf6d5a30a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759491986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3759491986
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.252465768
Short name T255
Test name
Test status
Simulation time 13487546419 ps
CPU time 29.79 seconds
Started Jul 20 05:28:35 PM PDT 24
Finished Jul 20 05:29:06 PM PDT 24
Peak memory 212056 kb
Host smart-6dc931c8-2f86-47ba-ac69-82c253f81b6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=252465768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.252465768
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.517945315
Short name T270
Test name
Test status
Simulation time 33715873104 ps
CPU time 103.59 seconds
Started Jul 20 05:28:34 PM PDT 24
Finished Jul 20 05:30:19 PM PDT 24
Peak memory 217116 kb
Host smart-271afa04-af7d-4a5e-ae78-df36c0fd9810
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517945315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.517945315
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1365311971
Short name T24
Test name
Test status
Simulation time 16869436999 ps
CPU time 32.11 seconds
Started Jul 20 05:28:35 PM PDT 24
Finished Jul 20 05:29:08 PM PDT 24
Peak memory 213332 kb
Host smart-0d8d4ad7-3d22-4a7d-800b-3487886be2fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365311971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1365311971
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2512865781
Short name T160
Test name
Test status
Simulation time 61170808087 ps
CPU time 423.16 seconds
Started Jul 20 05:28:35 PM PDT 24
Finished Jul 20 05:35:39 PM PDT 24
Peak memory 239768 kb
Host smart-76649161-b866-41fa-84ac-06e4ed36e6e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512865781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2512865781
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.4073409453
Short name T162
Test name
Test status
Simulation time 335976325 ps
CPU time 18.86 seconds
Started Jul 20 05:28:43 PM PDT 24
Finished Jul 20 05:29:02 PM PDT 24
Peak memory 219268 kb
Host smart-5b244797-fd88-4dce-b7d5-dffcb09b5df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073409453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.4073409453
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.311613799
Short name T225
Test name
Test status
Simulation time 15748394090 ps
CPU time 31.36 seconds
Started Jul 20 05:28:43 PM PDT 24
Finished Jul 20 05:29:15 PM PDT 24
Peak memory 219364 kb
Host smart-940c97b2-ff04-4f04-b5ba-f0f89804d212
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=311613799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.311613799
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.192512486
Short name T152
Test name
Test status
Simulation time 23127656102 ps
CPU time 54.75 seconds
Started Jul 20 05:28:39 PM PDT 24
Finished Jul 20 05:29:35 PM PDT 24
Peak memory 217188 kb
Host smart-fb5ea0ca-fbb8-4cd2-b11b-9ef77c28ec1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192512486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.192512486
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1807202199
Short name T48
Test name
Test status
Simulation time 20920205755 ps
CPU time 214.88 seconds
Started Jul 20 05:28:38 PM PDT 24
Finished Jul 20 05:32:14 PM PDT 24
Peak memory 220376 kb
Host smart-1d1b4a3a-3cbf-4e59-81d2-03fea884cfed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807202199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1807202199
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2630311675
Short name T134
Test name
Test status
Simulation time 1366307911 ps
CPU time 16.47 seconds
Started Jul 20 05:28:36 PM PDT 24
Finished Jul 20 05:28:54 PM PDT 24
Peak memory 213232 kb
Host smart-544b210c-05da-4b7f-b2b0-3aadc803358e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630311675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2630311675
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.17220403
Short name T278
Test name
Test status
Simulation time 137450054771 ps
CPU time 436.16 seconds
Started Jul 20 05:28:37 PM PDT 24
Finished Jul 20 05:35:55 PM PDT 24
Peak memory 236272 kb
Host smart-42c62056-767d-4b3f-b80c-9de26cec8f07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17220403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_co
rrupt_sig_fatal_chk.17220403
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1253782424
Short name T125
Test name
Test status
Simulation time 21652473451 ps
CPU time 48.57 seconds
Started Jul 20 05:28:35 PM PDT 24
Finished Jul 20 05:29:24 PM PDT 24
Peak memory 219388 kb
Host smart-ba6393aa-5e62-4970-8c5d-6c345ef2c4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253782424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1253782424
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1028295117
Short name T316
Test name
Test status
Simulation time 11287412468 ps
CPU time 26.93 seconds
Started Jul 20 05:28:36 PM PDT 24
Finished Jul 20 05:29:04 PM PDT 24
Peak memory 212076 kb
Host smart-00d48426-9f3e-48fd-8a1b-2e28162b2c37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1028295117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1028295117
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1055862933
Short name T216
Test name
Test status
Simulation time 23872854567 ps
CPU time 55.85 seconds
Started Jul 20 05:28:36 PM PDT 24
Finished Jul 20 05:29:33 PM PDT 24
Peak memory 217316 kb
Host smart-b9510835-0be5-4bdf-ae9d-44e498102ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055862933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1055862933
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.426125897
Short name T260
Test name
Test status
Simulation time 9326667855 ps
CPU time 34.43 seconds
Started Jul 20 05:28:35 PM PDT 24
Finished Jul 20 05:29:10 PM PDT 24
Peak memory 217220 kb
Host smart-cd8e31fb-0b79-4ac8-a782-5ef1d7752a60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426125897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.426125897
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1412543671
Short name T150
Test name
Test status
Simulation time 5142414258 ps
CPU time 23 seconds
Started Jul 20 05:28:38 PM PDT 24
Finished Jul 20 05:29:02 PM PDT 24
Peak memory 213368 kb
Host smart-bd4dbd65-0f1c-4b6b-9cd9-7a1f96fa1f08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412543671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1412543671
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2654556640
Short name T154
Test name
Test status
Simulation time 99141746817 ps
CPU time 522.37 seconds
Started Jul 20 05:28:36 PM PDT 24
Finished Jul 20 05:37:21 PM PDT 24
Peak memory 233024 kb
Host smart-856b89c4-a4a8-4930-9bd3-eb280ba88f18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654556640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2654556640
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.713394349
Short name T119
Test name
Test status
Simulation time 12273824393 ps
CPU time 38.5 seconds
Started Jul 20 05:28:36 PM PDT 24
Finished Jul 20 05:29:16 PM PDT 24
Peak memory 219304 kb
Host smart-92647970-233a-453d-a892-6fd35f09c992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713394349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.713394349
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3958369313
Short name T326
Test name
Test status
Simulation time 2322164937 ps
CPU time 23.67 seconds
Started Jul 20 05:28:35 PM PDT 24
Finished Jul 20 05:28:59 PM PDT 24
Peak memory 219400 kb
Host smart-e079a0e4-8e67-4d5b-986f-a42ac5bc001f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3958369313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3958369313
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.590191589
Short name T234
Test name
Test status
Simulation time 13374960865 ps
CPU time 32.87 seconds
Started Jul 20 05:28:36 PM PDT 24
Finished Jul 20 05:29:11 PM PDT 24
Peak memory 216832 kb
Host smart-e6b3dbab-768d-4c9f-bc3c-19ff27ced7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590191589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.590191589
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3310840263
Short name T267
Test name
Test status
Simulation time 5125039301 ps
CPU time 94.59 seconds
Started Jul 20 05:28:35 PM PDT 24
Finished Jul 20 05:30:10 PM PDT 24
Peak memory 220620 kb
Host smart-f714be90-cf1d-4024-809f-db5a9c15a67d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310840263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3310840263
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.974090002
Short name T179
Test name
Test status
Simulation time 2348638326 ps
CPU time 22 seconds
Started Jul 20 05:28:39 PM PDT 24
Finished Jul 20 05:29:01 PM PDT 24
Peak memory 218296 kb
Host smart-b7874edf-b42a-4850-8979-c8a8ee0b9e8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974090002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.974090002
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2932043158
Short name T320
Test name
Test status
Simulation time 259488166143 ps
CPU time 546.2 seconds
Started Jul 20 05:28:36 PM PDT 24
Finished Jul 20 05:37:44 PM PDT 24
Peak memory 236620 kb
Host smart-9c595ddb-22f8-4173-8e05-fcaa76459df5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932043158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2932043158
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2682530349
Short name T4
Test name
Test status
Simulation time 5290276432 ps
CPU time 50.43 seconds
Started Jul 20 05:28:37 PM PDT 24
Finished Jul 20 05:29:29 PM PDT 24
Peak memory 219212 kb
Host smart-d96c0c04-f339-4323-8a72-411772d37025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682530349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2682530349
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2617400067
Short name T178
Test name
Test status
Simulation time 7209227661 ps
CPU time 20.96 seconds
Started Jul 20 05:28:38 PM PDT 24
Finished Jul 20 05:29:00 PM PDT 24
Peak memory 212068 kb
Host smart-d99a70f7-8fd2-4b9e-a715-1bcc43817cba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2617400067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2617400067
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.548184728
Short name T224
Test name
Test status
Simulation time 9905608315 ps
CPU time 47.62 seconds
Started Jul 20 05:28:38 PM PDT 24
Finished Jul 20 05:29:27 PM PDT 24
Peak memory 216168 kb
Host smart-72567cd8-10e8-4be7-a23e-9541eae8b714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548184728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.548184728
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.335112972
Short name T341
Test name
Test status
Simulation time 23667698678 ps
CPU time 115.25 seconds
Started Jul 20 05:28:35 PM PDT 24
Finished Jul 20 05:30:31 PM PDT 24
Peak memory 227604 kb
Host smart-aa1bcef5-9322-4ead-a2fa-d5286c9f6e47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335112972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.335112972
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1184786087
Short name T140
Test name
Test status
Simulation time 325850444 ps
CPU time 8.42 seconds
Started Jul 20 05:28:43 PM PDT 24
Finished Jul 20 05:28:53 PM PDT 24
Peak memory 213284 kb
Host smart-09a4fdc7-f0f4-4621-9b1c-e73e66a15f23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184786087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1184786087
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2088351869
Short name T196
Test name
Test status
Simulation time 110856693407 ps
CPU time 685.47 seconds
Started Jul 20 05:28:43 PM PDT 24
Finished Jul 20 05:40:10 PM PDT 24
Peak memory 238980 kb
Host smart-51ce5349-06df-4312-ab11-4147bfd262f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088351869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2088351869
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.413995126
Short name T155
Test name
Test status
Simulation time 48859402482 ps
CPU time 34.73 seconds
Started Jul 20 05:28:45 PM PDT 24
Finished Jul 20 05:29:21 PM PDT 24
Peak memory 219308 kb
Host smart-a67cf2fb-2b03-49db-8e9d-f291d56f38fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413995126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.413995126
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1843231332
Short name T248
Test name
Test status
Simulation time 2711181413 ps
CPU time 18.47 seconds
Started Jul 20 05:28:46 PM PDT 24
Finished Jul 20 05:29:05 PM PDT 24
Peak memory 211332 kb
Host smart-130f77eb-34b7-4969-8a61-28f69042b89a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1843231332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1843231332
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2777787769
Short name T189
Test name
Test status
Simulation time 32213883666 ps
CPU time 72.94 seconds
Started Jul 20 05:28:34 PM PDT 24
Finished Jul 20 05:29:48 PM PDT 24
Peak memory 217428 kb
Host smart-1add5d87-9c61-4254-b75d-ae8cad331b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777787769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2777787769
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1230557730
Short name T10
Test name
Test status
Simulation time 37666508854 ps
CPU time 30.34 seconds
Started Jul 20 05:28:46 PM PDT 24
Finished Jul 20 05:29:17 PM PDT 24
Peak memory 219248 kb
Host smart-baf9b7c5-8425-41c2-8336-baf282c26b28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230557730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1230557730
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.1115676036
Short name T44
Test name
Test status
Simulation time 70076745321 ps
CPU time 675.22 seconds
Started Jul 20 05:28:47 PM PDT 24
Finished Jul 20 05:40:03 PM PDT 24
Peak memory 233536 kb
Host smart-4d95f0c7-d903-4a82-bafe-fe1b82e782a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115676036 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.1115676036
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1738924352
Short name T204
Test name
Test status
Simulation time 3032605749 ps
CPU time 26.09 seconds
Started Jul 20 05:28:45 PM PDT 24
Finished Jul 20 05:29:11 PM PDT 24
Peak memory 217192 kb
Host smart-6f51061d-c44f-46fc-a3ac-6206aa90077b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738924352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1738924352
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1603674665
Short name T157
Test name
Test status
Simulation time 10123633968 ps
CPU time 163.71 seconds
Started Jul 20 05:28:44 PM PDT 24
Finished Jul 20 05:31:28 PM PDT 24
Peak memory 240620 kb
Host smart-44770b17-234f-4d04-8c8e-22310718eff4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603674665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1603674665
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3897931717
Short name T169
Test name
Test status
Simulation time 3186288749 ps
CPU time 39.39 seconds
Started Jul 20 05:28:46 PM PDT 24
Finished Jul 20 05:29:26 PM PDT 24
Peak memory 219376 kb
Host smart-b26bf235-d0e9-4705-8723-4427f3398e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897931717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3897931717
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1480885014
Short name T65
Test name
Test status
Simulation time 3684712730 ps
CPU time 30.7 seconds
Started Jul 20 05:28:47 PM PDT 24
Finished Jul 20 05:29:18 PM PDT 24
Peak memory 211340 kb
Host smart-303baa06-df4f-4d20-b66f-b15405ed9801
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1480885014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1480885014
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2744550570
Short name T239
Test name
Test status
Simulation time 362646546 ps
CPU time 19.07 seconds
Started Jul 20 05:28:45 PM PDT 24
Finished Jul 20 05:29:05 PM PDT 24
Peak memory 216416 kb
Host smart-4413aa9b-33d6-4f5d-83be-96c3ba69da47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744550570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2744550570
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2078709033
Short name T307
Test name
Test status
Simulation time 3766603428 ps
CPU time 31.79 seconds
Started Jul 20 05:27:54 PM PDT 24
Finished Jul 20 05:28:27 PM PDT 24
Peak memory 217124 kb
Host smart-3a79220d-30ee-4f79-9af0-f3203541ac2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078709033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2078709033
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1077758803
Short name T188
Test name
Test status
Simulation time 147261019239 ps
CPU time 424.81 seconds
Started Jul 20 05:27:53 PM PDT 24
Finished Jul 20 05:34:59 PM PDT 24
Peak memory 224360 kb
Host smart-ed6a15cb-ce15-4915-9a0a-ee23526bb5b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077758803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1077758803
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1769747916
Short name T308
Test name
Test status
Simulation time 26674091765 ps
CPU time 49.66 seconds
Started Jul 20 05:27:56 PM PDT 24
Finished Jul 20 05:28:47 PM PDT 24
Peak memory 219412 kb
Host smart-142cab2b-5233-4305-9546-97c7e94aebdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769747916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1769747916
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2137471230
Short name T294
Test name
Test status
Simulation time 2823554821 ps
CPU time 26.69 seconds
Started Jul 20 05:27:56 PM PDT 24
Finished Jul 20 05:28:24 PM PDT 24
Peak memory 219372 kb
Host smart-582d3d1f-782e-4b2f-b61a-bb646617606d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2137471230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2137471230
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3953258267
Short name T226
Test name
Test status
Simulation time 1422479284 ps
CPU time 19.91 seconds
Started Jul 20 05:27:56 PM PDT 24
Finished Jul 20 05:28:17 PM PDT 24
Peak memory 216220 kb
Host smart-1ec8187e-d703-4210-8862-59fa4c1225ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953258267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3953258267
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2529707365
Short name T76
Test name
Test status
Simulation time 11322180777 ps
CPU time 113.94 seconds
Started Jul 20 05:27:53 PM PDT 24
Finished Jul 20 05:29:48 PM PDT 24
Peak memory 219416 kb
Host smart-6e7d4bcb-947e-46b2-abc4-09ee0a424c7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529707365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2529707365
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3124226358
Short name T146
Test name
Test status
Simulation time 1003889876 ps
CPU time 11.41 seconds
Started Jul 20 05:28:43 PM PDT 24
Finished Jul 20 05:28:54 PM PDT 24
Peak memory 213240 kb
Host smart-a48e4cac-0c13-4bef-94e6-71b2cf7ba23a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124226358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3124226358
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1654008988
Short name T122
Test name
Test status
Simulation time 204228921834 ps
CPU time 247.37 seconds
Started Jul 20 05:28:44 PM PDT 24
Finished Jul 20 05:32:52 PM PDT 24
Peak memory 235632 kb
Host smart-210b3026-78da-4703-99dd-8e49c2392336
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654008988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1654008988
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3293529812
Short name T118
Test name
Test status
Simulation time 5868703867 ps
CPU time 54.41 seconds
Started Jul 20 05:28:44 PM PDT 24
Finished Jul 20 05:29:39 PM PDT 24
Peak memory 219396 kb
Host smart-88a78da6-0dd4-416f-ae24-63e345f9a27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293529812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3293529812
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2473124126
Short name T136
Test name
Test status
Simulation time 3955343894 ps
CPU time 21.43 seconds
Started Jul 20 05:28:44 PM PDT 24
Finished Jul 20 05:29:06 PM PDT 24
Peak memory 219340 kb
Host smart-6bf43607-d261-49eb-8f46-8d74262e1475
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2473124126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2473124126
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1516393792
Short name T254
Test name
Test status
Simulation time 5741618566 ps
CPU time 51.6 seconds
Started Jul 20 05:28:45 PM PDT 24
Finished Jul 20 05:29:38 PM PDT 24
Peak memory 216792 kb
Host smart-2feb114a-b8e5-4759-a733-77bbfbe5b139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516393792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1516393792
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1322297118
Short name T330
Test name
Test status
Simulation time 3787191525 ps
CPU time 37.15 seconds
Started Jul 20 05:28:43 PM PDT 24
Finished Jul 20 05:29:21 PM PDT 24
Peak memory 211960 kb
Host smart-34f1e375-be64-4ef0-97ec-c02c48e3c880
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322297118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1322297118
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1933213498
Short name T143
Test name
Test status
Simulation time 8582883041 ps
CPU time 279.46 seconds
Started Jul 20 05:28:53 PM PDT 24
Finished Jul 20 05:33:33 PM PDT 24
Peak memory 236208 kb
Host smart-63fa3fb3-8554-4b7a-a3b3-7d6c153e1eab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933213498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1933213498
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3806915468
Short name T263
Test name
Test status
Simulation time 29176204500 ps
CPU time 56.06 seconds
Started Jul 20 05:28:53 PM PDT 24
Finished Jul 20 05:29:50 PM PDT 24
Peak memory 219400 kb
Host smart-a575b5f4-cecd-4a23-aaeb-c1560f4d4b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806915468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3806915468
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1686590540
Short name T205
Test name
Test status
Simulation time 19033419383 ps
CPU time 26.67 seconds
Started Jul 20 05:28:44 PM PDT 24
Finished Jul 20 05:29:11 PM PDT 24
Peak memory 219400 kb
Host smart-ed368141-14c0-4e86-932c-672354a9b594
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1686590540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1686590540
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2118759943
Short name T78
Test name
Test status
Simulation time 55012554033 ps
CPU time 48.16 seconds
Started Jul 20 05:28:45 PM PDT 24
Finished Jul 20 05:29:34 PM PDT 24
Peak memory 216344 kb
Host smart-aac74a58-3065-4176-a85c-372115730bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118759943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2118759943
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2290390935
Short name T344
Test name
Test status
Simulation time 2485060663 ps
CPU time 45.43 seconds
Started Jul 20 05:28:45 PM PDT 24
Finished Jul 20 05:29:31 PM PDT 24
Peak memory 218184 kb
Host smart-9d957cab-c48a-4976-b408-7cc2334fae4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290390935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2290390935
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.355384760
Short name T142
Test name
Test status
Simulation time 3668310831 ps
CPU time 19.21 seconds
Started Jul 20 05:28:54 PM PDT 24
Finished Jul 20 05:29:14 PM PDT 24
Peak memory 217232 kb
Host smart-b7a23e2c-87dd-4899-9fa2-6f69538c8861
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355384760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.355384760
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1545915638
Short name T192
Test name
Test status
Simulation time 19656288759 ps
CPU time 327.9 seconds
Started Jul 20 05:28:54 PM PDT 24
Finished Jul 20 05:34:23 PM PDT 24
Peak memory 219616 kb
Host smart-1485290d-9c85-4c04-8f3e-6f7c67a633d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545915638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1545915638
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.351718183
Short name T246
Test name
Test status
Simulation time 26233241392 ps
CPU time 36.71 seconds
Started Jul 20 05:28:55 PM PDT 24
Finished Jul 20 05:29:33 PM PDT 24
Peak memory 219400 kb
Host smart-41325bab-9fb2-4cc5-8166-0a2ae396cb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351718183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.351718183
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1740066466
Short name T202
Test name
Test status
Simulation time 694801302 ps
CPU time 10.45 seconds
Started Jul 20 05:28:53 PM PDT 24
Finished Jul 20 05:29:04 PM PDT 24
Peak memory 219340 kb
Host smart-538d0b71-bf5b-449b-82ef-a3802224af5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1740066466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1740066466
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.4135377505
Short name T166
Test name
Test status
Simulation time 27617850090 ps
CPU time 59.18 seconds
Started Jul 20 05:28:55 PM PDT 24
Finished Jul 20 05:29:55 PM PDT 24
Peak memory 217116 kb
Host smart-2eaac3f8-803e-43b9-bb37-1c3798d3a45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135377505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.4135377505
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1268464441
Short name T137
Test name
Test status
Simulation time 13138356024 ps
CPU time 105.88 seconds
Started Jul 20 05:28:53 PM PDT 24
Finished Jul 20 05:30:39 PM PDT 24
Peak memory 220220 kb
Host smart-2ea81f89-8054-4915-9cac-cb2aaa6d725d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268464441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1268464441
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3112283088
Short name T228
Test name
Test status
Simulation time 751916914 ps
CPU time 8.42 seconds
Started Jul 20 05:28:53 PM PDT 24
Finished Jul 20 05:29:02 PM PDT 24
Peak memory 217048 kb
Host smart-e333844f-1ee7-4069-a130-e418e22fa35d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112283088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3112283088
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.4020435505
Short name T34
Test name
Test status
Simulation time 206606641651 ps
CPU time 499.87 seconds
Started Jul 20 05:28:52 PM PDT 24
Finished Jul 20 05:37:12 PM PDT 24
Peak memory 240344 kb
Host smart-075c789e-ceca-4bd0-9b21-037e859e341d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020435505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.4020435505
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1728532152
Short name T265
Test name
Test status
Simulation time 1268381104 ps
CPU time 19.32 seconds
Started Jul 20 05:28:53 PM PDT 24
Finished Jul 20 05:29:13 PM PDT 24
Peak memory 219336 kb
Host smart-5c79f1d6-1bbd-4bdb-abcd-75e32e4a20f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728532152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1728532152
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3579715724
Short name T350
Test name
Test status
Simulation time 6177861648 ps
CPU time 20.04 seconds
Started Jul 20 05:28:54 PM PDT 24
Finished Jul 20 05:29:15 PM PDT 24
Peak memory 217688 kb
Host smart-076997fa-34a7-4beb-bef6-b2178691b525
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3579715724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3579715724
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.1310459691
Short name T101
Test name
Test status
Simulation time 20907733386 ps
CPU time 47.85 seconds
Started Jul 20 05:28:52 PM PDT 24
Finished Jul 20 05:29:41 PM PDT 24
Peak memory 217128 kb
Host smart-5f2d8c41-6505-4a3d-834f-c21d81a86247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310459691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1310459691
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.258170947
Short name T243
Test name
Test status
Simulation time 754659653 ps
CPU time 54.8 seconds
Started Jul 20 05:28:55 PM PDT 24
Finished Jul 20 05:29:51 PM PDT 24
Peak memory 219584 kb
Host smart-59e89859-9a3d-4722-ae56-aeb7e87909af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258170947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.258170947
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1418611183
Short name T190
Test name
Test status
Simulation time 9743123085 ps
CPU time 22.96 seconds
Started Jul 20 05:28:51 PM PDT 24
Finished Jul 20 05:29:15 PM PDT 24
Peak memory 217500 kb
Host smart-e0a2aa88-882d-4d35-9523-55cca149484f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418611183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1418611183
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.296360795
Short name T200
Test name
Test status
Simulation time 38225773396 ps
CPU time 353.08 seconds
Started Jul 20 05:28:53 PM PDT 24
Finished Jul 20 05:34:47 PM PDT 24
Peak memory 236260 kb
Host smart-ba987f8c-fa99-496c-bc72-203ea441bd90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296360795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.296360795
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3034802905
Short name T252
Test name
Test status
Simulation time 2824868558 ps
CPU time 35.63 seconds
Started Jul 20 05:28:55 PM PDT 24
Finished Jul 20 05:29:31 PM PDT 24
Peak memory 219372 kb
Host smart-15dd9992-e564-4323-9128-e52b2bc5a9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034802905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3034802905
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.764561610
Short name T207
Test name
Test status
Simulation time 703383520 ps
CPU time 10.48 seconds
Started Jul 20 05:28:52 PM PDT 24
Finished Jul 20 05:29:03 PM PDT 24
Peak memory 219284 kb
Host smart-91fcc3af-84aa-4de3-b8ec-c16c1083b571
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=764561610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.764561610
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3587429517
Short name T306
Test name
Test status
Simulation time 8529732993 ps
CPU time 85.93 seconds
Started Jul 20 05:28:54 PM PDT 24
Finished Jul 20 05:30:21 PM PDT 24
Peak memory 217372 kb
Host smart-12c097b9-d676-4c9e-b9c0-d146b634a002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587429517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3587429517
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2694861918
Short name T285
Test name
Test status
Simulation time 7360053008 ps
CPU time 64.38 seconds
Started Jul 20 05:28:54 PM PDT 24
Finished Jul 20 05:29:59 PM PDT 24
Peak memory 217556 kb
Host smart-f9ba2286-9ae4-46b1-a9e4-a77e1c262c56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694861918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2694861918
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2260509080
Short name T171
Test name
Test status
Simulation time 11975803031 ps
CPU time 26 seconds
Started Jul 20 05:29:00 PM PDT 24
Finished Jul 20 05:29:27 PM PDT 24
Peak memory 217512 kb
Host smart-296d40df-5693-408f-844c-74011f1074ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260509080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2260509080
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.886445965
Short name T358
Test name
Test status
Simulation time 21317237082 ps
CPU time 355.85 seconds
Started Jul 20 05:29:02 PM PDT 24
Finished Jul 20 05:34:59 PM PDT 24
Peak memory 237880 kb
Host smart-6d364d83-49f1-4a0b-8ea7-a67d5e96da62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886445965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.886445965
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2456180225
Short name T286
Test name
Test status
Simulation time 2361191372 ps
CPU time 23.86 seconds
Started Jul 20 05:29:02 PM PDT 24
Finished Jul 20 05:29:27 PM PDT 24
Peak memory 218856 kb
Host smart-769d157c-71db-464f-88fc-526ecba495ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456180225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2456180225
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.297297743
Short name T128
Test name
Test status
Simulation time 177697048 ps
CPU time 10.51 seconds
Started Jul 20 05:29:00 PM PDT 24
Finished Jul 20 05:29:11 PM PDT 24
Peak memory 219292 kb
Host smart-0d2c2b85-b5cc-494c-8d77-818fb2bac0c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=297297743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.297297743
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.47085217
Short name T9
Test name
Test status
Simulation time 5552725011 ps
CPU time 58.02 seconds
Started Jul 20 05:28:54 PM PDT 24
Finished Jul 20 05:29:53 PM PDT 24
Peak memory 216868 kb
Host smart-115e60d1-9f2d-4559-84d0-396c3d27ed0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47085217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.47085217
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3953361599
Short name T347
Test name
Test status
Simulation time 145114295380 ps
CPU time 130.19 seconds
Started Jul 20 05:29:02 PM PDT 24
Finished Jul 20 05:31:13 PM PDT 24
Peak memory 220220 kb
Host smart-fdd5e0f4-3de4-4c94-99d8-4636c0c0ec0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953361599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3953361599
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3118020396
Short name T63
Test name
Test status
Simulation time 4263308256 ps
CPU time 15.7 seconds
Started Jul 20 05:29:03 PM PDT 24
Finished Jul 20 05:29:19 PM PDT 24
Peak memory 217332 kb
Host smart-e404a1b6-907a-40ad-aae5-4952e517283a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118020396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3118020396
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2517874623
Short name T282
Test name
Test status
Simulation time 1319822665 ps
CPU time 19.31 seconds
Started Jul 20 05:29:00 PM PDT 24
Finished Jul 20 05:29:20 PM PDT 24
Peak memory 219340 kb
Host smart-d4ca19e2-a5ff-4c4f-a5c4-4d50e75e7a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517874623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2517874623
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.4288294134
Short name T305
Test name
Test status
Simulation time 18316275016 ps
CPU time 31.34 seconds
Started Jul 20 05:29:00 PM PDT 24
Finished Jul 20 05:29:33 PM PDT 24
Peak memory 217652 kb
Host smart-443ec51e-6b66-481e-86ab-327c9912477d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4288294134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.4288294134
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.2998834611
Short name T237
Test name
Test status
Simulation time 6833321502 ps
CPU time 55.94 seconds
Started Jul 20 05:29:01 PM PDT 24
Finished Jul 20 05:29:58 PM PDT 24
Peak memory 216820 kb
Host smart-8f0af26d-365c-4104-af97-2b8ef407cc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998834611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2998834611
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2242881354
Short name T145
Test name
Test status
Simulation time 3476738927 ps
CPU time 25.47 seconds
Started Jul 20 05:29:01 PM PDT 24
Finished Jul 20 05:29:27 PM PDT 24
Peak memory 219268 kb
Host smart-d3bffec0-ffad-4cf7-a15d-099634dbcf75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242881354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2242881354
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1726970905
Short name T124
Test name
Test status
Simulation time 7540534395 ps
CPU time 28.75 seconds
Started Jul 20 05:29:00 PM PDT 24
Finished Jul 20 05:29:29 PM PDT 24
Peak memory 217604 kb
Host smart-02ef79d3-9f4f-4737-adc9-2bd37e17dab8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726970905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1726970905
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1959477859
Short name T266
Test name
Test status
Simulation time 65482055106 ps
CPU time 641.25 seconds
Started Jul 20 05:29:01 PM PDT 24
Finished Jul 20 05:39:43 PM PDT 24
Peak memory 228668 kb
Host smart-5919b476-57a4-4076-b4ee-d7faf0fed806
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959477859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1959477859
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3027971599
Short name T35
Test name
Test status
Simulation time 1435216612 ps
CPU time 19.21 seconds
Started Jul 20 05:29:00 PM PDT 24
Finished Jul 20 05:29:21 PM PDT 24
Peak memory 219324 kb
Host smart-99f5ab10-4157-476f-b0ab-73357df75310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027971599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3027971599
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.61054599
Short name T147
Test name
Test status
Simulation time 4801205280 ps
CPU time 23.81 seconds
Started Jul 20 05:29:01 PM PDT 24
Finished Jul 20 05:29:26 PM PDT 24
Peak memory 219372 kb
Host smart-80355027-e4b2-4d88-a19a-dd3ece306aee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=61054599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.61054599
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.452622830
Short name T3
Test name
Test status
Simulation time 347097722 ps
CPU time 19.89 seconds
Started Jul 20 05:29:01 PM PDT 24
Finished Jul 20 05:29:22 PM PDT 24
Peak memory 216308 kb
Host smart-8a807acc-dfca-4c7b-83f7-a802f18a3574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452622830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.452622830
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2570794062
Short name T203
Test name
Test status
Simulation time 7552924331 ps
CPU time 81.57 seconds
Started Jul 20 05:29:01 PM PDT 24
Finished Jul 20 05:30:24 PM PDT 24
Peak memory 217736 kb
Host smart-bf620cad-2c62-497f-ba09-d1fdbd498a1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570794062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2570794062
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.474672435
Short name T42
Test name
Test status
Simulation time 55690044865 ps
CPU time 2377.46 seconds
Started Jul 20 05:29:00 PM PDT 24
Finished Jul 20 06:08:38 PM PDT 24
Peak memory 252236 kb
Host smart-cbaeb343-67c8-4917-ad4b-1544c0ccf2e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474672435 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.474672435
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1604486045
Short name T301
Test name
Test status
Simulation time 1735623571 ps
CPU time 10.81 seconds
Started Jul 20 05:29:10 PM PDT 24
Finished Jul 20 05:29:21 PM PDT 24
Peak memory 217112 kb
Host smart-dcbd38ca-2fec-4572-bf38-5cd28e337019
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604486045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1604486045
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1952464467
Short name T230
Test name
Test status
Simulation time 3832272158 ps
CPU time 162.33 seconds
Started Jul 20 05:29:07 PM PDT 24
Finished Jul 20 05:31:50 PM PDT 24
Peak memory 243312 kb
Host smart-44f6322e-9ac2-4c65-b31d-4165bc54c571
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952464467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1952464467
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1253509394
Short name T130
Test name
Test status
Simulation time 2634946371 ps
CPU time 36.19 seconds
Started Jul 20 05:29:09 PM PDT 24
Finished Jul 20 05:29:46 PM PDT 24
Peak memory 219388 kb
Host smart-38f631b0-2a2e-4c86-82f8-6ee3df0d7052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253509394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1253509394
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3155940822
Short name T238
Test name
Test status
Simulation time 24757105995 ps
CPU time 23.08 seconds
Started Jul 20 05:29:00 PM PDT 24
Finished Jul 20 05:29:25 PM PDT 24
Peak memory 219400 kb
Host smart-7f7847dd-6a9f-457c-8571-4b1177c3c1ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3155940822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3155940822
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1942019292
Short name T331
Test name
Test status
Simulation time 5170132359 ps
CPU time 25.41 seconds
Started Jul 20 05:29:00 PM PDT 24
Finished Jul 20 05:29:26 PM PDT 24
Peak memory 216488 kb
Host smart-435b2cb9-9608-43d9-92dc-e2b243feb981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942019292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1942019292
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1153250042
Short name T354
Test name
Test status
Simulation time 76818120500 ps
CPU time 179.19 seconds
Started Jul 20 05:29:00 PM PDT 24
Finished Jul 20 05:32:01 PM PDT 24
Peak memory 219440 kb
Host smart-33344eda-b252-4a5c-b332-f92b0094cec3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153250042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1153250042
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2597316797
Short name T15
Test name
Test status
Simulation time 78395990979 ps
CPU time 1633.68 seconds
Started Jul 20 05:29:09 PM PDT 24
Finished Jul 20 05:56:24 PM PDT 24
Peak memory 244040 kb
Host smart-655046c7-29b6-4a8a-815a-6bb4ab2905cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597316797 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.2597316797
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1936327928
Short name T26
Test name
Test status
Simulation time 14544404401 ps
CPU time 30.47 seconds
Started Jul 20 05:29:08 PM PDT 24
Finished Jul 20 05:29:39 PM PDT 24
Peak memory 217480 kb
Host smart-24861f27-e41a-4a3c-8f87-69d7ae1ed347
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936327928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1936327928
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2267486103
Short name T19
Test name
Test status
Simulation time 17298645744 ps
CPU time 175.94 seconds
Started Jul 20 05:29:11 PM PDT 24
Finished Jul 20 05:32:07 PM PDT 24
Peak memory 228524 kb
Host smart-1fabf680-2941-4be4-8203-2339be73a643
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267486103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2267486103
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1701526606
Short name T40
Test name
Test status
Simulation time 2398654300 ps
CPU time 32.88 seconds
Started Jul 20 05:29:08 PM PDT 24
Finished Jul 20 05:29:42 PM PDT 24
Peak memory 219384 kb
Host smart-56d8ea70-5a8c-47aa-a0c2-564cc7ab4aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701526606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1701526606
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1547809682
Short name T355
Test name
Test status
Simulation time 5175211141 ps
CPU time 47.18 seconds
Started Jul 20 05:29:09 PM PDT 24
Finished Jul 20 05:29:57 PM PDT 24
Peak memory 217452 kb
Host smart-d8eb4783-705b-4dae-bc92-db9130d8d997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547809682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1547809682
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3139833668
Short name T209
Test name
Test status
Simulation time 67632544999 ps
CPU time 105.22 seconds
Started Jul 20 05:29:07 PM PDT 24
Finished Jul 20 05:30:53 PM PDT 24
Peak memory 221012 kb
Host smart-3e56022c-4ead-4b01-a1d3-42b55c8fca19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139833668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3139833668
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1342529521
Short name T214
Test name
Test status
Simulation time 167405525 ps
CPU time 8.38 seconds
Started Jul 20 05:28:02 PM PDT 24
Finished Jul 20 05:28:13 PM PDT 24
Peak memory 217268 kb
Host smart-5b60d27b-e755-429f-9526-070ef7bb9826
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342529521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1342529521
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.808573170
Short name T336
Test name
Test status
Simulation time 11242240337 ps
CPU time 274.01 seconds
Started Jul 20 05:28:02 PM PDT 24
Finished Jul 20 05:32:38 PM PDT 24
Peak memory 239720 kb
Host smart-c7b407db-1869-48b2-ba7b-f494a95a6ea6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808573170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.808573170
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2043233769
Short name T332
Test name
Test status
Simulation time 12000827635 ps
CPU time 53.09 seconds
Started Jul 20 05:28:00 PM PDT 24
Finished Jul 20 05:28:53 PM PDT 24
Peak memory 219352 kb
Host smart-898fac99-2337-4e50-84b5-98049016213f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043233769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2043233769
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.188747861
Short name T173
Test name
Test status
Simulation time 920576590 ps
CPU time 10.58 seconds
Started Jul 20 05:28:00 PM PDT 24
Finished Jul 20 05:28:11 PM PDT 24
Peak memory 219352 kb
Host smart-a04c9c7b-0275-4c56-9d29-ac79f6465439
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=188747861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.188747861
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3185723969
Short name T323
Test name
Test status
Simulation time 25361125533 ps
CPU time 53.58 seconds
Started Jul 20 05:28:01 PM PDT 24
Finished Jul 20 05:28:56 PM PDT 24
Peak memory 217344 kb
Host smart-7093f699-7432-4783-b058-580f0695fc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185723969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3185723969
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2519338698
Short name T251
Test name
Test status
Simulation time 2078209870 ps
CPU time 65.05 seconds
Started Jul 20 05:28:02 PM PDT 24
Finished Jul 20 05:29:09 PM PDT 24
Peak memory 219288 kb
Host smart-efe08862-f0ff-48d6-8fa8-6a4012cc65bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519338698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2519338698
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3038981732
Short name T213
Test name
Test status
Simulation time 16453990965 ps
CPU time 18.47 seconds
Started Jul 20 05:28:00 PM PDT 24
Finished Jul 20 05:28:20 PM PDT 24
Peak memory 213332 kb
Host smart-476c96cd-10c8-4638-ae43-0de68a209a1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038981732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3038981732
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1353196622
Short name T182
Test name
Test status
Simulation time 75392965809 ps
CPU time 748.69 seconds
Started Jul 20 05:28:02 PM PDT 24
Finished Jul 20 05:40:32 PM PDT 24
Peak memory 226284 kb
Host smart-5f66cc1e-b43a-4896-8caf-f8b8d0d8fece
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353196622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1353196622
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3869513745
Short name T151
Test name
Test status
Simulation time 11690992282 ps
CPU time 57.91 seconds
Started Jul 20 05:28:04 PM PDT 24
Finished Jul 20 05:29:03 PM PDT 24
Peak memory 219404 kb
Host smart-2e94b927-59c6-4458-b03f-3349c370337c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869513745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3869513745
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.676812427
Short name T299
Test name
Test status
Simulation time 6333759439 ps
CPU time 27.16 seconds
Started Jul 20 05:28:02 PM PDT 24
Finished Jul 20 05:28:31 PM PDT 24
Peak memory 217876 kb
Host smart-5cc09acb-6a97-4fe1-bf60-bcafc66eb312
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=676812427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.676812427
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3443314248
Short name T232
Test name
Test status
Simulation time 8147023940 ps
CPU time 65.02 seconds
Started Jul 20 05:28:01 PM PDT 24
Finished Jul 20 05:29:07 PM PDT 24
Peak memory 217012 kb
Host smart-48b2550d-1921-4dcb-b10c-5052a48ec796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443314248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3443314248
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1542256845
Short name T77
Test name
Test status
Simulation time 9486407215 ps
CPU time 98.54 seconds
Started Jul 20 05:28:04 PM PDT 24
Finished Jul 20 05:29:44 PM PDT 24
Peak memory 219384 kb
Host smart-204204bd-f3bd-4343-9b9a-eac05e687faf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542256845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1542256845
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2041859498
Short name T271
Test name
Test status
Simulation time 4367912751 ps
CPU time 23.06 seconds
Started Jul 20 05:28:00 PM PDT 24
Finished Jul 20 05:28:24 PM PDT 24
Peak memory 213356 kb
Host smart-f4595445-5756-4ce2-bdf3-ef1df41e3516
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041859498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2041859498
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2504708116
Short name T258
Test name
Test status
Simulation time 58238848481 ps
CPU time 476.98 seconds
Started Jul 20 05:28:04 PM PDT 24
Finished Jul 20 05:36:02 PM PDT 24
Peak memory 238324 kb
Host smart-91bd0596-15d1-491f-980a-2e57a5c8593b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504708116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2504708116
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.4085076442
Short name T7
Test name
Test status
Simulation time 17821989225 ps
CPU time 45.93 seconds
Started Jul 20 05:28:01 PM PDT 24
Finished Jul 20 05:28:48 PM PDT 24
Peak memory 219320 kb
Host smart-7b0e2c3e-3941-4fbd-b8c5-7a10ec521701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085076442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.4085076442
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.4027180598
Short name T276
Test name
Test status
Simulation time 1852374092 ps
CPU time 20.79 seconds
Started Jul 20 05:28:02 PM PDT 24
Finished Jul 20 05:28:24 PM PDT 24
Peak memory 211576 kb
Host smart-9960a208-9b0e-42cd-872f-e05528c33544
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4027180598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.4027180598
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2830042132
Short name T261
Test name
Test status
Simulation time 1444705579 ps
CPU time 19.61 seconds
Started Jul 20 05:28:02 PM PDT 24
Finished Jul 20 05:28:23 PM PDT 24
Peak memory 216824 kb
Host smart-645d98b5-9f61-44a0-a34d-57f0fd79889e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830042132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2830042132
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.511390303
Short name T156
Test name
Test status
Simulation time 1706065422 ps
CPU time 56.5 seconds
Started Jul 20 05:28:02 PM PDT 24
Finished Jul 20 05:29:00 PM PDT 24
Peak memory 219260 kb
Host smart-aa00ce5e-a6a1-4036-9de1-dbc60b81ebba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511390303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.511390303
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.261450613
Short name T25
Test name
Test status
Simulation time 338499992 ps
CPU time 8.55 seconds
Started Jul 20 05:28:04 PM PDT 24
Finished Jul 20 05:28:14 PM PDT 24
Peak memory 216820 kb
Host smart-7df7570b-76bf-4052-97e9-87bf729cad60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261450613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.261450613
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.869527401
Short name T33
Test name
Test status
Simulation time 85448539309 ps
CPU time 340.44 seconds
Started Jul 20 05:28:04 PM PDT 24
Finished Jul 20 05:33:46 PM PDT 24
Peak memory 219060 kb
Host smart-e85541fb-cfa2-4705-9e2d-7630b667706d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869527401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.869527401
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1234205871
Short name T177
Test name
Test status
Simulation time 8526776925 ps
CPU time 45.15 seconds
Started Jul 20 05:28:02 PM PDT 24
Finished Jul 20 05:28:49 PM PDT 24
Peak memory 219328 kb
Host smart-0ed0d38a-4dc0-4cac-9bdc-430116352eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234205871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1234205871
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3046316678
Short name T126
Test name
Test status
Simulation time 5581895767 ps
CPU time 20.15 seconds
Started Jul 20 05:28:04 PM PDT 24
Finished Jul 20 05:28:25 PM PDT 24
Peak memory 219468 kb
Host smart-429363d8-4d72-43d8-b3e3-0e8116c44de8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3046316678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3046316678
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.4259577076
Short name T327
Test name
Test status
Simulation time 690633679 ps
CPU time 20.29 seconds
Started Jul 20 05:28:01 PM PDT 24
Finished Jul 20 05:28:23 PM PDT 24
Peak memory 215964 kb
Host smart-0aa2587a-f7e2-46af-a800-e95f7f0763e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259577076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.4259577076
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3813132368
Short name T18
Test name
Test status
Simulation time 9068844272 ps
CPU time 33.93 seconds
Started Jul 20 05:28:02 PM PDT 24
Finished Jul 20 05:28:38 PM PDT 24
Peak memory 219340 kb
Host smart-db9a7407-bc70-4823-a0d0-7ac90a7500b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813132368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3813132368
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1328140682
Short name T259
Test name
Test status
Simulation time 677618398 ps
CPU time 10.82 seconds
Started Jul 20 05:28:01 PM PDT 24
Finished Jul 20 05:28:14 PM PDT 24
Peak memory 217088 kb
Host smart-148684ea-5d50-40db-91a8-3c8027c2557a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328140682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1328140682
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2652611526
Short name T319
Test name
Test status
Simulation time 1321419178 ps
CPU time 19.16 seconds
Started Jul 20 05:28:02 PM PDT 24
Finished Jul 20 05:28:23 PM PDT 24
Peak memory 219344 kb
Host smart-cc6a56ab-56ff-45dd-913c-2b608cca12c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652611526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2652611526
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1129652358
Short name T102
Test name
Test status
Simulation time 3287000153 ps
CPU time 28.23 seconds
Started Jul 20 05:28:04 PM PDT 24
Finished Jul 20 05:28:34 PM PDT 24
Peak memory 211408 kb
Host smart-d0f49c32-fba8-4518-b1d5-8dec6c88e756
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1129652358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1129652358
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3472947219
Short name T208
Test name
Test status
Simulation time 31355805650 ps
CPU time 63.42 seconds
Started Jul 20 05:28:02 PM PDT 24
Finished Jul 20 05:29:08 PM PDT 24
Peak memory 216204 kb
Host smart-807470a2-b080-4c55-a52e-92d6723c0b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472947219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3472947219
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.108098562
Short name T253
Test name
Test status
Simulation time 1105608352 ps
CPU time 68.71 seconds
Started Jul 20 05:28:03 PM PDT 24
Finished Jul 20 05:29:14 PM PDT 24
Peak memory 228668 kb
Host smart-77e94679-1940-4e69-b3df-8fdca8ee9d26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108098562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.108098562
Directory /workspace/9.rom_ctrl_stress_all/latest
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