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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.24 96.89 91.99 97.68 100.00 98.28 97.45 98.37


Total test records in report: 456
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T292 /workspace/coverage/default/15.rom_ctrl_alert_test.4070049994 Jul 21 04:59:37 PM PDT 24 Jul 21 05:00:01 PM PDT 24 6216183862 ps
T293 /workspace/coverage/default/9.rom_ctrl_stress_all.2706484114 Jul 21 04:59:16 PM PDT 24 Jul 21 04:59:38 PM PDT 24 4121332582 ps
T294 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.678656412 Jul 21 04:59:43 PM PDT 24 Jul 21 05:00:04 PM PDT 24 5033539413 ps
T295 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3767135020 Jul 21 05:01:32 PM PDT 24 Jul 21 05:13:22 PM PDT 24 140451894912 ps
T296 /workspace/coverage/default/25.rom_ctrl_smoke.587997922 Jul 21 05:00:15 PM PDT 24 Jul 21 05:01:00 PM PDT 24 19710358795 ps
T297 /workspace/coverage/default/33.rom_ctrl_stress_all.102206438 Jul 21 05:00:41 PM PDT 24 Jul 21 05:01:02 PM PDT 24 371705649 ps
T298 /workspace/coverage/default/44.rom_ctrl_stress_all.2017393639 Jul 21 05:01:16 PM PDT 24 Jul 21 05:02:01 PM PDT 24 4718968480 ps
T299 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2786879947 Jul 21 05:01:22 PM PDT 24 Jul 21 05:01:51 PM PDT 24 6730177171 ps
T300 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2895108868 Jul 21 04:59:36 PM PDT 24 Jul 21 05:00:42 PM PDT 24 16350217598 ps
T301 /workspace/coverage/default/11.rom_ctrl_smoke.3856313960 Jul 21 04:59:20 PM PDT 24 Jul 21 05:00:04 PM PDT 24 7720638315 ps
T302 /workspace/coverage/default/16.rom_ctrl_stress_all.2875389014 Jul 21 04:59:45 PM PDT 24 Jul 21 05:01:28 PM PDT 24 12598231888 ps
T22 /workspace/coverage/default/3.rom_ctrl_sec_cm.2846443428 Jul 21 04:58:50 PM PDT 24 Jul 21 05:02:30 PM PDT 24 2773190909 ps
T303 /workspace/coverage/default/27.rom_ctrl_smoke.2765569682 Jul 21 05:00:18 PM PDT 24 Jul 21 05:00:49 PM PDT 24 1386709668 ps
T304 /workspace/coverage/default/25.rom_ctrl_stress_all.2261639528 Jul 21 05:00:13 PM PDT 24 Jul 21 05:02:27 PM PDT 24 15967140083 ps
T305 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3410691997 Jul 21 05:00:36 PM PDT 24 Jul 21 05:11:29 PM PDT 24 70434247912 ps
T306 /workspace/coverage/default/23.rom_ctrl_stress_all.1722221004 Jul 21 05:00:07 PM PDT 24 Jul 21 05:00:44 PM PDT 24 3068350483 ps
T307 /workspace/coverage/default/20.rom_ctrl_stress_all.3247565220 Jul 21 04:59:54 PM PDT 24 Jul 21 05:00:53 PM PDT 24 5450809299 ps
T308 /workspace/coverage/default/29.rom_ctrl_stress_all.3931338472 Jul 21 05:00:32 PM PDT 24 Jul 21 05:04:01 PM PDT 24 41143861985 ps
T309 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2980213748 Jul 21 04:59:25 PM PDT 24 Jul 21 05:00:29 PM PDT 24 32730677660 ps
T310 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2898968622 Jul 21 05:01:34 PM PDT 24 Jul 21 05:02:03 PM PDT 24 18819294957 ps
T28 /workspace/coverage/default/4.rom_ctrl_sec_cm.1377890206 Jul 21 04:58:54 PM PDT 24 Jul 21 05:02:39 PM PDT 24 405106149 ps
T311 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3038620221 Jul 21 04:58:41 PM PDT 24 Jul 21 05:03:11 PM PDT 24 24426377440 ps
T312 /workspace/coverage/default/9.rom_ctrl_alert_test.3432400116 Jul 21 04:59:19 PM PDT 24 Jul 21 04:59:36 PM PDT 24 1414687805 ps
T313 /workspace/coverage/default/28.rom_ctrl_smoke.3659020962 Jul 21 05:00:22 PM PDT 24 Jul 21 05:01:30 PM PDT 24 7234479148 ps
T314 /workspace/coverage/default/5.rom_ctrl_alert_test.199532599 Jul 21 04:59:01 PM PDT 24 Jul 21 04:59:25 PM PDT 24 10430556846 ps
T315 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.498606616 Jul 21 04:59:44 PM PDT 24 Jul 21 05:00:53 PM PDT 24 16733842895 ps
T316 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3244691081 Jul 21 05:01:00 PM PDT 24 Jul 21 05:01:11 PM PDT 24 186999363 ps
T317 /workspace/coverage/default/34.rom_ctrl_smoke.2856805303 Jul 21 05:00:45 PM PDT 24 Jul 21 05:01:09 PM PDT 24 2111149241 ps
T318 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.294261356 Jul 21 05:01:19 PM PDT 24 Jul 21 05:08:20 PM PDT 24 338928133149 ps
T319 /workspace/coverage/default/14.rom_ctrl_alert_test.2697932395 Jul 21 04:59:38 PM PDT 24 Jul 21 04:59:51 PM PDT 24 2727610875 ps
T320 /workspace/coverage/default/6.rom_ctrl_alert_test.415900709 Jul 21 04:59:07 PM PDT 24 Jul 21 04:59:29 PM PDT 24 2194958787 ps
T321 /workspace/coverage/default/19.rom_ctrl_stress_all.2370379997 Jul 21 04:59:47 PM PDT 24 Jul 21 05:00:03 PM PDT 24 1071925304 ps
T322 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1723159276 Jul 21 05:01:33 PM PDT 24 Jul 21 05:06:18 PM PDT 24 16929287576 ps
T323 /workspace/coverage/default/49.rom_ctrl_stress_all.3157393709 Jul 21 05:01:38 PM PDT 24 Jul 21 05:03:55 PM PDT 24 12444527628 ps
T324 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3682124899 Jul 21 04:59:46 PM PDT 24 Jul 21 05:03:23 PM PDT 24 20223793553 ps
T325 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1521238936 Jul 21 05:01:30 PM PDT 24 Jul 21 05:01:40 PM PDT 24 728659935 ps
T326 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.35194070 Jul 21 05:01:34 PM PDT 24 Jul 21 05:09:57 PM PDT 24 151682571114 ps
T327 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1163959455 Jul 21 04:59:43 PM PDT 24 Jul 21 05:00:08 PM PDT 24 14929382758 ps
T328 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3151166210 Jul 21 04:59:48 PM PDT 24 Jul 21 05:00:41 PM PDT 24 23701312405 ps
T329 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2441471149 Jul 21 05:01:17 PM PDT 24 Jul 21 05:12:00 PM PDT 24 111886405784 ps
T330 /workspace/coverage/default/28.rom_ctrl_alert_test.1138646632 Jul 21 05:00:30 PM PDT 24 Jul 21 05:00:55 PM PDT 24 7151886354 ps
T331 /workspace/coverage/default/42.rom_ctrl_stress_all.831384688 Jul 21 05:01:08 PM PDT 24 Jul 21 05:03:12 PM PDT 24 41173535693 ps
T332 /workspace/coverage/default/41.rom_ctrl_alert_test.581301515 Jul 21 05:01:06 PM PDT 24 Jul 21 05:01:39 PM PDT 24 7967850399 ps
T333 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1635580393 Jul 21 05:00:59 PM PDT 24 Jul 21 05:01:25 PM PDT 24 5474175915 ps
T334 /workspace/coverage/default/30.rom_ctrl_stress_all.3036371322 Jul 21 05:00:30 PM PDT 24 Jul 21 05:02:25 PM PDT 24 9192364014 ps
T335 /workspace/coverage/default/36.rom_ctrl_alert_test.1706689361 Jul 21 05:00:59 PM PDT 24 Jul 21 05:01:31 PM PDT 24 4458727489 ps
T336 /workspace/coverage/default/45.rom_ctrl_stress_all.3482161472 Jul 21 05:01:17 PM PDT 24 Jul 21 05:02:32 PM PDT 24 27878595671 ps
T337 /workspace/coverage/default/22.rom_ctrl_alert_test.650764505 Jul 21 05:00:05 PM PDT 24 Jul 21 05:00:14 PM PDT 24 550859275 ps
T29 /workspace/coverage/default/1.rom_ctrl_sec_cm.47478369 Jul 21 04:58:44 PM PDT 24 Jul 21 05:02:40 PM PDT 24 5363621315 ps
T338 /workspace/coverage/default/5.rom_ctrl_stress_all.3775098637 Jul 21 04:58:55 PM PDT 24 Jul 21 04:59:55 PM PDT 24 6059058828 ps
T339 /workspace/coverage/default/20.rom_ctrl_smoke.1842256423 Jul 21 04:59:48 PM PDT 24 Jul 21 05:00:35 PM PDT 24 18575644506 ps
T340 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3912197990 Jul 21 05:00:01 PM PDT 24 Jul 21 05:04:00 PM PDT 24 16099912628 ps
T341 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.4062848241 Jul 21 04:59:26 PM PDT 24 Jul 21 04:59:43 PM PDT 24 1184280263 ps
T342 /workspace/coverage/default/37.rom_ctrl_stress_all.1002783806 Jul 21 05:00:48 PM PDT 24 Jul 21 05:02:48 PM PDT 24 13665669065 ps
T343 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1359623544 Jul 21 04:59:19 PM PDT 24 Jul 21 04:59:53 PM PDT 24 7071749225 ps
T344 /workspace/coverage/default/29.rom_ctrl_alert_test.4083810998 Jul 21 05:00:33 PM PDT 24 Jul 21 05:01:07 PM PDT 24 16710769248 ps
T345 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3285539462 Jul 21 05:01:22 PM PDT 24 Jul 21 05:01:50 PM PDT 24 3197338519 ps
T346 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2308513181 Jul 21 05:00:05 PM PDT 24 Jul 21 05:02:50 PM PDT 24 1906460849 ps
T347 /workspace/coverage/default/32.rom_ctrl_alert_test.1937885488 Jul 21 05:00:37 PM PDT 24 Jul 21 05:00:46 PM PDT 24 687881059 ps
T348 /workspace/coverage/default/40.rom_ctrl_smoke.1371381116 Jul 21 05:01:02 PM PDT 24 Jul 21 05:01:22 PM PDT 24 700160615 ps
T349 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3891248942 Jul 21 04:59:43 PM PDT 24 Jul 21 05:05:00 PM PDT 24 60602096360 ps
T350 /workspace/coverage/default/2.rom_ctrl_alert_test.687334047 Jul 21 04:58:51 PM PDT 24 Jul 21 04:59:18 PM PDT 24 11062318035 ps
T65 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2086091640 Jul 21 04:56:51 PM PDT 24 Jul 21 04:57:23 PM PDT 24 16635049499 ps
T66 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.767948260 Jul 21 04:56:46 PM PDT 24 Jul 21 04:57:25 PM PDT 24 1971535702 ps
T67 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3261787670 Jul 21 04:58:30 PM PDT 24 Jul 21 04:58:55 PM PDT 24 11789401146 ps
T103 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2612906136 Jul 21 04:57:56 PM PDT 24 Jul 21 04:58:08 PM PDT 24 923048456 ps
T351 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1031320052 Jul 21 04:56:59 PM PDT 24 Jul 21 04:57:21 PM PDT 24 9756587932 ps
T74 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2291697677 Jul 21 04:58:32 PM PDT 24 Jul 21 04:59:03 PM PDT 24 37027854101 ps
T104 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1019112490 Jul 21 04:57:38 PM PDT 24 Jul 21 04:57:56 PM PDT 24 5582420958 ps
T60 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1494911662 Jul 21 04:58:03 PM PDT 24 Jul 21 05:00:44 PM PDT 24 3821030779 ps
T75 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1121456241 Jul 21 04:58:04 PM PDT 24 Jul 21 04:58:42 PM PDT 24 714176346 ps
T61 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2963080756 Jul 21 04:57:10 PM PDT 24 Jul 21 04:57:26 PM PDT 24 5937787853 ps
T76 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3004296129 Jul 21 04:57:55 PM PDT 24 Jul 21 04:58:53 PM PDT 24 6885673482 ps
T73 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4035122564 Jul 21 04:58:03 PM PDT 24 Jul 21 04:58:34 PM PDT 24 3112957220 ps
T77 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4285743938 Jul 21 04:57:03 PM PDT 24 Jul 21 04:58:17 PM PDT 24 26983662600 ps
T78 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2360109705 Jul 21 04:57:17 PM PDT 24 Jul 21 04:57:29 PM PDT 24 1854436830 ps
T79 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2203674685 Jul 21 04:58:15 PM PDT 24 Jul 21 04:58:33 PM PDT 24 5163551512 ps
T352 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1375620523 Jul 21 04:57:37 PM PDT 24 Jul 21 04:58:10 PM PDT 24 4267288450 ps
T353 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3202664191 Jul 21 04:57:37 PM PDT 24 Jul 21 04:58:11 PM PDT 24 15016476780 ps
T62 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.864061945 Jul 21 04:58:31 PM PDT 24 Jul 21 04:59:56 PM PDT 24 2311126376 ps
T63 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.536947270 Jul 21 04:57:46 PM PDT 24 Jul 21 05:00:26 PM PDT 24 5940302966 ps
T354 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1261887794 Jul 21 04:57:01 PM PDT 24 Jul 21 04:57:39 PM PDT 24 16317783380 ps
T355 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.504921485 Jul 21 04:57:14 PM PDT 24 Jul 21 04:59:23 PM PDT 24 17695172403 ps
T356 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3514696245 Jul 21 04:58:15 PM PDT 24 Jul 21 04:58:46 PM PDT 24 16136120248 ps
T118 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.4045618698 Jul 21 04:58:01 PM PDT 24 Jul 21 04:59:27 PM PDT 24 3550893780 ps
T357 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1037025334 Jul 21 04:58:13 PM PDT 24 Jul 21 04:58:48 PM PDT 24 8145758385 ps
T80 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1030222164 Jul 21 04:57:11 PM PDT 24 Jul 21 04:57:35 PM PDT 24 2777297799 ps
T358 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2224854171 Jul 21 04:57:15 PM PDT 24 Jul 21 04:57:50 PM PDT 24 4353935674 ps
T116 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2999713199 Jul 21 04:57:54 PM PDT 24 Jul 21 04:59:24 PM PDT 24 1254435128 ps
T81 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1545099029 Jul 21 04:57:26 PM PDT 24 Jul 21 04:57:59 PM PDT 24 19580600266 ps
T359 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3930142681 Jul 21 04:58:35 PM PDT 24 Jul 21 05:00:16 PM PDT 24 4360122804 ps
T360 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2348136383 Jul 21 04:58:20 PM PDT 24 Jul 21 04:58:50 PM PDT 24 12109046039 ps
T105 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.560399393 Jul 21 04:58:15 PM PDT 24 Jul 21 05:01:13 PM PDT 24 82524665948 ps
T106 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1496047563 Jul 21 04:57:46 PM PDT 24 Jul 21 04:58:36 PM PDT 24 11910071707 ps
T361 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2970591961 Jul 21 04:57:50 PM PDT 24 Jul 21 04:59:16 PM PDT 24 4175687438 ps
T362 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.167067506 Jul 21 04:58:12 PM PDT 24 Jul 21 04:58:37 PM PDT 24 6009897265 ps
T363 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2626269810 Jul 21 04:57:03 PM PDT 24 Jul 21 04:57:12 PM PDT 24 498525185 ps
T364 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1787385988 Jul 21 04:58:03 PM PDT 24 Jul 21 04:58:18 PM PDT 24 922020204 ps
T365 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3922752806 Jul 21 04:57:20 PM PDT 24 Jul 21 04:57:51 PM PDT 24 15667714642 ps
T366 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1120087548 Jul 21 04:57:03 PM PDT 24 Jul 21 04:57:32 PM PDT 24 5985299570 ps
T112 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1896100802 Jul 21 04:58:21 PM PDT 24 Jul 21 05:00:19 PM PDT 24 13996050418 ps
T88 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.577779602 Jul 21 04:58:21 PM PDT 24 Jul 21 05:00:05 PM PDT 24 7908860579 ps
T107 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.490162193 Jul 21 04:57:01 PM PDT 24 Jul 21 04:57:31 PM PDT 24 14675816978 ps
T108 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2523691804 Jul 21 04:57:50 PM PDT 24 Jul 21 04:57:58 PM PDT 24 688930907 ps
T109 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3775116441 Jul 21 04:57:31 PM PDT 24 Jul 21 04:57:54 PM PDT 24 2859067968 ps
T367 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.140632680 Jul 21 04:57:02 PM PDT 24 Jul 21 04:57:33 PM PDT 24 7703544567 ps
T119 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2120471831 Jul 21 04:58:30 PM PDT 24 Jul 21 05:00:08 PM PDT 24 11212500596 ps
T368 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2717172783 Jul 21 04:57:26 PM PDT 24 Jul 21 04:58:22 PM PDT 24 1078451836 ps
T89 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3124664706 Jul 21 04:57:20 PM PDT 24 Jul 21 04:59:06 PM PDT 24 17147708289 ps
T369 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.615361774 Jul 21 04:58:15 PM PDT 24 Jul 21 04:58:33 PM PDT 24 1547927840 ps
T370 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3329132902 Jul 21 04:58:10 PM PDT 24 Jul 21 04:58:22 PM PDT 24 689623728 ps
T371 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1978875002 Jul 21 04:57:56 PM PDT 24 Jul 21 04:58:06 PM PDT 24 3062113195 ps
T372 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1098948610 Jul 21 04:57:11 PM PDT 24 Jul 21 04:57:48 PM PDT 24 15355231604 ps
T373 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4262257553 Jul 21 04:58:25 PM PDT 24 Jul 21 04:58:50 PM PDT 24 11622761264 ps
T374 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1083949145 Jul 21 04:58:14 PM PDT 24 Jul 21 04:58:23 PM PDT 24 180392825 ps
T375 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3713046119 Jul 21 04:56:59 PM PDT 24 Jul 21 04:57:08 PM PDT 24 176319898 ps
T376 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2968526526 Jul 21 04:57:04 PM PDT 24 Jul 21 04:57:24 PM PDT 24 6807258780 ps
T377 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3485074523 Jul 21 04:58:31 PM PDT 24 Jul 21 04:58:54 PM PDT 24 2562741501 ps
T378 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.780177472 Jul 21 04:58:32 PM PDT 24 Jul 21 04:58:59 PM PDT 24 12707629647 ps
T379 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3486491552 Jul 21 04:56:51 PM PDT 24 Jul 21 04:57:23 PM PDT 24 15379132622 ps
T121 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2785327749 Jul 21 04:56:46 PM PDT 24 Jul 21 04:58:29 PM PDT 24 64740590629 ps
T380 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3234974254 Jul 21 04:58:15 PM PDT 24 Jul 21 04:58:48 PM PDT 24 10726679804 ps
T381 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.4248103165 Jul 21 04:58:12 PM PDT 24 Jul 21 04:58:21 PM PDT 24 167730284 ps
T382 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1370196622 Jul 21 04:57:52 PM PDT 24 Jul 21 04:58:01 PM PDT 24 688249044 ps
T383 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3153532830 Jul 21 04:58:22 PM PDT 24 Jul 21 04:58:58 PM PDT 24 16125643972 ps
T384 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1087423746 Jul 21 04:58:03 PM PDT 24 Jul 21 04:58:34 PM PDT 24 3901935564 ps
T385 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3550255847 Jul 21 04:58:32 PM PDT 24 Jul 21 04:59:06 PM PDT 24 17229206117 ps
T386 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3902470639 Jul 21 04:58:02 PM PDT 24 Jul 21 04:58:34 PM PDT 24 15272219922 ps
T387 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2926602296 Jul 21 04:57:21 PM PDT 24 Jul 21 04:57:55 PM PDT 24 3510787713 ps
T388 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.532779291 Jul 21 04:58:21 PM PDT 24 Jul 21 04:59:53 PM PDT 24 8947049000 ps
T389 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3521470480 Jul 21 04:58:31 PM PDT 24 Jul 21 04:58:58 PM PDT 24 2315219105 ps
T390 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3212726085 Jul 21 04:57:20 PM PDT 24 Jul 21 04:58:55 PM PDT 24 4908819352 ps
T391 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.812682198 Jul 21 04:57:32 PM PDT 24 Jul 21 04:57:51 PM PDT 24 14885018260 ps
T392 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1513048690 Jul 21 04:56:53 PM PDT 24 Jul 21 04:57:22 PM PDT 24 6422692239 ps
T393 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2495956862 Jul 21 04:56:51 PM PDT 24 Jul 21 04:57:14 PM PDT 24 4243160424 ps
T394 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.4257835494 Jul 21 04:58:33 PM PDT 24 Jul 21 05:01:16 PM PDT 24 114996145817 ps
T395 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.4521411 Jul 21 04:57:32 PM PDT 24 Jul 21 04:57:46 PM PDT 24 928454554 ps
T396 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1031286204 Jul 21 04:57:49 PM PDT 24 Jul 21 04:58:15 PM PDT 24 9175469686 ps
T397 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2547337664 Jul 21 04:57:01 PM PDT 24 Jul 21 04:57:09 PM PDT 24 170797216 ps
T398 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1541659816 Jul 21 04:57:27 PM PDT 24 Jul 21 04:57:57 PM PDT 24 3753905780 ps
T399 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1582758867 Jul 21 04:57:36 PM PDT 24 Jul 21 04:58:00 PM PDT 24 5353377273 ps
T400 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.59388200 Jul 21 04:57:15 PM PDT 24 Jul 21 04:57:23 PM PDT 24 1833275805 ps
T401 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1891988579 Jul 21 04:58:12 PM PDT 24 Jul 21 05:00:36 PM PDT 24 14413946119 ps
T402 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2767211040 Jul 21 04:57:15 PM PDT 24 Jul 21 04:57:37 PM PDT 24 28287957995 ps
T403 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2750384463 Jul 21 04:57:28 PM PDT 24 Jul 21 04:57:58 PM PDT 24 11502779078 ps
T404 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.235408255 Jul 21 04:58:02 PM PDT 24 Jul 21 04:58:11 PM PDT 24 613338730 ps
T405 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3057449057 Jul 21 04:57:50 PM PDT 24 Jul 21 04:58:15 PM PDT 24 34308537918 ps
T406 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.193148391 Jul 21 04:57:00 PM PDT 24 Jul 21 04:57:08 PM PDT 24 338560030 ps
T407 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1024312950 Jul 21 04:56:45 PM PDT 24 Jul 21 04:57:18 PM PDT 24 3741586396 ps
T408 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2238777892 Jul 21 04:57:49 PM PDT 24 Jul 21 04:59:55 PM PDT 24 15428886783 ps
T409 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1434529648 Jul 21 04:57:15 PM PDT 24 Jul 21 04:57:23 PM PDT 24 661046358 ps
T410 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3287544716 Jul 21 04:58:25 PM PDT 24 Jul 21 04:58:37 PM PDT 24 414347771 ps
T113 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2002339558 Jul 21 04:57:04 PM PDT 24 Jul 21 04:59:55 PM PDT 24 14564069304 ps
T411 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1465960554 Jul 21 04:57:08 PM PDT 24 Jul 21 04:57:17 PM PDT 24 636243744 ps
T412 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1062398298 Jul 21 04:57:21 PM PDT 24 Jul 21 04:57:45 PM PDT 24 3861687567 ps
T413 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2816881001 Jul 21 04:56:52 PM PDT 24 Jul 21 04:57:08 PM PDT 24 1023589342 ps
T414 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4224668164 Jul 21 04:57:21 PM PDT 24 Jul 21 04:57:35 PM PDT 24 697875999 ps
T415 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1142544606 Jul 21 04:57:54 PM PDT 24 Jul 21 04:59:05 PM PDT 24 30929583810 ps
T416 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3171500657 Jul 21 04:58:03 PM PDT 24 Jul 21 04:58:22 PM PDT 24 1567461675 ps
T417 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3251566286 Jul 21 04:57:46 PM PDT 24 Jul 21 04:58:11 PM PDT 24 13770914557 ps
T418 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.766668289 Jul 21 04:58:15 PM PDT 24 Jul 21 04:59:38 PM PDT 24 310673964 ps
T90 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.416003961 Jul 21 04:57:27 PM PDT 24 Jul 21 04:57:49 PM PDT 24 7853849440 ps
T419 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2768235669 Jul 21 04:57:45 PM PDT 24 Jul 21 04:58:12 PM PDT 24 10135001720 ps
T420 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.537244648 Jul 21 04:58:15 PM PDT 24 Jul 21 04:58:31 PM PDT 24 670024067 ps
T421 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.645224722 Jul 21 04:57:27 PM PDT 24 Jul 21 04:57:58 PM PDT 24 10986334347 ps
T422 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1836474670 Jul 21 04:58:33 PM PDT 24 Jul 21 04:58:56 PM PDT 24 2556918935 ps
T91 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1646291679 Jul 21 04:56:51 PM PDT 24 Jul 21 04:57:18 PM PDT 24 1813941335 ps
T423 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.233354272 Jul 21 04:57:15 PM PDT 24 Jul 21 04:57:26 PM PDT 24 343990864 ps
T424 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.72196985 Jul 21 04:57:48 PM PDT 24 Jul 21 04:57:56 PM PDT 24 203368327 ps
T425 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3344699417 Jul 21 04:58:03 PM PDT 24 Jul 21 04:58:26 PM PDT 24 4416010785 ps
T92 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2923231984 Jul 21 04:57:08 PM PDT 24 Jul 21 04:57:30 PM PDT 24 2953142411 ps
T426 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3399135727 Jul 21 04:57:01 PM PDT 24 Jul 21 04:57:13 PM PDT 24 758921505 ps
T427 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.850314766 Jul 21 04:56:45 PM PDT 24 Jul 21 04:56:54 PM PDT 24 170895312 ps
T428 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3462671522 Jul 21 04:58:12 PM PDT 24 Jul 21 04:58:43 PM PDT 24 14733145779 ps
T429 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3447275874 Jul 21 04:58:31 PM PDT 24 Jul 21 04:58:40 PM PDT 24 176119696 ps
T430 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2941869457 Jul 21 04:58:25 PM PDT 24 Jul 21 04:58:34 PM PDT 24 3406577640 ps
T431 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.349867470 Jul 21 04:57:32 PM PDT 24 Jul 21 05:00:18 PM PDT 24 20068944740 ps
T432 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3555014722 Jul 21 04:57:02 PM PDT 24 Jul 21 04:57:18 PM PDT 24 1252740096 ps
T433 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2343585678 Jul 21 04:57:09 PM PDT 24 Jul 21 04:57:37 PM PDT 24 13181142413 ps
T434 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1322189551 Jul 21 04:58:32 PM PDT 24 Jul 21 04:58:49 PM PDT 24 1155613056 ps
T435 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3830192989 Jul 21 04:57:34 PM PDT 24 Jul 21 04:59:00 PM PDT 24 4220876809 ps
T436 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.931724600 Jul 21 04:58:15 PM PDT 24 Jul 21 04:58:32 PM PDT 24 1182394105 ps
T437 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.313620758 Jul 21 04:58:22 PM PDT 24 Jul 21 04:58:31 PM PDT 24 635463828 ps
T117 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.6679715 Jul 21 04:58:15 PM PDT 24 Jul 21 04:59:44 PM PDT 24 2957000598 ps
T438 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2433052678 Jul 21 04:57:37 PM PDT 24 Jul 21 04:59:22 PM PDT 24 4893868946 ps
T115 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.631560542 Jul 21 04:58:11 PM PDT 24 Jul 21 05:01:03 PM PDT 24 6650291063 ps
T120 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.543180114 Jul 21 04:58:33 PM PDT 24 Jul 21 05:01:25 PM PDT 24 18272783952 ps
T439 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1586792194 Jul 21 04:57:56 PM PDT 24 Jul 21 04:58:10 PM PDT 24 661980929 ps
T440 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.281132926 Jul 21 04:57:54 PM PDT 24 Jul 21 04:58:07 PM PDT 24 331643529 ps
T441 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.567220848 Jul 21 04:57:00 PM PDT 24 Jul 21 04:57:56 PM PDT 24 4160533641 ps
T442 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.756859921 Jul 21 04:57:27 PM PDT 24 Jul 21 04:57:59 PM PDT 24 3617670182 ps
T443 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1225299760 Jul 21 04:57:54 PM PDT 24 Jul 21 04:58:20 PM PDT 24 12553165957 ps
T444 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1375272182 Jul 21 04:58:21 PM PDT 24 Jul 21 04:58:40 PM PDT 24 1523931554 ps
T445 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3270229447 Jul 21 04:58:25 PM PDT 24 Jul 21 04:59:04 PM PDT 24 757858799 ps
T446 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3531268425 Jul 21 04:58:33 PM PDT 24 Jul 21 04:58:44 PM PDT 24 1378209450 ps
T447 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.235629941 Jul 21 04:57:50 PM PDT 24 Jul 21 04:58:09 PM PDT 24 3382033050 ps
T448 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4241111961 Jul 21 04:57:15 PM PDT 24 Jul 21 04:57:39 PM PDT 24 8524721244 ps
T449 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3731955621 Jul 21 04:58:25 PM PDT 24 Jul 21 04:58:42 PM PDT 24 8203499771 ps
T450 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2067083963 Jul 21 04:57:20 PM PDT 24 Jul 21 04:57:50 PM PDT 24 3846811419 ps
T451 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1471566077 Jul 21 04:57:22 PM PDT 24 Jul 21 04:57:35 PM PDT 24 599406245 ps
T114 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3553705687 Jul 21 04:57:01 PM PDT 24 Jul 21 04:59:41 PM PDT 24 29216410678 ps
T452 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3457801539 Jul 21 04:58:33 PM PDT 24 Jul 21 05:01:43 PM PDT 24 24674150483 ps
T453 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1263040518 Jul 21 04:57:17 PM PDT 24 Jul 21 04:58:39 PM PDT 24 1076917625 ps
T454 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1056447542 Jul 21 04:56:45 PM PDT 24 Jul 21 04:57:20 PM PDT 24 16388405593 ps
T455 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3365603653 Jul 21 04:58:32 PM PDT 24 Jul 21 04:59:00 PM PDT 24 15201887072 ps
T456 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3792205280 Jul 21 04:58:26 PM PDT 24 Jul 21 04:58:52 PM PDT 24 2344961758 ps

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2994872932
Short name T1
Test name
Test status
Simulation time 43216984580 ps
CPU time 896.51 seconds
Started Jul 21 05:00:31 PM PDT 24
Finished Jul 21 05:15:28 PM PDT 24
Peak memory 235760 kb
Host smart-a22b4ed3-9806-4839-9aac-76f16b7754b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994872932 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.2994872932
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3396173194
Short name T39
Test name
Test status
Simulation time 42969807454 ps
CPU time 521.29 seconds
Started Jul 21 04:58:54 PM PDT 24
Finished Jul 21 05:07:36 PM PDT 24
Peak memory 226236 kb
Host smart-003fed7b-c51f-465b-8d9e-d151440844e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396173194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3396173194
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1639072352
Short name T10
Test name
Test status
Simulation time 15438573080 ps
CPU time 136.29 seconds
Started Jul 21 04:59:31 PM PDT 24
Finished Jul 21 05:01:48 PM PDT 24
Peak memory 219304 kb
Host smart-9ad6d26c-db5a-401c-905c-07625de185a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639072352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1639072352
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.536947270
Short name T63
Test name
Test status
Simulation time 5940302966 ps
CPU time 159.82 seconds
Started Jul 21 04:57:46 PM PDT 24
Finished Jul 21 05:00:26 PM PDT 24
Peak memory 214100 kb
Host smart-fa5f23e4-9816-4b94-8987-662f9a390fd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536947270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.536947270
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3466492259
Short name T16
Test name
Test status
Simulation time 4973327792 ps
CPU time 185.1 seconds
Started Jul 21 04:59:06 PM PDT 24
Finished Jul 21 05:02:12 PM PDT 24
Peak memory 225108 kb
Host smart-c52f9cdc-70ed-4d9a-b862-61e2f3335c46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466492259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3466492259
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1046739280
Short name T82
Test name
Test status
Simulation time 6938349732 ps
CPU time 43.85 seconds
Started Jul 21 05:00:30 PM PDT 24
Finished Jul 21 05:01:14 PM PDT 24
Peak memory 217124 kb
Host smart-5505b6e7-0a3d-4354-8937-d021a8fd49af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046739280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1046739280
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.710540461
Short name T20
Test name
Test status
Simulation time 1398520667 ps
CPU time 118.49 seconds
Started Jul 21 04:58:38 PM PDT 24
Finished Jul 21 05:00:37 PM PDT 24
Peak memory 237488 kb
Host smart-8ae44f71-a910-4d53-bed8-bbda14d01721
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710540461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.710540461
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4285743938
Short name T77
Test name
Test status
Simulation time 26983662600 ps
CPU time 73.3 seconds
Started Jul 21 04:57:03 PM PDT 24
Finished Jul 21 04:58:17 PM PDT 24
Peak memory 213768 kb
Host smart-a5ae2b0b-4bb8-4748-aea4-660a108f6e3f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285743938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.4285743938
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2002339558
Short name T113
Test name
Test status
Simulation time 14564069304 ps
CPU time 170.95 seconds
Started Jul 21 04:57:04 PM PDT 24
Finished Jul 21 04:59:55 PM PDT 24
Peak memory 213956 kb
Host smart-aaae1c93-35e8-42a6-8c72-e510195d2779
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002339558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2002339558
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.725362602
Short name T24
Test name
Test status
Simulation time 1724501876 ps
CPU time 18.59 seconds
Started Jul 21 05:00:38 PM PDT 24
Finished Jul 21 05:00:57 PM PDT 24
Peak memory 217152 kb
Host smart-a9b06c68-8c59-470b-b983-07b773999c53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725362602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.725362602
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1457754502
Short name T54
Test name
Test status
Simulation time 13894403330 ps
CPU time 58.29 seconds
Started Jul 21 04:58:42 PM PDT 24
Finished Jul 21 04:59:41 PM PDT 24
Peak memory 219240 kb
Host smart-160b8789-953a-4014-a24f-3ac8d02ddd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457754502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1457754502
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2125090742
Short name T142
Test name
Test status
Simulation time 28627773595 ps
CPU time 34.33 seconds
Started Jul 21 04:59:33 PM PDT 24
Finished Jul 21 05:00:08 PM PDT 24
Peak memory 219280 kb
Host smart-38061efd-1924-4859-946f-c747f04a79dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125090742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2125090742
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1494911662
Short name T60
Test name
Test status
Simulation time 3821030779 ps
CPU time 160.44 seconds
Started Jul 21 04:58:03 PM PDT 24
Finished Jul 21 05:00:44 PM PDT 24
Peak memory 213836 kb
Host smart-6b513b06-2da6-41d4-b545-0784c0a12a3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494911662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1494911662
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.1018142935
Short name T13
Test name
Test status
Simulation time 62860558326 ps
CPU time 609.16 seconds
Started Jul 21 05:01:01 PM PDT 24
Finished Jul 21 05:11:11 PM PDT 24
Peak memory 235680 kb
Host smart-00ff2706-1d5f-4295-bfcc-d02af4a441b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018142935 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.1018142935
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3978636741
Short name T42
Test name
Test status
Simulation time 59638669206 ps
CPU time 638.38 seconds
Started Jul 21 04:59:44 PM PDT 24
Finished Jul 21 05:10:23 PM PDT 24
Peak memory 237760 kb
Host smart-287caa63-943d-4428-882b-9439016c1cf7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978636741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3978636741
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1550665465
Short name T93
Test name
Test status
Simulation time 18693377472 ps
CPU time 44.85 seconds
Started Jul 21 05:01:00 PM PDT 24
Finished Jul 21 05:01:45 PM PDT 24
Peak memory 217020 kb
Host smart-69a5f026-6170-47c7-ae62-e40480c47c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550665465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1550665465
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2006538117
Short name T55
Test name
Test status
Simulation time 17722451961 ps
CPU time 190.03 seconds
Started Jul 21 04:59:37 PM PDT 24
Finished Jul 21 05:02:47 PM PDT 24
Peak memory 228524 kb
Host smart-9c834c6a-9fb7-4721-93f6-7ef0959aaa18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006538117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2006538117
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2086091640
Short name T65
Test name
Test status
Simulation time 16635049499 ps
CPU time 31.21 seconds
Started Jul 21 04:56:51 PM PDT 24
Finished Jul 21 04:57:23 PM PDT 24
Peak memory 211604 kb
Host smart-24de5737-0312-4c98-9dc1-988f11051240
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086091640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2086091640
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3486491552
Short name T379
Test name
Test status
Simulation time 15379132622 ps
CPU time 31.7 seconds
Started Jul 21 04:56:51 PM PDT 24
Finished Jul 21 04:57:23 PM PDT 24
Peak memory 211500 kb
Host smart-d4e51dd2-4912-435b-8935-3da07cc28de6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486491552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3486491552
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1646291679
Short name T91
Test name
Test status
Simulation time 1813941335 ps
CPU time 26.9 seconds
Started Jul 21 04:56:51 PM PDT 24
Finished Jul 21 04:57:18 PM PDT 24
Peak memory 211492 kb
Host smart-b773c935-dfad-4278-b93c-77110f0f9bb9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646291679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1646291679
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2816881001
Short name T413
Test name
Test status
Simulation time 1023589342 ps
CPU time 15.66 seconds
Started Jul 21 04:56:52 PM PDT 24
Finished Jul 21 04:57:08 PM PDT 24
Peak memory 216708 kb
Host smart-e0692867-9500-4f89-9e6e-c8103418741b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816881001 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2816881001
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2495956862
Short name T393
Test name
Test status
Simulation time 4243160424 ps
CPU time 22.07 seconds
Started Jul 21 04:56:51 PM PDT 24
Finished Jul 21 04:57:14 PM PDT 24
Peak memory 211772 kb
Host smart-45d2f108-75c3-4bf8-98f4-15fd1b1e1341
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495956862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2495956862
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1056447542
Short name T454
Test name
Test status
Simulation time 16388405593 ps
CPU time 35.36 seconds
Started Jul 21 04:56:45 PM PDT 24
Finished Jul 21 04:57:20 PM PDT 24
Peak memory 210416 kb
Host smart-b73cefe5-8b35-4c34-9536-ed512b50f30e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056447542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1056447542
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.850314766
Short name T427
Test name
Test status
Simulation time 170895312 ps
CPU time 8.27 seconds
Started Jul 21 04:56:45 PM PDT 24
Finished Jul 21 04:56:54 PM PDT 24
Peak memory 210332 kb
Host smart-0c012203-7dce-4113-ae3b-3a5340ad554f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850314766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
850314766
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.767948260
Short name T66
Test name
Test status
Simulation time 1971535702 ps
CPU time 37.79 seconds
Started Jul 21 04:56:46 PM PDT 24
Finished Jul 21 04:57:25 PM PDT 24
Peak memory 213576 kb
Host smart-3a6413d1-f7b8-42cb-81e5-fbff8fcb7b0f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767948260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.767948260
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1513048690
Short name T392
Test name
Test status
Simulation time 6422692239 ps
CPU time 29.54 seconds
Started Jul 21 04:56:53 PM PDT 24
Finished Jul 21 04:57:22 PM PDT 24
Peak memory 212060 kb
Host smart-c9ce6167-9b8f-43d5-85d9-b8b798700430
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513048690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1513048690
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1024312950
Short name T407
Test name
Test status
Simulation time 3741586396 ps
CPU time 33.32 seconds
Started Jul 21 04:56:45 PM PDT 24
Finished Jul 21 04:57:18 PM PDT 24
Peak memory 218196 kb
Host smart-eab5d803-575e-4eb4-b7f6-84b4205fdad7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024312950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1024312950
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2785327749
Short name T121
Test name
Test status
Simulation time 64740590629 ps
CPU time 103.27 seconds
Started Jul 21 04:56:46 PM PDT 24
Finished Jul 21 04:58:29 PM PDT 24
Peak memory 213500 kb
Host smart-18f93f18-83b1-40ec-aecf-f71c71ab0bf2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785327749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2785327749
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.193148391
Short name T406
Test name
Test status
Simulation time 338560030 ps
CPU time 8.1 seconds
Started Jul 21 04:57:00 PM PDT 24
Finished Jul 21 04:57:08 PM PDT 24
Peak memory 210496 kb
Host smart-6a95a923-2b37-4f3d-8621-dd189a44f27d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193148391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.193148391
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3713046119
Short name T375
Test name
Test status
Simulation time 176319898 ps
CPU time 8.7 seconds
Started Jul 21 04:56:59 PM PDT 24
Finished Jul 21 04:57:08 PM PDT 24
Peak memory 210416 kb
Host smart-e8f4fc60-84cc-4827-ad0b-507084355545
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713046119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3713046119
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3399135727
Short name T426
Test name
Test status
Simulation time 758921505 ps
CPU time 11.77 seconds
Started Jul 21 04:57:01 PM PDT 24
Finished Jul 21 04:57:13 PM PDT 24
Peak memory 211428 kb
Host smart-8cd4ac39-2551-422c-b7fb-51f1ff89a751
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399135727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3399135727
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.140632680
Short name T367
Test name
Test status
Simulation time 7703544567 ps
CPU time 30.57 seconds
Started Jul 21 04:57:02 PM PDT 24
Finished Jul 21 04:57:33 PM PDT 24
Peak memory 215796 kb
Host smart-6d7ac601-c34c-447b-bd70-9f2963877c0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140632680 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.140632680
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3555014722
Short name T432
Test name
Test status
Simulation time 1252740096 ps
CPU time 16.3 seconds
Started Jul 21 04:57:02 PM PDT 24
Finished Jul 21 04:57:18 PM PDT 24
Peak memory 211436 kb
Host smart-8009aa43-bfae-4497-a2e7-c8d2fe27f4be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555014722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3555014722
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1031320052
Short name T351
Test name
Test status
Simulation time 9756587932 ps
CPU time 22.05 seconds
Started Jul 21 04:56:59 PM PDT 24
Finished Jul 21 04:57:21 PM PDT 24
Peak memory 210760 kb
Host smart-0c80be59-3954-4d5f-9f47-1d1e6a06af37
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031320052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1031320052
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2547337664
Short name T397
Test name
Test status
Simulation time 170797216 ps
CPU time 7.96 seconds
Started Jul 21 04:57:01 PM PDT 24
Finished Jul 21 04:57:09 PM PDT 24
Peak memory 210364 kb
Host smart-bdf85584-7dcb-45dd-997d-c1b0203295c3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547337664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2547337664
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.567220848
Short name T441
Test name
Test status
Simulation time 4160533641 ps
CPU time 56.3 seconds
Started Jul 21 04:57:00 PM PDT 24
Finished Jul 21 04:57:56 PM PDT 24
Peak memory 214032 kb
Host smart-5c3bf392-6e69-47c4-bc02-8fd91b49f6bd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567220848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.567220848
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.490162193
Short name T107
Test name
Test status
Simulation time 14675816978 ps
CPU time 29.27 seconds
Started Jul 21 04:57:01 PM PDT 24
Finished Jul 21 04:57:31 PM PDT 24
Peak memory 212060 kb
Host smart-b557ee1f-e3b3-4752-9370-78ed9bedf4f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490162193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.490162193
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1261887794
Short name T354
Test name
Test status
Simulation time 16317783380 ps
CPU time 37.67 seconds
Started Jul 21 04:57:01 PM PDT 24
Finished Jul 21 04:57:39 PM PDT 24
Peak memory 218136 kb
Host smart-1e5153ae-1650-4b9c-87d8-7e34ab2b9dc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261887794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1261887794
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3553705687
Short name T114
Test name
Test status
Simulation time 29216410678 ps
CPU time 159.77 seconds
Started Jul 21 04:57:01 PM PDT 24
Finished Jul 21 04:59:41 PM PDT 24
Peak memory 214232 kb
Host smart-4c2006f6-5b32-4794-89d3-b9168edaf34b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553705687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3553705687
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1787385988
Short name T364
Test name
Test status
Simulation time 922020204 ps
CPU time 14.61 seconds
Started Jul 21 04:58:03 PM PDT 24
Finished Jul 21 04:58:18 PM PDT 24
Peak memory 218692 kb
Host smart-0f900d10-a2fc-4dc7-823c-19315058613f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787385988 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1787385988
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3902470639
Short name T386
Test name
Test status
Simulation time 15272219922 ps
CPU time 31.96 seconds
Started Jul 21 04:58:02 PM PDT 24
Finished Jul 21 04:58:34 PM PDT 24
Peak memory 211856 kb
Host smart-84c15743-c5a8-4fdd-8361-4d3d9b87d922
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902470639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3902470639
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1142544606
Short name T415
Test name
Test status
Simulation time 30929583810 ps
CPU time 70.31 seconds
Started Jul 21 04:57:54 PM PDT 24
Finished Jul 21 04:59:05 PM PDT 24
Peak memory 213732 kb
Host smart-8d9a80b8-bde1-4e3b-bdbe-9cf32df07107
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142544606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1142544606
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3344699417
Short name T425
Test name
Test status
Simulation time 4416010785 ps
CPU time 22.91 seconds
Started Jul 21 04:58:03 PM PDT 24
Finished Jul 21 04:58:26 PM PDT 24
Peak memory 212464 kb
Host smart-a372e203-353f-4fe5-a2e7-db4d59c587f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344699417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3344699417
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.281132926
Short name T440
Test name
Test status
Simulation time 331643529 ps
CPU time 12.66 seconds
Started Jul 21 04:57:54 PM PDT 24
Finished Jul 21 04:58:07 PM PDT 24
Peak memory 217288 kb
Host smart-49c8d96b-4dd6-4ebf-ad98-07c43e18e763
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281132926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.281132926
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1087423746
Short name T384
Test name
Test status
Simulation time 3901935564 ps
CPU time 31.17 seconds
Started Jul 21 04:58:03 PM PDT 24
Finished Jul 21 04:58:34 PM PDT 24
Peak memory 218312 kb
Host smart-d951c82e-76e7-44f2-af08-447bf3671af5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087423746 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1087423746
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3171500657
Short name T416
Test name
Test status
Simulation time 1567461675 ps
CPU time 18.13 seconds
Started Jul 21 04:58:03 PM PDT 24
Finished Jul 21 04:58:22 PM PDT 24
Peak memory 210412 kb
Host smart-a6d463ac-c7b8-4f28-9bf8-5c7ffdc56e90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171500657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3171500657
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.235408255
Short name T404
Test name
Test status
Simulation time 613338730 ps
CPU time 8.22 seconds
Started Jul 21 04:58:02 PM PDT 24
Finished Jul 21 04:58:11 PM PDT 24
Peak memory 211056 kb
Host smart-f9decb7d-8d7d-4d2b-af15-3f8c05aff8a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235408255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.235408255
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4035122564
Short name T73
Test name
Test status
Simulation time 3112957220 ps
CPU time 30.26 seconds
Started Jul 21 04:58:03 PM PDT 24
Finished Jul 21 04:58:34 PM PDT 24
Peak memory 216548 kb
Host smart-fdb12754-9804-4d50-a7b0-f25c6bb76c27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035122564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.4035122564
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.4045618698
Short name T118
Test name
Test status
Simulation time 3550893780 ps
CPU time 85.74 seconds
Started Jul 21 04:58:01 PM PDT 24
Finished Jul 21 04:59:27 PM PDT 24
Peak memory 212464 kb
Host smart-34645400-9fed-43f2-bb6d-bf18c41dfab8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045618698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.4045618698
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.167067506
Short name T362
Test name
Test status
Simulation time 6009897265 ps
CPU time 24.72 seconds
Started Jul 21 04:58:12 PM PDT 24
Finished Jul 21 04:58:37 PM PDT 24
Peak memory 216240 kb
Host smart-7e2aab46-343d-4726-a093-da31941c2009
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167067506 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.167067506
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3462671522
Short name T428
Test name
Test status
Simulation time 14733145779 ps
CPU time 30.74 seconds
Started Jul 21 04:58:12 PM PDT 24
Finished Jul 21 04:58:43 PM PDT 24
Peak memory 211712 kb
Host smart-3d63d49a-d98d-4693-b3f3-2ee5998fec97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462671522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3462671522
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1121456241
Short name T75
Test name
Test status
Simulation time 714176346 ps
CPU time 37.96 seconds
Started Jul 21 04:58:04 PM PDT 24
Finished Jul 21 04:58:42 PM PDT 24
Peak memory 212752 kb
Host smart-ac9f61d5-2c06-4c9d-b468-5ea40f5ac68b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121456241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1121456241
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.4248103165
Short name T381
Test name
Test status
Simulation time 167730284 ps
CPU time 8.37 seconds
Started Jul 21 04:58:12 PM PDT 24
Finished Jul 21 04:58:21 PM PDT 24
Peak memory 211120 kb
Host smart-baf3b459-dd81-4053-afbf-19a7950402bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248103165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.4248103165
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3329132902
Short name T370
Test name
Test status
Simulation time 689623728 ps
CPU time 11.53 seconds
Started Jul 21 04:58:10 PM PDT 24
Finished Jul 21 04:58:22 PM PDT 24
Peak memory 216856 kb
Host smart-f30d1724-b0a0-4944-a55a-836732ddf9fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329132902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3329132902
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.631560542
Short name T115
Test name
Test status
Simulation time 6650291063 ps
CPU time 171.24 seconds
Started Jul 21 04:58:11 PM PDT 24
Finished Jul 21 05:01:03 PM PDT 24
Peak memory 214084 kb
Host smart-a79fc218-4fbe-49ca-b2b2-3415c96ff8a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631560542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.631560542
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.615361774
Short name T369
Test name
Test status
Simulation time 1547927840 ps
CPU time 17.57 seconds
Started Jul 21 04:58:15 PM PDT 24
Finished Jul 21 04:58:33 PM PDT 24
Peak memory 214528 kb
Host smart-ac48ba8c-7641-42aa-a359-2cac30667965
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615361774 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.615361774
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3514696245
Short name T356
Test name
Test status
Simulation time 16136120248 ps
CPU time 30.19 seconds
Started Jul 21 04:58:15 PM PDT 24
Finished Jul 21 04:58:46 PM PDT 24
Peak memory 212156 kb
Host smart-cda9dd86-f46a-41d8-a30c-96eda7f81765
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514696245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3514696245
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1891988579
Short name T401
Test name
Test status
Simulation time 14413946119 ps
CPU time 144.25 seconds
Started Jul 21 04:58:12 PM PDT 24
Finished Jul 21 05:00:36 PM PDT 24
Peak memory 215136 kb
Host smart-05e005f1-958c-4750-8513-1deec14422c5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891988579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1891988579
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2203674685
Short name T79
Test name
Test status
Simulation time 5163551512 ps
CPU time 17.3 seconds
Started Jul 21 04:58:15 PM PDT 24
Finished Jul 21 04:58:33 PM PDT 24
Peak memory 212464 kb
Host smart-30772b4c-30b4-4a18-b476-448324a39888
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203674685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2203674685
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1037025334
Short name T357
Test name
Test status
Simulation time 8145758385 ps
CPU time 34.25 seconds
Started Jul 21 04:58:13 PM PDT 24
Finished Jul 21 04:58:48 PM PDT 24
Peak memory 217256 kb
Host smart-547df805-64ec-4681-99c5-8f9ded580532
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037025334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1037025334
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.766668289
Short name T418
Test name
Test status
Simulation time 310673964 ps
CPU time 82.42 seconds
Started Jul 21 04:58:15 PM PDT 24
Finished Jul 21 04:59:38 PM PDT 24
Peak memory 213408 kb
Host smart-f3a5b33c-ce30-4852-8f3f-79ffa9ab79cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766668289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.766668289
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1083949145
Short name T374
Test name
Test status
Simulation time 180392825 ps
CPU time 8.69 seconds
Started Jul 21 04:58:14 PM PDT 24
Finished Jul 21 04:58:23 PM PDT 24
Peak memory 214512 kb
Host smart-dc5f5d71-b54c-45a4-a9a9-fe6c20a58572
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083949145 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1083949145
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.931724600
Short name T436
Test name
Test status
Simulation time 1182394105 ps
CPU time 16.17 seconds
Started Jul 21 04:58:15 PM PDT 24
Finished Jul 21 04:58:32 PM PDT 24
Peak memory 210732 kb
Host smart-039e4b92-9732-40c4-9f21-ef21e931ae42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931724600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.931724600
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.560399393
Short name T105
Test name
Test status
Simulation time 82524665948 ps
CPU time 177.68 seconds
Started Jul 21 04:58:15 PM PDT 24
Finished Jul 21 05:01:13 PM PDT 24
Peak memory 214940 kb
Host smart-da2ea0e8-f579-44af-b0bd-09c4fd4c07ec
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560399393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa
ssthru_mem_tl_intg_err.560399393
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3234974254
Short name T380
Test name
Test status
Simulation time 10726679804 ps
CPU time 32.65 seconds
Started Jul 21 04:58:15 PM PDT 24
Finished Jul 21 04:58:48 PM PDT 24
Peak memory 212468 kb
Host smart-00a6c653-b89c-462b-a6b4-1a0ce702df3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234974254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3234974254
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.537244648
Short name T420
Test name
Test status
Simulation time 670024067 ps
CPU time 15.75 seconds
Started Jul 21 04:58:15 PM PDT 24
Finished Jul 21 04:58:31 PM PDT 24
Peak memory 218180 kb
Host smart-2d5b469e-9119-472d-a271-92514767b649
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537244648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.537244648
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.6679715
Short name T117
Test name
Test status
Simulation time 2957000598 ps
CPU time 88.56 seconds
Started Jul 21 04:58:15 PM PDT 24
Finished Jul 21 04:59:44 PM PDT 24
Peak memory 213128 kb
Host smart-f67ccd2a-1c47-427e-8b64-471b4a72bd1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6679715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_intg
_err.6679715
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1375272182
Short name T444
Test name
Test status
Simulation time 1523931554 ps
CPU time 18.29 seconds
Started Jul 21 04:58:21 PM PDT 24
Finished Jul 21 04:58:40 PM PDT 24
Peak memory 217060 kb
Host smart-39e0570a-a532-4136-8590-f327c40f46ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375272182 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1375272182
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.313620758
Short name T437
Test name
Test status
Simulation time 635463828 ps
CPU time 8.22 seconds
Started Jul 21 04:58:22 PM PDT 24
Finished Jul 21 04:58:31 PM PDT 24
Peak memory 210460 kb
Host smart-9385d98b-57e6-495b-9a60-2881ccd90517
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313620758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.313620758
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1896100802
Short name T112
Test name
Test status
Simulation time 13996050418 ps
CPU time 117.25 seconds
Started Jul 21 04:58:21 PM PDT 24
Finished Jul 21 05:00:19 PM PDT 24
Peak memory 213696 kb
Host smart-bc3ce18c-82a8-4187-ae36-afd5d23a6595
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896100802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1896100802
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3153532830
Short name T383
Test name
Test status
Simulation time 16125643972 ps
CPU time 35.28 seconds
Started Jul 21 04:58:22 PM PDT 24
Finished Jul 21 04:58:58 PM PDT 24
Peak memory 212644 kb
Host smart-bd600c5c-29fe-4e94-b3ee-3f1138691166
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153532830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3153532830
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2348136383
Short name T360
Test name
Test status
Simulation time 12109046039 ps
CPU time 29.13 seconds
Started Jul 21 04:58:20 PM PDT 24
Finished Jul 21 04:58:50 PM PDT 24
Peak memory 217100 kb
Host smart-d6d519f4-43a3-43c7-a140-c048d384ed8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348136383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2348136383
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.532779291
Short name T388
Test name
Test status
Simulation time 8947049000 ps
CPU time 92.24 seconds
Started Jul 21 04:58:21 PM PDT 24
Finished Jul 21 04:59:53 PM PDT 24
Peak memory 213876 kb
Host smart-beeaffb5-c5ac-45d2-a650-fff6c548c287
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532779291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.532779291
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2941869457
Short name T430
Test name
Test status
Simulation time 3406577640 ps
CPU time 8.72 seconds
Started Jul 21 04:58:25 PM PDT 24
Finished Jul 21 04:58:34 PM PDT 24
Peak memory 214700 kb
Host smart-74326efc-d657-4890-a6ac-d34e6e63ff1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941869457 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2941869457
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3261787670
Short name T67
Test name
Test status
Simulation time 11789401146 ps
CPU time 24.94 seconds
Started Jul 21 04:58:30 PM PDT 24
Finished Jul 21 04:58:55 PM PDT 24
Peak memory 211896 kb
Host smart-270ff58d-9a80-4fd1-ae8f-b05431a78fcc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261787670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3261787670
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.577779602
Short name T88
Test name
Test status
Simulation time 7908860579 ps
CPU time 104.6 seconds
Started Jul 21 04:58:21 PM PDT 24
Finished Jul 21 05:00:05 PM PDT 24
Peak memory 215400 kb
Host smart-420a018c-bdb9-4bca-a79d-add77e714708
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577779602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.577779602
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3731955621
Short name T449
Test name
Test status
Simulation time 8203499771 ps
CPU time 16.67 seconds
Started Jul 21 04:58:25 PM PDT 24
Finished Jul 21 04:58:42 PM PDT 24
Peak memory 212500 kb
Host smart-357f4160-a476-429f-b3ad-7008821276a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731955621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3731955621
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3792205280
Short name T456
Test name
Test status
Simulation time 2344961758 ps
CPU time 25.73 seconds
Started Jul 21 04:58:26 PM PDT 24
Finished Jul 21 04:58:52 PM PDT 24
Peak memory 218756 kb
Host smart-63734505-8ac7-4975-96da-c4dd1d9f7682
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792205280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3792205280
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2120471831
Short name T119
Test name
Test status
Simulation time 11212500596 ps
CPU time 97 seconds
Started Jul 21 04:58:30 PM PDT 24
Finished Jul 21 05:00:08 PM PDT 24
Peak memory 213444 kb
Host smart-da33d5fa-5cb2-4c3f-8b75-73b9f155e3fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120471831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2120471831
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1322189551
Short name T434
Test name
Test status
Simulation time 1155613056 ps
CPU time 15.91 seconds
Started Jul 21 04:58:32 PM PDT 24
Finished Jul 21 04:58:49 PM PDT 24
Peak memory 215916 kb
Host smart-987f8b81-1169-401b-a34d-33040a06d8f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322189551 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1322189551
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4262257553
Short name T373
Test name
Test status
Simulation time 11622761264 ps
CPU time 24.72 seconds
Started Jul 21 04:58:25 PM PDT 24
Finished Jul 21 04:58:50 PM PDT 24
Peak memory 211840 kb
Host smart-ec190a1c-c504-47d9-b341-79004a41427c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262257553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.4262257553
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3270229447
Short name T445
Test name
Test status
Simulation time 757858799 ps
CPU time 38.33 seconds
Started Jul 21 04:58:25 PM PDT 24
Finished Jul 21 04:59:04 PM PDT 24
Peak memory 213636 kb
Host smart-f45d33fd-a01d-44da-8998-d7e98217ddee
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270229447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3270229447
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3287544716
Short name T410
Test name
Test status
Simulation time 414347771 ps
CPU time 11.52 seconds
Started Jul 21 04:58:25 PM PDT 24
Finished Jul 21 04:58:37 PM PDT 24
Peak memory 211120 kb
Host smart-c7405d8b-aa19-4469-a68a-d19519346426
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287544716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3287544716
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3521470480
Short name T389
Test name
Test status
Simulation time 2315219105 ps
CPU time 27.17 seconds
Started Jul 21 04:58:31 PM PDT 24
Finished Jul 21 04:58:58 PM PDT 24
Peak memory 218384 kb
Host smart-01917165-087b-4633-88fe-738df6d79437
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521470480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3521470480
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.864061945
Short name T62
Test name
Test status
Simulation time 2311126376 ps
CPU time 84.21 seconds
Started Jul 21 04:58:31 PM PDT 24
Finished Jul 21 04:59:56 PM PDT 24
Peak memory 213104 kb
Host smart-796070c1-89ce-487f-b19e-f7418de44f18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864061945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.864061945
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3365603653
Short name T455
Test name
Test status
Simulation time 15201887072 ps
CPU time 27.76 seconds
Started Jul 21 04:58:32 PM PDT 24
Finished Jul 21 04:59:00 PM PDT 24
Peak memory 217640 kb
Host smart-daf4d9bc-c440-49ca-8380-08f9cdd99721
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365603653 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3365603653
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3531268425
Short name T446
Test name
Test status
Simulation time 1378209450 ps
CPU time 10.66 seconds
Started Jul 21 04:58:33 PM PDT 24
Finished Jul 21 04:58:44 PM PDT 24
Peak memory 210744 kb
Host smart-19446b15-7b06-4e95-979f-8a12bb3c920e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531268425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3531268425
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.4257835494
Short name T394
Test name
Test status
Simulation time 114996145817 ps
CPU time 162.48 seconds
Started Jul 21 04:58:33 PM PDT 24
Finished Jul 21 05:01:16 PM PDT 24
Peak memory 215132 kb
Host smart-b30d5fb9-9b64-43f4-84c6-6f8dc03e6ce2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257835494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.4257835494
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3447275874
Short name T429
Test name
Test status
Simulation time 176119696 ps
CPU time 8.27 seconds
Started Jul 21 04:58:31 PM PDT 24
Finished Jul 21 04:58:40 PM PDT 24
Peak memory 210704 kb
Host smart-cd98c16c-e8ac-431b-8043-533034d67026
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447275874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3447275874
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.780177472
Short name T378
Test name
Test status
Simulation time 12707629647 ps
CPU time 26.3 seconds
Started Jul 21 04:58:32 PM PDT 24
Finished Jul 21 04:58:59 PM PDT 24
Peak memory 218836 kb
Host smart-0f7074c8-f2f2-4825-88d5-b8c05a11ff57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780177472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.780177472
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3930142681
Short name T359
Test name
Test status
Simulation time 4360122804 ps
CPU time 100.83 seconds
Started Jul 21 04:58:35 PM PDT 24
Finished Jul 21 05:00:16 PM PDT 24
Peak memory 213556 kb
Host smart-45b65898-3b9a-42dc-8c2f-f28f226d2efb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930142681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3930142681
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3485074523
Short name T377
Test name
Test status
Simulation time 2562741501 ps
CPU time 23.38 seconds
Started Jul 21 04:58:31 PM PDT 24
Finished Jul 21 04:58:54 PM PDT 24
Peak memory 215516 kb
Host smart-a87b93c1-83b0-46ac-bbbe-f552db73592d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485074523 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3485074523
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1836474670
Short name T422
Test name
Test status
Simulation time 2556918935 ps
CPU time 22.74 seconds
Started Jul 21 04:58:33 PM PDT 24
Finished Jul 21 04:58:56 PM PDT 24
Peak memory 211208 kb
Host smart-14b6083e-2b01-43c8-9ea1-9467c7ca11b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836474670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1836474670
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3457801539
Short name T452
Test name
Test status
Simulation time 24674150483 ps
CPU time 189.55 seconds
Started Jul 21 04:58:33 PM PDT 24
Finished Jul 21 05:01:43 PM PDT 24
Peak memory 215056 kb
Host smart-6d5d7a36-3808-41f7-be7f-e7e33ac2c25e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457801539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3457801539
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2291697677
Short name T74
Test name
Test status
Simulation time 37027854101 ps
CPU time 31.23 seconds
Started Jul 21 04:58:32 PM PDT 24
Finished Jul 21 04:59:03 PM PDT 24
Peak memory 212360 kb
Host smart-65dd200f-7ce7-487c-8517-9d5b93dfcf8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291697677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2291697677
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3550255847
Short name T385
Test name
Test status
Simulation time 17229206117 ps
CPU time 33.57 seconds
Started Jul 21 04:58:32 PM PDT 24
Finished Jul 21 04:59:06 PM PDT 24
Peak memory 217348 kb
Host smart-0b5d3a36-7d9e-47a0-90e3-67ef66fadfe9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550255847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3550255847
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.543180114
Short name T120
Test name
Test status
Simulation time 18272783952 ps
CPU time 171.68 seconds
Started Jul 21 04:58:33 PM PDT 24
Finished Jul 21 05:01:25 PM PDT 24
Peak memory 218760 kb
Host smart-08e172b7-4b9a-4671-bff7-dcde8339d51c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543180114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.543180114
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2923231984
Short name T92
Test name
Test status
Simulation time 2953142411 ps
CPU time 21.59 seconds
Started Jul 21 04:57:08 PM PDT 24
Finished Jul 21 04:57:30 PM PDT 24
Peak memory 211444 kb
Host smart-2065d158-ef40-461e-a627-5596379d34c3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923231984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2923231984
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1465960554
Short name T411
Test name
Test status
Simulation time 636243744 ps
CPU time 8.11 seconds
Started Jul 21 04:57:08 PM PDT 24
Finished Jul 21 04:57:17 PM PDT 24
Peak memory 210488 kb
Host smart-69638814-5194-4fde-9b6c-0bb0fb1ad2c6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465960554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1465960554
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1098948610
Short name T372
Test name
Test status
Simulation time 15355231604 ps
CPU time 37.3 seconds
Started Jul 21 04:57:11 PM PDT 24
Finished Jul 21 04:57:48 PM PDT 24
Peak memory 211940 kb
Host smart-be26a2be-f884-4d54-aa54-09d046af9e2d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098948610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1098948610
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2963080756
Short name T61
Test name
Test status
Simulation time 5937787853 ps
CPU time 15.51 seconds
Started Jul 21 04:57:10 PM PDT 24
Finished Jul 21 04:57:26 PM PDT 24
Peak memory 217440 kb
Host smart-823d7e3d-746d-4794-8cc8-73b65d14a923
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963080756 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2963080756
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1030222164
Short name T80
Test name
Test status
Simulation time 2777297799 ps
CPU time 24.36 seconds
Started Jul 21 04:57:11 PM PDT 24
Finished Jul 21 04:57:35 PM PDT 24
Peak memory 211424 kb
Host smart-aae674b2-8bb4-4c64-9b22-8b834d5aa9ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030222164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1030222164
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2968526526
Short name T376
Test name
Test status
Simulation time 6807258780 ps
CPU time 19.39 seconds
Started Jul 21 04:57:04 PM PDT 24
Finished Jul 21 04:57:24 PM PDT 24
Peak memory 210736 kb
Host smart-623491d1-78f2-4e8b-bc47-a8be3957bfd9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968526526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2968526526
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2626269810
Short name T363
Test name
Test status
Simulation time 498525185 ps
CPU time 9.49 seconds
Started Jul 21 04:57:03 PM PDT 24
Finished Jul 21 04:57:12 PM PDT 24
Peak memory 210264 kb
Host smart-30ddebd2-847f-4c1b-a006-5f75a78343dc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626269810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2626269810
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2343585678
Short name T433
Test name
Test status
Simulation time 13181142413 ps
CPU time 28.35 seconds
Started Jul 21 04:57:09 PM PDT 24
Finished Jul 21 04:57:37 PM PDT 24
Peak memory 212380 kb
Host smart-4a291126-2e9d-4f51-a168-705a41d3bdbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343585678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2343585678
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1120087548
Short name T366
Test name
Test status
Simulation time 5985299570 ps
CPU time 28.52 seconds
Started Jul 21 04:57:03 PM PDT 24
Finished Jul 21 04:57:32 PM PDT 24
Peak memory 217296 kb
Host smart-417d8b4a-2fc9-4860-b8ba-5ccad217fd4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120087548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1120087548
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2767211040
Short name T402
Test name
Test status
Simulation time 28287957995 ps
CPU time 21.63 seconds
Started Jul 21 04:57:15 PM PDT 24
Finished Jul 21 04:57:37 PM PDT 24
Peak memory 211620 kb
Host smart-2874b12c-9e5b-43d3-932c-b166655c18d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767211040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2767211040
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.233354272
Short name T423
Test name
Test status
Simulation time 343990864 ps
CPU time 10.59 seconds
Started Jul 21 04:57:15 PM PDT 24
Finished Jul 21 04:57:26 PM PDT 24
Peak memory 210444 kb
Host smart-b2cdd8a7-f483-471a-a4ef-1ef3904fdf97
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233354272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.233354272
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2360109705
Short name T78
Test name
Test status
Simulation time 1854436830 ps
CPU time 11.78 seconds
Started Jul 21 04:57:17 PM PDT 24
Finished Jul 21 04:57:29 PM PDT 24
Peak memory 211484 kb
Host smart-26033855-91d5-4057-86f0-5703daa012b4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360109705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2360109705
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4224668164
Short name T414
Test name
Test status
Simulation time 697875999 ps
CPU time 13.03 seconds
Started Jul 21 04:57:21 PM PDT 24
Finished Jul 21 04:57:35 PM PDT 24
Peak memory 214916 kb
Host smart-c1ba2b65-f5a2-4f71-9cdf-0f677e274d12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224668164 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.4224668164
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.59388200
Short name T400
Test name
Test status
Simulation time 1833275805 ps
CPU time 8.29 seconds
Started Jul 21 04:57:15 PM PDT 24
Finished Jul 21 04:57:23 PM PDT 24
Peak memory 210788 kb
Host smart-10e94bc4-d308-4cae-ab36-3460dffbfba4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59388200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.59388200
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1434529648
Short name T409
Test name
Test status
Simulation time 661046358 ps
CPU time 8.03 seconds
Started Jul 21 04:57:15 PM PDT 24
Finished Jul 21 04:57:23 PM PDT 24
Peak memory 210336 kb
Host smart-548f2b76-5111-4fe0-b750-cc1c6f4919d7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434529648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1434529648
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2224854171
Short name T358
Test name
Test status
Simulation time 4353935674 ps
CPU time 34.48 seconds
Started Jul 21 04:57:15 PM PDT 24
Finished Jul 21 04:57:50 PM PDT 24
Peak memory 210448 kb
Host smart-ca684d05-a29e-4874-acbe-243176753610
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224854171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2224854171
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.504921485
Short name T355
Test name
Test status
Simulation time 17695172403 ps
CPU time 129 seconds
Started Jul 21 04:57:14 PM PDT 24
Finished Jul 21 04:59:23 PM PDT 24
Peak memory 213756 kb
Host smart-4d0b47d2-bc93-4131-a145-c9d9b98f1fc6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504921485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.504921485
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1471566077
Short name T451
Test name
Test status
Simulation time 599406245 ps
CPU time 11.99 seconds
Started Jul 21 04:57:22 PM PDT 24
Finished Jul 21 04:57:35 PM PDT 24
Peak memory 210852 kb
Host smart-1c90b163-e1d1-42d2-88e7-dc80037b4eb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471566077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1471566077
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4241111961
Short name T448
Test name
Test status
Simulation time 8524721244 ps
CPU time 23.35 seconds
Started Jul 21 04:57:15 PM PDT 24
Finished Jul 21 04:57:39 PM PDT 24
Peak memory 218600 kb
Host smart-8df5dcb8-2235-4658-9120-c9b4837f8121
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241111961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.4241111961
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1263040518
Short name T453
Test name
Test status
Simulation time 1076917625 ps
CPU time 81.43 seconds
Started Jul 21 04:57:17 PM PDT 24
Finished Jul 21 04:58:39 PM PDT 24
Peak memory 213556 kb
Host smart-e7a7ba54-afb0-4a55-a53a-d76211ba2018
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263040518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1263040518
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.416003961
Short name T90
Test name
Test status
Simulation time 7853849440 ps
CPU time 21.09 seconds
Started Jul 21 04:57:27 PM PDT 24
Finished Jul 21 04:57:49 PM PDT 24
Peak memory 212072 kb
Host smart-3fb784a6-aa69-41bc-87ba-5b76941d78f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416003961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.416003961
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.645224722
Short name T421
Test name
Test status
Simulation time 10986334347 ps
CPU time 30.52 seconds
Started Jul 21 04:57:27 PM PDT 24
Finished Jul 21 04:57:58 PM PDT 24
Peak memory 211672 kb
Host smart-24bf4073-243c-41ff-97e0-ee8a92b2403e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645224722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.645224722
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2926602296
Short name T387
Test name
Test status
Simulation time 3510787713 ps
CPU time 33.01 seconds
Started Jul 21 04:57:21 PM PDT 24
Finished Jul 21 04:57:55 PM PDT 24
Peak memory 211168 kb
Host smart-645c49dd-4398-470b-9588-f1d9c29d6883
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926602296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2926602296
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1541659816
Short name T398
Test name
Test status
Simulation time 3753905780 ps
CPU time 29.45 seconds
Started Jul 21 04:57:27 PM PDT 24
Finished Jul 21 04:57:57 PM PDT 24
Peak memory 216500 kb
Host smart-56e2dc7a-08bd-4110-9045-3ade2d1070dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541659816 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1541659816
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1545099029
Short name T81
Test name
Test status
Simulation time 19580600266 ps
CPU time 32.69 seconds
Started Jul 21 04:57:26 PM PDT 24
Finished Jul 21 04:57:59 PM PDT 24
Peak memory 212024 kb
Host smart-221896da-120b-4b79-84b7-2b50d5a3a799
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545099029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1545099029
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2067083963
Short name T450
Test name
Test status
Simulation time 3846811419 ps
CPU time 29.13 seconds
Started Jul 21 04:57:20 PM PDT 24
Finished Jul 21 04:57:50 PM PDT 24
Peak memory 210400 kb
Host smart-dc5e934a-ba9c-4b99-a336-c22f7d26591f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067083963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2067083963
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3922752806
Short name T365
Test name
Test status
Simulation time 15667714642 ps
CPU time 30.63 seconds
Started Jul 21 04:57:20 PM PDT 24
Finished Jul 21 04:57:51 PM PDT 24
Peak memory 210432 kb
Host smart-439e8461-221f-446e-92a9-b1ab77bfe82a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922752806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3922752806
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3124664706
Short name T89
Test name
Test status
Simulation time 17147708289 ps
CPU time 105.39 seconds
Started Jul 21 04:57:20 PM PDT 24
Finished Jul 21 04:59:06 PM PDT 24
Peak memory 215160 kb
Host smart-a68c4d6c-030d-4bef-b2e9-b923d8760b58
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124664706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3124664706
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.756859921
Short name T442
Test name
Test status
Simulation time 3617670182 ps
CPU time 32.44 seconds
Started Jul 21 04:57:27 PM PDT 24
Finished Jul 21 04:57:59 PM PDT 24
Peak memory 212176 kb
Host smart-bc437a8e-6eee-44a6-a5f6-22b6d0e4252b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756859921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.756859921
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1062398298
Short name T412
Test name
Test status
Simulation time 3861687567 ps
CPU time 23.69 seconds
Started Jul 21 04:57:21 PM PDT 24
Finished Jul 21 04:57:45 PM PDT 24
Peak memory 218128 kb
Host smart-edaaac1f-06fe-40d9-a1c5-2c793bd63442
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062398298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1062398298
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3212726085
Short name T390
Test name
Test status
Simulation time 4908819352 ps
CPU time 94.22 seconds
Started Jul 21 04:57:20 PM PDT 24
Finished Jul 21 04:58:55 PM PDT 24
Peak memory 213576 kb
Host smart-da4343ba-6968-4e49-acfc-0d0f4af3acf2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212726085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3212726085
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.812682198
Short name T391
Test name
Test status
Simulation time 14885018260 ps
CPU time 18.3 seconds
Started Jul 21 04:57:32 PM PDT 24
Finished Jul 21 04:57:51 PM PDT 24
Peak memory 215232 kb
Host smart-5764b1f3-4d58-4d69-9df8-1e4a805af19a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812682198 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.812682198
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.4521411
Short name T395
Test name
Test status
Simulation time 928454554 ps
CPU time 14.02 seconds
Started Jul 21 04:57:32 PM PDT 24
Finished Jul 21 04:57:46 PM PDT 24
Peak memory 211652 kb
Host smart-44269784-3f5f-44fa-a6b6-b4d67b60f15b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4521411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.4521411
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2717172783
Short name T368
Test name
Test status
Simulation time 1078451836 ps
CPU time 55.28 seconds
Started Jul 21 04:57:26 PM PDT 24
Finished Jul 21 04:58:22 PM PDT 24
Peak memory 214984 kb
Host smart-9451d83f-5b0d-48de-9b10-980671c00682
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717172783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2717172783
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3775116441
Short name T109
Test name
Test status
Simulation time 2859067968 ps
CPU time 22.3 seconds
Started Jul 21 04:57:31 PM PDT 24
Finished Jul 21 04:57:54 PM PDT 24
Peak memory 212284 kb
Host smart-2286fac2-c809-46ad-bced-19157cd61285
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775116441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3775116441
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2750384463
Short name T403
Test name
Test status
Simulation time 11502779078 ps
CPU time 29.96 seconds
Started Jul 21 04:57:28 PM PDT 24
Finished Jul 21 04:57:58 PM PDT 24
Peak memory 217528 kb
Host smart-681beb5b-8268-4788-b55b-e7ac9b9eb102
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750384463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2750384463
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3830192989
Short name T435
Test name
Test status
Simulation time 4220876809 ps
CPU time 86 seconds
Started Jul 21 04:57:34 PM PDT 24
Finished Jul 21 04:59:00 PM PDT 24
Peak memory 213216 kb
Host smart-ddec66c5-9c69-4087-b8c0-5b12a7be702d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830192989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3830192989
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1582758867
Short name T399
Test name
Test status
Simulation time 5353377273 ps
CPU time 23.49 seconds
Started Jul 21 04:57:36 PM PDT 24
Finished Jul 21 04:58:00 PM PDT 24
Peak memory 215536 kb
Host smart-66e2fcf2-9986-4262-811d-533e96b7f46b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582758867 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1582758867
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1375620523
Short name T352
Test name
Test status
Simulation time 4267288450 ps
CPU time 32.42 seconds
Started Jul 21 04:57:37 PM PDT 24
Finished Jul 21 04:58:10 PM PDT 24
Peak memory 211172 kb
Host smart-f335efa9-f5b6-496a-b279-d63fc2169430
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375620523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1375620523
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.349867470
Short name T431
Test name
Test status
Simulation time 20068944740 ps
CPU time 166.1 seconds
Started Jul 21 04:57:32 PM PDT 24
Finished Jul 21 05:00:18 PM PDT 24
Peak memory 215188 kb
Host smart-b26f2d86-5680-42b4-a935-1fde1d85510d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349867470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.349867470
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1019112490
Short name T104
Test name
Test status
Simulation time 5582420958 ps
CPU time 17.67 seconds
Started Jul 21 04:57:38 PM PDT 24
Finished Jul 21 04:57:56 PM PDT 24
Peak memory 211228 kb
Host smart-ccde1015-0903-4173-87e2-2d1d3ea66b08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019112490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1019112490
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3202664191
Short name T353
Test name
Test status
Simulation time 15016476780 ps
CPU time 33.94 seconds
Started Jul 21 04:57:37 PM PDT 24
Finished Jul 21 04:58:11 PM PDT 24
Peak memory 218796 kb
Host smart-53e55e09-c0c9-411e-90b5-e4489341ee67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202664191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3202664191
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2433052678
Short name T438
Test name
Test status
Simulation time 4893868946 ps
CPU time 105.19 seconds
Started Jul 21 04:57:37 PM PDT 24
Finished Jul 21 04:59:22 PM PDT 24
Peak memory 213728 kb
Host smart-27a54f11-f763-46b2-857e-b07a92deee25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433052678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2433052678
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1370196622
Short name T382
Test name
Test status
Simulation time 688249044 ps
CPU time 8.58 seconds
Started Jul 21 04:57:52 PM PDT 24
Finished Jul 21 04:58:01 PM PDT 24
Peak memory 214912 kb
Host smart-b353a56b-fad6-453a-bacf-df3acd1ddd4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370196622 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1370196622
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3251566286
Short name T417
Test name
Test status
Simulation time 13770914557 ps
CPU time 24.15 seconds
Started Jul 21 04:57:46 PM PDT 24
Finished Jul 21 04:58:11 PM PDT 24
Peak memory 212104 kb
Host smart-ad459579-3b5b-4d2b-9c93-872c39fcc267
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251566286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3251566286
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1496047563
Short name T106
Test name
Test status
Simulation time 11910071707 ps
CPU time 49.75 seconds
Started Jul 21 04:57:46 PM PDT 24
Finished Jul 21 04:58:36 PM PDT 24
Peak memory 214088 kb
Host smart-3363971d-b425-4d78-af5a-9e3c03c628f5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496047563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1496047563
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2523691804
Short name T108
Test name
Test status
Simulation time 688930907 ps
CPU time 8.19 seconds
Started Jul 21 04:57:50 PM PDT 24
Finished Jul 21 04:57:58 PM PDT 24
Peak memory 211012 kb
Host smart-bfeecd44-4b06-489b-925d-8afc76974602
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523691804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2523691804
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2768235669
Short name T419
Test name
Test status
Simulation time 10135001720 ps
CPU time 27.25 seconds
Started Jul 21 04:57:45 PM PDT 24
Finished Jul 21 04:58:12 PM PDT 24
Peak memory 217276 kb
Host smart-a47882ca-e4ef-4967-8e1f-7f1a64b52a88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768235669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2768235669
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.235629941
Short name T447
Test name
Test status
Simulation time 3382033050 ps
CPU time 18.88 seconds
Started Jul 21 04:57:50 PM PDT 24
Finished Jul 21 04:58:09 PM PDT 24
Peak memory 216600 kb
Host smart-219b1387-9486-453c-8381-fbaaea71b7f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235629941 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.235629941
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.72196985
Short name T424
Test name
Test status
Simulation time 203368327 ps
CPU time 7.99 seconds
Started Jul 21 04:57:48 PM PDT 24
Finished Jul 21 04:57:56 PM PDT 24
Peak memory 210400 kb
Host smart-d156d7e2-5d0a-4db6-9068-68816e50cf73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72196985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.72196985
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2238777892
Short name T408
Test name
Test status
Simulation time 15428886783 ps
CPU time 125.48 seconds
Started Jul 21 04:57:49 PM PDT 24
Finished Jul 21 04:59:55 PM PDT 24
Peak memory 214048 kb
Host smart-bf644806-5ae7-41de-8be5-2a596e575e72
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238777892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2238777892
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1031286204
Short name T396
Test name
Test status
Simulation time 9175469686 ps
CPU time 25.25 seconds
Started Jul 21 04:57:49 PM PDT 24
Finished Jul 21 04:58:15 PM PDT 24
Peak memory 212360 kb
Host smart-4bc054df-316b-4fd3-a7af-14ebb00bcfdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031286204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1031286204
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3057449057
Short name T405
Test name
Test status
Simulation time 34308537918 ps
CPU time 25.49 seconds
Started Jul 21 04:57:50 PM PDT 24
Finished Jul 21 04:58:15 PM PDT 24
Peak memory 217332 kb
Host smart-07e2e566-21a3-41fe-8a21-60e9f08b86e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057449057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3057449057
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2970591961
Short name T361
Test name
Test status
Simulation time 4175687438 ps
CPU time 85.44 seconds
Started Jul 21 04:57:50 PM PDT 24
Finished Jul 21 04:59:16 PM PDT 24
Peak memory 213436 kb
Host smart-8f3f6a40-372a-44b6-88d3-e268faeae38b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970591961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2970591961
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1978875002
Short name T371
Test name
Test status
Simulation time 3062113195 ps
CPU time 9.57 seconds
Started Jul 21 04:57:56 PM PDT 24
Finished Jul 21 04:58:06 PM PDT 24
Peak memory 216792 kb
Host smart-408829b0-56f4-436f-ae9d-a39194a15721
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978875002 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1978875002
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1225299760
Short name T443
Test name
Test status
Simulation time 12553165957 ps
CPU time 25.27 seconds
Started Jul 21 04:57:54 PM PDT 24
Finished Jul 21 04:58:20 PM PDT 24
Peak memory 212176 kb
Host smart-3d07955e-7769-4a37-8ff6-31ef75e04683
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225299760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1225299760
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3004296129
Short name T76
Test name
Test status
Simulation time 6885673482 ps
CPU time 57.8 seconds
Started Jul 21 04:57:55 PM PDT 24
Finished Jul 21 04:58:53 PM PDT 24
Peak memory 214856 kb
Host smart-93fba54d-5a9c-4f52-9d30-3cfd811b9986
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004296129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3004296129
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2612906136
Short name T103
Test name
Test status
Simulation time 923048456 ps
CPU time 12.29 seconds
Started Jul 21 04:57:56 PM PDT 24
Finished Jul 21 04:58:08 PM PDT 24
Peak memory 212356 kb
Host smart-b2d0388b-41ba-424d-94bb-c0b572469a50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612906136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2612906136
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1586792194
Short name T439
Test name
Test status
Simulation time 661980929 ps
CPU time 13.84 seconds
Started Jul 21 04:57:56 PM PDT 24
Finished Jul 21 04:58:10 PM PDT 24
Peak memory 216168 kb
Host smart-cd8f00d4-f2d8-404a-a27e-6e739819e77c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586792194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1586792194
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2999713199
Short name T116
Test name
Test status
Simulation time 1254435128 ps
CPU time 88.9 seconds
Started Jul 21 04:57:54 PM PDT 24
Finished Jul 21 04:59:24 PM PDT 24
Peak memory 212228 kb
Host smart-98fd11c4-9e50-46e4-a353-180148d036b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999713199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2999713199
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1056114403
Short name T256
Test name
Test status
Simulation time 5794846300 ps
CPU time 16.9 seconds
Started Jul 21 04:58:37 PM PDT 24
Finished Jul 21 04:58:55 PM PDT 24
Peak memory 217356 kb
Host smart-d29e82fd-c250-45e8-9229-da9cbcec26f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056114403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1056114403
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1767026629
Short name T177
Test name
Test status
Simulation time 305588606238 ps
CPU time 933.92 seconds
Started Jul 21 04:58:38 PM PDT 24
Finished Jul 21 05:14:12 PM PDT 24
Peak memory 234436 kb
Host smart-1f64420c-8019-4a04-99cb-bca1cc1189bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767026629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1767026629
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1668428988
Short name T236
Test name
Test status
Simulation time 8198621382 ps
CPU time 54.77 seconds
Started Jul 21 04:58:37 PM PDT 24
Finished Jul 21 04:59:32 PM PDT 24
Peak memory 219100 kb
Host smart-cb0732dc-33a4-4a75-b168-aedf93063105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668428988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1668428988
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3877276457
Short name T250
Test name
Test status
Simulation time 4450444686 ps
CPU time 20.47 seconds
Started Jul 21 04:58:37 PM PDT 24
Finished Jul 21 04:58:58 PM PDT 24
Peak memory 211928 kb
Host smart-323effc0-80ad-4e76-a255-5c96d782d371
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3877276457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3877276457
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1527822687
Short name T273
Test name
Test status
Simulation time 8291671242 ps
CPU time 70.66 seconds
Started Jul 21 04:58:33 PM PDT 24
Finished Jul 21 04:59:44 PM PDT 24
Peak memory 216348 kb
Host smart-6c31e80c-45b5-4957-993a-398ad70c14c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527822687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1527822687
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.544322939
Short name T282
Test name
Test status
Simulation time 32771084201 ps
CPU time 280.26 seconds
Started Jul 21 04:58:38 PM PDT 24
Finished Jul 21 05:03:19 PM PDT 24
Peak memory 222532 kb
Host smart-f8debae3-ca43-4fc7-9267-a37c95efd60c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544322939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.544322939
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3722261716
Short name T291
Test name
Test status
Simulation time 8482063873 ps
CPU time 21.36 seconds
Started Jul 21 04:58:43 PM PDT 24
Finished Jul 21 04:59:04 PM PDT 24
Peak memory 213200 kb
Host smart-d4527158-1db5-4068-8329-74177f6383d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722261716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3722261716
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3095413265
Short name T239
Test name
Test status
Simulation time 107540111225 ps
CPU time 283.88 seconds
Started Jul 21 04:58:43 PM PDT 24
Finished Jul 21 05:03:27 PM PDT 24
Peak memory 223672 kb
Host smart-c7d279f3-effa-43e3-862b-c6cb234e7ee2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095413265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3095413265
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.37791875
Short name T126
Test name
Test status
Simulation time 60403776487 ps
CPU time 32.33 seconds
Started Jul 21 04:58:37 PM PDT 24
Finished Jul 21 04:59:10 PM PDT 24
Peak memory 217624 kb
Host smart-526fa9ef-d12f-49ca-a653-4bfa7d3989af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=37791875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.37791875
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.47478369
Short name T29
Test name
Test status
Simulation time 5363621315 ps
CPU time 236.27 seconds
Started Jul 21 04:58:44 PM PDT 24
Finished Jul 21 05:02:40 PM PDT 24
Peak memory 238004 kb
Host smart-d25e34c0-fe05-4406-b577-6b04c80d9e9b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47478369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.47478369
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1839659892
Short name T129
Test name
Test status
Simulation time 4090168055 ps
CPU time 32.97 seconds
Started Jul 21 04:58:38 PM PDT 24
Finished Jul 21 04:59:11 PM PDT 24
Peak memory 216188 kb
Host smart-3fbc5809-caff-4228-b1c9-44f980013894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839659892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1839659892
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.382252506
Short name T244
Test name
Test status
Simulation time 60897258007 ps
CPU time 133.37 seconds
Started Jul 21 04:58:40 PM PDT 24
Finished Jul 21 05:00:53 PM PDT 24
Peak memory 219624 kb
Host smart-db440c68-7349-4ebb-b21e-3a5ea847b18f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382252506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.382252506
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3062122982
Short name T101
Test name
Test status
Simulation time 2057032510 ps
CPU time 8.29 seconds
Started Jul 21 04:59:21 PM PDT 24
Finished Jul 21 04:59:29 PM PDT 24
Peak memory 213088 kb
Host smart-2ca9dbdd-6723-4022-be76-9873c66495a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062122982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3062122982
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3070649343
Short name T258
Test name
Test status
Simulation time 22121273165 ps
CPU time 327.06 seconds
Started Jul 21 04:59:21 PM PDT 24
Finished Jul 21 05:04:48 PM PDT 24
Peak memory 215860 kb
Host smart-bbfb4545-6463-4cbf-98af-f1b5e7967e5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070649343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3070649343
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3711777049
Short name T151
Test name
Test status
Simulation time 8358647258 ps
CPU time 65.54 seconds
Started Jul 21 04:59:17 PM PDT 24
Finished Jul 21 05:00:23 PM PDT 24
Peak memory 219536 kb
Host smart-07e11b87-ed9e-45e8-a1a7-d5cacf91476a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711777049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3711777049
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1359623544
Short name T343
Test name
Test status
Simulation time 7071749225 ps
CPU time 33.43 seconds
Started Jul 21 04:59:19 PM PDT 24
Finished Jul 21 04:59:53 PM PDT 24
Peak memory 219228 kb
Host smart-367e4632-ea3f-40c0-89a7-b3ec97c7f15f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1359623544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1359623544
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.4081328913
Short name T211
Test name
Test status
Simulation time 28949564901 ps
CPU time 36.52 seconds
Started Jul 21 04:59:19 PM PDT 24
Finished Jul 21 04:59:56 PM PDT 24
Peak memory 217160 kb
Host smart-45ec1cec-c9b1-4082-85ee-92c8682b1fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081328913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.4081328913
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1628584712
Short name T86
Test name
Test status
Simulation time 29392321335 ps
CPU time 69.49 seconds
Started Jul 21 04:59:18 PM PDT 24
Finished Jul 21 05:00:28 PM PDT 24
Peak memory 218172 kb
Host smart-11719781-30c6-4fa4-8fe2-67aae6593070
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628584712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1628584712
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2434376258
Short name T34
Test name
Test status
Simulation time 339272090 ps
CPU time 8.53 seconds
Started Jul 21 04:59:24 PM PDT 24
Finished Jul 21 04:59:33 PM PDT 24
Peak memory 216708 kb
Host smart-096dbb12-5c28-40c2-a7c6-fcb69ef9df82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434376258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2434376258
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2212181704
Short name T41
Test name
Test status
Simulation time 186970631861 ps
CPU time 688.16 seconds
Started Jul 21 04:59:27 PM PDT 24
Finished Jul 21 05:10:55 PM PDT 24
Peak memory 235880 kb
Host smart-66be645c-182f-49a1-a593-16e6db6d28d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212181704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2212181704
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2954991682
Short name T226
Test name
Test status
Simulation time 28367255386 ps
CPU time 58.52 seconds
Started Jul 21 04:59:25 PM PDT 24
Finished Jul 21 05:00:23 PM PDT 24
Peak memory 219344 kb
Host smart-aa8642c2-529c-4844-b4cf-938e7a83bdb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954991682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2954991682
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.4062848241
Short name T341
Test name
Test status
Simulation time 1184280263 ps
CPU time 16.81 seconds
Started Jul 21 04:59:26 PM PDT 24
Finished Jul 21 04:59:43 PM PDT 24
Peak memory 219180 kb
Host smart-c709dcc6-cfc8-4d1a-8c90-add01eb3b10e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4062848241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.4062848241
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3856313960
Short name T301
Test name
Test status
Simulation time 7720638315 ps
CPU time 43.87 seconds
Started Jul 21 04:59:20 PM PDT 24
Finished Jul 21 05:00:04 PM PDT 24
Peak memory 216756 kb
Host smart-e6684873-8ada-4cfa-aaba-a5e428fc4784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856313960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3856313960
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2331539884
Short name T232
Test name
Test status
Simulation time 726333189 ps
CPU time 44.26 seconds
Started Jul 21 04:59:21 PM PDT 24
Finished Jul 21 05:00:05 PM PDT 24
Peak memory 219168 kb
Host smart-08be569f-a24c-41e3-a203-93e34bb727b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331539884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2331539884
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1859597738
Short name T289
Test name
Test status
Simulation time 26265439623 ps
CPU time 35.37 seconds
Started Jul 21 04:59:32 PM PDT 24
Finished Jul 21 05:00:07 PM PDT 24
Peak memory 213256 kb
Host smart-70c6ad03-c6cc-4980-a7f7-e4f398fa6120
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859597738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1859597738
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1821483291
Short name T247
Test name
Test status
Simulation time 127018476764 ps
CPU time 310.29 seconds
Started Jul 21 04:59:25 PM PDT 24
Finished Jul 21 05:04:36 PM PDT 24
Peak memory 238160 kb
Host smart-991c41f3-41a1-434f-91b0-ae038adac010
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821483291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1821483291
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2980213748
Short name T309
Test name
Test status
Simulation time 32730677660 ps
CPU time 63.59 seconds
Started Jul 21 04:59:25 PM PDT 24
Finished Jul 21 05:00:29 PM PDT 24
Peak memory 218788 kb
Host smart-30647e28-beaa-40de-aad6-171c1f915572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980213748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2980213748
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.4209871728
Short name T191
Test name
Test status
Simulation time 18288726973 ps
CPU time 32.66 seconds
Started Jul 21 04:59:23 PM PDT 24
Finished Jul 21 04:59:56 PM PDT 24
Peak memory 217632 kb
Host smart-5c7f8a24-c727-424d-8c63-5bf135847094
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4209871728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.4209871728
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3993838237
Short name T199
Test name
Test status
Simulation time 350229924 ps
CPU time 19.83 seconds
Started Jul 21 04:59:24 PM PDT 24
Finished Jul 21 04:59:44 PM PDT 24
Peak memory 216604 kb
Host smart-c983550c-215e-48fc-8260-9d78c95671fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993838237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3993838237
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2287948255
Short name T204
Test name
Test status
Simulation time 12782091045 ps
CPU time 57.21 seconds
Started Jul 21 04:59:25 PM PDT 24
Finished Jul 21 05:00:22 PM PDT 24
Peak memory 219240 kb
Host smart-8ed3e2e3-1af9-47a5-83ef-d7b5763d26eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287948255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2287948255
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2224349461
Short name T224
Test name
Test status
Simulation time 17053968374 ps
CPU time 21.03 seconds
Started Jul 21 04:59:31 PM PDT 24
Finished Jul 21 04:59:53 PM PDT 24
Peak memory 217412 kb
Host smart-0ff69f25-4815-46a3-a5cf-db59326193ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224349461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2224349461
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2242969419
Short name T149
Test name
Test status
Simulation time 60469506477 ps
CPU time 583.68 seconds
Started Jul 21 04:59:32 PM PDT 24
Finished Jul 21 05:09:16 PM PDT 24
Peak memory 217800 kb
Host smart-0ae65597-4ac2-4f42-a9e4-ea6d1d5d8adf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242969419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2242969419
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.160717996
Short name T220
Test name
Test status
Simulation time 6692976404 ps
CPU time 29.06 seconds
Started Jul 21 04:59:30 PM PDT 24
Finished Jul 21 04:59:59 PM PDT 24
Peak memory 219272 kb
Host smart-9f3b7016-54e4-49b6-9320-c94b7d505233
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=160717996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.160717996
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.4038056086
Short name T265
Test name
Test status
Simulation time 4397261162 ps
CPU time 35.93 seconds
Started Jul 21 04:59:32 PM PDT 24
Finished Jul 21 05:00:08 PM PDT 24
Peak memory 216492 kb
Host smart-ba84a1ef-365c-4366-b190-4a5a81542fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038056086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.4038056086
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2697932395
Short name T319
Test name
Test status
Simulation time 2727610875 ps
CPU time 12.94 seconds
Started Jul 21 04:59:38 PM PDT 24
Finished Jul 21 04:59:51 PM PDT 24
Peak memory 217128 kb
Host smart-5a135726-54fe-4ae5-a9d1-837948374a6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697932395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2697932395
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1972964356
Short name T36
Test name
Test status
Simulation time 82664227496 ps
CPU time 760.7 seconds
Started Jul 21 04:59:31 PM PDT 24
Finished Jul 21 05:12:12 PM PDT 24
Peak memory 239584 kb
Host smart-6a708711-ee85-48a0-b1ca-5e5dab9d47c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972964356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1972964356
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.810624454
Short name T140
Test name
Test status
Simulation time 26053056605 ps
CPU time 53.65 seconds
Started Jul 21 04:59:39 PM PDT 24
Finished Jul 21 05:00:33 PM PDT 24
Peak memory 219252 kb
Host smart-9fa3912f-4575-4c7b-810b-54b326790d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810624454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.810624454
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1724879208
Short name T138
Test name
Test status
Simulation time 3476361221 ps
CPU time 29.72 seconds
Started Jul 21 04:59:32 PM PDT 24
Finished Jul 21 05:00:02 PM PDT 24
Peak memory 211208 kb
Host smart-c84cac0f-29f1-45c5-8672-88c811a33953
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1724879208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1724879208
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.597595333
Short name T212
Test name
Test status
Simulation time 7722969773 ps
CPU time 43.23 seconds
Started Jul 21 04:59:31 PM PDT 24
Finished Jul 21 05:00:15 PM PDT 24
Peak memory 217008 kb
Host smart-5d58ac28-46be-4ae4-8fe8-9096d557e029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597595333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.597595333
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.264321598
Short name T233
Test name
Test status
Simulation time 6748730259 ps
CPU time 61.6 seconds
Started Jul 21 04:59:31 PM PDT 24
Finished Jul 21 05:00:33 PM PDT 24
Peak memory 220752 kb
Host smart-920ed501-d986-431f-99e1-0cda9b7057b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264321598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.264321598
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.4070049994
Short name T292
Test name
Test status
Simulation time 6216183862 ps
CPU time 24.42 seconds
Started Jul 21 04:59:37 PM PDT 24
Finished Jul 21 05:00:01 PM PDT 24
Peak memory 213200 kb
Host smart-a380d140-36aa-4cff-8cea-5c291bc3a7cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070049994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.4070049994
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2895108868
Short name T300
Test name
Test status
Simulation time 16350217598 ps
CPU time 65.84 seconds
Started Jul 21 04:59:36 PM PDT 24
Finished Jul 21 05:00:42 PM PDT 24
Peak memory 219232 kb
Host smart-da744a77-adfd-4317-a943-3eec76aa71a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895108868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2895108868
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3275726205
Short name T190
Test name
Test status
Simulation time 1123203848 ps
CPU time 16.87 seconds
Started Jul 21 04:59:36 PM PDT 24
Finished Jul 21 04:59:53 PM PDT 24
Peak memory 219252 kb
Host smart-ca7765a4-15a6-4281-a575-f667c06e94cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3275726205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3275726205
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3158409417
Short name T64
Test name
Test status
Simulation time 8211814892 ps
CPU time 67.14 seconds
Started Jul 21 04:59:38 PM PDT 24
Finished Jul 21 05:00:45 PM PDT 24
Peak memory 216352 kb
Host smart-aec2b4e0-bc55-40f5-80f9-c58790a3eb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158409417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3158409417
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2891337733
Short name T87
Test name
Test status
Simulation time 11345879166 ps
CPU time 67.64 seconds
Started Jul 21 04:59:36 PM PDT 24
Finished Jul 21 05:00:44 PM PDT 24
Peak memory 217820 kb
Host smart-d3f1d102-e017-4dc5-aec0-224dee45bd23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891337733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2891337733
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2061064964
Short name T158
Test name
Test status
Simulation time 2545627012 ps
CPU time 23.95 seconds
Started Jul 21 04:59:42 PM PDT 24
Finished Jul 21 05:00:06 PM PDT 24
Peak memory 217256 kb
Host smart-5d51f770-a28f-4088-96c6-18c69cd1821d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061064964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2061064964
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3927811468
Short name T131
Test name
Test status
Simulation time 19146157492 ps
CPU time 45.94 seconds
Started Jul 21 04:59:45 PM PDT 24
Finished Jul 21 05:00:31 PM PDT 24
Peak memory 219320 kb
Host smart-f31e944c-5f42-4758-b4f0-430e5e60b86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927811468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3927811468
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1163959455
Short name T327
Test name
Test status
Simulation time 14929382758 ps
CPU time 24 seconds
Started Jul 21 04:59:43 PM PDT 24
Finished Jul 21 05:00:08 PM PDT 24
Peak memory 219224 kb
Host smart-74f42d14-c6cc-46d3-91ba-ad146f1c8c07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1163959455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1163959455
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2875389014
Short name T302
Test name
Test status
Simulation time 12598231888 ps
CPU time 103.19 seconds
Started Jul 21 04:59:45 PM PDT 24
Finished Jul 21 05:01:28 PM PDT 24
Peak memory 219304 kb
Host smart-2a977b60-3bed-4d1a-bc2c-5827835f78de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875389014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2875389014
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3744741127
Short name T210
Test name
Test status
Simulation time 8262604152 ps
CPU time 21.24 seconds
Started Jul 21 04:59:42 PM PDT 24
Finished Jul 21 05:00:04 PM PDT 24
Peak memory 217120 kb
Host smart-08e5c6f9-0d24-4714-a21e-ad81f1156d31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744741127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3744741127
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3891248942
Short name T349
Test name
Test status
Simulation time 60602096360 ps
CPU time 317.27 seconds
Started Jul 21 04:59:43 PM PDT 24
Finished Jul 21 05:05:00 PM PDT 24
Peak memory 242004 kb
Host smart-e3f8db71-013b-4d78-b4f0-7f58c955ea24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891248942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3891248942
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.498606616
Short name T315
Test name
Test status
Simulation time 16733842895 ps
CPU time 68.35 seconds
Started Jul 21 04:59:44 PM PDT 24
Finished Jul 21 05:00:53 PM PDT 24
Peak memory 219292 kb
Host smart-069fa0a8-445b-4429-a2be-44940d8963f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498606616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.498606616
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3740831622
Short name T192
Test name
Test status
Simulation time 3125021319 ps
CPU time 15.69 seconds
Started Jul 21 04:59:42 PM PDT 24
Finished Jul 21 04:59:58 PM PDT 24
Peak memory 219252 kb
Host smart-0a98c3aa-a76d-461d-bf5d-bc9316c51f62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3740831622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3740831622
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.931024411
Short name T9
Test name
Test status
Simulation time 10954101657 ps
CPU time 55.66 seconds
Started Jul 21 04:59:45 PM PDT 24
Finished Jul 21 05:00:41 PM PDT 24
Peak memory 217060 kb
Host smart-94d06a9a-f071-4d9b-9106-23a9a8977c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931024411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.931024411
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3027318264
Short name T125
Test name
Test status
Simulation time 1731607831 ps
CPU time 13.18 seconds
Started Jul 21 04:59:45 PM PDT 24
Finished Jul 21 04:59:58 PM PDT 24
Peak memory 215684 kb
Host smart-1c50f969-916b-450a-9b6c-4bda81ca0e5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027318264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3027318264
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.430527184
Short name T286
Test name
Test status
Simulation time 185971025 ps
CPU time 8.36 seconds
Started Jul 21 04:59:47 PM PDT 24
Finished Jul 21 04:59:55 PM PDT 24
Peak memory 217104 kb
Host smart-a8b305c9-d159-4589-a617-4d48b0b0214e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430527184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.430527184
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.4074788184
Short name T99
Test name
Test status
Simulation time 165933978270 ps
CPU time 545.96 seconds
Started Jul 21 04:59:47 PM PDT 24
Finished Jul 21 05:08:53 PM PDT 24
Peak memory 236140 kb
Host smart-248f793d-0700-40f4-bea8-8b3d41bde806
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074788184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.4074788184
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.659830179
Short name T27
Test name
Test status
Simulation time 7563435788 ps
CPU time 64.84 seconds
Started Jul 21 04:59:48 PM PDT 24
Finished Jul 21 05:00:53 PM PDT 24
Peak memory 219288 kb
Host smart-0e1594bc-d83f-4dab-8d3b-d0ba5d108b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659830179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.659830179
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.678656412
Short name T294
Test name
Test status
Simulation time 5033539413 ps
CPU time 20.77 seconds
Started Jul 21 04:59:43 PM PDT 24
Finished Jul 21 05:00:04 PM PDT 24
Peak memory 211736 kb
Host smart-4e7622ff-a66d-45f7-8cd1-c97de6f837ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=678656412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.678656412
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.3334010824
Short name T128
Test name
Test status
Simulation time 32735942235 ps
CPU time 65.18 seconds
Started Jul 21 04:59:45 PM PDT 24
Finished Jul 21 05:00:50 PM PDT 24
Peak memory 215824 kb
Host smart-cea37ace-bf6d-4db1-8358-77aeb2a4c8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334010824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.3334010824
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1455816816
Short name T7
Test name
Test status
Simulation time 7886995066 ps
CPU time 40.23 seconds
Started Jul 21 04:59:45 PM PDT 24
Finished Jul 21 05:00:25 PM PDT 24
Peak memory 219164 kb
Host smart-177fa852-04ac-4984-8ed9-0360a93795f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455816816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1455816816
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1155164794
Short name T231
Test name
Test status
Simulation time 10813481226 ps
CPU time 25.39 seconds
Started Jul 21 04:59:48 PM PDT 24
Finished Jul 21 05:00:13 PM PDT 24
Peak memory 213292 kb
Host smart-ff82c762-8d3f-4b4d-9076-fa858795e2c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155164794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1155164794
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3682124899
Short name T324
Test name
Test status
Simulation time 20223793553 ps
CPU time 217.3 seconds
Started Jul 21 04:59:46 PM PDT 24
Finished Jul 21 05:03:23 PM PDT 24
Peak memory 237864 kb
Host smart-994b7ec0-f89e-4684-848e-b488908a44e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682124899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3682124899
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3151166210
Short name T328
Test name
Test status
Simulation time 23701312405 ps
CPU time 52.27 seconds
Started Jul 21 04:59:48 PM PDT 24
Finished Jul 21 05:00:41 PM PDT 24
Peak memory 219276 kb
Host smart-100423a1-12e2-45df-b812-4babd31ce20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151166210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3151166210
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2385319135
Short name T156
Test name
Test status
Simulation time 593580992 ps
CPU time 14.79 seconds
Started Jul 21 04:59:47 PM PDT 24
Finished Jul 21 05:00:02 PM PDT 24
Peak memory 211264 kb
Host smart-b62a0795-64a2-4444-bd55-95268de2f6ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2385319135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2385319135
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.981259453
Short name T248
Test name
Test status
Simulation time 5487303702 ps
CPU time 49.65 seconds
Started Jul 21 04:59:47 PM PDT 24
Finished Jul 21 05:00:37 PM PDT 24
Peak memory 216564 kb
Host smart-fa03138a-f0aa-4330-a730-92182d77922d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981259453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.981259453
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2370379997
Short name T321
Test name
Test status
Simulation time 1071925304 ps
CPU time 15.11 seconds
Started Jul 21 04:59:47 PM PDT 24
Finished Jul 21 05:00:03 PM PDT 24
Peak memory 214684 kb
Host smart-8b843605-0cb4-4387-aeb2-304dc9176c62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370379997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2370379997
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.3342104942
Short name T56
Test name
Test status
Simulation time 127658553698 ps
CPU time 1264.64 seconds
Started Jul 21 04:59:47 PM PDT 24
Finished Jul 21 05:20:52 PM PDT 24
Peak memory 235692 kb
Host smart-5a3c8430-cd22-446d-8b7d-3bb7300e8854
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342104942 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.3342104942
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.687334047
Short name T350
Test name
Test status
Simulation time 11062318035 ps
CPU time 26.93 seconds
Started Jul 21 04:58:51 PM PDT 24
Finished Jul 21 04:59:18 PM PDT 24
Peak memory 213212 kb
Host smart-cda47a35-7144-45df-bb79-3c1946d5417f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687334047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.687334047
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3038620221
Short name T311
Test name
Test status
Simulation time 24426377440 ps
CPU time 268.69 seconds
Started Jul 21 04:58:41 PM PDT 24
Finished Jul 21 05:03:11 PM PDT 24
Peak memory 237828 kb
Host smart-8f7e78f0-62f6-4bdb-b31c-4136eb7c196d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038620221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3038620221
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.553229629
Short name T268
Test name
Test status
Simulation time 14045581333 ps
CPU time 60.08 seconds
Started Jul 21 04:58:42 PM PDT 24
Finished Jul 21 04:59:43 PM PDT 24
Peak memory 219156 kb
Host smart-d65549dc-62a8-4cdc-bd10-d1ac6f158c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553229629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.553229629
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3939615775
Short name T96
Test name
Test status
Simulation time 13382264937 ps
CPU time 15.36 seconds
Started Jul 21 04:58:42 PM PDT 24
Finished Jul 21 04:58:58 PM PDT 24
Peak memory 211092 kb
Host smart-3729eec5-00b3-49d2-80f0-18a136c33066
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3939615775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3939615775
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3071313852
Short name T21
Test name
Test status
Simulation time 3620085048 ps
CPU time 137.76 seconds
Started Jul 21 04:58:50 PM PDT 24
Finished Jul 21 05:01:08 PM PDT 24
Peak memory 238424 kb
Host smart-76aba480-1ae3-46c3-9015-fa9ffe3fd9aa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071313852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3071313852
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2326429222
Short name T144
Test name
Test status
Simulation time 1404804044 ps
CPU time 20.07 seconds
Started Jul 21 04:58:42 PM PDT 24
Finished Jul 21 04:59:03 PM PDT 24
Peak memory 216408 kb
Host smart-f3e101f7-065c-4240-ba35-c92ad340a83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326429222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2326429222
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3723848184
Short name T85
Test name
Test status
Simulation time 12117867316 ps
CPU time 117.76 seconds
Started Jul 21 04:58:42 PM PDT 24
Finished Jul 21 05:00:40 PM PDT 24
Peak memory 219288 kb
Host smart-4c892110-2e38-4f12-92b7-dfaa09ab69d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723848184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3723848184
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1390675822
Short name T11
Test name
Test status
Simulation time 27448360722 ps
CPU time 1087.26 seconds
Started Jul 21 04:58:51 PM PDT 24
Finished Jul 21 05:16:59 PM PDT 24
Peak memory 235748 kb
Host smart-92f0da82-022b-4fa4-9075-4a3a135a7ab7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390675822 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.1390675822
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.353167129
Short name T205
Test name
Test status
Simulation time 10162918419 ps
CPU time 28.38 seconds
Started Jul 21 04:59:53 PM PDT 24
Finished Jul 21 05:00:21 PM PDT 24
Peak memory 217460 kb
Host smart-d2aa890a-99b2-4ecc-b5b0-69478287cd38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353167129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.353167129
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.377468400
Short name T207
Test name
Test status
Simulation time 67700346892 ps
CPU time 692.67 seconds
Started Jul 21 04:59:54 PM PDT 24
Finished Jul 21 05:11:28 PM PDT 24
Peak memory 237908 kb
Host smart-3d1bda7a-f206-4206-9608-b85e3a9861ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377468400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.377468400
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3131218472
Short name T255
Test name
Test status
Simulation time 7944359354 ps
CPU time 67.98 seconds
Started Jul 21 04:59:54 PM PDT 24
Finished Jul 21 05:01:02 PM PDT 24
Peak memory 219256 kb
Host smart-edbd4614-1f25-4559-9320-8a3bd73a4819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131218472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3131218472
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.647113171
Short name T164
Test name
Test status
Simulation time 789192521 ps
CPU time 10.46 seconds
Started Jul 21 04:59:52 PM PDT 24
Finished Jul 21 05:00:03 PM PDT 24
Peak memory 219276 kb
Host smart-b00e27b1-aaaf-43f4-af18-de7e1e9e57ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=647113171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.647113171
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.1842256423
Short name T339
Test name
Test status
Simulation time 18575644506 ps
CPU time 46.01 seconds
Started Jul 21 04:59:48 PM PDT 24
Finished Jul 21 05:00:35 PM PDT 24
Peak memory 219040 kb
Host smart-3586c804-3415-4e2e-9603-38468015f5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842256423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.1842256423
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3247565220
Short name T307
Test name
Test status
Simulation time 5450809299 ps
CPU time 59.46 seconds
Started Jul 21 04:59:54 PM PDT 24
Finished Jul 21 05:00:53 PM PDT 24
Peak memory 216900 kb
Host smart-e2452d76-2018-45f0-b4c9-319254b2d49e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247565220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3247565220
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2792012017
Short name T262
Test name
Test status
Simulation time 177826594 ps
CPU time 8.57 seconds
Started Jul 21 05:00:01 PM PDT 24
Finished Jul 21 05:00:10 PM PDT 24
Peak memory 217028 kb
Host smart-7a2c1fd2-79ad-49e5-bb69-92b333b53b03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792012017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2792012017
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3912197990
Short name T340
Test name
Test status
Simulation time 16099912628 ps
CPU time 238.3 seconds
Started Jul 21 05:00:01 PM PDT 24
Finished Jul 21 05:04:00 PM PDT 24
Peak memory 242584 kb
Host smart-96bf9e23-ba74-4b17-88bd-14d2f48eb24b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912197990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3912197990
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1118442990
Short name T94
Test name
Test status
Simulation time 8144527198 ps
CPU time 34.77 seconds
Started Jul 21 05:00:00 PM PDT 24
Finished Jul 21 05:00:35 PM PDT 24
Peak memory 219336 kb
Host smart-79a28f9c-e3ae-44a9-850d-699876779354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118442990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1118442990
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.544222110
Short name T143
Test name
Test status
Simulation time 13433118688 ps
CPU time 28.57 seconds
Started Jul 21 05:00:00 PM PDT 24
Finished Jul 21 05:00:29 PM PDT 24
Peak memory 219260 kb
Host smart-20066d25-4403-4fdd-b039-5736d8effa36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=544222110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.544222110
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3633545262
Short name T288
Test name
Test status
Simulation time 8056011324 ps
CPU time 81.32 seconds
Started Jul 21 04:59:52 PM PDT 24
Finished Jul 21 05:01:14 PM PDT 24
Peak memory 217152 kb
Host smart-ebdc4b05-7473-4449-bffa-11d5d90a85d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633545262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3633545262
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3354678004
Short name T234
Test name
Test status
Simulation time 6894342200 ps
CPU time 67.81 seconds
Started Jul 21 04:59:54 PM PDT 24
Finished Jul 21 05:01:02 PM PDT 24
Peak memory 219280 kb
Host smart-43faba03-be81-44d5-9aad-9917640e5323
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354678004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3354678004
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.650764505
Short name T337
Test name
Test status
Simulation time 550859275 ps
CPU time 8.56 seconds
Started Jul 21 05:00:05 PM PDT 24
Finished Jul 21 05:00:14 PM PDT 24
Peak memory 217068 kb
Host smart-aeb039fb-130f-4447-9185-13aafc76973e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650764505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.650764505
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.4154961436
Short name T45
Test name
Test status
Simulation time 40613428201 ps
CPU time 475.8 seconds
Started Jul 21 05:00:01 PM PDT 24
Finished Jul 21 05:07:57 PM PDT 24
Peak memory 237684 kb
Host smart-d5250711-1779-4108-bd4b-ac17b5983cfa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154961436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.4154961436
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2022398722
Short name T189
Test name
Test status
Simulation time 7060911625 ps
CPU time 40.63 seconds
Started Jul 21 04:59:59 PM PDT 24
Finished Jul 21 05:00:40 PM PDT 24
Peak memory 219320 kb
Host smart-ca4c1f43-c0d2-4bca-8e8f-8b757bd5950a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022398722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2022398722
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3214724541
Short name T170
Test name
Test status
Simulation time 1004303764 ps
CPU time 17.14 seconds
Started Jul 21 05:00:00 PM PDT 24
Finished Jul 21 05:00:18 PM PDT 24
Peak memory 211636 kb
Host smart-14d2ca0c-0b73-4203-a968-4b67f1c6c779
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3214724541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3214724541
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1815707530
Short name T111
Test name
Test status
Simulation time 34066131365 ps
CPU time 66.8 seconds
Started Jul 21 05:00:01 PM PDT 24
Finished Jul 21 05:01:08 PM PDT 24
Peak memory 216940 kb
Host smart-73e8ecf0-ff35-48bd-b203-0050c22dda3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815707530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1815707530
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2535832336
Short name T278
Test name
Test status
Simulation time 2018319705 ps
CPU time 24.19 seconds
Started Jul 21 05:00:01 PM PDT 24
Finished Jul 21 05:00:25 PM PDT 24
Peak memory 214656 kb
Host smart-35fe55c6-68ea-4aeb-8069-775e572598cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535832336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2535832336
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2380832133
Short name T167
Test name
Test status
Simulation time 2833413645 ps
CPU time 13.88 seconds
Started Jul 21 05:00:06 PM PDT 24
Finished Jul 21 05:00:21 PM PDT 24
Peak memory 217072 kb
Host smart-97299931-0231-4abb-88d4-3a8b189e55b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380832133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2380832133
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2353972440
Short name T241
Test name
Test status
Simulation time 164668343580 ps
CPU time 466.05 seconds
Started Jul 21 05:00:05 PM PDT 24
Finished Jul 21 05:07:52 PM PDT 24
Peak memory 237772 kb
Host smart-5957b2ba-d9d8-4d98-81e7-ebc266d28070
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353972440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2353972440
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.544547380
Short name T38
Test name
Test status
Simulation time 3468873989 ps
CPU time 39.75 seconds
Started Jul 21 05:00:07 PM PDT 24
Finished Jul 21 05:00:47 PM PDT 24
Peak memory 219340 kb
Host smart-f89cac5b-8473-4738-b8dd-5ab3b8e7402a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544547380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.544547380
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2076168494
Short name T260
Test name
Test status
Simulation time 2058077483 ps
CPU time 21.92 seconds
Started Jul 21 05:00:06 PM PDT 24
Finished Jul 21 05:00:28 PM PDT 24
Peak memory 219188 kb
Host smart-7825c300-c55c-4f8f-80df-7a1f5b78194b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2076168494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2076168494
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3798727947
Short name T32
Test name
Test status
Simulation time 2310993005 ps
CPU time 39.39 seconds
Started Jul 21 05:00:06 PM PDT 24
Finished Jul 21 05:00:46 PM PDT 24
Peak memory 216296 kb
Host smart-26e770c1-8a20-45cb-ad3a-f9298ff16336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798727947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3798727947
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1722221004
Short name T306
Test name
Test status
Simulation time 3068350483 ps
CPU time 36.8 seconds
Started Jul 21 05:00:07 PM PDT 24
Finished Jul 21 05:00:44 PM PDT 24
Peak memory 219316 kb
Host smart-656229b3-107b-47c1-bafe-610ac39b0b48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722221004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1722221004
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1559791929
Short name T280
Test name
Test status
Simulation time 167576528 ps
CPU time 8.4 seconds
Started Jul 21 05:00:15 PM PDT 24
Finished Jul 21 05:00:24 PM PDT 24
Peak memory 217096 kb
Host smart-ccbec7e5-f04e-40fc-940d-90ec31f90b2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559791929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1559791929
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2308513181
Short name T346
Test name
Test status
Simulation time 1906460849 ps
CPU time 165.29 seconds
Started Jul 21 05:00:05 PM PDT 24
Finished Jul 21 05:02:50 PM PDT 24
Peak memory 237188 kb
Host smart-82259db9-e1d3-4d0b-b7c3-0c2da4603f8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308513181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2308513181
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.859957964
Short name T235
Test name
Test status
Simulation time 7852066195 ps
CPU time 62.89 seconds
Started Jul 21 05:00:12 PM PDT 24
Finished Jul 21 05:01:15 PM PDT 24
Peak memory 219236 kb
Host smart-3e2cc3a3-9439-4864-8f6f-bd1a68ea15b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859957964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.859957964
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.598968128
Short name T219
Test name
Test status
Simulation time 5662650517 ps
CPU time 23.99 seconds
Started Jul 21 05:00:07 PM PDT 24
Finished Jul 21 05:00:31 PM PDT 24
Peak memory 211884 kb
Host smart-f390a018-14ae-4a2a-b0b0-89133e30ee91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=598968128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.598968128
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1709416618
Short name T48
Test name
Test status
Simulation time 425362653 ps
CPU time 19.67 seconds
Started Jul 21 05:00:05 PM PDT 24
Finished Jul 21 05:00:25 PM PDT 24
Peak memory 217952 kb
Host smart-6210cff0-fa1c-4166-a46d-f9f0bdcc09e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709416618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1709416618
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3712645038
Short name T252
Test name
Test status
Simulation time 1975013900 ps
CPU time 34.46 seconds
Started Jul 21 05:00:05 PM PDT 24
Finished Jul 21 05:00:40 PM PDT 24
Peak memory 216812 kb
Host smart-610b19a4-a0f5-4d88-9b20-71dda8c8bb45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712645038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3712645038
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2822357388
Short name T95
Test name
Test status
Simulation time 5216072508 ps
CPU time 16.25 seconds
Started Jul 21 05:00:21 PM PDT 24
Finished Jul 21 05:00:37 PM PDT 24
Peak memory 213292 kb
Host smart-2f4d4df6-9785-47c4-813f-2e6761deb436
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822357388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2822357388
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2696161722
Short name T110
Test name
Test status
Simulation time 3232522857 ps
CPU time 172.18 seconds
Started Jul 21 05:00:17 PM PDT 24
Finished Jul 21 05:03:09 PM PDT 24
Peak memory 238740 kb
Host smart-067719a9-2cd5-49cf-bf3b-0c36562b900c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696161722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2696161722
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.58721136
Short name T163
Test name
Test status
Simulation time 10768030091 ps
CPU time 64.56 seconds
Started Jul 21 05:00:18 PM PDT 24
Finished Jul 21 05:01:23 PM PDT 24
Peak memory 219316 kb
Host smart-471cdad8-5821-4fe4-b94d-9ab72a023bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58721136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.58721136
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.409361757
Short name T184
Test name
Test status
Simulation time 2501721072 ps
CPU time 22.91 seconds
Started Jul 21 05:00:11 PM PDT 24
Finished Jul 21 05:00:34 PM PDT 24
Peak memory 211144 kb
Host smart-6870bb41-7ad3-44c9-9ef2-12b3596759e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=409361757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.409361757
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.587997922
Short name T296
Test name
Test status
Simulation time 19710358795 ps
CPU time 44.36 seconds
Started Jul 21 05:00:15 PM PDT 24
Finished Jul 21 05:01:00 PM PDT 24
Peak memory 216892 kb
Host smart-5e2abdfe-2c98-44aa-ad66-2bcbbf096adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587997922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.587997922
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2261639528
Short name T304
Test name
Test status
Simulation time 15967140083 ps
CPU time 134.71 seconds
Started Jul 21 05:00:13 PM PDT 24
Finished Jul 21 05:02:27 PM PDT 24
Peak memory 230516 kb
Host smart-148cfa79-be32-4f14-bf0c-07e18f9c937b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261639528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2261639528
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2617726913
Short name T57
Test name
Test status
Simulation time 50360602816 ps
CPU time 1929.06 seconds
Started Jul 21 05:00:17 PM PDT 24
Finished Jul 21 05:32:26 PM PDT 24
Peak memory 236788 kb
Host smart-46deee6e-a88b-4956-9aad-2478c7e22c04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617726913 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.2617726913
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3320995468
Short name T159
Test name
Test status
Simulation time 2889797049 ps
CPU time 25.55 seconds
Started Jul 21 05:00:19 PM PDT 24
Finished Jul 21 05:00:45 PM PDT 24
Peak memory 217076 kb
Host smart-25914792-8129-43fa-959a-10966d684d55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320995468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3320995468
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3814330929
Short name T147
Test name
Test status
Simulation time 30329225803 ps
CPU time 534 seconds
Started Jul 21 05:00:17 PM PDT 24
Finished Jul 21 05:09:12 PM PDT 24
Peak memory 233700 kb
Host smart-564899a6-d3fd-4259-b718-99a98c7cd2a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814330929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3814330929
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.660488559
Short name T30
Test name
Test status
Simulation time 12564766599 ps
CPU time 68 seconds
Started Jul 21 05:00:18 PM PDT 24
Finished Jul 21 05:01:26 PM PDT 24
Peak memory 219268 kb
Host smart-d156a7fb-8337-4052-9380-da5e674ad23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660488559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.660488559
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3126942857
Short name T174
Test name
Test status
Simulation time 3069279478 ps
CPU time 27.15 seconds
Started Jul 21 05:00:17 PM PDT 24
Finished Jul 21 05:00:45 PM PDT 24
Peak memory 219308 kb
Host smart-8d2ea185-08c9-495c-b476-9bea9d20ae24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3126942857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3126942857
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.304821698
Short name T242
Test name
Test status
Simulation time 6368234667 ps
CPU time 41.33 seconds
Started Jul 21 05:00:18 PM PDT 24
Finished Jul 21 05:01:00 PM PDT 24
Peak memory 216864 kb
Host smart-b4d447ee-0f9c-40e3-af8d-c6af5c204062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304821698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.304821698
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3710533996
Short name T145
Test name
Test status
Simulation time 7941281544 ps
CPU time 81.52 seconds
Started Jul 21 05:00:19 PM PDT 24
Finished Jul 21 05:01:40 PM PDT 24
Peak memory 219272 kb
Host smart-68546788-05fe-42cf-bf68-e79431787295
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710533996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3710533996
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2022593227
Short name T68
Test name
Test status
Simulation time 5020879752 ps
CPU time 21.64 seconds
Started Jul 21 05:00:24 PM PDT 24
Finished Jul 21 05:00:46 PM PDT 24
Peak memory 217392 kb
Host smart-f34cb197-87eb-4466-8c15-64a73c9d8d74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022593227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2022593227
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2314897025
Short name T283
Test name
Test status
Simulation time 111175618976 ps
CPU time 376.8 seconds
Started Jul 21 05:00:24 PM PDT 24
Finished Jul 21 05:06:41 PM PDT 24
Peak memory 219416 kb
Host smart-bf721773-8c71-4630-89aa-71eab64cc6a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314897025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2314897025
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.992527869
Short name T50
Test name
Test status
Simulation time 59111030730 ps
CPU time 58.72 seconds
Started Jul 21 05:00:24 PM PDT 24
Finished Jul 21 05:01:23 PM PDT 24
Peak memory 219304 kb
Host smart-9d783cb2-c0ca-4b16-851d-6e156ed1535c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992527869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.992527869
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.4020913288
Short name T146
Test name
Test status
Simulation time 3141832744 ps
CPU time 23.35 seconds
Started Jul 21 05:00:18 PM PDT 24
Finished Jul 21 05:00:42 PM PDT 24
Peak memory 219308 kb
Host smart-d04c81eb-c35a-4e42-8ff5-c61c6fbfdde7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4020913288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.4020913288
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2765569682
Short name T303
Test name
Test status
Simulation time 1386709668 ps
CPU time 30.63 seconds
Started Jul 21 05:00:18 PM PDT 24
Finished Jul 21 05:00:49 PM PDT 24
Peak memory 216312 kb
Host smart-db784b16-f423-44b3-91b1-7431d32e09da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765569682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2765569682
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2169791971
Short name T186
Test name
Test status
Simulation time 37855298958 ps
CPU time 117.09 seconds
Started Jul 21 05:00:17 PM PDT 24
Finished Jul 21 05:02:15 PM PDT 24
Peak memory 227580 kb
Host smart-c899a710-5075-4bb9-99ce-1d0503263777
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169791971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2169791971
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.4208243081
Short name T58
Test name
Test status
Simulation time 50547027432 ps
CPU time 1093.4 seconds
Started Jul 21 05:00:24 PM PDT 24
Finished Jul 21 05:18:38 PM PDT 24
Peak memory 235708 kb
Host smart-c5bde6bb-bbb0-40cc-a4a0-1795e0ed9877
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208243081 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.4208243081
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1138646632
Short name T330
Test name
Test status
Simulation time 7151886354 ps
CPU time 25.08 seconds
Started Jul 21 05:00:30 PM PDT 24
Finished Jul 21 05:00:55 PM PDT 24
Peak memory 213228 kb
Host smart-b67bc7eb-10c3-43d8-92a7-b6d3966bf092
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138646632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1138646632
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.760367017
Short name T208
Test name
Test status
Simulation time 120509674811 ps
CPU time 655.13 seconds
Started Jul 21 05:00:24 PM PDT 24
Finished Jul 21 05:11:19 PM PDT 24
Peak memory 225820 kb
Host smart-e5ec2dca-eb1c-41a6-9f3b-ae4aca089060
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760367017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.760367017
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1553089400
Short name T135
Test name
Test status
Simulation time 3766879933 ps
CPU time 43.47 seconds
Started Jul 21 05:00:25 PM PDT 24
Finished Jul 21 05:01:09 PM PDT 24
Peak memory 219268 kb
Host smart-a121e274-45b1-43c1-8d41-9f6947dadd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553089400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1553089400
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3706813700
Short name T169
Test name
Test status
Simulation time 32143967965 ps
CPU time 33.36 seconds
Started Jul 21 05:00:26 PM PDT 24
Finished Jul 21 05:01:00 PM PDT 24
Peak memory 211908 kb
Host smart-5f0cd20c-c83b-47eb-8516-33b5221e529d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3706813700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3706813700
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3659020962
Short name T313
Test name
Test status
Simulation time 7234479148 ps
CPU time 67.2 seconds
Started Jul 21 05:00:22 PM PDT 24
Finished Jul 21 05:01:30 PM PDT 24
Peak memory 216496 kb
Host smart-8bf857a0-8816-48b6-892a-30e636ce5031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659020962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3659020962
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.484387867
Short name T124
Test name
Test status
Simulation time 3568446141 ps
CPU time 51.76 seconds
Started Jul 21 05:00:25 PM PDT 24
Finished Jul 21 05:01:17 PM PDT 24
Peak memory 219728 kb
Host smart-9e40fbce-7673-4b21-92fe-0485e9384682
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484387867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.rom_ctrl_stress_all.484387867
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.4083810998
Short name T344
Test name
Test status
Simulation time 16710769248 ps
CPU time 34.15 seconds
Started Jul 21 05:00:33 PM PDT 24
Finished Jul 21 05:01:07 PM PDT 24
Peak memory 213288 kb
Host smart-823664c3-540d-46a5-bf89-d95025834344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083810998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.4083810998
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1231683687
Short name T245
Test name
Test status
Simulation time 89492214858 ps
CPU time 971.87 seconds
Started Jul 21 05:00:31 PM PDT 24
Finished Jul 21 05:16:44 PM PDT 24
Peak memory 235724 kb
Host smart-81f51865-716b-42b6-9383-0ebfeb5eb4a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231683687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1231683687
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.377846295
Short name T254
Test name
Test status
Simulation time 4136466883 ps
CPU time 44.04 seconds
Started Jul 21 05:00:34 PM PDT 24
Finished Jul 21 05:01:19 PM PDT 24
Peak memory 219276 kb
Host smart-b6e144b3-6be1-4831-8a40-18f46af5643e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377846295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.377846295
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.4178912409
Short name T182
Test name
Test status
Simulation time 693359703 ps
CPU time 10.26 seconds
Started Jul 21 05:00:31 PM PDT 24
Finished Jul 21 05:00:42 PM PDT 24
Peak memory 219232 kb
Host smart-2c8e78eb-a209-4b7b-b3b7-6f3d5e11e9fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4178912409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.4178912409
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2979002567
Short name T180
Test name
Test status
Simulation time 32823027848 ps
CPU time 64.78 seconds
Started Jul 21 05:00:32 PM PDT 24
Finished Jul 21 05:01:37 PM PDT 24
Peak memory 218156 kb
Host smart-8c90df01-7b9f-4aa0-a8fc-ac3772edad1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979002567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2979002567
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3931338472
Short name T308
Test name
Test status
Simulation time 41143861985 ps
CPU time 208.89 seconds
Started Jul 21 05:00:32 PM PDT 24
Finished Jul 21 05:04:01 PM PDT 24
Peak memory 219348 kb
Host smart-b3c6cc99-ac4d-469f-864f-18b753908fd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931338472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3931338472
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1931007722
Short name T12
Test name
Test status
Simulation time 59665254871 ps
CPU time 2508.62 seconds
Started Jul 21 05:00:31 PM PDT 24
Finished Jul 21 05:42:21 PM PDT 24
Peak memory 244992 kb
Host smart-edb2447e-6805-40ed-beeb-fbc9f910e579
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931007722 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.1931007722
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1103846599
Short name T72
Test name
Test status
Simulation time 2111524329 ps
CPU time 21.66 seconds
Started Jul 21 04:58:50 PM PDT 24
Finished Jul 21 04:59:13 PM PDT 24
Peak memory 216524 kb
Host smart-57f05307-0c54-482a-b705-f60f4bfa637c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103846599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1103846599
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2588328222
Short name T217
Test name
Test status
Simulation time 7039219598 ps
CPU time 215.93 seconds
Started Jul 21 04:58:50 PM PDT 24
Finished Jul 21 05:02:26 PM PDT 24
Peak memory 240772 kb
Host smart-6fd948ec-974f-4800-a144-4f650d4492df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588328222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2588328222
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2762249646
Short name T251
Test name
Test status
Simulation time 17730619588 ps
CPU time 56.83 seconds
Started Jul 21 04:58:53 PM PDT 24
Finished Jul 21 04:59:50 PM PDT 24
Peak memory 219204 kb
Host smart-1fd71280-cd4f-477e-8116-4c643f29ca78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762249646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2762249646
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1442794396
Short name T123
Test name
Test status
Simulation time 9371183907 ps
CPU time 25.78 seconds
Started Jul 21 04:58:51 PM PDT 24
Finished Jul 21 04:59:17 PM PDT 24
Peak memory 211820 kb
Host smart-d8908d87-9e9e-4f84-91f4-d7c66df240ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1442794396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1442794396
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2846443428
Short name T22
Test name
Test status
Simulation time 2773190909 ps
CPU time 219.2 seconds
Started Jul 21 04:58:50 PM PDT 24
Finished Jul 21 05:02:30 PM PDT 24
Peak memory 238156 kb
Host smart-5c951358-36ef-4115-8169-7a63e9fce702
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846443428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2846443428
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1127116728
Short name T263
Test name
Test status
Simulation time 6831538371 ps
CPU time 57.99 seconds
Started Jul 21 04:58:50 PM PDT 24
Finished Jul 21 04:59:49 PM PDT 24
Peak memory 217608 kb
Host smart-ea694327-ef55-48fd-8332-a664ec36897f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127116728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1127116728
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.4294708061
Short name T228
Test name
Test status
Simulation time 10863994245 ps
CPU time 103.59 seconds
Started Jul 21 04:58:50 PM PDT 24
Finished Jul 21 05:00:34 PM PDT 24
Peak memory 219248 kb
Host smart-ec98d435-dcca-4177-9099-8cb50d67d498
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294708061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.4294708061
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1587620525
Short name T69
Test name
Test status
Simulation time 3145750861 ps
CPU time 26.63 seconds
Started Jul 21 05:00:30 PM PDT 24
Finished Jul 21 05:00:57 PM PDT 24
Peak memory 217172 kb
Host smart-a55d83c7-b341-43b5-9be3-de862e090bb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587620525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1587620525
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2432578917
Short name T100
Test name
Test status
Simulation time 81111429111 ps
CPU time 302.43 seconds
Started Jul 21 05:00:30 PM PDT 24
Finished Jul 21 05:05:33 PM PDT 24
Peak memory 235744 kb
Host smart-5f6124c8-974e-496c-a113-0a61903807f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432578917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2432578917
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1992681833
Short name T150
Test name
Test status
Simulation time 9849993523 ps
CPU time 26.76 seconds
Started Jul 21 05:00:36 PM PDT 24
Finished Jul 21 05:01:03 PM PDT 24
Peak memory 219276 kb
Host smart-e8d62d61-60b2-4e0d-bb25-1d6e7a85ee15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992681833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1992681833
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.577240669
Short name T33
Test name
Test status
Simulation time 3583579066 ps
CPU time 14.49 seconds
Started Jul 21 05:00:31 PM PDT 24
Finished Jul 21 05:00:46 PM PDT 24
Peak memory 219300 kb
Host smart-d30c87ce-1e0a-4dd5-ad3a-59ff69b10184
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=577240669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.577240669
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3036371322
Short name T334
Test name
Test status
Simulation time 9192364014 ps
CPU time 114.59 seconds
Started Jul 21 05:00:30 PM PDT 24
Finished Jul 21 05:02:25 PM PDT 24
Peak memory 219380 kb
Host smart-c9fee1f2-52f5-4412-b5cf-f11ce875d9fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036371322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3036371322
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3410691997
Short name T305
Test name
Test status
Simulation time 70434247912 ps
CPU time 652.74 seconds
Started Jul 21 05:00:36 PM PDT 24
Finished Jul 21 05:11:29 PM PDT 24
Peak memory 234372 kb
Host smart-3ef262b3-f5c8-44da-b6bc-215127136ae1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410691997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3410691997
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.145499043
Short name T270
Test name
Test status
Simulation time 2429026951 ps
CPU time 29.61 seconds
Started Jul 21 05:00:37 PM PDT 24
Finished Jul 21 05:01:07 PM PDT 24
Peak memory 218764 kb
Host smart-5348a171-576a-44b1-827e-9877258c36e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145499043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.145499043
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2129727121
Short name T168
Test name
Test status
Simulation time 10253731141 ps
CPU time 25.12 seconds
Started Jul 21 05:00:37 PM PDT 24
Finished Jul 21 05:01:02 PM PDT 24
Peak memory 219276 kb
Host smart-cd5cfbb8-3bb8-41cb-ad0b-36b504bff493
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2129727121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2129727121
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3774805872
Short name T253
Test name
Test status
Simulation time 76044453605 ps
CPU time 64.19 seconds
Started Jul 21 05:00:31 PM PDT 24
Finished Jul 21 05:01:35 PM PDT 24
Peak memory 216892 kb
Host smart-330bb5d5-4a61-458c-91ee-319989ef1f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774805872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3774805872
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1111760018
Short name T221
Test name
Test status
Simulation time 15134537573 ps
CPU time 146.33 seconds
Started Jul 21 05:00:29 PM PDT 24
Finished Jul 21 05:02:56 PM PDT 24
Peak memory 220796 kb
Host smart-7bede04e-d96b-4b97-b873-272363d00ceb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111760018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1111760018
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1937885488
Short name T347
Test name
Test status
Simulation time 687881059 ps
CPU time 8.42 seconds
Started Jul 21 05:00:37 PM PDT 24
Finished Jul 21 05:00:46 PM PDT 24
Peak memory 217136 kb
Host smart-3d979355-9cc9-41d6-a321-ea7169b81b6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937885488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1937885488
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2632533041
Short name T202
Test name
Test status
Simulation time 50416541709 ps
CPU time 218.49 seconds
Started Jul 21 05:00:35 PM PDT 24
Finished Jul 21 05:04:14 PM PDT 24
Peak memory 238056 kb
Host smart-250daea3-89b5-484b-a7f1-96d6af3d8903
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632533041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2632533041
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.752678511
Short name T197
Test name
Test status
Simulation time 28188814507 ps
CPU time 60.31 seconds
Started Jul 21 05:00:38 PM PDT 24
Finished Jul 21 05:01:38 PM PDT 24
Peak memory 219344 kb
Host smart-d18f5700-5f1b-4bac-9733-1127467ce3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752678511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.752678511
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3581499762
Short name T176
Test name
Test status
Simulation time 5285968424 ps
CPU time 30.6 seconds
Started Jul 21 05:00:35 PM PDT 24
Finished Jul 21 05:01:06 PM PDT 24
Peak memory 219276 kb
Host smart-6d94e431-828e-4b60-a332-f8b15c9ee91d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3581499762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3581499762
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.296474046
Short name T35
Test name
Test status
Simulation time 4143077715 ps
CPU time 50.61 seconds
Started Jul 21 05:00:36 PM PDT 24
Finished Jul 21 05:01:27 PM PDT 24
Peak memory 216248 kb
Host smart-3dd6566e-0e83-49cf-b078-2e7cfe7da8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296474046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.296474046
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3523781633
Short name T102
Test name
Test status
Simulation time 13899252570 ps
CPU time 70.93 seconds
Started Jul 21 05:00:37 PM PDT 24
Finished Jul 21 05:01:48 PM PDT 24
Peak memory 219268 kb
Host smart-2c34b7e4-ff3f-4007-aace-6fc087646e5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523781633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3523781633
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.4247250966
Short name T223
Test name
Test status
Simulation time 1966888816 ps
CPU time 18.27 seconds
Started Jul 21 05:00:43 PM PDT 24
Finished Jul 21 05:01:01 PM PDT 24
Peak memory 213168 kb
Host smart-dbaae3de-b4da-48e7-b6a6-a92bb8c955fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247250966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.4247250966
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.500177166
Short name T213
Test name
Test status
Simulation time 215333878965 ps
CPU time 560.46 seconds
Started Jul 21 05:00:47 PM PDT 24
Finished Jul 21 05:10:08 PM PDT 24
Peak memory 237932 kb
Host smart-a7ca6e85-069c-484b-86fe-56cfc8a4413d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500177166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.500177166
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2638397760
Short name T5
Test name
Test status
Simulation time 1032967071 ps
CPU time 19.15 seconds
Started Jul 21 05:00:48 PM PDT 24
Finished Jul 21 05:01:08 PM PDT 24
Peak memory 219236 kb
Host smart-9ca9782a-b1fb-4b03-b297-dd11c52b3b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638397760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2638397760
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2928375294
Short name T261
Test name
Test status
Simulation time 7908246092 ps
CPU time 36.28 seconds
Started Jul 21 05:00:41 PM PDT 24
Finished Jul 21 05:01:17 PM PDT 24
Peak memory 219248 kb
Host smart-df8a5ab0-19a5-4568-b5c2-475bf7359471
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2928375294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2928375294
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2524665140
Short name T83
Test name
Test status
Simulation time 14059745362 ps
CPU time 45.51 seconds
Started Jul 21 05:00:36 PM PDT 24
Finished Jul 21 05:01:21 PM PDT 24
Peak memory 216984 kb
Host smart-7a7fc4d4-7997-4142-a518-c7ca759196d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524665140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2524665140
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.102206438
Short name T297
Test name
Test status
Simulation time 371705649 ps
CPU time 21.31 seconds
Started Jul 21 05:00:41 PM PDT 24
Finished Jul 21 05:01:02 PM PDT 24
Peak memory 219080 kb
Host smart-e7441429-f228-4b47-b82b-22bf76d4f857
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102206438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.102206438
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1468664286
Short name T172
Test name
Test status
Simulation time 2340755693 ps
CPU time 21.03 seconds
Started Jul 21 05:00:47 PM PDT 24
Finished Jul 21 05:01:08 PM PDT 24
Peak memory 213288 kb
Host smart-e314c726-e86d-4b57-90b7-1903bb2ca44e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468664286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1468664286
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3987727308
Short name T46
Test name
Test status
Simulation time 405554120120 ps
CPU time 978.76 seconds
Started Jul 21 05:00:47 PM PDT 24
Finished Jul 21 05:17:06 PM PDT 24
Peak memory 236140 kb
Host smart-3558365c-600b-4822-81a3-bc5db66e551a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987727308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3987727308
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3013150524
Short name T137
Test name
Test status
Simulation time 12543349930 ps
CPU time 50.56 seconds
Started Jul 21 05:00:47 PM PDT 24
Finished Jul 21 05:01:39 PM PDT 24
Peak memory 219272 kb
Host smart-eda1731c-7ef2-4d5a-8b13-59a42df2235a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013150524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3013150524
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3162453663
Short name T203
Test name
Test status
Simulation time 12144792190 ps
CPU time 28.57 seconds
Started Jul 21 05:00:46 PM PDT 24
Finished Jul 21 05:01:15 PM PDT 24
Peak memory 219312 kb
Host smart-61f414e2-be25-4a0c-9146-8f2c506abfa7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3162453663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3162453663
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2856805303
Short name T317
Test name
Test status
Simulation time 2111149241 ps
CPU time 23.94 seconds
Started Jul 21 05:00:45 PM PDT 24
Finished Jul 21 05:01:09 PM PDT 24
Peak memory 217016 kb
Host smart-d6c5ca57-c859-45b4-98f7-bc3f40728046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856805303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2856805303
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1904666396
Short name T266
Test name
Test status
Simulation time 21797363267 ps
CPU time 125.29 seconds
Started Jul 21 05:00:39 PM PDT 24
Finished Jul 21 05:02:45 PM PDT 24
Peak memory 219280 kb
Host smart-2e20be3b-7084-4d4e-8976-d7f7d5225439
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904666396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1904666396
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3739447574
Short name T195
Test name
Test status
Simulation time 2576482120 ps
CPU time 23.82 seconds
Started Jul 21 05:00:52 PM PDT 24
Finished Jul 21 05:01:16 PM PDT 24
Peak memory 213284 kb
Host smart-bf65b229-411c-44f2-adde-c5eedfd2a51b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739447574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3739447574
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.80626502
Short name T274
Test name
Test status
Simulation time 9515533465 ps
CPU time 331.07 seconds
Started Jul 21 05:00:51 PM PDT 24
Finished Jul 21 05:06:22 PM PDT 24
Peak memory 225880 kb
Host smart-a06eea64-c6c0-4141-a8fd-e78aff32c57e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80626502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_co
rrupt_sig_fatal_chk.80626502
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1635580393
Short name T333
Test name
Test status
Simulation time 5474175915 ps
CPU time 26.04 seconds
Started Jul 21 05:00:59 PM PDT 24
Finished Jul 21 05:01:25 PM PDT 24
Peak memory 219208 kb
Host smart-77f202dc-9725-4250-a818-e6872e1023e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635580393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1635580393
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2603067386
Short name T284
Test name
Test status
Simulation time 7753910069 ps
CPU time 29.36 seconds
Started Jul 21 05:00:59 PM PDT 24
Finished Jul 21 05:01:29 PM PDT 24
Peak memory 211432 kb
Host smart-2d1df10d-5468-45b2-b720-9f06da29ed75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2603067386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2603067386
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3205985525
Short name T127
Test name
Test status
Simulation time 364896661 ps
CPU time 19.72 seconds
Started Jul 21 05:00:46 PM PDT 24
Finished Jul 21 05:01:06 PM PDT 24
Peak memory 215692 kb
Host smart-7c1a197c-ca7f-4a8d-bcbe-cd1e9ddb7866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205985525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3205985525
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2820486408
Short name T130
Test name
Test status
Simulation time 1111772932 ps
CPU time 31.02 seconds
Started Jul 21 05:00:46 PM PDT 24
Finished Jul 21 05:01:18 PM PDT 24
Peak memory 219260 kb
Host smart-8efa436d-5abe-479f-931a-db619ae007dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820486408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2820486408
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1706689361
Short name T335
Test name
Test status
Simulation time 4458727489 ps
CPU time 32 seconds
Started Jul 21 05:00:59 PM PDT 24
Finished Jul 21 05:01:31 PM PDT 24
Peak memory 217308 kb
Host smart-263077da-d96e-4b72-a6f6-73efd84b6742
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706689361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1706689361
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.563576694
Short name T40
Test name
Test status
Simulation time 22739433176 ps
CPU time 387.38 seconds
Started Jul 21 05:00:48 PM PDT 24
Finished Jul 21 05:07:17 PM PDT 24
Peak memory 239028 kb
Host smart-bedeabc9-a257-410a-9228-bb21cfb165c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563576694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.563576694
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1792280747
Short name T15
Test name
Test status
Simulation time 2099149796 ps
CPU time 31.82 seconds
Started Jul 21 05:00:48 PM PDT 24
Finished Jul 21 05:01:21 PM PDT 24
Peak memory 219208 kb
Host smart-bf2f6894-140e-46ba-8d08-7dfbb6785a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792280747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1792280747
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.156504740
Short name T240
Test name
Test status
Simulation time 12303519284 ps
CPU time 31.2 seconds
Started Jul 21 05:00:48 PM PDT 24
Finished Jul 21 05:01:20 PM PDT 24
Peak memory 211556 kb
Host smart-ef33ce2f-e977-413d-b5ab-4f6e7fa6b020
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=156504740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.156504740
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3761757498
Short name T52
Test name
Test status
Simulation time 23162990438 ps
CPU time 36.54 seconds
Started Jul 21 05:00:48 PM PDT 24
Finished Jul 21 05:01:25 PM PDT 24
Peak memory 217380 kb
Host smart-6b73f9cb-5a6e-45ba-aa73-0e144d5ffffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761757498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3761757498
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.904104912
Short name T178
Test name
Test status
Simulation time 14157376271 ps
CPU time 142.09 seconds
Started Jul 21 05:00:47 PM PDT 24
Finished Jul 21 05:03:10 PM PDT 24
Peak memory 220512 kb
Host smart-6ee804b3-cb9f-46d6-b7a4-50e230874262
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904104912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.904104912
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.26967044
Short name T269
Test name
Test status
Simulation time 14035543602 ps
CPU time 30.17 seconds
Started Jul 21 05:01:04 PM PDT 24
Finished Jul 21 05:01:35 PM PDT 24
Peak memory 217448 kb
Host smart-03d37ea5-4a57-407f-a8c9-f3b07cf4cd69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26967044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.26967044
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2898923193
Short name T185
Test name
Test status
Simulation time 3369079776 ps
CPU time 201.83 seconds
Started Jul 21 05:00:53 PM PDT 24
Finished Jul 21 05:04:15 PM PDT 24
Peak memory 219344 kb
Host smart-7a62b9e1-46e2-4d7c-b309-8757bc39e9b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898923193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2898923193
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1444583835
Short name T166
Test name
Test status
Simulation time 35465535274 ps
CPU time 46.14 seconds
Started Jul 21 05:00:54 PM PDT 24
Finished Jul 21 05:01:40 PM PDT 24
Peak memory 219324 kb
Host smart-b22b3c6d-5f7a-46b5-a3b2-2b3487687db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444583835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1444583835
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1948648818
Short name T6
Test name
Test status
Simulation time 5501862162 ps
CPU time 16.29 seconds
Started Jul 21 05:00:59 PM PDT 24
Finished Jul 21 05:01:16 PM PDT 24
Peak memory 219024 kb
Host smart-153105f9-aec9-4b85-9f5f-9bb446d8b662
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1948648818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1948648818
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3116423825
Short name T152
Test name
Test status
Simulation time 8400623869 ps
CPU time 63.53 seconds
Started Jul 21 05:00:53 PM PDT 24
Finished Jul 21 05:01:57 PM PDT 24
Peak memory 216588 kb
Host smart-d7944dc7-3693-414f-9208-c525e35cf5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116423825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3116423825
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1002783806
Short name T342
Test name
Test status
Simulation time 13665669065 ps
CPU time 119.03 seconds
Started Jul 21 05:00:48 PM PDT 24
Finished Jul 21 05:02:48 PM PDT 24
Peak memory 219280 kb
Host smart-ff1ce5ca-d457-4090-908d-d769dc713abb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002783806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1002783806
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.4120554903
Short name T148
Test name
Test status
Simulation time 29856037980 ps
CPU time 27.79 seconds
Started Jul 21 05:00:52 PM PDT 24
Finished Jul 21 05:01:20 PM PDT 24
Peak memory 217364 kb
Host smart-d23fa4fd-e8ab-4770-85f3-de04068aadee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120554903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.4120554903
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.747960949
Short name T160
Test name
Test status
Simulation time 17749035690 ps
CPU time 115.42 seconds
Started Jul 21 05:00:53 PM PDT 24
Finished Jul 21 05:02:49 PM PDT 24
Peak memory 229624 kb
Host smart-ffc0c02a-05b2-4fcc-9bce-a5196a93ef7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747960949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.747960949
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3233216236
Short name T230
Test name
Test status
Simulation time 674313955 ps
CPU time 18.94 seconds
Started Jul 21 05:01:01 PM PDT 24
Finished Jul 21 05:01:20 PM PDT 24
Peak memory 219124 kb
Host smart-146514fa-664f-43ec-87ed-add1cf6c382e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233216236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3233216236
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2264829887
Short name T187
Test name
Test status
Simulation time 9891348608 ps
CPU time 23.01 seconds
Started Jul 21 05:00:52 PM PDT 24
Finished Jul 21 05:01:15 PM PDT 24
Peak memory 219348 kb
Host smart-671874da-3309-467f-b5aa-0e0d82be4307
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2264829887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2264829887
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3745546042
Short name T2
Test name
Test status
Simulation time 6584207911 ps
CPU time 67.93 seconds
Started Jul 21 05:00:52 PM PDT 24
Finished Jul 21 05:02:01 PM PDT 24
Peak memory 216848 kb
Host smart-d195624f-d947-4f1b-9f40-2f47cb88a8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745546042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3745546042
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2639614736
Short name T215
Test name
Test status
Simulation time 5224567127 ps
CPU time 56 seconds
Started Jul 21 05:00:53 PM PDT 24
Finished Jul 21 05:01:50 PM PDT 24
Peak memory 219380 kb
Host smart-e8ef7277-c66a-4f4e-91f6-56447fbe1bc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639614736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2639614736
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1932300739
Short name T290
Test name
Test status
Simulation time 694603881 ps
CPU time 13.04 seconds
Started Jul 21 05:01:00 PM PDT 24
Finished Jul 21 05:01:13 PM PDT 24
Peak memory 216988 kb
Host smart-8dbe77a3-e5f3-4182-bb0a-6ddea6e81e61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932300739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1932300739
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.53537579
Short name T279
Test name
Test status
Simulation time 65942007196 ps
CPU time 718.69 seconds
Started Jul 21 05:00:59 PM PDT 24
Finished Jul 21 05:12:58 PM PDT 24
Peak memory 234716 kb
Host smart-04754492-4489-484e-9734-57f715436e77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53537579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_co
rrupt_sig_fatal_chk.53537579
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3920602830
Short name T227
Test name
Test status
Simulation time 16434190103 ps
CPU time 45.77 seconds
Started Jul 21 05:00:59 PM PDT 24
Finished Jul 21 05:01:46 PM PDT 24
Peak memory 219264 kb
Host smart-3d97a758-1f7a-462d-9868-c2fa45dc98b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920602830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3920602830
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3380071287
Short name T173
Test name
Test status
Simulation time 3978763086 ps
CPU time 16.74 seconds
Started Jul 21 05:01:01 PM PDT 24
Finished Jul 21 05:01:18 PM PDT 24
Peak memory 219300 kb
Host smart-f71b8b00-10c0-40d1-95c9-5784e6aca687
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3380071287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3380071287
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.3174780808
Short name T8
Test name
Test status
Simulation time 4868479416 ps
CPU time 53.28 seconds
Started Jul 21 05:01:01 PM PDT 24
Finished Jul 21 05:01:55 PM PDT 24
Peak memory 216992 kb
Host smart-9aac3172-7ebd-4067-ae9a-519d3facbcba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174780808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.3174780808
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.249035680
Short name T238
Test name
Test status
Simulation time 2694574033 ps
CPU time 24.72 seconds
Started Jul 21 05:01:01 PM PDT 24
Finished Jul 21 05:01:26 PM PDT 24
Peak memory 219404 kb
Host smart-b90cb554-c2ca-483f-8716-2b96aa442f8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249035680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.249035680
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3023588381
Short name T277
Test name
Test status
Simulation time 7124149783 ps
CPU time 18.94 seconds
Started Jul 21 04:58:55 PM PDT 24
Finished Jul 21 04:59:15 PM PDT 24
Peak memory 213260 kb
Host smart-4bceaa0b-70ce-47ad-8259-bb49c0d6ac59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023588381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3023588381
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1799826711
Short name T134
Test name
Test status
Simulation time 6126680597 ps
CPU time 36.78 seconds
Started Jul 21 04:58:56 PM PDT 24
Finished Jul 21 04:59:33 PM PDT 24
Peak memory 219296 kb
Host smart-84222afd-f5ec-4199-9fa5-7b8ccbfecc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799826711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1799826711
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1499864620
Short name T51
Test name
Test status
Simulation time 10014849700 ps
CPU time 14.44 seconds
Started Jul 21 04:58:55 PM PDT 24
Finished Jul 21 04:59:10 PM PDT 24
Peak memory 219288 kb
Host smart-c424dca0-31b6-4051-b8bb-207a45ec02f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1499864620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1499864620
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1377890206
Short name T28
Test name
Test status
Simulation time 405106149 ps
CPU time 224.67 seconds
Started Jul 21 04:58:54 PM PDT 24
Finished Jul 21 05:02:39 PM PDT 24
Peak memory 238192 kb
Host smart-c9fc9da1-831c-4d7a-a05c-b770aee7efda
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377890206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1377890206
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3119971513
Short name T31
Test name
Test status
Simulation time 31151321557 ps
CPU time 36 seconds
Started Jul 21 04:58:55 PM PDT 24
Finished Jul 21 04:59:31 PM PDT 24
Peak memory 216376 kb
Host smart-699cb2ee-e6b3-4d1e-a0a1-83abc78138de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119971513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3119971513
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3888683066
Short name T200
Test name
Test status
Simulation time 31937030012 ps
CPU time 58.48 seconds
Started Jul 21 04:58:55 PM PDT 24
Finished Jul 21 04:59:54 PM PDT 24
Peak memory 218296 kb
Host smart-7a3e0e02-8e8c-4877-8be2-957e8248a59b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888683066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3888683066
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2041313346
Short name T71
Test name
Test status
Simulation time 15358085214 ps
CPU time 30.88 seconds
Started Jul 21 05:01:00 PM PDT 24
Finished Jul 21 05:01:31 PM PDT 24
Peak memory 213228 kb
Host smart-2e53b87a-763b-4878-88e1-c56068cc9537
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041313346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2041313346
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3094301772
Short name T267
Test name
Test status
Simulation time 19005872019 ps
CPU time 293.06 seconds
Started Jul 21 05:01:02 PM PDT 24
Finished Jul 21 05:05:55 PM PDT 24
Peak memory 237724 kb
Host smart-ad5e11a7-383d-4a1a-913d-b851d203b4b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094301772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3094301772
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.483957122
Short name T133
Test name
Test status
Simulation time 19329438511 ps
CPU time 45.71 seconds
Started Jul 21 05:00:59 PM PDT 24
Finished Jul 21 05:01:46 PM PDT 24
Peak memory 219312 kb
Host smart-bea2f1d1-64ca-4804-b3fe-960290d59e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483957122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.483957122
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2683355811
Short name T17
Test name
Test status
Simulation time 179595551 ps
CPU time 10.23 seconds
Started Jul 21 05:01:00 PM PDT 24
Finished Jul 21 05:01:11 PM PDT 24
Peak memory 219216 kb
Host smart-002a8062-ffa4-4e80-b3db-ac87429f34b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2683355811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2683355811
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1371381116
Short name T348
Test name
Test status
Simulation time 700160615 ps
CPU time 20.12 seconds
Started Jul 21 05:01:02 PM PDT 24
Finished Jul 21 05:01:22 PM PDT 24
Peak memory 215780 kb
Host smart-ceebc24d-23d8-4a5f-a66b-0322f0315b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371381116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1371381116
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1345020024
Short name T14
Test name
Test status
Simulation time 736603223 ps
CPU time 20.2 seconds
Started Jul 21 05:01:02 PM PDT 24
Finished Jul 21 05:01:22 PM PDT 24
Peak memory 218716 kb
Host smart-341367ef-3f49-4d1a-9ba6-fdad54494d64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345020024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1345020024
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.581301515
Short name T332
Test name
Test status
Simulation time 7967850399 ps
CPU time 32.29 seconds
Started Jul 21 05:01:06 PM PDT 24
Finished Jul 21 05:01:39 PM PDT 24
Peak memory 213232 kb
Host smart-7211ab76-56c2-4911-894c-4fca07c73561
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581301515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.581301515
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.265566122
Short name T122
Test name
Test status
Simulation time 59787765408 ps
CPU time 351.4 seconds
Started Jul 21 05:01:09 PM PDT 24
Finished Jul 21 05:07:00 PM PDT 24
Peak memory 219508 kb
Host smart-c83216e2-92d1-44eb-acaf-6b57ffaecaa1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265566122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.265566122
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3227296035
Short name T249
Test name
Test status
Simulation time 31048249875 ps
CPU time 61.61 seconds
Started Jul 21 05:01:06 PM PDT 24
Finished Jul 21 05:02:08 PM PDT 24
Peak memory 219288 kb
Host smart-e9c15aa9-64e7-4e48-9283-832d3098fdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227296035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3227296035
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3244691081
Short name T316
Test name
Test status
Simulation time 186999363 ps
CPU time 10.4 seconds
Started Jul 21 05:01:00 PM PDT 24
Finished Jul 21 05:01:11 PM PDT 24
Peak memory 219176 kb
Host smart-d5749b15-f7a5-4f42-824f-4c3e5cb86da0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3244691081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3244691081
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.843116269
Short name T264
Test name
Test status
Simulation time 25555063406 ps
CPU time 79.93 seconds
Started Jul 21 05:00:59 PM PDT 24
Finished Jul 21 05:02:20 PM PDT 24
Peak memory 220000 kb
Host smart-fe3127c3-8307-4a02-9232-8c492737c9bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843116269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.843116269
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3770769827
Short name T59
Test name
Test status
Simulation time 124657834111 ps
CPU time 1155.11 seconds
Started Jul 21 05:01:07 PM PDT 24
Finished Jul 21 05:20:22 PM PDT 24
Peak memory 236240 kb
Host smart-16f668e3-4ca7-4c4d-8a32-eab81ec92011
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770769827 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.3770769827
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3480015039
Short name T216
Test name
Test status
Simulation time 500551894 ps
CPU time 11.65 seconds
Started Jul 21 05:01:07 PM PDT 24
Finished Jul 21 05:01:20 PM PDT 24
Peak memory 218236 kb
Host smart-e25443f3-4de5-4df4-a114-7f5821d51fc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480015039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3480015039
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.904315154
Short name T43
Test name
Test status
Simulation time 2868654117 ps
CPU time 206.89 seconds
Started Jul 21 05:01:08 PM PDT 24
Finished Jul 21 05:04:35 PM PDT 24
Peak memory 239788 kb
Host smart-b809cc6b-43a7-4462-b637-67d2d208d8e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904315154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.904315154
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2459364735
Short name T37
Test name
Test status
Simulation time 5344408455 ps
CPU time 49.34 seconds
Started Jul 21 05:01:06 PM PDT 24
Finished Jul 21 05:01:56 PM PDT 24
Peak memory 219252 kb
Host smart-92d2e873-d9d1-4815-9d74-7c743c20a5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459364735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2459364735
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3303298570
Short name T196
Test name
Test status
Simulation time 876599114 ps
CPU time 11.96 seconds
Started Jul 21 05:01:06 PM PDT 24
Finished Jul 21 05:01:18 PM PDT 24
Peak memory 219232 kb
Host smart-a03c162b-87f3-41a5-b91d-08de6b0dd79c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3303298570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3303298570
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2422484972
Short name T218
Test name
Test status
Simulation time 2969657736 ps
CPU time 41.55 seconds
Started Jul 21 05:01:07 PM PDT 24
Finished Jul 21 05:01:49 PM PDT 24
Peak memory 216488 kb
Host smart-cec9057a-2df0-4b9c-ad76-e039fe4f6ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422484972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2422484972
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.831384688
Short name T331
Test name
Test status
Simulation time 41173535693 ps
CPU time 123.7 seconds
Started Jul 21 05:01:08 PM PDT 24
Finished Jul 21 05:03:12 PM PDT 24
Peak memory 220556 kb
Host smart-6a1a54a1-6fc1-41e0-ade6-e6f1d379f58c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831384688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.831384688
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.441851508
Short name T97
Test name
Test status
Simulation time 332309465 ps
CPU time 8.37 seconds
Started Jul 21 05:01:13 PM PDT 24
Finished Jul 21 05:01:22 PM PDT 24
Peak memory 216388 kb
Host smart-e9a19085-8ec6-4683-ac04-b6ad19a4ed0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441851508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.441851508
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.180480191
Short name T237
Test name
Test status
Simulation time 247707042692 ps
CPU time 375.15 seconds
Started Jul 21 05:01:16 PM PDT 24
Finished Jul 21 05:07:31 PM PDT 24
Peak memory 224912 kb
Host smart-5908a8c3-f750-497b-a3c7-57c36bbcba82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180480191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.180480191
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2569127963
Short name T23
Test name
Test status
Simulation time 1321710685 ps
CPU time 18.76 seconds
Started Jul 21 05:01:13 PM PDT 24
Finished Jul 21 05:01:33 PM PDT 24
Peak memory 219200 kb
Host smart-d1c2206e-1be5-4411-8129-8daed6a6cfce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569127963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2569127963
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.4060370138
Short name T222
Test name
Test status
Simulation time 12534621269 ps
CPU time 27.02 seconds
Started Jul 21 05:01:16 PM PDT 24
Finished Jul 21 05:01:43 PM PDT 24
Peak memory 219212 kb
Host smart-efbffb4a-e4f8-4af7-8500-41703107d326
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4060370138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.4060370138
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.1344642670
Short name T175
Test name
Test status
Simulation time 3919308723 ps
CPU time 25.42 seconds
Started Jul 21 05:01:06 PM PDT 24
Finished Jul 21 05:01:32 PM PDT 24
Peak memory 216568 kb
Host smart-cf03cca1-cbff-4df6-8306-31ee33fe14ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344642670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1344642670
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1822464585
Short name T271
Test name
Test status
Simulation time 226048420 ps
CPU time 10.96 seconds
Started Jul 21 05:01:12 PM PDT 24
Finished Jul 21 05:01:24 PM PDT 24
Peak memory 214772 kb
Host smart-07f069da-a994-4ae9-8e6c-e22d5971e605
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822464585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1822464585
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3679331042
Short name T98
Test name
Test status
Simulation time 3822933621 ps
CPU time 29.64 seconds
Started Jul 21 05:01:14 PM PDT 24
Finished Jul 21 05:01:44 PM PDT 24
Peak memory 213512 kb
Host smart-9063f24e-81b2-417a-8ea7-3ebc49642d7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679331042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3679331042
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3041519866
Short name T157
Test name
Test status
Simulation time 295549273951 ps
CPU time 508.05 seconds
Started Jul 21 05:01:17 PM PDT 24
Finished Jul 21 05:09:46 PM PDT 24
Peak memory 233740 kb
Host smart-b3b3e80b-a6b4-44b0-9dcd-c6b726cbc151
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041519866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3041519866
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.975590149
Short name T246
Test name
Test status
Simulation time 10950414759 ps
CPU time 51.01 seconds
Started Jul 21 05:01:12 PM PDT 24
Finished Jul 21 05:02:04 PM PDT 24
Peak memory 219256 kb
Host smart-6c4da338-60c3-44b4-8479-38f6dc902d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975590149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.975590149
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1558149192
Short name T229
Test name
Test status
Simulation time 31226104791 ps
CPU time 33.66 seconds
Started Jul 21 05:01:13 PM PDT 24
Finished Jul 21 05:01:47 PM PDT 24
Peak memory 211896 kb
Host smart-fc941262-181c-43b5-a428-25e766b06fdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1558149192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1558149192
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2424849900
Short name T161
Test name
Test status
Simulation time 9909699590 ps
CPU time 35.16 seconds
Started Jul 21 05:01:13 PM PDT 24
Finished Jul 21 05:01:49 PM PDT 24
Peak memory 215984 kb
Host smart-b393f056-35f9-4e57-b5be-9cf909f6fb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424849900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2424849900
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2017393639
Short name T298
Test name
Test status
Simulation time 4718968480 ps
CPU time 45.01 seconds
Started Jul 21 05:01:16 PM PDT 24
Finished Jul 21 05:02:01 PM PDT 24
Peak memory 218056 kb
Host smart-08c99f99-838a-4804-8aec-818f979cc5a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017393639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2017393639
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3319075287
Short name T26
Test name
Test status
Simulation time 174673411 ps
CPU time 8.26 seconds
Started Jul 21 05:01:22 PM PDT 24
Finished Jul 21 05:01:31 PM PDT 24
Peak memory 217092 kb
Host smart-8fda102c-48ba-4e08-9ac5-353932a7ee57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319075287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3319075287
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.294261356
Short name T318
Test name
Test status
Simulation time 338928133149 ps
CPU time 420.49 seconds
Started Jul 21 05:01:19 PM PDT 24
Finished Jul 21 05:08:20 PM PDT 24
Peak memory 236176 kb
Host smart-0d8a561d-6710-4d5c-9617-da5a869375ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294261356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.294261356
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.423098632
Short name T53
Test name
Test status
Simulation time 17346299523 ps
CPU time 39.72 seconds
Started Jul 21 05:01:18 PM PDT 24
Finished Jul 21 05:01:58 PM PDT 24
Peak memory 219392 kb
Host smart-b8ea983e-e0da-478d-80da-ead7a149fb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423098632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.423098632
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2786879947
Short name T299
Test name
Test status
Simulation time 6730177171 ps
CPU time 29.29 seconds
Started Jul 21 05:01:22 PM PDT 24
Finished Jul 21 05:01:51 PM PDT 24
Peak memory 211944 kb
Host smart-9d979ce7-51ad-4e78-9849-f97825673b5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2786879947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2786879947
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.3207253514
Short name T165
Test name
Test status
Simulation time 14848681754 ps
CPU time 42.69 seconds
Started Jul 21 05:01:12 PM PDT 24
Finished Jul 21 05:01:55 PM PDT 24
Peak memory 217260 kb
Host smart-74280afd-a0cb-43f1-84da-2c2721a94d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207253514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.3207253514
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3482161472
Short name T336
Test name
Test status
Simulation time 27878595671 ps
CPU time 74.6 seconds
Started Jul 21 05:01:17 PM PDT 24
Finished Jul 21 05:02:32 PM PDT 24
Peak memory 220920 kb
Host smart-c1707365-3b67-400c-aeff-612fef65893c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482161472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3482161472
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.4208151848
Short name T201
Test name
Test status
Simulation time 7199287670 ps
CPU time 30.62 seconds
Started Jul 21 05:01:18 PM PDT 24
Finished Jul 21 05:01:49 PM PDT 24
Peak memory 213320 kb
Host smart-899b87ed-9268-4283-b61e-b644f73b6a71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208151848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.4208151848
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2441471149
Short name T329
Test name
Test status
Simulation time 111886405784 ps
CPU time 642.78 seconds
Started Jul 21 05:01:17 PM PDT 24
Finished Jul 21 05:12:00 PM PDT 24
Peak memory 216328 kb
Host smart-015709e6-6dcf-47e2-9b70-e100ea4ebb86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441471149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2441471149
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2630009390
Short name T179
Test name
Test status
Simulation time 332928467 ps
CPU time 18.78 seconds
Started Jul 21 05:01:23 PM PDT 24
Finished Jul 21 05:01:42 PM PDT 24
Peak memory 219236 kb
Host smart-9835e54b-3acc-436a-925a-7ae82cb9e4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630009390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2630009390
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3285539462
Short name T345
Test name
Test status
Simulation time 3197338519 ps
CPU time 27.64 seconds
Started Jul 21 05:01:22 PM PDT 24
Finished Jul 21 05:01:50 PM PDT 24
Peak memory 219336 kb
Host smart-a513412a-f253-4964-b795-865bc7290d08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3285539462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3285539462
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.4211968583
Short name T194
Test name
Test status
Simulation time 22178137027 ps
CPU time 61.26 seconds
Started Jul 21 05:01:21 PM PDT 24
Finished Jul 21 05:02:22 PM PDT 24
Peak memory 216340 kb
Host smart-15c4063f-c476-4e4a-be9e-5a1c1b250d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211968583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.4211968583
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3273635833
Short name T193
Test name
Test status
Simulation time 51399060318 ps
CPU time 83.58 seconds
Started Jul 21 05:01:21 PM PDT 24
Finished Jul 21 05:02:45 PM PDT 24
Peak memory 219812 kb
Host smart-55651393-a4c1-4d0e-a08d-37ef6d8b48a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273635833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3273635833
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.616105206
Short name T183
Test name
Test status
Simulation time 4010380731 ps
CPU time 32.45 seconds
Started Jul 21 05:01:33 PM PDT 24
Finished Jul 21 05:02:06 PM PDT 24
Peak memory 217152 kb
Host smart-6e32c1e1-1a8e-4d3a-ba46-8d812819ab81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616105206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.616105206
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1723159276
Short name T322
Test name
Test status
Simulation time 16929287576 ps
CPU time 284.97 seconds
Started Jul 21 05:01:33 PM PDT 24
Finished Jul 21 05:06:18 PM PDT 24
Peak memory 239884 kb
Host smart-f1740328-cace-4b4c-a860-8d951f0e981e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723159276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1723159276
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2593792277
Short name T214
Test name
Test status
Simulation time 346239953 ps
CPU time 19.24 seconds
Started Jul 21 05:01:30 PM PDT 24
Finished Jul 21 05:01:50 PM PDT 24
Peak memory 219204 kb
Host smart-ac350347-f7c4-457a-9582-e0c80c06587d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593792277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2593792277
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.927481569
Short name T4
Test name
Test status
Simulation time 208338048 ps
CPU time 10.72 seconds
Started Jul 21 05:01:32 PM PDT 24
Finished Jul 21 05:01:43 PM PDT 24
Peak memory 218656 kb
Host smart-a0edfe6f-b043-4ea4-943d-f1f9c593a4d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=927481569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.927481569
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2820153367
Short name T136
Test name
Test status
Simulation time 14502696219 ps
CPU time 41 seconds
Started Jul 21 05:01:21 PM PDT 24
Finished Jul 21 05:02:03 PM PDT 24
Peak memory 216620 kb
Host smart-c65f7ca6-526b-47b2-9bb4-d10192c7ed54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820153367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2820153367
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.581590190
Short name T281
Test name
Test status
Simulation time 34505161117 ps
CPU time 73.96 seconds
Started Jul 21 05:01:30 PM PDT 24
Finished Jul 21 05:02:45 PM PDT 24
Peak memory 217332 kb
Host smart-3ea57187-ba3a-40ac-9f66-5d5f66c60216
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581590190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.581590190
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1386518460
Short name T25
Test name
Test status
Simulation time 174432026 ps
CPU time 8.42 seconds
Started Jul 21 05:01:30 PM PDT 24
Finished Jul 21 05:01:38 PM PDT 24
Peak memory 217240 kb
Host smart-ff9a1427-4679-4cb1-bb84-5c29ec0df83f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386518460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1386518460
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3767135020
Short name T295
Test name
Test status
Simulation time 140451894912 ps
CPU time 709.72 seconds
Started Jul 21 05:01:32 PM PDT 24
Finished Jul 21 05:13:22 PM PDT 24
Peak memory 216424 kb
Host smart-09894cd3-e6bc-458f-9c03-ef8a44e0e0b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767135020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3767135020
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1631112872
Short name T141
Test name
Test status
Simulation time 25555684342 ps
CPU time 57.22 seconds
Started Jul 21 05:01:30 PM PDT 24
Finished Jul 21 05:02:28 PM PDT 24
Peak memory 219132 kb
Host smart-0a205676-33c2-4f07-a625-73a38b592bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631112872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1631112872
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1521238936
Short name T325
Test name
Test status
Simulation time 728659935 ps
CPU time 10.27 seconds
Started Jul 21 05:01:30 PM PDT 24
Finished Jul 21 05:01:40 PM PDT 24
Peak memory 219216 kb
Host smart-0fbfd08b-afac-41b6-820c-3bb1cce7a77b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1521238936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1521238936
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2369449988
Short name T3
Test name
Test status
Simulation time 12513550390 ps
CPU time 41.53 seconds
Started Jul 21 05:01:29 PM PDT 24
Finished Jul 21 05:02:11 PM PDT 24
Peak memory 216548 kb
Host smart-c9850a8a-e3cf-4a67-a0a2-714cbe98ebb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369449988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2369449988
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.231439463
Short name T188
Test name
Test status
Simulation time 26539169194 ps
CPU time 103.87 seconds
Started Jul 21 05:01:29 PM PDT 24
Finished Jul 21 05:03:13 PM PDT 24
Peak memory 221500 kb
Host smart-03a0f0e5-3edc-4c32-9391-b6cbe13e2062
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231439463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.231439463
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3649990741
Short name T70
Test name
Test status
Simulation time 174619126 ps
CPU time 8.28 seconds
Started Jul 21 05:01:34 PM PDT 24
Finished Jul 21 05:01:43 PM PDT 24
Peak memory 213220 kb
Host smart-9dbcf4fa-7b8f-4fa1-a2a0-91924ab3b6ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649990741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3649990741
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.35194070
Short name T326
Test name
Test status
Simulation time 151682571114 ps
CPU time 502.36 seconds
Started Jul 21 05:01:34 PM PDT 24
Finished Jul 21 05:09:57 PM PDT 24
Peak memory 216772 kb
Host smart-eca70cb5-90d2-4c91-a744-74ac33a89375
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35194070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_co
rrupt_sig_fatal_chk.35194070
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2898968622
Short name T310
Test name
Test status
Simulation time 18819294957 ps
CPU time 28.87 seconds
Started Jul 21 05:01:34 PM PDT 24
Finished Jul 21 05:02:03 PM PDT 24
Peak memory 219096 kb
Host smart-c80d30c0-ea3a-4d83-8993-3be4c2ce49b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898968622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2898968622
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2578170626
Short name T171
Test name
Test status
Simulation time 1436082051 ps
CPU time 18.36 seconds
Started Jul 21 05:01:33 PM PDT 24
Finished Jul 21 05:01:52 PM PDT 24
Peak memory 211640 kb
Host smart-a9440996-1a9d-44e8-b416-16afec7e63af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2578170626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2578170626
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.4107043817
Short name T225
Test name
Test status
Simulation time 5609805217 ps
CPU time 50.45 seconds
Started Jul 21 05:01:29 PM PDT 24
Finished Jul 21 05:02:20 PM PDT 24
Peak memory 216632 kb
Host smart-0cbf997c-8367-4c10-aa38-4d64d72c77f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107043817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.4107043817
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3157393709
Short name T323
Test name
Test status
Simulation time 12444527628 ps
CPU time 136.13 seconds
Started Jul 21 05:01:38 PM PDT 24
Finished Jul 21 05:03:55 PM PDT 24
Peak memory 221516 kb
Host smart-10f943e3-92e2-457f-8e38-04ef8d7751d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157393709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3157393709
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.199532599
Short name T314
Test name
Test status
Simulation time 10430556846 ps
CPU time 22.94 seconds
Started Jul 21 04:59:01 PM PDT 24
Finished Jul 21 04:59:25 PM PDT 24
Peak memory 217376 kb
Host smart-743f37f5-1584-42cd-b4d8-ae19193e65bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199532599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.199532599
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.202886720
Short name T44
Test name
Test status
Simulation time 27887942185 ps
CPU time 259.52 seconds
Started Jul 21 04:59:01 PM PDT 24
Finished Jul 21 05:03:20 PM PDT 24
Peak memory 229752 kb
Host smart-d6aa4dc0-eea0-4433-b79c-fc1dbce31246
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202886720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.202886720
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.477647538
Short name T198
Test name
Test status
Simulation time 25397316612 ps
CPU time 66.3 seconds
Started Jul 21 04:59:02 PM PDT 24
Finished Jul 21 05:00:08 PM PDT 24
Peak memory 219196 kb
Host smart-3f4b39a2-6a47-47a9-8b0b-f19f184831b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477647538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.477647538
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.940755260
Short name T162
Test name
Test status
Simulation time 46689440515 ps
CPU time 35.8 seconds
Started Jul 21 04:59:01 PM PDT 24
Finished Jul 21 04:59:37 PM PDT 24
Peak memory 217656 kb
Host smart-e1af82bc-7604-4c70-91ec-a1cb7e0be251
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=940755260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.940755260
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1202277082
Short name T287
Test name
Test status
Simulation time 8465444355 ps
CPU time 63.79 seconds
Started Jul 21 04:58:54 PM PDT 24
Finished Jul 21 04:59:58 PM PDT 24
Peak memory 216288 kb
Host smart-06e111cd-c8d4-429a-b8e3-a19363928309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202277082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1202277082
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3775098637
Short name T338
Test name
Test status
Simulation time 6059058828 ps
CPU time 58.86 seconds
Started Jul 21 04:58:55 PM PDT 24
Finished Jul 21 04:59:55 PM PDT 24
Peak memory 219320 kb
Host smart-536b9c7c-3dcd-4376-9c7e-f9c80565a416
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775098637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3775098637
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.415900709
Short name T320
Test name
Test status
Simulation time 2194958787 ps
CPU time 21.73 seconds
Started Jul 21 04:59:07 PM PDT 24
Finished Jul 21 04:59:29 PM PDT 24
Peak memory 213176 kb
Host smart-d6b19989-9742-4e8b-bb2d-9cfd1c439bd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415900709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.415900709
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.922993507
Short name T257
Test name
Test status
Simulation time 4928532464 ps
CPU time 48.61 seconds
Started Jul 21 04:59:07 PM PDT 24
Finished Jul 21 04:59:56 PM PDT 24
Peak memory 219308 kb
Host smart-5fd1fd2b-79dc-4396-b3af-cdeaa24e57f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922993507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.922993507
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3078033467
Short name T275
Test name
Test status
Simulation time 4152776122 ps
CPU time 19.55 seconds
Started Jul 21 04:59:06 PM PDT 24
Finished Jul 21 04:59:26 PM PDT 24
Peak memory 218004 kb
Host smart-6f6ce663-69f2-4e2c-9118-f8a3f2f0c8fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3078033467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3078033467
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.891102711
Short name T84
Test name
Test status
Simulation time 362826167 ps
CPU time 20.56 seconds
Started Jul 21 04:59:01 PM PDT 24
Finished Jul 21 04:59:22 PM PDT 24
Peak memory 216528 kb
Host smart-6e1d3111-4b02-4789-8efb-ff697652904e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891102711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.891102711
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.61265553
Short name T153
Test name
Test status
Simulation time 6674437505 ps
CPU time 33 seconds
Started Jul 21 04:59:01 PM PDT 24
Finished Jul 21 04:59:35 PM PDT 24
Peak memory 214560 kb
Host smart-7b6d12e3-e0f2-4a30-9c42-5927502df13f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61265553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 6.rom_ctrl_stress_all.61265553
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3912804991
Short name T243
Test name
Test status
Simulation time 1100064573 ps
CPU time 8.19 seconds
Started Jul 21 04:59:13 PM PDT 24
Finished Jul 21 04:59:22 PM PDT 24
Peak memory 213400 kb
Host smart-8ade8cbf-502e-40f3-9e9e-038b9bcd6dfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912804991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3912804991
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2114870871
Short name T19
Test name
Test status
Simulation time 103033969473 ps
CPU time 299.63 seconds
Started Jul 21 04:59:17 PM PDT 24
Finished Jul 21 05:04:17 PM PDT 24
Peak memory 227896 kb
Host smart-121c6a67-7208-464f-886c-ce7e5dcafbaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114870871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2114870871
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3419228926
Short name T259
Test name
Test status
Simulation time 15070447544 ps
CPU time 43.56 seconds
Started Jul 21 04:59:15 PM PDT 24
Finished Jul 21 04:59:59 PM PDT 24
Peak memory 219404 kb
Host smart-f5434db4-f985-43e9-b60f-d8ee0692297a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419228926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3419228926
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2390396834
Short name T49
Test name
Test status
Simulation time 3278487393 ps
CPU time 16.52 seconds
Started Jul 21 04:59:09 PM PDT 24
Finished Jul 21 04:59:25 PM PDT 24
Peak memory 218764 kb
Host smart-0b71bc9c-bd97-4b4d-95a5-0c270c54cea1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2390396834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2390396834
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2440547463
Short name T181
Test name
Test status
Simulation time 26698263104 ps
CPU time 56.67 seconds
Started Jul 21 04:59:08 PM PDT 24
Finished Jul 21 05:00:05 PM PDT 24
Peak memory 217260 kb
Host smart-71944fe6-c04c-42c2-a3fc-a0da25613bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440547463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2440547463
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.620467245
Short name T132
Test name
Test status
Simulation time 3289605604 ps
CPU time 19.08 seconds
Started Jul 21 04:59:08 PM PDT 24
Finished Jul 21 04:59:27 PM PDT 24
Peak memory 219184 kb
Host smart-789bad88-a37d-405a-98b1-12fb9a09c860
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620467245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.620467245
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2297305158
Short name T154
Test name
Test status
Simulation time 7695229424 ps
CPU time 31.63 seconds
Started Jul 21 04:59:14 PM PDT 24
Finished Jul 21 04:59:46 PM PDT 24
Peak memory 213232 kb
Host smart-bd530511-4c52-4f7a-b67e-3f53e5517780
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297305158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2297305158
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.961792048
Short name T206
Test name
Test status
Simulation time 14364161317 ps
CPU time 256.64 seconds
Started Jul 21 04:59:13 PM PDT 24
Finished Jul 21 05:03:30 PM PDT 24
Peak memory 234620 kb
Host smart-2c8fa666-5ad0-4d92-a5a2-bc130b9a72a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961792048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.961792048
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2733693183
Short name T285
Test name
Test status
Simulation time 8046869918 ps
CPU time 65.79 seconds
Started Jul 21 04:59:12 PM PDT 24
Finished Jul 21 05:00:18 PM PDT 24
Peak memory 219344 kb
Host smart-0ee9c6a0-973a-4e12-bf2c-b743e68ded29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733693183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2733693183
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2712356772
Short name T47
Test name
Test status
Simulation time 184121723 ps
CPU time 10.48 seconds
Started Jul 21 04:59:13 PM PDT 24
Finished Jul 21 04:59:24 PM PDT 24
Peak memory 219196 kb
Host smart-2a34dd17-8b55-48de-9b04-242a96602305
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2712356772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2712356772
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1282724409
Short name T276
Test name
Test status
Simulation time 3544219067 ps
CPU time 37.96 seconds
Started Jul 21 04:59:12 PM PDT 24
Finished Jul 21 04:59:51 PM PDT 24
Peak memory 216176 kb
Host smart-43759b53-5280-48dc-aa2a-bfc976ac7881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282724409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1282724409
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3124411982
Short name T155
Test name
Test status
Simulation time 23362296112 ps
CPU time 191.39 seconds
Started Jul 21 04:59:14 PM PDT 24
Finished Jul 21 05:02:25 PM PDT 24
Peak memory 228488 kb
Host smart-de11bd6b-68ac-4ce2-b53e-c016a2d24e2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124411982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3124411982
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3432400116
Short name T312
Test name
Test status
Simulation time 1414687805 ps
CPU time 16.78 seconds
Started Jul 21 04:59:19 PM PDT 24
Finished Jul 21 04:59:36 PM PDT 24
Peak memory 217188 kb
Host smart-2f5e5bbe-0d62-4636-a1e7-532c7d950709
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432400116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3432400116
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.4066113227
Short name T18
Test name
Test status
Simulation time 12862874808 ps
CPU time 192.98 seconds
Started Jul 21 04:59:18 PM PDT 24
Finished Jul 21 05:02:31 PM PDT 24
Peak memory 228592 kb
Host smart-7d093090-8972-43bb-942f-39569fd77071
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066113227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.4066113227
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2421407330
Short name T272
Test name
Test status
Simulation time 23439199287 ps
CPU time 59.75 seconds
Started Jul 21 04:59:20 PM PDT 24
Finished Jul 21 05:00:20 PM PDT 24
Peak memory 219360 kb
Host smart-a6ac04ba-6571-4ba1-9d6c-e202b4624adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421407330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2421407330
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2003493835
Short name T209
Test name
Test status
Simulation time 3695318662 ps
CPU time 31.15 seconds
Started Jul 21 04:59:18 PM PDT 24
Finished Jul 21 04:59:49 PM PDT 24
Peak memory 211452 kb
Host smart-efe152ca-2faa-42bb-98a1-8364549c0202
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2003493835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2003493835
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.310887094
Short name T139
Test name
Test status
Simulation time 31402215973 ps
CPU time 66.94 seconds
Started Jul 21 04:59:17 PM PDT 24
Finished Jul 21 05:00:25 PM PDT 24
Peak memory 214884 kb
Host smart-159cc230-787c-4221-8aba-b8e6389b2beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310887094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.310887094
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2706484114
Short name T293
Test name
Test status
Simulation time 4121332582 ps
CPU time 22.37 seconds
Started Jul 21 04:59:16 PM PDT 24
Finished Jul 21 04:59:38 PM PDT 24
Peak memory 214836 kb
Host smart-d5044b6c-057b-4224-a5d5-bae2e5a1bbbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706484114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2706484114
Directory /workspace/9.rom_ctrl_stress_all/latest
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