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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.28 96.89 92.13 97.68 100.00 98.62 97.30 98.37


Total test records in report: 459
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T299 /workspace/coverage/default/28.rom_ctrl_stress_all.3175373169 Jul 22 04:54:11 PM PDT 24 Jul 22 04:55:10 PM PDT 24 26842144899 ps
T300 /workspace/coverage/default/27.rom_ctrl_smoke.2340246710 Jul 22 04:53:40 PM PDT 24 Jul 22 04:54:40 PM PDT 24 28239852485 ps
T301 /workspace/coverage/default/37.rom_ctrl_smoke.1435319101 Jul 22 04:54:08 PM PDT 24 Jul 22 04:54:31 PM PDT 24 2127698969 ps
T302 /workspace/coverage/default/6.rom_ctrl_stress_all.2507885866 Jul 22 04:52:34 PM PDT 24 Jul 22 04:54:38 PM PDT 24 24281833605 ps
T303 /workspace/coverage/default/22.rom_ctrl_stress_all.1623377450 Jul 22 04:53:28 PM PDT 24 Jul 22 04:53:58 PM PDT 24 1382425001 ps
T304 /workspace/coverage/default/4.rom_ctrl_smoke.1307739179 Jul 22 04:52:27 PM PDT 24 Jul 22 04:53:05 PM PDT 24 2519262682 ps
T305 /workspace/coverage/default/25.rom_ctrl_stress_all.3193742484 Jul 22 04:53:40 PM PDT 24 Jul 22 04:54:15 PM PDT 24 5622834769 ps
T306 /workspace/coverage/default/26.rom_ctrl_stress_all.1500831034 Jul 22 04:53:39 PM PDT 24 Jul 22 04:55:01 PM PDT 24 8415612227 ps
T307 /workspace/coverage/default/43.rom_ctrl_smoke.4116572680 Jul 22 04:54:25 PM PDT 24 Jul 22 04:55:14 PM PDT 24 17762901970 ps
T308 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.182798278 Jul 22 04:54:29 PM PDT 24 Jul 22 04:55:30 PM PDT 24 7837416241 ps
T48 /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.1497621247 Jul 22 04:54:15 PM PDT 24 Jul 22 05:14:16 PM PDT 24 30039511345 ps
T309 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1100090044 Jul 22 04:54:33 PM PDT 24 Jul 22 04:55:02 PM PDT 24 5269413128 ps
T310 /workspace/coverage/default/33.rom_ctrl_alert_test.3719860754 Jul 22 04:56:13 PM PDT 24 Jul 22 04:56:28 PM PDT 24 1532234511 ps
T311 /workspace/coverage/default/24.rom_ctrl_smoke.1813903218 Jul 22 04:53:28 PM PDT 24 Jul 22 04:53:48 PM PDT 24 738371972 ps
T312 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3746338190 Jul 22 04:52:59 PM PDT 24 Jul 22 04:53:22 PM PDT 24 5755704936 ps
T313 /workspace/coverage/default/8.rom_ctrl_smoke.3168425797 Jul 22 04:52:34 PM PDT 24 Jul 22 04:52:55 PM PDT 24 370620130 ps
T314 /workspace/coverage/default/18.rom_ctrl_smoke.561757404 Jul 22 04:53:12 PM PDT 24 Jul 22 04:53:32 PM PDT 24 362267966 ps
T315 /workspace/coverage/default/14.rom_ctrl_smoke.3581622552 Jul 22 04:53:04 PM PDT 24 Jul 22 04:53:55 PM PDT 24 4693942259 ps
T316 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2254075473 Jul 22 04:54:17 PM PDT 24 Jul 22 04:54:33 PM PDT 24 3804338000 ps
T317 /workspace/coverage/default/39.rom_ctrl_alert_test.1541724086 Jul 22 04:54:18 PM PDT 24 Jul 22 04:54:27 PM PDT 24 170944838 ps
T49 /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3448866012 Jul 22 04:53:50 PM PDT 24 Jul 22 05:37:45 PM PDT 24 67648808021 ps
T318 /workspace/coverage/default/25.rom_ctrl_smoke.422711964 Jul 22 04:53:39 PM PDT 24 Jul 22 04:54:50 PM PDT 24 30101083168 ps
T319 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3505651950 Jul 22 04:53:10 PM PDT 24 Jul 22 05:00:37 PM PDT 24 48155125073 ps
T320 /workspace/coverage/default/44.rom_ctrl_alert_test.2486784180 Jul 22 04:55:31 PM PDT 24 Jul 22 04:55:40 PM PDT 24 339078396 ps
T321 /workspace/coverage/default/27.rom_ctrl_stress_all.3049422959 Jul 22 04:55:09 PM PDT 24 Jul 22 04:55:55 PM PDT 24 10001140374 ps
T322 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3887310046 Jul 22 04:53:50 PM PDT 24 Jul 22 04:54:56 PM PDT 24 15344699618 ps
T323 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.4195978412 Jul 22 04:53:11 PM PDT 24 Jul 22 04:53:30 PM PDT 24 827099406 ps
T324 /workspace/coverage/default/37.rom_ctrl_alert_test.979665757 Jul 22 04:54:08 PM PDT 24 Jul 22 04:54:30 PM PDT 24 44094120105 ps
T325 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1679226256 Jul 22 04:53:19 PM PDT 24 Jul 22 04:53:34 PM PDT 24 742758051 ps
T326 /workspace/coverage/default/35.rom_ctrl_stress_all.4038878045 Jul 22 04:54:07 PM PDT 24 Jul 22 04:55:07 PM PDT 24 66515569472 ps
T327 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2073307930 Jul 22 04:53:19 PM PDT 24 Jul 22 05:04:36 PM PDT 24 131021987743 ps
T328 /workspace/coverage/default/2.rom_ctrl_stress_all.2688784035 Jul 22 04:52:44 PM PDT 24 Jul 22 04:55:00 PM PDT 24 52165316602 ps
T329 /workspace/coverage/default/30.rom_ctrl_stress_all.3371619571 Jul 22 04:53:50 PM PDT 24 Jul 22 04:56:14 PM PDT 24 32832081993 ps
T330 /workspace/coverage/default/1.rom_ctrl_smoke.1345783987 Jul 22 04:52:23 PM PDT 24 Jul 22 04:53:36 PM PDT 24 8393890286 ps
T331 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1793112520 Jul 22 04:55:33 PM PDT 24 Jul 22 04:56:04 PM PDT 24 15351055830 ps
T332 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.4187711765 Jul 22 04:53:20 PM PDT 24 Jul 22 04:53:54 PM PDT 24 4073124095 ps
T333 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.361306305 Jul 22 04:52:42 PM PDT 24 Jul 22 04:53:13 PM PDT 24 3330142917 ps
T334 /workspace/coverage/default/20.rom_ctrl_alert_test.1799590504 Jul 22 04:53:20 PM PDT 24 Jul 22 04:53:43 PM PDT 24 4649535150 ps
T335 /workspace/coverage/default/19.rom_ctrl_smoke.1145408820 Jul 22 04:53:20 PM PDT 24 Jul 22 04:53:40 PM PDT 24 675066535 ps
T336 /workspace/coverage/default/46.rom_ctrl_alert_test.945865939 Jul 22 04:54:36 PM PDT 24 Jul 22 04:55:08 PM PDT 24 3669370219 ps
T337 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.189506720 Jul 22 04:53:29 PM PDT 24 Jul 22 04:54:02 PM PDT 24 2041178824 ps
T338 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.188267919 Jul 22 04:55:29 PM PDT 24 Jul 22 04:55:55 PM PDT 24 36600253253 ps
T339 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1671622774 Jul 22 04:56:12 PM PDT 24 Jul 22 04:56:24 PM PDT 24 264948510 ps
T29 /workspace/coverage/default/2.rom_ctrl_sec_cm.3942373129 Jul 22 04:52:30 PM PDT 24 Jul 22 04:56:27 PM PDT 24 15605210380 ps
T340 /workspace/coverage/default/26.rom_ctrl_smoke.2517196706 Jul 22 04:53:44 PM PDT 24 Jul 22 04:54:04 PM PDT 24 734413080 ps
T341 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1396680206 Jul 22 04:54:35 PM PDT 24 Jul 22 05:01:35 PM PDT 24 134354975504 ps
T342 /workspace/coverage/default/10.rom_ctrl_alert_test.3095390915 Jul 22 04:52:44 PM PDT 24 Jul 22 04:53:07 PM PDT 24 8514103516 ps
T50 /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2456764249 Jul 22 04:53:28 PM PDT 24 Jul 22 05:35:33 PM PDT 24 249407645424 ps
T343 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.654556187 Jul 22 04:54:44 PM PDT 24 Jul 22 05:02:33 PM PDT 24 195196719115 ps
T344 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2940779189 Jul 22 04:52:43 PM PDT 24 Jul 22 04:55:35 PM PDT 24 5633186207 ps
T345 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3776010770 Jul 22 04:55:18 PM PDT 24 Jul 22 04:55:50 PM PDT 24 14036686892 ps
T346 /workspace/coverage/default/35.rom_ctrl_smoke.2249109157 Jul 22 04:54:10 PM PDT 24 Jul 22 04:55:03 PM PDT 24 43408504342 ps
T347 /workspace/coverage/default/1.rom_ctrl_stress_all.1942272663 Jul 22 04:54:09 PM PDT 24 Jul 22 04:56:37 PM PDT 24 11544303457 ps
T348 /workspace/coverage/default/29.rom_ctrl_stress_all.1330826059 Jul 22 04:55:17 PM PDT 24 Jul 22 04:56:24 PM PDT 24 12261533601 ps
T349 /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1326493901 Jul 22 04:52:59 PM PDT 24 Jul 22 05:08:45 PM PDT 24 94838627509 ps
T350 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.4164736808 Jul 22 04:52:36 PM PDT 24 Jul 22 04:56:39 PM PDT 24 4097727349 ps
T351 /workspace/coverage/default/5.rom_ctrl_smoke.3142597214 Jul 22 04:52:30 PM PDT 24 Jul 22 04:52:50 PM PDT 24 1432855333 ps
T352 /workspace/coverage/default/21.rom_ctrl_smoke.1533807857 Jul 22 04:53:23 PM PDT 24 Jul 22 04:54:22 PM PDT 24 16877889248 ps
T353 /workspace/coverage/default/24.rom_ctrl_alert_test.1632684463 Jul 22 04:54:29 PM PDT 24 Jul 22 04:54:38 PM PDT 24 167370196 ps
T354 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.607458158 Jul 22 04:55:31 PM PDT 24 Jul 22 04:56:18 PM PDT 24 9855667290 ps
T355 /workspace/coverage/default/2.rom_ctrl_alert_test.790897615 Jul 22 04:52:30 PM PDT 24 Jul 22 04:52:52 PM PDT 24 4532768001 ps
T356 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3523289960 Jul 22 04:52:34 PM PDT 24 Jul 22 04:52:47 PM PDT 24 342130105 ps
T357 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2421293245 Jul 22 04:52:35 PM PDT 24 Jul 22 04:56:26 PM PDT 24 3307910454 ps
T358 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1250174147 Jul 22 04:54:08 PM PDT 24 Jul 22 04:54:33 PM PDT 24 2464672221 ps
T359 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1403605403 Jul 22 04:55:40 PM PDT 24 Jul 22 04:56:10 PM PDT 24 11900051470 ps
T54 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4231942905 Jul 22 04:55:54 PM PDT 24 Jul 22 04:57:27 PM PDT 24 8161076405 ps
T57 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4220175974 Jul 22 04:55:54 PM PDT 24 Jul 22 04:56:23 PM PDT 24 33652336637 ps
T58 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2249558870 Jul 22 04:58:18 PM PDT 24 Jul 22 04:58:45 PM PDT 24 2946671351 ps
T360 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3468173121 Jul 22 04:55:54 PM PDT 24 Jul 22 04:56:15 PM PDT 24 3164969809 ps
T361 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.362745562 Jul 22 04:56:18 PM PDT 24 Jul 22 04:56:47 PM PDT 24 7496086790 ps
T362 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1605978240 Jul 22 04:55:02 PM PDT 24 Jul 22 04:55:33 PM PDT 24 5571487033 ps
T363 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3882795342 Jul 22 04:55:53 PM PDT 24 Jul 22 04:56:22 PM PDT 24 11948702618 ps
T55 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2482623701 Jul 22 04:55:17 PM PDT 24 Jul 22 04:58:08 PM PDT 24 7925244764 ps
T364 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1563120875 Jul 22 04:54:53 PM PDT 24 Jul 22 04:55:11 PM PDT 24 5814004671 ps
T90 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2354356672 Jul 22 04:55:52 PM PDT 24 Jul 22 04:56:16 PM PDT 24 2915019530 ps
T365 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2230381857 Jul 22 04:55:41 PM PDT 24 Jul 22 04:56:01 PM PDT 24 19173349619 ps
T56 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2061928798 Jul 22 04:55:41 PM PDT 24 Jul 22 04:58:32 PM PDT 24 3384898018 ps
T93 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3104301231 Jul 22 04:55:56 PM PDT 24 Jul 22 04:58:27 PM PDT 24 16791314066 ps
T366 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1911726172 Jul 22 04:55:11 PM PDT 24 Jul 22 04:55:20 PM PDT 24 689302292 ps
T61 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2094483116 Jul 22 04:56:16 PM PDT 24 Jul 22 04:56:25 PM PDT 24 660426057 ps
T367 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3707670879 Jul 22 04:55:31 PM PDT 24 Jul 22 04:55:52 PM PDT 24 2133756388 ps
T91 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1233466274 Jul 22 04:55:53 PM PDT 24 Jul 22 04:56:18 PM PDT 24 12594164959 ps
T62 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.975906585 Jul 22 04:55:00 PM PDT 24 Jul 22 04:57:51 PM PDT 24 98401150110 ps
T63 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3837783003 Jul 22 04:55:41 PM PDT 24 Jul 22 04:55:50 PM PDT 24 172710279 ps
T64 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.578473442 Jul 22 04:55:06 PM PDT 24 Jul 22 04:56:14 PM PDT 24 41939667802 ps
T99 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.4217730426 Jul 22 04:55:55 PM PDT 24 Jul 22 04:58:42 PM PDT 24 2847649822 ps
T368 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4067053158 Jul 22 04:59:23 PM PDT 24 Jul 22 04:59:48 PM PDT 24 2117789575 ps
T65 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2697526209 Jul 22 04:56:05 PM PDT 24 Jul 22 04:56:14 PM PDT 24 352811336 ps
T66 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2508498148 Jul 22 04:55:29 PM PDT 24 Jul 22 04:55:39 PM PDT 24 826852702 ps
T369 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.230195187 Jul 22 04:55:11 PM PDT 24 Jul 22 04:55:40 PM PDT 24 3382320898 ps
T92 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.752126894 Jul 22 04:55:58 PM PDT 24 Jul 22 04:57:02 PM PDT 24 60877302200 ps
T370 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1375797319 Jul 22 04:55:54 PM PDT 24 Jul 22 04:56:14 PM PDT 24 8601331566 ps
T67 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.256215568 Jul 22 04:55:30 PM PDT 24 Jul 22 04:57:17 PM PDT 24 26614770736 ps
T68 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3233597388 Jul 22 04:55:54 PM PDT 24 Jul 22 04:57:32 PM PDT 24 28867341916 ps
T371 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.674511418 Jul 22 04:55:14 PM PDT 24 Jul 22 04:55:38 PM PDT 24 9016439166 ps
T69 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3154361103 Jul 22 04:55:00 PM PDT 24 Jul 22 04:55:29 PM PDT 24 21903850747 ps
T372 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2047186303 Jul 22 04:55:23 PM PDT 24 Jul 22 04:55:44 PM PDT 24 8198002724 ps
T96 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2031093718 Jul 22 04:55:20 PM PDT 24 Jul 22 04:57:01 PM PDT 24 41774762563 ps
T70 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1154210423 Jul 22 04:55:23 PM PDT 24 Jul 22 04:55:35 PM PDT 24 1971611547 ps
T373 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3048366722 Jul 22 04:55:07 PM PDT 24 Jul 22 04:55:15 PM PDT 24 167351036 ps
T374 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.428674340 Jul 22 04:54:52 PM PDT 24 Jul 22 04:55:24 PM PDT 24 3045095597 ps
T375 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2426087419 Jul 22 04:54:52 PM PDT 24 Jul 22 04:55:12 PM PDT 24 13188915995 ps
T100 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3565520129 Jul 22 04:55:07 PM PDT 24 Jul 22 04:57:57 PM PDT 24 3925679790 ps
T376 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3896232171 Jul 22 04:55:03 PM PDT 24 Jul 22 04:55:34 PM PDT 24 8521780968 ps
T77 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2388587508 Jul 22 04:55:12 PM PDT 24 Jul 22 04:58:03 PM PDT 24 67818117796 ps
T377 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3758035628 Jul 22 04:55:54 PM PDT 24 Jul 22 04:56:04 PM PDT 24 698011661 ps
T78 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2254639374 Jul 22 04:55:40 PM PDT 24 Jul 22 04:55:49 PM PDT 24 689455237 ps
T79 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.393233625 Jul 22 04:55:22 PM PDT 24 Jul 22 04:56:38 PM PDT 24 12484848193 ps
T378 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3185443397 Jul 22 04:56:13 PM PDT 24 Jul 22 04:56:25 PM PDT 24 338309237 ps
T80 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1887528325 Jul 22 04:57:15 PM PDT 24 Jul 22 04:57:25 PM PDT 24 262350038 ps
T379 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1434171800 Jul 22 04:55:30 PM PDT 24 Jul 22 04:55:39 PM PDT 24 1831633074 ps
T380 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2884520474 Jul 22 04:55:38 PM PDT 24 Jul 22 04:56:11 PM PDT 24 17258449270 ps
T381 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1578946986 Jul 22 04:55:22 PM PDT 24 Jul 22 04:55:37 PM PDT 24 2101963696 ps
T81 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.4016998137 Jul 22 04:55:12 PM PDT 24 Jul 22 04:55:41 PM PDT 24 5433431136 ps
T82 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4115154435 Jul 22 04:55:44 PM PDT 24 Jul 22 04:56:44 PM PDT 24 25430380100 ps
T103 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1237795254 Jul 22 04:55:57 PM PDT 24 Jul 22 04:58:33 PM PDT 24 3059015870 ps
T382 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2701304449 Jul 22 04:55:21 PM PDT 24 Jul 22 04:55:57 PM PDT 24 13144191375 ps
T383 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1647743700 Jul 22 04:55:13 PM PDT 24 Jul 22 04:55:27 PM PDT 24 2665012364 ps
T384 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.491642336 Jul 22 04:55:20 PM PDT 24 Jul 22 04:55:46 PM PDT 24 17398165992 ps
T385 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.863913113 Jul 22 04:55:30 PM PDT 24 Jul 22 04:55:57 PM PDT 24 8201917555 ps
T106 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.271955902 Jul 22 04:55:20 PM PDT 24 Jul 22 04:56:54 PM PDT 24 5170794770 ps
T386 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1733755264 Jul 22 04:55:21 PM PDT 24 Jul 22 04:55:44 PM PDT 24 2462957187 ps
T387 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.452667108 Jul 22 04:55:13 PM PDT 24 Jul 22 04:55:37 PM PDT 24 5844493504 ps
T107 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1134220004 Jul 22 04:55:43 PM PDT 24 Jul 22 04:58:15 PM PDT 24 1202383092 ps
T388 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.200863265 Jul 22 04:54:41 PM PDT 24 Jul 22 04:55:15 PM PDT 24 67367183859 ps
T86 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.380625045 Jul 22 04:55:14 PM PDT 24 Jul 22 04:55:52 PM PDT 24 12095421355 ps
T389 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2546816051 Jul 22 04:55:15 PM PDT 24 Jul 22 04:55:43 PM PDT 24 13323557869 ps
T97 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1214607794 Jul 22 04:55:54 PM PDT 24 Jul 22 04:57:17 PM PDT 24 530235710 ps
T390 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.181109726 Jul 22 04:55:50 PM PDT 24 Jul 22 04:57:36 PM PDT 24 11747869099 ps
T391 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1519191264 Jul 22 04:57:04 PM PDT 24 Jul 22 04:57:30 PM PDT 24 8506910476 ps
T392 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.4098553623 Jul 22 04:54:52 PM PDT 24 Jul 22 04:55:25 PM PDT 24 7736643119 ps
T393 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1299093680 Jul 22 04:55:15 PM PDT 24 Jul 22 04:55:32 PM PDT 24 3413678798 ps
T394 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4002321535 Jul 22 04:55:41 PM PDT 24 Jul 22 04:55:59 PM PDT 24 6252298275 ps
T395 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3093338115 Jul 22 04:55:14 PM PDT 24 Jul 22 04:56:47 PM PDT 24 10623078735 ps
T104 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3646721864 Jul 22 04:59:23 PM PDT 24 Jul 22 05:02:10 PM PDT 24 3264128117 ps
T396 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.873030075 Jul 22 04:55:17 PM PDT 24 Jul 22 04:55:54 PM PDT 24 4259455072 ps
T397 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.704635317 Jul 22 04:55:56 PM PDT 24 Jul 22 04:56:12 PM PDT 24 17506002261 ps
T398 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2622880054 Jul 22 04:55:05 PM PDT 24 Jul 22 04:55:26 PM PDT 24 9746400034 ps
T399 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2770650212 Jul 22 04:55:21 PM PDT 24 Jul 22 04:55:32 PM PDT 24 1343324954 ps
T400 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2357662324 Jul 22 04:56:16 PM PDT 24 Jul 22 04:56:38 PM PDT 24 4516846757 ps
T401 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.104823186 Jul 22 04:55:30 PM PDT 24 Jul 22 04:57:06 PM PDT 24 8264447931 ps
T83 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2438380403 Jul 22 04:55:56 PM PDT 24 Jul 22 04:56:22 PM PDT 24 5866183546 ps
T102 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.926050125 Jul 22 04:56:19 PM PDT 24 Jul 22 04:58:52 PM PDT 24 1982989196 ps
T402 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.952494368 Jul 22 04:55:54 PM PDT 24 Jul 22 04:56:22 PM PDT 24 5664605104 ps
T403 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4125076761 Jul 22 04:55:54 PM PDT 24 Jul 22 04:56:12 PM PDT 24 1442567482 ps
T404 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1106732675 Jul 22 04:55:23 PM PDT 24 Jul 22 04:56:53 PM PDT 24 2870858359 ps
T405 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.519977930 Jul 22 04:55:17 PM PDT 24 Jul 22 04:56:16 PM PDT 24 15124978183 ps
T406 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1703268700 Jul 22 04:55:43 PM PDT 24 Jul 22 04:55:51 PM PDT 24 660801310 ps
T407 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1563516034 Jul 22 04:55:01 PM PDT 24 Jul 22 04:55:23 PM PDT 24 1627908029 ps
T408 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1053838431 Jul 22 04:55:14 PM PDT 24 Jul 22 04:55:40 PM PDT 24 11726308280 ps
T409 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.499192213 Jul 22 04:55:21 PM PDT 24 Jul 22 04:55:40 PM PDT 24 7652858078 ps
T410 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3479134322 Jul 22 04:55:19 PM PDT 24 Jul 22 04:55:55 PM PDT 24 15529292702 ps
T411 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3506337386 Jul 22 04:55:00 PM PDT 24 Jul 22 04:55:09 PM PDT 24 613117242 ps
T412 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2658714416 Jul 22 04:55:22 PM PDT 24 Jul 22 04:56:52 PM PDT 24 18465410739 ps
T413 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2889242534 Jul 22 04:55:21 PM PDT 24 Jul 22 04:55:41 PM PDT 24 1757079827 ps
T414 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3516011830 Jul 22 04:55:01 PM PDT 24 Jul 22 04:55:10 PM PDT 24 167666619 ps
T415 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.95221981 Jul 22 04:56:16 PM PDT 24 Jul 22 04:56:43 PM PDT 24 11841423649 ps
T416 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.528979352 Jul 22 04:55:12 PM PDT 24 Jul 22 04:55:42 PM PDT 24 4029823885 ps
T417 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1026713758 Jul 22 04:55:20 PM PDT 24 Jul 22 04:55:44 PM PDT 24 4339037426 ps
T418 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.277947443 Jul 22 04:55:56 PM PDT 24 Jul 22 04:56:09 PM PDT 24 2050791457 ps
T419 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3071527559 Jul 22 04:55:01 PM PDT 24 Jul 22 04:55:25 PM PDT 24 10181314989 ps
T420 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.532045205 Jul 22 04:55:22 PM PDT 24 Jul 22 04:55:31 PM PDT 24 2058498200 ps
T89 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.302032804 Jul 22 04:55:41 PM PDT 24 Jul 22 04:57:44 PM PDT 24 81057298119 ps
T421 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2960041565 Jul 22 04:55:12 PM PDT 24 Jul 22 04:55:21 PM PDT 24 661545763 ps
T422 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1135862514 Jul 22 04:55:52 PM PDT 24 Jul 22 04:56:02 PM PDT 24 175458173 ps
T423 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1642502156 Jul 22 04:56:11 PM PDT 24 Jul 22 04:57:06 PM PDT 24 13967722199 ps
T87 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.649336131 Jul 22 04:55:42 PM PDT 24 Jul 22 04:57:02 PM PDT 24 3068448021 ps
T424 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.516727332 Jul 22 04:55:41 PM PDT 24 Jul 22 04:55:53 PM PDT 24 371692898 ps
T425 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.585350210 Jul 22 04:56:13 PM PDT 24 Jul 22 04:56:23 PM PDT 24 676629959 ps
T426 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.863752284 Jul 22 04:55:22 PM PDT 24 Jul 22 04:55:51 PM PDT 24 7068141760 ps
T427 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.733183662 Jul 22 04:54:54 PM PDT 24 Jul 22 04:55:02 PM PDT 24 194121420 ps
T428 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2693562271 Jul 22 04:55:54 PM PDT 24 Jul 22 04:56:08 PM PDT 24 1750674611 ps
T429 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.762048226 Jul 22 04:55:12 PM PDT 24 Jul 22 04:55:38 PM PDT 24 11294848014 ps
T430 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.675836403 Jul 22 04:55:11 PM PDT 24 Jul 22 04:55:20 PM PDT 24 2355156781 ps
T431 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.547620388 Jul 22 04:55:37 PM PDT 24 Jul 22 04:56:01 PM PDT 24 11218746279 ps
T432 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1594246924 Jul 22 04:55:21 PM PDT 24 Jul 22 04:55:47 PM PDT 24 11654095863 ps
T433 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2377490527 Jul 22 04:55:43 PM PDT 24 Jul 22 04:55:55 PM PDT 24 3426699057 ps
T434 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2354012968 Jul 22 04:55:43 PM PDT 24 Jul 22 04:56:09 PM PDT 24 6794182640 ps
T435 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3356474129 Jul 22 04:55:43 PM PDT 24 Jul 22 04:55:57 PM PDT 24 169353617 ps
T436 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.522342811 Jul 22 04:54:52 PM PDT 24 Jul 22 04:55:17 PM PDT 24 7001922089 ps
T437 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1323592823 Jul 22 04:55:42 PM PDT 24 Jul 22 04:57:33 PM PDT 24 16156476033 ps
T438 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.341677943 Jul 22 04:55:40 PM PDT 24 Jul 22 04:56:01 PM PDT 24 2215263319 ps
T439 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3468063266 Jul 22 04:55:31 PM PDT 24 Jul 22 04:55:41 PM PDT 24 189895372 ps
T84 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3943458624 Jul 22 04:55:29 PM PDT 24 Jul 22 04:58:44 PM PDT 24 42556517133 ps
T440 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4178029374 Jul 22 04:55:30 PM PDT 24 Jul 22 04:55:41 PM PDT 24 508150147 ps
T101 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.747507168 Jul 22 04:55:30 PM PDT 24 Jul 22 04:57:12 PM PDT 24 70519769608 ps
T441 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1034713826 Jul 22 04:55:11 PM PDT 24 Jul 22 04:56:45 PM PDT 24 48438048992 ps
T442 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.235885384 Jul 22 04:55:21 PM PDT 24 Jul 22 04:58:13 PM PDT 24 4022649005 ps
T443 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1130806716 Jul 22 04:55:43 PM PDT 24 Jul 22 04:55:52 PM PDT 24 362786830 ps
T444 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.4247126567 Jul 22 04:55:28 PM PDT 24 Jul 22 04:56:02 PM PDT 24 8395234668 ps
T445 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2465864314 Jul 22 04:55:07 PM PDT 24 Jul 22 04:55:39 PM PDT 24 13990262454 ps
T446 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1980895381 Jul 22 04:56:07 PM PDT 24 Jul 22 04:56:22 PM PDT 24 1897023027 ps
T447 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2734270365 Jul 22 04:55:29 PM PDT 24 Jul 22 04:57:32 PM PDT 24 10855388676 ps
T448 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2159736496 Jul 22 04:56:52 PM PDT 24 Jul 22 04:59:27 PM PDT 24 604996316 ps
T449 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2478388806 Jul 22 04:55:42 PM PDT 24 Jul 22 04:55:59 PM PDT 24 5775906504 ps
T450 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2579063209 Jul 22 04:55:54 PM PDT 24 Jul 22 04:56:15 PM PDT 24 3920482648 ps
T88 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1560347352 Jul 22 04:55:20 PM PDT 24 Jul 22 04:55:47 PM PDT 24 6111077300 ps
T451 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3554864875 Jul 22 04:55:53 PM PDT 24 Jul 22 04:56:18 PM PDT 24 3066664015 ps
T105 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2287365433 Jul 22 04:55:31 PM PDT 24 Jul 22 04:57:11 PM PDT 24 7730265313 ps
T452 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1147815096 Jul 22 04:55:21 PM PDT 24 Jul 22 04:55:38 PM PDT 24 3409666102 ps
T453 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.4094194830 Jul 22 04:56:06 PM PDT 24 Jul 22 04:56:29 PM PDT 24 15719208421 ps
T454 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.446527099 Jul 22 04:55:41 PM PDT 24 Jul 22 04:55:56 PM PDT 24 4876793507 ps
T455 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1236291086 Jul 22 04:55:02 PM PDT 24 Jul 22 04:55:30 PM PDT 24 3146530162 ps
T456 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3841796673 Jul 22 04:55:40 PM PDT 24 Jul 22 04:56:06 PM PDT 24 1968858804 ps
T457 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2275828897 Jul 22 04:55:41 PM PDT 24 Jul 22 04:55:59 PM PDT 24 581872982 ps
T98 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4274206658 Jul 22 04:56:05 PM PDT 24 Jul 22 04:57:28 PM PDT 24 1665710742 ps
T458 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.55670283 Jul 22 04:57:29 PM PDT 24 Jul 22 04:58:09 PM PDT 24 693901416 ps
T459 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2167595209 Jul 22 04:55:13 PM PDT 24 Jul 22 04:55:21 PM PDT 24 636318026 ps
T85 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3403166965 Jul 22 04:55:53 PM PDT 24 Jul 22 04:56:13 PM PDT 24 8563618064 ps

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.410781332
Short name T3
Test name
Test status
Simulation time 54598381599 ps
CPU time 382.73 seconds
Started Jul 22 04:52:26 PM PDT 24
Finished Jul 22 04:58:49 PM PDT 24
Peak memory 234612 kb
Host smart-843ebeaf-8a37-41a1-8053-a3813447bc85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410781332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.410781332
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.628413458
Short name T15
Test name
Test status
Simulation time 29928475694 ps
CPU time 1250.49 seconds
Started Jul 22 04:53:11 PM PDT 24
Finished Jul 22 05:14:02 PM PDT 24
Peak memory 235776 kb
Host smart-0567c895-f345-4566-b631-964ba66eaf47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628413458 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.628413458
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3467765784
Short name T11
Test name
Test status
Simulation time 47618310766 ps
CPU time 630.18 seconds
Started Jul 22 04:53:28 PM PDT 24
Finished Jul 22 05:03:59 PM PDT 24
Peak memory 218104 kb
Host smart-60e2221e-f123-4a41-99f7-4006c3882f34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467765784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3467765784
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.4217730426
Short name T99
Test name
Test status
Simulation time 2847649822 ps
CPU time 166.11 seconds
Started Jul 22 04:55:55 PM PDT 24
Finished Jul 22 04:58:42 PM PDT 24
Peak memory 213844 kb
Host smart-5cba6d6d-59ee-49b6-b8bd-0754499df68a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217730426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.4217730426
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2725426858
Short name T4
Test name
Test status
Simulation time 10653584482 ps
CPU time 48.29 seconds
Started Jul 22 04:52:43 PM PDT 24
Finished Jul 22 04:53:32 PM PDT 24
Peak memory 216384 kb
Host smart-19d1586c-6f99-4629-80a6-7ac8b8aec06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725426858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2725426858
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.255522612
Short name T25
Test name
Test status
Simulation time 282482605 ps
CPU time 118.41 seconds
Started Jul 22 04:52:28 PM PDT 24
Finished Jul 22 04:54:27 PM PDT 24
Peak memory 237524 kb
Host smart-00b10f11-3c0e-4df2-9467-39958bb95e1b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255522612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.255522612
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.578473442
Short name T64
Test name
Test status
Simulation time 41939667802 ps
CPU time 67.61 seconds
Started Jul 22 04:55:06 PM PDT 24
Finished Jul 22 04:56:14 PM PDT 24
Peak memory 213852 kb
Host smart-1d5dc795-499b-49fa-b241-46f2f6ba14e3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578473442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pas
sthru_mem_tl_intg_err.578473442
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2482623701
Short name T55
Test name
Test status
Simulation time 7925244764 ps
CPU time 170.52 seconds
Started Jul 22 04:55:17 PM PDT 24
Finished Jul 22 04:58:08 PM PDT 24
Peak memory 214128 kb
Host smart-645bc03e-11e8-4125-b258-4012d1369b12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482623701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2482623701
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1154276525
Short name T60
Test name
Test status
Simulation time 775756743 ps
CPU time 13.48 seconds
Started Jul 22 04:53:49 PM PDT 24
Finished Jul 22 04:54:03 PM PDT 24
Peak memory 217092 kb
Host smart-f52345bc-f553-450e-a56b-6d99c3581c6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154276525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1154276525
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3943458624
Short name T84
Test name
Test status
Simulation time 42556517133 ps
CPU time 194.11 seconds
Started Jul 22 04:55:29 PM PDT 24
Finished Jul 22 04:58:44 PM PDT 24
Peak memory 214732 kb
Host smart-1afa81b5-84b3-49cf-ad1a-1b47d5d84f65
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943458624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3943458624
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3401826538
Short name T108
Test name
Test status
Simulation time 1438902185 ps
CPU time 27.51 seconds
Started Jul 22 04:52:52 PM PDT 24
Finished Jul 22 04:53:20 PM PDT 24
Peak memory 219284 kb
Host smart-82d9fd2a-1194-41dd-bcc5-7aba0f694e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401826538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3401826538
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1362754800
Short name T42
Test name
Test status
Simulation time 353405704 ps
CPU time 18.76 seconds
Started Jul 22 04:53:04 PM PDT 24
Finished Jul 22 04:53:23 PM PDT 24
Peak memory 219308 kb
Host smart-fccd3ab4-3975-42f3-956b-36f865e43c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362754800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1362754800
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3994178085
Short name T44
Test name
Test status
Simulation time 15070353127 ps
CPU time 42.2 seconds
Started Jul 22 04:53:28 PM PDT 24
Finished Jul 22 04:54:11 PM PDT 24
Peak memory 219344 kb
Host smart-49a8ce16-6b53-42ce-87a0-93fa78db5a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994178085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3994178085
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2031093718
Short name T96
Test name
Test status
Simulation time 41774762563 ps
CPU time 100.33 seconds
Started Jul 22 04:55:20 PM PDT 24
Finished Jul 22 04:57:01 PM PDT 24
Peak memory 213840 kb
Host smart-184b318f-09ce-4f1b-b892-0c6d015619fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031093718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2031093718
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1690135928
Short name T21
Test name
Test status
Simulation time 246276251730 ps
CPU time 511.3 seconds
Started Jul 22 04:52:59 PM PDT 24
Finished Jul 22 05:01:31 PM PDT 24
Peak memory 236820 kb
Host smart-b9d8c111-4c0c-428e-8503-b7604af5337a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690135928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1690135928
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.747507168
Short name T101
Test name
Test status
Simulation time 70519769608 ps
CPU time 101.42 seconds
Started Jul 22 04:55:30 PM PDT 24
Finished Jul 22 04:57:12 PM PDT 24
Peak memory 213696 kb
Host smart-2fcc185a-03a2-4388-9e67-317b815b6f4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747507168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.747507168
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3646721864
Short name T104
Test name
Test status
Simulation time 3264128117 ps
CPU time 166.34 seconds
Started Jul 22 04:59:23 PM PDT 24
Finished Jul 22 05:02:10 PM PDT 24
Peak memory 213776 kb
Host smart-48c6f30d-36d0-4b1e-8ce4-f3adbfcc68c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646721864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3646721864
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4231942905
Short name T54
Test name
Test status
Simulation time 8161076405 ps
CPU time 93.17 seconds
Started Jul 22 04:55:54 PM PDT 24
Finished Jul 22 04:57:27 PM PDT 24
Peak memory 213752 kb
Host smart-f72e8e99-34a0-42b3-820c-c5e9cb98c818
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231942905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.4231942905
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3895671188
Short name T71
Test name
Test status
Simulation time 10347102390 ps
CPU time 65.17 seconds
Started Jul 22 04:55:04 PM PDT 24
Finished Jul 22 04:56:10 PM PDT 24
Peak memory 216848 kb
Host smart-9f0fbe02-cce9-4a96-b52e-edb0802e287b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895671188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3895671188
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.3758854865
Short name T18
Test name
Test status
Simulation time 44865007205 ps
CPU time 1769.89 seconds
Started Jul 22 04:54:37 PM PDT 24
Finished Jul 22 05:24:07 PM PDT 24
Peak memory 237148 kb
Host smart-5295e30f-7c6d-462f-a03e-c543259081fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758854865 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.3758854865
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3003942045
Short name T166
Test name
Test status
Simulation time 11756631698 ps
CPU time 79.1 seconds
Started Jul 22 04:52:59 PM PDT 24
Finished Jul 22 04:54:19 PM PDT 24
Peak memory 221024 kb
Host smart-3b0ef1e3-6e95-43e5-bd0b-27db8128f739
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003942045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3003942045
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2426087419
Short name T375
Test name
Test status
Simulation time 13188915995 ps
CPU time 19.49 seconds
Started Jul 22 04:54:52 PM PDT 24
Finished Jul 22 04:55:12 PM PDT 24
Peak memory 211972 kb
Host smart-26cbd35a-a36f-4d95-8922-460c18f23099
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426087419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2426087419
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.4098553623
Short name T392
Test name
Test status
Simulation time 7736643119 ps
CPU time 31.8 seconds
Started Jul 22 04:54:52 PM PDT 24
Finished Jul 22 04:55:25 PM PDT 24
Peak memory 210640 kb
Host smart-c190aa1f-2fe2-4fbb-b1fa-c04cdf9c86f4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098553623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.4098553623
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.428674340
Short name T374
Test name
Test status
Simulation time 3045095597 ps
CPU time 31.72 seconds
Started Jul 22 04:54:52 PM PDT 24
Finished Jul 22 04:55:24 PM PDT 24
Peak memory 211500 kb
Host smart-ebc17472-5a08-41b7-ba2c-8272e3f850e4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428674340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.428674340
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.522342811
Short name T436
Test name
Test status
Simulation time 7001922089 ps
CPU time 24.08 seconds
Started Jul 22 04:54:52 PM PDT 24
Finished Jul 22 04:55:17 PM PDT 24
Peak memory 216496 kb
Host smart-2c800fd0-5ce4-4cd2-a81b-50800f45cfc3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522342811 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.522342811
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.733183662
Short name T427
Test name
Test status
Simulation time 194121420 ps
CPU time 8.21 seconds
Started Jul 22 04:54:54 PM PDT 24
Finished Jul 22 04:55:02 PM PDT 24
Peak memory 210480 kb
Host smart-c43ecb25-aed1-433f-b0b9-97a83932f37b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733183662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.733183662
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1563120875
Short name T364
Test name
Test status
Simulation time 5814004671 ps
CPU time 17.38 seconds
Started Jul 22 04:54:53 PM PDT 24
Finished Jul 22 04:55:11 PM PDT 24
Peak memory 210800 kb
Host smart-d067f396-7393-439f-af28-e412e799410f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563120875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1563120875
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2047186303
Short name T372
Test name
Test status
Simulation time 8198002724 ps
CPU time 20.35 seconds
Started Jul 22 04:55:23 PM PDT 24
Finished Jul 22 04:55:44 PM PDT 24
Peak memory 210736 kb
Host smart-753db575-733c-4643-b55f-100d6f9f1335
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047186303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2047186303
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.256215568
Short name T67
Test name
Test status
Simulation time 26614770736 ps
CPU time 105.99 seconds
Started Jul 22 04:55:30 PM PDT 24
Finished Jul 22 04:57:17 PM PDT 24
Peak memory 213852 kb
Host smart-5b68a8ad-4907-4860-b95e-ae4def34f379
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256215568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.256215568
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.547620388
Short name T431
Test name
Test status
Simulation time 11218746279 ps
CPU time 23.78 seconds
Started Jul 22 04:55:37 PM PDT 24
Finished Jul 22 04:56:01 PM PDT 24
Peak memory 212384 kb
Host smart-4a48a8d6-5e6e-41fc-8fde-54e346d3e423
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547620388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.547620388
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.200863265
Short name T388
Test name
Test status
Simulation time 67367183859 ps
CPU time 33.21 seconds
Started Jul 22 04:54:41 PM PDT 24
Finished Jul 22 04:55:15 PM PDT 24
Peak memory 218912 kb
Host smart-5bf365d6-3c6c-4af4-9a3f-b6c3f7c5db44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200863265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.200863265
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3093338115
Short name T395
Test name
Test status
Simulation time 10623078735 ps
CPU time 92.7 seconds
Started Jul 22 04:55:14 PM PDT 24
Finished Jul 22 04:56:47 PM PDT 24
Peak memory 214788 kb
Host smart-ded407c2-2dec-46f9-853f-218ce46b55bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093338115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3093338115
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1236291086
Short name T455
Test name
Test status
Simulation time 3146530162 ps
CPU time 26.97 seconds
Started Jul 22 04:55:02 PM PDT 24
Finished Jul 22 04:55:30 PM PDT 24
Peak memory 211392 kb
Host smart-0ade1156-0558-4279-a84c-f13eece648b4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236291086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1236291086
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.362745562
Short name T361
Test name
Test status
Simulation time 7496086790 ps
CPU time 28.48 seconds
Started Jul 22 04:56:18 PM PDT 24
Finished Jul 22 04:56:47 PM PDT 24
Peak memory 211496 kb
Host smart-994b7e28-7a1d-490f-95e3-ac400a2404a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362745562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.362745562
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1563516034
Short name T407
Test name
Test status
Simulation time 1627908029 ps
CPU time 21.63 seconds
Started Jul 22 04:55:01 PM PDT 24
Finished Jul 22 04:55:23 PM PDT 24
Peak memory 211400 kb
Host smart-deac9a74-1ce1-465b-9487-9a59d706c39f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563516034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1563516034
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2884520474
Short name T380
Test name
Test status
Simulation time 17258449270 ps
CPU time 33.24 seconds
Started Jul 22 04:55:38 PM PDT 24
Finished Jul 22 04:56:11 PM PDT 24
Peak memory 216988 kb
Host smart-ffee6c56-707f-46ab-a4e4-dac1e3907b5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884520474 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2884520474
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2546816051
Short name T389
Test name
Test status
Simulation time 13323557869 ps
CPU time 27.24 seconds
Started Jul 22 04:55:15 PM PDT 24
Finished Jul 22 04:55:43 PM PDT 24
Peak memory 212228 kb
Host smart-8a7c68b4-76aa-429f-87b8-17cb46c7752f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546816051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2546816051
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3506337386
Short name T411
Test name
Test status
Simulation time 613117242 ps
CPU time 7.93 seconds
Started Jul 22 04:55:00 PM PDT 24
Finished Jul 22 04:55:09 PM PDT 24
Peak memory 210352 kb
Host smart-cad540e3-0320-4246-a3e2-0f4ca7771dde
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506337386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3506337386
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3896232171
Short name T376
Test name
Test status
Simulation time 8521780968 ps
CPU time 30.41 seconds
Started Jul 22 04:55:03 PM PDT 24
Finished Jul 22 04:55:34 PM PDT 24
Peak memory 210628 kb
Host smart-40a6c920-d05c-4131-9d0c-1b882a113ee5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896232171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3896232171
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1642502156
Short name T423
Test name
Test status
Simulation time 13967722199 ps
CPU time 54.93 seconds
Started Jul 22 04:56:11 PM PDT 24
Finished Jul 22 04:57:06 PM PDT 24
Peak memory 213620 kb
Host smart-a0132e6f-3cb5-4fc7-a1d7-ce5ed273cdd3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642502156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1642502156
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3154361103
Short name T69
Test name
Test status
Simulation time 21903850747 ps
CPU time 28 seconds
Started Jul 22 04:55:00 PM PDT 24
Finished Jul 22 04:55:29 PM PDT 24
Peak memory 212480 kb
Host smart-d6d52af8-edab-4317-a64f-8c49e367a549
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154361103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3154361103
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1605978240
Short name T362
Test name
Test status
Simulation time 5571487033 ps
CPU time 29.71 seconds
Started Jul 22 04:55:02 PM PDT 24
Finished Jul 22 04:55:33 PM PDT 24
Peak memory 218852 kb
Host smart-603d6db4-22ae-4e53-87b8-03c13eb5b3f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605978240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1605978240
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3565520129
Short name T100
Test name
Test status
Simulation time 3925679790 ps
CPU time 169.49 seconds
Started Jul 22 04:55:07 PM PDT 24
Finished Jul 22 04:57:57 PM PDT 24
Peak memory 213636 kb
Host smart-f1337f8d-643a-4e5c-b7c3-498a804e1bd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565520129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3565520129
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3468063266
Short name T439
Test name
Test status
Simulation time 189895372 ps
CPU time 8.78 seconds
Started Jul 22 04:55:31 PM PDT 24
Finished Jul 22 04:55:41 PM PDT 24
Peak memory 218984 kb
Host smart-ec472611-e28d-4e4a-9bf2-00be5ca71825
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468063266 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3468063266
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4178029374
Short name T440
Test name
Test status
Simulation time 508150147 ps
CPU time 9.77 seconds
Started Jul 22 04:55:30 PM PDT 24
Finished Jul 22 04:55:41 PM PDT 24
Peak memory 210444 kb
Host smart-48f52fc7-6776-4166-b4fb-d858a454e755
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178029374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.4178029374
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1434171800
Short name T379
Test name
Test status
Simulation time 1831633074 ps
CPU time 8.21 seconds
Started Jul 22 04:55:30 PM PDT 24
Finished Jul 22 04:55:39 PM PDT 24
Peak memory 211084 kb
Host smart-1c7561e4-ca8f-4b2c-b0fc-d6251b943526
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434171800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1434171800
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1519191264
Short name T391
Test name
Test status
Simulation time 8506910476 ps
CPU time 24.95 seconds
Started Jul 22 04:57:04 PM PDT 24
Finished Jul 22 04:57:30 PM PDT 24
Peak memory 217588 kb
Host smart-bed626f5-c1bb-441c-95c2-b96668e75d77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519191264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1519191264
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4002321535
Short name T394
Test name
Test status
Simulation time 6252298275 ps
CPU time 17.55 seconds
Started Jul 22 04:55:41 PM PDT 24
Finished Jul 22 04:55:59 PM PDT 24
Peak memory 217868 kb
Host smart-a709467b-c480-4d2f-833c-bdb241ae4b51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002321535 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.4002321535
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1703268700
Short name T406
Test name
Test status
Simulation time 660801310 ps
CPU time 8.06 seconds
Started Jul 22 04:55:43 PM PDT 24
Finished Jul 22 04:55:51 PM PDT 24
Peak memory 210456 kb
Host smart-90d7e030-f567-4688-8d4d-d18ea49e2ae0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703268700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1703268700
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1323592823
Short name T437
Test name
Test status
Simulation time 16156476033 ps
CPU time 109.81 seconds
Started Jul 22 04:55:42 PM PDT 24
Finished Jul 22 04:57:33 PM PDT 24
Peak memory 216088 kb
Host smart-2a84554e-e565-4f27-80a3-6a6cb82bf727
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323592823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1323592823
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2377490527
Short name T433
Test name
Test status
Simulation time 3426699057 ps
CPU time 11.22 seconds
Started Jul 22 04:55:43 PM PDT 24
Finished Jul 22 04:55:55 PM PDT 24
Peak memory 210932 kb
Host smart-a38affa4-76fd-4d77-9188-a8812682fe65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377490527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2377490527
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1403605403
Short name T359
Test name
Test status
Simulation time 11900051470 ps
CPU time 29.07 seconds
Started Jul 22 04:55:40 PM PDT 24
Finished Jul 22 04:56:10 PM PDT 24
Peak memory 217528 kb
Host smart-b6597576-94a9-4faf-9c73-5ed790b0564a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403605403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1403605403
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1134220004
Short name T107
Test name
Test status
Simulation time 1202383092 ps
CPU time 151.79 seconds
Started Jul 22 04:55:43 PM PDT 24
Finished Jul 22 04:58:15 PM PDT 24
Peak memory 213920 kb
Host smart-0fb59a73-67cf-4751-904b-482f45354efa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134220004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1134220004
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1130806716
Short name T443
Test name
Test status
Simulation time 362786830 ps
CPU time 8.32 seconds
Started Jul 22 04:55:43 PM PDT 24
Finished Jul 22 04:55:52 PM PDT 24
Peak memory 213764 kb
Host smart-55b8c77c-c014-4054-884c-4e40765b8bc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130806716 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1130806716
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2478388806
Short name T449
Test name
Test status
Simulation time 5775906504 ps
CPU time 16.25 seconds
Started Jul 22 04:55:42 PM PDT 24
Finished Jul 22 04:55:59 PM PDT 24
Peak memory 210560 kb
Host smart-3c49f3d7-db39-4df1-9390-5016af8d632b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478388806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2478388806
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.649336131
Short name T87
Test name
Test status
Simulation time 3068448021 ps
CPU time 78.76 seconds
Started Jul 22 04:55:42 PM PDT 24
Finished Jul 22 04:57:02 PM PDT 24
Peak memory 214804 kb
Host smart-60889fdf-0a37-4466-aec3-16d0b4e9947d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649336131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.649336131
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2354012968
Short name T434
Test name
Test status
Simulation time 6794182640 ps
CPU time 25.63 seconds
Started Jul 22 04:55:43 PM PDT 24
Finished Jul 22 04:56:09 PM PDT 24
Peak memory 212280 kb
Host smart-cacc2a87-830e-4c3b-a217-63a3804d9f10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354012968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2354012968
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3185443397
Short name T378
Test name
Test status
Simulation time 338309237 ps
CPU time 11.52 seconds
Started Jul 22 04:56:13 PM PDT 24
Finished Jul 22 04:56:25 PM PDT 24
Peak memory 217028 kb
Host smart-bdc1fd4b-337d-44a2-973d-a1102fab1fd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185443397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3185443397
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2061928798
Short name T56
Test name
Test status
Simulation time 3384898018 ps
CPU time 170.79 seconds
Started Jul 22 04:55:41 PM PDT 24
Finished Jul 22 04:58:32 PM PDT 24
Peak memory 213768 kb
Host smart-41a03d1d-d6db-4fe6-a3bc-330826fc5ed2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061928798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2061928798
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2230381857
Short name T365
Test name
Test status
Simulation time 19173349619 ps
CPU time 19.41 seconds
Started Jul 22 04:55:41 PM PDT 24
Finished Jul 22 04:56:01 PM PDT 24
Peak memory 217708 kb
Host smart-089ab035-1e10-42ed-907a-e5775aed9e7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230381857 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2230381857
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2254639374
Short name T78
Test name
Test status
Simulation time 689455237 ps
CPU time 8.35 seconds
Started Jul 22 04:55:40 PM PDT 24
Finished Jul 22 04:55:49 PM PDT 24
Peak memory 210532 kb
Host smart-c18736e3-c33d-4c3b-b8ed-e91f184d20d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254639374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2254639374
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.302032804
Short name T89
Test name
Test status
Simulation time 81057298119 ps
CPU time 122.15 seconds
Started Jul 22 04:55:41 PM PDT 24
Finished Jul 22 04:57:44 PM PDT 24
Peak memory 214868 kb
Host smart-96f9a8b6-aeab-4c2c-916e-8e92bead27a5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302032804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.302032804
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3837783003
Short name T63
Test name
Test status
Simulation time 172710279 ps
CPU time 8.39 seconds
Started Jul 22 04:55:41 PM PDT 24
Finished Jul 22 04:55:50 PM PDT 24
Peak memory 211388 kb
Host smart-ab55bc91-d3d8-4594-99a7-bf3685972724
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837783003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3837783003
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3841796673
Short name T456
Test name
Test status
Simulation time 1968858804 ps
CPU time 24.9 seconds
Started Jul 22 04:55:40 PM PDT 24
Finished Jul 22 04:56:06 PM PDT 24
Peak memory 218256 kb
Host smart-8aeaa0af-3a9f-45fe-acc7-8cc17ff4e33d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841796673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3841796673
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.446527099
Short name T454
Test name
Test status
Simulation time 4876793507 ps
CPU time 14.75 seconds
Started Jul 22 04:55:41 PM PDT 24
Finished Jul 22 04:55:56 PM PDT 24
Peak memory 216388 kb
Host smart-5b091de6-43cf-4f0b-a01b-e9f81e010acc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446527099 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.446527099
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.341677943
Short name T438
Test name
Test status
Simulation time 2215263319 ps
CPU time 20.77 seconds
Started Jul 22 04:55:40 PM PDT 24
Finished Jul 22 04:56:01 PM PDT 24
Peak memory 210516 kb
Host smart-9b428736-9e9f-4c98-ab96-a1e87ffaba1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341677943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.341677943
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.181109726
Short name T390
Test name
Test status
Simulation time 11747869099 ps
CPU time 105.27 seconds
Started Jul 22 04:55:50 PM PDT 24
Finished Jul 22 04:57:36 PM PDT 24
Peak memory 213792 kb
Host smart-4c37dcac-dfcb-40f7-a279-2434ee519d9e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181109726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa
ssthru_mem_tl_intg_err.181109726
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.516727332
Short name T424
Test name
Test status
Simulation time 371692898 ps
CPU time 12.06 seconds
Started Jul 22 04:55:41 PM PDT 24
Finished Jul 22 04:55:53 PM PDT 24
Peak memory 212452 kb
Host smart-844e6198-2d73-4235-9deb-2db4ad95e2df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516727332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.516727332
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3356474129
Short name T435
Test name
Test status
Simulation time 169353617 ps
CPU time 13.49 seconds
Started Jul 22 04:55:43 PM PDT 24
Finished Jul 22 04:55:57 PM PDT 24
Peak memory 217124 kb
Host smart-dc1ec4b5-98f0-461f-a24f-ae5e292faf36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356474129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3356474129
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2159736496
Short name T448
Test name
Test status
Simulation time 604996316 ps
CPU time 153.34 seconds
Started Jul 22 04:56:52 PM PDT 24
Finished Jul 22 04:59:27 PM PDT 24
Peak memory 212784 kb
Host smart-0946cd31-66a0-4a21-8272-e72bde8bed1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159736496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2159736496
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2249558870
Short name T58
Test name
Test status
Simulation time 2946671351 ps
CPU time 26.02 seconds
Started Jul 22 04:58:18 PM PDT 24
Finished Jul 22 04:58:45 PM PDT 24
Peak memory 217952 kb
Host smart-e91270ae-c1db-447f-aed2-644bf4679e8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249558870 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2249558870
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2438380403
Short name T83
Test name
Test status
Simulation time 5866183546 ps
CPU time 25.62 seconds
Started Jul 22 04:55:56 PM PDT 24
Finished Jul 22 04:56:22 PM PDT 24
Peak memory 212056 kb
Host smart-e2b179df-1adb-481c-9f61-f1f887b30235
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438380403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2438380403
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4115154435
Short name T82
Test name
Test status
Simulation time 25430380100 ps
CPU time 59.87 seconds
Started Jul 22 04:55:44 PM PDT 24
Finished Jul 22 04:56:44 PM PDT 24
Peak memory 213712 kb
Host smart-9d2160e7-3fb4-42dc-9e39-b4bd57d53d27
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115154435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.4115154435
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1233466274
Short name T91
Test name
Test status
Simulation time 12594164959 ps
CPU time 25.12 seconds
Started Jul 22 04:55:53 PM PDT 24
Finished Jul 22 04:56:18 PM PDT 24
Peak memory 212568 kb
Host smart-acb216a3-9fce-4607-ace4-75e284991d7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233466274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1233466274
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2275828897
Short name T457
Test name
Test status
Simulation time 581872982 ps
CPU time 17.36 seconds
Started Jul 22 04:55:41 PM PDT 24
Finished Jul 22 04:55:59 PM PDT 24
Peak memory 218336 kb
Host smart-412748c4-1f07-4a87-ac91-ea95abff0c40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275828897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2275828897
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1214607794
Short name T97
Test name
Test status
Simulation time 530235710 ps
CPU time 82.24 seconds
Started Jul 22 04:55:54 PM PDT 24
Finished Jul 22 04:57:17 PM PDT 24
Peak memory 213440 kb
Host smart-8265bb3f-918a-4fc4-86d2-b7dd546670a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214607794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1214607794
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2579063209
Short name T450
Test name
Test status
Simulation time 3920482648 ps
CPU time 19.86 seconds
Started Jul 22 04:55:54 PM PDT 24
Finished Jul 22 04:56:15 PM PDT 24
Peak memory 216196 kb
Host smart-13dba94f-2345-46fa-b330-39273aff696b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579063209 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2579063209
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2693562271
Short name T428
Test name
Test status
Simulation time 1750674611 ps
CPU time 13.73 seconds
Started Jul 22 04:55:54 PM PDT 24
Finished Jul 22 04:56:08 PM PDT 24
Peak memory 210612 kb
Host smart-43f1e3c0-a483-4b9c-93c5-91e0456e78c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693562271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2693562271
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3104301231
Short name T93
Test name
Test status
Simulation time 16791314066 ps
CPU time 151.19 seconds
Started Jul 22 04:55:56 PM PDT 24
Finished Jul 22 04:58:27 PM PDT 24
Peak memory 215396 kb
Host smart-21b4d131-5581-4943-b074-88158b8ddae1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104301231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3104301231
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.704635317
Short name T397
Test name
Test status
Simulation time 17506002261 ps
CPU time 16.43 seconds
Started Jul 22 04:55:56 PM PDT 24
Finished Jul 22 04:56:12 PM PDT 24
Peak memory 211388 kb
Host smart-3ce499a8-4f8a-4141-831e-a22782c42ec6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704635317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.704635317
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.952494368
Short name T402
Test name
Test status
Simulation time 5664605104 ps
CPU time 27.61 seconds
Started Jul 22 04:55:54 PM PDT 24
Finished Jul 22 04:56:22 PM PDT 24
Peak memory 218516 kb
Host smart-dc71ac87-83ed-4cb2-8114-a3daefc90fe7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952494368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.952494368
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1375797319
Short name T370
Test name
Test status
Simulation time 8601331566 ps
CPU time 18.87 seconds
Started Jul 22 04:55:54 PM PDT 24
Finished Jul 22 04:56:14 PM PDT 24
Peak memory 215104 kb
Host smart-d1cfe3b4-1a17-4a35-8aff-df0f3ad87ce7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375797319 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1375797319
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.277947443
Short name T418
Test name
Test status
Simulation time 2050791457 ps
CPU time 13.02 seconds
Started Jul 22 04:55:56 PM PDT 24
Finished Jul 22 04:56:09 PM PDT 24
Peak memory 210836 kb
Host smart-21863573-0656-4b50-babb-049c3061bd86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277947443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.277947443
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3233597388
Short name T68
Test name
Test status
Simulation time 28867341916 ps
CPU time 97.44 seconds
Started Jul 22 04:55:54 PM PDT 24
Finished Jul 22 04:57:32 PM PDT 24
Peak memory 214828 kb
Host smart-e0af57bd-79b1-48fe-a5aa-377f31b223c2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233597388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3233597388
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4220175974
Short name T57
Test name
Test status
Simulation time 33652336637 ps
CPU time 27.67 seconds
Started Jul 22 04:55:54 PM PDT 24
Finished Jul 22 04:56:23 PM PDT 24
Peak memory 212596 kb
Host smart-c8ac6a35-3780-48e7-bfb0-62178b82d667
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220175974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.4220175974
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3468173121
Short name T360
Test name
Test status
Simulation time 3164969809 ps
CPU time 20.4 seconds
Started Jul 22 04:55:54 PM PDT 24
Finished Jul 22 04:56:15 PM PDT 24
Peak memory 216880 kb
Host smart-96b85edb-005a-4688-80a3-33f8a9623887
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468173121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3468173121
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1135862514
Short name T422
Test name
Test status
Simulation time 175458173 ps
CPU time 8.65 seconds
Started Jul 22 04:55:52 PM PDT 24
Finished Jul 22 04:56:02 PM PDT 24
Peak memory 215948 kb
Host smart-22fa4240-3d8e-41aa-a82c-c08845c2bc56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135862514 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1135862514
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3403166965
Short name T85
Test name
Test status
Simulation time 8563618064 ps
CPU time 19.54 seconds
Started Jul 22 04:55:53 PM PDT 24
Finished Jul 22 04:56:13 PM PDT 24
Peak memory 212128 kb
Host smart-f801342c-f12f-4454-ae14-e0f80b56ed2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403166965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3403166965
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.55670283
Short name T458
Test name
Test status
Simulation time 693901416 ps
CPU time 38.43 seconds
Started Jul 22 04:57:29 PM PDT 24
Finished Jul 22 04:58:09 PM PDT 24
Peak memory 213632 kb
Host smart-e056e307-a8c2-483c-85b7-c3a1440395e9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55670283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pas
sthru_mem_tl_intg_err.55670283
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3554864875
Short name T451
Test name
Test status
Simulation time 3066664015 ps
CPU time 25.26 seconds
Started Jul 22 04:55:53 PM PDT 24
Finished Jul 22 04:56:18 PM PDT 24
Peak memory 211844 kb
Host smart-07175101-fe9d-4007-80c0-f95e006866c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554864875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3554864875
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3882795342
Short name T363
Test name
Test status
Simulation time 11948702618 ps
CPU time 28.35 seconds
Started Jul 22 04:55:53 PM PDT 24
Finished Jul 22 04:56:22 PM PDT 24
Peak memory 218324 kb
Host smart-386dd4d2-bc89-429c-8dc2-9823fd06f3fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882795342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3882795342
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1237795254
Short name T103
Test name
Test status
Simulation time 3059015870 ps
CPU time 155.75 seconds
Started Jul 22 04:55:57 PM PDT 24
Finished Jul 22 04:58:33 PM PDT 24
Peak memory 213548 kb
Host smart-913f671e-ce9e-471e-a253-630fe232656b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237795254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1237795254
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3758035628
Short name T377
Test name
Test status
Simulation time 698011661 ps
CPU time 8.7 seconds
Started Jul 22 04:55:54 PM PDT 24
Finished Jul 22 04:56:04 PM PDT 24
Peak memory 215304 kb
Host smart-74029654-e88f-4234-bf38-6169fb757ee2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758035628 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3758035628
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2354356672
Short name T90
Test name
Test status
Simulation time 2915019530 ps
CPU time 22.88 seconds
Started Jul 22 04:55:52 PM PDT 24
Finished Jul 22 04:56:16 PM PDT 24
Peak memory 211716 kb
Host smart-9c76d6a3-ce69-45f0-af16-c22ffb97a1d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354356672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2354356672
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.752126894
Short name T92
Test name
Test status
Simulation time 60877302200 ps
CPU time 63.3 seconds
Started Jul 22 04:55:58 PM PDT 24
Finished Jul 22 04:57:02 PM PDT 24
Peak memory 213848 kb
Host smart-792c5ba2-aa3a-4912-8537-414c72d843b8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752126894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.752126894
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4125076761
Short name T403
Test name
Test status
Simulation time 1442567482 ps
CPU time 16.95 seconds
Started Jul 22 04:55:54 PM PDT 24
Finished Jul 22 04:56:12 PM PDT 24
Peak memory 211228 kb
Host smart-a9019cc5-bc26-4aef-b2b8-a9651e68626e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125076761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.4125076761
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4067053158
Short name T368
Test name
Test status
Simulation time 2117789575 ps
CPU time 24.6 seconds
Started Jul 22 04:59:23 PM PDT 24
Finished Jul 22 04:59:48 PM PDT 24
Peak memory 218268 kb
Host smart-d6e97b59-7f25-4e76-9cc9-a7469e513dcd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067053158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.4067053158
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.926050125
Short name T102
Test name
Test status
Simulation time 1982989196 ps
CPU time 152.56 seconds
Started Jul 22 04:56:19 PM PDT 24
Finished Jul 22 04:58:52 PM PDT 24
Peak memory 213796 kb
Host smart-bc8b7ad8-4ce9-4c33-9a97-a62f75c8f305
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926050125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.926050125
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2094483116
Short name T61
Test name
Test status
Simulation time 660426057 ps
CPU time 8.01 seconds
Started Jul 22 04:56:16 PM PDT 24
Finished Jul 22 04:56:25 PM PDT 24
Peak memory 210748 kb
Host smart-fad18394-c5c3-4db0-b712-f29ceafca829
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094483116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2094483116
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2622880054
Short name T398
Test name
Test status
Simulation time 9746400034 ps
CPU time 20.99 seconds
Started Jul 22 04:55:05 PM PDT 24
Finished Jul 22 04:55:26 PM PDT 24
Peak memory 211988 kb
Host smart-920b83d8-eeeb-48c7-9289-5086231d7f4a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622880054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2622880054
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2465864314
Short name T445
Test name
Test status
Simulation time 13990262454 ps
CPU time 31.91 seconds
Started Jul 22 04:55:07 PM PDT 24
Finished Jul 22 04:55:39 PM PDT 24
Peak memory 212004 kb
Host smart-2f10ed08-8540-4877-92eb-4d4f488b342d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465864314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2465864314
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3071527559
Short name T419
Test name
Test status
Simulation time 10181314989 ps
CPU time 23.51 seconds
Started Jul 22 04:55:01 PM PDT 24
Finished Jul 22 04:55:25 PM PDT 24
Peak memory 216300 kb
Host smart-6568a188-3a51-4686-b444-b9a58ed960cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071527559 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3071527559
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3048366722
Short name T373
Test name
Test status
Simulation time 167351036 ps
CPU time 8.11 seconds
Started Jul 22 04:55:07 PM PDT 24
Finished Jul 22 04:55:15 PM PDT 24
Peak memory 210516 kb
Host smart-9ec15118-34ff-42f4-9952-2c2f6354fb74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048366722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3048366722
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.4247126567
Short name T444
Test name
Test status
Simulation time 8395234668 ps
CPU time 32.95 seconds
Started Jul 22 04:55:28 PM PDT 24
Finished Jul 22 04:56:02 PM PDT 24
Peak memory 210716 kb
Host smart-bb449ba7-e486-43cc-a30f-fc65b72f919d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247126567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.4247126567
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3516011830
Short name T414
Test name
Test status
Simulation time 167666619 ps
CPU time 8.21 seconds
Started Jul 22 04:55:01 PM PDT 24
Finished Jul 22 04:55:10 PM PDT 24
Peak memory 210372 kb
Host smart-7a7383b1-6056-42a8-8c23-24ceddbf6df0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516011830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3516011830
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2357662324
Short name T400
Test name
Test status
Simulation time 4516846757 ps
CPU time 21.8 seconds
Started Jul 22 04:56:16 PM PDT 24
Finished Jul 22 04:56:38 PM PDT 24
Peak memory 212620 kb
Host smart-f3027eea-221e-4924-ad85-9af24fea2e12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357662324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2357662324
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.95221981
Short name T415
Test name
Test status
Simulation time 11841423649 ps
CPU time 26.2 seconds
Started Jul 22 04:56:16 PM PDT 24
Finished Jul 22 04:56:43 PM PDT 24
Peak memory 217328 kb
Host smart-405a109d-bd12-4d5a-9693-8eae705994b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95221981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.95221981
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1034713826
Short name T441
Test name
Test status
Simulation time 48438048992 ps
CPU time 92.59 seconds
Started Jul 22 04:55:11 PM PDT 24
Finished Jul 22 04:56:45 PM PDT 24
Peak memory 212764 kb
Host smart-5ef1b858-ada6-4eb7-a3d2-127fa5e2d21c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034713826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1034713826
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2960041565
Short name T421
Test name
Test status
Simulation time 661545763 ps
CPU time 8.28 seconds
Started Jul 22 04:55:12 PM PDT 24
Finished Jul 22 04:55:21 PM PDT 24
Peak memory 210516 kb
Host smart-6eb972dc-b45f-4c73-9347-e327f55e3f98
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960041565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2960041565
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.675836403
Short name T430
Test name
Test status
Simulation time 2355156781 ps
CPU time 8.26 seconds
Started Jul 22 04:55:11 PM PDT 24
Finished Jul 22 04:55:20 PM PDT 24
Peak memory 210516 kb
Host smart-4e176c3b-4050-4f41-a1b1-8398b9f61983
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675836403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.675836403
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.4016998137
Short name T81
Test name
Test status
Simulation time 5433431136 ps
CPU time 28.64 seconds
Started Jul 22 04:55:12 PM PDT 24
Finished Jul 22 04:55:41 PM PDT 24
Peak memory 210712 kb
Host smart-d42d87c0-07db-406e-b098-9fef1d0c84bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016998137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.4016998137
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1647743700
Short name T383
Test name
Test status
Simulation time 2665012364 ps
CPU time 13.49 seconds
Started Jul 22 04:55:13 PM PDT 24
Finished Jul 22 04:55:27 PM PDT 24
Peak memory 218836 kb
Host smart-bab65d0a-9544-49e3-a5f3-0fd5ce0c62cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647743700 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1647743700
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1911726172
Short name T366
Test name
Test status
Simulation time 689302292 ps
CPU time 8.31 seconds
Started Jul 22 04:55:11 PM PDT 24
Finished Jul 22 04:55:20 PM PDT 24
Peak memory 210888 kb
Host smart-dc9da93c-f9fb-4296-95c4-9153281cd5c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911726172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1911726172
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2167595209
Short name T459
Test name
Test status
Simulation time 636318026 ps
CPU time 8.14 seconds
Started Jul 22 04:55:13 PM PDT 24
Finished Jul 22 04:55:21 PM PDT 24
Peak memory 210372 kb
Host smart-ca38dde2-c4bf-4720-942f-16586159c603
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167595209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2167595209
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.674511418
Short name T371
Test name
Test status
Simulation time 9016439166 ps
CPU time 24.13 seconds
Started Jul 22 04:55:14 PM PDT 24
Finished Jul 22 04:55:38 PM PDT 24
Peak memory 210488 kb
Host smart-61e2692c-e29d-4cbc-9147-5c21994bf6fc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674511418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
674511418
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.975906585
Short name T62
Test name
Test status
Simulation time 98401150110 ps
CPU time 170.34 seconds
Started Jul 22 04:55:00 PM PDT 24
Finished Jul 22 04:57:51 PM PDT 24
Peak memory 214952 kb
Host smart-5f7945eb-806c-4ae2-8be0-7c6377cfaaf8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975906585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.975906585
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2697526209
Short name T65
Test name
Test status
Simulation time 352811336 ps
CPU time 8.16 seconds
Started Jul 22 04:56:05 PM PDT 24
Finished Jul 22 04:56:14 PM PDT 24
Peak memory 210888 kb
Host smart-54b3fc6f-d010-4888-84b6-6845ba2fd243
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697526209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2697526209
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.873030075
Short name T396
Test name
Test status
Simulation time 4259455072 ps
CPU time 36.5 seconds
Started Jul 22 04:55:17 PM PDT 24
Finished Jul 22 04:55:54 PM PDT 24
Peak memory 218236 kb
Host smart-5d9314fc-56fb-4cec-90b9-050d35f644c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873030075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.873030075
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.4094194830
Short name T453
Test name
Test status
Simulation time 15719208421 ps
CPU time 22.11 seconds
Started Jul 22 04:56:06 PM PDT 24
Finished Jul 22 04:56:29 PM PDT 24
Peak memory 212000 kb
Host smart-36a13a17-e8b6-4ea4-8079-75cd6ab8d54d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094194830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.4094194830
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1980895381
Short name T446
Test name
Test status
Simulation time 1897023027 ps
CPU time 14.47 seconds
Started Jul 22 04:56:07 PM PDT 24
Finished Jul 22 04:56:22 PM PDT 24
Peak memory 210516 kb
Host smart-76038c8e-e85f-4157-8613-062d38c01fa9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980895381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1980895381
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.380625045
Short name T86
Test name
Test status
Simulation time 12095421355 ps
CPU time 37.42 seconds
Started Jul 22 04:55:14 PM PDT 24
Finished Jul 22 04:55:52 PM PDT 24
Peak memory 212040 kb
Host smart-7ecaf7a9-cd66-4805-aed4-f32211f70761
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380625045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.380625045
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.762048226
Short name T429
Test name
Test status
Simulation time 11294848014 ps
CPU time 25.07 seconds
Started Jul 22 04:55:12 PM PDT 24
Finished Jul 22 04:55:38 PM PDT 24
Peak memory 217116 kb
Host smart-ef94cbcb-558b-4024-a014-935b373fd1b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762048226 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.762048226
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.230195187
Short name T369
Test name
Test status
Simulation time 3382320898 ps
CPU time 27.71 seconds
Started Jul 22 04:55:11 PM PDT 24
Finished Jul 22 04:55:40 PM PDT 24
Peak memory 211248 kb
Host smart-1c17a0fb-b472-4375-921d-d64538455f63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230195187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.230195187
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1053838431
Short name T408
Test name
Test status
Simulation time 11726308280 ps
CPU time 25.91 seconds
Started Jul 22 04:55:14 PM PDT 24
Finished Jul 22 04:55:40 PM PDT 24
Peak memory 210764 kb
Host smart-a224334a-f25b-4f40-86bc-ca6e9c54e789
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053838431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1053838431
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.528979352
Short name T416
Test name
Test status
Simulation time 4029823885 ps
CPU time 29.57 seconds
Started Jul 22 04:55:12 PM PDT 24
Finished Jul 22 04:55:42 PM PDT 24
Peak memory 210424 kb
Host smart-083666ad-0c70-4ee5-9729-4513e209cfcd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528979352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
528979352
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.519977930
Short name T405
Test name
Test status
Simulation time 15124978183 ps
CPU time 58.46 seconds
Started Jul 22 04:55:17 PM PDT 24
Finished Jul 22 04:56:16 PM PDT 24
Peak memory 213684 kb
Host smart-e8204e2f-d801-4f2c-abfa-47a861bc5a1f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519977930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.519977930
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.452667108
Short name T387
Test name
Test status
Simulation time 5844493504 ps
CPU time 23.47 seconds
Started Jul 22 04:55:13 PM PDT 24
Finished Jul 22 04:55:37 PM PDT 24
Peak memory 212440 kb
Host smart-0f4ef519-1c96-4ea3-aac9-7bda586271b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452667108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.452667108
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1299093680
Short name T393
Test name
Test status
Simulation time 3413678798 ps
CPU time 16.84 seconds
Started Jul 22 04:55:15 PM PDT 24
Finished Jul 22 04:55:32 PM PDT 24
Peak memory 216996 kb
Host smart-9b9b02e3-1fc7-4403-b4e8-e7f7d5b5362b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299093680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1299093680
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4274206658
Short name T98
Test name
Test status
Simulation time 1665710742 ps
CPU time 82.04 seconds
Started Jul 22 04:56:05 PM PDT 24
Finished Jul 22 04:57:28 PM PDT 24
Peak memory 213124 kb
Host smart-67129e0f-ee62-4cef-943c-2fd2b0bb6f40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274206658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.4274206658
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1733755264
Short name T386
Test name
Test status
Simulation time 2462957187 ps
CPU time 22.37 seconds
Started Jul 22 04:55:21 PM PDT 24
Finished Jul 22 04:55:44 PM PDT 24
Peak memory 216292 kb
Host smart-025037bb-5702-45c6-9aa7-b46345f7be0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733755264 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1733755264
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.532045205
Short name T420
Test name
Test status
Simulation time 2058498200 ps
CPU time 8.29 seconds
Started Jul 22 04:55:22 PM PDT 24
Finished Jul 22 04:55:31 PM PDT 24
Peak memory 210552 kb
Host smart-078448fe-b66f-4648-a932-d4326b30f8b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532045205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.532045205
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2388587508
Short name T77
Test name
Test status
Simulation time 67818117796 ps
CPU time 170.41 seconds
Started Jul 22 04:55:12 PM PDT 24
Finished Jul 22 04:58:03 PM PDT 24
Peak memory 215164 kb
Host smart-e8883be8-3079-44cd-991d-89d0343b839e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388587508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2388587508
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3479134322
Short name T410
Test name
Test status
Simulation time 15529292702 ps
CPU time 35.29 seconds
Started Jul 22 04:55:19 PM PDT 24
Finished Jul 22 04:55:55 PM PDT 24
Peak memory 212760 kb
Host smart-6d6b1b6c-d399-4c77-a922-683e55e093d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479134322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3479134322
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2889242534
Short name T413
Test name
Test status
Simulation time 1757079827 ps
CPU time 19.28 seconds
Started Jul 22 04:55:21 PM PDT 24
Finished Jul 22 04:55:41 PM PDT 24
Peak memory 216836 kb
Host smart-6c976682-d3c5-4f7a-94f2-901d359f43ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889242534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2889242534
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1106732675
Short name T404
Test name
Test status
Simulation time 2870858359 ps
CPU time 89.39 seconds
Started Jul 22 04:55:23 PM PDT 24
Finished Jul 22 04:56:53 PM PDT 24
Peak memory 213512 kb
Host smart-e3e39ba3-88f2-49f3-b47c-313c2d70c771
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106732675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1106732675
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2770650212
Short name T399
Test name
Test status
Simulation time 1343324954 ps
CPU time 10.45 seconds
Started Jul 22 04:55:21 PM PDT 24
Finished Jul 22 04:55:32 PM PDT 24
Peak memory 214000 kb
Host smart-ff28fa26-2414-4aaa-b0eb-a8237c579140
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770650212 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2770650212
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1560347352
Short name T88
Test name
Test status
Simulation time 6111077300 ps
CPU time 26.89 seconds
Started Jul 22 04:55:20 PM PDT 24
Finished Jul 22 04:55:47 PM PDT 24
Peak memory 211548 kb
Host smart-5aaf2e11-e3bb-43ff-8f34-dfb227db1081
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560347352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1560347352
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2734270365
Short name T447
Test name
Test status
Simulation time 10855388676 ps
CPU time 121.04 seconds
Started Jul 22 04:55:29 PM PDT 24
Finished Jul 22 04:57:32 PM PDT 24
Peak memory 215420 kb
Host smart-421bdfcf-b608-4fef-b1cc-ef7639d25840
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734270365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2734270365
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1154210423
Short name T70
Test name
Test status
Simulation time 1971611547 ps
CPU time 11.39 seconds
Started Jul 22 04:55:23 PM PDT 24
Finished Jul 22 04:55:35 PM PDT 24
Peak memory 210480 kb
Host smart-9a09f502-8786-4fc3-b6fd-4c75a0d77549
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154210423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1154210423
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1147815096
Short name T452
Test name
Test status
Simulation time 3409666102 ps
CPU time 16.79 seconds
Started Jul 22 04:55:21 PM PDT 24
Finished Jul 22 04:55:38 PM PDT 24
Peak memory 218156 kb
Host smart-c4fdc9f4-6a1a-45b1-9f2d-4abb72534ff1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147815096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1147815096
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.271955902
Short name T106
Test name
Test status
Simulation time 5170794770 ps
CPU time 93.63 seconds
Started Jul 22 04:55:20 PM PDT 24
Finished Jul 22 04:56:54 PM PDT 24
Peak memory 213592 kb
Host smart-74d65810-e2cd-43a1-a1f9-b477d753d4ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271955902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.271955902
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.585350210
Short name T425
Test name
Test status
Simulation time 676629959 ps
CPU time 8.94 seconds
Started Jul 22 04:56:13 PM PDT 24
Finished Jul 22 04:56:23 PM PDT 24
Peak memory 216320 kb
Host smart-28671dcf-1556-4a3b-bdf9-bd1f8e72ceec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585350210 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.585350210
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.491642336
Short name T384
Test name
Test status
Simulation time 17398165992 ps
CPU time 25.52 seconds
Started Jul 22 04:55:20 PM PDT 24
Finished Jul 22 04:55:46 PM PDT 24
Peak memory 211796 kb
Host smart-0eb2fdef-1cf6-4ed7-8e33-1403767e2083
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491642336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.491642336
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2658714416
Short name T412
Test name
Test status
Simulation time 18465410739 ps
CPU time 90.27 seconds
Started Jul 22 04:55:22 PM PDT 24
Finished Jul 22 04:56:52 PM PDT 24
Peak memory 213768 kb
Host smart-50876ef6-5561-41c4-ada3-7b7aa45d307b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658714416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2658714416
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1026713758
Short name T417
Test name
Test status
Simulation time 4339037426 ps
CPU time 23.68 seconds
Started Jul 22 04:55:20 PM PDT 24
Finished Jul 22 04:55:44 PM PDT 24
Peak memory 212580 kb
Host smart-84bd797d-1e47-4041-9207-ca22c23ffa7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026713758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1026713758
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2701304449
Short name T382
Test name
Test status
Simulation time 13144191375 ps
CPU time 34.78 seconds
Started Jul 22 04:55:21 PM PDT 24
Finished Jul 22 04:55:57 PM PDT 24
Peak memory 217388 kb
Host smart-96194250-5479-4366-9081-54e9840935a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701304449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2701304449
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.235885384
Short name T442
Test name
Test status
Simulation time 4022649005 ps
CPU time 171.45 seconds
Started Jul 22 04:55:21 PM PDT 24
Finished Jul 22 04:58:13 PM PDT 24
Peak memory 212748 kb
Host smart-a4b54249-4d1f-4902-9c77-5e7020470418
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235885384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.235885384
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.863752284
Short name T426
Test name
Test status
Simulation time 7068141760 ps
CPU time 28.73 seconds
Started Jul 22 04:55:22 PM PDT 24
Finished Jul 22 04:55:51 PM PDT 24
Peak memory 218180 kb
Host smart-2397cc3e-ca41-4c09-a07e-a639c02f7ab2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863752284 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.863752284
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1578946986
Short name T381
Test name
Test status
Simulation time 2101963696 ps
CPU time 14.29 seconds
Started Jul 22 04:55:22 PM PDT 24
Finished Jul 22 04:55:37 PM PDT 24
Peak memory 210472 kb
Host smart-f2d019b3-01bb-42be-8766-66ce4de5604b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578946986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1578946986
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.393233625
Short name T79
Test name
Test status
Simulation time 12484848193 ps
CPU time 75.26 seconds
Started Jul 22 04:55:22 PM PDT 24
Finished Jul 22 04:56:38 PM PDT 24
Peak memory 215224 kb
Host smart-47e4f28c-d832-4956-b92f-ae561a5127e1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393233625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.393233625
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1594246924
Short name T432
Test name
Test status
Simulation time 11654095863 ps
CPU time 25.24 seconds
Started Jul 22 04:55:21 PM PDT 24
Finished Jul 22 04:55:47 PM PDT 24
Peak memory 212540 kb
Host smart-8e11a513-b320-441c-9985-07ea5d56ce27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594246924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1594246924
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.499192213
Short name T409
Test name
Test status
Simulation time 7652858078 ps
CPU time 19.29 seconds
Started Jul 22 04:55:21 PM PDT 24
Finished Jul 22 04:55:40 PM PDT 24
Peak memory 216460 kb
Host smart-e23b354a-0e94-4351-bc36-e8b111b7dac7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499192213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.499192213
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3707670879
Short name T367
Test name
Test status
Simulation time 2133756388 ps
CPU time 20.25 seconds
Started Jul 22 04:55:31 PM PDT 24
Finished Jul 22 04:55:52 PM PDT 24
Peak memory 216668 kb
Host smart-2545761c-e589-4fbf-af53-2267d8a8b2e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707670879 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3707670879
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1887528325
Short name T80
Test name
Test status
Simulation time 262350038 ps
CPU time 9.35 seconds
Started Jul 22 04:57:15 PM PDT 24
Finished Jul 22 04:57:25 PM PDT 24
Peak memory 210468 kb
Host smart-1b501425-1141-470c-ae35-972167d42481
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887528325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1887528325
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.104823186
Short name T401
Test name
Test status
Simulation time 8264447931 ps
CPU time 94.67 seconds
Started Jul 22 04:55:30 PM PDT 24
Finished Jul 22 04:57:06 PM PDT 24
Peak memory 215552 kb
Host smart-36797195-ced9-41b8-86ab-b91abae777aa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104823186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.104823186
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2508498148
Short name T66
Test name
Test status
Simulation time 826852702 ps
CPU time 8.24 seconds
Started Jul 22 04:55:29 PM PDT 24
Finished Jul 22 04:55:39 PM PDT 24
Peak memory 211104 kb
Host smart-a6e66689-8e15-4cc0-adc5-666c433af732
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508498148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2508498148
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.863913113
Short name T385
Test name
Test status
Simulation time 8201917555 ps
CPU time 26.06 seconds
Started Jul 22 04:55:30 PM PDT 24
Finished Jul 22 04:55:57 PM PDT 24
Peak memory 217684 kb
Host smart-93d7eea0-020c-41f7-aa50-9bff4a87d4a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863913113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.863913113
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2287365433
Short name T105
Test name
Test status
Simulation time 7730265313 ps
CPU time 99.06 seconds
Started Jul 22 04:55:31 PM PDT 24
Finished Jul 22 04:57:11 PM PDT 24
Peak memory 213840 kb
Host smart-8b368ffe-368f-47ef-b555-0743a3e0f214
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287365433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2287365433
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1211854390
Short name T34
Test name
Test status
Simulation time 5890056240 ps
CPU time 11.51 seconds
Started Jul 22 04:52:21 PM PDT 24
Finished Jul 22 04:52:34 PM PDT 24
Peak memory 217312 kb
Host smart-b0c5c689-5aee-4f1b-90fc-5a8f45c3082b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211854390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1211854390
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3714261888
Short name T37
Test name
Test status
Simulation time 245946562315 ps
CPU time 616.12 seconds
Started Jul 22 04:53:53 PM PDT 24
Finished Jul 22 05:04:10 PM PDT 24
Peak memory 233420 kb
Host smart-8d493f29-d204-4b52-971d-675489ef9a38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714261888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3714261888
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.288223592
Short name T277
Test name
Test status
Simulation time 34965482295 ps
CPU time 51.37 seconds
Started Jul 22 04:52:21 PM PDT 24
Finished Jul 22 04:53:13 PM PDT 24
Peak memory 219332 kb
Host smart-01c45e2a-66a4-4563-ac6e-822f1ef3740b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288223592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.288223592
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1081582395
Short name T207
Test name
Test status
Simulation time 17140649770 ps
CPU time 32.3 seconds
Started Jul 22 04:52:21 PM PDT 24
Finished Jul 22 04:52:54 PM PDT 24
Peak memory 219288 kb
Host smart-f4dfaec4-e00d-4d33-92bb-3cb2c542d9f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1081582395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1081582395
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.66054902
Short name T26
Test name
Test status
Simulation time 11483384967 ps
CPU time 239.71 seconds
Started Jul 22 04:52:21 PM PDT 24
Finished Jul 22 04:56:21 PM PDT 24
Peak memory 238204 kb
Host smart-a3cbc4d4-1d6b-483c-a658-b4a06b68e625
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66054902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.66054902
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3509992463
Short name T220
Test name
Test status
Simulation time 693993972 ps
CPU time 19.34 seconds
Started Jul 22 04:52:20 PM PDT 24
Finished Jul 22 04:52:40 PM PDT 24
Peak memory 216060 kb
Host smart-3a1227be-0e91-4149-b8d3-22ad4fd56cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509992463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3509992463
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.117747065
Short name T186
Test name
Test status
Simulation time 22099442611 ps
CPU time 64.27 seconds
Started Jul 22 04:52:20 PM PDT 24
Finished Jul 22 04:53:25 PM PDT 24
Peak memory 219304 kb
Host smart-6481c720-e089-4976-8604-e7af149eba8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117747065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.117747065
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.691866219
Short name T146
Test name
Test status
Simulation time 4430995183 ps
CPU time 22.46 seconds
Started Jul 22 04:52:29 PM PDT 24
Finished Jul 22 04:52:51 PM PDT 24
Peak memory 216872 kb
Host smart-45a68568-5379-4fab-8e23-467baf1e5fa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691866219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.691866219
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.274415763
Short name T31
Test name
Test status
Simulation time 69576900611 ps
CPU time 699.81 seconds
Started Jul 22 04:52:23 PM PDT 24
Finished Jul 22 05:04:03 PM PDT 24
Peak memory 225804 kb
Host smart-1c5c2e7c-4b7e-4d55-86db-acea8eda2671
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274415763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.274415763
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2179028986
Short name T217
Test name
Test status
Simulation time 6903024222 ps
CPU time 58.52 seconds
Started Jul 22 04:54:59 PM PDT 24
Finished Jul 22 04:55:58 PM PDT 24
Peak memory 219292 kb
Host smart-c8de9ae4-ae71-4413-be73-6df69f5e7cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179028986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2179028986
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.998396447
Short name T147
Test name
Test status
Simulation time 2025210757 ps
CPU time 21.82 seconds
Started Jul 22 04:52:22 PM PDT 24
Finished Jul 22 04:52:44 PM PDT 24
Peak memory 211268 kb
Host smart-cfc9683b-701d-4ee0-aeb9-cda653ad7cbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=998396447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.998396447
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1845378081
Short name T28
Test name
Test status
Simulation time 3284763017 ps
CPU time 239.42 seconds
Started Jul 22 04:52:26 PM PDT 24
Finished Jul 22 04:56:26 PM PDT 24
Peak memory 237900 kb
Host smart-458e677e-e7af-438d-9186-0f34dc6ad243
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845378081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1845378081
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1345783987
Short name T330
Test name
Test status
Simulation time 8393890286 ps
CPU time 73.19 seconds
Started Jul 22 04:52:23 PM PDT 24
Finished Jul 22 04:53:36 PM PDT 24
Peak memory 217020 kb
Host smart-4f08533e-9b8f-4ecf-ade9-7ba307a1fe3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345783987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1345783987
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1942272663
Short name T347
Test name
Test status
Simulation time 11544303457 ps
CPU time 147.03 seconds
Started Jul 22 04:54:09 PM PDT 24
Finished Jul 22 04:56:37 PM PDT 24
Peak memory 220840 kb
Host smart-17ea2a00-3d4b-44d8-946e-fc17e633621c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942272663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1942272663
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3095390915
Short name T342
Test name
Test status
Simulation time 8514103516 ps
CPU time 21.74 seconds
Started Jul 22 04:52:44 PM PDT 24
Finished Jul 22 04:53:07 PM PDT 24
Peak memory 213252 kb
Host smart-4e758ce4-af84-44c1-b345-32cba9c236bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095390915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3095390915
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2940779189
Short name T344
Test name
Test status
Simulation time 5633186207 ps
CPU time 170.2 seconds
Started Jul 22 04:52:43 PM PDT 24
Finished Jul 22 04:55:35 PM PDT 24
Peak memory 238952 kb
Host smart-80d4497e-b571-4217-9724-1d876cd31ee4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940779189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2940779189
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.218549589
Short name T195
Test name
Test status
Simulation time 8303662304 ps
CPU time 52.83 seconds
Started Jul 22 04:52:42 PM PDT 24
Finished Jul 22 04:53:35 PM PDT 24
Peak memory 219328 kb
Host smart-edb6d33c-fa9c-493b-99eb-28d4f1ecb8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218549589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.218549589
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.405755951
Short name T229
Test name
Test status
Simulation time 8237376558 ps
CPU time 22.91 seconds
Started Jul 22 04:52:43 PM PDT 24
Finished Jul 22 04:53:08 PM PDT 24
Peak memory 219356 kb
Host smart-23d7a5c9-4897-4355-a5b7-192786118795
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=405755951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.405755951
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.427298379
Short name T33
Test name
Test status
Simulation time 353075985 ps
CPU time 20.28 seconds
Started Jul 22 04:52:45 PM PDT 24
Finished Jul 22 04:53:06 PM PDT 24
Peak memory 218688 kb
Host smart-f8ef81dc-059f-4d30-9d9c-ddebd5384045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427298379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.427298379
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.4016112001
Short name T264
Test name
Test status
Simulation time 4898926998 ps
CPU time 78.01 seconds
Started Jul 22 04:52:42 PM PDT 24
Finished Jul 22 04:54:01 PM PDT 24
Peak memory 220060 kb
Host smart-a3591163-8d80-4c3b-b4cf-f1c80e737cd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016112001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.4016112001
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2204585156
Short name T223
Test name
Test status
Simulation time 343023240 ps
CPU time 9.94 seconds
Started Jul 22 04:52:43 PM PDT 24
Finished Jul 22 04:52:55 PM PDT 24
Peak memory 217116 kb
Host smart-c214b0e9-c3ed-49ea-b425-8c8782c4f760
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204585156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2204585156
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.216029880
Short name T117
Test name
Test status
Simulation time 45700570473 ps
CPU time 479.7 seconds
Started Jul 22 04:54:47 PM PDT 24
Finished Jul 22 05:02:48 PM PDT 24
Peak memory 234592 kb
Host smart-369769f6-ad72-49d8-a050-b2d7c929400a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216029880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.216029880
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.218775686
Short name T270
Test name
Test status
Simulation time 15715555382 ps
CPU time 64.75 seconds
Started Jul 22 04:54:47 PM PDT 24
Finished Jul 22 04:55:52 PM PDT 24
Peak memory 219288 kb
Host smart-468134c3-5798-41db-abb5-938dcb8bcb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218775686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.218775686
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.361306305
Short name T333
Test name
Test status
Simulation time 3330142917 ps
CPU time 29.06 seconds
Started Jul 22 04:52:42 PM PDT 24
Finished Jul 22 04:53:13 PM PDT 24
Peak memory 211348 kb
Host smart-7d81c556-6146-4795-9fb2-355a53ac643e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=361306305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.361306305
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2296327653
Short name T222
Test name
Test status
Simulation time 4290409057 ps
CPU time 42.23 seconds
Started Jul 22 04:52:43 PM PDT 24
Finished Jul 22 04:53:27 PM PDT 24
Peak memory 216328 kb
Host smart-462c4bc1-e0f9-4b2d-9a82-2f94481f2ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296327653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2296327653
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2095833365
Short name T269
Test name
Test status
Simulation time 2035388996 ps
CPU time 51.56 seconds
Started Jul 22 04:54:48 PM PDT 24
Finished Jul 22 04:55:40 PM PDT 24
Peak memory 219280 kb
Host smart-b914bbb1-3be2-46b8-8d31-bf6dc4e91c9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095833365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2095833365
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.193410369
Short name T291
Test name
Test status
Simulation time 174305442 ps
CPU time 8.29 seconds
Started Jul 22 04:55:33 PM PDT 24
Finished Jul 22 04:55:42 PM PDT 24
Peak memory 217004 kb
Host smart-c373d16b-b351-4bd2-a2f0-ef414cedd4cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193410369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.193410369
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2662208623
Short name T148
Test name
Test status
Simulation time 2514297641 ps
CPU time 144.83 seconds
Started Jul 22 04:53:21 PM PDT 24
Finished Jul 22 04:55:46 PM PDT 24
Peak memory 234528 kb
Host smart-901ad2f9-26f9-47b8-a228-8608cf54ed08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662208623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2662208623
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3936369401
Short name T120
Test name
Test status
Simulation time 5559959132 ps
CPU time 27.4 seconds
Started Jul 22 04:52:51 PM PDT 24
Finished Jul 22 04:53:19 PM PDT 24
Peak memory 217936 kb
Host smart-ba8a94f7-1327-4849-86a3-b90f6d798163
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3936369401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3936369401
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2143986357
Short name T196
Test name
Test status
Simulation time 11883339354 ps
CPU time 63.53 seconds
Started Jul 22 04:52:52 PM PDT 24
Finished Jul 22 04:53:56 PM PDT 24
Peak memory 219308 kb
Host smart-2e1d74ec-95b6-4501-85ac-0cf861fc3c0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143986357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2143986357
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3595392371
Short name T221
Test name
Test status
Simulation time 167430451 ps
CPU time 8.28 seconds
Started Jul 22 04:52:59 PM PDT 24
Finished Jul 22 04:53:08 PM PDT 24
Peak memory 217128 kb
Host smart-0fe7392e-bff5-405b-97d3-07e8c90ce109
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595392371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3595392371
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.124183049
Short name T247
Test name
Test status
Simulation time 98705969735 ps
CPU time 336.85 seconds
Started Jul 22 04:52:52 PM PDT 24
Finished Jul 22 04:58:29 PM PDT 24
Peak memory 233284 kb
Host smart-25424ca5-13fc-40dd-b928-da08144daf0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124183049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_c
orrupt_sig_fatal_chk.124183049
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3289675719
Short name T191
Test name
Test status
Simulation time 6190842676 ps
CPU time 25.43 seconds
Started Jul 22 04:55:33 PM PDT 24
Finished Jul 22 04:55:59 PM PDT 24
Peak memory 219272 kb
Host smart-c7b7fdc3-499e-4e4e-9280-0a35ffe3f998
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3289675719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3289675719
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3686007754
Short name T149
Test name
Test status
Simulation time 10573301045 ps
CPU time 92.24 seconds
Started Jul 22 04:52:52 PM PDT 24
Finished Jul 22 04:54:24 PM PDT 24
Peak memory 219316 kb
Host smart-0c632375-bf96-4f60-8400-0282964f5232
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686007754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3686007754
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2974168075
Short name T170
Test name
Test status
Simulation time 5666250978 ps
CPU time 25.31 seconds
Started Jul 22 04:53:00 PM PDT 24
Finished Jul 22 04:53:26 PM PDT 24
Peak memory 213324 kb
Host smart-f40fca96-c743-43a6-9f45-9201819af985
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974168075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2974168075
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2148398118
Short name T153
Test name
Test status
Simulation time 56026827308 ps
CPU time 653.01 seconds
Started Jul 22 04:52:59 PM PDT 24
Finished Jul 22 05:03:53 PM PDT 24
Peak memory 219464 kb
Host smart-a7b90d70-09d1-4416-ac4d-566c5baacf4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148398118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2148398118
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3572926520
Short name T242
Test name
Test status
Simulation time 17045435232 ps
CPU time 45.89 seconds
Started Jul 22 04:53:00 PM PDT 24
Finished Jul 22 04:53:46 PM PDT 24
Peak memory 219328 kb
Host smart-36e77cb5-5f09-4920-b988-6c6d5a6ff912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572926520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3572926520
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3746338190
Short name T312
Test name
Test status
Simulation time 5755704936 ps
CPU time 22.83 seconds
Started Jul 22 04:52:59 PM PDT 24
Finished Jul 22 04:53:22 PM PDT 24
Peak memory 219312 kb
Host smart-c9d554df-253f-4d2e-aa9d-fb4011be78a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3746338190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3746338190
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3581622552
Short name T315
Test name
Test status
Simulation time 4693942259 ps
CPU time 50.72 seconds
Started Jul 22 04:53:04 PM PDT 24
Finished Jul 22 04:53:55 PM PDT 24
Peak memory 216700 kb
Host smart-48d90f59-a311-4bef-b33c-3d22be78f85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581622552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3581622552
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1430932375
Short name T164
Test name
Test status
Simulation time 57903335644 ps
CPU time 178.04 seconds
Started Jul 22 04:52:58 PM PDT 24
Finished Jul 22 04:55:57 PM PDT 24
Peak memory 219948 kb
Host smart-cea8f8e3-29c1-4608-a988-0f3c62970e44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430932375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1430932375
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1326493901
Short name T349
Test name
Test status
Simulation time 94838627509 ps
CPU time 945.79 seconds
Started Jul 22 04:52:59 PM PDT 24
Finished Jul 22 05:08:45 PM PDT 24
Peak memory 233320 kb
Host smart-4f60ac50-7469-44cd-ac24-bcedf6eee4aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326493901 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.1326493901
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1591296049
Short name T281
Test name
Test status
Simulation time 10040329477 ps
CPU time 24.78 seconds
Started Jul 22 04:53:11 PM PDT 24
Finished Jul 22 04:53:36 PM PDT 24
Peak memory 213308 kb
Host smart-3b5f3a98-fe29-400e-b929-0b59eb1fed51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591296049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1591296049
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2663172913
Short name T112
Test name
Test status
Simulation time 12462194925 ps
CPU time 42.63 seconds
Started Jul 22 04:53:12 PM PDT 24
Finished Jul 22 04:53:55 PM PDT 24
Peak memory 219268 kb
Host smart-30c1ad2c-f969-4c5f-9970-3445cb14906b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663172913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2663172913
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2014359090
Short name T130
Test name
Test status
Simulation time 10206155666 ps
CPU time 34.59 seconds
Started Jul 22 04:53:04 PM PDT 24
Finished Jul 22 04:53:39 PM PDT 24
Peak memory 219340 kb
Host smart-48784d4a-ae86-4001-bc95-32bc262b3579
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2014359090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2014359090
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3802363919
Short name T234
Test name
Test status
Simulation time 21899664151 ps
CPU time 45.41 seconds
Started Jul 22 04:52:59 PM PDT 24
Finished Jul 22 04:53:45 PM PDT 24
Peak memory 215808 kb
Host smart-b3e8102c-17de-4805-ad86-b72a628a8a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802363919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3802363919
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3206937701
Short name T232
Test name
Test status
Simulation time 11255822603 ps
CPU time 24.56 seconds
Started Jul 22 04:53:10 PM PDT 24
Finished Jul 22 04:53:35 PM PDT 24
Peak memory 217472 kb
Host smart-e3155de5-a1c9-4831-b1a6-0ecd750e06a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206937701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3206937701
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3505651950
Short name T319
Test name
Test status
Simulation time 48155125073 ps
CPU time 446.44 seconds
Started Jul 22 04:53:10 PM PDT 24
Finished Jul 22 05:00:37 PM PDT 24
Peak memory 233780 kb
Host smart-33796938-25bb-4da3-848f-a202626d3a94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505651950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3505651950
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3945254777
Short name T296
Test name
Test status
Simulation time 5227725658 ps
CPU time 50.55 seconds
Started Jul 22 04:53:15 PM PDT 24
Finished Jul 22 04:54:06 PM PDT 24
Peak memory 219308 kb
Host smart-3b6b8dfc-0330-4eb5-84e9-c08463855676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945254777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3945254777
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3893752278
Short name T283
Test name
Test status
Simulation time 644594824 ps
CPU time 10.23 seconds
Started Jul 22 04:53:11 PM PDT 24
Finished Jul 22 04:53:22 PM PDT 24
Peak memory 219284 kb
Host smart-a2861020-4dca-4e3d-aee8-1cf0d1ca302a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3893752278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3893752278
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.186321171
Short name T159
Test name
Test status
Simulation time 11020940989 ps
CPU time 42.18 seconds
Started Jul 22 04:53:12 PM PDT 24
Finished Jul 22 04:53:55 PM PDT 24
Peak memory 216108 kb
Host smart-2c31684d-3288-4895-b600-885e7a1cc69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186321171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.186321171
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1116642047
Short name T72
Test name
Test status
Simulation time 12844083769 ps
CPU time 118.65 seconds
Started Jul 22 04:53:14 PM PDT 24
Finished Jul 22 04:55:13 PM PDT 24
Peak memory 218896 kb
Host smart-7054ebc8-78ff-4887-9fb6-967f53c5e143
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116642047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1116642047
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.4223147207
Short name T280
Test name
Test status
Simulation time 6428442538 ps
CPU time 26.78 seconds
Started Jul 22 04:53:13 PM PDT 24
Finished Jul 22 04:53:40 PM PDT 24
Peak memory 217416 kb
Host smart-e6b6eac1-d26a-473b-9963-f59ac00bca6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223147207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.4223147207
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2571760506
Short name T142
Test name
Test status
Simulation time 66276943743 ps
CPU time 622.8 seconds
Started Jul 22 04:53:26 PM PDT 24
Finished Jul 22 05:03:50 PM PDT 24
Peak memory 225716 kb
Host smart-1569c125-5bb2-4266-9cc8-2e95fcab4709
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571760506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2571760506
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.4195978412
Short name T323
Test name
Test status
Simulation time 827099406 ps
CPU time 18.55 seconds
Started Jul 22 04:53:11 PM PDT 24
Finished Jul 22 04:53:30 PM PDT 24
Peak memory 219228 kb
Host smart-d0fe68c1-a5d3-4f8c-a853-2e7fe3cdec23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195978412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.4195978412
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2346233559
Short name T22
Test name
Test status
Simulation time 565361177 ps
CPU time 13.39 seconds
Started Jul 22 04:53:11 PM PDT 24
Finished Jul 22 04:53:24 PM PDT 24
Peak memory 218512 kb
Host smart-62f80cee-2bb4-4548-8c59-1775ccbaac0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2346233559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2346233559
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3649811222
Short name T150
Test name
Test status
Simulation time 10547306656 ps
CPU time 51.04 seconds
Started Jul 22 04:53:11 PM PDT 24
Finished Jul 22 04:54:03 PM PDT 24
Peak memory 216956 kb
Host smart-b3337fbe-2147-4584-a2df-9e4945ba00d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649811222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3649811222
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.19635283
Short name T284
Test name
Test status
Simulation time 713684859 ps
CPU time 42.75 seconds
Started Jul 22 04:53:12 PM PDT 24
Finished Jul 22 04:53:55 PM PDT 24
Peak memory 219736 kb
Host smart-ddf58b05-d1ed-4351-9c2f-5fff30906915
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19635283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 17.rom_ctrl_stress_all.19635283
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1565905968
Short name T204
Test name
Test status
Simulation time 167464507 ps
CPU time 8.44 seconds
Started Jul 22 04:55:04 PM PDT 24
Finished Jul 22 04:55:13 PM PDT 24
Peak memory 217024 kb
Host smart-a2e12503-11d4-4750-aa19-da4dc01396af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565905968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1565905968
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2073307930
Short name T327
Test name
Test status
Simulation time 131021987743 ps
CPU time 676.38 seconds
Started Jul 22 04:53:19 PM PDT 24
Finished Jul 22 05:04:36 PM PDT 24
Peak memory 217784 kb
Host smart-3c1b2f9a-5798-4077-8429-0218f875db52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073307930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2073307930
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3312425426
Short name T267
Test name
Test status
Simulation time 23303415013 ps
CPU time 57.25 seconds
Started Jul 22 04:54:48 PM PDT 24
Finished Jul 22 04:55:46 PM PDT 24
Peak memory 219180 kb
Host smart-442593b2-3a24-46a0-a9ac-b3d76a07ec1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312425426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3312425426
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1137916500
Short name T230
Test name
Test status
Simulation time 13383362745 ps
CPU time 28.38 seconds
Started Jul 22 04:53:11 PM PDT 24
Finished Jul 22 04:53:40 PM PDT 24
Peak memory 211996 kb
Host smart-6b57e815-580f-45a5-9e60-e6906ccc3e9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1137916500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1137916500
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.561757404
Short name T314
Test name
Test status
Simulation time 362267966 ps
CPU time 19.59 seconds
Started Jul 22 04:53:12 PM PDT 24
Finished Jul 22 04:53:32 PM PDT 24
Peak memory 216312 kb
Host smart-1f71d294-c340-4464-8482-4be9dd74f337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561757404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.561757404
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.552926340
Short name T154
Test name
Test status
Simulation time 32579062716 ps
CPU time 95.19 seconds
Started Jul 22 04:53:10 PM PDT 24
Finished Jul 22 04:54:46 PM PDT 24
Peak memory 219268 kb
Host smart-46d03875-78b3-40c4-96bc-e2b47355d600
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552926340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.552926340
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1021011060
Short name T265
Test name
Test status
Simulation time 4194035215 ps
CPU time 31.39 seconds
Started Jul 22 04:55:04 PM PDT 24
Finished Jul 22 04:55:36 PM PDT 24
Peak memory 213268 kb
Host smart-f7cec6d8-1b27-4261-93de-6bf1713beafd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021011060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1021011060
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1088361215
Short name T171
Test name
Test status
Simulation time 87893448778 ps
CPU time 437.88 seconds
Started Jul 22 04:53:19 PM PDT 24
Finished Jul 22 05:00:37 PM PDT 24
Peak memory 219416 kb
Host smart-98da2826-df4c-4bf7-8722-ea72f00e1b3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088361215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1088361215
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2847638442
Short name T143
Test name
Test status
Simulation time 2493850599 ps
CPU time 27.06 seconds
Started Jul 22 04:53:22 PM PDT 24
Finished Jul 22 04:53:49 PM PDT 24
Peak memory 219340 kb
Host smart-4350fe60-75f6-4573-9cca-46625e67c773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847638442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2847638442
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.345266263
Short name T202
Test name
Test status
Simulation time 8316444725 ps
CPU time 23.26 seconds
Started Jul 22 04:53:20 PM PDT 24
Finished Jul 22 04:53:43 PM PDT 24
Peak memory 219600 kb
Host smart-037f36ed-357f-42e7-aa4a-619bb213d891
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=345266263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.345266263
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1145408820
Short name T335
Test name
Test status
Simulation time 675066535 ps
CPU time 19.7 seconds
Started Jul 22 04:53:20 PM PDT 24
Finished Jul 22 04:53:40 PM PDT 24
Peak memory 215936 kb
Host smart-b40ef0b3-2917-4455-ae4d-ec67e06cf628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145408820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1145408820
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.161101742
Short name T181
Test name
Test status
Simulation time 3743606680 ps
CPU time 55.56 seconds
Started Jul 22 04:54:48 PM PDT 24
Finished Jul 22 04:55:44 PM PDT 24
Peak memory 219316 kb
Host smart-530547dd-ae0d-4cf8-a9b9-9bf72d027bd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161101742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.161101742
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.790897615
Short name T355
Test name
Test status
Simulation time 4532768001 ps
CPU time 21.2 seconds
Started Jul 22 04:52:30 PM PDT 24
Finished Jul 22 04:52:52 PM PDT 24
Peak memory 217384 kb
Host smart-116a742e-333e-4823-9b26-3df19f3f2808
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790897615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.790897615
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2731450497
Short name T157
Test name
Test status
Simulation time 7165887309 ps
CPU time 62.35 seconds
Started Jul 22 04:52:35 PM PDT 24
Finished Jul 22 04:53:38 PM PDT 24
Peak memory 219268 kb
Host smart-fc469e0d-8a97-48a6-a736-b85aa6ae2870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731450497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2731450497
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2385110665
Short name T216
Test name
Test status
Simulation time 731955336 ps
CPU time 10.06 seconds
Started Jul 22 04:52:27 PM PDT 24
Finished Jul 22 04:52:38 PM PDT 24
Peak memory 219252 kb
Host smart-2a3618e1-6921-4609-879c-66b7564fa264
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2385110665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2385110665
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3942373129
Short name T29
Test name
Test status
Simulation time 15605210380 ps
CPU time 236.79 seconds
Started Jul 22 04:52:30 PM PDT 24
Finished Jul 22 04:56:27 PM PDT 24
Peak memory 238440 kb
Host smart-5587d293-a052-4e13-8e06-b2c22eb46d64
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942373129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3942373129
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3536368477
Short name T261
Test name
Test status
Simulation time 8053451670 ps
CPU time 46.92 seconds
Started Jul 22 04:52:26 PM PDT 24
Finished Jul 22 04:53:14 PM PDT 24
Peak memory 216108 kb
Host smart-528bb427-d3ae-484b-a08e-ebd264a95f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536368477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3536368477
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2688784035
Short name T328
Test name
Test status
Simulation time 52165316602 ps
CPU time 134.53 seconds
Started Jul 22 04:52:44 PM PDT 24
Finished Jul 22 04:55:00 PM PDT 24
Peak memory 221888 kb
Host smart-decf08af-64a4-4cbe-8523-436704d019fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688784035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2688784035
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1799590504
Short name T334
Test name
Test status
Simulation time 4649535150 ps
CPU time 23.25 seconds
Started Jul 22 04:53:20 PM PDT 24
Finished Jul 22 04:53:43 PM PDT 24
Peak memory 217396 kb
Host smart-1c0bc1f8-e503-4d9f-b2da-1cf86405aae0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799590504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1799590504
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1112002902
Short name T39
Test name
Test status
Simulation time 49963473027 ps
CPU time 284.21 seconds
Started Jul 22 04:53:19 PM PDT 24
Finished Jul 22 04:58:03 PM PDT 24
Peak memory 218948 kb
Host smart-4d14b427-6818-4823-83b7-20c313de47d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112002902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1112002902
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1942215168
Short name T228
Test name
Test status
Simulation time 342892884 ps
CPU time 18.77 seconds
Started Jul 22 04:53:21 PM PDT 24
Finished Jul 22 04:53:40 PM PDT 24
Peak memory 219196 kb
Host smart-2f7a59bb-fbee-4871-b007-015062eeaed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942215168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1942215168
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1679226256
Short name T325
Test name
Test status
Simulation time 742758051 ps
CPU time 14.42 seconds
Started Jul 22 04:53:19 PM PDT 24
Finished Jul 22 04:53:34 PM PDT 24
Peak memory 218496 kb
Host smart-5ffa4b5c-0c26-4088-9a3d-76240c9e9c31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1679226256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1679226256
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.110635504
Short name T74
Test name
Test status
Simulation time 2545607667 ps
CPU time 20.71 seconds
Started Jul 22 04:53:21 PM PDT 24
Finished Jul 22 04:53:42 PM PDT 24
Peak memory 218332 kb
Host smart-3e4df1de-8131-48bf-9e41-141bc0736e6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110635504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.110635504
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2686682204
Short name T233
Test name
Test status
Simulation time 2520391824 ps
CPU time 16.53 seconds
Started Jul 22 04:53:28 PM PDT 24
Finished Jul 22 04:53:45 PM PDT 24
Peak memory 213248 kb
Host smart-2caa1c33-d032-4730-943a-a9038c782263
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686682204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2686682204
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1529005922
Short name T292
Test name
Test status
Simulation time 38017450387 ps
CPU time 450.55 seconds
Started Jul 22 04:53:19 PM PDT 24
Finished Jul 22 05:00:50 PM PDT 24
Peak memory 234648 kb
Host smart-8baadd6a-15d3-46e5-b745-e539ec975c39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529005922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1529005922
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.189506720
Short name T337
Test name
Test status
Simulation time 2041178824 ps
CPU time 32.42 seconds
Started Jul 22 04:53:29 PM PDT 24
Finished Jul 22 04:54:02 PM PDT 24
Peak memory 218724 kb
Host smart-bdacd3f5-7629-415b-933e-db33b26d5c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189506720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.189506720
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.4187711765
Short name T332
Test name
Test status
Simulation time 4073124095 ps
CPU time 33.53 seconds
Started Jul 22 04:53:20 PM PDT 24
Finished Jul 22 04:53:54 PM PDT 24
Peak memory 211656 kb
Host smart-ed9f6de6-70b0-483e-bbc3-033da3c17561
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4187711765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.4187711765
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.1533807857
Short name T352
Test name
Test status
Simulation time 16877889248 ps
CPU time 58.81 seconds
Started Jul 22 04:53:23 PM PDT 24
Finished Jul 22 04:54:22 PM PDT 24
Peak memory 216404 kb
Host smart-21128f29-84d0-458b-a8d3-609e229cc16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533807857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.1533807857
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3513905835
Short name T194
Test name
Test status
Simulation time 13176768965 ps
CPU time 111.12 seconds
Started Jul 22 04:53:21 PM PDT 24
Finished Jul 22 04:55:12 PM PDT 24
Peak memory 219516 kb
Host smart-3e43b5f5-5397-4114-802d-aad766b9bdc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513905835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3513905835
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.4026191608
Short name T209
Test name
Test status
Simulation time 5658472610 ps
CPU time 26.26 seconds
Started Jul 22 04:53:29 PM PDT 24
Finished Jul 22 04:53:56 PM PDT 24
Peak memory 213308 kb
Host smart-9f04c01a-dea5-4765-a2d2-5a8c5401bd4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026191608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.4026191608
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3373518702
Short name T129
Test name
Test status
Simulation time 3080486747 ps
CPU time 164.43 seconds
Started Jul 22 04:53:31 PM PDT 24
Finished Jul 22 04:56:16 PM PDT 24
Peak memory 238692 kb
Host smart-91c490f0-4e8f-4f1e-9490-962fb522bffb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373518702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3373518702
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.4160877751
Short name T6
Test name
Test status
Simulation time 19540142466 ps
CPU time 50.9 seconds
Started Jul 22 04:53:29 PM PDT 24
Finished Jul 22 04:54:21 PM PDT 24
Peak memory 219300 kb
Host smart-7e57e864-5339-4ddd-9245-cca241a9f669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160877751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.4160877751
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.57417067
Short name T51
Test name
Test status
Simulation time 177589719 ps
CPU time 10.32 seconds
Started Jul 22 04:53:30 PM PDT 24
Finished Jul 22 04:53:40 PM PDT 24
Peak memory 219280 kb
Host smart-87fa82ac-ac64-4aa7-93a2-8e99f974ac8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=57417067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.57417067
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1623377450
Short name T303
Test name
Test status
Simulation time 1382425001 ps
CPU time 29.47 seconds
Started Jul 22 04:53:28 PM PDT 24
Finished Jul 22 04:53:58 PM PDT 24
Peak memory 219144 kb
Host smart-672931cb-c599-47d3-9e0b-cce591eb03f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623377450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1623377450
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2456764249
Short name T50
Test name
Test status
Simulation time 249407645424 ps
CPU time 2523.47 seconds
Started Jul 22 04:53:28 PM PDT 24
Finished Jul 22 05:35:33 PM PDT 24
Peak memory 244168 kb
Host smart-f7c5baf6-d1b6-46ff-860a-dbb48db1da69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456764249 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.2456764249
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2891135021
Short name T257
Test name
Test status
Simulation time 780385103 ps
CPU time 13.37 seconds
Started Jul 22 04:53:28 PM PDT 24
Finished Jul 22 04:53:42 PM PDT 24
Peak memory 217044 kb
Host smart-4378b253-e4c0-4058-84ea-1f6a56197c14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891135021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2891135021
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.837502712
Short name T192
Test name
Test status
Simulation time 15303164305 ps
CPU time 22.81 seconds
Started Jul 22 04:55:04 PM PDT 24
Finished Jul 22 04:55:28 PM PDT 24
Peak memory 219316 kb
Host smart-b1b7695b-284c-4d8e-a80c-3da6816dea30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=837502712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.837502712
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3269402551
Short name T294
Test name
Test status
Simulation time 6693665415 ps
CPU time 44.98 seconds
Started Jul 22 04:53:31 PM PDT 24
Finished Jul 22 04:54:16 PM PDT 24
Peak memory 216676 kb
Host smart-10a524d8-8f38-44c5-b93c-9bde89055553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269402551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3269402551
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2123592101
Short name T279
Test name
Test status
Simulation time 11873561761 ps
CPU time 176.46 seconds
Started Jul 22 04:53:55 PM PDT 24
Finished Jul 22 04:56:52 PM PDT 24
Peak memory 222232 kb
Host smart-4eba6024-68df-4837-90ce-0c834225e9dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123592101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2123592101
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1632684463
Short name T353
Test name
Test status
Simulation time 167370196 ps
CPU time 8.27 seconds
Started Jul 22 04:54:29 PM PDT 24
Finished Jul 22 04:54:38 PM PDT 24
Peak memory 217156 kb
Host smart-5f3d40bb-49ef-468b-baab-213b9d189589
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632684463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1632684463
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2947256645
Short name T213
Test name
Test status
Simulation time 124917017575 ps
CPU time 663.33 seconds
Started Jul 22 04:54:14 PM PDT 24
Finished Jul 22 05:05:17 PM PDT 24
Peak memory 225280 kb
Host smart-1a29959e-2f1c-4c14-84cb-1bb1f00bfa5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947256645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2947256645
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.182798278
Short name T308
Test name
Test status
Simulation time 7837416241 ps
CPU time 60.62 seconds
Started Jul 22 04:54:29 PM PDT 24
Finished Jul 22 04:55:30 PM PDT 24
Peak memory 219320 kb
Host smart-40dd3931-bf6c-47e0-afd5-d985dcf5b9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182798278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.182798278
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3768146379
Short name T243
Test name
Test status
Simulation time 16761810088 ps
CPU time 29.39 seconds
Started Jul 22 04:53:30 PM PDT 24
Finished Jul 22 04:54:00 PM PDT 24
Peak memory 217720 kb
Host smart-67e02e4c-6f6c-474d-88e8-6d9919709f4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3768146379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3768146379
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1813903218
Short name T311
Test name
Test status
Simulation time 738371972 ps
CPU time 19.59 seconds
Started Jul 22 04:53:28 PM PDT 24
Finished Jul 22 04:53:48 PM PDT 24
Peak memory 216768 kb
Host smart-4fbad30b-4084-4124-977b-19c90132c15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813903218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1813903218
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.4182441188
Short name T9
Test name
Test status
Simulation time 22992380108 ps
CPU time 87.86 seconds
Started Jul 22 04:53:31 PM PDT 24
Finished Jul 22 04:54:59 PM PDT 24
Peak memory 222972 kb
Host smart-8cb841bc-7cef-466b-b8de-630bb4d46c8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182441188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.4182441188
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3042962079
Short name T7
Test name
Test status
Simulation time 3727207579 ps
CPU time 31.37 seconds
Started Jul 22 04:53:39 PM PDT 24
Finished Jul 22 04:54:11 PM PDT 24
Peak memory 217244 kb
Host smart-f41be806-249a-4724-8c78-d9070b28d07d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042962079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3042962079
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.685918984
Short name T10
Test name
Test status
Simulation time 59905282754 ps
CPU time 298.11 seconds
Started Jul 22 04:54:15 PM PDT 24
Finished Jul 22 04:59:13 PM PDT 24
Peak memory 234004 kb
Host smart-3fb53b66-d1d9-495c-8eb8-a4027a3db12e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685918984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.685918984
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2403861484
Short name T274
Test name
Test status
Simulation time 6241172528 ps
CPU time 36.82 seconds
Started Jul 22 04:53:40 PM PDT 24
Finished Jul 22 04:54:17 PM PDT 24
Peak memory 219292 kb
Host smart-5399cb33-d473-49fe-9719-536dcb1b04b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403861484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2403861484
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3316139163
Short name T135
Test name
Test status
Simulation time 2557221306 ps
CPU time 24.6 seconds
Started Jul 22 04:53:39 PM PDT 24
Finished Jul 22 04:54:04 PM PDT 24
Peak memory 211296 kb
Host smart-c9cdfb6b-6ce2-4e23-b6e3-09141826d2e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3316139163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3316139163
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.422711964
Short name T318
Test name
Test status
Simulation time 30101083168 ps
CPU time 70.24 seconds
Started Jul 22 04:53:39 PM PDT 24
Finished Jul 22 04:54:50 PM PDT 24
Peak memory 215752 kb
Host smart-06e473f9-32e7-4a45-9e53-6cb4ded51e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422711964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.422711964
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3193742484
Short name T305
Test name
Test status
Simulation time 5622834769 ps
CPU time 34.76 seconds
Started Jul 22 04:53:40 PM PDT 24
Finished Jul 22 04:54:15 PM PDT 24
Peak memory 219460 kb
Host smart-552824c9-8b90-4878-bc7c-74b31ec27667
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193742484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3193742484
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.726158475
Short name T175
Test name
Test status
Simulation time 511236638 ps
CPU time 11.63 seconds
Started Jul 22 04:53:39 PM PDT 24
Finished Jul 22 04:53:51 PM PDT 24
Peak memory 218036 kb
Host smart-42dd5c43-e007-40f9-897c-b3bf09417249
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726158475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.726158475
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3379597326
Short name T255
Test name
Test status
Simulation time 10846892655 ps
CPU time 193.13 seconds
Started Jul 22 04:53:42 PM PDT 24
Finished Jul 22 04:56:56 PM PDT 24
Peak memory 239584 kb
Host smart-1f484d68-7775-49fc-b03c-bdcc5565b350
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379597326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3379597326
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1198620537
Short name T162
Test name
Test status
Simulation time 826421701 ps
CPU time 19.09 seconds
Started Jul 22 04:53:42 PM PDT 24
Finished Jul 22 04:54:01 PM PDT 24
Peak memory 219284 kb
Host smart-25d619e5-4e31-4196-91c3-bad7c6fe0272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198620537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1198620537
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3392051489
Short name T123
Test name
Test status
Simulation time 3590363177 ps
CPU time 29.35 seconds
Started Jul 22 04:53:41 PM PDT 24
Finished Jul 22 04:54:11 PM PDT 24
Peak memory 219372 kb
Host smart-b43b8cf5-033f-4cdd-b5a5-20feac1debb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3392051489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3392051489
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2517196706
Short name T340
Test name
Test status
Simulation time 734413080 ps
CPU time 20.17 seconds
Started Jul 22 04:53:44 PM PDT 24
Finished Jul 22 04:54:04 PM PDT 24
Peak memory 216324 kb
Host smart-74fcd8eb-756c-4975-9177-96b2be625cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517196706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2517196706
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1500831034
Short name T306
Test name
Test status
Simulation time 8415612227 ps
CPU time 81.12 seconds
Started Jul 22 04:53:39 PM PDT 24
Finished Jul 22 04:55:01 PM PDT 24
Peak memory 219356 kb
Host smart-aab564c0-725a-498c-8864-4f50521fa741
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500831034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1500831034
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.3947989658
Short name T46
Test name
Test status
Simulation time 102823619711 ps
CPU time 1134.13 seconds
Started Jul 22 04:53:39 PM PDT 24
Finished Jul 22 05:12:34 PM PDT 24
Peak memory 235780 kb
Host smart-dcc9c598-6eec-46a5-886b-3dd7afc7ad18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947989658 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.3947989658
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1650042776
Short name T125
Test name
Test status
Simulation time 3135315836 ps
CPU time 25.74 seconds
Started Jul 22 04:54:33 PM PDT 24
Finished Jul 22 04:54:59 PM PDT 24
Peak memory 213312 kb
Host smart-d7731903-0960-49a5-9976-3de7470ce33b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650042776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1650042776
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2802057784
Short name T208
Test name
Test status
Simulation time 64515692890 ps
CPU time 344.05 seconds
Started Jul 22 04:53:50 PM PDT 24
Finished Jul 22 04:59:35 PM PDT 24
Peak memory 236004 kb
Host smart-4a9f47f6-8bf3-43ed-99aa-c40cfb68ac2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802057784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2802057784
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2825640111
Short name T253
Test name
Test status
Simulation time 7988119945 ps
CPU time 67.52 seconds
Started Jul 22 04:53:49 PM PDT 24
Finished Jul 22 04:54:57 PM PDT 24
Peak memory 219308 kb
Host smart-54de2c7e-601e-4631-85ad-034c743c1b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825640111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2825640111
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.401258984
Short name T23
Test name
Test status
Simulation time 2799736037 ps
CPU time 25.79 seconds
Started Jul 22 04:53:52 PM PDT 24
Finished Jul 22 04:54:18 PM PDT 24
Peak memory 219292 kb
Host smart-e688fe8c-f845-4395-8a66-7a75a967fd03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=401258984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.401258984
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2340246710
Short name T300
Test name
Test status
Simulation time 28239852485 ps
CPU time 59.66 seconds
Started Jul 22 04:53:40 PM PDT 24
Finished Jul 22 04:54:40 PM PDT 24
Peak memory 217196 kb
Host smart-29941048-db04-4c11-a81f-8980dbe126d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340246710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2340246710
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3049422959
Short name T321
Test name
Test status
Simulation time 10001140374 ps
CPU time 45.33 seconds
Started Jul 22 04:55:09 PM PDT 24
Finished Jul 22 04:55:55 PM PDT 24
Peak memory 219272 kb
Host smart-f8c28b45-51a4-4cfe-b68f-ed704a457018
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049422959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3049422959
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.137487507
Short name T36
Test name
Test status
Simulation time 64045713435 ps
CPU time 256.58 seconds
Started Jul 22 04:55:21 PM PDT 24
Finished Jul 22 04:59:38 PM PDT 24
Peak memory 219496 kb
Host smart-0cd7f2a2-b3e8-4cd7-9229-08a6ae17e81d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137487507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.137487507
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1077285963
Short name T200
Test name
Test status
Simulation time 534433834 ps
CPU time 19.45 seconds
Started Jul 22 04:53:50 PM PDT 24
Finished Jul 22 04:54:10 PM PDT 24
Peak memory 219280 kb
Host smart-2381245f-3ad9-46e5-a538-368e53fde483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077285963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1077285963
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1226752379
Short name T273
Test name
Test status
Simulation time 2403232579 ps
CPU time 24.25 seconds
Started Jul 22 04:53:51 PM PDT 24
Finished Jul 22 04:54:15 PM PDT 24
Peak memory 219328 kb
Host smart-d45faddb-d393-48ae-9089-36557070bac6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1226752379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1226752379
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2355473998
Short name T1
Test name
Test status
Simulation time 1381722107 ps
CPU time 19.84 seconds
Started Jul 22 04:53:52 PM PDT 24
Finished Jul 22 04:54:12 PM PDT 24
Peak memory 216860 kb
Host smart-0faef518-462e-44b9-9232-55dcd240b3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355473998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2355473998
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3175373169
Short name T299
Test name
Test status
Simulation time 26842144899 ps
CPU time 59.38 seconds
Started Jul 22 04:54:11 PM PDT 24
Finished Jul 22 04:55:10 PM PDT 24
Peak memory 217912 kb
Host smart-397f99cc-1bda-47f1-a750-1747fa8bd803
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175373169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3175373169
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2057485344
Short name T201
Test name
Test status
Simulation time 6816588193 ps
CPU time 27.35 seconds
Started Jul 22 04:53:49 PM PDT 24
Finished Jul 22 04:54:17 PM PDT 24
Peak memory 213300 kb
Host smart-c09889e4-bd64-4b9b-824a-b2fb0102395b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057485344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2057485344
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.385102243
Short name T161
Test name
Test status
Simulation time 73035758876 ps
CPU time 918.1 seconds
Started Jul 22 04:53:54 PM PDT 24
Finished Jul 22 05:09:12 PM PDT 24
Peak memory 234888 kb
Host smart-536070a4-9c99-4c70-af2a-cd9760886237
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385102243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.385102243
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1166082326
Short name T13
Test name
Test status
Simulation time 8455542731 ps
CPU time 68.56 seconds
Started Jul 22 04:53:50 PM PDT 24
Finished Jul 22 04:54:59 PM PDT 24
Peak memory 219280 kb
Host smart-e33b4503-255c-4402-a93c-7819ac9461a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166082326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1166082326
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.530128400
Short name T177
Test name
Test status
Simulation time 13417003220 ps
CPU time 28.47 seconds
Started Jul 22 04:53:49 PM PDT 24
Finished Jul 22 04:54:17 PM PDT 24
Peak memory 211580 kb
Host smart-bb68d002-e597-401d-91dd-d1ad05ab2543
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=530128400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.530128400
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.383762231
Short name T165
Test name
Test status
Simulation time 5965269851 ps
CPU time 53.05 seconds
Started Jul 22 04:53:50 PM PDT 24
Finished Jul 22 04:54:43 PM PDT 24
Peak memory 216664 kb
Host smart-6ec15a38-6937-49d9-b18d-db56cda0dfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383762231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.383762231
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1330826059
Short name T348
Test name
Test status
Simulation time 12261533601 ps
CPU time 65.69 seconds
Started Jul 22 04:55:17 PM PDT 24
Finished Jul 22 04:56:24 PM PDT 24
Peak memory 217780 kb
Host smart-da17b11a-6d78-42fe-a40a-9d5656a34e52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330826059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1330826059
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3448866012
Short name T49
Test name
Test status
Simulation time 67648808021 ps
CPU time 2634.12 seconds
Started Jul 22 04:53:50 PM PDT 24
Finished Jul 22 05:37:45 PM PDT 24
Peak memory 248852 kb
Host smart-c0621373-7b6c-4536-b28d-d6fc278917a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448866012 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3448866012
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.892141520
Short name T260
Test name
Test status
Simulation time 3661886618 ps
CPU time 28.64 seconds
Started Jul 22 04:52:30 PM PDT 24
Finished Jul 22 04:52:59 PM PDT 24
Peak memory 217160 kb
Host smart-2a458aac-1186-42e7-88cb-8b9d621e4443
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892141520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.892141520
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3735143060
Short name T132
Test name
Test status
Simulation time 41149102775 ps
CPU time 572.53 seconds
Started Jul 22 04:52:35 PM PDT 24
Finished Jul 22 05:02:09 PM PDT 24
Peak memory 225388 kb
Host smart-6d2b5f61-e1e4-439b-a684-112c1c491bb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735143060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3735143060
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2496519537
Short name T183
Test name
Test status
Simulation time 3285247314 ps
CPU time 30.86 seconds
Started Jul 22 04:52:29 PM PDT 24
Finished Jul 22 04:53:00 PM PDT 24
Peak memory 219332 kb
Host smart-a7432d92-084f-45e6-bbed-ce9d988f125b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496519537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2496519537
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3461974936
Short name T94
Test name
Test status
Simulation time 727602844 ps
CPU time 10.6 seconds
Started Jul 22 04:52:27 PM PDT 24
Finished Jul 22 04:52:38 PM PDT 24
Peak memory 219296 kb
Host smart-52366bfa-b343-460c-9bc2-ef5007a59b8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3461974936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3461974936
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.127142304
Short name T24
Test name
Test status
Simulation time 831769182 ps
CPU time 119.52 seconds
Started Jul 22 04:52:25 PM PDT 24
Finished Jul 22 04:54:25 PM PDT 24
Peak memory 235612 kb
Host smart-91d7086e-efce-406b-99bd-8e5a0fb8dfae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127142304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.127142304
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2688907586
Short name T237
Test name
Test status
Simulation time 12168490185 ps
CPU time 62.79 seconds
Started Jul 22 04:52:44 PM PDT 24
Finished Jul 22 04:53:49 PM PDT 24
Peak memory 216880 kb
Host smart-fa438117-90b0-4152-b5dc-4f2a8f4dadaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688907586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2688907586
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3282413734
Short name T19
Test name
Test status
Simulation time 45561129575 ps
CPU time 102.29 seconds
Started Jul 22 04:55:33 PM PDT 24
Finished Jul 22 04:57:16 PM PDT 24
Peak memory 220368 kb
Host smart-30ab8f7d-15a1-45a0-bf7a-b6769d94a433
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282413734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3282413734
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.766148136
Short name T210
Test name
Test status
Simulation time 3064846425 ps
CPU time 26.04 seconds
Started Jul 22 04:55:21 PM PDT 24
Finished Jul 22 04:55:47 PM PDT 24
Peak memory 217248 kb
Host smart-366ddd12-f8ea-4c07-a294-eb844910eddd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766148136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.766148136
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.4024393451
Short name T215
Test name
Test status
Simulation time 355708269281 ps
CPU time 808.06 seconds
Started Jul 22 04:53:50 PM PDT 24
Finished Jul 22 05:07:19 PM PDT 24
Peak memory 218972 kb
Host smart-97b2dc46-8fdb-4989-ad02-f2e5327ff4ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024393451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.4024393451
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3887310046
Short name T322
Test name
Test status
Simulation time 15344699618 ps
CPU time 65.51 seconds
Started Jul 22 04:53:50 PM PDT 24
Finished Jul 22 04:54:56 PM PDT 24
Peak memory 219404 kb
Host smart-360940cd-5401-4e3c-8e56-c1617c9c3cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887310046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3887310046
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.953279783
Short name T32
Test name
Test status
Simulation time 9504289154 ps
CPU time 29.98 seconds
Started Jul 22 04:53:56 PM PDT 24
Finished Jul 22 04:54:26 PM PDT 24
Peak memory 211920 kb
Host smart-43a29147-bf5b-4c77-b4f4-c731ab84a4a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=953279783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.953279783
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1657898461
Short name T144
Test name
Test status
Simulation time 2205118982 ps
CPU time 33.24 seconds
Started Jul 22 04:53:50 PM PDT 24
Finished Jul 22 04:54:24 PM PDT 24
Peak memory 216556 kb
Host smart-13fa87a5-ec7d-47f5-86fd-4e101ed8de8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657898461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1657898461
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3371619571
Short name T329
Test name
Test status
Simulation time 32832081993 ps
CPU time 143.76 seconds
Started Jul 22 04:53:50 PM PDT 24
Finished Jul 22 04:56:14 PM PDT 24
Peak memory 219828 kb
Host smart-ce415606-8e6f-4a1a-916e-bba4a251cb0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371619571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3371619571
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.4175647425
Short name T185
Test name
Test status
Simulation time 2726892890 ps
CPU time 25.56 seconds
Started Jul 22 04:53:57 PM PDT 24
Finished Jul 22 04:54:23 PM PDT 24
Peak memory 213244 kb
Host smart-43d6d72a-a0c4-46c3-9b16-4622c050d1be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175647425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.4175647425
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.898230366
Short name T238
Test name
Test status
Simulation time 32428535024 ps
CPU time 318.17 seconds
Started Jul 22 04:55:32 PM PDT 24
Finished Jul 22 05:00:50 PM PDT 24
Peak memory 238864 kb
Host smart-509347de-de83-4af3-abb5-4364d162b225
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898230366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.898230366
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1088015126
Short name T197
Test name
Test status
Simulation time 23858933710 ps
CPU time 54.16 seconds
Started Jul 22 04:54:00 PM PDT 24
Finished Jul 22 04:54:54 PM PDT 24
Peak memory 219196 kb
Host smart-024f0ddb-c8cf-4ce5-ae76-4fe281d9a926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088015126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1088015126
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2609892493
Short name T110
Test name
Test status
Simulation time 49471891871 ps
CPU time 28.6 seconds
Started Jul 22 04:55:18 PM PDT 24
Finished Jul 22 04:55:47 PM PDT 24
Peak memory 219280 kb
Host smart-827a0004-2eca-419e-8a63-83bde3d78753
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2609892493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2609892493
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.513813286
Short name T156
Test name
Test status
Simulation time 31537222476 ps
CPU time 70.91 seconds
Started Jul 22 04:53:55 PM PDT 24
Finished Jul 22 04:55:06 PM PDT 24
Peak memory 216316 kb
Host smart-f104ecd1-92d3-4afd-ab46-46a083b940e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513813286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.513813286
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2238146787
Short name T231
Test name
Test status
Simulation time 44885323335 ps
CPU time 69.05 seconds
Started Jul 22 04:53:50 PM PDT 24
Finished Jul 22 04:55:00 PM PDT 24
Peak memory 217896 kb
Host smart-475967ef-d088-4783-b779-4dae3bdcc490
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238146787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2238146787
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1010601986
Short name T251
Test name
Test status
Simulation time 4152773092 ps
CPU time 33.18 seconds
Started Jul 22 04:53:57 PM PDT 24
Finished Jul 22 04:54:30 PM PDT 24
Peak memory 213272 kb
Host smart-e6bb2ef2-734d-4dab-8a1d-2d42d8f5414a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010601986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1010601986
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2025235977
Short name T206
Test name
Test status
Simulation time 142371467084 ps
CPU time 368.03 seconds
Started Jul 22 04:53:59 PM PDT 24
Finished Jul 22 05:00:07 PM PDT 24
Peak memory 236692 kb
Host smart-e61dfa22-bd12-46c0-a7be-b068b9545c66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025235977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2025235977
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2183312854
Short name T266
Test name
Test status
Simulation time 22339443994 ps
CPU time 52.22 seconds
Started Jul 22 04:55:18 PM PDT 24
Finished Jul 22 04:56:11 PM PDT 24
Peak memory 219224 kb
Host smart-f0db7ebf-99e5-4620-a26e-0a73460f2808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183312854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2183312854
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2981646661
Short name T163
Test name
Test status
Simulation time 5953096484 ps
CPU time 19.61 seconds
Started Jul 22 04:54:01 PM PDT 24
Finished Jul 22 04:54:21 PM PDT 24
Peak memory 219372 kb
Host smart-6ad6e3cb-3fde-4983-9a11-1a3f94e8c818
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2981646661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2981646661
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1987644359
Short name T235
Test name
Test status
Simulation time 5143263390 ps
CPU time 54.02 seconds
Started Jul 22 04:55:09 PM PDT 24
Finished Jul 22 04:56:03 PM PDT 24
Peak memory 216108 kb
Host smart-91df6a93-4afa-44b4-8250-2fd68edab946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987644359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1987644359
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1602102441
Short name T155
Test name
Test status
Simulation time 1778779215 ps
CPU time 14.74 seconds
Started Jul 22 04:54:01 PM PDT 24
Finished Jul 22 04:54:16 PM PDT 24
Peak memory 219336 kb
Host smart-a6612368-a77b-4379-ac61-5d7a8416e979
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602102441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1602102441
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3719860754
Short name T310
Test name
Test status
Simulation time 1532234511 ps
CPU time 13.48 seconds
Started Jul 22 04:56:13 PM PDT 24
Finished Jul 22 04:56:28 PM PDT 24
Peak memory 217228 kb
Host smart-57dd5b92-1edb-445f-93f6-597eb00cd861
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719860754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3719860754
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3321727854
Short name T252
Test name
Test status
Simulation time 408745497165 ps
CPU time 851.01 seconds
Started Jul 22 04:53:59 PM PDT 24
Finished Jul 22 05:08:10 PM PDT 24
Peak memory 217692 kb
Host smart-be07af4b-63e5-4bc9-96d2-80056f8a299d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321727854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3321727854
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3231217322
Short name T287
Test name
Test status
Simulation time 1376065053 ps
CPU time 18.5 seconds
Started Jul 22 04:55:18 PM PDT 24
Finished Jul 22 04:55:37 PM PDT 24
Peak memory 219164 kb
Host smart-f0435c36-542b-45db-b488-78c17e1e2329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231217322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3231217322
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1515647994
Short name T122
Test name
Test status
Simulation time 187780374 ps
CPU time 9.98 seconds
Started Jul 22 04:56:13 PM PDT 24
Finished Jul 22 04:56:24 PM PDT 24
Peak memory 219312 kb
Host smart-24b0743b-b216-419c-bd81-766b1bde00b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1515647994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1515647994
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.437007158
Short name T288
Test name
Test status
Simulation time 13007097494 ps
CPU time 39.02 seconds
Started Jul 22 04:53:58 PM PDT 24
Finished Jul 22 04:54:37 PM PDT 24
Peak memory 216616 kb
Host smart-b088f345-d7cc-4257-ad71-60b9dd9e1032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437007158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.437007158
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.266052935
Short name T250
Test name
Test status
Simulation time 4005299362 ps
CPU time 34.77 seconds
Started Jul 22 04:53:58 PM PDT 24
Finished Jul 22 04:54:33 PM PDT 24
Peak memory 214656 kb
Host smart-e19b97b0-9fab-494f-a143-4e74e288dd47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266052935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.266052935
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3085910269
Short name T168
Test name
Test status
Simulation time 3296060950 ps
CPU time 27.38 seconds
Started Jul 22 04:54:11 PM PDT 24
Finished Jul 22 04:54:39 PM PDT 24
Peak memory 217108 kb
Host smart-963772ab-597d-420b-a397-c715e421c2ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085910269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3085910269
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2718855012
Short name T218
Test name
Test status
Simulation time 306604957654 ps
CPU time 604.76 seconds
Started Jul 22 04:53:59 PM PDT 24
Finished Jul 22 05:04:04 PM PDT 24
Peak memory 235752 kb
Host smart-3bb42d31-602f-49f1-939a-b1e4b8a2ee67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718855012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2718855012
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1522796607
Short name T248
Test name
Test status
Simulation time 41075806112 ps
CPU time 59.1 seconds
Started Jul 22 04:53:57 PM PDT 24
Finished Jul 22 04:54:57 PM PDT 24
Peak memory 219356 kb
Host smart-181cb896-0bbb-423e-afc1-318430849237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522796607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1522796607
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3776010770
Short name T345
Test name
Test status
Simulation time 14036686892 ps
CPU time 31.08 seconds
Started Jul 22 04:55:18 PM PDT 24
Finished Jul 22 04:55:50 PM PDT 24
Peak memory 211844 kb
Host smart-85f528da-b9ec-459e-b8f8-473b59822f39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3776010770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3776010770
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1456569964
Short name T20
Test name
Test status
Simulation time 6640544346 ps
CPU time 55.15 seconds
Started Jul 22 04:55:31 PM PDT 24
Finished Jul 22 04:56:27 PM PDT 24
Peak memory 216460 kb
Host smart-63975a92-74b4-40ea-977b-efbf5e7470cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456569964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1456569964
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2922484165
Short name T174
Test name
Test status
Simulation time 7690039619 ps
CPU time 87.46 seconds
Started Jul 22 04:53:59 PM PDT 24
Finished Jul 22 04:55:26 PM PDT 24
Peak memory 219308 kb
Host smart-6a2e2056-b652-4216-8636-71cffb967c7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922484165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2922484165
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.547088463
Short name T285
Test name
Test status
Simulation time 30445652932 ps
CPU time 27.88 seconds
Started Jul 22 04:54:09 PM PDT 24
Finished Jul 22 04:54:37 PM PDT 24
Peak memory 217452 kb
Host smart-f179e6ba-6e16-46b5-8284-b688335dbbbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547088463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.547088463
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3706206180
Short name T262
Test name
Test status
Simulation time 61629562791 ps
CPU time 552.13 seconds
Started Jul 22 04:55:02 PM PDT 24
Finished Jul 22 05:04:15 PM PDT 24
Peak memory 219496 kb
Host smart-8462d9d8-b646-49d0-a86c-df144fc783fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706206180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3706206180
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.937089663
Short name T131
Test name
Test status
Simulation time 12292938379 ps
CPU time 36.89 seconds
Started Jul 22 04:54:33 PM PDT 24
Finished Jul 22 04:55:10 PM PDT 24
Peak memory 221244 kb
Host smart-b13baf06-6ae7-45ab-847b-4780362e42e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937089663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.937089663
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.225684431
Short name T111
Test name
Test status
Simulation time 1734125095 ps
CPU time 20.09 seconds
Started Jul 22 04:54:07 PM PDT 24
Finished Jul 22 04:54:27 PM PDT 24
Peak memory 219216 kb
Host smart-62649913-8477-4f6f-b067-dbf7715d1e1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=225684431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.225684431
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2249109157
Short name T346
Test name
Test status
Simulation time 43408504342 ps
CPU time 53.2 seconds
Started Jul 22 04:54:10 PM PDT 24
Finished Jul 22 04:55:03 PM PDT 24
Peak memory 216984 kb
Host smart-6c446344-c215-469e-a388-da042b7fb550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249109157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2249109157
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.4038878045
Short name T326
Test name
Test status
Simulation time 66515569472 ps
CPU time 59.74 seconds
Started Jul 22 04:54:07 PM PDT 24
Finished Jul 22 04:55:07 PM PDT 24
Peak memory 219356 kb
Host smart-ba593bbf-f969-4dd2-86b0-e248015034a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038878045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.4038878045
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.34723818
Short name T47
Test name
Test status
Simulation time 28985293125 ps
CPU time 955.63 seconds
Started Jul 22 04:54:08 PM PDT 24
Finished Jul 22 05:10:04 PM PDT 24
Peak memory 235848 kb
Host smart-2845a467-d491-48ac-bb0e-773ec1a51fac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34723818 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.34723818
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3929180341
Short name T219
Test name
Test status
Simulation time 1796080401 ps
CPU time 19.4 seconds
Started Jul 22 04:54:07 PM PDT 24
Finished Jul 22 04:54:26 PM PDT 24
Peak memory 213188 kb
Host smart-a6537e84-ce17-4df3-aed1-84921c05b3fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929180341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3929180341
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1226710808
Short name T268
Test name
Test status
Simulation time 27601831458 ps
CPU time 195.45 seconds
Started Jul 22 04:54:06 PM PDT 24
Finished Jul 22 04:57:22 PM PDT 24
Peak memory 240280 kb
Host smart-a016c0a1-1224-4d8b-bf13-84187122125c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226710808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1226710808
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2951719068
Short name T180
Test name
Test status
Simulation time 3153061437 ps
CPU time 30.56 seconds
Started Jul 22 04:54:06 PM PDT 24
Finished Jul 22 04:54:37 PM PDT 24
Peak memory 219312 kb
Host smart-8a8a1dc5-f28d-436f-8d97-0f61d9814015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951719068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2951719068
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2936728470
Short name T127
Test name
Test status
Simulation time 440776102 ps
CPU time 13.02 seconds
Started Jul 22 04:54:07 PM PDT 24
Finished Jul 22 04:54:21 PM PDT 24
Peak memory 218456 kb
Host smart-f064a375-6306-41c5-b748-1edf08abf6c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2936728470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2936728470
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3859248234
Short name T75
Test name
Test status
Simulation time 4342203277 ps
CPU time 28 seconds
Started Jul 22 04:54:11 PM PDT 24
Finished Jul 22 04:54:40 PM PDT 24
Peak memory 216380 kb
Host smart-b0b1aee8-3b7c-4047-a3c7-059840054af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859248234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3859248234
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.29025141
Short name T293
Test name
Test status
Simulation time 20667720370 ps
CPU time 195.77 seconds
Started Jul 22 04:54:08 PM PDT 24
Finished Jul 22 04:57:24 PM PDT 24
Peak memory 220088 kb
Host smart-a46e2171-f9df-41b5-8303-7c6fb327acac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29025141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 36.rom_ctrl_stress_all.29025141
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.979665757
Short name T324
Test name
Test status
Simulation time 44094120105 ps
CPU time 21.62 seconds
Started Jul 22 04:54:08 PM PDT 24
Finished Jul 22 04:54:30 PM PDT 24
Peak memory 217376 kb
Host smart-5f13bfe3-7e25-49cb-bd57-66fda84c2dc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979665757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.979665757
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3303625955
Short name T167
Test name
Test status
Simulation time 6196982702 ps
CPU time 234.08 seconds
Started Jul 22 04:54:07 PM PDT 24
Finished Jul 22 04:58:01 PM PDT 24
Peak memory 239300 kb
Host smart-858e549e-4252-4eb6-9270-48ebafff172f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303625955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3303625955
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1013800152
Short name T184
Test name
Test status
Simulation time 38288479297 ps
CPU time 34.34 seconds
Started Jul 22 04:54:07 PM PDT 24
Finished Jul 22 04:54:42 PM PDT 24
Peak memory 219280 kb
Host smart-935dee4b-164e-4d11-adac-26648770930b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013800152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1013800152
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1250174147
Short name T358
Test name
Test status
Simulation time 2464672221 ps
CPU time 25.04 seconds
Started Jul 22 04:54:08 PM PDT 24
Finished Jul 22 04:54:33 PM PDT 24
Peak memory 219372 kb
Host smart-1966ab3d-e8de-4b87-9374-cb8f2dbd2f38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1250174147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1250174147
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1435319101
Short name T301
Test name
Test status
Simulation time 2127698969 ps
CPU time 22.95 seconds
Started Jul 22 04:54:08 PM PDT 24
Finished Jul 22 04:54:31 PM PDT 24
Peak memory 216364 kb
Host smart-42eb83d0-bd8b-4daf-b3c9-f8b6c957d431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435319101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1435319101
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3783494532
Short name T116
Test name
Test status
Simulation time 8629840517 ps
CPU time 52.14 seconds
Started Jul 22 04:56:13 PM PDT 24
Finished Jul 22 04:57:06 PM PDT 24
Peak memory 218868 kb
Host smart-debfe8e6-4b45-4fe5-a1ef-e94447e7d1d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783494532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3783494532
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2189329589
Short name T282
Test name
Test status
Simulation time 4012398970 ps
CPU time 20.59 seconds
Started Jul 22 04:54:36 PM PDT 24
Finished Jul 22 04:54:57 PM PDT 24
Peak memory 213300 kb
Host smart-b98779d9-656d-4e7e-a22d-0d7f1e2a7189
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189329589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2189329589
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1336740168
Short name T211
Test name
Test status
Simulation time 202459586303 ps
CPU time 503.69 seconds
Started Jul 22 04:55:09 PM PDT 24
Finished Jul 22 05:03:33 PM PDT 24
Peak memory 215692 kb
Host smart-3d6bac43-3142-44c6-8035-8cf2c16f89cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336740168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1336740168
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.4160295417
Short name T2
Test name
Test status
Simulation time 12251589969 ps
CPU time 54.92 seconds
Started Jul 22 04:54:16 PM PDT 24
Finished Jul 22 04:55:11 PM PDT 24
Peak memory 215556 kb
Host smart-fd718330-7e91-47d8-a4fe-693b453c1c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160295417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.4160295417
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.4160371457
Short name T278
Test name
Test status
Simulation time 1686211026 ps
CPU time 15.58 seconds
Started Jul 22 04:54:14 PM PDT 24
Finished Jul 22 04:54:30 PM PDT 24
Peak memory 219256 kb
Host smart-cb240042-8139-4706-a604-ed1dcd496b50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4160371457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.4160371457
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.1268081346
Short name T290
Test name
Test status
Simulation time 340606915 ps
CPU time 20.72 seconds
Started Jul 22 04:54:06 PM PDT 24
Finished Jul 22 04:54:28 PM PDT 24
Peak memory 216104 kb
Host smart-c8ef2449-94dd-4d99-952e-2156a2570e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268081346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1268081346
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1350650448
Short name T239
Test name
Test status
Simulation time 10389316402 ps
CPU time 36.14 seconds
Started Jul 22 04:56:15 PM PDT 24
Finished Jul 22 04:56:51 PM PDT 24
Peak memory 212388 kb
Host smart-b20e1095-9634-4e06-bbe0-76393b476263
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350650448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1350650448
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1541724086
Short name T317
Test name
Test status
Simulation time 170944838 ps
CPU time 8.48 seconds
Started Jul 22 04:54:18 PM PDT 24
Finished Jul 22 04:54:27 PM PDT 24
Peak memory 217260 kb
Host smart-38aa7503-14ae-4b98-8c89-820615a456e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541724086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1541724086
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2093967009
Short name T145
Test name
Test status
Simulation time 188824235304 ps
CPU time 947.29 seconds
Started Jul 22 04:54:18 PM PDT 24
Finished Jul 22 05:10:06 PM PDT 24
Peak memory 218036 kb
Host smart-e1f3e35a-efab-4253-946c-89ece2e27065
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093967009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2093967009
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1750107441
Short name T259
Test name
Test status
Simulation time 24506616043 ps
CPU time 64.61 seconds
Started Jul 22 04:54:15 PM PDT 24
Finished Jul 22 04:55:20 PM PDT 24
Peak memory 219340 kb
Host smart-bce979c2-c06e-45ee-9542-d4bba49d56c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750107441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1750107441
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2227362359
Short name T272
Test name
Test status
Simulation time 747361715 ps
CPU time 10.14 seconds
Started Jul 22 04:54:17 PM PDT 24
Finished Jul 22 04:54:28 PM PDT 24
Peak memory 219288 kb
Host smart-6459165e-12bc-4866-8e57-db55a3c6839d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2227362359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2227362359
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.4053771667
Short name T52
Test name
Test status
Simulation time 9364163625 ps
CPU time 64.4 seconds
Started Jul 22 04:54:16 PM PDT 24
Finished Jul 22 04:55:21 PM PDT 24
Peak memory 216920 kb
Host smart-4c9e2e15-72b2-471b-8a2c-dded8d780749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053771667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.4053771667
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1663313196
Short name T212
Test name
Test status
Simulation time 29389162344 ps
CPU time 74.45 seconds
Started Jul 22 04:54:16 PM PDT 24
Finished Jul 22 04:55:31 PM PDT 24
Peak memory 219304 kb
Host smart-588c84ae-c22f-4955-aeb8-26d57fc081e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663313196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1663313196
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.1497621247
Short name T48
Test name
Test status
Simulation time 30039511345 ps
CPU time 1200.3 seconds
Started Jul 22 04:54:15 PM PDT 24
Finished Jul 22 05:14:16 PM PDT 24
Peak memory 236216 kb
Host smart-2c800bc3-d9a6-4bf0-8020-632fbf705c59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497621247 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.1497621247
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.134145643
Short name T121
Test name
Test status
Simulation time 3904812373 ps
CPU time 30.46 seconds
Started Jul 22 04:55:33 PM PDT 24
Finished Jul 22 04:56:04 PM PDT 24
Peak memory 217096 kb
Host smart-8feeb535-1776-4663-b8ca-ff929e3df329
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134145643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.134145643
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1691370501
Short name T45
Test name
Test status
Simulation time 10840728807 ps
CPU time 220.95 seconds
Started Jul 22 04:52:35 PM PDT 24
Finished Jul 22 04:56:16 PM PDT 24
Peak memory 237840 kb
Host smart-a59df78c-bf6d-4cc4-ba4f-55fac5e792b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691370501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1691370501
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2143892349
Short name T258
Test name
Test status
Simulation time 7839903738 ps
CPU time 63.47 seconds
Started Jul 22 04:52:31 PM PDT 24
Finished Jul 22 04:53:35 PM PDT 24
Peak memory 219084 kb
Host smart-326f3091-16db-4ddc-8b87-128a77c4d27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143892349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2143892349
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1793112520
Short name T331
Test name
Test status
Simulation time 15351055830 ps
CPU time 30.02 seconds
Started Jul 22 04:55:33 PM PDT 24
Finished Jul 22 04:56:04 PM PDT 24
Peak memory 219276 kb
Host smart-b94398f3-098d-4dad-bcce-cf4eedc04fb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1793112520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1793112520
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1307739179
Short name T304
Test name
Test status
Simulation time 2519262682 ps
CPU time 37.15 seconds
Started Jul 22 04:52:27 PM PDT 24
Finished Jul 22 04:53:05 PM PDT 24
Peak memory 216756 kb
Host smart-27526061-049b-4b24-90bd-163bfd2394b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307739179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1307739179
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3363877620
Short name T256
Test name
Test status
Simulation time 4410697959 ps
CPU time 26.66 seconds
Started Jul 22 04:52:35 PM PDT 24
Finished Jul 22 04:53:02 PM PDT 24
Peak memory 211668 kb
Host smart-c28b6bb0-af3c-4f7f-920b-0358aedf600a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363877620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3363877620
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3015381757
Short name T188
Test name
Test status
Simulation time 2292662839 ps
CPU time 22.16 seconds
Started Jul 22 04:54:24 PM PDT 24
Finished Jul 22 04:54:47 PM PDT 24
Peak memory 217184 kb
Host smart-48d6b579-15ac-401c-869b-f0859f7f66d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015381757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3015381757
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3718668878
Short name T286
Test name
Test status
Simulation time 5884468917 ps
CPU time 275.61 seconds
Started Jul 22 04:54:14 PM PDT 24
Finished Jul 22 04:58:51 PM PDT 24
Peak memory 236764 kb
Host smart-7fbacdfb-672c-462b-be02-28740e01871c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718668878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3718668878
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3517592779
Short name T226
Test name
Test status
Simulation time 1164782448 ps
CPU time 27.61 seconds
Started Jul 22 04:54:24 PM PDT 24
Finished Jul 22 04:54:52 PM PDT 24
Peak memory 219256 kb
Host smart-61a445bc-c491-4d23-8f51-c2bb912612f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517592779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3517592779
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2254075473
Short name T316
Test name
Test status
Simulation time 3804338000 ps
CPU time 16.03 seconds
Started Jul 22 04:54:17 PM PDT 24
Finished Jul 22 04:54:33 PM PDT 24
Peak memory 219340 kb
Host smart-8d2d596b-9635-42de-b694-7d7766bdd5a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2254075473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2254075473
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3759585139
Short name T203
Test name
Test status
Simulation time 10948811772 ps
CPU time 48.61 seconds
Started Jul 22 04:54:15 PM PDT 24
Finished Jul 22 04:55:04 PM PDT 24
Peak memory 217008 kb
Host smart-ade5835f-89d9-46a4-8a5e-21149a7acc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759585139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3759585139
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2199537009
Short name T73
Test name
Test status
Simulation time 913890963 ps
CPU time 51.03 seconds
Started Jul 22 04:54:14 PM PDT 24
Finished Jul 22 04:55:06 PM PDT 24
Peak memory 227412 kb
Host smart-377a0ca5-381a-479a-89e7-933ac9b23cbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199537009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2199537009
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1679780931
Short name T59
Test name
Test status
Simulation time 525863653 ps
CPU time 11.97 seconds
Started Jul 22 04:54:25 PM PDT 24
Finished Jul 22 04:54:38 PM PDT 24
Peak memory 213264 kb
Host smart-cbec652d-86a1-47b7-909b-b0db3bf2b31f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679780931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1679780931
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3993893869
Short name T271
Test name
Test status
Simulation time 821918111762 ps
CPU time 609.73 seconds
Started Jul 22 04:54:25 PM PDT 24
Finished Jul 22 05:04:35 PM PDT 24
Peak memory 225552 kb
Host smart-e13c8c4c-f058-4217-b376-ed8af6cb7dcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993893869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3993893869
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3425061211
Short name T249
Test name
Test status
Simulation time 14358549640 ps
CPU time 41.36 seconds
Started Jul 22 04:54:27 PM PDT 24
Finished Jul 22 04:55:09 PM PDT 24
Peak memory 219176 kb
Host smart-4f5b3c21-0660-4e20-a2bd-31bd518c3398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425061211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3425061211
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.188267919
Short name T338
Test name
Test status
Simulation time 36600253253 ps
CPU time 25.08 seconds
Started Jul 22 04:55:29 PM PDT 24
Finished Jul 22 04:55:55 PM PDT 24
Peak memory 211680 kb
Host smart-9be093a4-96c4-4b72-9238-540bec90ba85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=188267919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.188267919
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1660367301
Short name T118
Test name
Test status
Simulation time 370856997 ps
CPU time 20.11 seconds
Started Jul 22 04:54:26 PM PDT 24
Finished Jul 22 04:54:47 PM PDT 24
Peak memory 216748 kb
Host smart-949ade1c-b852-4064-94d7-da05a39ef1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660367301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1660367301
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2603794411
Short name T5
Test name
Test status
Simulation time 25607319788 ps
CPU time 79.3 seconds
Started Jul 22 04:54:27 PM PDT 24
Finished Jul 22 04:55:47 PM PDT 24
Peak memory 219328 kb
Host smart-c6f0593b-a415-4ca3-bf44-3427bc8a8123
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603794411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2603794411
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3133997301
Short name T138
Test name
Test status
Simulation time 1649743114 ps
CPU time 11.48 seconds
Started Jul 22 04:54:26 PM PDT 24
Finished Jul 22 04:54:38 PM PDT 24
Peak memory 217080 kb
Host smart-d7b557ff-c1e2-41f1-8f95-089ed0b885bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133997301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3133997301
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3013974458
Short name T141
Test name
Test status
Simulation time 3471172711 ps
CPU time 243.59 seconds
Started Jul 22 04:54:48 PM PDT 24
Finished Jul 22 04:58:53 PM PDT 24
Peak memory 238764 kb
Host smart-2ba0619e-37b7-4741-80c7-4b26c8300224
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013974458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3013974458
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3139593676
Short name T297
Test name
Test status
Simulation time 8186350783 ps
CPU time 65.33 seconds
Started Jul 22 04:54:26 PM PDT 24
Finished Jul 22 04:55:31 PM PDT 24
Peak memory 219352 kb
Host smart-3eb405a5-e4a2-446a-a32f-f0e51a5766a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139593676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3139593676
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3694969124
Short name T30
Test name
Test status
Simulation time 8533103191 ps
CPU time 33.69 seconds
Started Jul 22 04:55:04 PM PDT 24
Finished Jul 22 04:55:38 PM PDT 24
Peak memory 219356 kb
Host smart-a799dccb-48a8-4b18-8290-e87fa730596a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3694969124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3694969124
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.4284196404
Short name T53
Test name
Test status
Simulation time 5612940887 ps
CPU time 40.78 seconds
Started Jul 22 04:54:25 PM PDT 24
Finished Jul 22 04:55:06 PM PDT 24
Peak memory 216324 kb
Host smart-4df9fd93-8e09-424c-ad78-819fff78e6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284196404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.4284196404
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.880132619
Short name T289
Test name
Test status
Simulation time 20516929303 ps
CPU time 199.23 seconds
Started Jul 22 04:54:26 PM PDT 24
Finished Jul 22 04:57:45 PM PDT 24
Peak memory 222836 kb
Host smart-1c13a0c4-84d8-4d5e-b847-3582e13eb6d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880132619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.880132619
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.589850162
Short name T140
Test name
Test status
Simulation time 2185242333 ps
CPU time 15.13 seconds
Started Jul 22 04:55:04 PM PDT 24
Finished Jul 22 04:55:19 PM PDT 24
Peak memory 217112 kb
Host smart-3649e07c-3e42-4dbe-83cf-778589553384
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589850162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.589850162
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.273366655
Short name T38
Test name
Test status
Simulation time 5504706393 ps
CPU time 376.45 seconds
Started Jul 22 04:54:25 PM PDT 24
Finished Jul 22 05:00:41 PM PDT 24
Peak memory 238000 kb
Host smart-63c352f6-bdec-4411-95f3-70815d4c833a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273366655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.273366655
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.894592498
Short name T124
Test name
Test status
Simulation time 6447916401 ps
CPU time 54.43 seconds
Started Jul 22 04:54:51 PM PDT 24
Finished Jul 22 04:55:46 PM PDT 24
Peak memory 219316 kb
Host smart-551c0f7d-287e-44f7-9678-cdcf782fbdef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894592498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.894592498
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.4033400653
Short name T224
Test name
Test status
Simulation time 16808252475 ps
CPU time 33.29 seconds
Started Jul 22 04:55:32 PM PDT 24
Finished Jul 22 04:56:05 PM PDT 24
Peak memory 219288 kb
Host smart-86ebb736-04f2-40b5-9250-c0dadf383e07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4033400653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.4033400653
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.4116572680
Short name T307
Test name
Test status
Simulation time 17762901970 ps
CPU time 48.49 seconds
Started Jul 22 04:54:25 PM PDT 24
Finished Jul 22 04:55:14 PM PDT 24
Peak memory 216760 kb
Host smart-888d55cd-2c5d-4871-9675-7b327d0b1f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116572680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.4116572680
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3714175792
Short name T214
Test name
Test status
Simulation time 797534116 ps
CPU time 17.77 seconds
Started Jul 22 04:54:25 PM PDT 24
Finished Jul 22 04:54:43 PM PDT 24
Peak memory 219272 kb
Host smart-87ceaa31-d8f0-490d-921e-bef97b041223
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714175792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3714175792
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2486784180
Short name T320
Test name
Test status
Simulation time 339078396 ps
CPU time 8.42 seconds
Started Jul 22 04:55:31 PM PDT 24
Finished Jul 22 04:55:40 PM PDT 24
Peak memory 216548 kb
Host smart-064270eb-4e71-444f-8c57-aac740e62753
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486784180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2486784180
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1380155291
Short name T225
Test name
Test status
Simulation time 10875341837 ps
CPU time 315.92 seconds
Started Jul 22 04:54:33 PM PDT 24
Finished Jul 22 04:59:49 PM PDT 24
Peak memory 237360 kb
Host smart-93bbc0e3-5bb5-44cf-b125-faa6acf5be2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380155291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1380155291
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1100090044
Short name T309
Test name
Test status
Simulation time 5269413128 ps
CPU time 28.23 seconds
Started Jul 22 04:54:33 PM PDT 24
Finished Jul 22 04:55:02 PM PDT 24
Peak memory 218820 kb
Host smart-0d506fd3-2d5d-4495-b7a2-8b3bf925408b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100090044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1100090044
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1176329731
Short name T95
Test name
Test status
Simulation time 3865510900 ps
CPU time 31.47 seconds
Started Jul 22 04:54:46 PM PDT 24
Finished Jul 22 04:55:18 PM PDT 24
Peak memory 219336 kb
Host smart-a3549713-f238-486d-a0ca-c13f4c547809
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1176329731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1176329731
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3978891363
Short name T176
Test name
Test status
Simulation time 4119974026 ps
CPU time 36.79 seconds
Started Jul 22 04:54:33 PM PDT 24
Finished Jul 22 04:55:11 PM PDT 24
Peak memory 216712 kb
Host smart-ec4e1bcc-b51d-4519-ad9b-3dd09934225c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978891363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3978891363
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.736902081
Short name T137
Test name
Test status
Simulation time 1319506280 ps
CPU time 39.63 seconds
Started Jul 22 04:54:34 PM PDT 24
Finished Jul 22 04:55:14 PM PDT 24
Peak memory 219260 kb
Host smart-f852834e-8204-4434-9f9c-e829533f745e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736902081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.736902081
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2872509115
Short name T8
Test name
Test status
Simulation time 55731833721 ps
CPU time 30.91 seconds
Started Jul 22 04:54:36 PM PDT 24
Finished Jul 22 04:55:07 PM PDT 24
Peak memory 217464 kb
Host smart-18018ca5-4439-4178-aad5-f9f10a6d29cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872509115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2872509115
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1396680206
Short name T341
Test name
Test status
Simulation time 134354975504 ps
CPU time 420.43 seconds
Started Jul 22 04:54:35 PM PDT 24
Finished Jul 22 05:01:35 PM PDT 24
Peak memory 242092 kb
Host smart-41131acc-8d58-412c-a531-5dfe87b178e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396680206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1396680206
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.607458158
Short name T354
Test name
Test status
Simulation time 9855667290 ps
CPU time 46.83 seconds
Started Jul 22 04:55:31 PM PDT 24
Finished Jul 22 04:56:18 PM PDT 24
Peak memory 219304 kb
Host smart-5aad8a4c-74c4-46ff-8935-18854740a66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607458158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.607458158
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3518722903
Short name T109
Test name
Test status
Simulation time 7096803553 ps
CPU time 28.63 seconds
Started Jul 22 04:54:34 PM PDT 24
Finished Jul 22 04:55:03 PM PDT 24
Peak memory 219316 kb
Host smart-0c67da08-38d0-4894-91da-ae4e2b987a6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3518722903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3518722903
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2348420604
Short name T133
Test name
Test status
Simulation time 2148699445 ps
CPU time 33.49 seconds
Started Jul 22 04:54:39 PM PDT 24
Finished Jul 22 04:55:13 PM PDT 24
Peak memory 216576 kb
Host smart-057fa583-2219-4cdb-ac96-837d755350e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348420604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2348420604
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2396233529
Short name T151
Test name
Test status
Simulation time 1660487287 ps
CPU time 24.03 seconds
Started Jul 22 04:54:35 PM PDT 24
Finished Jul 22 04:54:59 PM PDT 24
Peak memory 219264 kb
Host smart-92944ce2-11fc-472a-8077-5003f2c768e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396233529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2396233529
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.945865939
Short name T336
Test name
Test status
Simulation time 3669370219 ps
CPU time 31.99 seconds
Started Jul 22 04:54:36 PM PDT 24
Finished Jul 22 04:55:08 PM PDT 24
Peak memory 217184 kb
Host smart-e33f84ec-25a4-4ddd-93fc-16f285d97984
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945865939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.945865939
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2595939151
Short name T35
Test name
Test status
Simulation time 84856421541 ps
CPU time 807.42 seconds
Started Jul 22 04:54:36 PM PDT 24
Finished Jul 22 05:08:03 PM PDT 24
Peak memory 237952 kb
Host smart-16a421c4-90ee-48f5-b6e0-fae28b4f6afe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595939151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2595939151
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.216313312
Short name T134
Test name
Test status
Simulation time 19969748779 ps
CPU time 38.22 seconds
Started Jul 22 04:54:36 PM PDT 24
Finished Jul 22 04:55:14 PM PDT 24
Peak memory 219376 kb
Host smart-afbf3752-d7b0-4a1c-bcee-cfca4e5d4f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216313312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.216313312
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.216992785
Short name T119
Test name
Test status
Simulation time 23089698629 ps
CPU time 17.49 seconds
Started Jul 22 04:54:33 PM PDT 24
Finished Jul 22 04:54:51 PM PDT 24
Peak memory 211964 kb
Host smart-dcbbea5f-1491-4c96-9837-9741a1e237b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=216992785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.216992785
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3717094598
Short name T115
Test name
Test status
Simulation time 7474581170 ps
CPU time 61.14 seconds
Started Jul 22 04:54:35 PM PDT 24
Finished Jul 22 04:55:37 PM PDT 24
Peak memory 216740 kb
Host smart-45fecada-bea9-4d31-ab0c-775c07ca52cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717094598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3717094598
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3526269877
Short name T276
Test name
Test status
Simulation time 31147989047 ps
CPU time 76.97 seconds
Started Jul 22 04:54:35 PM PDT 24
Finished Jul 22 04:55:53 PM PDT 24
Peak memory 219284 kb
Host smart-68f8d6d2-1286-4006-8604-a756d5ffb7aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526269877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3526269877
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1529479391
Short name T160
Test name
Test status
Simulation time 3748993099 ps
CPU time 20.57 seconds
Started Jul 22 04:54:58 PM PDT 24
Finished Jul 22 04:55:19 PM PDT 24
Peak memory 213264 kb
Host smart-6afb46ed-6376-4152-943c-edc887342520
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529479391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1529479391
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.654556187
Short name T343
Test name
Test status
Simulation time 195196719115 ps
CPU time 468.05 seconds
Started Jul 22 04:54:44 PM PDT 24
Finished Jul 22 05:02:33 PM PDT 24
Peak memory 217084 kb
Host smart-1ff5f113-e8b4-4e36-9c9b-41d399731e5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654556187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.654556187
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2723366429
Short name T152
Test name
Test status
Simulation time 350457351 ps
CPU time 18.78 seconds
Started Jul 22 04:54:44 PM PDT 24
Finished Jul 22 04:55:03 PM PDT 24
Peak memory 219312 kb
Host smart-46579ef9-bb31-4e01-85a8-0ac2a5916ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723366429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2723366429
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2721710456
Short name T227
Test name
Test status
Simulation time 6666176618 ps
CPU time 29.45 seconds
Started Jul 22 04:54:44 PM PDT 24
Finished Jul 22 04:55:14 PM PDT 24
Peak memory 212000 kb
Host smart-3256f81a-5eef-4a58-a218-3296efcea1f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2721710456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2721710456
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3108421000
Short name T245
Test name
Test status
Simulation time 1432974336 ps
CPU time 19.72 seconds
Started Jul 22 04:54:35 PM PDT 24
Finished Jul 22 04:54:55 PM PDT 24
Peak memory 216576 kb
Host smart-9eed2783-adb2-4e30-8fe8-afc8dffcf2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108421000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3108421000
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3729541607
Short name T246
Test name
Test status
Simulation time 22003097438 ps
CPU time 102.68 seconds
Started Jul 22 04:55:29 PM PDT 24
Finished Jul 22 04:57:13 PM PDT 24
Peak memory 216952 kb
Host smart-eb0f0ed2-4338-44c3-8616-71d0999cd480
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729541607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3729541607
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.2742741484
Short name T17
Test name
Test status
Simulation time 152513817808 ps
CPU time 2839.93 seconds
Started Jul 22 04:54:44 PM PDT 24
Finished Jul 22 05:42:05 PM PDT 24
Peak memory 249276 kb
Host smart-571db5f9-e885-466b-b2a7-d2ff987acabf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742741484 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.2742741484
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.550892881
Short name T114
Test name
Test status
Simulation time 21728107394 ps
CPU time 25.87 seconds
Started Jul 22 04:54:43 PM PDT 24
Finished Jul 22 04:55:09 PM PDT 24
Peak memory 217480 kb
Host smart-f5ca584b-b9c0-4a5e-be22-7c5fe60791b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550892881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.550892881
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1453699247
Short name T240
Test name
Test status
Simulation time 32686549467 ps
CPU time 447.59 seconds
Started Jul 22 04:54:43 PM PDT 24
Finished Jul 22 05:02:11 PM PDT 24
Peak memory 226060 kb
Host smart-605a62f4-a3f0-492b-ae88-8adf29a61e8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453699247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1453699247
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2202773897
Short name T179
Test name
Test status
Simulation time 2010765699 ps
CPU time 32.29 seconds
Started Jul 22 04:55:29 PM PDT 24
Finished Jul 22 04:56:03 PM PDT 24
Peak memory 219280 kb
Host smart-edc76e7a-c0ff-4660-a543-c5184793004d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202773897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2202773897
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1873640706
Short name T275
Test name
Test status
Simulation time 205047621 ps
CPU time 11 seconds
Started Jul 22 04:55:09 PM PDT 24
Finished Jul 22 04:55:20 PM PDT 24
Peak memory 219248 kb
Host smart-ad1312bf-38cd-485d-9909-49a098d88a87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1873640706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1873640706
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.369623257
Short name T198
Test name
Test status
Simulation time 23297347112 ps
CPU time 57.31 seconds
Started Jul 22 04:55:29 PM PDT 24
Finished Jul 22 04:56:27 PM PDT 24
Peak memory 218468 kb
Host smart-71d6b466-3209-4dfa-aebe-4584655e3a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369623257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.369623257
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2130560647
Short name T136
Test name
Test status
Simulation time 18732454399 ps
CPU time 30.86 seconds
Started Jul 22 04:54:44 PM PDT 24
Finished Jul 22 04:55:15 PM PDT 24
Peak memory 214636 kb
Host smart-609e615c-b8c9-481e-8c7a-b17c98206472
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130560647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2130560647
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1846238699
Short name T263
Test name
Test status
Simulation time 2530435032 ps
CPU time 22.97 seconds
Started Jul 22 04:54:50 PM PDT 24
Finished Jul 22 04:55:14 PM PDT 24
Peak memory 217192 kb
Host smart-22c22caa-5f07-4b29-a72c-4a4740ccb18c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846238699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1846238699
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1536213827
Short name T182
Test name
Test status
Simulation time 287743195596 ps
CPU time 449.87 seconds
Started Jul 22 04:54:51 PM PDT 24
Finished Jul 22 05:02:21 PM PDT 24
Peak memory 225384 kb
Host smart-8403c28d-d9cd-46cc-8294-bcb7b778d2e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536213827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1536213827
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2257706858
Short name T41
Test name
Test status
Simulation time 1831451829 ps
CPU time 18.67 seconds
Started Jul 22 04:56:12 PM PDT 24
Finished Jul 22 04:56:31 PM PDT 24
Peak memory 219212 kb
Host smart-a37b4db3-c13e-458b-a127-8842c43c576d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257706858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2257706858
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1671622774
Short name T339
Test name
Test status
Simulation time 264948510 ps
CPU time 12.12 seconds
Started Jul 22 04:56:12 PM PDT 24
Finished Jul 22 04:56:24 PM PDT 24
Peak memory 219240 kb
Host smart-6c87563f-9cf9-4f25-894f-c772212f07e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1671622774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1671622774
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.942837248
Short name T12
Test name
Test status
Simulation time 362678969 ps
CPU time 19.66 seconds
Started Jul 22 04:54:44 PM PDT 24
Finished Jul 22 04:55:04 PM PDT 24
Peak memory 216236 kb
Host smart-13fa4ac9-e7e8-4735-9113-94f81b732c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942837248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.942837248
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.51737286
Short name T193
Test name
Test status
Simulation time 9804071723 ps
CPU time 107.87 seconds
Started Jul 22 04:54:42 PM PDT 24
Finished Jul 22 04:56:30 PM PDT 24
Peak memory 219292 kb
Host smart-a6b27332-d87c-4e09-9421-37a82cec917a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51737286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 49.rom_ctrl_stress_all.51737286
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.127464846
Short name T27
Test name
Test status
Simulation time 1826293300 ps
CPU time 11.96 seconds
Started Jul 22 04:52:33 PM PDT 24
Finished Jul 22 04:52:46 PM PDT 24
Peak memory 213148 kb
Host smart-39d04399-8038-4fe3-bcb3-0f6545f45ccd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127464846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.127464846
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3405617333
Short name T43
Test name
Test status
Simulation time 136621625312 ps
CPU time 750.68 seconds
Started Jul 22 04:52:35 PM PDT 24
Finished Jul 22 05:05:06 PM PDT 24
Peak memory 234956 kb
Host smart-dc790a7c-51f9-4f82-b9f8-bf4fc7ea9870
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405617333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3405617333
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3515587045
Short name T189
Test name
Test status
Simulation time 1499336651 ps
CPU time 18.68 seconds
Started Jul 22 04:53:53 PM PDT 24
Finished Jul 22 04:54:12 PM PDT 24
Peak memory 219228 kb
Host smart-b83e4839-d43d-4a24-9250-51ff4af5ec40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515587045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3515587045
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.618014062
Short name T295
Test name
Test status
Simulation time 4134930987 ps
CPU time 22.57 seconds
Started Jul 22 04:52:44 PM PDT 24
Finished Jul 22 04:53:08 PM PDT 24
Peak memory 211668 kb
Host smart-84329fff-49d3-4212-ad45-a102ffdf9432
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=618014062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.618014062
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3142597214
Short name T351
Test name
Test status
Simulation time 1432855333 ps
CPU time 19.38 seconds
Started Jul 22 04:52:30 PM PDT 24
Finished Jul 22 04:52:50 PM PDT 24
Peak memory 215740 kb
Host smart-547a90b6-ff2a-4e76-bf54-5b53d32b1d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142597214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3142597214
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.4244097606
Short name T139
Test name
Test status
Simulation time 38381558596 ps
CPU time 84.87 seconds
Started Jul 22 04:52:26 PM PDT 24
Finished Jul 22 04:53:52 PM PDT 24
Peak memory 219324 kb
Host smart-f7d3156f-9d2a-4514-a516-9db0f32397f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244097606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.4244097606
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2776177842
Short name T205
Test name
Test status
Simulation time 238182575 ps
CPU time 8.26 seconds
Started Jul 22 04:52:34 PM PDT 24
Finished Jul 22 04:52:43 PM PDT 24
Peak memory 217020 kb
Host smart-5d87ab5c-6f8d-4ea8-bbb5-008665ab1f15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776177842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2776177842
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2826905466
Short name T126
Test name
Test status
Simulation time 168690466369 ps
CPU time 413.49 seconds
Started Jul 22 04:52:37 PM PDT 24
Finished Jul 22 04:59:31 PM PDT 24
Peak memory 237940 kb
Host smart-d6e751ae-60dd-4a90-ac38-b6ff297d8381
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826905466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2826905466
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3998467071
Short name T178
Test name
Test status
Simulation time 6847928844 ps
CPU time 58.66 seconds
Started Jul 22 04:54:28 PM PDT 24
Finished Jul 22 04:55:27 PM PDT 24
Peak memory 219116 kb
Host smart-fcee7e58-36bd-4999-9a09-369f109ec159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998467071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3998467071
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2022878915
Short name T128
Test name
Test status
Simulation time 8775495954 ps
CPU time 35.05 seconds
Started Jul 22 04:52:34 PM PDT 24
Finished Jul 22 04:53:09 PM PDT 24
Peak memory 219320 kb
Host smart-8a7db0ef-84bd-48f1-956b-916adb76533d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2022878915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2022878915
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1614852229
Short name T241
Test name
Test status
Simulation time 22513951590 ps
CPU time 56.34 seconds
Started Jul 22 04:52:34 PM PDT 24
Finished Jul 22 04:53:31 PM PDT 24
Peak memory 217104 kb
Host smart-65899fc9-6bcb-4f47-a621-dc18c7a5905a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614852229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1614852229
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2507885866
Short name T302
Test name
Test status
Simulation time 24281833605 ps
CPU time 123.39 seconds
Started Jul 22 04:52:34 PM PDT 24
Finished Jul 22 04:54:38 PM PDT 24
Peak memory 220048 kb
Host smart-a2bfe822-fc98-4af0-881c-8479fde522d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507885866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2507885866
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.4205722201
Short name T16
Test name
Test status
Simulation time 124725355158 ps
CPU time 937.3 seconds
Started Jul 22 04:52:33 PM PDT 24
Finished Jul 22 05:08:11 PM PDT 24
Peak memory 235792 kb
Host smart-559aa505-7497-4c29-aefb-73744aa87323
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205722201 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.4205722201
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.897138953
Short name T113
Test name
Test status
Simulation time 717628022 ps
CPU time 8.45 seconds
Started Jul 22 04:52:36 PM PDT 24
Finished Jul 22 04:52:45 PM PDT 24
Peak memory 213244 kb
Host smart-f637e2c8-5546-4f99-bd12-956871aab03e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897138953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.897138953
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.4164736808
Short name T350
Test name
Test status
Simulation time 4097727349 ps
CPU time 243.26 seconds
Started Jul 22 04:52:36 PM PDT 24
Finished Jul 22 04:56:39 PM PDT 24
Peak memory 224428 kb
Host smart-bd555205-57b0-47d1-baa7-9f18ecd726a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164736808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.4164736808
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1029447485
Short name T172
Test name
Test status
Simulation time 7638608821 ps
CPU time 41.77 seconds
Started Jul 22 04:52:36 PM PDT 24
Finished Jul 22 04:53:18 PM PDT 24
Peak memory 219200 kb
Host smart-25663ef4-ef67-450d-b129-afb898b80ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029447485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1029447485
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.406218649
Short name T254
Test name
Test status
Simulation time 6693539989 ps
CPU time 21.93 seconds
Started Jul 22 04:52:37 PM PDT 24
Finished Jul 22 04:53:00 PM PDT 24
Peak memory 217824 kb
Host smart-26375228-639c-40bb-83fb-cc57b49e21fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=406218649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.406218649
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1149281616
Short name T187
Test name
Test status
Simulation time 6617587439 ps
CPU time 64.65 seconds
Started Jul 22 04:52:33 PM PDT 24
Finished Jul 22 04:53:39 PM PDT 24
Peak memory 216860 kb
Host smart-1ca0ff69-3687-4cc8-8fe0-50f96b93149b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149281616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1149281616
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1816790384
Short name T76
Test name
Test status
Simulation time 411704848 ps
CPU time 14.41 seconds
Started Jul 22 04:52:33 PM PDT 24
Finished Jul 22 04:52:49 PM PDT 24
Peak memory 219268 kb
Host smart-842babcc-4e2b-4e2c-bb4b-a9d98e31c6bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816790384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1816790384
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.4039283840
Short name T169
Test name
Test status
Simulation time 7898682023 ps
CPU time 20.65 seconds
Started Jul 22 04:52:42 PM PDT 24
Finished Jul 22 04:53:03 PM PDT 24
Peak memory 213520 kb
Host smart-064bb8fa-f782-4e18-9116-e228b0019c53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039283840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.4039283840
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2421293245
Short name T357
Test name
Test status
Simulation time 3307910454 ps
CPU time 230.01 seconds
Started Jul 22 04:52:35 PM PDT 24
Finished Jul 22 04:56:26 PM PDT 24
Peak memory 235744 kb
Host smart-1978415b-4ec6-46e2-a968-c8d045ca6c2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421293245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2421293245
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2122552520
Short name T244
Test name
Test status
Simulation time 22952725862 ps
CPU time 54.76 seconds
Started Jul 22 04:52:33 PM PDT 24
Finished Jul 22 04:53:29 PM PDT 24
Peak memory 219316 kb
Host smart-1865d87d-0a89-4ca1-a087-2e873d0ac0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122552520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2122552520
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3523289960
Short name T356
Test name
Test status
Simulation time 342130105 ps
CPU time 12.51 seconds
Started Jul 22 04:52:34 PM PDT 24
Finished Jul 22 04:52:47 PM PDT 24
Peak memory 211056 kb
Host smart-97bd2393-0a3c-4e2b-b15a-f6c4216dddc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3523289960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3523289960
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3168425797
Short name T313
Test name
Test status
Simulation time 370620130 ps
CPU time 20.41 seconds
Started Jul 22 04:52:34 PM PDT 24
Finished Jul 22 04:52:55 PM PDT 24
Peak memory 216444 kb
Host smart-3e6214c3-db09-4efa-ab20-512665361409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168425797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3168425797
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1169371061
Short name T158
Test name
Test status
Simulation time 36738672608 ps
CPU time 127.79 seconds
Started Jul 22 04:52:35 PM PDT 24
Finished Jul 22 04:54:44 PM PDT 24
Peak memory 220264 kb
Host smart-0f8098df-f506-4df6-bcb1-ba084c3cd025
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169371061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1169371061
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.897623397
Short name T14
Test name
Test status
Simulation time 21060132376 ps
CPU time 778.08 seconds
Started Jul 22 04:52:43 PM PDT 24
Finished Jul 22 05:05:42 PM PDT 24
Peak memory 235816 kb
Host smart-de0ceb48-f000-47a0-8a03-d7c52cb8b106
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897623397 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.897623397
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3052874764
Short name T190
Test name
Test status
Simulation time 612435649 ps
CPU time 8.12 seconds
Started Jul 22 04:52:42 PM PDT 24
Finished Jul 22 04:52:51 PM PDT 24
Peak memory 217040 kb
Host smart-6e702620-c9d0-440a-af56-348a732cbf2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052874764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3052874764
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3042192353
Short name T236
Test name
Test status
Simulation time 16049819652 ps
CPU time 196.57 seconds
Started Jul 22 04:52:42 PM PDT 24
Finished Jul 22 04:56:00 PM PDT 24
Peak memory 228844 kb
Host smart-5d87bb6a-b368-4a08-a817-1cdb0dcb8ec8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042192353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3042192353
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2015941248
Short name T40
Test name
Test status
Simulation time 15699590174 ps
CPU time 65.59 seconds
Started Jul 22 04:52:45 PM PDT 24
Finished Jul 22 04:53:52 PM PDT 24
Peak memory 219180 kb
Host smart-f780e102-4a3f-465a-a2bc-188b482cf417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015941248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2015941248
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1064930560
Short name T199
Test name
Test status
Simulation time 177823023 ps
CPU time 10.03 seconds
Started Jul 22 04:52:43 PM PDT 24
Finished Jul 22 04:52:55 PM PDT 24
Peak memory 219284 kb
Host smart-c4f4a6de-2f53-4e6d-8b49-a63ee89f46bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1064930560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1064930560
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3054457090
Short name T173
Test name
Test status
Simulation time 4080195605 ps
CPU time 41.06 seconds
Started Jul 22 04:52:43 PM PDT 24
Finished Jul 22 04:53:26 PM PDT 24
Peak memory 216396 kb
Host smart-79827535-4f58-49fa-a22a-f0ce278bb320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054457090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3054457090
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.424990774
Short name T298
Test name
Test status
Simulation time 15293726167 ps
CPU time 156.29 seconds
Started Jul 22 04:52:41 PM PDT 24
Finished Jul 22 04:55:18 PM PDT 24
Peak memory 220976 kb
Host smart-e6036c4a-f75d-4f38-bc47-f71fa1bd6207
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424990774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.424990774
Directory /workspace/9.rom_ctrl_stress_all/latest
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